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mbed 2

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TARGET_NUCLEO_L011K4/core_cm7.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:39:34 2018 +0100
Revision:
170:e95d10626187
Parent:
169:a7c7b631e539 
mbed library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**************************************************************************//**
AnnaBridge 157:e7ca05fa8600 2 * @file core_cm7.h
AnnaBridge 157:e7ca05fa8600 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.5
Anna Bridge 169:a7c7b631e539 5 * @date 08. January 2018
AnnaBridge 157:e7ca05fa8600 6 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 7 /*
AnnaBridge 157:e7ca05fa8600 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 157:e7ca05fa8600 9 *
AnnaBridge 157:e7ca05fa8600 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 157:e7ca05fa8600 11 *
AnnaBridge 157:e7ca05fa8600 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 157:e7ca05fa8600 13 * not use this file except in compliance with the License.
AnnaBridge 157:e7ca05fa8600 14 * You may obtain a copy of the License at
AnnaBridge 157:e7ca05fa8600 15 *
AnnaBridge 157:e7ca05fa8600 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 157:e7ca05fa8600 17 *
AnnaBridge 157:e7ca05fa8600 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 157:e7ca05fa8600 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 157:e7ca05fa8600 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 157:e7ca05fa8600 21 * See the License for the specific language governing permissions and
AnnaBridge 157:e7ca05fa8600 22 * limitations under the License.
AnnaBridge 157:e7ca05fa8600 23 */
AnnaBridge 157:e7ca05fa8600 24
AnnaBridge 157:e7ca05fa8600 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
AnnaBridge 157:e7ca05fa8600 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 157:e7ca05fa8600 29 #endif
AnnaBridge 157:e7ca05fa8600 30
AnnaBridge 157:e7ca05fa8600 31 #ifndef __CORE_CM7_H_GENERIC
AnnaBridge 157:e7ca05fa8600 32 #define __CORE_CM7_H_GENERIC
AnnaBridge 157:e7ca05fa8600 33
AnnaBridge 157:e7ca05fa8600 34 #include <stdint.h>
AnnaBridge 157:e7ca05fa8600 35
AnnaBridge 157:e7ca05fa8600 36 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 37 extern "C" {
AnnaBridge 157:e7ca05fa8600 38 #endif
AnnaBridge 157:e7ca05fa8600 39
AnnaBridge 157:e7ca05fa8600 40 /**
AnnaBridge 157:e7ca05fa8600 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 157:e7ca05fa8600 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 157:e7ca05fa8600 43
AnnaBridge 157:e7ca05fa8600 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 157:e7ca05fa8600 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 157:e7ca05fa8600 46
AnnaBridge 157:e7ca05fa8600 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 157:e7ca05fa8600 48 Unions are used for effective representation of core registers.
AnnaBridge 157:e7ca05fa8600 49
AnnaBridge 157:e7ca05fa8600 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 157:e7ca05fa8600 51 Function-like macros are used to allow more efficient code.
AnnaBridge 157:e7ca05fa8600 52 */
AnnaBridge 157:e7ca05fa8600 53
AnnaBridge 157:e7ca05fa8600 54
AnnaBridge 157:e7ca05fa8600 55 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 56 * CMSIS definitions
AnnaBridge 157:e7ca05fa8600 57 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 58 /**
AnnaBridge 157:e7ca05fa8600 59 \ingroup Cortex_M7
AnnaBridge 157:e7ca05fa8600 60 @{
AnnaBridge 157:e7ca05fa8600 61 */
AnnaBridge 157:e7ca05fa8600 62
Anna Bridge 160:5571c4ff569f 63 #include "cmsis_version.h"
Anna Bridge 160:5571c4ff569f 64
AnnaBridge 157:e7ca05fa8600 65 /* CMSIS CM7 definitions */
Anna Bridge 160:5571c4ff569f 66 #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 160:5571c4ff569f 67 #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 157:e7ca05fa8600 68 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 160:5571c4ff569f 69 __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 157:e7ca05fa8600 70
AnnaBridge 157:e7ca05fa8600 71 #define __CORTEX_M (7U) /*!< Cortex-M Core */
AnnaBridge 157:e7ca05fa8600 72
AnnaBridge 157:e7ca05fa8600 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 157:e7ca05fa8600 74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge 157:e7ca05fa8600 75 */
AnnaBridge 157:e7ca05fa8600 76 #if defined ( __CC_ARM )
AnnaBridge 157:e7ca05fa8600 77 #if defined __TARGET_FPU_VFP
AnnaBridge 157:e7ca05fa8600 78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 79 #define __FPU_USED 1U
AnnaBridge 157:e7ca05fa8600 80 #else
AnnaBridge 157:e7ca05fa8600 81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 82 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 83 #endif
AnnaBridge 157:e7ca05fa8600 84 #else
AnnaBridge 157:e7ca05fa8600 85 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 86 #endif
AnnaBridge 157:e7ca05fa8600 87
AnnaBridge 157:e7ca05fa8600 88 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 157:e7ca05fa8600 89 #if defined __ARM_PCS_VFP
AnnaBridge 157:e7ca05fa8600 90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 91 #define __FPU_USED 1U
AnnaBridge 157:e7ca05fa8600 92 #else
AnnaBridge 157:e7ca05fa8600 93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 94 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 95 #endif
AnnaBridge 157:e7ca05fa8600 96 #else
AnnaBridge 157:e7ca05fa8600 97 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 98 #endif
AnnaBridge 157:e7ca05fa8600 99
AnnaBridge 157:e7ca05fa8600 100 #elif defined ( __GNUC__ )
AnnaBridge 157:e7ca05fa8600 101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 157:e7ca05fa8600 102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 103 #define __FPU_USED 1U
AnnaBridge 157:e7ca05fa8600 104 #else
AnnaBridge 157:e7ca05fa8600 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 106 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 107 #endif
AnnaBridge 157:e7ca05fa8600 108 #else
AnnaBridge 157:e7ca05fa8600 109 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 110 #endif
AnnaBridge 157:e7ca05fa8600 111
AnnaBridge 157:e7ca05fa8600 112 #elif defined ( __ICCARM__ )
AnnaBridge 157:e7ca05fa8600 113 #if defined __ARMVFP__
AnnaBridge 157:e7ca05fa8600 114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 115 #define __FPU_USED 1U
AnnaBridge 157:e7ca05fa8600 116 #else
AnnaBridge 157:e7ca05fa8600 117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 118 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 119 #endif
AnnaBridge 157:e7ca05fa8600 120 #else
AnnaBridge 157:e7ca05fa8600 121 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 122 #endif
AnnaBridge 157:e7ca05fa8600 123
AnnaBridge 157:e7ca05fa8600 124 #elif defined ( __TI_ARM__ )
AnnaBridge 157:e7ca05fa8600 125 #if defined __TI_VFP_SUPPORT__
AnnaBridge 157:e7ca05fa8600 126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 127 #define __FPU_USED 1U
AnnaBridge 157:e7ca05fa8600 128 #else
AnnaBridge 157:e7ca05fa8600 129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 130 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 131 #endif
AnnaBridge 157:e7ca05fa8600 132 #else
AnnaBridge 157:e7ca05fa8600 133 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 134 #endif
AnnaBridge 157:e7ca05fa8600 135
AnnaBridge 157:e7ca05fa8600 136 #elif defined ( __TASKING__ )
AnnaBridge 157:e7ca05fa8600 137 #if defined __FPU_VFP__
AnnaBridge 157:e7ca05fa8600 138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 139 #define __FPU_USED 1U
AnnaBridge 157:e7ca05fa8600 140 #else
AnnaBridge 157:e7ca05fa8600 141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 142 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 143 #endif
AnnaBridge 157:e7ca05fa8600 144 #else
AnnaBridge 157:e7ca05fa8600 145 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 146 #endif
AnnaBridge 157:e7ca05fa8600 147
AnnaBridge 157:e7ca05fa8600 148 #elif defined ( __CSMC__ )
AnnaBridge 157:e7ca05fa8600 149 #if ( __CSMC__ & 0x400U)
AnnaBridge 157:e7ca05fa8600 150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 151 #define __FPU_USED 1U
AnnaBridge 157:e7ca05fa8600 152 #else
AnnaBridge 157:e7ca05fa8600 153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 154 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 155 #endif
AnnaBridge 157:e7ca05fa8600 156 #else
AnnaBridge 157:e7ca05fa8600 157 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 158 #endif
AnnaBridge 157:e7ca05fa8600 159
AnnaBridge 157:e7ca05fa8600 160 #endif
AnnaBridge 157:e7ca05fa8600 161
AnnaBridge 157:e7ca05fa8600 162 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 157:e7ca05fa8600 163
AnnaBridge 157:e7ca05fa8600 164
AnnaBridge 157:e7ca05fa8600 165 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 166 }
AnnaBridge 157:e7ca05fa8600 167 #endif
AnnaBridge 157:e7ca05fa8600 168
AnnaBridge 157:e7ca05fa8600 169 #endif /* __CORE_CM7_H_GENERIC */
AnnaBridge 157:e7ca05fa8600 170
AnnaBridge 157:e7ca05fa8600 171 #ifndef __CMSIS_GENERIC
AnnaBridge 157:e7ca05fa8600 172
AnnaBridge 157:e7ca05fa8600 173 #ifndef __CORE_CM7_H_DEPENDANT
AnnaBridge 157:e7ca05fa8600 174 #define __CORE_CM7_H_DEPENDANT
AnnaBridge 157:e7ca05fa8600 175
AnnaBridge 157:e7ca05fa8600 176 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 177 extern "C" {
AnnaBridge 157:e7ca05fa8600 178 #endif
AnnaBridge 157:e7ca05fa8600 179
AnnaBridge 157:e7ca05fa8600 180 /* check device defines and use defaults */
AnnaBridge 157:e7ca05fa8600 181 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 157:e7ca05fa8600 182 #ifndef __CM7_REV
AnnaBridge 157:e7ca05fa8600 183 #define __CM7_REV 0x0000U
AnnaBridge 157:e7ca05fa8600 184 #warning "__CM7_REV not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 185 #endif
AnnaBridge 157:e7ca05fa8600 186
AnnaBridge 157:e7ca05fa8600 187 #ifndef __FPU_PRESENT
AnnaBridge 157:e7ca05fa8600 188 #define __FPU_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 189 #warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 190 #endif
AnnaBridge 157:e7ca05fa8600 191
AnnaBridge 157:e7ca05fa8600 192 #ifndef __MPU_PRESENT
AnnaBridge 157:e7ca05fa8600 193 #define __MPU_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 194 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 195 #endif
AnnaBridge 157:e7ca05fa8600 196
AnnaBridge 157:e7ca05fa8600 197 #ifndef __ICACHE_PRESENT
AnnaBridge 157:e7ca05fa8600 198 #define __ICACHE_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 199 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 200 #endif
AnnaBridge 157:e7ca05fa8600 201
AnnaBridge 157:e7ca05fa8600 202 #ifndef __DCACHE_PRESENT
AnnaBridge 157:e7ca05fa8600 203 #define __DCACHE_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 204 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 205 #endif
AnnaBridge 157:e7ca05fa8600 206
AnnaBridge 157:e7ca05fa8600 207 #ifndef __DTCM_PRESENT
AnnaBridge 157:e7ca05fa8600 208 #define __DTCM_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 209 #warning "__DTCM_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 210 #endif
AnnaBridge 157:e7ca05fa8600 211
AnnaBridge 157:e7ca05fa8600 212 #ifndef __NVIC_PRIO_BITS
AnnaBridge 157:e7ca05fa8600 213 #define __NVIC_PRIO_BITS 3U
AnnaBridge 157:e7ca05fa8600 214 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 215 #endif
AnnaBridge 157:e7ca05fa8600 216
AnnaBridge 157:e7ca05fa8600 217 #ifndef __Vendor_SysTickConfig
AnnaBridge 157:e7ca05fa8600 218 #define __Vendor_SysTickConfig 0U
AnnaBridge 157:e7ca05fa8600 219 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 220 #endif
AnnaBridge 157:e7ca05fa8600 221 #endif
AnnaBridge 157:e7ca05fa8600 222
AnnaBridge 157:e7ca05fa8600 223 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 157:e7ca05fa8600 224 /**
AnnaBridge 157:e7ca05fa8600 225 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 157:e7ca05fa8600 226
AnnaBridge 157:e7ca05fa8600 227 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 157:e7ca05fa8600 228 \li to specify the access to peripheral variables.
AnnaBridge 157:e7ca05fa8600 229 \li for automatic generation of peripheral register debug information.
AnnaBridge 157:e7ca05fa8600 230 */
AnnaBridge 157:e7ca05fa8600 231 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 232 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 157:e7ca05fa8600 233 #else
AnnaBridge 157:e7ca05fa8600 234 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 157:e7ca05fa8600 235 #endif
AnnaBridge 157:e7ca05fa8600 236 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 157:e7ca05fa8600 237 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 157:e7ca05fa8600 238
AnnaBridge 157:e7ca05fa8600 239 /* following defines should be used for structure members */
AnnaBridge 157:e7ca05fa8600 240 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 157:e7ca05fa8600 241 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 157:e7ca05fa8600 242 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 157:e7ca05fa8600 243
AnnaBridge 157:e7ca05fa8600 244 /*@} end of group Cortex_M7 */
AnnaBridge 157:e7ca05fa8600 245
AnnaBridge 157:e7ca05fa8600 246
AnnaBridge 157:e7ca05fa8600 247
AnnaBridge 157:e7ca05fa8600 248 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 249 * Register Abstraction
AnnaBridge 157:e7ca05fa8600 250 Core Register contain:
AnnaBridge 157:e7ca05fa8600 251 - Core Register
AnnaBridge 157:e7ca05fa8600 252 - Core NVIC Register
AnnaBridge 157:e7ca05fa8600 253 - Core SCB Register
AnnaBridge 157:e7ca05fa8600 254 - Core SysTick Register
AnnaBridge 157:e7ca05fa8600 255 - Core Debug Register
AnnaBridge 157:e7ca05fa8600 256 - Core MPU Register
AnnaBridge 157:e7ca05fa8600 257 - Core FPU Register
AnnaBridge 157:e7ca05fa8600 258 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 259 /**
AnnaBridge 157:e7ca05fa8600 260 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 157:e7ca05fa8600 261 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 157:e7ca05fa8600 262 */
AnnaBridge 157:e7ca05fa8600 263
AnnaBridge 157:e7ca05fa8600 264 /**
AnnaBridge 157:e7ca05fa8600 265 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 266 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 157:e7ca05fa8600 267 \brief Core Register type definitions.
AnnaBridge 157:e7ca05fa8600 268 @{
AnnaBridge 157:e7ca05fa8600 269 */
AnnaBridge 157:e7ca05fa8600 270
AnnaBridge 157:e7ca05fa8600 271 /**
AnnaBridge 157:e7ca05fa8600 272 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 157:e7ca05fa8600 273 */
AnnaBridge 157:e7ca05fa8600 274 typedef union
AnnaBridge 157:e7ca05fa8600 275 {
AnnaBridge 157:e7ca05fa8600 276 struct
AnnaBridge 157:e7ca05fa8600 277 {
AnnaBridge 157:e7ca05fa8600 278 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
AnnaBridge 157:e7ca05fa8600 279 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
AnnaBridge 157:e7ca05fa8600 280 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
AnnaBridge 157:e7ca05fa8600 281 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 157:e7ca05fa8600 282 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 157:e7ca05fa8600 283 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 157:e7ca05fa8600 284 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 157:e7ca05fa8600 285 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 157:e7ca05fa8600 286 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 287 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 288 } APSR_Type;
AnnaBridge 157:e7ca05fa8600 289
AnnaBridge 157:e7ca05fa8600 290 /* APSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 291 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 157:e7ca05fa8600 292 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 157:e7ca05fa8600 293
AnnaBridge 157:e7ca05fa8600 294 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 157:e7ca05fa8600 295 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 157:e7ca05fa8600 296
AnnaBridge 157:e7ca05fa8600 297 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 157:e7ca05fa8600 298 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 157:e7ca05fa8600 299
AnnaBridge 157:e7ca05fa8600 300 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 157:e7ca05fa8600 301 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 157:e7ca05fa8600 302
AnnaBridge 157:e7ca05fa8600 303 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
AnnaBridge 157:e7ca05fa8600 304 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
AnnaBridge 157:e7ca05fa8600 305
AnnaBridge 157:e7ca05fa8600 306 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
AnnaBridge 157:e7ca05fa8600 307 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
AnnaBridge 157:e7ca05fa8600 308
AnnaBridge 157:e7ca05fa8600 309
AnnaBridge 157:e7ca05fa8600 310 /**
AnnaBridge 157:e7ca05fa8600 311 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 157:e7ca05fa8600 312 */
AnnaBridge 157:e7ca05fa8600 313 typedef union
AnnaBridge 157:e7ca05fa8600 314 {
AnnaBridge 157:e7ca05fa8600 315 struct
AnnaBridge 157:e7ca05fa8600 316 {
AnnaBridge 157:e7ca05fa8600 317 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 157:e7ca05fa8600 318 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 157:e7ca05fa8600 319 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 320 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 321 } IPSR_Type;
AnnaBridge 157:e7ca05fa8600 322
AnnaBridge 157:e7ca05fa8600 323 /* IPSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 324 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 157:e7ca05fa8600 325 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 157:e7ca05fa8600 326
AnnaBridge 157:e7ca05fa8600 327
AnnaBridge 157:e7ca05fa8600 328 /**
AnnaBridge 157:e7ca05fa8600 329 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 157:e7ca05fa8600 330 */
AnnaBridge 157:e7ca05fa8600 331 typedef union
AnnaBridge 157:e7ca05fa8600 332 {
AnnaBridge 157:e7ca05fa8600 333 struct
AnnaBridge 157:e7ca05fa8600 334 {
AnnaBridge 157:e7ca05fa8600 335 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 157:e7ca05fa8600 336 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
AnnaBridge 157:e7ca05fa8600 337 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
AnnaBridge 157:e7ca05fa8600 338 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
AnnaBridge 157:e7ca05fa8600 339 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
AnnaBridge 157:e7ca05fa8600 340 uint32_t T:1; /*!< bit: 24 Thumb bit */
AnnaBridge 157:e7ca05fa8600 341 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
AnnaBridge 157:e7ca05fa8600 342 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 157:e7ca05fa8600 343 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 157:e7ca05fa8600 344 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 157:e7ca05fa8600 345 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 157:e7ca05fa8600 346 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 157:e7ca05fa8600 347 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 348 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 349 } xPSR_Type;
AnnaBridge 157:e7ca05fa8600 350
AnnaBridge 157:e7ca05fa8600 351 /* xPSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 352 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 157:e7ca05fa8600 353 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 157:e7ca05fa8600 354
AnnaBridge 157:e7ca05fa8600 355 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 157:e7ca05fa8600 356 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 157:e7ca05fa8600 357
AnnaBridge 157:e7ca05fa8600 358 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 157:e7ca05fa8600 359 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 157:e7ca05fa8600 360
AnnaBridge 157:e7ca05fa8600 361 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 157:e7ca05fa8600 362 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 157:e7ca05fa8600 363
AnnaBridge 157:e7ca05fa8600 364 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
AnnaBridge 157:e7ca05fa8600 365 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
AnnaBridge 157:e7ca05fa8600 366
AnnaBridge 157:e7ca05fa8600 367 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
AnnaBridge 157:e7ca05fa8600 368 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
AnnaBridge 157:e7ca05fa8600 369
AnnaBridge 157:e7ca05fa8600 370 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 157:e7ca05fa8600 371 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 157:e7ca05fa8600 372
AnnaBridge 157:e7ca05fa8600 373 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
AnnaBridge 157:e7ca05fa8600 374 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
AnnaBridge 157:e7ca05fa8600 375
AnnaBridge 157:e7ca05fa8600 376 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
AnnaBridge 157:e7ca05fa8600 377 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
AnnaBridge 157:e7ca05fa8600 378
AnnaBridge 157:e7ca05fa8600 379 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 157:e7ca05fa8600 380 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 157:e7ca05fa8600 381
AnnaBridge 157:e7ca05fa8600 382
AnnaBridge 157:e7ca05fa8600 383 /**
AnnaBridge 157:e7ca05fa8600 384 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 157:e7ca05fa8600 385 */
AnnaBridge 157:e7ca05fa8600 386 typedef union
AnnaBridge 157:e7ca05fa8600 387 {
AnnaBridge 157:e7ca05fa8600 388 struct
AnnaBridge 157:e7ca05fa8600 389 {
AnnaBridge 157:e7ca05fa8600 390 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 157:e7ca05fa8600 391 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 157:e7ca05fa8600 392 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
AnnaBridge 157:e7ca05fa8600 393 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
AnnaBridge 157:e7ca05fa8600 394 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 395 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 396 } CONTROL_Type;
AnnaBridge 157:e7ca05fa8600 397
AnnaBridge 157:e7ca05fa8600 398 /* CONTROL Register Definitions */
AnnaBridge 157:e7ca05fa8600 399 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
AnnaBridge 157:e7ca05fa8600 400 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
AnnaBridge 157:e7ca05fa8600 401
AnnaBridge 157:e7ca05fa8600 402 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 157:e7ca05fa8600 403 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 157:e7ca05fa8600 404
AnnaBridge 157:e7ca05fa8600 405 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 157:e7ca05fa8600 406 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 157:e7ca05fa8600 407
AnnaBridge 157:e7ca05fa8600 408 /*@} end of group CMSIS_CORE */
AnnaBridge 157:e7ca05fa8600 409
AnnaBridge 157:e7ca05fa8600 410
AnnaBridge 157:e7ca05fa8600 411 /**
AnnaBridge 157:e7ca05fa8600 412 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 413 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 157:e7ca05fa8600 414 \brief Type definitions for the NVIC Registers
AnnaBridge 157:e7ca05fa8600 415 @{
AnnaBridge 157:e7ca05fa8600 416 */
AnnaBridge 157:e7ca05fa8600 417
AnnaBridge 157:e7ca05fa8600 418 /**
AnnaBridge 157:e7ca05fa8600 419 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 157:e7ca05fa8600 420 */
AnnaBridge 157:e7ca05fa8600 421 typedef struct
AnnaBridge 157:e7ca05fa8600 422 {
AnnaBridge 157:e7ca05fa8600 423 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 157:e7ca05fa8600 424 uint32_t RESERVED0[24U];
AnnaBridge 157:e7ca05fa8600 425 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 157:e7ca05fa8600 426 uint32_t RSERVED1[24U];
AnnaBridge 157:e7ca05fa8600 427 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 157:e7ca05fa8600 428 uint32_t RESERVED2[24U];
AnnaBridge 157:e7ca05fa8600 429 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 157:e7ca05fa8600 430 uint32_t RESERVED3[24U];
AnnaBridge 157:e7ca05fa8600 431 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 157:e7ca05fa8600 432 uint32_t RESERVED4[56U];
AnnaBridge 157:e7ca05fa8600 433 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
AnnaBridge 157:e7ca05fa8600 434 uint32_t RESERVED5[644U];
AnnaBridge 157:e7ca05fa8600 435 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
AnnaBridge 157:e7ca05fa8600 436 } NVIC_Type;
AnnaBridge 157:e7ca05fa8600 437
AnnaBridge 157:e7ca05fa8600 438 /* Software Triggered Interrupt Register Definitions */
AnnaBridge 157:e7ca05fa8600 439 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
AnnaBridge 157:e7ca05fa8600 440 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
AnnaBridge 157:e7ca05fa8600 441
AnnaBridge 157:e7ca05fa8600 442 /*@} end of group CMSIS_NVIC */
AnnaBridge 157:e7ca05fa8600 443
AnnaBridge 157:e7ca05fa8600 444
AnnaBridge 157:e7ca05fa8600 445 /**
AnnaBridge 157:e7ca05fa8600 446 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 447 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 157:e7ca05fa8600 448 \brief Type definitions for the System Control Block Registers
AnnaBridge 157:e7ca05fa8600 449 @{
AnnaBridge 157:e7ca05fa8600 450 */
AnnaBridge 157:e7ca05fa8600 451
AnnaBridge 157:e7ca05fa8600 452 /**
AnnaBridge 157:e7ca05fa8600 453 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 157:e7ca05fa8600 454 */
AnnaBridge 157:e7ca05fa8600 455 typedef struct
AnnaBridge 157:e7ca05fa8600 456 {
AnnaBridge 157:e7ca05fa8600 457 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 157:e7ca05fa8600 458 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 157:e7ca05fa8600 459 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 157:e7ca05fa8600 460 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 157:e7ca05fa8600 461 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 157:e7ca05fa8600 462 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 157:e7ca05fa8600 463 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
AnnaBridge 157:e7ca05fa8600 464 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 157:e7ca05fa8600 465 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
AnnaBridge 157:e7ca05fa8600 466 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
AnnaBridge 157:e7ca05fa8600 467 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
AnnaBridge 157:e7ca05fa8600 468 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
AnnaBridge 157:e7ca05fa8600 469 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
AnnaBridge 157:e7ca05fa8600 470 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
AnnaBridge 157:e7ca05fa8600 471 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
AnnaBridge 157:e7ca05fa8600 472 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
AnnaBridge 157:e7ca05fa8600 473 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
AnnaBridge 157:e7ca05fa8600 474 __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
AnnaBridge 157:e7ca05fa8600 475 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
AnnaBridge 157:e7ca05fa8600 476 uint32_t RESERVED0[1U];
AnnaBridge 157:e7ca05fa8600 477 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
AnnaBridge 157:e7ca05fa8600 478 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
AnnaBridge 157:e7ca05fa8600 479 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
AnnaBridge 157:e7ca05fa8600 480 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
AnnaBridge 157:e7ca05fa8600 481 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
AnnaBridge 157:e7ca05fa8600 482 uint32_t RESERVED3[93U];
AnnaBridge 157:e7ca05fa8600 483 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
AnnaBridge 157:e7ca05fa8600 484 uint32_t RESERVED4[15U];
AnnaBridge 157:e7ca05fa8600 485 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
AnnaBridge 157:e7ca05fa8600 486 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
Anna Bridge 160:5571c4ff569f 487 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
AnnaBridge 157:e7ca05fa8600 488 uint32_t RESERVED5[1U];
AnnaBridge 157:e7ca05fa8600 489 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
AnnaBridge 157:e7ca05fa8600 490 uint32_t RESERVED6[1U];
AnnaBridge 157:e7ca05fa8600 491 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
AnnaBridge 157:e7ca05fa8600 492 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
AnnaBridge 157:e7ca05fa8600 493 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
AnnaBridge 157:e7ca05fa8600 494 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
AnnaBridge 157:e7ca05fa8600 495 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
AnnaBridge 157:e7ca05fa8600 496 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
AnnaBridge 157:e7ca05fa8600 497 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
AnnaBridge 157:e7ca05fa8600 498 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
AnnaBridge 157:e7ca05fa8600 499 uint32_t RESERVED7[6U];
AnnaBridge 157:e7ca05fa8600 500 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
AnnaBridge 157:e7ca05fa8600 501 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
AnnaBridge 157:e7ca05fa8600 502 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
AnnaBridge 157:e7ca05fa8600 503 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
AnnaBridge 157:e7ca05fa8600 504 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
AnnaBridge 157:e7ca05fa8600 505 uint32_t RESERVED8[1U];
AnnaBridge 157:e7ca05fa8600 506 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
AnnaBridge 157:e7ca05fa8600 507 } SCB_Type;
AnnaBridge 157:e7ca05fa8600 508
AnnaBridge 157:e7ca05fa8600 509 /* SCB CPUID Register Definitions */
AnnaBridge 157:e7ca05fa8600 510 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 157:e7ca05fa8600 511 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 157:e7ca05fa8600 512
AnnaBridge 157:e7ca05fa8600 513 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 157:e7ca05fa8600 514 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 157:e7ca05fa8600 515
AnnaBridge 157:e7ca05fa8600 516 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 157:e7ca05fa8600 517 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 157:e7ca05fa8600 518
AnnaBridge 157:e7ca05fa8600 519 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 157:e7ca05fa8600 520 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 157:e7ca05fa8600 521
AnnaBridge 157:e7ca05fa8600 522 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 157:e7ca05fa8600 523 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 157:e7ca05fa8600 524
AnnaBridge 157:e7ca05fa8600 525 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 157:e7ca05fa8600 526 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 157:e7ca05fa8600 527 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 157:e7ca05fa8600 528
AnnaBridge 157:e7ca05fa8600 529 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 157:e7ca05fa8600 530 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 157:e7ca05fa8600 531
AnnaBridge 157:e7ca05fa8600 532 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 157:e7ca05fa8600 533 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 157:e7ca05fa8600 534
AnnaBridge 157:e7ca05fa8600 535 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 157:e7ca05fa8600 536 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 157:e7ca05fa8600 537
AnnaBridge 157:e7ca05fa8600 538 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 157:e7ca05fa8600 539 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 157:e7ca05fa8600 540
AnnaBridge 157:e7ca05fa8600 541 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 157:e7ca05fa8600 542 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 157:e7ca05fa8600 543
AnnaBridge 157:e7ca05fa8600 544 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 157:e7ca05fa8600 545 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 157:e7ca05fa8600 546
AnnaBridge 157:e7ca05fa8600 547 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 157:e7ca05fa8600 548 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 157:e7ca05fa8600 549
AnnaBridge 157:e7ca05fa8600 550 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 157:e7ca05fa8600 551 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 157:e7ca05fa8600 552
AnnaBridge 157:e7ca05fa8600 553 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 157:e7ca05fa8600 554 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 157:e7ca05fa8600 555
AnnaBridge 157:e7ca05fa8600 556 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 157:e7ca05fa8600 557 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 157:e7ca05fa8600 558 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 157:e7ca05fa8600 559
AnnaBridge 157:e7ca05fa8600 560 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 561 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 157:e7ca05fa8600 562 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 157:e7ca05fa8600 563
AnnaBridge 157:e7ca05fa8600 564 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 157:e7ca05fa8600 565 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 157:e7ca05fa8600 566
AnnaBridge 157:e7ca05fa8600 567 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 157:e7ca05fa8600 568 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 157:e7ca05fa8600 569
AnnaBridge 157:e7ca05fa8600 570 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
AnnaBridge 157:e7ca05fa8600 571 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
AnnaBridge 157:e7ca05fa8600 572
AnnaBridge 157:e7ca05fa8600 573 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 157:e7ca05fa8600 574 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 157:e7ca05fa8600 575
AnnaBridge 157:e7ca05fa8600 576 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 157:e7ca05fa8600 577 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 157:e7ca05fa8600 578
AnnaBridge 157:e7ca05fa8600 579 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
AnnaBridge 157:e7ca05fa8600 580 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
AnnaBridge 157:e7ca05fa8600 581
AnnaBridge 157:e7ca05fa8600 582 /* SCB System Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 583 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 157:e7ca05fa8600 584 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 157:e7ca05fa8600 585
AnnaBridge 157:e7ca05fa8600 586 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 157:e7ca05fa8600 587 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 157:e7ca05fa8600 588
AnnaBridge 157:e7ca05fa8600 589 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 157:e7ca05fa8600 590 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 157:e7ca05fa8600 591
AnnaBridge 157:e7ca05fa8600 592 /* SCB Configuration Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 593 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
AnnaBridge 157:e7ca05fa8600 594 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
AnnaBridge 157:e7ca05fa8600 595
AnnaBridge 157:e7ca05fa8600 596 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
AnnaBridge 157:e7ca05fa8600 597 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
AnnaBridge 157:e7ca05fa8600 598
AnnaBridge 157:e7ca05fa8600 599 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
AnnaBridge 157:e7ca05fa8600 600 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
AnnaBridge 157:e7ca05fa8600 601
AnnaBridge 157:e7ca05fa8600 602 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 157:e7ca05fa8600 603 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 157:e7ca05fa8600 604
AnnaBridge 157:e7ca05fa8600 605 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 157:e7ca05fa8600 606 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 157:e7ca05fa8600 607
AnnaBridge 157:e7ca05fa8600 608 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 157:e7ca05fa8600 609 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 157:e7ca05fa8600 610
AnnaBridge 157:e7ca05fa8600 611 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 157:e7ca05fa8600 612 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 157:e7ca05fa8600 613
AnnaBridge 157:e7ca05fa8600 614 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 157:e7ca05fa8600 615 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 157:e7ca05fa8600 616
AnnaBridge 157:e7ca05fa8600 617 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
AnnaBridge 157:e7ca05fa8600 618 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
AnnaBridge 157:e7ca05fa8600 619
AnnaBridge 157:e7ca05fa8600 620 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 157:e7ca05fa8600 621 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
AnnaBridge 157:e7ca05fa8600 622 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
AnnaBridge 157:e7ca05fa8600 623
AnnaBridge 157:e7ca05fa8600 624 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
AnnaBridge 157:e7ca05fa8600 625 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
AnnaBridge 157:e7ca05fa8600 626
AnnaBridge 157:e7ca05fa8600 627 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
AnnaBridge 157:e7ca05fa8600 628 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
AnnaBridge 157:e7ca05fa8600 629
AnnaBridge 157:e7ca05fa8600 630 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 157:e7ca05fa8600 631 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 157:e7ca05fa8600 632
AnnaBridge 157:e7ca05fa8600 633 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
AnnaBridge 157:e7ca05fa8600 634 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
AnnaBridge 157:e7ca05fa8600 635
AnnaBridge 157:e7ca05fa8600 636 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
AnnaBridge 157:e7ca05fa8600 637 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
AnnaBridge 157:e7ca05fa8600 638
AnnaBridge 157:e7ca05fa8600 639 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
AnnaBridge 157:e7ca05fa8600 640 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
AnnaBridge 157:e7ca05fa8600 641
AnnaBridge 157:e7ca05fa8600 642 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 157:e7ca05fa8600 643 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 157:e7ca05fa8600 644
AnnaBridge 157:e7ca05fa8600 645 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 157:e7ca05fa8600 646 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 157:e7ca05fa8600 647
AnnaBridge 157:e7ca05fa8600 648 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
AnnaBridge 157:e7ca05fa8600 649 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
AnnaBridge 157:e7ca05fa8600 650
AnnaBridge 157:e7ca05fa8600 651 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 157:e7ca05fa8600 652 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 157:e7ca05fa8600 653
AnnaBridge 157:e7ca05fa8600 654 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
AnnaBridge 157:e7ca05fa8600 655 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
AnnaBridge 157:e7ca05fa8600 656
AnnaBridge 157:e7ca05fa8600 657 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
AnnaBridge 157:e7ca05fa8600 658 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
AnnaBridge 157:e7ca05fa8600 659
AnnaBridge 157:e7ca05fa8600 660 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
AnnaBridge 157:e7ca05fa8600 661 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
AnnaBridge 157:e7ca05fa8600 662
AnnaBridge 157:e7ca05fa8600 663 /* SCB Configurable Fault Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 664 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
AnnaBridge 157:e7ca05fa8600 665 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
AnnaBridge 157:e7ca05fa8600 666
AnnaBridge 157:e7ca05fa8600 667 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
AnnaBridge 157:e7ca05fa8600 668 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
AnnaBridge 157:e7ca05fa8600 669
AnnaBridge 157:e7ca05fa8600 670 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
AnnaBridge 157:e7ca05fa8600 671 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
AnnaBridge 157:e7ca05fa8600 672
AnnaBridge 157:e7ca05fa8600 673 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 157:e7ca05fa8600 674 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
AnnaBridge 157:e7ca05fa8600 675 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
AnnaBridge 157:e7ca05fa8600 676
AnnaBridge 157:e7ca05fa8600 677 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
AnnaBridge 157:e7ca05fa8600 678 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
AnnaBridge 157:e7ca05fa8600 679
AnnaBridge 157:e7ca05fa8600 680 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
AnnaBridge 157:e7ca05fa8600 681 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
AnnaBridge 157:e7ca05fa8600 682
AnnaBridge 157:e7ca05fa8600 683 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
AnnaBridge 157:e7ca05fa8600 684 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
AnnaBridge 157:e7ca05fa8600 685
AnnaBridge 157:e7ca05fa8600 686 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
AnnaBridge 157:e7ca05fa8600 687 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
AnnaBridge 157:e7ca05fa8600 688
AnnaBridge 157:e7ca05fa8600 689 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
AnnaBridge 157:e7ca05fa8600 690 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
AnnaBridge 157:e7ca05fa8600 691
AnnaBridge 157:e7ca05fa8600 692 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 157:e7ca05fa8600 693 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
AnnaBridge 157:e7ca05fa8600 694 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
AnnaBridge 157:e7ca05fa8600 695
AnnaBridge 157:e7ca05fa8600 696 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
AnnaBridge 157:e7ca05fa8600 697 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
AnnaBridge 157:e7ca05fa8600 698
AnnaBridge 157:e7ca05fa8600 699 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
AnnaBridge 157:e7ca05fa8600 700 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
AnnaBridge 157:e7ca05fa8600 701
AnnaBridge 157:e7ca05fa8600 702 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
AnnaBridge 157:e7ca05fa8600 703 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
AnnaBridge 157:e7ca05fa8600 704
AnnaBridge 157:e7ca05fa8600 705 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
AnnaBridge 157:e7ca05fa8600 706 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
AnnaBridge 157:e7ca05fa8600 707
AnnaBridge 157:e7ca05fa8600 708 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
AnnaBridge 157:e7ca05fa8600 709 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
AnnaBridge 157:e7ca05fa8600 710
AnnaBridge 157:e7ca05fa8600 711 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
AnnaBridge 157:e7ca05fa8600 712 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
AnnaBridge 157:e7ca05fa8600 713
AnnaBridge 157:e7ca05fa8600 714 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 157:e7ca05fa8600 715 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
AnnaBridge 157:e7ca05fa8600 716 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
AnnaBridge 157:e7ca05fa8600 717
AnnaBridge 157:e7ca05fa8600 718 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
AnnaBridge 157:e7ca05fa8600 719 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
AnnaBridge 157:e7ca05fa8600 720
AnnaBridge 157:e7ca05fa8600 721 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
AnnaBridge 157:e7ca05fa8600 722 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
AnnaBridge 157:e7ca05fa8600 723
AnnaBridge 157:e7ca05fa8600 724 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
AnnaBridge 157:e7ca05fa8600 725 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
AnnaBridge 157:e7ca05fa8600 726
AnnaBridge 157:e7ca05fa8600 727 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
AnnaBridge 157:e7ca05fa8600 728 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
AnnaBridge 157:e7ca05fa8600 729
AnnaBridge 157:e7ca05fa8600 730 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
AnnaBridge 157:e7ca05fa8600 731 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
AnnaBridge 157:e7ca05fa8600 732
AnnaBridge 157:e7ca05fa8600 733 /* SCB Hard Fault Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 734 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
AnnaBridge 157:e7ca05fa8600 735 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
AnnaBridge 157:e7ca05fa8600 736
AnnaBridge 157:e7ca05fa8600 737 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
AnnaBridge 157:e7ca05fa8600 738 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
AnnaBridge 157:e7ca05fa8600 739
AnnaBridge 157:e7ca05fa8600 740 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
AnnaBridge 157:e7ca05fa8600 741 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
AnnaBridge 157:e7ca05fa8600 742
AnnaBridge 157:e7ca05fa8600 743 /* SCB Debug Fault Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 744 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
AnnaBridge 157:e7ca05fa8600 745 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
AnnaBridge 157:e7ca05fa8600 746
AnnaBridge 157:e7ca05fa8600 747 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
AnnaBridge 157:e7ca05fa8600 748 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
AnnaBridge 157:e7ca05fa8600 749
AnnaBridge 157:e7ca05fa8600 750 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
AnnaBridge 157:e7ca05fa8600 751 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
AnnaBridge 157:e7ca05fa8600 752
AnnaBridge 157:e7ca05fa8600 753 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
AnnaBridge 157:e7ca05fa8600 754 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
AnnaBridge 157:e7ca05fa8600 755
AnnaBridge 157:e7ca05fa8600 756 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
AnnaBridge 157:e7ca05fa8600 757 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
AnnaBridge 157:e7ca05fa8600 758
AnnaBridge 157:e7ca05fa8600 759 /* SCB Cache Level ID Register Definitions */
AnnaBridge 157:e7ca05fa8600 760 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
AnnaBridge 157:e7ca05fa8600 761 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
AnnaBridge 157:e7ca05fa8600 762
AnnaBridge 157:e7ca05fa8600 763 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
AnnaBridge 157:e7ca05fa8600 764 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
AnnaBridge 157:e7ca05fa8600 765
AnnaBridge 157:e7ca05fa8600 766 /* SCB Cache Type Register Definitions */
AnnaBridge 157:e7ca05fa8600 767 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
AnnaBridge 157:e7ca05fa8600 768 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
AnnaBridge 157:e7ca05fa8600 769
AnnaBridge 157:e7ca05fa8600 770 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
AnnaBridge 157:e7ca05fa8600 771 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
AnnaBridge 157:e7ca05fa8600 772
AnnaBridge 157:e7ca05fa8600 773 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
AnnaBridge 157:e7ca05fa8600 774 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
AnnaBridge 157:e7ca05fa8600 775
AnnaBridge 157:e7ca05fa8600 776 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
AnnaBridge 157:e7ca05fa8600 777 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
AnnaBridge 157:e7ca05fa8600 778
AnnaBridge 157:e7ca05fa8600 779 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
AnnaBridge 157:e7ca05fa8600 780 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
AnnaBridge 157:e7ca05fa8600 781
AnnaBridge 157:e7ca05fa8600 782 /* SCB Cache Size ID Register Definitions */
AnnaBridge 157:e7ca05fa8600 783 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
AnnaBridge 157:e7ca05fa8600 784 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
AnnaBridge 157:e7ca05fa8600 785
AnnaBridge 157:e7ca05fa8600 786 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
AnnaBridge 157:e7ca05fa8600 787 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
AnnaBridge 157:e7ca05fa8600 788
AnnaBridge 157:e7ca05fa8600 789 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
AnnaBridge 157:e7ca05fa8600 790 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
AnnaBridge 157:e7ca05fa8600 791
AnnaBridge 157:e7ca05fa8600 792 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
AnnaBridge 157:e7ca05fa8600 793 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
AnnaBridge 157:e7ca05fa8600 794
AnnaBridge 157:e7ca05fa8600 795 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
AnnaBridge 157:e7ca05fa8600 796 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
AnnaBridge 157:e7ca05fa8600 797
AnnaBridge 157:e7ca05fa8600 798 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
AnnaBridge 157:e7ca05fa8600 799 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
AnnaBridge 157:e7ca05fa8600 800
AnnaBridge 157:e7ca05fa8600 801 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
AnnaBridge 157:e7ca05fa8600 802 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
AnnaBridge 157:e7ca05fa8600 803
AnnaBridge 157:e7ca05fa8600 804 /* SCB Cache Size Selection Register Definitions */
AnnaBridge 157:e7ca05fa8600 805 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
AnnaBridge 157:e7ca05fa8600 806 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
AnnaBridge 157:e7ca05fa8600 807
AnnaBridge 157:e7ca05fa8600 808 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
AnnaBridge 157:e7ca05fa8600 809 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
AnnaBridge 157:e7ca05fa8600 810
AnnaBridge 157:e7ca05fa8600 811 /* SCB Software Triggered Interrupt Register Definitions */
AnnaBridge 157:e7ca05fa8600 812 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
AnnaBridge 157:e7ca05fa8600 813 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
AnnaBridge 157:e7ca05fa8600 814
AnnaBridge 157:e7ca05fa8600 815 /* SCB D-Cache Invalidate by Set-way Register Definitions */
AnnaBridge 157:e7ca05fa8600 816 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
AnnaBridge 157:e7ca05fa8600 817 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
AnnaBridge 157:e7ca05fa8600 818
AnnaBridge 157:e7ca05fa8600 819 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
AnnaBridge 157:e7ca05fa8600 820 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
AnnaBridge 157:e7ca05fa8600 821
AnnaBridge 157:e7ca05fa8600 822 /* SCB D-Cache Clean by Set-way Register Definitions */
AnnaBridge 157:e7ca05fa8600 823 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
AnnaBridge 157:e7ca05fa8600 824 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
AnnaBridge 157:e7ca05fa8600 825
AnnaBridge 157:e7ca05fa8600 826 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
AnnaBridge 157:e7ca05fa8600 827 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
AnnaBridge 157:e7ca05fa8600 828
AnnaBridge 157:e7ca05fa8600 829 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
AnnaBridge 157:e7ca05fa8600 830 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
AnnaBridge 157:e7ca05fa8600 831 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
AnnaBridge 157:e7ca05fa8600 832
AnnaBridge 157:e7ca05fa8600 833 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
AnnaBridge 157:e7ca05fa8600 834 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
AnnaBridge 157:e7ca05fa8600 835
AnnaBridge 157:e7ca05fa8600 836 /* Instruction Tightly-Coupled Memory Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 837 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
AnnaBridge 157:e7ca05fa8600 838 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
AnnaBridge 157:e7ca05fa8600 839
AnnaBridge 157:e7ca05fa8600 840 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
AnnaBridge 157:e7ca05fa8600 841 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
AnnaBridge 157:e7ca05fa8600 842
AnnaBridge 157:e7ca05fa8600 843 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
AnnaBridge 157:e7ca05fa8600 844 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
AnnaBridge 157:e7ca05fa8600 845
AnnaBridge 157:e7ca05fa8600 846 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
AnnaBridge 157:e7ca05fa8600 847 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
AnnaBridge 157:e7ca05fa8600 848
AnnaBridge 157:e7ca05fa8600 849 /* Data Tightly-Coupled Memory Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 850 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
AnnaBridge 157:e7ca05fa8600 851 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
AnnaBridge 157:e7ca05fa8600 852
AnnaBridge 157:e7ca05fa8600 853 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
AnnaBridge 157:e7ca05fa8600 854 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
AnnaBridge 157:e7ca05fa8600 855
AnnaBridge 157:e7ca05fa8600 856 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
AnnaBridge 157:e7ca05fa8600 857 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
AnnaBridge 157:e7ca05fa8600 858
AnnaBridge 157:e7ca05fa8600 859 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
AnnaBridge 157:e7ca05fa8600 860 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
AnnaBridge 157:e7ca05fa8600 861
AnnaBridge 157:e7ca05fa8600 862 /* AHBP Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 863 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
AnnaBridge 157:e7ca05fa8600 864 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
AnnaBridge 157:e7ca05fa8600 865
AnnaBridge 157:e7ca05fa8600 866 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
AnnaBridge 157:e7ca05fa8600 867 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
AnnaBridge 157:e7ca05fa8600 868
AnnaBridge 157:e7ca05fa8600 869 /* L1 Cache Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 870 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
AnnaBridge 157:e7ca05fa8600 871 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
AnnaBridge 157:e7ca05fa8600 872
AnnaBridge 157:e7ca05fa8600 873 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
AnnaBridge 157:e7ca05fa8600 874 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
AnnaBridge 157:e7ca05fa8600 875
AnnaBridge 157:e7ca05fa8600 876 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
AnnaBridge 157:e7ca05fa8600 877 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
AnnaBridge 157:e7ca05fa8600 878
AnnaBridge 157:e7ca05fa8600 879 /* AHBS Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 880 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
AnnaBridge 157:e7ca05fa8600 881 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
AnnaBridge 157:e7ca05fa8600 882
AnnaBridge 157:e7ca05fa8600 883 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
AnnaBridge 157:e7ca05fa8600 884 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
AnnaBridge 157:e7ca05fa8600 885
AnnaBridge 157:e7ca05fa8600 886 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
AnnaBridge 157:e7ca05fa8600 887 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
AnnaBridge 157:e7ca05fa8600 888
AnnaBridge 157:e7ca05fa8600 889 /* Auxiliary Bus Fault Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 890 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
AnnaBridge 157:e7ca05fa8600 891 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
AnnaBridge 157:e7ca05fa8600 892
AnnaBridge 157:e7ca05fa8600 893 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
AnnaBridge 157:e7ca05fa8600 894 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
AnnaBridge 157:e7ca05fa8600 895
AnnaBridge 157:e7ca05fa8600 896 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
AnnaBridge 157:e7ca05fa8600 897 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
AnnaBridge 157:e7ca05fa8600 898
AnnaBridge 157:e7ca05fa8600 899 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
AnnaBridge 157:e7ca05fa8600 900 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
AnnaBridge 157:e7ca05fa8600 901
AnnaBridge 157:e7ca05fa8600 902 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
AnnaBridge 157:e7ca05fa8600 903 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
AnnaBridge 157:e7ca05fa8600 904
AnnaBridge 157:e7ca05fa8600 905 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
AnnaBridge 157:e7ca05fa8600 906 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
AnnaBridge 157:e7ca05fa8600 907
AnnaBridge 157:e7ca05fa8600 908 /*@} end of group CMSIS_SCB */
AnnaBridge 157:e7ca05fa8600 909
AnnaBridge 157:e7ca05fa8600 910
AnnaBridge 157:e7ca05fa8600 911 /**
AnnaBridge 157:e7ca05fa8600 912 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 913 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 157:e7ca05fa8600 914 \brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge 157:e7ca05fa8600 915 @{
AnnaBridge 157:e7ca05fa8600 916 */
AnnaBridge 157:e7ca05fa8600 917
AnnaBridge 157:e7ca05fa8600 918 /**
AnnaBridge 157:e7ca05fa8600 919 \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge 157:e7ca05fa8600 920 */
AnnaBridge 157:e7ca05fa8600 921 typedef struct
AnnaBridge 157:e7ca05fa8600 922 {
AnnaBridge 157:e7ca05fa8600 923 uint32_t RESERVED0[1U];
AnnaBridge 157:e7ca05fa8600 924 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
AnnaBridge 157:e7ca05fa8600 925 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
AnnaBridge 157:e7ca05fa8600 926 } SCnSCB_Type;
AnnaBridge 157:e7ca05fa8600 927
AnnaBridge 157:e7ca05fa8600 928 /* Interrupt Controller Type Register Definitions */
AnnaBridge 157:e7ca05fa8600 929 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
AnnaBridge 157:e7ca05fa8600 930 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
AnnaBridge 157:e7ca05fa8600 931
AnnaBridge 157:e7ca05fa8600 932 /* Auxiliary Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 933 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
AnnaBridge 157:e7ca05fa8600 934 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
AnnaBridge 157:e7ca05fa8600 935
AnnaBridge 157:e7ca05fa8600 936 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
AnnaBridge 157:e7ca05fa8600 937 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
AnnaBridge 157:e7ca05fa8600 938
AnnaBridge 157:e7ca05fa8600 939 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
AnnaBridge 157:e7ca05fa8600 940 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
AnnaBridge 157:e7ca05fa8600 941
AnnaBridge 157:e7ca05fa8600 942 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
AnnaBridge 157:e7ca05fa8600 943 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
AnnaBridge 157:e7ca05fa8600 944
AnnaBridge 157:e7ca05fa8600 945 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
AnnaBridge 157:e7ca05fa8600 946 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
AnnaBridge 157:e7ca05fa8600 947
AnnaBridge 157:e7ca05fa8600 948 /*@} end of group CMSIS_SCnotSCB */
AnnaBridge 157:e7ca05fa8600 949
AnnaBridge 157:e7ca05fa8600 950
AnnaBridge 157:e7ca05fa8600 951 /**
AnnaBridge 157:e7ca05fa8600 952 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 953 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 157:e7ca05fa8600 954 \brief Type definitions for the System Timer Registers.
AnnaBridge 157:e7ca05fa8600 955 @{
AnnaBridge 157:e7ca05fa8600 956 */
AnnaBridge 157:e7ca05fa8600 957
AnnaBridge 157:e7ca05fa8600 958 /**
AnnaBridge 157:e7ca05fa8600 959 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 157:e7ca05fa8600 960 */
AnnaBridge 157:e7ca05fa8600 961 typedef struct
AnnaBridge 157:e7ca05fa8600 962 {
AnnaBridge 157:e7ca05fa8600 963 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 157:e7ca05fa8600 964 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 157:e7ca05fa8600 965 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 157:e7ca05fa8600 966 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 157:e7ca05fa8600 967 } SysTick_Type;
AnnaBridge 157:e7ca05fa8600 968
AnnaBridge 157:e7ca05fa8600 969 /* SysTick Control / Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 970 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 157:e7ca05fa8600 971 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 157:e7ca05fa8600 972
AnnaBridge 157:e7ca05fa8600 973 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 157:e7ca05fa8600 974 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 157:e7ca05fa8600 975
AnnaBridge 157:e7ca05fa8600 976 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 157:e7ca05fa8600 977 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 157:e7ca05fa8600 978
AnnaBridge 157:e7ca05fa8600 979 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 157:e7ca05fa8600 980 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 157:e7ca05fa8600 981
AnnaBridge 157:e7ca05fa8600 982 /* SysTick Reload Register Definitions */
AnnaBridge 157:e7ca05fa8600 983 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 157:e7ca05fa8600 984 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 157:e7ca05fa8600 985
AnnaBridge 157:e7ca05fa8600 986 /* SysTick Current Register Definitions */
AnnaBridge 157:e7ca05fa8600 987 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 157:e7ca05fa8600 988 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 157:e7ca05fa8600 989
AnnaBridge 157:e7ca05fa8600 990 /* SysTick Calibration Register Definitions */
AnnaBridge 157:e7ca05fa8600 991 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 157:e7ca05fa8600 992 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 157:e7ca05fa8600 993
AnnaBridge 157:e7ca05fa8600 994 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 157:e7ca05fa8600 995 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 157:e7ca05fa8600 996
AnnaBridge 157:e7ca05fa8600 997 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 157:e7ca05fa8600 998 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 157:e7ca05fa8600 999
AnnaBridge 157:e7ca05fa8600 1000 /*@} end of group CMSIS_SysTick */
AnnaBridge 157:e7ca05fa8600 1001
AnnaBridge 157:e7ca05fa8600 1002
AnnaBridge 157:e7ca05fa8600 1003 /**
AnnaBridge 157:e7ca05fa8600 1004 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 1005 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge 157:e7ca05fa8600 1006 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge 157:e7ca05fa8600 1007 @{
AnnaBridge 157:e7ca05fa8600 1008 */
AnnaBridge 157:e7ca05fa8600 1009
AnnaBridge 157:e7ca05fa8600 1010 /**
AnnaBridge 157:e7ca05fa8600 1011 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge 157:e7ca05fa8600 1012 */
AnnaBridge 157:e7ca05fa8600 1013 typedef struct
AnnaBridge 157:e7ca05fa8600 1014 {
AnnaBridge 157:e7ca05fa8600 1015 __OM union
AnnaBridge 157:e7ca05fa8600 1016 {
AnnaBridge 157:e7ca05fa8600 1017 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
AnnaBridge 157:e7ca05fa8600 1018 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
AnnaBridge 157:e7ca05fa8600 1019 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
AnnaBridge 157:e7ca05fa8600 1020 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
AnnaBridge 157:e7ca05fa8600 1021 uint32_t RESERVED0[864U];
AnnaBridge 157:e7ca05fa8600 1022 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
AnnaBridge 157:e7ca05fa8600 1023 uint32_t RESERVED1[15U];
AnnaBridge 157:e7ca05fa8600 1024 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
AnnaBridge 157:e7ca05fa8600 1025 uint32_t RESERVED2[15U];
AnnaBridge 157:e7ca05fa8600 1026 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
AnnaBridge 157:e7ca05fa8600 1027 uint32_t RESERVED3[29U];
AnnaBridge 157:e7ca05fa8600 1028 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
AnnaBridge 157:e7ca05fa8600 1029 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
AnnaBridge 157:e7ca05fa8600 1030 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
AnnaBridge 157:e7ca05fa8600 1031 uint32_t RESERVED4[43U];
AnnaBridge 157:e7ca05fa8600 1032 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
AnnaBridge 157:e7ca05fa8600 1033 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
AnnaBridge 157:e7ca05fa8600 1034 uint32_t RESERVED5[6U];
AnnaBridge 157:e7ca05fa8600 1035 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
AnnaBridge 157:e7ca05fa8600 1036 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
AnnaBridge 157:e7ca05fa8600 1037 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
AnnaBridge 157:e7ca05fa8600 1038 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
AnnaBridge 157:e7ca05fa8600 1039 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
AnnaBridge 157:e7ca05fa8600 1040 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
AnnaBridge 157:e7ca05fa8600 1041 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
AnnaBridge 157:e7ca05fa8600 1042 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
AnnaBridge 157:e7ca05fa8600 1043 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
AnnaBridge 157:e7ca05fa8600 1044 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
AnnaBridge 157:e7ca05fa8600 1045 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
AnnaBridge 157:e7ca05fa8600 1046 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
AnnaBridge 157:e7ca05fa8600 1047 } ITM_Type;
AnnaBridge 157:e7ca05fa8600 1048
AnnaBridge 157:e7ca05fa8600 1049 /* ITM Trace Privilege Register Definitions */
AnnaBridge 157:e7ca05fa8600 1050 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
Anna Bridge 169:a7c7b631e539 1051 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
AnnaBridge 157:e7ca05fa8600 1052
AnnaBridge 157:e7ca05fa8600 1053 /* ITM Trace Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 1054 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
AnnaBridge 157:e7ca05fa8600 1055 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
AnnaBridge 157:e7ca05fa8600 1056
AnnaBridge 157:e7ca05fa8600 1057 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
AnnaBridge 157:e7ca05fa8600 1058 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
AnnaBridge 157:e7ca05fa8600 1059
AnnaBridge 157:e7ca05fa8600 1060 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
AnnaBridge 157:e7ca05fa8600 1061 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
AnnaBridge 157:e7ca05fa8600 1062
AnnaBridge 157:e7ca05fa8600 1063 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
AnnaBridge 157:e7ca05fa8600 1064 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
AnnaBridge 157:e7ca05fa8600 1065
AnnaBridge 157:e7ca05fa8600 1066 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
AnnaBridge 157:e7ca05fa8600 1067 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
AnnaBridge 157:e7ca05fa8600 1068
AnnaBridge 157:e7ca05fa8600 1069 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
AnnaBridge 157:e7ca05fa8600 1070 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
AnnaBridge 157:e7ca05fa8600 1071
AnnaBridge 157:e7ca05fa8600 1072 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
AnnaBridge 157:e7ca05fa8600 1073 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
AnnaBridge 157:e7ca05fa8600 1074
AnnaBridge 157:e7ca05fa8600 1075 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
AnnaBridge 157:e7ca05fa8600 1076 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
AnnaBridge 157:e7ca05fa8600 1077
AnnaBridge 157:e7ca05fa8600 1078 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
AnnaBridge 157:e7ca05fa8600 1079 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
AnnaBridge 157:e7ca05fa8600 1080
AnnaBridge 157:e7ca05fa8600 1081 /* ITM Integration Write Register Definitions */
AnnaBridge 157:e7ca05fa8600 1082 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
AnnaBridge 157:e7ca05fa8600 1083 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
AnnaBridge 157:e7ca05fa8600 1084
AnnaBridge 157:e7ca05fa8600 1085 /* ITM Integration Read Register Definitions */
AnnaBridge 157:e7ca05fa8600 1086 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
AnnaBridge 157:e7ca05fa8600 1087 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
AnnaBridge 157:e7ca05fa8600 1088
AnnaBridge 157:e7ca05fa8600 1089 /* ITM Integration Mode Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 1090 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
AnnaBridge 157:e7ca05fa8600 1091 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
AnnaBridge 157:e7ca05fa8600 1092
AnnaBridge 157:e7ca05fa8600 1093 /* ITM Lock Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 1094 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
AnnaBridge 157:e7ca05fa8600 1095 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
AnnaBridge 157:e7ca05fa8600 1096
AnnaBridge 157:e7ca05fa8600 1097 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
AnnaBridge 157:e7ca05fa8600 1098 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
AnnaBridge 157:e7ca05fa8600 1099
AnnaBridge 157:e7ca05fa8600 1100 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
AnnaBridge 157:e7ca05fa8600 1101 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
AnnaBridge 157:e7ca05fa8600 1102
AnnaBridge 157:e7ca05fa8600 1103 /*@}*/ /* end of group CMSIS_ITM */
AnnaBridge 157:e7ca05fa8600 1104
AnnaBridge 157:e7ca05fa8600 1105
AnnaBridge 157:e7ca05fa8600 1106 /**
AnnaBridge 157:e7ca05fa8600 1107 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 1108 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 157:e7ca05fa8600 1109 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 157:e7ca05fa8600 1110 @{
AnnaBridge 157:e7ca05fa8600 1111 */
AnnaBridge 157:e7ca05fa8600 1112
AnnaBridge 157:e7ca05fa8600 1113 /**
AnnaBridge 157:e7ca05fa8600 1114 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 157:e7ca05fa8600 1115 */
AnnaBridge 157:e7ca05fa8600 1116 typedef struct
AnnaBridge 157:e7ca05fa8600 1117 {
AnnaBridge 157:e7ca05fa8600 1118 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 157:e7ca05fa8600 1119 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
AnnaBridge 157:e7ca05fa8600 1120 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
AnnaBridge 157:e7ca05fa8600 1121 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
AnnaBridge 157:e7ca05fa8600 1122 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
AnnaBridge 157:e7ca05fa8600 1123 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
AnnaBridge 157:e7ca05fa8600 1124 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
AnnaBridge 157:e7ca05fa8600 1125 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 157:e7ca05fa8600 1126 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 157:e7ca05fa8600 1127 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
AnnaBridge 157:e7ca05fa8600 1128 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 157:e7ca05fa8600 1129 uint32_t RESERVED0[1U];
AnnaBridge 157:e7ca05fa8600 1130 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 157:e7ca05fa8600 1131 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
AnnaBridge 157:e7ca05fa8600 1132 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 157:e7ca05fa8600 1133 uint32_t RESERVED1[1U];
AnnaBridge 157:e7ca05fa8600 1134 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 157:e7ca05fa8600 1135 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
AnnaBridge 157:e7ca05fa8600 1136 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 157:e7ca05fa8600 1137 uint32_t RESERVED2[1U];
AnnaBridge 157:e7ca05fa8600 1138 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 157:e7ca05fa8600 1139 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
AnnaBridge 157:e7ca05fa8600 1140 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 157:e7ca05fa8600 1141 uint32_t RESERVED3[981U];
AnnaBridge 157:e7ca05fa8600 1142 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
AnnaBridge 157:e7ca05fa8600 1143 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
AnnaBridge 157:e7ca05fa8600 1144 } DWT_Type;
AnnaBridge 157:e7ca05fa8600 1145
AnnaBridge 157:e7ca05fa8600 1146 /* DWT Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 1147 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 157:e7ca05fa8600 1148 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 157:e7ca05fa8600 1149
AnnaBridge 157:e7ca05fa8600 1150 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 157:e7ca05fa8600 1151 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 157:e7ca05fa8600 1152
AnnaBridge 157:e7ca05fa8600 1153 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 157:e7ca05fa8600 1154 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 157:e7ca05fa8600 1155
AnnaBridge 157:e7ca05fa8600 1156 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 157:e7ca05fa8600 1157 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 157:e7ca05fa8600 1158
AnnaBridge 157:e7ca05fa8600 1159 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 157:e7ca05fa8600 1160 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 157:e7ca05fa8600 1161
AnnaBridge 157:e7ca05fa8600 1162 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
AnnaBridge 157:e7ca05fa8600 1163 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
AnnaBridge 157:e7ca05fa8600 1164
AnnaBridge 157:e7ca05fa8600 1165 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
AnnaBridge 157:e7ca05fa8600 1166 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
AnnaBridge 157:e7ca05fa8600 1167
AnnaBridge 157:e7ca05fa8600 1168 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
AnnaBridge 157:e7ca05fa8600 1169 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
AnnaBridge 157:e7ca05fa8600 1170
AnnaBridge 157:e7ca05fa8600 1171 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
AnnaBridge 157:e7ca05fa8600 1172 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
AnnaBridge 157:e7ca05fa8600 1173
AnnaBridge 157:e7ca05fa8600 1174 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
AnnaBridge 157:e7ca05fa8600 1175 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
AnnaBridge 157:e7ca05fa8600 1176
AnnaBridge 157:e7ca05fa8600 1177 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
AnnaBridge 157:e7ca05fa8600 1178 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
AnnaBridge 157:e7ca05fa8600 1179
AnnaBridge 157:e7ca05fa8600 1180 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
AnnaBridge 157:e7ca05fa8600 1181 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
AnnaBridge 157:e7ca05fa8600 1182
AnnaBridge 157:e7ca05fa8600 1183 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
AnnaBridge 157:e7ca05fa8600 1184 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
AnnaBridge 157:e7ca05fa8600 1185
AnnaBridge 157:e7ca05fa8600 1186 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
AnnaBridge 157:e7ca05fa8600 1187 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
AnnaBridge 157:e7ca05fa8600 1188
AnnaBridge 157:e7ca05fa8600 1189 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
AnnaBridge 157:e7ca05fa8600 1190 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
AnnaBridge 157:e7ca05fa8600 1191
AnnaBridge 157:e7ca05fa8600 1192 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
AnnaBridge 157:e7ca05fa8600 1193 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
AnnaBridge 157:e7ca05fa8600 1194
AnnaBridge 157:e7ca05fa8600 1195 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
AnnaBridge 157:e7ca05fa8600 1196 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
AnnaBridge 157:e7ca05fa8600 1197
AnnaBridge 157:e7ca05fa8600 1198 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
AnnaBridge 157:e7ca05fa8600 1199 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
AnnaBridge 157:e7ca05fa8600 1200
AnnaBridge 157:e7ca05fa8600 1201 /* DWT CPI Count Register Definitions */
AnnaBridge 157:e7ca05fa8600 1202 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
AnnaBridge 157:e7ca05fa8600 1203 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
AnnaBridge 157:e7ca05fa8600 1204
AnnaBridge 157:e7ca05fa8600 1205 /* DWT Exception Overhead Count Register Definitions */
AnnaBridge 157:e7ca05fa8600 1206 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
AnnaBridge 157:e7ca05fa8600 1207 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
AnnaBridge 157:e7ca05fa8600 1208
AnnaBridge 157:e7ca05fa8600 1209 /* DWT Sleep Count Register Definitions */
AnnaBridge 157:e7ca05fa8600 1210 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
AnnaBridge 157:e7ca05fa8600 1211 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
AnnaBridge 157:e7ca05fa8600 1212
AnnaBridge 157:e7ca05fa8600 1213 /* DWT LSU Count Register Definitions */
AnnaBridge 157:e7ca05fa8600 1214 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
AnnaBridge 157:e7ca05fa8600 1215 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
AnnaBridge 157:e7ca05fa8600 1216
AnnaBridge 157:e7ca05fa8600 1217 /* DWT Folded-instruction Count Register Definitions */
AnnaBridge 157:e7ca05fa8600 1218 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
AnnaBridge 157:e7ca05fa8600 1219 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
AnnaBridge 157:e7ca05fa8600 1220
AnnaBridge 157:e7ca05fa8600 1221 /* DWT Comparator Mask Register Definitions */
AnnaBridge 157:e7ca05fa8600 1222 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
AnnaBridge 157:e7ca05fa8600 1223 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
AnnaBridge 157:e7ca05fa8600 1224
AnnaBridge 157:e7ca05fa8600 1225 /* DWT Comparator Function Register Definitions */
AnnaBridge 157:e7ca05fa8600 1226 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 157:e7ca05fa8600 1227 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 157:e7ca05fa8600 1228
AnnaBridge 157:e7ca05fa8600 1229 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
AnnaBridge 157:e7ca05fa8600 1230 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
AnnaBridge 157:e7ca05fa8600 1231
AnnaBridge 157:e7ca05fa8600 1232 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
AnnaBridge 157:e7ca05fa8600 1233 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
AnnaBridge 157:e7ca05fa8600 1234
AnnaBridge 157:e7ca05fa8600 1235 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 157:e7ca05fa8600 1236 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 157:e7ca05fa8600 1237
AnnaBridge 157:e7ca05fa8600 1238 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
AnnaBridge 157:e7ca05fa8600 1239 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
AnnaBridge 157:e7ca05fa8600 1240
AnnaBridge 157:e7ca05fa8600 1241 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
AnnaBridge 157:e7ca05fa8600 1242 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
AnnaBridge 157:e7ca05fa8600 1243
AnnaBridge 157:e7ca05fa8600 1244 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
AnnaBridge 157:e7ca05fa8600 1245 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
AnnaBridge 157:e7ca05fa8600 1246
AnnaBridge 157:e7ca05fa8600 1247 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
AnnaBridge 157:e7ca05fa8600 1248 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
AnnaBridge 157:e7ca05fa8600 1249
AnnaBridge 157:e7ca05fa8600 1250 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
AnnaBridge 157:e7ca05fa8600 1251 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
AnnaBridge 157:e7ca05fa8600 1252
AnnaBridge 157:e7ca05fa8600 1253 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 157:e7ca05fa8600 1254
AnnaBridge 157:e7ca05fa8600 1255
AnnaBridge 157:e7ca05fa8600 1256 /**
AnnaBridge 157:e7ca05fa8600 1257 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 1258 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 157:e7ca05fa8600 1259 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 157:e7ca05fa8600 1260 @{
AnnaBridge 157:e7ca05fa8600 1261 */
AnnaBridge 157:e7ca05fa8600 1262
AnnaBridge 157:e7ca05fa8600 1263 /**
AnnaBridge 157:e7ca05fa8600 1264 \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 157:e7ca05fa8600 1265 */
AnnaBridge 157:e7ca05fa8600 1266 typedef struct
AnnaBridge 157:e7ca05fa8600 1267 {
AnnaBridge 157:e7ca05fa8600 1268 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 157:e7ca05fa8600 1269 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 157:e7ca05fa8600 1270 uint32_t RESERVED0[2U];
AnnaBridge 157:e7ca05fa8600 1271 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 157:e7ca05fa8600 1272 uint32_t RESERVED1[55U];
AnnaBridge 157:e7ca05fa8600 1273 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 157:e7ca05fa8600 1274 uint32_t RESERVED2[131U];
AnnaBridge 157:e7ca05fa8600 1275 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 157:e7ca05fa8600 1276 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 157:e7ca05fa8600 1277 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 157:e7ca05fa8600 1278 uint32_t RESERVED3[759U];
AnnaBridge 157:e7ca05fa8600 1279 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 157:e7ca05fa8600 1280 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 157:e7ca05fa8600 1281 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 157:e7ca05fa8600 1282 uint32_t RESERVED4[1U];
AnnaBridge 157:e7ca05fa8600 1283 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 157:e7ca05fa8600 1284 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 157:e7ca05fa8600 1285 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 157:e7ca05fa8600 1286 uint32_t RESERVED5[39U];
AnnaBridge 157:e7ca05fa8600 1287 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 157:e7ca05fa8600 1288 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 157:e7ca05fa8600 1289 uint32_t RESERVED7[8U];
AnnaBridge 157:e7ca05fa8600 1290 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 157:e7ca05fa8600 1291 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
AnnaBridge 157:e7ca05fa8600 1292 } TPI_Type;
AnnaBridge 157:e7ca05fa8600 1293
AnnaBridge 157:e7ca05fa8600 1294 /* TPI Asynchronous Clock Prescaler Register Definitions */
Anna Bridge 169:a7c7b631e539 1295 #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
Anna Bridge 169:a7c7b631e539 1296 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
Anna Bridge 169:a7c7b631e539 1297
Anna Bridge 169:a7c7b631e539 1298 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
Anna Bridge 169:a7c7b631e539 1299 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
AnnaBridge 157:e7ca05fa8600 1300
AnnaBridge 157:e7ca05fa8600 1301 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 157:e7ca05fa8600 1302 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
AnnaBridge 157:e7ca05fa8600 1303 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 157:e7ca05fa8600 1304
AnnaBridge 157:e7ca05fa8600 1305 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 1306 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 157:e7ca05fa8600 1307 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 157:e7ca05fa8600 1308
AnnaBridge 157:e7ca05fa8600 1309 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
AnnaBridge 157:e7ca05fa8600 1310 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 157:e7ca05fa8600 1311
AnnaBridge 157:e7ca05fa8600 1312 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
AnnaBridge 157:e7ca05fa8600 1313 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 157:e7ca05fa8600 1314
AnnaBridge 157:e7ca05fa8600 1315 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
AnnaBridge 157:e7ca05fa8600 1316 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 157:e7ca05fa8600 1317
AnnaBridge 157:e7ca05fa8600 1318 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 1319 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
AnnaBridge 157:e7ca05fa8600 1320 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 157:e7ca05fa8600 1321
AnnaBridge 157:e7ca05fa8600 1322 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
AnnaBridge 157:e7ca05fa8600 1323 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 157:e7ca05fa8600 1324
AnnaBridge 157:e7ca05fa8600 1325 /* TPI TRIGGER Register Definitions */
AnnaBridge 157:e7ca05fa8600 1326 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
AnnaBridge 157:e7ca05fa8600 1327 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
AnnaBridge 157:e7ca05fa8600 1328
AnnaBridge 157:e7ca05fa8600 1329 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 157:e7ca05fa8600 1330 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
AnnaBridge 157:e7ca05fa8600 1331 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
AnnaBridge 157:e7ca05fa8600 1332
AnnaBridge 157:e7ca05fa8600 1333 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
AnnaBridge 157:e7ca05fa8600 1334 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
AnnaBridge 157:e7ca05fa8600 1335
AnnaBridge 157:e7ca05fa8600 1336 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
AnnaBridge 157:e7ca05fa8600 1337 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
AnnaBridge 157:e7ca05fa8600 1338
AnnaBridge 157:e7ca05fa8600 1339 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
AnnaBridge 157:e7ca05fa8600 1340 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
AnnaBridge 157:e7ca05fa8600 1341
AnnaBridge 157:e7ca05fa8600 1342 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
AnnaBridge 157:e7ca05fa8600 1343 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
AnnaBridge 157:e7ca05fa8600 1344
AnnaBridge 157:e7ca05fa8600 1345 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
AnnaBridge 157:e7ca05fa8600 1346 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
AnnaBridge 157:e7ca05fa8600 1347
AnnaBridge 157:e7ca05fa8600 1348 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
AnnaBridge 157:e7ca05fa8600 1349 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
AnnaBridge 157:e7ca05fa8600 1350
AnnaBridge 157:e7ca05fa8600 1351 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 157:e7ca05fa8600 1352 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
AnnaBridge 157:e7ca05fa8600 1353 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
AnnaBridge 157:e7ca05fa8600 1354
AnnaBridge 157:e7ca05fa8600 1355 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 157:e7ca05fa8600 1356 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
AnnaBridge 157:e7ca05fa8600 1357 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
AnnaBridge 157:e7ca05fa8600 1358
AnnaBridge 157:e7ca05fa8600 1359 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
AnnaBridge 157:e7ca05fa8600 1360 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
AnnaBridge 157:e7ca05fa8600 1361
AnnaBridge 157:e7ca05fa8600 1362 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
AnnaBridge 157:e7ca05fa8600 1363 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
AnnaBridge 157:e7ca05fa8600 1364
AnnaBridge 157:e7ca05fa8600 1365 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
AnnaBridge 157:e7ca05fa8600 1366 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
AnnaBridge 157:e7ca05fa8600 1367
AnnaBridge 157:e7ca05fa8600 1368 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
AnnaBridge 157:e7ca05fa8600 1369 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
AnnaBridge 157:e7ca05fa8600 1370
AnnaBridge 157:e7ca05fa8600 1371 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
AnnaBridge 157:e7ca05fa8600 1372 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
AnnaBridge 157:e7ca05fa8600 1373
AnnaBridge 157:e7ca05fa8600 1374 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
AnnaBridge 157:e7ca05fa8600 1375 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
AnnaBridge 157:e7ca05fa8600 1376
AnnaBridge 157:e7ca05fa8600 1377 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 157:e7ca05fa8600 1378 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
AnnaBridge 157:e7ca05fa8600 1379 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
AnnaBridge 157:e7ca05fa8600 1380
AnnaBridge 157:e7ca05fa8600 1381 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 1382 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
AnnaBridge 157:e7ca05fa8600 1383 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
AnnaBridge 157:e7ca05fa8600 1384
AnnaBridge 157:e7ca05fa8600 1385 /* TPI DEVID Register Definitions */
AnnaBridge 157:e7ca05fa8600 1386 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 157:e7ca05fa8600 1387 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 157:e7ca05fa8600 1388
AnnaBridge 157:e7ca05fa8600 1389 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 157:e7ca05fa8600 1390 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 157:e7ca05fa8600 1391
AnnaBridge 157:e7ca05fa8600 1392 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 157:e7ca05fa8600 1393 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 157:e7ca05fa8600 1394
AnnaBridge 157:e7ca05fa8600 1395 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
AnnaBridge 157:e7ca05fa8600 1396 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
AnnaBridge 157:e7ca05fa8600 1397
AnnaBridge 157:e7ca05fa8600 1398 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
AnnaBridge 157:e7ca05fa8600 1399 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
AnnaBridge 157:e7ca05fa8600 1400
AnnaBridge 157:e7ca05fa8600 1401 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 157:e7ca05fa8600 1402 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
AnnaBridge 157:e7ca05fa8600 1403
AnnaBridge 157:e7ca05fa8600 1404 /* TPI DEVTYPE Register Definitions */
AnnaBridge 157:e7ca05fa8600 1405 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 157:e7ca05fa8600 1406 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 157:e7ca05fa8600 1407
AnnaBridge 157:e7ca05fa8600 1408 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 157:e7ca05fa8600 1409 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 157:e7ca05fa8600 1410
AnnaBridge 157:e7ca05fa8600 1411 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 157:e7ca05fa8600 1412
AnnaBridge 157:e7ca05fa8600 1413
AnnaBridge 157:e7ca05fa8600 1414 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 1415 /**
AnnaBridge 157:e7ca05fa8600 1416 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 1417 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 157:e7ca05fa8600 1418 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 157:e7ca05fa8600 1419 @{
AnnaBridge 157:e7ca05fa8600 1420 */
AnnaBridge 157:e7ca05fa8600 1421
AnnaBridge 157:e7ca05fa8600 1422 /**
AnnaBridge 157:e7ca05fa8600 1423 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 157:e7ca05fa8600 1424 */
AnnaBridge 157:e7ca05fa8600 1425 typedef struct
AnnaBridge 157:e7ca05fa8600 1426 {
AnnaBridge 157:e7ca05fa8600 1427 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 157:e7ca05fa8600 1428 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 157:e7ca05fa8600 1429 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 157:e7ca05fa8600 1430 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 157:e7ca05fa8600 1431 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 157:e7ca05fa8600 1432 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
AnnaBridge 157:e7ca05fa8600 1433 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
AnnaBridge 157:e7ca05fa8600 1434 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
AnnaBridge 157:e7ca05fa8600 1435 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
AnnaBridge 157:e7ca05fa8600 1436 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
AnnaBridge 157:e7ca05fa8600 1437 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
AnnaBridge 157:e7ca05fa8600 1438 } MPU_Type;
AnnaBridge 157:e7ca05fa8600 1439
Anna Bridge 160:5571c4ff569f 1440 #define MPU_TYPE_RALIASES 4U
Anna Bridge 160:5571c4ff569f 1441
AnnaBridge 157:e7ca05fa8600 1442 /* MPU Type Register Definitions */
AnnaBridge 157:e7ca05fa8600 1443 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 157:e7ca05fa8600 1444 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 157:e7ca05fa8600 1445
AnnaBridge 157:e7ca05fa8600 1446 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 157:e7ca05fa8600 1447 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 157:e7ca05fa8600 1448
AnnaBridge 157:e7ca05fa8600 1449 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 157:e7ca05fa8600 1450 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 157:e7ca05fa8600 1451
AnnaBridge 157:e7ca05fa8600 1452 /* MPU Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 1453 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 157:e7ca05fa8600 1454 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 157:e7ca05fa8600 1455
AnnaBridge 157:e7ca05fa8600 1456 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 157:e7ca05fa8600 1457 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 157:e7ca05fa8600 1458
AnnaBridge 157:e7ca05fa8600 1459 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 157:e7ca05fa8600 1460 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 157:e7ca05fa8600 1461
AnnaBridge 157:e7ca05fa8600 1462 /* MPU Region Number Register Definitions */
AnnaBridge 157:e7ca05fa8600 1463 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 157:e7ca05fa8600 1464 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 157:e7ca05fa8600 1465
AnnaBridge 157:e7ca05fa8600 1466 /* MPU Region Base Address Register Definitions */
AnnaBridge 157:e7ca05fa8600 1467 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
AnnaBridge 157:e7ca05fa8600 1468 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 157:e7ca05fa8600 1469
AnnaBridge 157:e7ca05fa8600 1470 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
AnnaBridge 157:e7ca05fa8600 1471 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 157:e7ca05fa8600 1472
AnnaBridge 157:e7ca05fa8600 1473 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
AnnaBridge 157:e7ca05fa8600 1474 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 157:e7ca05fa8600 1475
AnnaBridge 157:e7ca05fa8600 1476 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 157:e7ca05fa8600 1477 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 157:e7ca05fa8600 1478 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 157:e7ca05fa8600 1479
AnnaBridge 157:e7ca05fa8600 1480 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 157:e7ca05fa8600 1481 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 157:e7ca05fa8600 1482
AnnaBridge 157:e7ca05fa8600 1483 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 157:e7ca05fa8600 1484 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 157:e7ca05fa8600 1485
AnnaBridge 157:e7ca05fa8600 1486 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 157:e7ca05fa8600 1487 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 157:e7ca05fa8600 1488
AnnaBridge 157:e7ca05fa8600 1489 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 157:e7ca05fa8600 1490 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 157:e7ca05fa8600 1491
AnnaBridge 157:e7ca05fa8600 1492 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 157:e7ca05fa8600 1493 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 157:e7ca05fa8600 1494
AnnaBridge 157:e7ca05fa8600 1495 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 157:e7ca05fa8600 1496 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 157:e7ca05fa8600 1497
AnnaBridge 157:e7ca05fa8600 1498 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 157:e7ca05fa8600 1499 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 157:e7ca05fa8600 1500
AnnaBridge 157:e7ca05fa8600 1501 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
AnnaBridge 157:e7ca05fa8600 1502 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 157:e7ca05fa8600 1503
AnnaBridge 157:e7ca05fa8600 1504 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
AnnaBridge 157:e7ca05fa8600 1505 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 157:e7ca05fa8600 1506
AnnaBridge 157:e7ca05fa8600 1507 /*@} end of group CMSIS_MPU */
AnnaBridge 157:e7ca05fa8600 1508 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
AnnaBridge 157:e7ca05fa8600 1509
AnnaBridge 157:e7ca05fa8600 1510
AnnaBridge 157:e7ca05fa8600 1511 /**
AnnaBridge 157:e7ca05fa8600 1512 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 1513 \defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge 157:e7ca05fa8600 1514 \brief Type definitions for the Floating Point Unit (FPU)
AnnaBridge 157:e7ca05fa8600 1515 @{
AnnaBridge 157:e7ca05fa8600 1516 */
AnnaBridge 157:e7ca05fa8600 1517
AnnaBridge 157:e7ca05fa8600 1518 /**
AnnaBridge 157:e7ca05fa8600 1519 \brief Structure type to access the Floating Point Unit (FPU).
AnnaBridge 157:e7ca05fa8600 1520 */
AnnaBridge 157:e7ca05fa8600 1521 typedef struct
AnnaBridge 157:e7ca05fa8600 1522 {
AnnaBridge 157:e7ca05fa8600 1523 uint32_t RESERVED0[1U];
AnnaBridge 157:e7ca05fa8600 1524 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
AnnaBridge 157:e7ca05fa8600 1525 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
AnnaBridge 157:e7ca05fa8600 1526 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
AnnaBridge 157:e7ca05fa8600 1527 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
AnnaBridge 157:e7ca05fa8600 1528 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
AnnaBridge 157:e7ca05fa8600 1529 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
AnnaBridge 157:e7ca05fa8600 1530 } FPU_Type;
AnnaBridge 157:e7ca05fa8600 1531
AnnaBridge 157:e7ca05fa8600 1532 /* Floating-Point Context Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 1533 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
AnnaBridge 157:e7ca05fa8600 1534 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
AnnaBridge 157:e7ca05fa8600 1535
AnnaBridge 157:e7ca05fa8600 1536 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
AnnaBridge 157:e7ca05fa8600 1537 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
AnnaBridge 157:e7ca05fa8600 1538
AnnaBridge 157:e7ca05fa8600 1539 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
AnnaBridge 157:e7ca05fa8600 1540 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
AnnaBridge 157:e7ca05fa8600 1541
AnnaBridge 157:e7ca05fa8600 1542 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
AnnaBridge 157:e7ca05fa8600 1543 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
AnnaBridge 157:e7ca05fa8600 1544
AnnaBridge 157:e7ca05fa8600 1545 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
AnnaBridge 157:e7ca05fa8600 1546 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
AnnaBridge 157:e7ca05fa8600 1547
AnnaBridge 157:e7ca05fa8600 1548 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
AnnaBridge 157:e7ca05fa8600 1549 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
AnnaBridge 157:e7ca05fa8600 1550
AnnaBridge 157:e7ca05fa8600 1551 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
AnnaBridge 157:e7ca05fa8600 1552 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
AnnaBridge 157:e7ca05fa8600 1553
AnnaBridge 157:e7ca05fa8600 1554 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
AnnaBridge 157:e7ca05fa8600 1555 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
AnnaBridge 157:e7ca05fa8600 1556
AnnaBridge 157:e7ca05fa8600 1557 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
AnnaBridge 157:e7ca05fa8600 1558 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
AnnaBridge 157:e7ca05fa8600 1559
AnnaBridge 157:e7ca05fa8600 1560 /* Floating-Point Context Address Register Definitions */
AnnaBridge 157:e7ca05fa8600 1561 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
AnnaBridge 157:e7ca05fa8600 1562 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
AnnaBridge 157:e7ca05fa8600 1563
AnnaBridge 157:e7ca05fa8600 1564 /* Floating-Point Default Status Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 1565 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
AnnaBridge 157:e7ca05fa8600 1566 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
AnnaBridge 157:e7ca05fa8600 1567
AnnaBridge 157:e7ca05fa8600 1568 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
AnnaBridge 157:e7ca05fa8600 1569 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
AnnaBridge 157:e7ca05fa8600 1570
AnnaBridge 157:e7ca05fa8600 1571 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
AnnaBridge 157:e7ca05fa8600 1572 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
AnnaBridge 157:e7ca05fa8600 1573
AnnaBridge 157:e7ca05fa8600 1574 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
AnnaBridge 157:e7ca05fa8600 1575 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
AnnaBridge 157:e7ca05fa8600 1576
AnnaBridge 157:e7ca05fa8600 1577 /* Media and FP Feature Register 0 Definitions */
AnnaBridge 157:e7ca05fa8600 1578 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
AnnaBridge 157:e7ca05fa8600 1579 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
AnnaBridge 157:e7ca05fa8600 1580
AnnaBridge 157:e7ca05fa8600 1581 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
AnnaBridge 157:e7ca05fa8600 1582 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
AnnaBridge 157:e7ca05fa8600 1583
AnnaBridge 157:e7ca05fa8600 1584 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
AnnaBridge 157:e7ca05fa8600 1585 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
AnnaBridge 157:e7ca05fa8600 1586
AnnaBridge 157:e7ca05fa8600 1587 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
AnnaBridge 157:e7ca05fa8600 1588 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
AnnaBridge 157:e7ca05fa8600 1589
AnnaBridge 157:e7ca05fa8600 1590 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
AnnaBridge 157:e7ca05fa8600 1591 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
AnnaBridge 157:e7ca05fa8600 1592
AnnaBridge 157:e7ca05fa8600 1593 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
AnnaBridge 157:e7ca05fa8600 1594 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
AnnaBridge 157:e7ca05fa8600 1595
AnnaBridge 157:e7ca05fa8600 1596 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
AnnaBridge 157:e7ca05fa8600 1597 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
AnnaBridge 157:e7ca05fa8600 1598
AnnaBridge 157:e7ca05fa8600 1599 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
AnnaBridge 157:e7ca05fa8600 1600 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
AnnaBridge 157:e7ca05fa8600 1601
AnnaBridge 157:e7ca05fa8600 1602 /* Media and FP Feature Register 1 Definitions */
AnnaBridge 157:e7ca05fa8600 1603 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
AnnaBridge 157:e7ca05fa8600 1604 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
AnnaBridge 157:e7ca05fa8600 1605
AnnaBridge 157:e7ca05fa8600 1606 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
AnnaBridge 157:e7ca05fa8600 1607 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
AnnaBridge 157:e7ca05fa8600 1608
AnnaBridge 157:e7ca05fa8600 1609 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
AnnaBridge 157:e7ca05fa8600 1610 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
AnnaBridge 157:e7ca05fa8600 1611
AnnaBridge 157:e7ca05fa8600 1612 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
AnnaBridge 157:e7ca05fa8600 1613 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
AnnaBridge 157:e7ca05fa8600 1614
AnnaBridge 157:e7ca05fa8600 1615 /* Media and FP Feature Register 2 Definitions */
AnnaBridge 157:e7ca05fa8600 1616
AnnaBridge 157:e7ca05fa8600 1617 /*@} end of group CMSIS_FPU */
AnnaBridge 157:e7ca05fa8600 1618
AnnaBridge 157:e7ca05fa8600 1619
AnnaBridge 157:e7ca05fa8600 1620 /**
AnnaBridge 157:e7ca05fa8600 1621 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 1622 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 157:e7ca05fa8600 1623 \brief Type definitions for the Core Debug Registers
AnnaBridge 157:e7ca05fa8600 1624 @{
AnnaBridge 157:e7ca05fa8600 1625 */
AnnaBridge 157:e7ca05fa8600 1626
AnnaBridge 157:e7ca05fa8600 1627 /**
AnnaBridge 157:e7ca05fa8600 1628 \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 157:e7ca05fa8600 1629 */
AnnaBridge 157:e7ca05fa8600 1630 typedef struct
AnnaBridge 157:e7ca05fa8600 1631 {
AnnaBridge 157:e7ca05fa8600 1632 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 157:e7ca05fa8600 1633 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 157:e7ca05fa8600 1634 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 157:e7ca05fa8600 1635 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 157:e7ca05fa8600 1636 } CoreDebug_Type;
AnnaBridge 157:e7ca05fa8600 1637
AnnaBridge 157:e7ca05fa8600 1638 /* Debug Halting Control and Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 1639 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 157:e7ca05fa8600 1640 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 157:e7ca05fa8600 1641
AnnaBridge 157:e7ca05fa8600 1642 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 157:e7ca05fa8600 1643 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 157:e7ca05fa8600 1644
AnnaBridge 157:e7ca05fa8600 1645 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 157:e7ca05fa8600 1646 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 157:e7ca05fa8600 1647
AnnaBridge 157:e7ca05fa8600 1648 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 157:e7ca05fa8600 1649 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 157:e7ca05fa8600 1650
AnnaBridge 157:e7ca05fa8600 1651 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 157:e7ca05fa8600 1652 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 157:e7ca05fa8600 1653
AnnaBridge 157:e7ca05fa8600 1654 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 157:e7ca05fa8600 1655 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 157:e7ca05fa8600 1656
AnnaBridge 157:e7ca05fa8600 1657 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 157:e7ca05fa8600 1658 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 157:e7ca05fa8600 1659
AnnaBridge 157:e7ca05fa8600 1660 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
AnnaBridge 157:e7ca05fa8600 1661 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
AnnaBridge 157:e7ca05fa8600 1662
AnnaBridge 157:e7ca05fa8600 1663 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 157:e7ca05fa8600 1664 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 157:e7ca05fa8600 1665
AnnaBridge 157:e7ca05fa8600 1666 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 157:e7ca05fa8600 1667 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 157:e7ca05fa8600 1668
AnnaBridge 157:e7ca05fa8600 1669 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 157:e7ca05fa8600 1670 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 157:e7ca05fa8600 1671
AnnaBridge 157:e7ca05fa8600 1672 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 157:e7ca05fa8600 1673 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 157:e7ca05fa8600 1674
AnnaBridge 157:e7ca05fa8600 1675 /* Debug Core Register Selector Register Definitions */
AnnaBridge 157:e7ca05fa8600 1676 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 157:e7ca05fa8600 1677 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 157:e7ca05fa8600 1678
AnnaBridge 157:e7ca05fa8600 1679 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 157:e7ca05fa8600 1680 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 157:e7ca05fa8600 1681
AnnaBridge 157:e7ca05fa8600 1682 /* Debug Exception and Monitor Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 1683 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
AnnaBridge 157:e7ca05fa8600 1684 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
AnnaBridge 157:e7ca05fa8600 1685
AnnaBridge 157:e7ca05fa8600 1686 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
AnnaBridge 157:e7ca05fa8600 1687 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
AnnaBridge 157:e7ca05fa8600 1688
AnnaBridge 157:e7ca05fa8600 1689 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
AnnaBridge 157:e7ca05fa8600 1690 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
AnnaBridge 157:e7ca05fa8600 1691
AnnaBridge 157:e7ca05fa8600 1692 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
AnnaBridge 157:e7ca05fa8600 1693 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
AnnaBridge 157:e7ca05fa8600 1694
AnnaBridge 157:e7ca05fa8600 1695 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
AnnaBridge 157:e7ca05fa8600 1696 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
AnnaBridge 157:e7ca05fa8600 1697
AnnaBridge 157:e7ca05fa8600 1698 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 157:e7ca05fa8600 1699 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 157:e7ca05fa8600 1700
AnnaBridge 157:e7ca05fa8600 1701 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
AnnaBridge 157:e7ca05fa8600 1702 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
AnnaBridge 157:e7ca05fa8600 1703
AnnaBridge 157:e7ca05fa8600 1704 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
AnnaBridge 157:e7ca05fa8600 1705 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
AnnaBridge 157:e7ca05fa8600 1706
AnnaBridge 157:e7ca05fa8600 1707 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
AnnaBridge 157:e7ca05fa8600 1708 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
AnnaBridge 157:e7ca05fa8600 1709
AnnaBridge 157:e7ca05fa8600 1710 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
AnnaBridge 157:e7ca05fa8600 1711 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
AnnaBridge 157:e7ca05fa8600 1712
AnnaBridge 157:e7ca05fa8600 1713 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
AnnaBridge 157:e7ca05fa8600 1714 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
AnnaBridge 157:e7ca05fa8600 1715
AnnaBridge 157:e7ca05fa8600 1716 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
AnnaBridge 157:e7ca05fa8600 1717 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
AnnaBridge 157:e7ca05fa8600 1718
AnnaBridge 157:e7ca05fa8600 1719 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 157:e7ca05fa8600 1720 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 157:e7ca05fa8600 1721
AnnaBridge 157:e7ca05fa8600 1722 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 157:e7ca05fa8600 1723
AnnaBridge 157:e7ca05fa8600 1724
AnnaBridge 157:e7ca05fa8600 1725 /**
AnnaBridge 157:e7ca05fa8600 1726 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 1727 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 157:e7ca05fa8600 1728 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 157:e7ca05fa8600 1729 @{
AnnaBridge 157:e7ca05fa8600 1730 */
AnnaBridge 157:e7ca05fa8600 1731
AnnaBridge 157:e7ca05fa8600 1732 /**
AnnaBridge 157:e7ca05fa8600 1733 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 157:e7ca05fa8600 1734 \param[in] field Name of the register bit field.
AnnaBridge 157:e7ca05fa8600 1735 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 157:e7ca05fa8600 1736 \return Masked and shifted value.
AnnaBridge 157:e7ca05fa8600 1737 */
AnnaBridge 157:e7ca05fa8600 1738 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 157:e7ca05fa8600 1739
AnnaBridge 157:e7ca05fa8600 1740 /**
AnnaBridge 157:e7ca05fa8600 1741 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 157:e7ca05fa8600 1742 \param[in] field Name of the register bit field.
AnnaBridge 157:e7ca05fa8600 1743 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 157:e7ca05fa8600 1744 \return Masked and shifted bit field value.
AnnaBridge 157:e7ca05fa8600 1745 */
AnnaBridge 157:e7ca05fa8600 1746 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 157:e7ca05fa8600 1747
AnnaBridge 157:e7ca05fa8600 1748 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 157:e7ca05fa8600 1749
AnnaBridge 157:e7ca05fa8600 1750
AnnaBridge 157:e7ca05fa8600 1751 /**
AnnaBridge 157:e7ca05fa8600 1752 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 1753 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 157:e7ca05fa8600 1754 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 157:e7ca05fa8600 1755 @{
AnnaBridge 157:e7ca05fa8600 1756 */
AnnaBridge 157:e7ca05fa8600 1757
AnnaBridge 157:e7ca05fa8600 1758 /* Memory mapping of Core Hardware */
AnnaBridge 157:e7ca05fa8600 1759 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 157:e7ca05fa8600 1760 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
AnnaBridge 157:e7ca05fa8600 1761 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 157:e7ca05fa8600 1762 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 157:e7ca05fa8600 1763 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 157:e7ca05fa8600 1764 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 157:e7ca05fa8600 1765 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 157:e7ca05fa8600 1766 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 157:e7ca05fa8600 1767
AnnaBridge 157:e7ca05fa8600 1768 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 157:e7ca05fa8600 1769 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 157:e7ca05fa8600 1770 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 157:e7ca05fa8600 1771 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 157:e7ca05fa8600 1772 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
AnnaBridge 157:e7ca05fa8600 1773 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 157:e7ca05fa8600 1774 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 157:e7ca05fa8600 1775 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
AnnaBridge 157:e7ca05fa8600 1776
AnnaBridge 157:e7ca05fa8600 1777 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 1778 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 157:e7ca05fa8600 1779 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 157:e7ca05fa8600 1780 #endif
AnnaBridge 157:e7ca05fa8600 1781
AnnaBridge 157:e7ca05fa8600 1782 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
AnnaBridge 157:e7ca05fa8600 1783 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
AnnaBridge 157:e7ca05fa8600 1784
AnnaBridge 157:e7ca05fa8600 1785 /*@} */
AnnaBridge 157:e7ca05fa8600 1786
AnnaBridge 157:e7ca05fa8600 1787
AnnaBridge 157:e7ca05fa8600 1788
AnnaBridge 157:e7ca05fa8600 1789 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 1790 * Hardware Abstraction Layer
AnnaBridge 157:e7ca05fa8600 1791 Core Function Interface contains:
AnnaBridge 157:e7ca05fa8600 1792 - Core NVIC Functions
AnnaBridge 157:e7ca05fa8600 1793 - Core SysTick Functions
AnnaBridge 157:e7ca05fa8600 1794 - Core Debug Functions
AnnaBridge 157:e7ca05fa8600 1795 - Core Register Access Functions
AnnaBridge 157:e7ca05fa8600 1796 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 1797 /**
AnnaBridge 157:e7ca05fa8600 1798 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 157:e7ca05fa8600 1799 */
AnnaBridge 157:e7ca05fa8600 1800
AnnaBridge 157:e7ca05fa8600 1801
AnnaBridge 157:e7ca05fa8600 1802
AnnaBridge 157:e7ca05fa8600 1803 /* ########################## NVIC functions #################################### */
AnnaBridge 157:e7ca05fa8600 1804 /**
AnnaBridge 157:e7ca05fa8600 1805 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 1806 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 157:e7ca05fa8600 1807 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 157:e7ca05fa8600 1808 @{
AnnaBridge 157:e7ca05fa8600 1809 */
AnnaBridge 157:e7ca05fa8600 1810
AnnaBridge 157:e7ca05fa8600 1811 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 157:e7ca05fa8600 1812 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 1813 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 157:e7ca05fa8600 1814 #endif
AnnaBridge 157:e7ca05fa8600 1815 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 1816 #else
AnnaBridge 157:e7ca05fa8600 1817 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge 157:e7ca05fa8600 1818 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge 157:e7ca05fa8600 1819 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 157:e7ca05fa8600 1820 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 157:e7ca05fa8600 1821 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 157:e7ca05fa8600 1822 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 157:e7ca05fa8600 1823 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 157:e7ca05fa8600 1824 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 157:e7ca05fa8600 1825 #define NVIC_GetActive __NVIC_GetActive
AnnaBridge 157:e7ca05fa8600 1826 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 157:e7ca05fa8600 1827 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 157:e7ca05fa8600 1828 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 157:e7ca05fa8600 1829 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 157:e7ca05fa8600 1830
AnnaBridge 157:e7ca05fa8600 1831 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 157:e7ca05fa8600 1832 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 1833 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 157:e7ca05fa8600 1834 #endif
AnnaBridge 157:e7ca05fa8600 1835 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 1836 #else
AnnaBridge 157:e7ca05fa8600 1837 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 157:e7ca05fa8600 1838 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 157:e7ca05fa8600 1839 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 157:e7ca05fa8600 1840
AnnaBridge 157:e7ca05fa8600 1841 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 157:e7ca05fa8600 1842
AnnaBridge 157:e7ca05fa8600 1843
AnnaBridge 157:e7ca05fa8600 1844
AnnaBridge 157:e7ca05fa8600 1845 /**
AnnaBridge 157:e7ca05fa8600 1846 \brief Set Priority Grouping
AnnaBridge 157:e7ca05fa8600 1847 \details Sets the priority grouping field using the required unlock sequence.
AnnaBridge 157:e7ca05fa8600 1848 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge 157:e7ca05fa8600 1849 Only values from 0..7 are used.
AnnaBridge 157:e7ca05fa8600 1850 In case of a conflict between priority grouping and available
AnnaBridge 157:e7ca05fa8600 1851 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 157:e7ca05fa8600 1852 \param [in] PriorityGroup Priority grouping field.
AnnaBridge 157:e7ca05fa8600 1853 */
AnnaBridge 157:e7ca05fa8600 1854 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge 157:e7ca05fa8600 1855 {
AnnaBridge 157:e7ca05fa8600 1856 uint32_t reg_value;
AnnaBridge 157:e7ca05fa8600 1857 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 157:e7ca05fa8600 1858
AnnaBridge 157:e7ca05fa8600 1859 reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge 157:e7ca05fa8600 1860 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge 157:e7ca05fa8600 1861 reg_value = (reg_value |
AnnaBridge 157:e7ca05fa8600 1862 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 169:a7c7b631e539 1863 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
AnnaBridge 157:e7ca05fa8600 1864 SCB->AIRCR = reg_value;
AnnaBridge 157:e7ca05fa8600 1865 }
AnnaBridge 157:e7ca05fa8600 1866
AnnaBridge 157:e7ca05fa8600 1867
AnnaBridge 157:e7ca05fa8600 1868 /**
AnnaBridge 157:e7ca05fa8600 1869 \brief Get Priority Grouping
AnnaBridge 157:e7ca05fa8600 1870 \details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge 157:e7ca05fa8600 1871 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge 157:e7ca05fa8600 1872 */
AnnaBridge 157:e7ca05fa8600 1873 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge 157:e7ca05fa8600 1874 {
AnnaBridge 157:e7ca05fa8600 1875 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge 157:e7ca05fa8600 1876 }
AnnaBridge 157:e7ca05fa8600 1877
AnnaBridge 157:e7ca05fa8600 1878
AnnaBridge 157:e7ca05fa8600 1879 /**
AnnaBridge 157:e7ca05fa8600 1880 \brief Enable Interrupt
AnnaBridge 157:e7ca05fa8600 1881 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 1882 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1883 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1884 */
AnnaBridge 157:e7ca05fa8600 1885 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1886 {
AnnaBridge 157:e7ca05fa8600 1887 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1888 {
Anna Bridge 169:a7c7b631e539 1889 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 1890 }
AnnaBridge 157:e7ca05fa8600 1891 }
AnnaBridge 157:e7ca05fa8600 1892
AnnaBridge 157:e7ca05fa8600 1893
AnnaBridge 157:e7ca05fa8600 1894 /**
AnnaBridge 157:e7ca05fa8600 1895 \brief Get Interrupt Enable status
AnnaBridge 157:e7ca05fa8600 1896 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 1897 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1898 \return 0 Interrupt is not enabled.
AnnaBridge 157:e7ca05fa8600 1899 \return 1 Interrupt is enabled.
AnnaBridge 157:e7ca05fa8600 1900 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1901 */
AnnaBridge 157:e7ca05fa8600 1902 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1903 {
AnnaBridge 157:e7ca05fa8600 1904 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1905 {
Anna Bridge 169:a7c7b631e539 1906 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 1907 }
AnnaBridge 157:e7ca05fa8600 1908 else
AnnaBridge 157:e7ca05fa8600 1909 {
AnnaBridge 157:e7ca05fa8600 1910 return(0U);
AnnaBridge 157:e7ca05fa8600 1911 }
AnnaBridge 157:e7ca05fa8600 1912 }
AnnaBridge 157:e7ca05fa8600 1913
AnnaBridge 157:e7ca05fa8600 1914
AnnaBridge 157:e7ca05fa8600 1915 /**
AnnaBridge 157:e7ca05fa8600 1916 \brief Disable Interrupt
AnnaBridge 157:e7ca05fa8600 1917 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 1918 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1919 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1920 */
AnnaBridge 157:e7ca05fa8600 1921 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1922 {
AnnaBridge 157:e7ca05fa8600 1923 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1924 {
Anna Bridge 169:a7c7b631e539 1925 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 1926 __DSB();
AnnaBridge 157:e7ca05fa8600 1927 __ISB();
AnnaBridge 157:e7ca05fa8600 1928 }
AnnaBridge 157:e7ca05fa8600 1929 }
AnnaBridge 157:e7ca05fa8600 1930
AnnaBridge 157:e7ca05fa8600 1931
AnnaBridge 157:e7ca05fa8600 1932 /**
AnnaBridge 157:e7ca05fa8600 1933 \brief Get Pending Interrupt
AnnaBridge 157:e7ca05fa8600 1934 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 157:e7ca05fa8600 1935 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1936 \return 0 Interrupt status is not pending.
AnnaBridge 157:e7ca05fa8600 1937 \return 1 Interrupt status is pending.
AnnaBridge 157:e7ca05fa8600 1938 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1939 */
AnnaBridge 157:e7ca05fa8600 1940 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1941 {
AnnaBridge 157:e7ca05fa8600 1942 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1943 {
Anna Bridge 169:a7c7b631e539 1944 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 1945 }
AnnaBridge 157:e7ca05fa8600 1946 else
AnnaBridge 157:e7ca05fa8600 1947 {
AnnaBridge 157:e7ca05fa8600 1948 return(0U);
AnnaBridge 157:e7ca05fa8600 1949 }
AnnaBridge 157:e7ca05fa8600 1950 }
AnnaBridge 157:e7ca05fa8600 1951
AnnaBridge 157:e7ca05fa8600 1952
AnnaBridge 157:e7ca05fa8600 1953 /**
AnnaBridge 157:e7ca05fa8600 1954 \brief Set Pending Interrupt
AnnaBridge 157:e7ca05fa8600 1955 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 157:e7ca05fa8600 1956 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1957 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1958 */
AnnaBridge 157:e7ca05fa8600 1959 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1960 {
AnnaBridge 157:e7ca05fa8600 1961 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1962 {
Anna Bridge 169:a7c7b631e539 1963 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 1964 }
AnnaBridge 157:e7ca05fa8600 1965 }
AnnaBridge 157:e7ca05fa8600 1966
AnnaBridge 157:e7ca05fa8600 1967
AnnaBridge 157:e7ca05fa8600 1968 /**
AnnaBridge 157:e7ca05fa8600 1969 \brief Clear Pending Interrupt
AnnaBridge 157:e7ca05fa8600 1970 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 157:e7ca05fa8600 1971 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1972 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1973 */
AnnaBridge 157:e7ca05fa8600 1974 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1975 {
AnnaBridge 157:e7ca05fa8600 1976 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1977 {
Anna Bridge 169:a7c7b631e539 1978 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 1979 }
AnnaBridge 157:e7ca05fa8600 1980 }
AnnaBridge 157:e7ca05fa8600 1981
AnnaBridge 157:e7ca05fa8600 1982
AnnaBridge 157:e7ca05fa8600 1983 /**
AnnaBridge 157:e7ca05fa8600 1984 \brief Get Active Interrupt
AnnaBridge 157:e7ca05fa8600 1985 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge 157:e7ca05fa8600 1986 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1987 \return 0 Interrupt status is not active.
AnnaBridge 157:e7ca05fa8600 1988 \return 1 Interrupt status is active.
AnnaBridge 157:e7ca05fa8600 1989 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1990 */
AnnaBridge 157:e7ca05fa8600 1991 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1992 {
AnnaBridge 157:e7ca05fa8600 1993 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1994 {
Anna Bridge 169:a7c7b631e539 1995 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 1996 }
AnnaBridge 157:e7ca05fa8600 1997 else
AnnaBridge 157:e7ca05fa8600 1998 {
AnnaBridge 157:e7ca05fa8600 1999 return(0U);
AnnaBridge 157:e7ca05fa8600 2000 }
AnnaBridge 157:e7ca05fa8600 2001 }
AnnaBridge 157:e7ca05fa8600 2002
AnnaBridge 157:e7ca05fa8600 2003
AnnaBridge 157:e7ca05fa8600 2004 /**
AnnaBridge 157:e7ca05fa8600 2005 \brief Set Interrupt Priority
AnnaBridge 157:e7ca05fa8600 2006 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 157:e7ca05fa8600 2007 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 2008 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 2009 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 2010 \param [in] priority Priority to set.
AnnaBridge 157:e7ca05fa8600 2011 \note The priority cannot be set for every processor exception.
AnnaBridge 157:e7ca05fa8600 2012 */
AnnaBridge 157:e7ca05fa8600 2013 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 157:e7ca05fa8600 2014 {
AnnaBridge 157:e7ca05fa8600 2015 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 2016 {
Anna Bridge 169:a7c7b631e539 2017 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 157:e7ca05fa8600 2018 }
AnnaBridge 157:e7ca05fa8600 2019 else
AnnaBridge 157:e7ca05fa8600 2020 {
Anna Bridge 169:a7c7b631e539 2021 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 157:e7ca05fa8600 2022 }
AnnaBridge 157:e7ca05fa8600 2023 }
AnnaBridge 157:e7ca05fa8600 2024
AnnaBridge 157:e7ca05fa8600 2025
AnnaBridge 157:e7ca05fa8600 2026 /**
AnnaBridge 157:e7ca05fa8600 2027 \brief Get Interrupt Priority
AnnaBridge 157:e7ca05fa8600 2028 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 157:e7ca05fa8600 2029 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 2030 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 2031 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 2032 \return Interrupt Priority.
AnnaBridge 157:e7ca05fa8600 2033 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 157:e7ca05fa8600 2034 */
AnnaBridge 157:e7ca05fa8600 2035 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 2036 {
AnnaBridge 157:e7ca05fa8600 2037
AnnaBridge 157:e7ca05fa8600 2038 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 2039 {
Anna Bridge 169:a7c7b631e539 2040 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 157:e7ca05fa8600 2041 }
AnnaBridge 157:e7ca05fa8600 2042 else
AnnaBridge 157:e7ca05fa8600 2043 {
Anna Bridge 169:a7c7b631e539 2044 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 157:e7ca05fa8600 2045 }
AnnaBridge 157:e7ca05fa8600 2046 }
AnnaBridge 157:e7ca05fa8600 2047
AnnaBridge 157:e7ca05fa8600 2048
AnnaBridge 157:e7ca05fa8600 2049 /**
AnnaBridge 157:e7ca05fa8600 2050 \brief Encode Priority
AnnaBridge 157:e7ca05fa8600 2051 \details Encodes the priority for an interrupt with the given priority group,
AnnaBridge 157:e7ca05fa8600 2052 preemptive priority value, and subpriority value.
AnnaBridge 157:e7ca05fa8600 2053 In case of a conflict between priority grouping and available
AnnaBridge 157:e7ca05fa8600 2054 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 157:e7ca05fa8600 2055 \param [in] PriorityGroup Used priority group.
AnnaBridge 157:e7ca05fa8600 2056 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 157:e7ca05fa8600 2057 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 157:e7ca05fa8600 2058 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge 157:e7ca05fa8600 2059 */
AnnaBridge 157:e7ca05fa8600 2060 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 157:e7ca05fa8600 2061 {
AnnaBridge 157:e7ca05fa8600 2062 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 157:e7ca05fa8600 2063 uint32_t PreemptPriorityBits;
AnnaBridge 157:e7ca05fa8600 2064 uint32_t SubPriorityBits;
AnnaBridge 157:e7ca05fa8600 2065
AnnaBridge 157:e7ca05fa8600 2066 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 157:e7ca05fa8600 2067 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 157:e7ca05fa8600 2068
AnnaBridge 157:e7ca05fa8600 2069 return (
AnnaBridge 157:e7ca05fa8600 2070 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
AnnaBridge 157:e7ca05fa8600 2071 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge 157:e7ca05fa8600 2072 );
AnnaBridge 157:e7ca05fa8600 2073 }
AnnaBridge 157:e7ca05fa8600 2074
AnnaBridge 157:e7ca05fa8600 2075
AnnaBridge 157:e7ca05fa8600 2076 /**
AnnaBridge 157:e7ca05fa8600 2077 \brief Decode Priority
AnnaBridge 157:e7ca05fa8600 2078 \details Decodes an interrupt priority value with a given priority group to
AnnaBridge 157:e7ca05fa8600 2079 preemptive priority value and subpriority value.
AnnaBridge 157:e7ca05fa8600 2080 In case of a conflict between priority grouping and available
AnnaBridge 157:e7ca05fa8600 2081 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 157:e7ca05fa8600 2082 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 157:e7ca05fa8600 2083 \param [in] PriorityGroup Used priority group.
AnnaBridge 157:e7ca05fa8600 2084 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 157:e7ca05fa8600 2085 \param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge 157:e7ca05fa8600 2086 */
AnnaBridge 157:e7ca05fa8600 2087 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge 157:e7ca05fa8600 2088 {
AnnaBridge 157:e7ca05fa8600 2089 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 157:e7ca05fa8600 2090 uint32_t PreemptPriorityBits;
AnnaBridge 157:e7ca05fa8600 2091 uint32_t SubPriorityBits;
AnnaBridge 157:e7ca05fa8600 2092
AnnaBridge 157:e7ca05fa8600 2093 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 157:e7ca05fa8600 2094 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 157:e7ca05fa8600 2095
AnnaBridge 157:e7ca05fa8600 2096 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge 157:e7ca05fa8600 2097 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge 157:e7ca05fa8600 2098 }
AnnaBridge 157:e7ca05fa8600 2099
AnnaBridge 157:e7ca05fa8600 2100
AnnaBridge 157:e7ca05fa8600 2101 /**
AnnaBridge 157:e7ca05fa8600 2102 \brief Set Interrupt Vector
AnnaBridge 157:e7ca05fa8600 2103 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 157:e7ca05fa8600 2104 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 2105 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 2106 VTOR must been relocated to SRAM before.
AnnaBridge 157:e7ca05fa8600 2107 \param [in] IRQn Interrupt number
AnnaBridge 157:e7ca05fa8600 2108 \param [in] vector Address of interrupt handler function
AnnaBridge 157:e7ca05fa8600 2109 */
AnnaBridge 157:e7ca05fa8600 2110 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 157:e7ca05fa8600 2111 {
AnnaBridge 157:e7ca05fa8600 2112 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 157:e7ca05fa8600 2113 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 157:e7ca05fa8600 2114 }
AnnaBridge 157:e7ca05fa8600 2115
AnnaBridge 157:e7ca05fa8600 2116
AnnaBridge 157:e7ca05fa8600 2117 /**
AnnaBridge 157:e7ca05fa8600 2118 \brief Get Interrupt Vector
AnnaBridge 157:e7ca05fa8600 2119 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 157:e7ca05fa8600 2120 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 2121 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 2122 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 2123 \return Address of interrupt handler function
AnnaBridge 157:e7ca05fa8600 2124 */
AnnaBridge 157:e7ca05fa8600 2125 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 2126 {
AnnaBridge 157:e7ca05fa8600 2127 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 157:e7ca05fa8600 2128 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 157:e7ca05fa8600 2129 }
AnnaBridge 157:e7ca05fa8600 2130
AnnaBridge 157:e7ca05fa8600 2131
AnnaBridge 157:e7ca05fa8600 2132 /**
AnnaBridge 157:e7ca05fa8600 2133 \brief System Reset
AnnaBridge 157:e7ca05fa8600 2134 \details Initiates a system reset request to reset the MCU.
AnnaBridge 157:e7ca05fa8600 2135 */
AnnaBridge 157:e7ca05fa8600 2136 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 157:e7ca05fa8600 2137 {
AnnaBridge 157:e7ca05fa8600 2138 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 157:e7ca05fa8600 2139 buffered write are completed before reset */
AnnaBridge 157:e7ca05fa8600 2140 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 157:e7ca05fa8600 2141 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
AnnaBridge 157:e7ca05fa8600 2142 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge 157:e7ca05fa8600 2143 __DSB(); /* Ensure completion of memory access */
AnnaBridge 157:e7ca05fa8600 2144
AnnaBridge 157:e7ca05fa8600 2145 for(;;) /* wait until reset */
AnnaBridge 157:e7ca05fa8600 2146 {
AnnaBridge 157:e7ca05fa8600 2147 __NOP();
AnnaBridge 157:e7ca05fa8600 2148 }
AnnaBridge 157:e7ca05fa8600 2149 }
AnnaBridge 157:e7ca05fa8600 2150
AnnaBridge 157:e7ca05fa8600 2151 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 157:e7ca05fa8600 2152
Anna Bridge 160:5571c4ff569f 2153 /* ########################## MPU functions #################################### */
Anna Bridge 160:5571c4ff569f 2154
Anna Bridge 160:5571c4ff569f 2155 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 2156
Anna Bridge 160:5571c4ff569f 2157 #include "mpu_armv7.h"
Anna Bridge 160:5571c4ff569f 2158
Anna Bridge 160:5571c4ff569f 2159 #endif
AnnaBridge 157:e7ca05fa8600 2160
AnnaBridge 157:e7ca05fa8600 2161 /* ########################## FPU functions #################################### */
AnnaBridge 157:e7ca05fa8600 2162 /**
AnnaBridge 157:e7ca05fa8600 2163 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 2164 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 157:e7ca05fa8600 2165 \brief Function that provides FPU type.
AnnaBridge 157:e7ca05fa8600 2166 @{
AnnaBridge 157:e7ca05fa8600 2167 */
AnnaBridge 157:e7ca05fa8600 2168
AnnaBridge 157:e7ca05fa8600 2169 /**
AnnaBridge 157:e7ca05fa8600 2170 \brief get FPU type
AnnaBridge 157:e7ca05fa8600 2171 \details returns the FPU type
AnnaBridge 157:e7ca05fa8600 2172 \returns
AnnaBridge 157:e7ca05fa8600 2173 - \b 0: No FPU
AnnaBridge 157:e7ca05fa8600 2174 - \b 1: Single precision FPU
AnnaBridge 157:e7ca05fa8600 2175 - \b 2: Double + Single precision FPU
AnnaBridge 157:e7ca05fa8600 2176 */
AnnaBridge 157:e7ca05fa8600 2177 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 157:e7ca05fa8600 2178 {
AnnaBridge 157:e7ca05fa8600 2179 uint32_t mvfr0;
AnnaBridge 157:e7ca05fa8600 2180
AnnaBridge 157:e7ca05fa8600 2181 mvfr0 = SCB->MVFR0;
AnnaBridge 157:e7ca05fa8600 2182 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
AnnaBridge 157:e7ca05fa8600 2183 {
AnnaBridge 157:e7ca05fa8600 2184 return 2U; /* Double + Single precision FPU */
AnnaBridge 157:e7ca05fa8600 2185 }
AnnaBridge 157:e7ca05fa8600 2186 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge 157:e7ca05fa8600 2187 {
AnnaBridge 157:e7ca05fa8600 2188 return 1U; /* Single precision FPU */
AnnaBridge 157:e7ca05fa8600 2189 }
AnnaBridge 157:e7ca05fa8600 2190 else
AnnaBridge 157:e7ca05fa8600 2191 {
AnnaBridge 157:e7ca05fa8600 2192 return 0U; /* No FPU */
AnnaBridge 157:e7ca05fa8600 2193 }
AnnaBridge 157:e7ca05fa8600 2194 }
AnnaBridge 157:e7ca05fa8600 2195
AnnaBridge 157:e7ca05fa8600 2196
AnnaBridge 157:e7ca05fa8600 2197 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 157:e7ca05fa8600 2198
AnnaBridge 157:e7ca05fa8600 2199
AnnaBridge 157:e7ca05fa8600 2200
AnnaBridge 157:e7ca05fa8600 2201 /* ########################## Cache functions #################################### */
AnnaBridge 157:e7ca05fa8600 2202 /**
AnnaBridge 157:e7ca05fa8600 2203 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 2204 \defgroup CMSIS_Core_CacheFunctions Cache Functions
AnnaBridge 157:e7ca05fa8600 2205 \brief Functions that configure Instruction and Data cache.
AnnaBridge 157:e7ca05fa8600 2206 @{
AnnaBridge 157:e7ca05fa8600 2207 */
AnnaBridge 157:e7ca05fa8600 2208
AnnaBridge 157:e7ca05fa8600 2209 /* Cache Size ID Register Macros */
AnnaBridge 157:e7ca05fa8600 2210 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
AnnaBridge 157:e7ca05fa8600 2211 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
AnnaBridge 157:e7ca05fa8600 2212
AnnaBridge 157:e7ca05fa8600 2213
AnnaBridge 157:e7ca05fa8600 2214 /**
AnnaBridge 157:e7ca05fa8600 2215 \brief Enable I-Cache
AnnaBridge 157:e7ca05fa8600 2216 \details Turns on I-Cache
AnnaBridge 157:e7ca05fa8600 2217 */
AnnaBridge 157:e7ca05fa8600 2218 __STATIC_INLINE void SCB_EnableICache (void)
AnnaBridge 157:e7ca05fa8600 2219 {
AnnaBridge 157:e7ca05fa8600 2220 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 2221 __DSB();
AnnaBridge 157:e7ca05fa8600 2222 __ISB();
AnnaBridge 157:e7ca05fa8600 2223 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
AnnaBridge 157:e7ca05fa8600 2224 __DSB();
AnnaBridge 157:e7ca05fa8600 2225 __ISB();
AnnaBridge 157:e7ca05fa8600 2226 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
AnnaBridge 157:e7ca05fa8600 2227 __DSB();
AnnaBridge 157:e7ca05fa8600 2228 __ISB();
AnnaBridge 157:e7ca05fa8600 2229 #endif
AnnaBridge 157:e7ca05fa8600 2230 }
AnnaBridge 157:e7ca05fa8600 2231
AnnaBridge 157:e7ca05fa8600 2232
AnnaBridge 157:e7ca05fa8600 2233 /**
AnnaBridge 157:e7ca05fa8600 2234 \brief Disable I-Cache
AnnaBridge 157:e7ca05fa8600 2235 \details Turns off I-Cache
AnnaBridge 157:e7ca05fa8600 2236 */
AnnaBridge 157:e7ca05fa8600 2237 __STATIC_INLINE void SCB_DisableICache (void)
AnnaBridge 157:e7ca05fa8600 2238 {
AnnaBridge 157:e7ca05fa8600 2239 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 2240 __DSB();
AnnaBridge 157:e7ca05fa8600 2241 __ISB();
AnnaBridge 157:e7ca05fa8600 2242 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
AnnaBridge 157:e7ca05fa8600 2243 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
AnnaBridge 157:e7ca05fa8600 2244 __DSB();
AnnaBridge 157:e7ca05fa8600 2245 __ISB();
AnnaBridge 157:e7ca05fa8600 2246 #endif
AnnaBridge 157:e7ca05fa8600 2247 }
AnnaBridge 157:e7ca05fa8600 2248
AnnaBridge 157:e7ca05fa8600 2249
AnnaBridge 157:e7ca05fa8600 2250 /**
AnnaBridge 157:e7ca05fa8600 2251 \brief Invalidate I-Cache
AnnaBridge 157:e7ca05fa8600 2252 \details Invalidates I-Cache
AnnaBridge 157:e7ca05fa8600 2253 */
AnnaBridge 157:e7ca05fa8600 2254 __STATIC_INLINE void SCB_InvalidateICache (void)
AnnaBridge 157:e7ca05fa8600 2255 {
AnnaBridge 157:e7ca05fa8600 2256 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 2257 __DSB();
AnnaBridge 157:e7ca05fa8600 2258 __ISB();
AnnaBridge 157:e7ca05fa8600 2259 SCB->ICIALLU = 0UL;
AnnaBridge 157:e7ca05fa8600 2260 __DSB();
AnnaBridge 157:e7ca05fa8600 2261 __ISB();
AnnaBridge 157:e7ca05fa8600 2262 #endif
AnnaBridge 157:e7ca05fa8600 2263 }
AnnaBridge 157:e7ca05fa8600 2264
AnnaBridge 157:e7ca05fa8600 2265
AnnaBridge 157:e7ca05fa8600 2266 /**
AnnaBridge 157:e7ca05fa8600 2267 \brief Enable D-Cache
AnnaBridge 157:e7ca05fa8600 2268 \details Turns on D-Cache
AnnaBridge 157:e7ca05fa8600 2269 */
AnnaBridge 157:e7ca05fa8600 2270 __STATIC_INLINE void SCB_EnableDCache (void)
AnnaBridge 157:e7ca05fa8600 2271 {
AnnaBridge 157:e7ca05fa8600 2272 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 2273 uint32_t ccsidr;
AnnaBridge 157:e7ca05fa8600 2274 uint32_t sets;
AnnaBridge 157:e7ca05fa8600 2275 uint32_t ways;
AnnaBridge 157:e7ca05fa8600 2276
AnnaBridge 157:e7ca05fa8600 2277 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
AnnaBridge 157:e7ca05fa8600 2278 __DSB();
AnnaBridge 157:e7ca05fa8600 2279
AnnaBridge 157:e7ca05fa8600 2280 ccsidr = SCB->CCSIDR;
AnnaBridge 157:e7ca05fa8600 2281
AnnaBridge 157:e7ca05fa8600 2282 /* invalidate D-Cache */
AnnaBridge 157:e7ca05fa8600 2283 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge 157:e7ca05fa8600 2284 do {
AnnaBridge 157:e7ca05fa8600 2285 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge 157:e7ca05fa8600 2286 do {
AnnaBridge 157:e7ca05fa8600 2287 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
AnnaBridge 157:e7ca05fa8600 2288 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
AnnaBridge 157:e7ca05fa8600 2289 #if defined ( __CC_ARM )
AnnaBridge 157:e7ca05fa8600 2290 __schedule_barrier();
AnnaBridge 157:e7ca05fa8600 2291 #endif
AnnaBridge 157:e7ca05fa8600 2292 } while (ways-- != 0U);
AnnaBridge 157:e7ca05fa8600 2293 } while(sets-- != 0U);
AnnaBridge 157:e7ca05fa8600 2294 __DSB();
AnnaBridge 157:e7ca05fa8600 2295
AnnaBridge 157:e7ca05fa8600 2296 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
AnnaBridge 157:e7ca05fa8600 2297
AnnaBridge 157:e7ca05fa8600 2298 __DSB();
AnnaBridge 157:e7ca05fa8600 2299 __ISB();
AnnaBridge 157:e7ca05fa8600 2300 #endif
AnnaBridge 157:e7ca05fa8600 2301 }
AnnaBridge 157:e7ca05fa8600 2302
AnnaBridge 157:e7ca05fa8600 2303
AnnaBridge 157:e7ca05fa8600 2304 /**
AnnaBridge 157:e7ca05fa8600 2305 \brief Disable D-Cache
AnnaBridge 157:e7ca05fa8600 2306 \details Turns off D-Cache
AnnaBridge 157:e7ca05fa8600 2307 */
AnnaBridge 157:e7ca05fa8600 2308 __STATIC_INLINE void SCB_DisableDCache (void)
AnnaBridge 157:e7ca05fa8600 2309 {
AnnaBridge 157:e7ca05fa8600 2310 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 2311 register uint32_t ccsidr;
AnnaBridge 157:e7ca05fa8600 2312 register uint32_t sets;
AnnaBridge 157:e7ca05fa8600 2313 register uint32_t ways;
AnnaBridge 157:e7ca05fa8600 2314
AnnaBridge 157:e7ca05fa8600 2315 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
AnnaBridge 157:e7ca05fa8600 2316 __DSB();
AnnaBridge 157:e7ca05fa8600 2317
AnnaBridge 157:e7ca05fa8600 2318 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
AnnaBridge 157:e7ca05fa8600 2319 __DSB();
AnnaBridge 157:e7ca05fa8600 2320
AnnaBridge 157:e7ca05fa8600 2321 ccsidr = SCB->CCSIDR;
AnnaBridge 157:e7ca05fa8600 2322
AnnaBridge 157:e7ca05fa8600 2323 /* clean & invalidate D-Cache */
AnnaBridge 157:e7ca05fa8600 2324 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge 157:e7ca05fa8600 2325 do {
AnnaBridge 157:e7ca05fa8600 2326 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge 157:e7ca05fa8600 2327 do {
AnnaBridge 157:e7ca05fa8600 2328 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
AnnaBridge 157:e7ca05fa8600 2329 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
AnnaBridge 157:e7ca05fa8600 2330 #if defined ( __CC_ARM )
AnnaBridge 157:e7ca05fa8600 2331 __schedule_barrier();
AnnaBridge 157:e7ca05fa8600 2332 #endif
AnnaBridge 157:e7ca05fa8600 2333 } while (ways-- != 0U);
AnnaBridge 157:e7ca05fa8600 2334 } while(sets-- != 0U);
AnnaBridge 157:e7ca05fa8600 2335
AnnaBridge 157:e7ca05fa8600 2336 __DSB();
AnnaBridge 157:e7ca05fa8600 2337 __ISB();
AnnaBridge 157:e7ca05fa8600 2338 #endif
AnnaBridge 157:e7ca05fa8600 2339 }
AnnaBridge 157:e7ca05fa8600 2340
AnnaBridge 157:e7ca05fa8600 2341
AnnaBridge 157:e7ca05fa8600 2342 /**
AnnaBridge 157:e7ca05fa8600 2343 \brief Invalidate D-Cache
AnnaBridge 157:e7ca05fa8600 2344 \details Invalidates D-Cache
AnnaBridge 157:e7ca05fa8600 2345 */
AnnaBridge 157:e7ca05fa8600 2346 __STATIC_INLINE void SCB_InvalidateDCache (void)
AnnaBridge 157:e7ca05fa8600 2347 {
AnnaBridge 157:e7ca05fa8600 2348 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 2349 uint32_t ccsidr;
AnnaBridge 157:e7ca05fa8600 2350 uint32_t sets;
AnnaBridge 157:e7ca05fa8600 2351 uint32_t ways;
AnnaBridge 157:e7ca05fa8600 2352
AnnaBridge 157:e7ca05fa8600 2353 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
AnnaBridge 157:e7ca05fa8600 2354 __DSB();
AnnaBridge 157:e7ca05fa8600 2355
AnnaBridge 157:e7ca05fa8600 2356 ccsidr = SCB->CCSIDR;
AnnaBridge 157:e7ca05fa8600 2357
AnnaBridge 157:e7ca05fa8600 2358 /* invalidate D-Cache */
AnnaBridge 157:e7ca05fa8600 2359 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge 157:e7ca05fa8600 2360 do {
AnnaBridge 157:e7ca05fa8600 2361 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge 157:e7ca05fa8600 2362 do {
AnnaBridge 157:e7ca05fa8600 2363 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
AnnaBridge 157:e7ca05fa8600 2364 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
AnnaBridge 157:e7ca05fa8600 2365 #if defined ( __CC_ARM )
AnnaBridge 157:e7ca05fa8600 2366 __schedule_barrier();
AnnaBridge 157:e7ca05fa8600 2367 #endif
AnnaBridge 157:e7ca05fa8600 2368 } while (ways-- != 0U);
AnnaBridge 157:e7ca05fa8600 2369 } while(sets-- != 0U);
AnnaBridge 157:e7ca05fa8600 2370
AnnaBridge 157:e7ca05fa8600 2371 __DSB();
AnnaBridge 157:e7ca05fa8600 2372 __ISB();
AnnaBridge 157:e7ca05fa8600 2373 #endif
AnnaBridge 157:e7ca05fa8600 2374 }
AnnaBridge 157:e7ca05fa8600 2375
AnnaBridge 157:e7ca05fa8600 2376
AnnaBridge 157:e7ca05fa8600 2377 /**
AnnaBridge 157:e7ca05fa8600 2378 \brief Clean D-Cache
AnnaBridge 157:e7ca05fa8600 2379 \details Cleans D-Cache
AnnaBridge 157:e7ca05fa8600 2380 */
AnnaBridge 157:e7ca05fa8600 2381 __STATIC_INLINE void SCB_CleanDCache (void)
AnnaBridge 157:e7ca05fa8600 2382 {
AnnaBridge 157:e7ca05fa8600 2383 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 2384 uint32_t ccsidr;
AnnaBridge 157:e7ca05fa8600 2385 uint32_t sets;
AnnaBridge 157:e7ca05fa8600 2386 uint32_t ways;
AnnaBridge 157:e7ca05fa8600 2387
AnnaBridge 157:e7ca05fa8600 2388 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
AnnaBridge 157:e7ca05fa8600 2389 __DSB();
AnnaBridge 157:e7ca05fa8600 2390
AnnaBridge 157:e7ca05fa8600 2391 ccsidr = SCB->CCSIDR;
AnnaBridge 157:e7ca05fa8600 2392
AnnaBridge 157:e7ca05fa8600 2393 /* clean D-Cache */
AnnaBridge 157:e7ca05fa8600 2394 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge 157:e7ca05fa8600 2395 do {
AnnaBridge 157:e7ca05fa8600 2396 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge 157:e7ca05fa8600 2397 do {
AnnaBridge 157:e7ca05fa8600 2398 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
AnnaBridge 157:e7ca05fa8600 2399 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
AnnaBridge 157:e7ca05fa8600 2400 #if defined ( __CC_ARM )
AnnaBridge 157:e7ca05fa8600 2401 __schedule_barrier();
AnnaBridge 157:e7ca05fa8600 2402 #endif
AnnaBridge 157:e7ca05fa8600 2403 } while (ways-- != 0U);
AnnaBridge 157:e7ca05fa8600 2404 } while(sets-- != 0U);
AnnaBridge 157:e7ca05fa8600 2405
AnnaBridge 157:e7ca05fa8600 2406 __DSB();
AnnaBridge 157:e7ca05fa8600 2407 __ISB();
AnnaBridge 157:e7ca05fa8600 2408 #endif
AnnaBridge 157:e7ca05fa8600 2409 }
AnnaBridge 157:e7ca05fa8600 2410
AnnaBridge 157:e7ca05fa8600 2411
AnnaBridge 157:e7ca05fa8600 2412 /**
AnnaBridge 157:e7ca05fa8600 2413 \brief Clean & Invalidate D-Cache
AnnaBridge 157:e7ca05fa8600 2414 \details Cleans and Invalidates D-Cache
AnnaBridge 157:e7ca05fa8600 2415 */
AnnaBridge 157:e7ca05fa8600 2416 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
AnnaBridge 157:e7ca05fa8600 2417 {
AnnaBridge 157:e7ca05fa8600 2418 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 2419 uint32_t ccsidr;
AnnaBridge 157:e7ca05fa8600 2420 uint32_t sets;
AnnaBridge 157:e7ca05fa8600 2421 uint32_t ways;
AnnaBridge 157:e7ca05fa8600 2422
AnnaBridge 157:e7ca05fa8600 2423 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
AnnaBridge 157:e7ca05fa8600 2424 __DSB();
AnnaBridge 157:e7ca05fa8600 2425
AnnaBridge 157:e7ca05fa8600 2426 ccsidr = SCB->CCSIDR;
AnnaBridge 157:e7ca05fa8600 2427
AnnaBridge 157:e7ca05fa8600 2428 /* clean & invalidate D-Cache */
AnnaBridge 157:e7ca05fa8600 2429 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge 157:e7ca05fa8600 2430 do {
AnnaBridge 157:e7ca05fa8600 2431 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge 157:e7ca05fa8600 2432 do {
AnnaBridge 157:e7ca05fa8600 2433 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
AnnaBridge 157:e7ca05fa8600 2434 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
AnnaBridge 157:e7ca05fa8600 2435 #if defined ( __CC_ARM )
AnnaBridge 157:e7ca05fa8600 2436 __schedule_barrier();
AnnaBridge 157:e7ca05fa8600 2437 #endif
AnnaBridge 157:e7ca05fa8600 2438 } while (ways-- != 0U);
AnnaBridge 157:e7ca05fa8600 2439 } while(sets-- != 0U);
AnnaBridge 157:e7ca05fa8600 2440
AnnaBridge 157:e7ca05fa8600 2441 __DSB();
AnnaBridge 157:e7ca05fa8600 2442 __ISB();
AnnaBridge 157:e7ca05fa8600 2443 #endif
AnnaBridge 157:e7ca05fa8600 2444 }
AnnaBridge 157:e7ca05fa8600 2445
AnnaBridge 157:e7ca05fa8600 2446
AnnaBridge 157:e7ca05fa8600 2447 /**
AnnaBridge 157:e7ca05fa8600 2448 \brief D-Cache Invalidate by address
AnnaBridge 157:e7ca05fa8600 2449 \details Invalidates D-Cache for the given address
AnnaBridge 157:e7ca05fa8600 2450 \param[in] addr address (aligned to 32-byte boundary)
AnnaBridge 157:e7ca05fa8600 2451 \param[in] dsize size of memory block (in number of bytes)
AnnaBridge 157:e7ca05fa8600 2452 */
AnnaBridge 157:e7ca05fa8600 2453 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge 157:e7ca05fa8600 2454 {
AnnaBridge 157:e7ca05fa8600 2455 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 2456 int32_t op_size = dsize;
AnnaBridge 157:e7ca05fa8600 2457 uint32_t op_addr = (uint32_t)addr;
AnnaBridge 157:e7ca05fa8600 2458 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
AnnaBridge 157:e7ca05fa8600 2459
AnnaBridge 157:e7ca05fa8600 2460 __DSB();
AnnaBridge 157:e7ca05fa8600 2461
AnnaBridge 157:e7ca05fa8600 2462 while (op_size > 0) {
AnnaBridge 157:e7ca05fa8600 2463 SCB->DCIMVAC = op_addr;
AnnaBridge 157:e7ca05fa8600 2464 op_addr += (uint32_t)linesize;
AnnaBridge 157:e7ca05fa8600 2465 op_size -= linesize;
AnnaBridge 157:e7ca05fa8600 2466 }
AnnaBridge 157:e7ca05fa8600 2467
AnnaBridge 157:e7ca05fa8600 2468 __DSB();
AnnaBridge 157:e7ca05fa8600 2469 __ISB();
AnnaBridge 157:e7ca05fa8600 2470 #endif
AnnaBridge 157:e7ca05fa8600 2471 }
AnnaBridge 157:e7ca05fa8600 2472
AnnaBridge 157:e7ca05fa8600 2473
AnnaBridge 157:e7ca05fa8600 2474 /**
AnnaBridge 157:e7ca05fa8600 2475 \brief D-Cache Clean by address
AnnaBridge 157:e7ca05fa8600 2476 \details Cleans D-Cache for the given address
AnnaBridge 157:e7ca05fa8600 2477 \param[in] addr address (aligned to 32-byte boundary)
AnnaBridge 157:e7ca05fa8600 2478 \param[in] dsize size of memory block (in number of bytes)
AnnaBridge 157:e7ca05fa8600 2479 */
AnnaBridge 157:e7ca05fa8600 2480 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge 157:e7ca05fa8600 2481 {
AnnaBridge 157:e7ca05fa8600 2482 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 2483 int32_t op_size = dsize;
AnnaBridge 157:e7ca05fa8600 2484 uint32_t op_addr = (uint32_t) addr;
AnnaBridge 157:e7ca05fa8600 2485 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
AnnaBridge 157:e7ca05fa8600 2486
AnnaBridge 157:e7ca05fa8600 2487 __DSB();
AnnaBridge 157:e7ca05fa8600 2488
AnnaBridge 157:e7ca05fa8600 2489 while (op_size > 0) {
AnnaBridge 157:e7ca05fa8600 2490 SCB->DCCMVAC = op_addr;
AnnaBridge 157:e7ca05fa8600 2491 op_addr += (uint32_t)linesize;
AnnaBridge 157:e7ca05fa8600 2492 op_size -= linesize;
AnnaBridge 157:e7ca05fa8600 2493 }
AnnaBridge 157:e7ca05fa8600 2494
AnnaBridge 157:e7ca05fa8600 2495 __DSB();
AnnaBridge 157:e7ca05fa8600 2496 __ISB();
AnnaBridge 157:e7ca05fa8600 2497 #endif
AnnaBridge 157:e7ca05fa8600 2498 }
AnnaBridge 157:e7ca05fa8600 2499
AnnaBridge 157:e7ca05fa8600 2500
AnnaBridge 157:e7ca05fa8600 2501 /**
AnnaBridge 157:e7ca05fa8600 2502 \brief D-Cache Clean and Invalidate by address
AnnaBridge 157:e7ca05fa8600 2503 \details Cleans and invalidates D_Cache for the given address
AnnaBridge 157:e7ca05fa8600 2504 \param[in] addr address (aligned to 32-byte boundary)
AnnaBridge 157:e7ca05fa8600 2505 \param[in] dsize size of memory block (in number of bytes)
AnnaBridge 157:e7ca05fa8600 2506 */
AnnaBridge 157:e7ca05fa8600 2507 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge 157:e7ca05fa8600 2508 {
AnnaBridge 157:e7ca05fa8600 2509 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 2510 int32_t op_size = dsize;
AnnaBridge 157:e7ca05fa8600 2511 uint32_t op_addr = (uint32_t) addr;
AnnaBridge 157:e7ca05fa8600 2512 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
AnnaBridge 157:e7ca05fa8600 2513
AnnaBridge 157:e7ca05fa8600 2514 __DSB();
AnnaBridge 157:e7ca05fa8600 2515
AnnaBridge 157:e7ca05fa8600 2516 while (op_size > 0) {
AnnaBridge 157:e7ca05fa8600 2517 SCB->DCCIMVAC = op_addr;
AnnaBridge 157:e7ca05fa8600 2518 op_addr += (uint32_t)linesize;
AnnaBridge 157:e7ca05fa8600 2519 op_size -= linesize;
AnnaBridge 157:e7ca05fa8600 2520 }
AnnaBridge 157:e7ca05fa8600 2521
AnnaBridge 157:e7ca05fa8600 2522 __DSB();
AnnaBridge 157:e7ca05fa8600 2523 __ISB();
AnnaBridge 157:e7ca05fa8600 2524 #endif
AnnaBridge 157:e7ca05fa8600 2525 }
AnnaBridge 157:e7ca05fa8600 2526
AnnaBridge 157:e7ca05fa8600 2527
AnnaBridge 157:e7ca05fa8600 2528 /*@} end of CMSIS_Core_CacheFunctions */
AnnaBridge 157:e7ca05fa8600 2529
AnnaBridge 157:e7ca05fa8600 2530
AnnaBridge 157:e7ca05fa8600 2531
AnnaBridge 157:e7ca05fa8600 2532 /* ################################## SysTick function ############################################ */
AnnaBridge 157:e7ca05fa8600 2533 /**
AnnaBridge 157:e7ca05fa8600 2534 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 2535 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 157:e7ca05fa8600 2536 \brief Functions that configure the System.
AnnaBridge 157:e7ca05fa8600 2537 @{
AnnaBridge 157:e7ca05fa8600 2538 */
AnnaBridge 157:e7ca05fa8600 2539
AnnaBridge 157:e7ca05fa8600 2540 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 157:e7ca05fa8600 2541
AnnaBridge 157:e7ca05fa8600 2542 /**
AnnaBridge 157:e7ca05fa8600 2543 \brief System Tick Configuration
AnnaBridge 157:e7ca05fa8600 2544 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 157:e7ca05fa8600 2545 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 157:e7ca05fa8600 2546 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 157:e7ca05fa8600 2547 \return 0 Function succeeded.
AnnaBridge 157:e7ca05fa8600 2548 \return 1 Function failed.
AnnaBridge 157:e7ca05fa8600 2549 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 157:e7ca05fa8600 2550 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 157:e7ca05fa8600 2551 must contain a vendor-specific implementation of this function.
AnnaBridge 157:e7ca05fa8600 2552 */
AnnaBridge 157:e7ca05fa8600 2553 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 157:e7ca05fa8600 2554 {
AnnaBridge 157:e7ca05fa8600 2555 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 157:e7ca05fa8600 2556 {
AnnaBridge 157:e7ca05fa8600 2557 return (1UL); /* Reload value impossible */
AnnaBridge 157:e7ca05fa8600 2558 }
AnnaBridge 157:e7ca05fa8600 2559
AnnaBridge 157:e7ca05fa8600 2560 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 157:e7ca05fa8600 2561 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 157:e7ca05fa8600 2562 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 157:e7ca05fa8600 2563 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 157:e7ca05fa8600 2564 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 157:e7ca05fa8600 2565 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 157:e7ca05fa8600 2566 return (0UL); /* Function successful */
AnnaBridge 157:e7ca05fa8600 2567 }
AnnaBridge 157:e7ca05fa8600 2568
AnnaBridge 157:e7ca05fa8600 2569 #endif
AnnaBridge 157:e7ca05fa8600 2570
AnnaBridge 157:e7ca05fa8600 2571 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 157:e7ca05fa8600 2572
AnnaBridge 157:e7ca05fa8600 2573
AnnaBridge 157:e7ca05fa8600 2574
AnnaBridge 157:e7ca05fa8600 2575 /* ##################################### Debug In/Output function ########################################### */
AnnaBridge 157:e7ca05fa8600 2576 /**
AnnaBridge 157:e7ca05fa8600 2577 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 2578 \defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge 157:e7ca05fa8600 2579 \brief Functions that access the ITM debug interface.
AnnaBridge 157:e7ca05fa8600 2580 @{
AnnaBridge 157:e7ca05fa8600 2581 */
AnnaBridge 157:e7ca05fa8600 2582
AnnaBridge 157:e7ca05fa8600 2583 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
AnnaBridge 157:e7ca05fa8600 2584 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
AnnaBridge 157:e7ca05fa8600 2585
AnnaBridge 157:e7ca05fa8600 2586
AnnaBridge 157:e7ca05fa8600 2587 /**
AnnaBridge 157:e7ca05fa8600 2588 \brief ITM Send Character
AnnaBridge 157:e7ca05fa8600 2589 \details Transmits a character via the ITM channel 0, and
AnnaBridge 157:e7ca05fa8600 2590 \li Just returns when no debugger is connected that has booked the output.
AnnaBridge 157:e7ca05fa8600 2591 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge 157:e7ca05fa8600 2592 \param [in] ch Character to transmit.
AnnaBridge 157:e7ca05fa8600 2593 \returns Character to transmit.
AnnaBridge 157:e7ca05fa8600 2594 */
AnnaBridge 157:e7ca05fa8600 2595 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge 157:e7ca05fa8600 2596 {
AnnaBridge 157:e7ca05fa8600 2597 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge 157:e7ca05fa8600 2598 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge 157:e7ca05fa8600 2599 {
AnnaBridge 157:e7ca05fa8600 2600 while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge 157:e7ca05fa8600 2601 {
AnnaBridge 157:e7ca05fa8600 2602 __NOP();
AnnaBridge 157:e7ca05fa8600 2603 }
AnnaBridge 157:e7ca05fa8600 2604 ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge 157:e7ca05fa8600 2605 }
AnnaBridge 157:e7ca05fa8600 2606 return (ch);
AnnaBridge 157:e7ca05fa8600 2607 }
AnnaBridge 157:e7ca05fa8600 2608
AnnaBridge 157:e7ca05fa8600 2609
AnnaBridge 157:e7ca05fa8600 2610 /**
AnnaBridge 157:e7ca05fa8600 2611 \brief ITM Receive Character
AnnaBridge 157:e7ca05fa8600 2612 \details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge 157:e7ca05fa8600 2613 \return Received character.
AnnaBridge 157:e7ca05fa8600 2614 \return -1 No character pending.
AnnaBridge 157:e7ca05fa8600 2615 */
AnnaBridge 157:e7ca05fa8600 2616 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge 157:e7ca05fa8600 2617 {
AnnaBridge 157:e7ca05fa8600 2618 int32_t ch = -1; /* no character available */
AnnaBridge 157:e7ca05fa8600 2619
AnnaBridge 157:e7ca05fa8600 2620 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge 157:e7ca05fa8600 2621 {
AnnaBridge 157:e7ca05fa8600 2622 ch = ITM_RxBuffer;
AnnaBridge 157:e7ca05fa8600 2623 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge 157:e7ca05fa8600 2624 }
AnnaBridge 157:e7ca05fa8600 2625
AnnaBridge 157:e7ca05fa8600 2626 return (ch);
AnnaBridge 157:e7ca05fa8600 2627 }
AnnaBridge 157:e7ca05fa8600 2628
AnnaBridge 157:e7ca05fa8600 2629
AnnaBridge 157:e7ca05fa8600 2630 /**
AnnaBridge 157:e7ca05fa8600 2631 \brief ITM Check Character
AnnaBridge 157:e7ca05fa8600 2632 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge 157:e7ca05fa8600 2633 \return 0 No character available.
AnnaBridge 157:e7ca05fa8600 2634 \return 1 Character available.
AnnaBridge 157:e7ca05fa8600 2635 */
AnnaBridge 157:e7ca05fa8600 2636 __STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge 157:e7ca05fa8600 2637 {
AnnaBridge 157:e7ca05fa8600 2638
AnnaBridge 157:e7ca05fa8600 2639 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge 157:e7ca05fa8600 2640 {
AnnaBridge 157:e7ca05fa8600 2641 return (0); /* no character available */
AnnaBridge 157:e7ca05fa8600 2642 }
AnnaBridge 157:e7ca05fa8600 2643 else
AnnaBridge 157:e7ca05fa8600 2644 {
AnnaBridge 157:e7ca05fa8600 2645 return (1); /* character available */
AnnaBridge 157:e7ca05fa8600 2646 }
AnnaBridge 157:e7ca05fa8600 2647 }
AnnaBridge 157:e7ca05fa8600 2648
AnnaBridge 157:e7ca05fa8600 2649 /*@} end of CMSIS_core_DebugFunctions */
AnnaBridge 157:e7ca05fa8600 2650
AnnaBridge 157:e7ca05fa8600 2651
AnnaBridge 157:e7ca05fa8600 2652
AnnaBridge 157:e7ca05fa8600 2653
AnnaBridge 157:e7ca05fa8600 2654 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 2655 }
AnnaBridge 157:e7ca05fa8600 2656 #endif
AnnaBridge 157:e7ca05fa8600 2657
AnnaBridge 157:e7ca05fa8600 2658 #endif /* __CORE_CM7_H_DEPENDANT */
AnnaBridge 157:e7ca05fa8600 2659
AnnaBridge 157:e7ca05fa8600 2660 #endif /* __CMSIS_GENERIC */