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TARGET_NUCLEO_L011K4/core_cm0plus.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:39:34 2018 +0100
Revision:
170:e95d10626187
Parent:
169:a7c7b631e539 
mbed library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**************************************************************************//**
AnnaBridge 157:e7ca05fa8600 2 * @file core_cm0plus.h
AnnaBridge 157:e7ca05fa8600 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.4
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
AnnaBridge 157:e7ca05fa8600 6 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 157:e7ca05fa8600 9 *
AnnaBridge 157:e7ca05fa8600 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 157:e7ca05fa8600 11 *
AnnaBridge 157:e7ca05fa8600 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 157:e7ca05fa8600 13 * not use this file except in compliance with the License.
AnnaBridge 157:e7ca05fa8600 14 * You may obtain a copy of the License at
AnnaBridge 157:e7ca05fa8600 15 *
AnnaBridge 157:e7ca05fa8600 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 157:e7ca05fa8600 17 *
AnnaBridge 157:e7ca05fa8600 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 157:e7ca05fa8600 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 157:e7ca05fa8600 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 157:e7ca05fa8600 21 * See the License for the specific language governing permissions and
AnnaBridge 157:e7ca05fa8600 22 * limitations under the License.
AnnaBridge 157:e7ca05fa8600 23 */
AnnaBridge 157:e7ca05fa8600 24
AnnaBridge 157:e7ca05fa8600 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
AnnaBridge 157:e7ca05fa8600 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 157:e7ca05fa8600 29 #endif
AnnaBridge 157:e7ca05fa8600 30
AnnaBridge 157:e7ca05fa8600 31 #ifndef __CORE_CM0PLUS_H_GENERIC
AnnaBridge 157:e7ca05fa8600 32 #define __CORE_CM0PLUS_H_GENERIC
AnnaBridge 157:e7ca05fa8600 33
AnnaBridge 157:e7ca05fa8600 34 #include <stdint.h>
AnnaBridge 157:e7ca05fa8600 35
AnnaBridge 157:e7ca05fa8600 36 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 37 extern "C" {
AnnaBridge 157:e7ca05fa8600 38 #endif
AnnaBridge 157:e7ca05fa8600 39
AnnaBridge 157:e7ca05fa8600 40 /**
AnnaBridge 157:e7ca05fa8600 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 157:e7ca05fa8600 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 157:e7ca05fa8600 43
AnnaBridge 157:e7ca05fa8600 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 157:e7ca05fa8600 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 157:e7ca05fa8600 46
AnnaBridge 157:e7ca05fa8600 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 157:e7ca05fa8600 48 Unions are used for effective representation of core registers.
AnnaBridge 157:e7ca05fa8600 49
AnnaBridge 157:e7ca05fa8600 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 157:e7ca05fa8600 51 Function-like macros are used to allow more efficient code.
AnnaBridge 157:e7ca05fa8600 52 */
AnnaBridge 157:e7ca05fa8600 53
AnnaBridge 157:e7ca05fa8600 54
AnnaBridge 157:e7ca05fa8600 55 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 56 * CMSIS definitions
AnnaBridge 157:e7ca05fa8600 57 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 58 /**
AnnaBridge 157:e7ca05fa8600 59 \ingroup Cortex-M0+
AnnaBridge 157:e7ca05fa8600 60 @{
AnnaBridge 157:e7ca05fa8600 61 */
AnnaBridge 157:e7ca05fa8600 62
Anna Bridge 160:5571c4ff569f 63 #include "cmsis_version.h"
Anna Bridge 160:5571c4ff569f 64
AnnaBridge 157:e7ca05fa8600 65 /* CMSIS CM0+ definitions */
Anna Bridge 160:5571c4ff569f 66 #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 160:5571c4ff569f 67 #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 157:e7ca05fa8600 68 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 160:5571c4ff569f 69 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 157:e7ca05fa8600 70
AnnaBridge 157:e7ca05fa8600 71 #define __CORTEX_M (0U) /*!< Cortex-M Core */
AnnaBridge 157:e7ca05fa8600 72
AnnaBridge 157:e7ca05fa8600 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 157:e7ca05fa8600 74 This core does not support an FPU at all
AnnaBridge 157:e7ca05fa8600 75 */
AnnaBridge 157:e7ca05fa8600 76 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 77
AnnaBridge 157:e7ca05fa8600 78 #if defined ( __CC_ARM )
AnnaBridge 157:e7ca05fa8600 79 #if defined __TARGET_FPU_VFP
AnnaBridge 157:e7ca05fa8600 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 81 #endif
AnnaBridge 157:e7ca05fa8600 82
AnnaBridge 157:e7ca05fa8600 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 157:e7ca05fa8600 84 #if defined __ARM_PCS_VFP
AnnaBridge 157:e7ca05fa8600 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 86 #endif
AnnaBridge 157:e7ca05fa8600 87
AnnaBridge 157:e7ca05fa8600 88 #elif defined ( __GNUC__ )
AnnaBridge 157:e7ca05fa8600 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 157:e7ca05fa8600 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 91 #endif
AnnaBridge 157:e7ca05fa8600 92
AnnaBridge 157:e7ca05fa8600 93 #elif defined ( __ICCARM__ )
AnnaBridge 157:e7ca05fa8600 94 #if defined __ARMVFP__
AnnaBridge 157:e7ca05fa8600 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 96 #endif
AnnaBridge 157:e7ca05fa8600 97
AnnaBridge 157:e7ca05fa8600 98 #elif defined ( __TI_ARM__ )
AnnaBridge 157:e7ca05fa8600 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 157:e7ca05fa8600 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 101 #endif
AnnaBridge 157:e7ca05fa8600 102
AnnaBridge 157:e7ca05fa8600 103 #elif defined ( __TASKING__ )
AnnaBridge 157:e7ca05fa8600 104 #if defined __FPU_VFP__
AnnaBridge 157:e7ca05fa8600 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 106 #endif
AnnaBridge 157:e7ca05fa8600 107
AnnaBridge 157:e7ca05fa8600 108 #elif defined ( __CSMC__ )
AnnaBridge 157:e7ca05fa8600 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 157:e7ca05fa8600 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 111 #endif
AnnaBridge 157:e7ca05fa8600 112
AnnaBridge 157:e7ca05fa8600 113 #endif
AnnaBridge 157:e7ca05fa8600 114
AnnaBridge 157:e7ca05fa8600 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 157:e7ca05fa8600 116
AnnaBridge 157:e7ca05fa8600 117
AnnaBridge 157:e7ca05fa8600 118 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 119 }
AnnaBridge 157:e7ca05fa8600 120 #endif
AnnaBridge 157:e7ca05fa8600 121
AnnaBridge 157:e7ca05fa8600 122 #endif /* __CORE_CM0PLUS_H_GENERIC */
AnnaBridge 157:e7ca05fa8600 123
AnnaBridge 157:e7ca05fa8600 124 #ifndef __CMSIS_GENERIC
AnnaBridge 157:e7ca05fa8600 125
AnnaBridge 157:e7ca05fa8600 126 #ifndef __CORE_CM0PLUS_H_DEPENDANT
AnnaBridge 157:e7ca05fa8600 127 #define __CORE_CM0PLUS_H_DEPENDANT
AnnaBridge 157:e7ca05fa8600 128
AnnaBridge 157:e7ca05fa8600 129 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 130 extern "C" {
AnnaBridge 157:e7ca05fa8600 131 #endif
AnnaBridge 157:e7ca05fa8600 132
AnnaBridge 157:e7ca05fa8600 133 /* check device defines and use defaults */
AnnaBridge 157:e7ca05fa8600 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 157:e7ca05fa8600 135 #ifndef __CM0PLUS_REV
AnnaBridge 157:e7ca05fa8600 136 #define __CM0PLUS_REV 0x0000U
AnnaBridge 157:e7ca05fa8600 137 #warning "__CM0PLUS_REV not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 138 #endif
AnnaBridge 157:e7ca05fa8600 139
AnnaBridge 157:e7ca05fa8600 140 #ifndef __MPU_PRESENT
AnnaBridge 157:e7ca05fa8600 141 #define __MPU_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 143 #endif
AnnaBridge 157:e7ca05fa8600 144
AnnaBridge 157:e7ca05fa8600 145 #ifndef __VTOR_PRESENT
AnnaBridge 157:e7ca05fa8600 146 #define __VTOR_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 147 #warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 148 #endif
AnnaBridge 157:e7ca05fa8600 149
AnnaBridge 157:e7ca05fa8600 150 #ifndef __NVIC_PRIO_BITS
AnnaBridge 157:e7ca05fa8600 151 #define __NVIC_PRIO_BITS 2U
AnnaBridge 157:e7ca05fa8600 152 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 153 #endif
AnnaBridge 157:e7ca05fa8600 154
AnnaBridge 157:e7ca05fa8600 155 #ifndef __Vendor_SysTickConfig
AnnaBridge 157:e7ca05fa8600 156 #define __Vendor_SysTickConfig 0U
AnnaBridge 157:e7ca05fa8600 157 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 158 #endif
AnnaBridge 157:e7ca05fa8600 159 #endif
AnnaBridge 157:e7ca05fa8600 160
AnnaBridge 157:e7ca05fa8600 161 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 157:e7ca05fa8600 162 /**
AnnaBridge 157:e7ca05fa8600 163 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 157:e7ca05fa8600 164
AnnaBridge 157:e7ca05fa8600 165 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 157:e7ca05fa8600 166 \li to specify the access to peripheral variables.
AnnaBridge 157:e7ca05fa8600 167 \li for automatic generation of peripheral register debug information.
AnnaBridge 157:e7ca05fa8600 168 */
AnnaBridge 157:e7ca05fa8600 169 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 170 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 157:e7ca05fa8600 171 #else
AnnaBridge 157:e7ca05fa8600 172 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 157:e7ca05fa8600 173 #endif
AnnaBridge 157:e7ca05fa8600 174 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 157:e7ca05fa8600 175 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 157:e7ca05fa8600 176
AnnaBridge 157:e7ca05fa8600 177 /* following defines should be used for structure members */
AnnaBridge 157:e7ca05fa8600 178 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 157:e7ca05fa8600 179 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 157:e7ca05fa8600 180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 157:e7ca05fa8600 181
AnnaBridge 157:e7ca05fa8600 182 /*@} end of group Cortex-M0+ */
AnnaBridge 157:e7ca05fa8600 183
AnnaBridge 157:e7ca05fa8600 184
AnnaBridge 157:e7ca05fa8600 185
AnnaBridge 157:e7ca05fa8600 186 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 187 * Register Abstraction
AnnaBridge 157:e7ca05fa8600 188 Core Register contain:
AnnaBridge 157:e7ca05fa8600 189 - Core Register
AnnaBridge 157:e7ca05fa8600 190 - Core NVIC Register
AnnaBridge 157:e7ca05fa8600 191 - Core SCB Register
AnnaBridge 157:e7ca05fa8600 192 - Core SysTick Register
AnnaBridge 157:e7ca05fa8600 193 - Core MPU Register
AnnaBridge 157:e7ca05fa8600 194 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 195 /**
AnnaBridge 157:e7ca05fa8600 196 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 157:e7ca05fa8600 197 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 157:e7ca05fa8600 198 */
AnnaBridge 157:e7ca05fa8600 199
AnnaBridge 157:e7ca05fa8600 200 /**
AnnaBridge 157:e7ca05fa8600 201 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 202 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 157:e7ca05fa8600 203 \brief Core Register type definitions.
AnnaBridge 157:e7ca05fa8600 204 @{
AnnaBridge 157:e7ca05fa8600 205 */
AnnaBridge 157:e7ca05fa8600 206
AnnaBridge 157:e7ca05fa8600 207 /**
AnnaBridge 157:e7ca05fa8600 208 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 157:e7ca05fa8600 209 */
AnnaBridge 157:e7ca05fa8600 210 typedef union
AnnaBridge 157:e7ca05fa8600 211 {
AnnaBridge 157:e7ca05fa8600 212 struct
AnnaBridge 157:e7ca05fa8600 213 {
AnnaBridge 157:e7ca05fa8600 214 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 157:e7ca05fa8600 215 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 157:e7ca05fa8600 216 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 157:e7ca05fa8600 217 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 157:e7ca05fa8600 218 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 157:e7ca05fa8600 219 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 220 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 221 } APSR_Type;
AnnaBridge 157:e7ca05fa8600 222
AnnaBridge 157:e7ca05fa8600 223 /* APSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 224 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 157:e7ca05fa8600 225 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 157:e7ca05fa8600 226
AnnaBridge 157:e7ca05fa8600 227 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 157:e7ca05fa8600 228 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 157:e7ca05fa8600 229
AnnaBridge 157:e7ca05fa8600 230 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 157:e7ca05fa8600 231 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 157:e7ca05fa8600 232
AnnaBridge 157:e7ca05fa8600 233 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 157:e7ca05fa8600 234 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 157:e7ca05fa8600 235
AnnaBridge 157:e7ca05fa8600 236
AnnaBridge 157:e7ca05fa8600 237 /**
AnnaBridge 157:e7ca05fa8600 238 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 157:e7ca05fa8600 239 */
AnnaBridge 157:e7ca05fa8600 240 typedef union
AnnaBridge 157:e7ca05fa8600 241 {
AnnaBridge 157:e7ca05fa8600 242 struct
AnnaBridge 157:e7ca05fa8600 243 {
AnnaBridge 157:e7ca05fa8600 244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 157:e7ca05fa8600 245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 157:e7ca05fa8600 246 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 247 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 248 } IPSR_Type;
AnnaBridge 157:e7ca05fa8600 249
AnnaBridge 157:e7ca05fa8600 250 /* IPSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 157:e7ca05fa8600 252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 157:e7ca05fa8600 253
AnnaBridge 157:e7ca05fa8600 254
AnnaBridge 157:e7ca05fa8600 255 /**
AnnaBridge 157:e7ca05fa8600 256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 157:e7ca05fa8600 257 */
AnnaBridge 157:e7ca05fa8600 258 typedef union
AnnaBridge 157:e7ca05fa8600 259 {
AnnaBridge 157:e7ca05fa8600 260 struct
AnnaBridge 157:e7ca05fa8600 261 {
AnnaBridge 157:e7ca05fa8600 262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 157:e7ca05fa8600 263 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 157:e7ca05fa8600 264 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 157:e7ca05fa8600 265 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 157:e7ca05fa8600 266 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 157:e7ca05fa8600 267 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 157:e7ca05fa8600 268 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 157:e7ca05fa8600 269 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 157:e7ca05fa8600 270 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 271 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 272 } xPSR_Type;
AnnaBridge 157:e7ca05fa8600 273
AnnaBridge 157:e7ca05fa8600 274 /* xPSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 275 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 157:e7ca05fa8600 276 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 157:e7ca05fa8600 277
AnnaBridge 157:e7ca05fa8600 278 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 157:e7ca05fa8600 279 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 157:e7ca05fa8600 280
AnnaBridge 157:e7ca05fa8600 281 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 157:e7ca05fa8600 282 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 157:e7ca05fa8600 283
AnnaBridge 157:e7ca05fa8600 284 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 157:e7ca05fa8600 285 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 157:e7ca05fa8600 286
AnnaBridge 157:e7ca05fa8600 287 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 157:e7ca05fa8600 288 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 157:e7ca05fa8600 289
AnnaBridge 157:e7ca05fa8600 290 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 157:e7ca05fa8600 291 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 157:e7ca05fa8600 292
AnnaBridge 157:e7ca05fa8600 293
AnnaBridge 157:e7ca05fa8600 294 /**
AnnaBridge 157:e7ca05fa8600 295 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 157:e7ca05fa8600 296 */
AnnaBridge 157:e7ca05fa8600 297 typedef union
AnnaBridge 157:e7ca05fa8600 298 {
AnnaBridge 157:e7ca05fa8600 299 struct
AnnaBridge 157:e7ca05fa8600 300 {
AnnaBridge 157:e7ca05fa8600 301 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 157:e7ca05fa8600 302 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 157:e7ca05fa8600 303 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 157:e7ca05fa8600 304 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 305 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 306 } CONTROL_Type;
AnnaBridge 157:e7ca05fa8600 307
AnnaBridge 157:e7ca05fa8600 308 /* CONTROL Register Definitions */
AnnaBridge 157:e7ca05fa8600 309 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 157:e7ca05fa8600 310 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 157:e7ca05fa8600 311
AnnaBridge 157:e7ca05fa8600 312 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 157:e7ca05fa8600 313 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 157:e7ca05fa8600 314
AnnaBridge 157:e7ca05fa8600 315 /*@} end of group CMSIS_CORE */
AnnaBridge 157:e7ca05fa8600 316
AnnaBridge 157:e7ca05fa8600 317
AnnaBridge 157:e7ca05fa8600 318 /**
AnnaBridge 157:e7ca05fa8600 319 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 320 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 157:e7ca05fa8600 321 \brief Type definitions for the NVIC Registers
AnnaBridge 157:e7ca05fa8600 322 @{
AnnaBridge 157:e7ca05fa8600 323 */
AnnaBridge 157:e7ca05fa8600 324
AnnaBridge 157:e7ca05fa8600 325 /**
AnnaBridge 157:e7ca05fa8600 326 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 157:e7ca05fa8600 327 */
AnnaBridge 157:e7ca05fa8600 328 typedef struct
AnnaBridge 157:e7ca05fa8600 329 {
AnnaBridge 157:e7ca05fa8600 330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 157:e7ca05fa8600 331 uint32_t RESERVED0[31U];
AnnaBridge 157:e7ca05fa8600 332 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 157:e7ca05fa8600 333 uint32_t RSERVED1[31U];
AnnaBridge 157:e7ca05fa8600 334 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 157:e7ca05fa8600 335 uint32_t RESERVED2[31U];
AnnaBridge 157:e7ca05fa8600 336 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 157:e7ca05fa8600 337 uint32_t RESERVED3[31U];
AnnaBridge 157:e7ca05fa8600 338 uint32_t RESERVED4[64U];
AnnaBridge 157:e7ca05fa8600 339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 157:e7ca05fa8600 340 } NVIC_Type;
AnnaBridge 157:e7ca05fa8600 341
AnnaBridge 157:e7ca05fa8600 342 /*@} end of group CMSIS_NVIC */
AnnaBridge 157:e7ca05fa8600 343
AnnaBridge 157:e7ca05fa8600 344
AnnaBridge 157:e7ca05fa8600 345 /**
AnnaBridge 157:e7ca05fa8600 346 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 347 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 157:e7ca05fa8600 348 \brief Type definitions for the System Control Block Registers
AnnaBridge 157:e7ca05fa8600 349 @{
AnnaBridge 157:e7ca05fa8600 350 */
AnnaBridge 157:e7ca05fa8600 351
AnnaBridge 157:e7ca05fa8600 352 /**
AnnaBridge 157:e7ca05fa8600 353 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 157:e7ca05fa8600 354 */
AnnaBridge 157:e7ca05fa8600 355 typedef struct
AnnaBridge 157:e7ca05fa8600 356 {
AnnaBridge 157:e7ca05fa8600 357 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 157:e7ca05fa8600 358 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 157:e7ca05fa8600 359 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 360 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 157:e7ca05fa8600 361 #else
AnnaBridge 157:e7ca05fa8600 362 uint32_t RESERVED0;
AnnaBridge 157:e7ca05fa8600 363 #endif
AnnaBridge 157:e7ca05fa8600 364 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 157:e7ca05fa8600 365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 157:e7ca05fa8600 366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 157:e7ca05fa8600 367 uint32_t RESERVED1;
AnnaBridge 157:e7ca05fa8600 368 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 157:e7ca05fa8600 369 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 157:e7ca05fa8600 370 } SCB_Type;
AnnaBridge 157:e7ca05fa8600 371
AnnaBridge 157:e7ca05fa8600 372 /* SCB CPUID Register Definitions */
AnnaBridge 157:e7ca05fa8600 373 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 157:e7ca05fa8600 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 157:e7ca05fa8600 375
AnnaBridge 157:e7ca05fa8600 376 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 157:e7ca05fa8600 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 157:e7ca05fa8600 378
AnnaBridge 157:e7ca05fa8600 379 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 157:e7ca05fa8600 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 157:e7ca05fa8600 381
AnnaBridge 157:e7ca05fa8600 382 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 157:e7ca05fa8600 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 157:e7ca05fa8600 384
AnnaBridge 157:e7ca05fa8600 385 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 157:e7ca05fa8600 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 157:e7ca05fa8600 387
AnnaBridge 157:e7ca05fa8600 388 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 157:e7ca05fa8600 389 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 157:e7ca05fa8600 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 157:e7ca05fa8600 391
AnnaBridge 157:e7ca05fa8600 392 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 157:e7ca05fa8600 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 157:e7ca05fa8600 394
AnnaBridge 157:e7ca05fa8600 395 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 157:e7ca05fa8600 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 157:e7ca05fa8600 397
AnnaBridge 157:e7ca05fa8600 398 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 157:e7ca05fa8600 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 157:e7ca05fa8600 400
AnnaBridge 157:e7ca05fa8600 401 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 157:e7ca05fa8600 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 157:e7ca05fa8600 403
AnnaBridge 157:e7ca05fa8600 404 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 157:e7ca05fa8600 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 157:e7ca05fa8600 406
AnnaBridge 157:e7ca05fa8600 407 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 157:e7ca05fa8600 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 157:e7ca05fa8600 409
AnnaBridge 157:e7ca05fa8600 410 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 157:e7ca05fa8600 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 157:e7ca05fa8600 412
AnnaBridge 157:e7ca05fa8600 413 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 157:e7ca05fa8600 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 157:e7ca05fa8600 415
AnnaBridge 157:e7ca05fa8600 416 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 417 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 157:e7ca05fa8600 418 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 157:e7ca05fa8600 419 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 157:e7ca05fa8600 420 #endif
AnnaBridge 157:e7ca05fa8600 421
AnnaBridge 157:e7ca05fa8600 422 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 423 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 157:e7ca05fa8600 424 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 157:e7ca05fa8600 425
AnnaBridge 157:e7ca05fa8600 426 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 157:e7ca05fa8600 427 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 157:e7ca05fa8600 428
AnnaBridge 157:e7ca05fa8600 429 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 157:e7ca05fa8600 430 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 157:e7ca05fa8600 431
AnnaBridge 157:e7ca05fa8600 432 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 157:e7ca05fa8600 433 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 157:e7ca05fa8600 434
AnnaBridge 157:e7ca05fa8600 435 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 157:e7ca05fa8600 436 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 157:e7ca05fa8600 437
AnnaBridge 157:e7ca05fa8600 438 /* SCB System Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 439 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 157:e7ca05fa8600 440 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 157:e7ca05fa8600 441
AnnaBridge 157:e7ca05fa8600 442 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 157:e7ca05fa8600 443 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 157:e7ca05fa8600 444
AnnaBridge 157:e7ca05fa8600 445 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 157:e7ca05fa8600 446 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 157:e7ca05fa8600 447
AnnaBridge 157:e7ca05fa8600 448 /* SCB Configuration Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 449 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 157:e7ca05fa8600 450 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 157:e7ca05fa8600 451
AnnaBridge 157:e7ca05fa8600 452 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 157:e7ca05fa8600 453 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 157:e7ca05fa8600 454
AnnaBridge 157:e7ca05fa8600 455 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 157:e7ca05fa8600 456 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 157:e7ca05fa8600 457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 157:e7ca05fa8600 458
AnnaBridge 157:e7ca05fa8600 459 /*@} end of group CMSIS_SCB */
AnnaBridge 157:e7ca05fa8600 460
AnnaBridge 157:e7ca05fa8600 461
AnnaBridge 157:e7ca05fa8600 462 /**
AnnaBridge 157:e7ca05fa8600 463 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 464 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 157:e7ca05fa8600 465 \brief Type definitions for the System Timer Registers.
AnnaBridge 157:e7ca05fa8600 466 @{
AnnaBridge 157:e7ca05fa8600 467 */
AnnaBridge 157:e7ca05fa8600 468
AnnaBridge 157:e7ca05fa8600 469 /**
AnnaBridge 157:e7ca05fa8600 470 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 157:e7ca05fa8600 471 */
AnnaBridge 157:e7ca05fa8600 472 typedef struct
AnnaBridge 157:e7ca05fa8600 473 {
AnnaBridge 157:e7ca05fa8600 474 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 157:e7ca05fa8600 475 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 157:e7ca05fa8600 476 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 157:e7ca05fa8600 477 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 157:e7ca05fa8600 478 } SysTick_Type;
AnnaBridge 157:e7ca05fa8600 479
AnnaBridge 157:e7ca05fa8600 480 /* SysTick Control / Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 481 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 157:e7ca05fa8600 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 157:e7ca05fa8600 483
AnnaBridge 157:e7ca05fa8600 484 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 157:e7ca05fa8600 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 157:e7ca05fa8600 486
AnnaBridge 157:e7ca05fa8600 487 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 157:e7ca05fa8600 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 157:e7ca05fa8600 489
AnnaBridge 157:e7ca05fa8600 490 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 157:e7ca05fa8600 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 157:e7ca05fa8600 492
AnnaBridge 157:e7ca05fa8600 493 /* SysTick Reload Register Definitions */
AnnaBridge 157:e7ca05fa8600 494 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 157:e7ca05fa8600 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 157:e7ca05fa8600 496
AnnaBridge 157:e7ca05fa8600 497 /* SysTick Current Register Definitions */
AnnaBridge 157:e7ca05fa8600 498 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 157:e7ca05fa8600 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 157:e7ca05fa8600 500
AnnaBridge 157:e7ca05fa8600 501 /* SysTick Calibration Register Definitions */
AnnaBridge 157:e7ca05fa8600 502 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 157:e7ca05fa8600 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 157:e7ca05fa8600 504
AnnaBridge 157:e7ca05fa8600 505 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 157:e7ca05fa8600 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 157:e7ca05fa8600 507
AnnaBridge 157:e7ca05fa8600 508 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 157:e7ca05fa8600 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 157:e7ca05fa8600 510
AnnaBridge 157:e7ca05fa8600 511 /*@} end of group CMSIS_SysTick */
AnnaBridge 157:e7ca05fa8600 512
AnnaBridge 157:e7ca05fa8600 513 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 514 /**
AnnaBridge 157:e7ca05fa8600 515 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 516 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 157:e7ca05fa8600 517 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 157:e7ca05fa8600 518 @{
AnnaBridge 157:e7ca05fa8600 519 */
AnnaBridge 157:e7ca05fa8600 520
AnnaBridge 157:e7ca05fa8600 521 /**
AnnaBridge 157:e7ca05fa8600 522 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 157:e7ca05fa8600 523 */
AnnaBridge 157:e7ca05fa8600 524 typedef struct
AnnaBridge 157:e7ca05fa8600 525 {
AnnaBridge 157:e7ca05fa8600 526 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 157:e7ca05fa8600 527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 157:e7ca05fa8600 528 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 157:e7ca05fa8600 529 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 157:e7ca05fa8600 530 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 157:e7ca05fa8600 531 } MPU_Type;
AnnaBridge 157:e7ca05fa8600 532
Anna Bridge 160:5571c4ff569f 533 #define MPU_TYPE_RALIASES 1U
Anna Bridge 160:5571c4ff569f 534
AnnaBridge 157:e7ca05fa8600 535 /* MPU Type Register Definitions */
AnnaBridge 157:e7ca05fa8600 536 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 157:e7ca05fa8600 537 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 157:e7ca05fa8600 538
AnnaBridge 157:e7ca05fa8600 539 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 157:e7ca05fa8600 540 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 157:e7ca05fa8600 541
AnnaBridge 157:e7ca05fa8600 542 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 157:e7ca05fa8600 543 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 157:e7ca05fa8600 544
AnnaBridge 157:e7ca05fa8600 545 /* MPU Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 546 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 157:e7ca05fa8600 547 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 157:e7ca05fa8600 548
AnnaBridge 157:e7ca05fa8600 549 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 157:e7ca05fa8600 550 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 157:e7ca05fa8600 551
AnnaBridge 157:e7ca05fa8600 552 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 157:e7ca05fa8600 553 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 157:e7ca05fa8600 554
AnnaBridge 157:e7ca05fa8600 555 /* MPU Region Number Register Definitions */
AnnaBridge 157:e7ca05fa8600 556 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 157:e7ca05fa8600 557 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 157:e7ca05fa8600 558
AnnaBridge 157:e7ca05fa8600 559 /* MPU Region Base Address Register Definitions */
AnnaBridge 157:e7ca05fa8600 560 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
AnnaBridge 157:e7ca05fa8600 561 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 157:e7ca05fa8600 562
AnnaBridge 157:e7ca05fa8600 563 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
AnnaBridge 157:e7ca05fa8600 564 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 157:e7ca05fa8600 565
AnnaBridge 157:e7ca05fa8600 566 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
AnnaBridge 157:e7ca05fa8600 567 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 157:e7ca05fa8600 568
AnnaBridge 157:e7ca05fa8600 569 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 157:e7ca05fa8600 570 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 157:e7ca05fa8600 571 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 157:e7ca05fa8600 572
AnnaBridge 157:e7ca05fa8600 573 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 157:e7ca05fa8600 574 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 157:e7ca05fa8600 575
AnnaBridge 157:e7ca05fa8600 576 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 157:e7ca05fa8600 577 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 157:e7ca05fa8600 578
AnnaBridge 157:e7ca05fa8600 579 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 157:e7ca05fa8600 580 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 157:e7ca05fa8600 581
AnnaBridge 157:e7ca05fa8600 582 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 157:e7ca05fa8600 583 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 157:e7ca05fa8600 584
AnnaBridge 157:e7ca05fa8600 585 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 157:e7ca05fa8600 586 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 157:e7ca05fa8600 587
AnnaBridge 157:e7ca05fa8600 588 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 157:e7ca05fa8600 589 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 157:e7ca05fa8600 590
AnnaBridge 157:e7ca05fa8600 591 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 157:e7ca05fa8600 592 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 157:e7ca05fa8600 593
AnnaBridge 157:e7ca05fa8600 594 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
AnnaBridge 157:e7ca05fa8600 595 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 157:e7ca05fa8600 596
AnnaBridge 157:e7ca05fa8600 597 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
AnnaBridge 157:e7ca05fa8600 598 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 157:e7ca05fa8600 599
AnnaBridge 157:e7ca05fa8600 600 /*@} end of group CMSIS_MPU */
AnnaBridge 157:e7ca05fa8600 601 #endif
AnnaBridge 157:e7ca05fa8600 602
AnnaBridge 157:e7ca05fa8600 603
AnnaBridge 157:e7ca05fa8600 604 /**
AnnaBridge 157:e7ca05fa8600 605 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 606 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 157:e7ca05fa8600 607 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 157:e7ca05fa8600 608 Therefore they are not covered by the Cortex-M0+ header file.
AnnaBridge 157:e7ca05fa8600 609 @{
AnnaBridge 157:e7ca05fa8600 610 */
AnnaBridge 157:e7ca05fa8600 611 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 157:e7ca05fa8600 612
AnnaBridge 157:e7ca05fa8600 613
AnnaBridge 157:e7ca05fa8600 614 /**
AnnaBridge 157:e7ca05fa8600 615 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 616 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 157:e7ca05fa8600 617 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 157:e7ca05fa8600 618 @{
AnnaBridge 157:e7ca05fa8600 619 */
AnnaBridge 157:e7ca05fa8600 620
AnnaBridge 157:e7ca05fa8600 621 /**
AnnaBridge 157:e7ca05fa8600 622 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 157:e7ca05fa8600 623 \param[in] field Name of the register bit field.
AnnaBridge 157:e7ca05fa8600 624 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 157:e7ca05fa8600 625 \return Masked and shifted value.
AnnaBridge 157:e7ca05fa8600 626 */
AnnaBridge 157:e7ca05fa8600 627 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 157:e7ca05fa8600 628
AnnaBridge 157:e7ca05fa8600 629 /**
AnnaBridge 157:e7ca05fa8600 630 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 157:e7ca05fa8600 631 \param[in] field Name of the register bit field.
AnnaBridge 157:e7ca05fa8600 632 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 157:e7ca05fa8600 633 \return Masked and shifted bit field value.
AnnaBridge 157:e7ca05fa8600 634 */
AnnaBridge 157:e7ca05fa8600 635 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 157:e7ca05fa8600 636
AnnaBridge 157:e7ca05fa8600 637 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 157:e7ca05fa8600 638
AnnaBridge 157:e7ca05fa8600 639
AnnaBridge 157:e7ca05fa8600 640 /**
AnnaBridge 157:e7ca05fa8600 641 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 642 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 157:e7ca05fa8600 643 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 157:e7ca05fa8600 644 @{
AnnaBridge 157:e7ca05fa8600 645 */
AnnaBridge 157:e7ca05fa8600 646
AnnaBridge 157:e7ca05fa8600 647 /* Memory mapping of Core Hardware */
AnnaBridge 157:e7ca05fa8600 648 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 157:e7ca05fa8600 649 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 157:e7ca05fa8600 650 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 157:e7ca05fa8600 651 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 157:e7ca05fa8600 652
AnnaBridge 157:e7ca05fa8600 653 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 157:e7ca05fa8600 654 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 157:e7ca05fa8600 655 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 157:e7ca05fa8600 656
AnnaBridge 157:e7ca05fa8600 657 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 658 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 157:e7ca05fa8600 659 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 157:e7ca05fa8600 660 #endif
AnnaBridge 157:e7ca05fa8600 661
AnnaBridge 157:e7ca05fa8600 662 /*@} */
AnnaBridge 157:e7ca05fa8600 663
AnnaBridge 157:e7ca05fa8600 664
AnnaBridge 157:e7ca05fa8600 665
AnnaBridge 157:e7ca05fa8600 666 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 667 * Hardware Abstraction Layer
AnnaBridge 157:e7ca05fa8600 668 Core Function Interface contains:
AnnaBridge 157:e7ca05fa8600 669 - Core NVIC Functions
AnnaBridge 157:e7ca05fa8600 670 - Core SysTick Functions
AnnaBridge 157:e7ca05fa8600 671 - Core Register Access Functions
AnnaBridge 157:e7ca05fa8600 672 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 673 /**
AnnaBridge 157:e7ca05fa8600 674 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 157:e7ca05fa8600 675 */
AnnaBridge 157:e7ca05fa8600 676
AnnaBridge 157:e7ca05fa8600 677
AnnaBridge 157:e7ca05fa8600 678
AnnaBridge 157:e7ca05fa8600 679 /* ########################## NVIC functions #################################### */
AnnaBridge 157:e7ca05fa8600 680 /**
AnnaBridge 157:e7ca05fa8600 681 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 682 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 157:e7ca05fa8600 683 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 157:e7ca05fa8600 684 @{
AnnaBridge 157:e7ca05fa8600 685 */
AnnaBridge 157:e7ca05fa8600 686
AnnaBridge 157:e7ca05fa8600 687 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 157:e7ca05fa8600 688 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 689 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 157:e7ca05fa8600 690 #endif
AnnaBridge 157:e7ca05fa8600 691 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 692 #else
AnnaBridge 157:e7ca05fa8600 693 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
AnnaBridge 157:e7ca05fa8600 694 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
AnnaBridge 157:e7ca05fa8600 695 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 157:e7ca05fa8600 696 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 157:e7ca05fa8600 697 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 157:e7ca05fa8600 698 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 157:e7ca05fa8600 699 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 157:e7ca05fa8600 700 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 157:e7ca05fa8600 701 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
AnnaBridge 157:e7ca05fa8600 702 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 157:e7ca05fa8600 703 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 157:e7ca05fa8600 704 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 157:e7ca05fa8600 705 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 157:e7ca05fa8600 706
AnnaBridge 157:e7ca05fa8600 707 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 157:e7ca05fa8600 708 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 709 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 157:e7ca05fa8600 710 #endif
AnnaBridge 157:e7ca05fa8600 711 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 712 #else
AnnaBridge 157:e7ca05fa8600 713 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 157:e7ca05fa8600 714 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 157:e7ca05fa8600 715 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 157:e7ca05fa8600 716
AnnaBridge 157:e7ca05fa8600 717 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 157:e7ca05fa8600 718
AnnaBridge 157:e7ca05fa8600 719
Anna Bridge 169:a7c7b631e539 720 /* Interrupt Priorities are WORD accessible only under Armv6-M */
AnnaBridge 157:e7ca05fa8600 721 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 157:e7ca05fa8600 722 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 157:e7ca05fa8600 723 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 157:e7ca05fa8600 724 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 157:e7ca05fa8600 725
AnnaBridge 157:e7ca05fa8600 726
AnnaBridge 157:e7ca05fa8600 727 /**
AnnaBridge 157:e7ca05fa8600 728 \brief Enable Interrupt
AnnaBridge 157:e7ca05fa8600 729 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 730 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 731 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 732 */
AnnaBridge 157:e7ca05fa8600 733 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 734 {
AnnaBridge 157:e7ca05fa8600 735 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 736 {
Anna Bridge 169:a7c7b631e539 737 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 738 }
AnnaBridge 157:e7ca05fa8600 739 }
AnnaBridge 157:e7ca05fa8600 740
AnnaBridge 157:e7ca05fa8600 741
AnnaBridge 157:e7ca05fa8600 742 /**
AnnaBridge 157:e7ca05fa8600 743 \brief Get Interrupt Enable status
AnnaBridge 157:e7ca05fa8600 744 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 745 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 746 \return 0 Interrupt is not enabled.
AnnaBridge 157:e7ca05fa8600 747 \return 1 Interrupt is enabled.
AnnaBridge 157:e7ca05fa8600 748 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 749 */
AnnaBridge 157:e7ca05fa8600 750 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 751 {
AnnaBridge 157:e7ca05fa8600 752 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 753 {
Anna Bridge 169:a7c7b631e539 754 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 755 }
AnnaBridge 157:e7ca05fa8600 756 else
AnnaBridge 157:e7ca05fa8600 757 {
AnnaBridge 157:e7ca05fa8600 758 return(0U);
AnnaBridge 157:e7ca05fa8600 759 }
AnnaBridge 157:e7ca05fa8600 760 }
AnnaBridge 157:e7ca05fa8600 761
AnnaBridge 157:e7ca05fa8600 762
AnnaBridge 157:e7ca05fa8600 763 /**
AnnaBridge 157:e7ca05fa8600 764 \brief Disable Interrupt
AnnaBridge 157:e7ca05fa8600 765 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 766 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 767 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 768 */
AnnaBridge 157:e7ca05fa8600 769 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 770 {
AnnaBridge 157:e7ca05fa8600 771 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 772 {
Anna Bridge 169:a7c7b631e539 773 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 774 __DSB();
AnnaBridge 157:e7ca05fa8600 775 __ISB();
AnnaBridge 157:e7ca05fa8600 776 }
AnnaBridge 157:e7ca05fa8600 777 }
AnnaBridge 157:e7ca05fa8600 778
AnnaBridge 157:e7ca05fa8600 779
AnnaBridge 157:e7ca05fa8600 780 /**
AnnaBridge 157:e7ca05fa8600 781 \brief Get Pending Interrupt
AnnaBridge 157:e7ca05fa8600 782 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 157:e7ca05fa8600 783 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 784 \return 0 Interrupt status is not pending.
AnnaBridge 157:e7ca05fa8600 785 \return 1 Interrupt status is pending.
AnnaBridge 157:e7ca05fa8600 786 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 787 */
AnnaBridge 157:e7ca05fa8600 788 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 789 {
AnnaBridge 157:e7ca05fa8600 790 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 791 {
Anna Bridge 169:a7c7b631e539 792 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 793 }
AnnaBridge 157:e7ca05fa8600 794 else
AnnaBridge 157:e7ca05fa8600 795 {
AnnaBridge 157:e7ca05fa8600 796 return(0U);
AnnaBridge 157:e7ca05fa8600 797 }
AnnaBridge 157:e7ca05fa8600 798 }
AnnaBridge 157:e7ca05fa8600 799
AnnaBridge 157:e7ca05fa8600 800
AnnaBridge 157:e7ca05fa8600 801 /**
AnnaBridge 157:e7ca05fa8600 802 \brief Set Pending Interrupt
AnnaBridge 157:e7ca05fa8600 803 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 157:e7ca05fa8600 804 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 805 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 806 */
AnnaBridge 157:e7ca05fa8600 807 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 808 {
AnnaBridge 157:e7ca05fa8600 809 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 810 {
Anna Bridge 169:a7c7b631e539 811 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 812 }
AnnaBridge 157:e7ca05fa8600 813 }
AnnaBridge 157:e7ca05fa8600 814
AnnaBridge 157:e7ca05fa8600 815
AnnaBridge 157:e7ca05fa8600 816 /**
AnnaBridge 157:e7ca05fa8600 817 \brief Clear Pending Interrupt
AnnaBridge 157:e7ca05fa8600 818 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 157:e7ca05fa8600 819 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 820 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 821 */
AnnaBridge 157:e7ca05fa8600 822 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 823 {
AnnaBridge 157:e7ca05fa8600 824 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 825 {
Anna Bridge 169:a7c7b631e539 826 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 827 }
AnnaBridge 157:e7ca05fa8600 828 }
AnnaBridge 157:e7ca05fa8600 829
AnnaBridge 157:e7ca05fa8600 830
AnnaBridge 157:e7ca05fa8600 831 /**
AnnaBridge 157:e7ca05fa8600 832 \brief Set Interrupt Priority
AnnaBridge 157:e7ca05fa8600 833 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 157:e7ca05fa8600 834 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 835 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 836 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 837 \param [in] priority Priority to set.
AnnaBridge 157:e7ca05fa8600 838 \note The priority cannot be set for every processor exception.
AnnaBridge 157:e7ca05fa8600 839 */
AnnaBridge 157:e7ca05fa8600 840 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 157:e7ca05fa8600 841 {
AnnaBridge 157:e7ca05fa8600 842 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 843 {
AnnaBridge 157:e7ca05fa8600 844 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 157:e7ca05fa8600 845 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 157:e7ca05fa8600 846 }
AnnaBridge 157:e7ca05fa8600 847 else
AnnaBridge 157:e7ca05fa8600 848 {
AnnaBridge 157:e7ca05fa8600 849 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 157:e7ca05fa8600 850 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 157:e7ca05fa8600 851 }
AnnaBridge 157:e7ca05fa8600 852 }
AnnaBridge 157:e7ca05fa8600 853
AnnaBridge 157:e7ca05fa8600 854
AnnaBridge 157:e7ca05fa8600 855 /**
AnnaBridge 157:e7ca05fa8600 856 \brief Get Interrupt Priority
AnnaBridge 157:e7ca05fa8600 857 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 157:e7ca05fa8600 858 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 859 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 860 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 861 \return Interrupt Priority.
AnnaBridge 157:e7ca05fa8600 862 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 157:e7ca05fa8600 863 */
AnnaBridge 157:e7ca05fa8600 864 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 865 {
AnnaBridge 157:e7ca05fa8600 866
AnnaBridge 157:e7ca05fa8600 867 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 868 {
AnnaBridge 157:e7ca05fa8600 869 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 157:e7ca05fa8600 870 }
AnnaBridge 157:e7ca05fa8600 871 else
AnnaBridge 157:e7ca05fa8600 872 {
AnnaBridge 157:e7ca05fa8600 873 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 157:e7ca05fa8600 874 }
AnnaBridge 157:e7ca05fa8600 875 }
AnnaBridge 157:e7ca05fa8600 876
AnnaBridge 157:e7ca05fa8600 877
AnnaBridge 157:e7ca05fa8600 878 /**
AnnaBridge 157:e7ca05fa8600 879 \brief Set Interrupt Vector
AnnaBridge 157:e7ca05fa8600 880 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 157:e7ca05fa8600 881 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 882 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 883 VTOR must been relocated to SRAM before.
AnnaBridge 157:e7ca05fa8600 884 If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge 157:e7ca05fa8600 885 \param [in] IRQn Interrupt number
AnnaBridge 157:e7ca05fa8600 886 \param [in] vector Address of interrupt handler function
AnnaBridge 157:e7ca05fa8600 887 */
AnnaBridge 157:e7ca05fa8600 888 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 157:e7ca05fa8600 889 {
AnnaBridge 157:e7ca05fa8600 890 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 891 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 157:e7ca05fa8600 892 #else
AnnaBridge 157:e7ca05fa8600 893 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 157:e7ca05fa8600 894 #endif
AnnaBridge 157:e7ca05fa8600 895 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 157:e7ca05fa8600 896 }
AnnaBridge 157:e7ca05fa8600 897
AnnaBridge 157:e7ca05fa8600 898
AnnaBridge 157:e7ca05fa8600 899 /**
AnnaBridge 157:e7ca05fa8600 900 \brief Get Interrupt Vector
AnnaBridge 157:e7ca05fa8600 901 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 157:e7ca05fa8600 902 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 903 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 904 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 905 \return Address of interrupt handler function
AnnaBridge 157:e7ca05fa8600 906 */
AnnaBridge 157:e7ca05fa8600 907 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 908 {
AnnaBridge 157:e7ca05fa8600 909 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 910 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 157:e7ca05fa8600 911 #else
AnnaBridge 157:e7ca05fa8600 912 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 157:e7ca05fa8600 913 #endif
AnnaBridge 157:e7ca05fa8600 914 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 157:e7ca05fa8600 915
AnnaBridge 157:e7ca05fa8600 916 }
AnnaBridge 157:e7ca05fa8600 917
AnnaBridge 157:e7ca05fa8600 918
AnnaBridge 157:e7ca05fa8600 919 /**
AnnaBridge 157:e7ca05fa8600 920 \brief System Reset
AnnaBridge 157:e7ca05fa8600 921 \details Initiates a system reset request to reset the MCU.
AnnaBridge 157:e7ca05fa8600 922 */
AnnaBridge 157:e7ca05fa8600 923 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 157:e7ca05fa8600 924 {
AnnaBridge 157:e7ca05fa8600 925 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 157:e7ca05fa8600 926 buffered write are completed before reset */
AnnaBridge 157:e7ca05fa8600 927 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 157:e7ca05fa8600 928 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 157:e7ca05fa8600 929 __DSB(); /* Ensure completion of memory access */
AnnaBridge 157:e7ca05fa8600 930
AnnaBridge 157:e7ca05fa8600 931 for(;;) /* wait until reset */
AnnaBridge 157:e7ca05fa8600 932 {
AnnaBridge 157:e7ca05fa8600 933 __NOP();
AnnaBridge 157:e7ca05fa8600 934 }
AnnaBridge 157:e7ca05fa8600 935 }
AnnaBridge 157:e7ca05fa8600 936
AnnaBridge 157:e7ca05fa8600 937 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 157:e7ca05fa8600 938
Anna Bridge 160:5571c4ff569f 939 /* ########################## MPU functions #################################### */
Anna Bridge 160:5571c4ff569f 940
Anna Bridge 160:5571c4ff569f 941 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 942
Anna Bridge 160:5571c4ff569f 943 #include "mpu_armv7.h"
Anna Bridge 160:5571c4ff569f 944
Anna Bridge 160:5571c4ff569f 945 #endif
AnnaBridge 157:e7ca05fa8600 946
AnnaBridge 157:e7ca05fa8600 947 /* ########################## FPU functions #################################### */
AnnaBridge 157:e7ca05fa8600 948 /**
AnnaBridge 157:e7ca05fa8600 949 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 950 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 157:e7ca05fa8600 951 \brief Function that provides FPU type.
AnnaBridge 157:e7ca05fa8600 952 @{
AnnaBridge 157:e7ca05fa8600 953 */
AnnaBridge 157:e7ca05fa8600 954
AnnaBridge 157:e7ca05fa8600 955 /**
AnnaBridge 157:e7ca05fa8600 956 \brief get FPU type
AnnaBridge 157:e7ca05fa8600 957 \details returns the FPU type
AnnaBridge 157:e7ca05fa8600 958 \returns
AnnaBridge 157:e7ca05fa8600 959 - \b 0: No FPU
AnnaBridge 157:e7ca05fa8600 960 - \b 1: Single precision FPU
AnnaBridge 157:e7ca05fa8600 961 - \b 2: Double + Single precision FPU
AnnaBridge 157:e7ca05fa8600 962 */
AnnaBridge 157:e7ca05fa8600 963 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 157:e7ca05fa8600 964 {
AnnaBridge 157:e7ca05fa8600 965 return 0U; /* No FPU */
AnnaBridge 157:e7ca05fa8600 966 }
AnnaBridge 157:e7ca05fa8600 967
AnnaBridge 157:e7ca05fa8600 968
AnnaBridge 157:e7ca05fa8600 969 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 157:e7ca05fa8600 970
AnnaBridge 157:e7ca05fa8600 971
AnnaBridge 157:e7ca05fa8600 972
AnnaBridge 157:e7ca05fa8600 973 /* ################################## SysTick function ############################################ */
AnnaBridge 157:e7ca05fa8600 974 /**
AnnaBridge 157:e7ca05fa8600 975 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 976 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 157:e7ca05fa8600 977 \brief Functions that configure the System.
AnnaBridge 157:e7ca05fa8600 978 @{
AnnaBridge 157:e7ca05fa8600 979 */
AnnaBridge 157:e7ca05fa8600 980
AnnaBridge 157:e7ca05fa8600 981 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 157:e7ca05fa8600 982
AnnaBridge 157:e7ca05fa8600 983 /**
AnnaBridge 157:e7ca05fa8600 984 \brief System Tick Configuration
AnnaBridge 157:e7ca05fa8600 985 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 157:e7ca05fa8600 986 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 157:e7ca05fa8600 987 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 157:e7ca05fa8600 988 \return 0 Function succeeded.
AnnaBridge 157:e7ca05fa8600 989 \return 1 Function failed.
AnnaBridge 157:e7ca05fa8600 990 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 157:e7ca05fa8600 991 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 157:e7ca05fa8600 992 must contain a vendor-specific implementation of this function.
AnnaBridge 157:e7ca05fa8600 993 */
AnnaBridge 157:e7ca05fa8600 994 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 157:e7ca05fa8600 995 {
AnnaBridge 157:e7ca05fa8600 996 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 157:e7ca05fa8600 997 {
AnnaBridge 157:e7ca05fa8600 998 return (1UL); /* Reload value impossible */
AnnaBridge 157:e7ca05fa8600 999 }
AnnaBridge 157:e7ca05fa8600 1000
AnnaBridge 157:e7ca05fa8600 1001 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 157:e7ca05fa8600 1002 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 157:e7ca05fa8600 1003 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 157:e7ca05fa8600 1004 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 157:e7ca05fa8600 1005 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 157:e7ca05fa8600 1006 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 157:e7ca05fa8600 1007 return (0UL); /* Function successful */
AnnaBridge 157:e7ca05fa8600 1008 }
AnnaBridge 157:e7ca05fa8600 1009
AnnaBridge 157:e7ca05fa8600 1010 #endif
AnnaBridge 157:e7ca05fa8600 1011
AnnaBridge 157:e7ca05fa8600 1012 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 157:e7ca05fa8600 1013
AnnaBridge 157:e7ca05fa8600 1014
AnnaBridge 157:e7ca05fa8600 1015
AnnaBridge 157:e7ca05fa8600 1016
AnnaBridge 157:e7ca05fa8600 1017 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 1018 }
AnnaBridge 157:e7ca05fa8600 1019 #endif
AnnaBridge 157:e7ca05fa8600 1020
AnnaBridge 157:e7ca05fa8600 1021 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
AnnaBridge 157:e7ca05fa8600 1022
AnnaBridge 157:e7ca05fa8600 1023 #endif /* __CMSIS_GENERIC */