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TARGET_LPC546XX/core_sc300.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:39:34 2018 +0100
Revision:
170:e95d10626187
Parent:
169:a7c7b631e539 
mbed library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 153:b484a57bc302 1 /**************************************************************************//**
AnnaBridge 153:b484a57bc302 2 * @file core_sc300.h
AnnaBridge 153:b484a57bc302 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.3
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
AnnaBridge 153:b484a57bc302 6 ******************************************************************************/
AnnaBridge 153:b484a57bc302 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 153:b484a57bc302 9 *
AnnaBridge 153:b484a57bc302 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 153:b484a57bc302 11 *
AnnaBridge 153:b484a57bc302 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 153:b484a57bc302 13 * not use this file except in compliance with the License.
AnnaBridge 153:b484a57bc302 14 * You may obtain a copy of the License at
AnnaBridge 153:b484a57bc302 15 *
AnnaBridge 153:b484a57bc302 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 153:b484a57bc302 17 *
AnnaBridge 153:b484a57bc302 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 153:b484a57bc302 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 153:b484a57bc302 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 153:b484a57bc302 21 * See the License for the specific language governing permissions and
AnnaBridge 153:b484a57bc302 22 * limitations under the License.
AnnaBridge 153:b484a57bc302 23 */
AnnaBridge 153:b484a57bc302 24
AnnaBridge 153:b484a57bc302 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
AnnaBridge 153:b484a57bc302 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 153:b484a57bc302 29 #endif
AnnaBridge 153:b484a57bc302 30
AnnaBridge 153:b484a57bc302 31 #ifndef __CORE_SC300_H_GENERIC
AnnaBridge 153:b484a57bc302 32 #define __CORE_SC300_H_GENERIC
AnnaBridge 153:b484a57bc302 33
AnnaBridge 153:b484a57bc302 34 #include <stdint.h>
AnnaBridge 153:b484a57bc302 35
AnnaBridge 153:b484a57bc302 36 #ifdef __cplusplus
AnnaBridge 153:b484a57bc302 37 extern "C" {
AnnaBridge 153:b484a57bc302 38 #endif
AnnaBridge 153:b484a57bc302 39
AnnaBridge 153:b484a57bc302 40 /**
AnnaBridge 153:b484a57bc302 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 153:b484a57bc302 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 153:b484a57bc302 43
AnnaBridge 153:b484a57bc302 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 153:b484a57bc302 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 153:b484a57bc302 46
AnnaBridge 153:b484a57bc302 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 153:b484a57bc302 48 Unions are used for effective representation of core registers.
AnnaBridge 153:b484a57bc302 49
AnnaBridge 153:b484a57bc302 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 153:b484a57bc302 51 Function-like macros are used to allow more efficient code.
AnnaBridge 153:b484a57bc302 52 */
AnnaBridge 153:b484a57bc302 53
AnnaBridge 153:b484a57bc302 54
AnnaBridge 153:b484a57bc302 55 /*******************************************************************************
AnnaBridge 153:b484a57bc302 56 * CMSIS definitions
AnnaBridge 153:b484a57bc302 57 ******************************************************************************/
AnnaBridge 153:b484a57bc302 58 /**
AnnaBridge 153:b484a57bc302 59 \ingroup SC3000
AnnaBridge 153:b484a57bc302 60 @{
AnnaBridge 153:b484a57bc302 61 */
AnnaBridge 153:b484a57bc302 62
Anna Bridge 160:5571c4ff569f 63 #include "cmsis_version.h"
Anna Bridge 160:5571c4ff569f 64
AnnaBridge 153:b484a57bc302 65 /* CMSIS SC300 definitions */
Anna Bridge 160:5571c4ff569f 66 #define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 160:5571c4ff569f 67 #define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 153:b484a57bc302 68 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 160:5571c4ff569f 69 __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 153:b484a57bc302 70
AnnaBridge 153:b484a57bc302 71 #define __CORTEX_SC (300U) /*!< Cortex secure core */
AnnaBridge 153:b484a57bc302 72
AnnaBridge 153:b484a57bc302 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 153:b484a57bc302 74 This core does not support an FPU at all
AnnaBridge 153:b484a57bc302 75 */
AnnaBridge 153:b484a57bc302 76 #define __FPU_USED 0U
AnnaBridge 153:b484a57bc302 77
AnnaBridge 153:b484a57bc302 78 #if defined ( __CC_ARM )
AnnaBridge 153:b484a57bc302 79 #if defined __TARGET_FPU_VFP
AnnaBridge 153:b484a57bc302 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 153:b484a57bc302 81 #endif
AnnaBridge 153:b484a57bc302 82
AnnaBridge 153:b484a57bc302 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 153:b484a57bc302 84 #if defined __ARM_PCS_VFP
AnnaBridge 153:b484a57bc302 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 153:b484a57bc302 86 #endif
AnnaBridge 153:b484a57bc302 87
AnnaBridge 153:b484a57bc302 88 #elif defined ( __GNUC__ )
AnnaBridge 153:b484a57bc302 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 153:b484a57bc302 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 153:b484a57bc302 91 #endif
AnnaBridge 153:b484a57bc302 92
AnnaBridge 153:b484a57bc302 93 #elif defined ( __ICCARM__ )
AnnaBridge 153:b484a57bc302 94 #if defined __ARMVFP__
AnnaBridge 153:b484a57bc302 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 153:b484a57bc302 96 #endif
AnnaBridge 153:b484a57bc302 97
AnnaBridge 153:b484a57bc302 98 #elif defined ( __TI_ARM__ )
AnnaBridge 153:b484a57bc302 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 153:b484a57bc302 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 153:b484a57bc302 101 #endif
AnnaBridge 153:b484a57bc302 102
AnnaBridge 153:b484a57bc302 103 #elif defined ( __TASKING__ )
AnnaBridge 153:b484a57bc302 104 #if defined __FPU_VFP__
AnnaBridge 153:b484a57bc302 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 153:b484a57bc302 106 #endif
AnnaBridge 153:b484a57bc302 107
AnnaBridge 153:b484a57bc302 108 #elif defined ( __CSMC__ )
AnnaBridge 153:b484a57bc302 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 153:b484a57bc302 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 153:b484a57bc302 111 #endif
AnnaBridge 153:b484a57bc302 112
AnnaBridge 153:b484a57bc302 113 #endif
AnnaBridge 153:b484a57bc302 114
AnnaBridge 153:b484a57bc302 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 153:b484a57bc302 116
AnnaBridge 153:b484a57bc302 117
AnnaBridge 153:b484a57bc302 118 #ifdef __cplusplus
AnnaBridge 153:b484a57bc302 119 }
AnnaBridge 153:b484a57bc302 120 #endif
AnnaBridge 153:b484a57bc302 121
AnnaBridge 153:b484a57bc302 122 #endif /* __CORE_SC300_H_GENERIC */
AnnaBridge 153:b484a57bc302 123
AnnaBridge 153:b484a57bc302 124 #ifndef __CMSIS_GENERIC
AnnaBridge 153:b484a57bc302 125
AnnaBridge 153:b484a57bc302 126 #ifndef __CORE_SC300_H_DEPENDANT
AnnaBridge 153:b484a57bc302 127 #define __CORE_SC300_H_DEPENDANT
AnnaBridge 153:b484a57bc302 128
AnnaBridge 153:b484a57bc302 129 #ifdef __cplusplus
AnnaBridge 153:b484a57bc302 130 extern "C" {
AnnaBridge 153:b484a57bc302 131 #endif
AnnaBridge 153:b484a57bc302 132
AnnaBridge 153:b484a57bc302 133 /* check device defines and use defaults */
AnnaBridge 153:b484a57bc302 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 153:b484a57bc302 135 #ifndef __SC300_REV
AnnaBridge 153:b484a57bc302 136 #define __SC300_REV 0x0000U
AnnaBridge 153:b484a57bc302 137 #warning "__SC300_REV not defined in device header file; using default!"
AnnaBridge 153:b484a57bc302 138 #endif
AnnaBridge 153:b484a57bc302 139
AnnaBridge 153:b484a57bc302 140 #ifndef __MPU_PRESENT
AnnaBridge 153:b484a57bc302 141 #define __MPU_PRESENT 0U
AnnaBridge 153:b484a57bc302 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 153:b484a57bc302 143 #endif
AnnaBridge 153:b484a57bc302 144
AnnaBridge 153:b484a57bc302 145 #ifndef __NVIC_PRIO_BITS
AnnaBridge 153:b484a57bc302 146 #define __NVIC_PRIO_BITS 3U
AnnaBridge 153:b484a57bc302 147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 153:b484a57bc302 148 #endif
AnnaBridge 153:b484a57bc302 149
AnnaBridge 153:b484a57bc302 150 #ifndef __Vendor_SysTickConfig
AnnaBridge 153:b484a57bc302 151 #define __Vendor_SysTickConfig 0U
AnnaBridge 153:b484a57bc302 152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 153:b484a57bc302 153 #endif
AnnaBridge 153:b484a57bc302 154 #endif
AnnaBridge 153:b484a57bc302 155
AnnaBridge 153:b484a57bc302 156 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 153:b484a57bc302 157 /**
AnnaBridge 153:b484a57bc302 158 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 153:b484a57bc302 159
AnnaBridge 153:b484a57bc302 160 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 153:b484a57bc302 161 \li to specify the access to peripheral variables.
AnnaBridge 153:b484a57bc302 162 \li for automatic generation of peripheral register debug information.
AnnaBridge 153:b484a57bc302 163 */
AnnaBridge 153:b484a57bc302 164 #ifdef __cplusplus
AnnaBridge 153:b484a57bc302 165 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 153:b484a57bc302 166 #else
AnnaBridge 153:b484a57bc302 167 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 153:b484a57bc302 168 #endif
AnnaBridge 153:b484a57bc302 169 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 153:b484a57bc302 170 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 153:b484a57bc302 171
AnnaBridge 153:b484a57bc302 172 /* following defines should be used for structure members */
AnnaBridge 153:b484a57bc302 173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 153:b484a57bc302 174 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 153:b484a57bc302 175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 153:b484a57bc302 176
AnnaBridge 153:b484a57bc302 177 /*@} end of group SC300 */
AnnaBridge 153:b484a57bc302 178
AnnaBridge 153:b484a57bc302 179
AnnaBridge 153:b484a57bc302 180
AnnaBridge 153:b484a57bc302 181 /*******************************************************************************
AnnaBridge 153:b484a57bc302 182 * Register Abstraction
AnnaBridge 153:b484a57bc302 183 Core Register contain:
AnnaBridge 153:b484a57bc302 184 - Core Register
AnnaBridge 153:b484a57bc302 185 - Core NVIC Register
AnnaBridge 153:b484a57bc302 186 - Core SCB Register
AnnaBridge 153:b484a57bc302 187 - Core SysTick Register
AnnaBridge 153:b484a57bc302 188 - Core Debug Register
AnnaBridge 153:b484a57bc302 189 - Core MPU Register
AnnaBridge 153:b484a57bc302 190 ******************************************************************************/
AnnaBridge 153:b484a57bc302 191 /**
AnnaBridge 153:b484a57bc302 192 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 153:b484a57bc302 193 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 153:b484a57bc302 194 */
AnnaBridge 153:b484a57bc302 195
AnnaBridge 153:b484a57bc302 196 /**
AnnaBridge 153:b484a57bc302 197 \ingroup CMSIS_core_register
AnnaBridge 153:b484a57bc302 198 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 153:b484a57bc302 199 \brief Core Register type definitions.
AnnaBridge 153:b484a57bc302 200 @{
AnnaBridge 153:b484a57bc302 201 */
AnnaBridge 153:b484a57bc302 202
AnnaBridge 153:b484a57bc302 203 /**
AnnaBridge 153:b484a57bc302 204 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 153:b484a57bc302 205 */
AnnaBridge 153:b484a57bc302 206 typedef union
AnnaBridge 153:b484a57bc302 207 {
AnnaBridge 153:b484a57bc302 208 struct
AnnaBridge 153:b484a57bc302 209 {
AnnaBridge 153:b484a57bc302 210 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
AnnaBridge 153:b484a57bc302 211 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 153:b484a57bc302 212 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 153:b484a57bc302 213 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 153:b484a57bc302 214 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 153:b484a57bc302 215 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 153:b484a57bc302 216 } b; /*!< Structure used for bit access */
AnnaBridge 153:b484a57bc302 217 uint32_t w; /*!< Type used for word access */
AnnaBridge 153:b484a57bc302 218 } APSR_Type;
AnnaBridge 153:b484a57bc302 219
AnnaBridge 153:b484a57bc302 220 /* APSR Register Definitions */
AnnaBridge 153:b484a57bc302 221 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 153:b484a57bc302 222 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 153:b484a57bc302 223
AnnaBridge 153:b484a57bc302 224 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 153:b484a57bc302 225 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 153:b484a57bc302 226
AnnaBridge 153:b484a57bc302 227 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 153:b484a57bc302 228 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 153:b484a57bc302 229
AnnaBridge 153:b484a57bc302 230 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 153:b484a57bc302 231 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 153:b484a57bc302 232
AnnaBridge 153:b484a57bc302 233 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
AnnaBridge 153:b484a57bc302 234 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
AnnaBridge 153:b484a57bc302 235
AnnaBridge 153:b484a57bc302 236
AnnaBridge 153:b484a57bc302 237 /**
AnnaBridge 153:b484a57bc302 238 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 153:b484a57bc302 239 */
AnnaBridge 153:b484a57bc302 240 typedef union
AnnaBridge 153:b484a57bc302 241 {
AnnaBridge 153:b484a57bc302 242 struct
AnnaBridge 153:b484a57bc302 243 {
AnnaBridge 153:b484a57bc302 244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 153:b484a57bc302 245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 153:b484a57bc302 246 } b; /*!< Structure used for bit access */
AnnaBridge 153:b484a57bc302 247 uint32_t w; /*!< Type used for word access */
AnnaBridge 153:b484a57bc302 248 } IPSR_Type;
AnnaBridge 153:b484a57bc302 249
AnnaBridge 153:b484a57bc302 250 /* IPSR Register Definitions */
AnnaBridge 153:b484a57bc302 251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 153:b484a57bc302 252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 153:b484a57bc302 253
AnnaBridge 153:b484a57bc302 254
AnnaBridge 153:b484a57bc302 255 /**
AnnaBridge 153:b484a57bc302 256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 153:b484a57bc302 257 */
AnnaBridge 153:b484a57bc302 258 typedef union
AnnaBridge 153:b484a57bc302 259 {
AnnaBridge 153:b484a57bc302 260 struct
AnnaBridge 153:b484a57bc302 261 {
AnnaBridge 153:b484a57bc302 262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 153:b484a57bc302 263 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
AnnaBridge 153:b484a57bc302 264 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
AnnaBridge 153:b484a57bc302 265 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
AnnaBridge 153:b484a57bc302 266 uint32_t T:1; /*!< bit: 24 Thumb bit */
AnnaBridge 153:b484a57bc302 267 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
AnnaBridge 153:b484a57bc302 268 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 153:b484a57bc302 269 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 153:b484a57bc302 270 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 153:b484a57bc302 271 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 153:b484a57bc302 272 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 153:b484a57bc302 273 } b; /*!< Structure used for bit access */
AnnaBridge 153:b484a57bc302 274 uint32_t w; /*!< Type used for word access */
AnnaBridge 153:b484a57bc302 275 } xPSR_Type;
AnnaBridge 153:b484a57bc302 276
AnnaBridge 153:b484a57bc302 277 /* xPSR Register Definitions */
AnnaBridge 153:b484a57bc302 278 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 153:b484a57bc302 279 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 153:b484a57bc302 280
AnnaBridge 153:b484a57bc302 281 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 153:b484a57bc302 282 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 153:b484a57bc302 283
AnnaBridge 153:b484a57bc302 284 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 153:b484a57bc302 285 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 153:b484a57bc302 286
AnnaBridge 153:b484a57bc302 287 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 153:b484a57bc302 288 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 153:b484a57bc302 289
AnnaBridge 153:b484a57bc302 290 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
AnnaBridge 153:b484a57bc302 291 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
AnnaBridge 153:b484a57bc302 292
AnnaBridge 153:b484a57bc302 293 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
AnnaBridge 153:b484a57bc302 294 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
AnnaBridge 153:b484a57bc302 295
AnnaBridge 153:b484a57bc302 296 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 153:b484a57bc302 297 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 153:b484a57bc302 298
AnnaBridge 153:b484a57bc302 299 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
AnnaBridge 153:b484a57bc302 300 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
AnnaBridge 153:b484a57bc302 301
AnnaBridge 153:b484a57bc302 302 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 153:b484a57bc302 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 153:b484a57bc302 304
AnnaBridge 153:b484a57bc302 305
AnnaBridge 153:b484a57bc302 306 /**
AnnaBridge 153:b484a57bc302 307 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 153:b484a57bc302 308 */
AnnaBridge 153:b484a57bc302 309 typedef union
AnnaBridge 153:b484a57bc302 310 {
AnnaBridge 153:b484a57bc302 311 struct
AnnaBridge 153:b484a57bc302 312 {
AnnaBridge 153:b484a57bc302 313 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 153:b484a57bc302 314 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 153:b484a57bc302 315 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 153:b484a57bc302 316 } b; /*!< Structure used for bit access */
AnnaBridge 153:b484a57bc302 317 uint32_t w; /*!< Type used for word access */
AnnaBridge 153:b484a57bc302 318 } CONTROL_Type;
AnnaBridge 153:b484a57bc302 319
AnnaBridge 153:b484a57bc302 320 /* CONTROL Register Definitions */
AnnaBridge 153:b484a57bc302 321 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 153:b484a57bc302 322 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 153:b484a57bc302 323
AnnaBridge 153:b484a57bc302 324 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 153:b484a57bc302 325 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 153:b484a57bc302 326
AnnaBridge 153:b484a57bc302 327 /*@} end of group CMSIS_CORE */
AnnaBridge 153:b484a57bc302 328
AnnaBridge 153:b484a57bc302 329
AnnaBridge 153:b484a57bc302 330 /**
AnnaBridge 153:b484a57bc302 331 \ingroup CMSIS_core_register
AnnaBridge 153:b484a57bc302 332 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 153:b484a57bc302 333 \brief Type definitions for the NVIC Registers
AnnaBridge 153:b484a57bc302 334 @{
AnnaBridge 153:b484a57bc302 335 */
AnnaBridge 153:b484a57bc302 336
AnnaBridge 153:b484a57bc302 337 /**
AnnaBridge 153:b484a57bc302 338 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 153:b484a57bc302 339 */
AnnaBridge 153:b484a57bc302 340 typedef struct
AnnaBridge 153:b484a57bc302 341 {
AnnaBridge 153:b484a57bc302 342 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 153:b484a57bc302 343 uint32_t RESERVED0[24U];
AnnaBridge 153:b484a57bc302 344 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 153:b484a57bc302 345 uint32_t RSERVED1[24U];
AnnaBridge 153:b484a57bc302 346 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 153:b484a57bc302 347 uint32_t RESERVED2[24U];
AnnaBridge 153:b484a57bc302 348 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 153:b484a57bc302 349 uint32_t RESERVED3[24U];
AnnaBridge 153:b484a57bc302 350 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 153:b484a57bc302 351 uint32_t RESERVED4[56U];
AnnaBridge 153:b484a57bc302 352 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
AnnaBridge 153:b484a57bc302 353 uint32_t RESERVED5[644U];
AnnaBridge 153:b484a57bc302 354 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
AnnaBridge 153:b484a57bc302 355 } NVIC_Type;
AnnaBridge 153:b484a57bc302 356
AnnaBridge 153:b484a57bc302 357 /* Software Triggered Interrupt Register Definitions */
AnnaBridge 153:b484a57bc302 358 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
AnnaBridge 153:b484a57bc302 359 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
AnnaBridge 153:b484a57bc302 360
AnnaBridge 153:b484a57bc302 361 /*@} end of group CMSIS_NVIC */
AnnaBridge 153:b484a57bc302 362
AnnaBridge 153:b484a57bc302 363
AnnaBridge 153:b484a57bc302 364 /**
AnnaBridge 153:b484a57bc302 365 \ingroup CMSIS_core_register
AnnaBridge 153:b484a57bc302 366 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 153:b484a57bc302 367 \brief Type definitions for the System Control Block Registers
AnnaBridge 153:b484a57bc302 368 @{
AnnaBridge 153:b484a57bc302 369 */
AnnaBridge 153:b484a57bc302 370
AnnaBridge 153:b484a57bc302 371 /**
AnnaBridge 153:b484a57bc302 372 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 153:b484a57bc302 373 */
AnnaBridge 153:b484a57bc302 374 typedef struct
AnnaBridge 153:b484a57bc302 375 {
AnnaBridge 153:b484a57bc302 376 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 153:b484a57bc302 377 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 153:b484a57bc302 378 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 153:b484a57bc302 379 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 153:b484a57bc302 380 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 153:b484a57bc302 381 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 153:b484a57bc302 382 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
AnnaBridge 153:b484a57bc302 383 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 153:b484a57bc302 384 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
AnnaBridge 153:b484a57bc302 385 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
AnnaBridge 153:b484a57bc302 386 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
AnnaBridge 153:b484a57bc302 387 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
AnnaBridge 153:b484a57bc302 388 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
AnnaBridge 153:b484a57bc302 389 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
AnnaBridge 153:b484a57bc302 390 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
AnnaBridge 153:b484a57bc302 391 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
AnnaBridge 153:b484a57bc302 392 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
AnnaBridge 153:b484a57bc302 393 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
AnnaBridge 153:b484a57bc302 394 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
AnnaBridge 153:b484a57bc302 395 uint32_t RESERVED0[5U];
AnnaBridge 153:b484a57bc302 396 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
AnnaBridge 153:b484a57bc302 397 uint32_t RESERVED1[129U];
AnnaBridge 153:b484a57bc302 398 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
AnnaBridge 153:b484a57bc302 399 } SCB_Type;
AnnaBridge 153:b484a57bc302 400
AnnaBridge 153:b484a57bc302 401 /* SCB CPUID Register Definitions */
AnnaBridge 153:b484a57bc302 402 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 153:b484a57bc302 403 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 153:b484a57bc302 404
AnnaBridge 153:b484a57bc302 405 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 153:b484a57bc302 406 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 153:b484a57bc302 407
AnnaBridge 153:b484a57bc302 408 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 153:b484a57bc302 409 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 153:b484a57bc302 410
AnnaBridge 153:b484a57bc302 411 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 153:b484a57bc302 412 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 153:b484a57bc302 413
AnnaBridge 153:b484a57bc302 414 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 153:b484a57bc302 415 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 153:b484a57bc302 416
AnnaBridge 153:b484a57bc302 417 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 153:b484a57bc302 418 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 153:b484a57bc302 419 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 153:b484a57bc302 420
AnnaBridge 153:b484a57bc302 421 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 153:b484a57bc302 422 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 153:b484a57bc302 423
AnnaBridge 153:b484a57bc302 424 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 153:b484a57bc302 425 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 153:b484a57bc302 426
AnnaBridge 153:b484a57bc302 427 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 153:b484a57bc302 428 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 153:b484a57bc302 429
AnnaBridge 153:b484a57bc302 430 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 153:b484a57bc302 431 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 153:b484a57bc302 432
AnnaBridge 153:b484a57bc302 433 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 153:b484a57bc302 434 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 153:b484a57bc302 435
AnnaBridge 153:b484a57bc302 436 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 153:b484a57bc302 437 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 153:b484a57bc302 438
AnnaBridge 153:b484a57bc302 439 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 153:b484a57bc302 440 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 153:b484a57bc302 441
AnnaBridge 153:b484a57bc302 442 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 153:b484a57bc302 443 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 153:b484a57bc302 444
AnnaBridge 153:b484a57bc302 445 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 153:b484a57bc302 446 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 153:b484a57bc302 447
AnnaBridge 153:b484a57bc302 448 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 153:b484a57bc302 449 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
AnnaBridge 153:b484a57bc302 450 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
AnnaBridge 153:b484a57bc302 451
AnnaBridge 153:b484a57bc302 452 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 153:b484a57bc302 453 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 153:b484a57bc302 454
AnnaBridge 153:b484a57bc302 455 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 153:b484a57bc302 456 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 153:b484a57bc302 457 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 153:b484a57bc302 458
AnnaBridge 153:b484a57bc302 459 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 153:b484a57bc302 460 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 153:b484a57bc302 461
AnnaBridge 153:b484a57bc302 462 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 153:b484a57bc302 463 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 153:b484a57bc302 464
AnnaBridge 153:b484a57bc302 465 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
AnnaBridge 153:b484a57bc302 466 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
AnnaBridge 153:b484a57bc302 467
AnnaBridge 153:b484a57bc302 468 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 153:b484a57bc302 469 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 153:b484a57bc302 470
AnnaBridge 153:b484a57bc302 471 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 153:b484a57bc302 472 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 153:b484a57bc302 473
AnnaBridge 153:b484a57bc302 474 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
AnnaBridge 153:b484a57bc302 475 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
AnnaBridge 153:b484a57bc302 476
AnnaBridge 153:b484a57bc302 477 /* SCB System Control Register Definitions */
AnnaBridge 153:b484a57bc302 478 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 153:b484a57bc302 479 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 153:b484a57bc302 480
AnnaBridge 153:b484a57bc302 481 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 153:b484a57bc302 482 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 153:b484a57bc302 483
AnnaBridge 153:b484a57bc302 484 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 153:b484a57bc302 485 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 153:b484a57bc302 486
AnnaBridge 153:b484a57bc302 487 /* SCB Configuration Control Register Definitions */
AnnaBridge 153:b484a57bc302 488 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 153:b484a57bc302 489 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 153:b484a57bc302 490
AnnaBridge 153:b484a57bc302 491 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 153:b484a57bc302 492 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 153:b484a57bc302 493
AnnaBridge 153:b484a57bc302 494 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 153:b484a57bc302 495 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 153:b484a57bc302 496
AnnaBridge 153:b484a57bc302 497 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 153:b484a57bc302 498 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 153:b484a57bc302 499
AnnaBridge 153:b484a57bc302 500 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 153:b484a57bc302 501 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 153:b484a57bc302 502
AnnaBridge 153:b484a57bc302 503 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
AnnaBridge 153:b484a57bc302 504 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
AnnaBridge 153:b484a57bc302 505
AnnaBridge 153:b484a57bc302 506 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 153:b484a57bc302 507 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
AnnaBridge 153:b484a57bc302 508 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
AnnaBridge 153:b484a57bc302 509
AnnaBridge 153:b484a57bc302 510 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
AnnaBridge 153:b484a57bc302 511 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
AnnaBridge 153:b484a57bc302 512
AnnaBridge 153:b484a57bc302 513 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
AnnaBridge 153:b484a57bc302 514 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
AnnaBridge 153:b484a57bc302 515
AnnaBridge 153:b484a57bc302 516 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 153:b484a57bc302 517 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 153:b484a57bc302 518
AnnaBridge 153:b484a57bc302 519 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
AnnaBridge 153:b484a57bc302 520 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
AnnaBridge 153:b484a57bc302 521
AnnaBridge 153:b484a57bc302 522 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
AnnaBridge 153:b484a57bc302 523 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
AnnaBridge 153:b484a57bc302 524
AnnaBridge 153:b484a57bc302 525 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
AnnaBridge 153:b484a57bc302 526 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
AnnaBridge 153:b484a57bc302 527
AnnaBridge 153:b484a57bc302 528 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 153:b484a57bc302 529 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 153:b484a57bc302 530
AnnaBridge 153:b484a57bc302 531 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 153:b484a57bc302 532 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 153:b484a57bc302 533
AnnaBridge 153:b484a57bc302 534 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
AnnaBridge 153:b484a57bc302 535 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
AnnaBridge 153:b484a57bc302 536
AnnaBridge 153:b484a57bc302 537 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 153:b484a57bc302 538 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 153:b484a57bc302 539
AnnaBridge 153:b484a57bc302 540 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
AnnaBridge 153:b484a57bc302 541 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
AnnaBridge 153:b484a57bc302 542
AnnaBridge 153:b484a57bc302 543 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
AnnaBridge 153:b484a57bc302 544 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
AnnaBridge 153:b484a57bc302 545
AnnaBridge 153:b484a57bc302 546 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
AnnaBridge 153:b484a57bc302 547 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
AnnaBridge 153:b484a57bc302 548
AnnaBridge 153:b484a57bc302 549 /* SCB Configurable Fault Status Register Definitions */
AnnaBridge 153:b484a57bc302 550 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
AnnaBridge 153:b484a57bc302 551 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
AnnaBridge 153:b484a57bc302 552
AnnaBridge 153:b484a57bc302 553 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
AnnaBridge 153:b484a57bc302 554 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
AnnaBridge 153:b484a57bc302 555
AnnaBridge 153:b484a57bc302 556 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
AnnaBridge 153:b484a57bc302 557 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
AnnaBridge 153:b484a57bc302 558
AnnaBridge 153:b484a57bc302 559 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 153:b484a57bc302 560 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
AnnaBridge 153:b484a57bc302 561 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
AnnaBridge 153:b484a57bc302 562
AnnaBridge 153:b484a57bc302 563 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
AnnaBridge 153:b484a57bc302 564 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
AnnaBridge 153:b484a57bc302 565
AnnaBridge 153:b484a57bc302 566 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
AnnaBridge 153:b484a57bc302 567 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
AnnaBridge 153:b484a57bc302 568
AnnaBridge 153:b484a57bc302 569 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
AnnaBridge 153:b484a57bc302 570 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
AnnaBridge 153:b484a57bc302 571
AnnaBridge 153:b484a57bc302 572 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
AnnaBridge 153:b484a57bc302 573 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
AnnaBridge 153:b484a57bc302 574
AnnaBridge 153:b484a57bc302 575 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 153:b484a57bc302 576 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
AnnaBridge 153:b484a57bc302 577 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
AnnaBridge 153:b484a57bc302 578
AnnaBridge 153:b484a57bc302 579 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
AnnaBridge 153:b484a57bc302 580 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
AnnaBridge 153:b484a57bc302 581
AnnaBridge 153:b484a57bc302 582 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
AnnaBridge 153:b484a57bc302 583 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
AnnaBridge 153:b484a57bc302 584
AnnaBridge 153:b484a57bc302 585 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
AnnaBridge 153:b484a57bc302 586 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
AnnaBridge 153:b484a57bc302 587
AnnaBridge 153:b484a57bc302 588 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
AnnaBridge 153:b484a57bc302 589 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
AnnaBridge 153:b484a57bc302 590
AnnaBridge 153:b484a57bc302 591 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
AnnaBridge 153:b484a57bc302 592 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
AnnaBridge 153:b484a57bc302 593
AnnaBridge 153:b484a57bc302 594 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 153:b484a57bc302 595 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
AnnaBridge 153:b484a57bc302 596 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
AnnaBridge 153:b484a57bc302 597
AnnaBridge 153:b484a57bc302 598 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
AnnaBridge 153:b484a57bc302 599 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
AnnaBridge 153:b484a57bc302 600
AnnaBridge 153:b484a57bc302 601 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
AnnaBridge 153:b484a57bc302 602 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
AnnaBridge 153:b484a57bc302 603
AnnaBridge 153:b484a57bc302 604 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
AnnaBridge 153:b484a57bc302 605 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
AnnaBridge 153:b484a57bc302 606
AnnaBridge 153:b484a57bc302 607 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
AnnaBridge 153:b484a57bc302 608 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
AnnaBridge 153:b484a57bc302 609
AnnaBridge 153:b484a57bc302 610 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
AnnaBridge 153:b484a57bc302 611 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
AnnaBridge 153:b484a57bc302 612
AnnaBridge 153:b484a57bc302 613 /* SCB Hard Fault Status Register Definitions */
AnnaBridge 153:b484a57bc302 614 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
AnnaBridge 153:b484a57bc302 615 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
AnnaBridge 153:b484a57bc302 616
AnnaBridge 153:b484a57bc302 617 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
AnnaBridge 153:b484a57bc302 618 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
AnnaBridge 153:b484a57bc302 619
AnnaBridge 153:b484a57bc302 620 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
AnnaBridge 153:b484a57bc302 621 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
AnnaBridge 153:b484a57bc302 622
AnnaBridge 153:b484a57bc302 623 /* SCB Debug Fault Status Register Definitions */
AnnaBridge 153:b484a57bc302 624 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
AnnaBridge 153:b484a57bc302 625 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
AnnaBridge 153:b484a57bc302 626
AnnaBridge 153:b484a57bc302 627 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
AnnaBridge 153:b484a57bc302 628 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
AnnaBridge 153:b484a57bc302 629
AnnaBridge 153:b484a57bc302 630 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
AnnaBridge 153:b484a57bc302 631 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
AnnaBridge 153:b484a57bc302 632
AnnaBridge 153:b484a57bc302 633 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
AnnaBridge 153:b484a57bc302 634 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
AnnaBridge 153:b484a57bc302 635
AnnaBridge 153:b484a57bc302 636 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
AnnaBridge 153:b484a57bc302 637 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
AnnaBridge 153:b484a57bc302 638
AnnaBridge 153:b484a57bc302 639 /*@} end of group CMSIS_SCB */
AnnaBridge 153:b484a57bc302 640
AnnaBridge 153:b484a57bc302 641
AnnaBridge 153:b484a57bc302 642 /**
AnnaBridge 153:b484a57bc302 643 \ingroup CMSIS_core_register
AnnaBridge 153:b484a57bc302 644 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 153:b484a57bc302 645 \brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge 153:b484a57bc302 646 @{
AnnaBridge 153:b484a57bc302 647 */
AnnaBridge 153:b484a57bc302 648
AnnaBridge 153:b484a57bc302 649 /**
AnnaBridge 153:b484a57bc302 650 \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge 153:b484a57bc302 651 */
AnnaBridge 153:b484a57bc302 652 typedef struct
AnnaBridge 153:b484a57bc302 653 {
AnnaBridge 153:b484a57bc302 654 uint32_t RESERVED0[1U];
AnnaBridge 153:b484a57bc302 655 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
AnnaBridge 153:b484a57bc302 656 uint32_t RESERVED1[1U];
AnnaBridge 153:b484a57bc302 657 } SCnSCB_Type;
AnnaBridge 153:b484a57bc302 658
AnnaBridge 153:b484a57bc302 659 /* Interrupt Controller Type Register Definitions */
AnnaBridge 153:b484a57bc302 660 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
AnnaBridge 153:b484a57bc302 661 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
AnnaBridge 153:b484a57bc302 662
AnnaBridge 153:b484a57bc302 663 /*@} end of group CMSIS_SCnotSCB */
AnnaBridge 153:b484a57bc302 664
AnnaBridge 153:b484a57bc302 665
AnnaBridge 153:b484a57bc302 666 /**
AnnaBridge 153:b484a57bc302 667 \ingroup CMSIS_core_register
AnnaBridge 153:b484a57bc302 668 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 153:b484a57bc302 669 \brief Type definitions for the System Timer Registers.
AnnaBridge 153:b484a57bc302 670 @{
AnnaBridge 153:b484a57bc302 671 */
AnnaBridge 153:b484a57bc302 672
AnnaBridge 153:b484a57bc302 673 /**
AnnaBridge 153:b484a57bc302 674 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 153:b484a57bc302 675 */
AnnaBridge 153:b484a57bc302 676 typedef struct
AnnaBridge 153:b484a57bc302 677 {
AnnaBridge 153:b484a57bc302 678 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 153:b484a57bc302 679 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 153:b484a57bc302 680 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 153:b484a57bc302 681 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 153:b484a57bc302 682 } SysTick_Type;
AnnaBridge 153:b484a57bc302 683
AnnaBridge 153:b484a57bc302 684 /* SysTick Control / Status Register Definitions */
AnnaBridge 153:b484a57bc302 685 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 153:b484a57bc302 686 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 153:b484a57bc302 687
AnnaBridge 153:b484a57bc302 688 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 153:b484a57bc302 689 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 153:b484a57bc302 690
AnnaBridge 153:b484a57bc302 691 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 153:b484a57bc302 692 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 153:b484a57bc302 693
AnnaBridge 153:b484a57bc302 694 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 153:b484a57bc302 695 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 153:b484a57bc302 696
AnnaBridge 153:b484a57bc302 697 /* SysTick Reload Register Definitions */
AnnaBridge 153:b484a57bc302 698 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 153:b484a57bc302 699 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 153:b484a57bc302 700
AnnaBridge 153:b484a57bc302 701 /* SysTick Current Register Definitions */
AnnaBridge 153:b484a57bc302 702 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 153:b484a57bc302 703 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 153:b484a57bc302 704
AnnaBridge 153:b484a57bc302 705 /* SysTick Calibration Register Definitions */
AnnaBridge 153:b484a57bc302 706 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 153:b484a57bc302 707 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 153:b484a57bc302 708
AnnaBridge 153:b484a57bc302 709 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 153:b484a57bc302 710 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 153:b484a57bc302 711
AnnaBridge 153:b484a57bc302 712 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 153:b484a57bc302 713 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 153:b484a57bc302 714
AnnaBridge 153:b484a57bc302 715 /*@} end of group CMSIS_SysTick */
AnnaBridge 153:b484a57bc302 716
AnnaBridge 153:b484a57bc302 717
AnnaBridge 153:b484a57bc302 718 /**
AnnaBridge 153:b484a57bc302 719 \ingroup CMSIS_core_register
AnnaBridge 153:b484a57bc302 720 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge 153:b484a57bc302 721 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge 153:b484a57bc302 722 @{
AnnaBridge 153:b484a57bc302 723 */
AnnaBridge 153:b484a57bc302 724
AnnaBridge 153:b484a57bc302 725 /**
AnnaBridge 153:b484a57bc302 726 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge 153:b484a57bc302 727 */
AnnaBridge 153:b484a57bc302 728 typedef struct
AnnaBridge 153:b484a57bc302 729 {
AnnaBridge 153:b484a57bc302 730 __OM union
AnnaBridge 153:b484a57bc302 731 {
AnnaBridge 153:b484a57bc302 732 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
AnnaBridge 153:b484a57bc302 733 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
AnnaBridge 153:b484a57bc302 734 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
AnnaBridge 153:b484a57bc302 735 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
AnnaBridge 153:b484a57bc302 736 uint32_t RESERVED0[864U];
AnnaBridge 153:b484a57bc302 737 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
AnnaBridge 153:b484a57bc302 738 uint32_t RESERVED1[15U];
AnnaBridge 153:b484a57bc302 739 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
AnnaBridge 153:b484a57bc302 740 uint32_t RESERVED2[15U];
AnnaBridge 153:b484a57bc302 741 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
AnnaBridge 153:b484a57bc302 742 uint32_t RESERVED3[29U];
AnnaBridge 153:b484a57bc302 743 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
AnnaBridge 153:b484a57bc302 744 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
AnnaBridge 153:b484a57bc302 745 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
AnnaBridge 153:b484a57bc302 746 uint32_t RESERVED4[43U];
AnnaBridge 153:b484a57bc302 747 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
AnnaBridge 153:b484a57bc302 748 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
AnnaBridge 153:b484a57bc302 749 uint32_t RESERVED5[6U];
AnnaBridge 153:b484a57bc302 750 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
AnnaBridge 153:b484a57bc302 751 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
AnnaBridge 153:b484a57bc302 752 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
AnnaBridge 153:b484a57bc302 753 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
AnnaBridge 153:b484a57bc302 754 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
AnnaBridge 153:b484a57bc302 755 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
AnnaBridge 153:b484a57bc302 756 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
AnnaBridge 153:b484a57bc302 757 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
AnnaBridge 153:b484a57bc302 758 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
AnnaBridge 153:b484a57bc302 759 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
AnnaBridge 153:b484a57bc302 760 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
AnnaBridge 153:b484a57bc302 761 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
AnnaBridge 153:b484a57bc302 762 } ITM_Type;
AnnaBridge 153:b484a57bc302 763
AnnaBridge 153:b484a57bc302 764 /* ITM Trace Privilege Register Definitions */
AnnaBridge 153:b484a57bc302 765 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
AnnaBridge 153:b484a57bc302 766 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
AnnaBridge 153:b484a57bc302 767
AnnaBridge 153:b484a57bc302 768 /* ITM Trace Control Register Definitions */
AnnaBridge 153:b484a57bc302 769 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
AnnaBridge 153:b484a57bc302 770 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
AnnaBridge 153:b484a57bc302 771
AnnaBridge 153:b484a57bc302 772 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
AnnaBridge 153:b484a57bc302 773 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
AnnaBridge 153:b484a57bc302 774
AnnaBridge 153:b484a57bc302 775 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
AnnaBridge 153:b484a57bc302 776 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
AnnaBridge 153:b484a57bc302 777
AnnaBridge 153:b484a57bc302 778 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
AnnaBridge 153:b484a57bc302 779 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
AnnaBridge 153:b484a57bc302 780
AnnaBridge 153:b484a57bc302 781 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
AnnaBridge 153:b484a57bc302 782 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
AnnaBridge 153:b484a57bc302 783
AnnaBridge 153:b484a57bc302 784 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
AnnaBridge 153:b484a57bc302 785 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
AnnaBridge 153:b484a57bc302 786
AnnaBridge 153:b484a57bc302 787 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
AnnaBridge 153:b484a57bc302 788 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
AnnaBridge 153:b484a57bc302 789
AnnaBridge 153:b484a57bc302 790 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
AnnaBridge 153:b484a57bc302 791 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
AnnaBridge 153:b484a57bc302 792
AnnaBridge 153:b484a57bc302 793 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
AnnaBridge 153:b484a57bc302 794 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
AnnaBridge 153:b484a57bc302 795
AnnaBridge 153:b484a57bc302 796 /* ITM Integration Write Register Definitions */
AnnaBridge 153:b484a57bc302 797 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
AnnaBridge 153:b484a57bc302 798 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
AnnaBridge 153:b484a57bc302 799
AnnaBridge 153:b484a57bc302 800 /* ITM Integration Read Register Definitions */
AnnaBridge 153:b484a57bc302 801 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
AnnaBridge 153:b484a57bc302 802 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
AnnaBridge 153:b484a57bc302 803
AnnaBridge 153:b484a57bc302 804 /* ITM Integration Mode Control Register Definitions */
AnnaBridge 153:b484a57bc302 805 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
AnnaBridge 153:b484a57bc302 806 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
AnnaBridge 153:b484a57bc302 807
AnnaBridge 153:b484a57bc302 808 /* ITM Lock Status Register Definitions */
AnnaBridge 153:b484a57bc302 809 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
AnnaBridge 153:b484a57bc302 810 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
AnnaBridge 153:b484a57bc302 811
AnnaBridge 153:b484a57bc302 812 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
AnnaBridge 153:b484a57bc302 813 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
AnnaBridge 153:b484a57bc302 814
AnnaBridge 153:b484a57bc302 815 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
AnnaBridge 153:b484a57bc302 816 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
AnnaBridge 153:b484a57bc302 817
AnnaBridge 153:b484a57bc302 818 /*@}*/ /* end of group CMSIS_ITM */
AnnaBridge 153:b484a57bc302 819
AnnaBridge 153:b484a57bc302 820
AnnaBridge 153:b484a57bc302 821 /**
AnnaBridge 153:b484a57bc302 822 \ingroup CMSIS_core_register
AnnaBridge 153:b484a57bc302 823 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 153:b484a57bc302 824 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 153:b484a57bc302 825 @{
AnnaBridge 153:b484a57bc302 826 */
AnnaBridge 153:b484a57bc302 827
AnnaBridge 153:b484a57bc302 828 /**
AnnaBridge 153:b484a57bc302 829 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 153:b484a57bc302 830 */
AnnaBridge 153:b484a57bc302 831 typedef struct
AnnaBridge 153:b484a57bc302 832 {
AnnaBridge 153:b484a57bc302 833 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 153:b484a57bc302 834 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
AnnaBridge 153:b484a57bc302 835 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
AnnaBridge 153:b484a57bc302 836 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
AnnaBridge 153:b484a57bc302 837 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
AnnaBridge 153:b484a57bc302 838 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
AnnaBridge 153:b484a57bc302 839 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
AnnaBridge 153:b484a57bc302 840 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 153:b484a57bc302 841 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 153:b484a57bc302 842 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
AnnaBridge 153:b484a57bc302 843 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 153:b484a57bc302 844 uint32_t RESERVED0[1U];
AnnaBridge 153:b484a57bc302 845 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 153:b484a57bc302 846 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
AnnaBridge 153:b484a57bc302 847 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 153:b484a57bc302 848 uint32_t RESERVED1[1U];
AnnaBridge 153:b484a57bc302 849 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 153:b484a57bc302 850 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
AnnaBridge 153:b484a57bc302 851 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 153:b484a57bc302 852 uint32_t RESERVED2[1U];
AnnaBridge 153:b484a57bc302 853 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 153:b484a57bc302 854 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
AnnaBridge 153:b484a57bc302 855 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 153:b484a57bc302 856 } DWT_Type;
AnnaBridge 153:b484a57bc302 857
AnnaBridge 153:b484a57bc302 858 /* DWT Control Register Definitions */
AnnaBridge 153:b484a57bc302 859 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 153:b484a57bc302 860 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 153:b484a57bc302 861
AnnaBridge 153:b484a57bc302 862 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 153:b484a57bc302 863 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 153:b484a57bc302 864
AnnaBridge 153:b484a57bc302 865 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 153:b484a57bc302 866 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 153:b484a57bc302 867
AnnaBridge 153:b484a57bc302 868 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 153:b484a57bc302 869 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 153:b484a57bc302 870
AnnaBridge 153:b484a57bc302 871 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 153:b484a57bc302 872 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 153:b484a57bc302 873
AnnaBridge 153:b484a57bc302 874 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
AnnaBridge 153:b484a57bc302 875 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
AnnaBridge 153:b484a57bc302 876
AnnaBridge 153:b484a57bc302 877 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
AnnaBridge 153:b484a57bc302 878 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
AnnaBridge 153:b484a57bc302 879
AnnaBridge 153:b484a57bc302 880 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
AnnaBridge 153:b484a57bc302 881 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
AnnaBridge 153:b484a57bc302 882
AnnaBridge 153:b484a57bc302 883 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
AnnaBridge 153:b484a57bc302 884 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
AnnaBridge 153:b484a57bc302 885
AnnaBridge 153:b484a57bc302 886 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
AnnaBridge 153:b484a57bc302 887 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
AnnaBridge 153:b484a57bc302 888
AnnaBridge 153:b484a57bc302 889 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
AnnaBridge 153:b484a57bc302 890 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
AnnaBridge 153:b484a57bc302 891
AnnaBridge 153:b484a57bc302 892 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
AnnaBridge 153:b484a57bc302 893 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
AnnaBridge 153:b484a57bc302 894
AnnaBridge 153:b484a57bc302 895 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
AnnaBridge 153:b484a57bc302 896 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
AnnaBridge 153:b484a57bc302 897
AnnaBridge 153:b484a57bc302 898 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
AnnaBridge 153:b484a57bc302 899 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
AnnaBridge 153:b484a57bc302 900
AnnaBridge 153:b484a57bc302 901 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
AnnaBridge 153:b484a57bc302 902 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
AnnaBridge 153:b484a57bc302 903
AnnaBridge 153:b484a57bc302 904 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
AnnaBridge 153:b484a57bc302 905 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
AnnaBridge 153:b484a57bc302 906
AnnaBridge 153:b484a57bc302 907 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
AnnaBridge 153:b484a57bc302 908 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
AnnaBridge 153:b484a57bc302 909
AnnaBridge 153:b484a57bc302 910 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
AnnaBridge 153:b484a57bc302 911 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
AnnaBridge 153:b484a57bc302 912
AnnaBridge 153:b484a57bc302 913 /* DWT CPI Count Register Definitions */
AnnaBridge 153:b484a57bc302 914 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
AnnaBridge 153:b484a57bc302 915 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
AnnaBridge 153:b484a57bc302 916
AnnaBridge 153:b484a57bc302 917 /* DWT Exception Overhead Count Register Definitions */
AnnaBridge 153:b484a57bc302 918 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
AnnaBridge 153:b484a57bc302 919 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
AnnaBridge 153:b484a57bc302 920
AnnaBridge 153:b484a57bc302 921 /* DWT Sleep Count Register Definitions */
AnnaBridge 153:b484a57bc302 922 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
AnnaBridge 153:b484a57bc302 923 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
AnnaBridge 153:b484a57bc302 924
AnnaBridge 153:b484a57bc302 925 /* DWT LSU Count Register Definitions */
AnnaBridge 153:b484a57bc302 926 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
AnnaBridge 153:b484a57bc302 927 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
AnnaBridge 153:b484a57bc302 928
AnnaBridge 153:b484a57bc302 929 /* DWT Folded-instruction Count Register Definitions */
AnnaBridge 153:b484a57bc302 930 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
AnnaBridge 153:b484a57bc302 931 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
AnnaBridge 153:b484a57bc302 932
AnnaBridge 153:b484a57bc302 933 /* DWT Comparator Mask Register Definitions */
AnnaBridge 153:b484a57bc302 934 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
AnnaBridge 153:b484a57bc302 935 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
AnnaBridge 153:b484a57bc302 936
AnnaBridge 153:b484a57bc302 937 /* DWT Comparator Function Register Definitions */
AnnaBridge 153:b484a57bc302 938 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 153:b484a57bc302 939 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 153:b484a57bc302 940
AnnaBridge 153:b484a57bc302 941 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
AnnaBridge 153:b484a57bc302 942 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
AnnaBridge 153:b484a57bc302 943
AnnaBridge 153:b484a57bc302 944 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
AnnaBridge 153:b484a57bc302 945 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
AnnaBridge 153:b484a57bc302 946
AnnaBridge 153:b484a57bc302 947 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 153:b484a57bc302 948 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 153:b484a57bc302 949
AnnaBridge 153:b484a57bc302 950 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
AnnaBridge 153:b484a57bc302 951 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
AnnaBridge 153:b484a57bc302 952
AnnaBridge 153:b484a57bc302 953 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
AnnaBridge 153:b484a57bc302 954 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
AnnaBridge 153:b484a57bc302 955
AnnaBridge 153:b484a57bc302 956 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
AnnaBridge 153:b484a57bc302 957 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
AnnaBridge 153:b484a57bc302 958
AnnaBridge 153:b484a57bc302 959 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
AnnaBridge 153:b484a57bc302 960 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
AnnaBridge 153:b484a57bc302 961
AnnaBridge 153:b484a57bc302 962 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
AnnaBridge 153:b484a57bc302 963 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
AnnaBridge 153:b484a57bc302 964
AnnaBridge 153:b484a57bc302 965 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 153:b484a57bc302 966
AnnaBridge 153:b484a57bc302 967
AnnaBridge 153:b484a57bc302 968 /**
AnnaBridge 153:b484a57bc302 969 \ingroup CMSIS_core_register
AnnaBridge 153:b484a57bc302 970 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 153:b484a57bc302 971 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 153:b484a57bc302 972 @{
AnnaBridge 153:b484a57bc302 973 */
AnnaBridge 153:b484a57bc302 974
AnnaBridge 153:b484a57bc302 975 /**
AnnaBridge 153:b484a57bc302 976 \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 153:b484a57bc302 977 */
AnnaBridge 153:b484a57bc302 978 typedef struct
AnnaBridge 153:b484a57bc302 979 {
AnnaBridge 153:b484a57bc302 980 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 153:b484a57bc302 981 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 153:b484a57bc302 982 uint32_t RESERVED0[2U];
AnnaBridge 153:b484a57bc302 983 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 153:b484a57bc302 984 uint32_t RESERVED1[55U];
AnnaBridge 153:b484a57bc302 985 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 153:b484a57bc302 986 uint32_t RESERVED2[131U];
AnnaBridge 153:b484a57bc302 987 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 153:b484a57bc302 988 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 153:b484a57bc302 989 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 153:b484a57bc302 990 uint32_t RESERVED3[759U];
AnnaBridge 153:b484a57bc302 991 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 153:b484a57bc302 992 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 153:b484a57bc302 993 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 153:b484a57bc302 994 uint32_t RESERVED4[1U];
AnnaBridge 153:b484a57bc302 995 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 153:b484a57bc302 996 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 153:b484a57bc302 997 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 153:b484a57bc302 998 uint32_t RESERVED5[39U];
AnnaBridge 153:b484a57bc302 999 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 153:b484a57bc302 1000 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 153:b484a57bc302 1001 uint32_t RESERVED7[8U];
AnnaBridge 153:b484a57bc302 1002 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 153:b484a57bc302 1003 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
AnnaBridge 153:b484a57bc302 1004 } TPI_Type;
AnnaBridge 153:b484a57bc302 1005
AnnaBridge 153:b484a57bc302 1006 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 153:b484a57bc302 1007 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
AnnaBridge 153:b484a57bc302 1008 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
AnnaBridge 153:b484a57bc302 1009
AnnaBridge 153:b484a57bc302 1010 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 153:b484a57bc302 1011 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
AnnaBridge 153:b484a57bc302 1012 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 153:b484a57bc302 1013
AnnaBridge 153:b484a57bc302 1014 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 153:b484a57bc302 1015 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 153:b484a57bc302 1016 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 153:b484a57bc302 1017
AnnaBridge 153:b484a57bc302 1018 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
AnnaBridge 153:b484a57bc302 1019 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 153:b484a57bc302 1020
AnnaBridge 153:b484a57bc302 1021 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
AnnaBridge 153:b484a57bc302 1022 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 153:b484a57bc302 1023
AnnaBridge 153:b484a57bc302 1024 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
AnnaBridge 153:b484a57bc302 1025 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 153:b484a57bc302 1026
AnnaBridge 153:b484a57bc302 1027 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 153:b484a57bc302 1028 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
AnnaBridge 153:b484a57bc302 1029 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 153:b484a57bc302 1030
AnnaBridge 153:b484a57bc302 1031 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
AnnaBridge 153:b484a57bc302 1032 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 153:b484a57bc302 1033
AnnaBridge 153:b484a57bc302 1034 /* TPI TRIGGER Register Definitions */
AnnaBridge 153:b484a57bc302 1035 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
AnnaBridge 153:b484a57bc302 1036 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
AnnaBridge 153:b484a57bc302 1037
AnnaBridge 153:b484a57bc302 1038 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 153:b484a57bc302 1039 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
AnnaBridge 153:b484a57bc302 1040 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
AnnaBridge 153:b484a57bc302 1041
AnnaBridge 153:b484a57bc302 1042 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
AnnaBridge 153:b484a57bc302 1043 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
AnnaBridge 153:b484a57bc302 1044
AnnaBridge 153:b484a57bc302 1045 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
AnnaBridge 153:b484a57bc302 1046 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
AnnaBridge 153:b484a57bc302 1047
AnnaBridge 153:b484a57bc302 1048 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
AnnaBridge 153:b484a57bc302 1049 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
AnnaBridge 153:b484a57bc302 1050
AnnaBridge 153:b484a57bc302 1051 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
AnnaBridge 153:b484a57bc302 1052 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
AnnaBridge 153:b484a57bc302 1053
AnnaBridge 153:b484a57bc302 1054 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
AnnaBridge 153:b484a57bc302 1055 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
AnnaBridge 153:b484a57bc302 1056
AnnaBridge 153:b484a57bc302 1057 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
AnnaBridge 153:b484a57bc302 1058 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
AnnaBridge 153:b484a57bc302 1059
AnnaBridge 153:b484a57bc302 1060 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 153:b484a57bc302 1061 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
AnnaBridge 153:b484a57bc302 1062 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
AnnaBridge 153:b484a57bc302 1063
AnnaBridge 153:b484a57bc302 1064 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 153:b484a57bc302 1065 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
AnnaBridge 153:b484a57bc302 1066 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
AnnaBridge 153:b484a57bc302 1067
AnnaBridge 153:b484a57bc302 1068 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
AnnaBridge 153:b484a57bc302 1069 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
AnnaBridge 153:b484a57bc302 1070
AnnaBridge 153:b484a57bc302 1071 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
AnnaBridge 153:b484a57bc302 1072 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
AnnaBridge 153:b484a57bc302 1073
AnnaBridge 153:b484a57bc302 1074 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
AnnaBridge 153:b484a57bc302 1075 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
AnnaBridge 153:b484a57bc302 1076
AnnaBridge 153:b484a57bc302 1077 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
AnnaBridge 153:b484a57bc302 1078 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
AnnaBridge 153:b484a57bc302 1079
AnnaBridge 153:b484a57bc302 1080 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
AnnaBridge 153:b484a57bc302 1081 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
AnnaBridge 153:b484a57bc302 1082
AnnaBridge 153:b484a57bc302 1083 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
AnnaBridge 153:b484a57bc302 1084 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
AnnaBridge 153:b484a57bc302 1085
AnnaBridge 153:b484a57bc302 1086 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 153:b484a57bc302 1087 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
AnnaBridge 153:b484a57bc302 1088 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
AnnaBridge 153:b484a57bc302 1089
AnnaBridge 153:b484a57bc302 1090 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 153:b484a57bc302 1091 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
AnnaBridge 153:b484a57bc302 1092 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
AnnaBridge 153:b484a57bc302 1093
AnnaBridge 153:b484a57bc302 1094 /* TPI DEVID Register Definitions */
AnnaBridge 153:b484a57bc302 1095 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 153:b484a57bc302 1096 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 153:b484a57bc302 1097
AnnaBridge 153:b484a57bc302 1098 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 153:b484a57bc302 1099 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 153:b484a57bc302 1100
AnnaBridge 153:b484a57bc302 1101 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 153:b484a57bc302 1102 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 153:b484a57bc302 1103
AnnaBridge 153:b484a57bc302 1104 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
AnnaBridge 153:b484a57bc302 1105 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
AnnaBridge 153:b484a57bc302 1106
AnnaBridge 153:b484a57bc302 1107 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
AnnaBridge 153:b484a57bc302 1108 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
AnnaBridge 153:b484a57bc302 1109
AnnaBridge 153:b484a57bc302 1110 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 153:b484a57bc302 1111 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
AnnaBridge 153:b484a57bc302 1112
AnnaBridge 153:b484a57bc302 1113 /* TPI DEVTYPE Register Definitions */
AnnaBridge 153:b484a57bc302 1114 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 153:b484a57bc302 1115 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 153:b484a57bc302 1116
AnnaBridge 153:b484a57bc302 1117 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 153:b484a57bc302 1118 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 153:b484a57bc302 1119
AnnaBridge 153:b484a57bc302 1120 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 153:b484a57bc302 1121
AnnaBridge 153:b484a57bc302 1122
AnnaBridge 153:b484a57bc302 1123 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 153:b484a57bc302 1124 /**
AnnaBridge 153:b484a57bc302 1125 \ingroup CMSIS_core_register
AnnaBridge 153:b484a57bc302 1126 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 153:b484a57bc302 1127 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 153:b484a57bc302 1128 @{
AnnaBridge 153:b484a57bc302 1129 */
AnnaBridge 153:b484a57bc302 1130
AnnaBridge 153:b484a57bc302 1131 /**
AnnaBridge 153:b484a57bc302 1132 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 153:b484a57bc302 1133 */
AnnaBridge 153:b484a57bc302 1134 typedef struct
AnnaBridge 153:b484a57bc302 1135 {
AnnaBridge 153:b484a57bc302 1136 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 153:b484a57bc302 1137 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 153:b484a57bc302 1138 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 153:b484a57bc302 1139 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 153:b484a57bc302 1140 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 153:b484a57bc302 1141 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
AnnaBridge 153:b484a57bc302 1142 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
AnnaBridge 153:b484a57bc302 1143 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
AnnaBridge 153:b484a57bc302 1144 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
AnnaBridge 153:b484a57bc302 1145 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
AnnaBridge 153:b484a57bc302 1146 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
AnnaBridge 153:b484a57bc302 1147 } MPU_Type;
AnnaBridge 153:b484a57bc302 1148
AnnaBridge 153:b484a57bc302 1149 /* MPU Type Register Definitions */
AnnaBridge 153:b484a57bc302 1150 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 153:b484a57bc302 1151 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 153:b484a57bc302 1152
AnnaBridge 153:b484a57bc302 1153 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 153:b484a57bc302 1154 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 153:b484a57bc302 1155
AnnaBridge 153:b484a57bc302 1156 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 153:b484a57bc302 1157 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 153:b484a57bc302 1158
AnnaBridge 153:b484a57bc302 1159 /* MPU Control Register Definitions */
AnnaBridge 153:b484a57bc302 1160 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 153:b484a57bc302 1161 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 153:b484a57bc302 1162
AnnaBridge 153:b484a57bc302 1163 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 153:b484a57bc302 1164 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 153:b484a57bc302 1165
AnnaBridge 153:b484a57bc302 1166 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 153:b484a57bc302 1167 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 153:b484a57bc302 1168
AnnaBridge 153:b484a57bc302 1169 /* MPU Region Number Register Definitions */
AnnaBridge 153:b484a57bc302 1170 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 153:b484a57bc302 1171 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 153:b484a57bc302 1172
AnnaBridge 153:b484a57bc302 1173 /* MPU Region Base Address Register Definitions */
AnnaBridge 153:b484a57bc302 1174 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
AnnaBridge 153:b484a57bc302 1175 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 153:b484a57bc302 1176
AnnaBridge 153:b484a57bc302 1177 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
AnnaBridge 153:b484a57bc302 1178 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 153:b484a57bc302 1179
AnnaBridge 153:b484a57bc302 1180 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
AnnaBridge 153:b484a57bc302 1181 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 153:b484a57bc302 1182
AnnaBridge 153:b484a57bc302 1183 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 153:b484a57bc302 1184 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 153:b484a57bc302 1185 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 153:b484a57bc302 1186
AnnaBridge 153:b484a57bc302 1187 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 153:b484a57bc302 1188 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 153:b484a57bc302 1189
AnnaBridge 153:b484a57bc302 1190 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 153:b484a57bc302 1191 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 153:b484a57bc302 1192
AnnaBridge 153:b484a57bc302 1193 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 153:b484a57bc302 1194 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 153:b484a57bc302 1195
AnnaBridge 153:b484a57bc302 1196 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 153:b484a57bc302 1197 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 153:b484a57bc302 1198
AnnaBridge 153:b484a57bc302 1199 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 153:b484a57bc302 1200 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 153:b484a57bc302 1201
AnnaBridge 153:b484a57bc302 1202 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 153:b484a57bc302 1203 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 153:b484a57bc302 1204
AnnaBridge 153:b484a57bc302 1205 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 153:b484a57bc302 1206 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 153:b484a57bc302 1207
AnnaBridge 153:b484a57bc302 1208 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
AnnaBridge 153:b484a57bc302 1209 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 153:b484a57bc302 1210
AnnaBridge 153:b484a57bc302 1211 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
AnnaBridge 153:b484a57bc302 1212 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 153:b484a57bc302 1213
AnnaBridge 153:b484a57bc302 1214 /*@} end of group CMSIS_MPU */
AnnaBridge 153:b484a57bc302 1215 #endif
AnnaBridge 153:b484a57bc302 1216
AnnaBridge 153:b484a57bc302 1217
AnnaBridge 153:b484a57bc302 1218 /**
AnnaBridge 153:b484a57bc302 1219 \ingroup CMSIS_core_register
AnnaBridge 153:b484a57bc302 1220 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 153:b484a57bc302 1221 \brief Type definitions for the Core Debug Registers
AnnaBridge 153:b484a57bc302 1222 @{
AnnaBridge 153:b484a57bc302 1223 */
AnnaBridge 153:b484a57bc302 1224
AnnaBridge 153:b484a57bc302 1225 /**
AnnaBridge 153:b484a57bc302 1226 \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 153:b484a57bc302 1227 */
AnnaBridge 153:b484a57bc302 1228 typedef struct
AnnaBridge 153:b484a57bc302 1229 {
AnnaBridge 153:b484a57bc302 1230 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 153:b484a57bc302 1231 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 153:b484a57bc302 1232 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 153:b484a57bc302 1233 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 153:b484a57bc302 1234 } CoreDebug_Type;
AnnaBridge 153:b484a57bc302 1235
AnnaBridge 153:b484a57bc302 1236 /* Debug Halting Control and Status Register Definitions */
AnnaBridge 153:b484a57bc302 1237 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 153:b484a57bc302 1238 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 153:b484a57bc302 1239
AnnaBridge 153:b484a57bc302 1240 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 153:b484a57bc302 1241 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 153:b484a57bc302 1242
AnnaBridge 153:b484a57bc302 1243 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 153:b484a57bc302 1244 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 153:b484a57bc302 1245
AnnaBridge 153:b484a57bc302 1246 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 153:b484a57bc302 1247 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 153:b484a57bc302 1248
AnnaBridge 153:b484a57bc302 1249 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 153:b484a57bc302 1250 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 153:b484a57bc302 1251
AnnaBridge 153:b484a57bc302 1252 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 153:b484a57bc302 1253 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 153:b484a57bc302 1254
AnnaBridge 153:b484a57bc302 1255 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 153:b484a57bc302 1256 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 153:b484a57bc302 1257
AnnaBridge 153:b484a57bc302 1258 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
AnnaBridge 153:b484a57bc302 1259 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
AnnaBridge 153:b484a57bc302 1260
AnnaBridge 153:b484a57bc302 1261 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 153:b484a57bc302 1262 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 153:b484a57bc302 1263
AnnaBridge 153:b484a57bc302 1264 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 153:b484a57bc302 1265 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 153:b484a57bc302 1266
AnnaBridge 153:b484a57bc302 1267 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 153:b484a57bc302 1268 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 153:b484a57bc302 1269
AnnaBridge 153:b484a57bc302 1270 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 153:b484a57bc302 1271 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 153:b484a57bc302 1272
AnnaBridge 153:b484a57bc302 1273 /* Debug Core Register Selector Register Definitions */
AnnaBridge 153:b484a57bc302 1274 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 153:b484a57bc302 1275 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 153:b484a57bc302 1276
AnnaBridge 153:b484a57bc302 1277 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 153:b484a57bc302 1278 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 153:b484a57bc302 1279
AnnaBridge 153:b484a57bc302 1280 /* Debug Exception and Monitor Control Register Definitions */
AnnaBridge 153:b484a57bc302 1281 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
AnnaBridge 153:b484a57bc302 1282 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
AnnaBridge 153:b484a57bc302 1283
AnnaBridge 153:b484a57bc302 1284 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
AnnaBridge 153:b484a57bc302 1285 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
AnnaBridge 153:b484a57bc302 1286
AnnaBridge 153:b484a57bc302 1287 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
AnnaBridge 153:b484a57bc302 1288 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
AnnaBridge 153:b484a57bc302 1289
AnnaBridge 153:b484a57bc302 1290 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
AnnaBridge 153:b484a57bc302 1291 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
AnnaBridge 153:b484a57bc302 1292
AnnaBridge 153:b484a57bc302 1293 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
AnnaBridge 153:b484a57bc302 1294 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
AnnaBridge 153:b484a57bc302 1295
AnnaBridge 153:b484a57bc302 1296 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 153:b484a57bc302 1297 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 153:b484a57bc302 1298
AnnaBridge 153:b484a57bc302 1299 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
AnnaBridge 153:b484a57bc302 1300 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
AnnaBridge 153:b484a57bc302 1301
AnnaBridge 153:b484a57bc302 1302 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
AnnaBridge 153:b484a57bc302 1303 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
AnnaBridge 153:b484a57bc302 1304
AnnaBridge 153:b484a57bc302 1305 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
AnnaBridge 153:b484a57bc302 1306 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
AnnaBridge 153:b484a57bc302 1307
AnnaBridge 153:b484a57bc302 1308 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
AnnaBridge 153:b484a57bc302 1309 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
AnnaBridge 153:b484a57bc302 1310
AnnaBridge 153:b484a57bc302 1311 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
AnnaBridge 153:b484a57bc302 1312 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
AnnaBridge 153:b484a57bc302 1313
AnnaBridge 153:b484a57bc302 1314 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
AnnaBridge 153:b484a57bc302 1315 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
AnnaBridge 153:b484a57bc302 1316
AnnaBridge 153:b484a57bc302 1317 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 153:b484a57bc302 1318 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 153:b484a57bc302 1319
AnnaBridge 153:b484a57bc302 1320 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 153:b484a57bc302 1321
AnnaBridge 153:b484a57bc302 1322
AnnaBridge 153:b484a57bc302 1323 /**
AnnaBridge 153:b484a57bc302 1324 \ingroup CMSIS_core_register
AnnaBridge 153:b484a57bc302 1325 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 153:b484a57bc302 1326 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 153:b484a57bc302 1327 @{
AnnaBridge 153:b484a57bc302 1328 */
AnnaBridge 153:b484a57bc302 1329
AnnaBridge 153:b484a57bc302 1330 /**
AnnaBridge 153:b484a57bc302 1331 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 153:b484a57bc302 1332 \param[in] field Name of the register bit field.
AnnaBridge 153:b484a57bc302 1333 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 153:b484a57bc302 1334 \return Masked and shifted value.
AnnaBridge 153:b484a57bc302 1335 */
AnnaBridge 153:b484a57bc302 1336 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 153:b484a57bc302 1337
AnnaBridge 153:b484a57bc302 1338 /**
AnnaBridge 153:b484a57bc302 1339 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 153:b484a57bc302 1340 \param[in] field Name of the register bit field.
AnnaBridge 153:b484a57bc302 1341 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 153:b484a57bc302 1342 \return Masked and shifted bit field value.
AnnaBridge 153:b484a57bc302 1343 */
AnnaBridge 153:b484a57bc302 1344 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 153:b484a57bc302 1345
AnnaBridge 153:b484a57bc302 1346 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 153:b484a57bc302 1347
AnnaBridge 153:b484a57bc302 1348
AnnaBridge 153:b484a57bc302 1349 /**
AnnaBridge 153:b484a57bc302 1350 \ingroup CMSIS_core_register
AnnaBridge 153:b484a57bc302 1351 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 153:b484a57bc302 1352 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 153:b484a57bc302 1353 @{
AnnaBridge 153:b484a57bc302 1354 */
AnnaBridge 153:b484a57bc302 1355
AnnaBridge 153:b484a57bc302 1356 /* Memory mapping of Core Hardware */
AnnaBridge 153:b484a57bc302 1357 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 153:b484a57bc302 1358 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
AnnaBridge 153:b484a57bc302 1359 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 153:b484a57bc302 1360 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 153:b484a57bc302 1361 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 153:b484a57bc302 1362 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 153:b484a57bc302 1363 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 153:b484a57bc302 1364 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 153:b484a57bc302 1365
AnnaBridge 153:b484a57bc302 1366 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 153:b484a57bc302 1367 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 153:b484a57bc302 1368 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 153:b484a57bc302 1369 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 153:b484a57bc302 1370 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
AnnaBridge 153:b484a57bc302 1371 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 153:b484a57bc302 1372 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 153:b484a57bc302 1373 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
AnnaBridge 153:b484a57bc302 1374
AnnaBridge 153:b484a57bc302 1375 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 153:b484a57bc302 1376 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 153:b484a57bc302 1377 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 153:b484a57bc302 1378 #endif
AnnaBridge 153:b484a57bc302 1379
AnnaBridge 153:b484a57bc302 1380 /*@} */
AnnaBridge 153:b484a57bc302 1381
AnnaBridge 153:b484a57bc302 1382
AnnaBridge 153:b484a57bc302 1383
AnnaBridge 153:b484a57bc302 1384 /*******************************************************************************
AnnaBridge 153:b484a57bc302 1385 * Hardware Abstraction Layer
AnnaBridge 153:b484a57bc302 1386 Core Function Interface contains:
AnnaBridge 153:b484a57bc302 1387 - Core NVIC Functions
AnnaBridge 153:b484a57bc302 1388 - Core SysTick Functions
AnnaBridge 153:b484a57bc302 1389 - Core Debug Functions
AnnaBridge 153:b484a57bc302 1390 - Core Register Access Functions
AnnaBridge 153:b484a57bc302 1391 ******************************************************************************/
AnnaBridge 153:b484a57bc302 1392 /**
AnnaBridge 153:b484a57bc302 1393 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 153:b484a57bc302 1394 */
AnnaBridge 153:b484a57bc302 1395
AnnaBridge 153:b484a57bc302 1396
AnnaBridge 153:b484a57bc302 1397
AnnaBridge 153:b484a57bc302 1398 /* ########################## NVIC functions #################################### */
AnnaBridge 153:b484a57bc302 1399 /**
AnnaBridge 153:b484a57bc302 1400 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 153:b484a57bc302 1401 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 153:b484a57bc302 1402 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 153:b484a57bc302 1403 @{
AnnaBridge 153:b484a57bc302 1404 */
AnnaBridge 153:b484a57bc302 1405
AnnaBridge 153:b484a57bc302 1406 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 153:b484a57bc302 1407 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 153:b484a57bc302 1408 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 153:b484a57bc302 1409 #endif
AnnaBridge 153:b484a57bc302 1410 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 153:b484a57bc302 1411 #else
AnnaBridge 153:b484a57bc302 1412 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge 153:b484a57bc302 1413 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge 153:b484a57bc302 1414 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 153:b484a57bc302 1415 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 153:b484a57bc302 1416 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 153:b484a57bc302 1417 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 153:b484a57bc302 1418 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 153:b484a57bc302 1419 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 153:b484a57bc302 1420 #define NVIC_GetActive __NVIC_GetActive
AnnaBridge 153:b484a57bc302 1421 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 153:b484a57bc302 1422 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 153:b484a57bc302 1423 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 153:b484a57bc302 1424 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 153:b484a57bc302 1425
AnnaBridge 153:b484a57bc302 1426 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 153:b484a57bc302 1427 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 153:b484a57bc302 1428 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 153:b484a57bc302 1429 #endif
AnnaBridge 153:b484a57bc302 1430 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 153:b484a57bc302 1431 #else
AnnaBridge 153:b484a57bc302 1432 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 153:b484a57bc302 1433 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 153:b484a57bc302 1434 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 153:b484a57bc302 1435
AnnaBridge 153:b484a57bc302 1436 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 153:b484a57bc302 1437
AnnaBridge 153:b484a57bc302 1438
AnnaBridge 153:b484a57bc302 1439
AnnaBridge 153:b484a57bc302 1440 /**
AnnaBridge 153:b484a57bc302 1441 \brief Set Priority Grouping
AnnaBridge 153:b484a57bc302 1442 \details Sets the priority grouping field using the required unlock sequence.
AnnaBridge 153:b484a57bc302 1443 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge 153:b484a57bc302 1444 Only values from 0..7 are used.
AnnaBridge 153:b484a57bc302 1445 In case of a conflict between priority grouping and available
AnnaBridge 153:b484a57bc302 1446 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 153:b484a57bc302 1447 \param [in] PriorityGroup Priority grouping field.
AnnaBridge 153:b484a57bc302 1448 */
AnnaBridge 153:b484a57bc302 1449 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge 153:b484a57bc302 1450 {
AnnaBridge 153:b484a57bc302 1451 uint32_t reg_value;
AnnaBridge 153:b484a57bc302 1452 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 153:b484a57bc302 1453
AnnaBridge 153:b484a57bc302 1454 reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge 153:b484a57bc302 1455 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge 153:b484a57bc302 1456 reg_value = (reg_value |
AnnaBridge 153:b484a57bc302 1457 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 153:b484a57bc302 1458 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
AnnaBridge 153:b484a57bc302 1459 SCB->AIRCR = reg_value;
AnnaBridge 153:b484a57bc302 1460 }
AnnaBridge 153:b484a57bc302 1461
AnnaBridge 153:b484a57bc302 1462
AnnaBridge 153:b484a57bc302 1463 /**
AnnaBridge 153:b484a57bc302 1464 \brief Get Priority Grouping
AnnaBridge 153:b484a57bc302 1465 \details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge 153:b484a57bc302 1466 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge 153:b484a57bc302 1467 */
AnnaBridge 153:b484a57bc302 1468 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge 153:b484a57bc302 1469 {
AnnaBridge 153:b484a57bc302 1470 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge 153:b484a57bc302 1471 }
AnnaBridge 153:b484a57bc302 1472
AnnaBridge 153:b484a57bc302 1473
AnnaBridge 153:b484a57bc302 1474 /**
AnnaBridge 153:b484a57bc302 1475 \brief Enable Interrupt
AnnaBridge 153:b484a57bc302 1476 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 153:b484a57bc302 1477 \param [in] IRQn Device specific interrupt number.
AnnaBridge 153:b484a57bc302 1478 \note IRQn must not be negative.
AnnaBridge 153:b484a57bc302 1479 */
AnnaBridge 153:b484a57bc302 1480 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 1481 {
AnnaBridge 153:b484a57bc302 1482 if ((int32_t)(IRQn) >= 0)
AnnaBridge 153:b484a57bc302 1483 {
Anna Bridge 169:a7c7b631e539 1484 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 153:b484a57bc302 1485 }
AnnaBridge 153:b484a57bc302 1486 }
AnnaBridge 153:b484a57bc302 1487
AnnaBridge 153:b484a57bc302 1488
AnnaBridge 153:b484a57bc302 1489 /**
AnnaBridge 153:b484a57bc302 1490 \brief Get Interrupt Enable status
AnnaBridge 153:b484a57bc302 1491 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 153:b484a57bc302 1492 \param [in] IRQn Device specific interrupt number.
AnnaBridge 153:b484a57bc302 1493 \return 0 Interrupt is not enabled.
AnnaBridge 153:b484a57bc302 1494 \return 1 Interrupt is enabled.
AnnaBridge 153:b484a57bc302 1495 \note IRQn must not be negative.
AnnaBridge 153:b484a57bc302 1496 */
AnnaBridge 153:b484a57bc302 1497 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 1498 {
AnnaBridge 153:b484a57bc302 1499 if ((int32_t)(IRQn) >= 0)
AnnaBridge 153:b484a57bc302 1500 {
Anna Bridge 169:a7c7b631e539 1501 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 153:b484a57bc302 1502 }
AnnaBridge 153:b484a57bc302 1503 else
AnnaBridge 153:b484a57bc302 1504 {
AnnaBridge 153:b484a57bc302 1505 return(0U);
AnnaBridge 153:b484a57bc302 1506 }
AnnaBridge 153:b484a57bc302 1507 }
AnnaBridge 153:b484a57bc302 1508
AnnaBridge 153:b484a57bc302 1509
AnnaBridge 153:b484a57bc302 1510 /**
AnnaBridge 153:b484a57bc302 1511 \brief Disable Interrupt
AnnaBridge 153:b484a57bc302 1512 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 153:b484a57bc302 1513 \param [in] IRQn Device specific interrupt number.
AnnaBridge 153:b484a57bc302 1514 \note IRQn must not be negative.
AnnaBridge 153:b484a57bc302 1515 */
AnnaBridge 153:b484a57bc302 1516 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 1517 {
AnnaBridge 153:b484a57bc302 1518 if ((int32_t)(IRQn) >= 0)
AnnaBridge 153:b484a57bc302 1519 {
Anna Bridge 169:a7c7b631e539 1520 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 153:b484a57bc302 1521 __DSB();
AnnaBridge 153:b484a57bc302 1522 __ISB();
AnnaBridge 153:b484a57bc302 1523 }
AnnaBridge 153:b484a57bc302 1524 }
AnnaBridge 153:b484a57bc302 1525
AnnaBridge 153:b484a57bc302 1526
AnnaBridge 153:b484a57bc302 1527 /**
AnnaBridge 153:b484a57bc302 1528 \brief Get Pending Interrupt
AnnaBridge 153:b484a57bc302 1529 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 153:b484a57bc302 1530 \param [in] IRQn Device specific interrupt number.
AnnaBridge 153:b484a57bc302 1531 \return 0 Interrupt status is not pending.
AnnaBridge 153:b484a57bc302 1532 \return 1 Interrupt status is pending.
AnnaBridge 153:b484a57bc302 1533 \note IRQn must not be negative.
AnnaBridge 153:b484a57bc302 1534 */
AnnaBridge 153:b484a57bc302 1535 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 1536 {
AnnaBridge 153:b484a57bc302 1537 if ((int32_t)(IRQn) >= 0)
AnnaBridge 153:b484a57bc302 1538 {
Anna Bridge 169:a7c7b631e539 1539 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 153:b484a57bc302 1540 }
AnnaBridge 153:b484a57bc302 1541 else
AnnaBridge 153:b484a57bc302 1542 {
AnnaBridge 153:b484a57bc302 1543 return(0U);
AnnaBridge 153:b484a57bc302 1544 }
AnnaBridge 153:b484a57bc302 1545 }
AnnaBridge 153:b484a57bc302 1546
AnnaBridge 153:b484a57bc302 1547
AnnaBridge 153:b484a57bc302 1548 /**
AnnaBridge 153:b484a57bc302 1549 \brief Set Pending Interrupt
AnnaBridge 153:b484a57bc302 1550 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 153:b484a57bc302 1551 \param [in] IRQn Device specific interrupt number.
AnnaBridge 153:b484a57bc302 1552 \note IRQn must not be negative.
AnnaBridge 153:b484a57bc302 1553 */
AnnaBridge 153:b484a57bc302 1554 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 1555 {
AnnaBridge 153:b484a57bc302 1556 if ((int32_t)(IRQn) >= 0)
AnnaBridge 153:b484a57bc302 1557 {
Anna Bridge 169:a7c7b631e539 1558 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 153:b484a57bc302 1559 }
AnnaBridge 153:b484a57bc302 1560 }
AnnaBridge 153:b484a57bc302 1561
AnnaBridge 153:b484a57bc302 1562
AnnaBridge 153:b484a57bc302 1563 /**
AnnaBridge 153:b484a57bc302 1564 \brief Clear Pending Interrupt
AnnaBridge 153:b484a57bc302 1565 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 153:b484a57bc302 1566 \param [in] IRQn Device specific interrupt number.
AnnaBridge 153:b484a57bc302 1567 \note IRQn must not be negative.
AnnaBridge 153:b484a57bc302 1568 */
AnnaBridge 153:b484a57bc302 1569 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 1570 {
AnnaBridge 153:b484a57bc302 1571 if ((int32_t)(IRQn) >= 0)
AnnaBridge 153:b484a57bc302 1572 {
Anna Bridge 169:a7c7b631e539 1573 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 153:b484a57bc302 1574 }
AnnaBridge 153:b484a57bc302 1575 }
AnnaBridge 153:b484a57bc302 1576
AnnaBridge 153:b484a57bc302 1577
AnnaBridge 153:b484a57bc302 1578 /**
AnnaBridge 153:b484a57bc302 1579 \brief Get Active Interrupt
AnnaBridge 153:b484a57bc302 1580 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge 153:b484a57bc302 1581 \param [in] IRQn Device specific interrupt number.
AnnaBridge 153:b484a57bc302 1582 \return 0 Interrupt status is not active.
AnnaBridge 153:b484a57bc302 1583 \return 1 Interrupt status is active.
AnnaBridge 153:b484a57bc302 1584 \note IRQn must not be negative.
AnnaBridge 153:b484a57bc302 1585 */
AnnaBridge 153:b484a57bc302 1586 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 1587 {
AnnaBridge 153:b484a57bc302 1588 if ((int32_t)(IRQn) >= 0)
AnnaBridge 153:b484a57bc302 1589 {
Anna Bridge 169:a7c7b631e539 1590 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 153:b484a57bc302 1591 }
AnnaBridge 153:b484a57bc302 1592 else
AnnaBridge 153:b484a57bc302 1593 {
AnnaBridge 153:b484a57bc302 1594 return(0U);
AnnaBridge 153:b484a57bc302 1595 }
AnnaBridge 153:b484a57bc302 1596 }
AnnaBridge 153:b484a57bc302 1597
AnnaBridge 153:b484a57bc302 1598
AnnaBridge 153:b484a57bc302 1599 /**
AnnaBridge 153:b484a57bc302 1600 \brief Set Interrupt Priority
AnnaBridge 153:b484a57bc302 1601 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 153:b484a57bc302 1602 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 153:b484a57bc302 1603 or negative to specify a processor exception.
AnnaBridge 153:b484a57bc302 1604 \param [in] IRQn Interrupt number.
AnnaBridge 153:b484a57bc302 1605 \param [in] priority Priority to set.
AnnaBridge 153:b484a57bc302 1606 \note The priority cannot be set for every processor exception.
AnnaBridge 153:b484a57bc302 1607 */
AnnaBridge 153:b484a57bc302 1608 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 153:b484a57bc302 1609 {
AnnaBridge 153:b484a57bc302 1610 if ((int32_t)(IRQn) >= 0)
AnnaBridge 153:b484a57bc302 1611 {
Anna Bridge 169:a7c7b631e539 1612 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 153:b484a57bc302 1613 }
AnnaBridge 153:b484a57bc302 1614 else
AnnaBridge 153:b484a57bc302 1615 {
Anna Bridge 169:a7c7b631e539 1616 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 153:b484a57bc302 1617 }
AnnaBridge 153:b484a57bc302 1618 }
AnnaBridge 153:b484a57bc302 1619
AnnaBridge 153:b484a57bc302 1620
AnnaBridge 153:b484a57bc302 1621 /**
AnnaBridge 153:b484a57bc302 1622 \brief Get Interrupt Priority
AnnaBridge 153:b484a57bc302 1623 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 153:b484a57bc302 1624 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 153:b484a57bc302 1625 or negative to specify a processor exception.
AnnaBridge 153:b484a57bc302 1626 \param [in] IRQn Interrupt number.
AnnaBridge 153:b484a57bc302 1627 \return Interrupt Priority.
AnnaBridge 153:b484a57bc302 1628 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 153:b484a57bc302 1629 */
AnnaBridge 153:b484a57bc302 1630 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 1631 {
AnnaBridge 153:b484a57bc302 1632
AnnaBridge 153:b484a57bc302 1633 if ((int32_t)(IRQn) >= 0)
AnnaBridge 153:b484a57bc302 1634 {
Anna Bridge 169:a7c7b631e539 1635 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 153:b484a57bc302 1636 }
AnnaBridge 153:b484a57bc302 1637 else
AnnaBridge 153:b484a57bc302 1638 {
Anna Bridge 169:a7c7b631e539 1639 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 153:b484a57bc302 1640 }
AnnaBridge 153:b484a57bc302 1641 }
AnnaBridge 153:b484a57bc302 1642
AnnaBridge 153:b484a57bc302 1643
AnnaBridge 153:b484a57bc302 1644 /**
AnnaBridge 153:b484a57bc302 1645 \brief Encode Priority
AnnaBridge 153:b484a57bc302 1646 \details Encodes the priority for an interrupt with the given priority group,
AnnaBridge 153:b484a57bc302 1647 preemptive priority value, and subpriority value.
AnnaBridge 153:b484a57bc302 1648 In case of a conflict between priority grouping and available
AnnaBridge 153:b484a57bc302 1649 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 153:b484a57bc302 1650 \param [in] PriorityGroup Used priority group.
AnnaBridge 153:b484a57bc302 1651 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 153:b484a57bc302 1652 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 153:b484a57bc302 1653 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge 153:b484a57bc302 1654 */
AnnaBridge 153:b484a57bc302 1655 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 153:b484a57bc302 1656 {
AnnaBridge 153:b484a57bc302 1657 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 153:b484a57bc302 1658 uint32_t PreemptPriorityBits;
AnnaBridge 153:b484a57bc302 1659 uint32_t SubPriorityBits;
AnnaBridge 153:b484a57bc302 1660
AnnaBridge 153:b484a57bc302 1661 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 153:b484a57bc302 1662 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 153:b484a57bc302 1663
AnnaBridge 153:b484a57bc302 1664 return (
AnnaBridge 153:b484a57bc302 1665 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
AnnaBridge 153:b484a57bc302 1666 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge 153:b484a57bc302 1667 );
AnnaBridge 153:b484a57bc302 1668 }
AnnaBridge 153:b484a57bc302 1669
AnnaBridge 153:b484a57bc302 1670
AnnaBridge 153:b484a57bc302 1671 /**
AnnaBridge 153:b484a57bc302 1672 \brief Decode Priority
AnnaBridge 153:b484a57bc302 1673 \details Decodes an interrupt priority value with a given priority group to
AnnaBridge 153:b484a57bc302 1674 preemptive priority value and subpriority value.
AnnaBridge 153:b484a57bc302 1675 In case of a conflict between priority grouping and available
AnnaBridge 153:b484a57bc302 1676 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 153:b484a57bc302 1677 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 153:b484a57bc302 1678 \param [in] PriorityGroup Used priority group.
AnnaBridge 153:b484a57bc302 1679 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 153:b484a57bc302 1680 \param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge 153:b484a57bc302 1681 */
AnnaBridge 153:b484a57bc302 1682 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge 153:b484a57bc302 1683 {
AnnaBridge 153:b484a57bc302 1684 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 153:b484a57bc302 1685 uint32_t PreemptPriorityBits;
AnnaBridge 153:b484a57bc302 1686 uint32_t SubPriorityBits;
AnnaBridge 153:b484a57bc302 1687
AnnaBridge 153:b484a57bc302 1688 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 153:b484a57bc302 1689 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 153:b484a57bc302 1690
AnnaBridge 153:b484a57bc302 1691 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge 153:b484a57bc302 1692 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge 153:b484a57bc302 1693 }
AnnaBridge 153:b484a57bc302 1694
AnnaBridge 153:b484a57bc302 1695
AnnaBridge 153:b484a57bc302 1696 /**
AnnaBridge 153:b484a57bc302 1697 \brief Set Interrupt Vector
AnnaBridge 153:b484a57bc302 1698 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 153:b484a57bc302 1699 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 153:b484a57bc302 1700 or negative to specify a processor exception.
AnnaBridge 153:b484a57bc302 1701 VTOR must been relocated to SRAM before.
AnnaBridge 153:b484a57bc302 1702 \param [in] IRQn Interrupt number
AnnaBridge 153:b484a57bc302 1703 \param [in] vector Address of interrupt handler function
AnnaBridge 153:b484a57bc302 1704 */
AnnaBridge 153:b484a57bc302 1705 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 153:b484a57bc302 1706 {
AnnaBridge 153:b484a57bc302 1707 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 153:b484a57bc302 1708 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 153:b484a57bc302 1709 }
AnnaBridge 153:b484a57bc302 1710
AnnaBridge 153:b484a57bc302 1711
AnnaBridge 153:b484a57bc302 1712 /**
AnnaBridge 153:b484a57bc302 1713 \brief Get Interrupt Vector
AnnaBridge 153:b484a57bc302 1714 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 153:b484a57bc302 1715 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 153:b484a57bc302 1716 or negative to specify a processor exception.
AnnaBridge 153:b484a57bc302 1717 \param [in] IRQn Interrupt number.
AnnaBridge 153:b484a57bc302 1718 \return Address of interrupt handler function
AnnaBridge 153:b484a57bc302 1719 */
AnnaBridge 153:b484a57bc302 1720 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 1721 {
AnnaBridge 153:b484a57bc302 1722 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 153:b484a57bc302 1723 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 153:b484a57bc302 1724 }
AnnaBridge 153:b484a57bc302 1725
AnnaBridge 153:b484a57bc302 1726
AnnaBridge 153:b484a57bc302 1727 /**
AnnaBridge 153:b484a57bc302 1728 \brief System Reset
AnnaBridge 153:b484a57bc302 1729 \details Initiates a system reset request to reset the MCU.
AnnaBridge 153:b484a57bc302 1730 */
AnnaBridge 153:b484a57bc302 1731 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 153:b484a57bc302 1732 {
AnnaBridge 153:b484a57bc302 1733 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 153:b484a57bc302 1734 buffered write are completed before reset */
AnnaBridge 153:b484a57bc302 1735 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 153:b484a57bc302 1736 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
AnnaBridge 153:b484a57bc302 1737 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge 153:b484a57bc302 1738 __DSB(); /* Ensure completion of memory access */
AnnaBridge 153:b484a57bc302 1739
AnnaBridge 153:b484a57bc302 1740 for(;;) /* wait until reset */
AnnaBridge 153:b484a57bc302 1741 {
AnnaBridge 153:b484a57bc302 1742 __NOP();
AnnaBridge 153:b484a57bc302 1743 }
AnnaBridge 153:b484a57bc302 1744 }
AnnaBridge 153:b484a57bc302 1745
AnnaBridge 153:b484a57bc302 1746 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 153:b484a57bc302 1747
AnnaBridge 153:b484a57bc302 1748
AnnaBridge 153:b484a57bc302 1749 /* ########################## FPU functions #################################### */
AnnaBridge 153:b484a57bc302 1750 /**
AnnaBridge 153:b484a57bc302 1751 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 153:b484a57bc302 1752 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 153:b484a57bc302 1753 \brief Function that provides FPU type.
AnnaBridge 153:b484a57bc302 1754 @{
AnnaBridge 153:b484a57bc302 1755 */
AnnaBridge 153:b484a57bc302 1756
AnnaBridge 153:b484a57bc302 1757 /**
AnnaBridge 153:b484a57bc302 1758 \brief get FPU type
AnnaBridge 153:b484a57bc302 1759 \details returns the FPU type
AnnaBridge 153:b484a57bc302 1760 \returns
AnnaBridge 153:b484a57bc302 1761 - \b 0: No FPU
AnnaBridge 153:b484a57bc302 1762 - \b 1: Single precision FPU
AnnaBridge 153:b484a57bc302 1763 - \b 2: Double + Single precision FPU
AnnaBridge 153:b484a57bc302 1764 */
AnnaBridge 153:b484a57bc302 1765 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 153:b484a57bc302 1766 {
AnnaBridge 153:b484a57bc302 1767 return 0U; /* No FPU */
AnnaBridge 153:b484a57bc302 1768 }
AnnaBridge 153:b484a57bc302 1769
AnnaBridge 153:b484a57bc302 1770
AnnaBridge 153:b484a57bc302 1771 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 153:b484a57bc302 1772
AnnaBridge 153:b484a57bc302 1773
AnnaBridge 153:b484a57bc302 1774
AnnaBridge 153:b484a57bc302 1775 /* ################################## SysTick function ############################################ */
AnnaBridge 153:b484a57bc302 1776 /**
AnnaBridge 153:b484a57bc302 1777 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 153:b484a57bc302 1778 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 153:b484a57bc302 1779 \brief Functions that configure the System.
AnnaBridge 153:b484a57bc302 1780 @{
AnnaBridge 153:b484a57bc302 1781 */
AnnaBridge 153:b484a57bc302 1782
AnnaBridge 153:b484a57bc302 1783 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 153:b484a57bc302 1784
AnnaBridge 153:b484a57bc302 1785 /**
AnnaBridge 153:b484a57bc302 1786 \brief System Tick Configuration
AnnaBridge 153:b484a57bc302 1787 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 153:b484a57bc302 1788 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 153:b484a57bc302 1789 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 153:b484a57bc302 1790 \return 0 Function succeeded.
AnnaBridge 153:b484a57bc302 1791 \return 1 Function failed.
AnnaBridge 153:b484a57bc302 1792 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 153:b484a57bc302 1793 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 153:b484a57bc302 1794 must contain a vendor-specific implementation of this function.
AnnaBridge 153:b484a57bc302 1795 */
AnnaBridge 153:b484a57bc302 1796 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 153:b484a57bc302 1797 {
AnnaBridge 153:b484a57bc302 1798 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 153:b484a57bc302 1799 {
AnnaBridge 153:b484a57bc302 1800 return (1UL); /* Reload value impossible */
AnnaBridge 153:b484a57bc302 1801 }
AnnaBridge 153:b484a57bc302 1802
AnnaBridge 153:b484a57bc302 1803 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 153:b484a57bc302 1804 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 153:b484a57bc302 1805 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 153:b484a57bc302 1806 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 153:b484a57bc302 1807 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 153:b484a57bc302 1808 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 153:b484a57bc302 1809 return (0UL); /* Function successful */
AnnaBridge 153:b484a57bc302 1810 }
AnnaBridge 153:b484a57bc302 1811
AnnaBridge 153:b484a57bc302 1812 #endif
AnnaBridge 153:b484a57bc302 1813
AnnaBridge 153:b484a57bc302 1814 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 153:b484a57bc302 1815
AnnaBridge 153:b484a57bc302 1816
AnnaBridge 153:b484a57bc302 1817
AnnaBridge 153:b484a57bc302 1818 /* ##################################### Debug In/Output function ########################################### */
AnnaBridge 153:b484a57bc302 1819 /**
AnnaBridge 153:b484a57bc302 1820 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 153:b484a57bc302 1821 \defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge 153:b484a57bc302 1822 \brief Functions that access the ITM debug interface.
AnnaBridge 153:b484a57bc302 1823 @{
AnnaBridge 153:b484a57bc302 1824 */
AnnaBridge 153:b484a57bc302 1825
AnnaBridge 153:b484a57bc302 1826 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
AnnaBridge 153:b484a57bc302 1827 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
AnnaBridge 153:b484a57bc302 1828
AnnaBridge 153:b484a57bc302 1829
AnnaBridge 153:b484a57bc302 1830 /**
AnnaBridge 153:b484a57bc302 1831 \brief ITM Send Character
AnnaBridge 153:b484a57bc302 1832 \details Transmits a character via the ITM channel 0, and
AnnaBridge 153:b484a57bc302 1833 \li Just returns when no debugger is connected that has booked the output.
AnnaBridge 153:b484a57bc302 1834 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge 153:b484a57bc302 1835 \param [in] ch Character to transmit.
AnnaBridge 153:b484a57bc302 1836 \returns Character to transmit.
AnnaBridge 153:b484a57bc302 1837 */
AnnaBridge 153:b484a57bc302 1838 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge 153:b484a57bc302 1839 {
AnnaBridge 153:b484a57bc302 1840 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge 153:b484a57bc302 1841 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge 153:b484a57bc302 1842 {
AnnaBridge 153:b484a57bc302 1843 while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge 153:b484a57bc302 1844 {
AnnaBridge 153:b484a57bc302 1845 __NOP();
AnnaBridge 153:b484a57bc302 1846 }
AnnaBridge 153:b484a57bc302 1847 ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge 153:b484a57bc302 1848 }
AnnaBridge 153:b484a57bc302 1849 return (ch);
AnnaBridge 153:b484a57bc302 1850 }
AnnaBridge 153:b484a57bc302 1851
AnnaBridge 153:b484a57bc302 1852
AnnaBridge 153:b484a57bc302 1853 /**
AnnaBridge 153:b484a57bc302 1854 \brief ITM Receive Character
AnnaBridge 153:b484a57bc302 1855 \details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge 153:b484a57bc302 1856 \return Received character.
AnnaBridge 153:b484a57bc302 1857 \return -1 No character pending.
AnnaBridge 153:b484a57bc302 1858 */
AnnaBridge 153:b484a57bc302 1859 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge 153:b484a57bc302 1860 {
AnnaBridge 153:b484a57bc302 1861 int32_t ch = -1; /* no character available */
AnnaBridge 153:b484a57bc302 1862
AnnaBridge 153:b484a57bc302 1863 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge 153:b484a57bc302 1864 {
AnnaBridge 153:b484a57bc302 1865 ch = ITM_RxBuffer;
AnnaBridge 153:b484a57bc302 1866 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge 153:b484a57bc302 1867 }
AnnaBridge 153:b484a57bc302 1868
AnnaBridge 153:b484a57bc302 1869 return (ch);
AnnaBridge 153:b484a57bc302 1870 }
AnnaBridge 153:b484a57bc302 1871
AnnaBridge 153:b484a57bc302 1872
AnnaBridge 153:b484a57bc302 1873 /**
AnnaBridge 153:b484a57bc302 1874 \brief ITM Check Character
AnnaBridge 153:b484a57bc302 1875 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge 153:b484a57bc302 1876 \return 0 No character available.
AnnaBridge 153:b484a57bc302 1877 \return 1 Character available.
AnnaBridge 153:b484a57bc302 1878 */
AnnaBridge 153:b484a57bc302 1879 __STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge 153:b484a57bc302 1880 {
AnnaBridge 153:b484a57bc302 1881
AnnaBridge 153:b484a57bc302 1882 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge 153:b484a57bc302 1883 {
AnnaBridge 153:b484a57bc302 1884 return (0); /* no character available */
AnnaBridge 153:b484a57bc302 1885 }
AnnaBridge 153:b484a57bc302 1886 else
AnnaBridge 153:b484a57bc302 1887 {
AnnaBridge 153:b484a57bc302 1888 return (1); /* character available */
AnnaBridge 153:b484a57bc302 1889 }
AnnaBridge 153:b484a57bc302 1890 }
AnnaBridge 153:b484a57bc302 1891
AnnaBridge 153:b484a57bc302 1892 /*@} end of CMSIS_core_DebugFunctions */
AnnaBridge 153:b484a57bc302 1893
AnnaBridge 153:b484a57bc302 1894
AnnaBridge 153:b484a57bc302 1895
AnnaBridge 153:b484a57bc302 1896
AnnaBridge 153:b484a57bc302 1897 #ifdef __cplusplus
AnnaBridge 153:b484a57bc302 1898 }
AnnaBridge 153:b484a57bc302 1899 #endif
AnnaBridge 153:b484a57bc302 1900
AnnaBridge 153:b484a57bc302 1901 #endif /* __CORE_SC300_H_DEPENDANT */
AnnaBridge 153:b484a57bc302 1902
AnnaBridge 153:b484a57bc302 1903 #endif /* __CMSIS_GENERIC */