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TARGET_LPC546XX/core_cm7.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:: AnnaBridge
Date:: Thu Sep 06 13:39:34 2018 +0100
Revision:: 170:e95d10626187
Parent:: 169:a7c7b631e539

mbed library. Release version 163

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	153:b484a57bc302	1	/************************************************************************//
AnnaBridge	153:b484a57bc302	2	* @file core_cm7.h
AnnaBridge	153:b484a57bc302	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
Anna Bridge	169:a7c7b631e539	4	* @version V5.0.5
Anna Bridge	169:a7c7b631e539	5	* @date 08. January 2018
AnnaBridge	153:b484a57bc302	6	******************************************************************************/
AnnaBridge	153:b484a57bc302	7	/*
AnnaBridge	153:b484a57bc302	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	153:b484a57bc302	9	*
AnnaBridge	153:b484a57bc302	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	153:b484a57bc302	11	*
AnnaBridge	153:b484a57bc302	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	153:b484a57bc302	13	* not use this file except in compliance with the License.
AnnaBridge	153:b484a57bc302	14	* You may obtain a copy of the License at
AnnaBridge	153:b484a57bc302	15	*
AnnaBridge	153:b484a57bc302	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	153:b484a57bc302	17	*
AnnaBridge	153:b484a57bc302	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	153:b484a57bc302	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	153:b484a57bc302	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	153:b484a57bc302	21	* See the License for the specific language governing permissions and
AnnaBridge	153:b484a57bc302	22	* limitations under the License.
AnnaBridge	153:b484a57bc302	23	*/
AnnaBridge	153:b484a57bc302	24
AnnaBridge	153:b484a57bc302	25	#if defined ( __ICCARM__ )
Anna Bridge	169:a7c7b631e539	26	#pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge	169:a7c7b631e539	27	#elif defined (__clang__)
AnnaBridge	153:b484a57bc302	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	153:b484a57bc302	29	#endif
AnnaBridge	153:b484a57bc302	30
AnnaBridge	153:b484a57bc302	31	#ifndef __CORE_CM7_H_GENERIC
AnnaBridge	153:b484a57bc302	32	#define __CORE_CM7_H_GENERIC
AnnaBridge	153:b484a57bc302	33
AnnaBridge	153:b484a57bc302	34	#include <stdint.h>
AnnaBridge	153:b484a57bc302	35
AnnaBridge	153:b484a57bc302	36	#ifdef __cplusplus
AnnaBridge	153:b484a57bc302	37	extern "C" {
AnnaBridge	153:b484a57bc302	38	#endif
AnnaBridge	153:b484a57bc302	39
AnnaBridge	153:b484a57bc302	40	/**
AnnaBridge	153:b484a57bc302	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	153:b484a57bc302	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	153:b484a57bc302	43
AnnaBridge	153:b484a57bc302	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	153:b484a57bc302	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	153:b484a57bc302	46
AnnaBridge	153:b484a57bc302	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	153:b484a57bc302	48	Unions are used for effective representation of core registers.
AnnaBridge	153:b484a57bc302	49
AnnaBridge	153:b484a57bc302	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	153:b484a57bc302	51	Function-like macros are used to allow more efficient code.
AnnaBridge	153:b484a57bc302	52	*/
AnnaBridge	153:b484a57bc302	53
AnnaBridge	153:b484a57bc302	54
AnnaBridge	153:b484a57bc302	55	/*******************************************************************************
AnnaBridge	153:b484a57bc302	56	* CMSIS definitions
AnnaBridge	153:b484a57bc302	57	******************************************************************************/
AnnaBridge	153:b484a57bc302	58	/**
AnnaBridge	153:b484a57bc302	59	\ingroup Cortex_M7
AnnaBridge	153:b484a57bc302	60	@{
AnnaBridge	153:b484a57bc302	61	*/
AnnaBridge	153:b484a57bc302	62
Anna Bridge	160:5571c4ff569f	63	#include "cmsis_version.h"
Anna Bridge	160:5571c4ff569f	64
AnnaBridge	153:b484a57bc302	65	/* CMSIS CM7 definitions */
Anna Bridge	160:5571c4ff569f	66	#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
Anna Bridge	160:5571c4ff569f	67	#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
AnnaBridge	153:b484a57bc302	68	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) \| \
Anna Bridge	160:5571c4ff569f	69	__CM7_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
AnnaBridge	153:b484a57bc302	70
AnnaBridge	153:b484a57bc302	71	#define __CORTEX_M (7U) /!< Cortex-M Core /
AnnaBridge	153:b484a57bc302	72
AnnaBridge	153:b484a57bc302	73	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	153:b484a57bc302	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge	153:b484a57bc302	75	*/
AnnaBridge	153:b484a57bc302	76	#if defined ( __CC_ARM )
AnnaBridge	153:b484a57bc302	77	#if defined __TARGET_FPU_VFP
AnnaBridge	153:b484a57bc302	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	79	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	80	#else
AnnaBridge	153:b484a57bc302	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	82	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	83	#endif
AnnaBridge	153:b484a57bc302	84	#else
AnnaBridge	153:b484a57bc302	85	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	86	#endif
AnnaBridge	153:b484a57bc302	87
AnnaBridge	153:b484a57bc302	88	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	153:b484a57bc302	89	#if defined __ARM_PCS_VFP
AnnaBridge	153:b484a57bc302	90	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	91	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	92	#else
AnnaBridge	153:b484a57bc302	93	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	94	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	95	#endif
AnnaBridge	153:b484a57bc302	96	#else
AnnaBridge	153:b484a57bc302	97	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	98	#endif
AnnaBridge	153:b484a57bc302	99
AnnaBridge	153:b484a57bc302	100	#elif defined ( __GNUC__ )
AnnaBridge	153:b484a57bc302	101	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	153:b484a57bc302	102	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	103	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	104	#else
AnnaBridge	153:b484a57bc302	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	106	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	107	#endif
AnnaBridge	153:b484a57bc302	108	#else
AnnaBridge	153:b484a57bc302	109	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	110	#endif
AnnaBridge	153:b484a57bc302	111
AnnaBridge	153:b484a57bc302	112	#elif defined ( __ICCARM__ )
AnnaBridge	153:b484a57bc302	113	#if defined __ARMVFP__
AnnaBridge	153:b484a57bc302	114	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	115	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	116	#else
AnnaBridge	153:b484a57bc302	117	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	118	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	119	#endif
AnnaBridge	153:b484a57bc302	120	#else
AnnaBridge	153:b484a57bc302	121	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	122	#endif
AnnaBridge	153:b484a57bc302	123
AnnaBridge	153:b484a57bc302	124	#elif defined ( __TI_ARM__ )
AnnaBridge	153:b484a57bc302	125	#if defined __TI_VFP_SUPPORT__
AnnaBridge	153:b484a57bc302	126	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	127	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	128	#else
AnnaBridge	153:b484a57bc302	129	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	130	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	131	#endif
AnnaBridge	153:b484a57bc302	132	#else
AnnaBridge	153:b484a57bc302	133	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	134	#endif
AnnaBridge	153:b484a57bc302	135
AnnaBridge	153:b484a57bc302	136	#elif defined ( __TASKING__ )
AnnaBridge	153:b484a57bc302	137	#if defined __FPU_VFP__
AnnaBridge	153:b484a57bc302	138	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	139	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	140	#else
AnnaBridge	153:b484a57bc302	141	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	142	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	143	#endif
AnnaBridge	153:b484a57bc302	144	#else
AnnaBridge	153:b484a57bc302	145	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	146	#endif
AnnaBridge	153:b484a57bc302	147
AnnaBridge	153:b484a57bc302	148	#elif defined ( __CSMC__ )
AnnaBridge	153:b484a57bc302	149	#if ( __CSMC__ & 0x400U)
AnnaBridge	153:b484a57bc302	150	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	151	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	152	#else
AnnaBridge	153:b484a57bc302	153	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	154	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	155	#endif
AnnaBridge	153:b484a57bc302	156	#else
AnnaBridge	153:b484a57bc302	157	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	158	#endif
AnnaBridge	153:b484a57bc302	159
AnnaBridge	153:b484a57bc302	160	#endif
AnnaBridge	153:b484a57bc302	161
AnnaBridge	153:b484a57bc302	162	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	153:b484a57bc302	163
AnnaBridge	153:b484a57bc302	164
AnnaBridge	153:b484a57bc302	165	#ifdef __cplusplus
AnnaBridge	153:b484a57bc302	166	}
AnnaBridge	153:b484a57bc302	167	#endif
AnnaBridge	153:b484a57bc302	168
AnnaBridge	153:b484a57bc302	169	#endif /* __CORE_CM7_H_GENERIC */
AnnaBridge	153:b484a57bc302	170
AnnaBridge	153:b484a57bc302	171	#ifndef __CMSIS_GENERIC
AnnaBridge	153:b484a57bc302	172
AnnaBridge	153:b484a57bc302	173	#ifndef __CORE_CM7_H_DEPENDANT
AnnaBridge	153:b484a57bc302	174	#define __CORE_CM7_H_DEPENDANT
AnnaBridge	153:b484a57bc302	175
AnnaBridge	153:b484a57bc302	176	#ifdef __cplusplus
AnnaBridge	153:b484a57bc302	177	extern "C" {
AnnaBridge	153:b484a57bc302	178	#endif
AnnaBridge	153:b484a57bc302	179
AnnaBridge	153:b484a57bc302	180	/* check device defines and use defaults */
AnnaBridge	153:b484a57bc302	181	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	153:b484a57bc302	182	#ifndef __CM7_REV
AnnaBridge	153:b484a57bc302	183	#define __CM7_REV 0x0000U
AnnaBridge	153:b484a57bc302	184	#warning "__CM7_REV not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	185	#endif
AnnaBridge	153:b484a57bc302	186
AnnaBridge	153:b484a57bc302	187	#ifndef __FPU_PRESENT
AnnaBridge	153:b484a57bc302	188	#define __FPU_PRESENT 0U
AnnaBridge	153:b484a57bc302	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	190	#endif
AnnaBridge	153:b484a57bc302	191
AnnaBridge	153:b484a57bc302	192	#ifndef __MPU_PRESENT
AnnaBridge	153:b484a57bc302	193	#define __MPU_PRESENT 0U
AnnaBridge	153:b484a57bc302	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	195	#endif
AnnaBridge	153:b484a57bc302	196
AnnaBridge	153:b484a57bc302	197	#ifndef __ICACHE_PRESENT
AnnaBridge	153:b484a57bc302	198	#define __ICACHE_PRESENT 0U
AnnaBridge	153:b484a57bc302	199	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	200	#endif
AnnaBridge	153:b484a57bc302	201
AnnaBridge	153:b484a57bc302	202	#ifndef __DCACHE_PRESENT
AnnaBridge	153:b484a57bc302	203	#define __DCACHE_PRESENT 0U
AnnaBridge	153:b484a57bc302	204	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	205	#endif
AnnaBridge	153:b484a57bc302	206
AnnaBridge	153:b484a57bc302	207	#ifndef __DTCM_PRESENT
AnnaBridge	153:b484a57bc302	208	#define __DTCM_PRESENT 0U
AnnaBridge	153:b484a57bc302	209	#warning "__DTCM_PRESENT not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	210	#endif
AnnaBridge	153:b484a57bc302	211
AnnaBridge	153:b484a57bc302	212	#ifndef __NVIC_PRIO_BITS
AnnaBridge	153:b484a57bc302	213	#define __NVIC_PRIO_BITS 3U
AnnaBridge	153:b484a57bc302	214	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	215	#endif
AnnaBridge	153:b484a57bc302	216
AnnaBridge	153:b484a57bc302	217	#ifndef __Vendor_SysTickConfig
AnnaBridge	153:b484a57bc302	218	#define __Vendor_SysTickConfig 0U
AnnaBridge	153:b484a57bc302	219	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	220	#endif
AnnaBridge	153:b484a57bc302	221	#endif
AnnaBridge	153:b484a57bc302	222
AnnaBridge	153:b484a57bc302	223	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	153:b484a57bc302	224	/**
AnnaBridge	153:b484a57bc302	225	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	153:b484a57bc302	226
AnnaBridge	153:b484a57bc302	227	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	153:b484a57bc302	228	\li to specify the access to peripheral variables.
AnnaBridge	153:b484a57bc302	229	\li for automatic generation of peripheral register debug information.
AnnaBridge	153:b484a57bc302	230	*/
AnnaBridge	153:b484a57bc302	231	#ifdef __cplusplus
AnnaBridge	153:b484a57bc302	232	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	153:b484a57bc302	233	#else
AnnaBridge	153:b484a57bc302	234	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	153:b484a57bc302	235	#endif
AnnaBridge	153:b484a57bc302	236	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	153:b484a57bc302	237	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	153:b484a57bc302	238
AnnaBridge	153:b484a57bc302	239	/* following defines should be used for structure members */
AnnaBridge	153:b484a57bc302	240	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	153:b484a57bc302	241	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	153:b484a57bc302	242	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	153:b484a57bc302	243
AnnaBridge	153:b484a57bc302	244	/@} end of group Cortex_M7 /
AnnaBridge	153:b484a57bc302	245
AnnaBridge	153:b484a57bc302	246
AnnaBridge	153:b484a57bc302	247
AnnaBridge	153:b484a57bc302	248	/*******************************************************************************
AnnaBridge	153:b484a57bc302	249	* Register Abstraction
AnnaBridge	153:b484a57bc302	250	Core Register contain:
AnnaBridge	153:b484a57bc302	251	- Core Register
AnnaBridge	153:b484a57bc302	252	- Core NVIC Register
AnnaBridge	153:b484a57bc302	253	- Core SCB Register
AnnaBridge	153:b484a57bc302	254	- Core SysTick Register
AnnaBridge	153:b484a57bc302	255	- Core Debug Register
AnnaBridge	153:b484a57bc302	256	- Core MPU Register
AnnaBridge	153:b484a57bc302	257	- Core FPU Register
AnnaBridge	153:b484a57bc302	258	******************************************************************************/
AnnaBridge	153:b484a57bc302	259	/**
AnnaBridge	153:b484a57bc302	260	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	153:b484a57bc302	261	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	153:b484a57bc302	262	*/
AnnaBridge	153:b484a57bc302	263
AnnaBridge	153:b484a57bc302	264	/**
AnnaBridge	153:b484a57bc302	265	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	266	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	153:b484a57bc302	267	\brief Core Register type definitions.
AnnaBridge	153:b484a57bc302	268	@{
AnnaBridge	153:b484a57bc302	269	*/
AnnaBridge	153:b484a57bc302	270
AnnaBridge	153:b484a57bc302	271	/**
AnnaBridge	153:b484a57bc302	272	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	153:b484a57bc302	273	*/
AnnaBridge	153:b484a57bc302	274	typedef union
AnnaBridge	153:b484a57bc302	275	{
AnnaBridge	153:b484a57bc302	276	struct
AnnaBridge	153:b484a57bc302	277	{
AnnaBridge	153:b484a57bc302	278	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
AnnaBridge	153:b484a57bc302	279	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	153:b484a57bc302	280	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
AnnaBridge	153:b484a57bc302	281	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	153:b484a57bc302	282	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	153:b484a57bc302	283	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	153:b484a57bc302	284	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	153:b484a57bc302	285	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	153:b484a57bc302	286	} b; /!< Structure used for bit access /
AnnaBridge	153:b484a57bc302	287	uint32_t w; /!< Type used for word access /
AnnaBridge	153:b484a57bc302	288	} APSR_Type;
AnnaBridge	153:b484a57bc302	289
AnnaBridge	153:b484a57bc302	290	/* APSR Register Definitions */
AnnaBridge	153:b484a57bc302	291	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	153:b484a57bc302	292	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	153:b484a57bc302	293
AnnaBridge	153:b484a57bc302	294	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	153:b484a57bc302	295	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	153:b484a57bc302	296
AnnaBridge	153:b484a57bc302	297	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	153:b484a57bc302	298	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	153:b484a57bc302	299
AnnaBridge	153:b484a57bc302	300	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	153:b484a57bc302	301	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	153:b484a57bc302	302
AnnaBridge	153:b484a57bc302	303	#define APSR_Q_Pos 27U /!< APSR: Q Position /
AnnaBridge	153:b484a57bc302	304	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
AnnaBridge	153:b484a57bc302	305
AnnaBridge	153:b484a57bc302	306	#define APSR_GE_Pos 16U /!< APSR: GE Position /
AnnaBridge	153:b484a57bc302	307	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
AnnaBridge	153:b484a57bc302	308
AnnaBridge	153:b484a57bc302	309
AnnaBridge	153:b484a57bc302	310	/**
AnnaBridge	153:b484a57bc302	311	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	153:b484a57bc302	312	*/
AnnaBridge	153:b484a57bc302	313	typedef union
AnnaBridge	153:b484a57bc302	314	{
AnnaBridge	153:b484a57bc302	315	struct
AnnaBridge	153:b484a57bc302	316	{
AnnaBridge	153:b484a57bc302	317	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	153:b484a57bc302	318	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	153:b484a57bc302	319	} b; /!< Structure used for bit access /
AnnaBridge	153:b484a57bc302	320	uint32_t w; /!< Type used for word access /
AnnaBridge	153:b484a57bc302	321	} IPSR_Type;
AnnaBridge	153:b484a57bc302	322
AnnaBridge	153:b484a57bc302	323	/* IPSR Register Definitions */
AnnaBridge	153:b484a57bc302	324	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	153:b484a57bc302	325	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	153:b484a57bc302	326
AnnaBridge	153:b484a57bc302	327
AnnaBridge	153:b484a57bc302	328	/**
AnnaBridge	153:b484a57bc302	329	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	153:b484a57bc302	330	*/
AnnaBridge	153:b484a57bc302	331	typedef union
AnnaBridge	153:b484a57bc302	332	{
AnnaBridge	153:b484a57bc302	333	struct
AnnaBridge	153:b484a57bc302	334	{
AnnaBridge	153:b484a57bc302	335	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	153:b484a57bc302	336	uint32_t _reserved0:1; /!< bit: 9 Reserved /
AnnaBridge	153:b484a57bc302	337	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
AnnaBridge	153:b484a57bc302	338	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	153:b484a57bc302	339	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
AnnaBridge	153:b484a57bc302	340	uint32_t T:1; /!< bit: 24 Thumb bit /
AnnaBridge	153:b484a57bc302	341	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
AnnaBridge	153:b484a57bc302	342	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	153:b484a57bc302	343	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	153:b484a57bc302	344	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	153:b484a57bc302	345	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	153:b484a57bc302	346	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	153:b484a57bc302	347	} b; /!< Structure used for bit access /
AnnaBridge	153:b484a57bc302	348	uint32_t w; /!< Type used for word access /
AnnaBridge	153:b484a57bc302	349	} xPSR_Type;
AnnaBridge	153:b484a57bc302	350
AnnaBridge	153:b484a57bc302	351	/* xPSR Register Definitions */
AnnaBridge	153:b484a57bc302	352	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	153:b484a57bc302	353	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	153:b484a57bc302	354
AnnaBridge	153:b484a57bc302	355	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	153:b484a57bc302	356	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	153:b484a57bc302	357
AnnaBridge	153:b484a57bc302	358	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	153:b484a57bc302	359	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	153:b484a57bc302	360
AnnaBridge	153:b484a57bc302	361	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	153:b484a57bc302	362	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	153:b484a57bc302	363
AnnaBridge	153:b484a57bc302	364	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
AnnaBridge	153:b484a57bc302	365	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
AnnaBridge	153:b484a57bc302	366
AnnaBridge	153:b484a57bc302	367	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
AnnaBridge	153:b484a57bc302	368	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
AnnaBridge	153:b484a57bc302	369
AnnaBridge	153:b484a57bc302	370	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	153:b484a57bc302	371	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	153:b484a57bc302	372
AnnaBridge	153:b484a57bc302	373	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
AnnaBridge	153:b484a57bc302	374	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
AnnaBridge	153:b484a57bc302	375
AnnaBridge	153:b484a57bc302	376	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
AnnaBridge	153:b484a57bc302	377	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
AnnaBridge	153:b484a57bc302	378
AnnaBridge	153:b484a57bc302	379	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	153:b484a57bc302	380	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	153:b484a57bc302	381
AnnaBridge	153:b484a57bc302	382
AnnaBridge	153:b484a57bc302	383	/**
AnnaBridge	153:b484a57bc302	384	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	153:b484a57bc302	385	*/
AnnaBridge	153:b484a57bc302	386	typedef union
AnnaBridge	153:b484a57bc302	387	{
AnnaBridge	153:b484a57bc302	388	struct
AnnaBridge	153:b484a57bc302	389	{
AnnaBridge	153:b484a57bc302	390	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	153:b484a57bc302	391	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
AnnaBridge	153:b484a57bc302	392	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
AnnaBridge	153:b484a57bc302	393	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
AnnaBridge	153:b484a57bc302	394	} b; /!< Structure used for bit access /
AnnaBridge	153:b484a57bc302	395	uint32_t w; /!< Type used for word access /
AnnaBridge	153:b484a57bc302	396	} CONTROL_Type;
AnnaBridge	153:b484a57bc302	397
AnnaBridge	153:b484a57bc302	398	/* CONTROL Register Definitions */
AnnaBridge	153:b484a57bc302	399	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
AnnaBridge	153:b484a57bc302	400	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
AnnaBridge	153:b484a57bc302	401
AnnaBridge	153:b484a57bc302	402	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	153:b484a57bc302	403	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	153:b484a57bc302	404
AnnaBridge	153:b484a57bc302	405	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	153:b484a57bc302	406	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	153:b484a57bc302	407
AnnaBridge	153:b484a57bc302	408	/@} end of group CMSIS_CORE /
AnnaBridge	153:b484a57bc302	409
AnnaBridge	153:b484a57bc302	410
AnnaBridge	153:b484a57bc302	411	/**
AnnaBridge	153:b484a57bc302	412	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	413	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	153:b484a57bc302	414	\brief Type definitions for the NVIC Registers
AnnaBridge	153:b484a57bc302	415	@{
AnnaBridge	153:b484a57bc302	416	*/
AnnaBridge	153:b484a57bc302	417
AnnaBridge	153:b484a57bc302	418	/**
AnnaBridge	153:b484a57bc302	419	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	153:b484a57bc302	420	*/
AnnaBridge	153:b484a57bc302	421	typedef struct
AnnaBridge	153:b484a57bc302	422	{
AnnaBridge	153:b484a57bc302	423	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	153:b484a57bc302	424	uint32_t RESERVED0[24U];
AnnaBridge	153:b484a57bc302	425	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	153:b484a57bc302	426	uint32_t RSERVED1[24U];
AnnaBridge	153:b484a57bc302	427	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	153:b484a57bc302	428	uint32_t RESERVED2[24U];
AnnaBridge	153:b484a57bc302	429	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	153:b484a57bc302	430	uint32_t RESERVED3[24U];
AnnaBridge	153:b484a57bc302	431	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	153:b484a57bc302	432	uint32_t RESERVED4[56U];
AnnaBridge	153:b484a57bc302	433	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	153:b484a57bc302	434	uint32_t RESERVED5[644U];
AnnaBridge	153:b484a57bc302	435	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
AnnaBridge	153:b484a57bc302	436	} NVIC_Type;
AnnaBridge	153:b484a57bc302	437
AnnaBridge	153:b484a57bc302	438	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	153:b484a57bc302	439	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
AnnaBridge	153:b484a57bc302	440	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
AnnaBridge	153:b484a57bc302	441
AnnaBridge	153:b484a57bc302	442	/@} end of group CMSIS_NVIC /
AnnaBridge	153:b484a57bc302	443
AnnaBridge	153:b484a57bc302	444
AnnaBridge	153:b484a57bc302	445	/**
AnnaBridge	153:b484a57bc302	446	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	447	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	153:b484a57bc302	448	\brief Type definitions for the System Control Block Registers
AnnaBridge	153:b484a57bc302	449	@{
AnnaBridge	153:b484a57bc302	450	*/
AnnaBridge	153:b484a57bc302	451
AnnaBridge	153:b484a57bc302	452	/**
AnnaBridge	153:b484a57bc302	453	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	153:b484a57bc302	454	*/
AnnaBridge	153:b484a57bc302	455	typedef struct
AnnaBridge	153:b484a57bc302	456	{
AnnaBridge	153:b484a57bc302	457	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	153:b484a57bc302	458	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	153:b484a57bc302	459	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	153:b484a57bc302	460	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	153:b484a57bc302	461	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	153:b484a57bc302	462	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	153:b484a57bc302	463	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	153:b484a57bc302	464	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	153:b484a57bc302	465	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	153:b484a57bc302	466	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	153:b484a57bc302	467	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	153:b484a57bc302	468	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	153:b484a57bc302	469	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	153:b484a57bc302	470	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	153:b484a57bc302	471	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	153:b484a57bc302	472	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	153:b484a57bc302	473	__IM uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	153:b484a57bc302	474	__IM uint32_t ID_MFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	153:b484a57bc302	475	__IM uint32_t ID_ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	153:b484a57bc302	476	uint32_t RESERVED0[1U];
AnnaBridge	153:b484a57bc302	477	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
AnnaBridge	153:b484a57bc302	478	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
AnnaBridge	153:b484a57bc302	479	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
AnnaBridge	153:b484a57bc302	480	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
AnnaBridge	153:b484a57bc302	481	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	153:b484a57bc302	482	uint32_t RESERVED3[93U];
AnnaBridge	153:b484a57bc302	483	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
AnnaBridge	153:b484a57bc302	484	uint32_t RESERVED4[15U];
AnnaBridge	153:b484a57bc302	485	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
AnnaBridge	153:b484a57bc302	486	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
Anna Bridge	160:5571c4ff569f	487	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
AnnaBridge	153:b484a57bc302	488	uint32_t RESERVED5[1U];
AnnaBridge	153:b484a57bc302	489	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
AnnaBridge	153:b484a57bc302	490	uint32_t RESERVED6[1U];
AnnaBridge	153:b484a57bc302	491	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
AnnaBridge	153:b484a57bc302	492	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
AnnaBridge	153:b484a57bc302	493	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
AnnaBridge	153:b484a57bc302	494	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
AnnaBridge	153:b484a57bc302	495	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
AnnaBridge	153:b484a57bc302	496	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
AnnaBridge	153:b484a57bc302	497	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
AnnaBridge	153:b484a57bc302	498	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
AnnaBridge	153:b484a57bc302	499	uint32_t RESERVED7[6U];
AnnaBridge	153:b484a57bc302	500	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
AnnaBridge	153:b484a57bc302	501	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
AnnaBridge	153:b484a57bc302	502	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
AnnaBridge	153:b484a57bc302	503	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
AnnaBridge	153:b484a57bc302	504	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
AnnaBridge	153:b484a57bc302	505	uint32_t RESERVED8[1U];
AnnaBridge	153:b484a57bc302	506	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
AnnaBridge	153:b484a57bc302	507	} SCB_Type;
AnnaBridge	153:b484a57bc302	508
AnnaBridge	153:b484a57bc302	509	/* SCB CPUID Register Definitions */
AnnaBridge	153:b484a57bc302	510	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	153:b484a57bc302	511	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	153:b484a57bc302	512
AnnaBridge	153:b484a57bc302	513	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	153:b484a57bc302	514	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	153:b484a57bc302	515
AnnaBridge	153:b484a57bc302	516	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	153:b484a57bc302	517	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	153:b484a57bc302	518
AnnaBridge	153:b484a57bc302	519	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	153:b484a57bc302	520	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	153:b484a57bc302	521
AnnaBridge	153:b484a57bc302	522	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	153:b484a57bc302	523	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	153:b484a57bc302	524
AnnaBridge	153:b484a57bc302	525	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	153:b484a57bc302	526	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
AnnaBridge	153:b484a57bc302	527	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
AnnaBridge	153:b484a57bc302	528
AnnaBridge	153:b484a57bc302	529	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	153:b484a57bc302	530	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	153:b484a57bc302	531
AnnaBridge	153:b484a57bc302	532	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	153:b484a57bc302	533	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	153:b484a57bc302	534
AnnaBridge	153:b484a57bc302	535	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	153:b484a57bc302	536	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	153:b484a57bc302	537
AnnaBridge	153:b484a57bc302	538	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	153:b484a57bc302	539	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	153:b484a57bc302	540
AnnaBridge	153:b484a57bc302	541	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	153:b484a57bc302	542	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	153:b484a57bc302	543
AnnaBridge	153:b484a57bc302	544	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	153:b484a57bc302	545	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	153:b484a57bc302	546
AnnaBridge	153:b484a57bc302	547	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	153:b484a57bc302	548	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	153:b484a57bc302	549
AnnaBridge	153:b484a57bc302	550	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	153:b484a57bc302	551	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	153:b484a57bc302	552
AnnaBridge	153:b484a57bc302	553	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	153:b484a57bc302	554	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	153:b484a57bc302	555
AnnaBridge	153:b484a57bc302	556	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	153:b484a57bc302	557	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	153:b484a57bc302	558	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	153:b484a57bc302	559
AnnaBridge	153:b484a57bc302	560	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	153:b484a57bc302	561	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	153:b484a57bc302	562	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	153:b484a57bc302	563
AnnaBridge	153:b484a57bc302	564	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	153:b484a57bc302	565	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	153:b484a57bc302	566
AnnaBridge	153:b484a57bc302	567	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	153:b484a57bc302	568	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	153:b484a57bc302	569
AnnaBridge	153:b484a57bc302	570	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
AnnaBridge	153:b484a57bc302	571	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
AnnaBridge	153:b484a57bc302	572
AnnaBridge	153:b484a57bc302	573	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	153:b484a57bc302	574	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	153:b484a57bc302	575
AnnaBridge	153:b484a57bc302	576	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	153:b484a57bc302	577	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	153:b484a57bc302	578
AnnaBridge	153:b484a57bc302	579	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
AnnaBridge	153:b484a57bc302	580	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
AnnaBridge	153:b484a57bc302	581
AnnaBridge	153:b484a57bc302	582	/* SCB System Control Register Definitions */
AnnaBridge	153:b484a57bc302	583	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	153:b484a57bc302	584	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	153:b484a57bc302	585
AnnaBridge	153:b484a57bc302	586	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	153:b484a57bc302	587	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	153:b484a57bc302	588
AnnaBridge	153:b484a57bc302	589	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	153:b484a57bc302	590	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	153:b484a57bc302	591
AnnaBridge	153:b484a57bc302	592	/* SCB Configuration Control Register Definitions */
AnnaBridge	153:b484a57bc302	593	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: Branch prediction enable bit Position /
AnnaBridge	153:b484a57bc302	594	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
AnnaBridge	153:b484a57bc302	595
AnnaBridge	153:b484a57bc302	596	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: Instruction cache enable bit Position /
AnnaBridge	153:b484a57bc302	597	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
AnnaBridge	153:b484a57bc302	598
AnnaBridge	153:b484a57bc302	599	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: Cache enable bit Position /
AnnaBridge	153:b484a57bc302	600	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
AnnaBridge	153:b484a57bc302	601
AnnaBridge	153:b484a57bc302	602	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
AnnaBridge	153:b484a57bc302	603	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
AnnaBridge	153:b484a57bc302	604
AnnaBridge	153:b484a57bc302	605	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	153:b484a57bc302	606	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	153:b484a57bc302	607
AnnaBridge	153:b484a57bc302	608	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	153:b484a57bc302	609	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	153:b484a57bc302	610
AnnaBridge	153:b484a57bc302	611	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	153:b484a57bc302	612	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	153:b484a57bc302	613
AnnaBridge	153:b484a57bc302	614	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	153:b484a57bc302	615	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	153:b484a57bc302	616
AnnaBridge	153:b484a57bc302	617	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
AnnaBridge	153:b484a57bc302	618	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
AnnaBridge	153:b484a57bc302	619
AnnaBridge	153:b484a57bc302	620	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	153:b484a57bc302	621	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
AnnaBridge	153:b484a57bc302	622	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
AnnaBridge	153:b484a57bc302	623
AnnaBridge	153:b484a57bc302	624	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
AnnaBridge	153:b484a57bc302	625	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
AnnaBridge	153:b484a57bc302	626
AnnaBridge	153:b484a57bc302	627	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
AnnaBridge	153:b484a57bc302	628	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
AnnaBridge	153:b484a57bc302	629
AnnaBridge	153:b484a57bc302	630	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	153:b484a57bc302	631	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	153:b484a57bc302	632
AnnaBridge	153:b484a57bc302	633	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
AnnaBridge	153:b484a57bc302	634	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
AnnaBridge	153:b484a57bc302	635
AnnaBridge	153:b484a57bc302	636	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
AnnaBridge	153:b484a57bc302	637	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
AnnaBridge	153:b484a57bc302	638
AnnaBridge	153:b484a57bc302	639	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
AnnaBridge	153:b484a57bc302	640	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
AnnaBridge	153:b484a57bc302	641
AnnaBridge	153:b484a57bc302	642	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	153:b484a57bc302	643	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	153:b484a57bc302	644
AnnaBridge	153:b484a57bc302	645	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	153:b484a57bc302	646	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	153:b484a57bc302	647
AnnaBridge	153:b484a57bc302	648	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
AnnaBridge	153:b484a57bc302	649	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
AnnaBridge	153:b484a57bc302	650
AnnaBridge	153:b484a57bc302	651	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	153:b484a57bc302	652	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	153:b484a57bc302	653
AnnaBridge	153:b484a57bc302	654	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
AnnaBridge	153:b484a57bc302	655	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
AnnaBridge	153:b484a57bc302	656
AnnaBridge	153:b484a57bc302	657	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
AnnaBridge	153:b484a57bc302	658	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
AnnaBridge	153:b484a57bc302	659
AnnaBridge	153:b484a57bc302	660	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
AnnaBridge	153:b484a57bc302	661	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
AnnaBridge	153:b484a57bc302	662
AnnaBridge	153:b484a57bc302	663	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	153:b484a57bc302	664	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
AnnaBridge	153:b484a57bc302	665	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
AnnaBridge	153:b484a57bc302	666
AnnaBridge	153:b484a57bc302	667	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
AnnaBridge	153:b484a57bc302	668	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
AnnaBridge	153:b484a57bc302	669
AnnaBridge	153:b484a57bc302	670	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
AnnaBridge	153:b484a57bc302	671	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
AnnaBridge	153:b484a57bc302	672
AnnaBridge	153:b484a57bc302	673	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	153:b484a57bc302	674	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	153:b484a57bc302	675	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	153:b484a57bc302	676
AnnaBridge	153:b484a57bc302	677	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
AnnaBridge	153:b484a57bc302	678	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
AnnaBridge	153:b484a57bc302	679
AnnaBridge	153:b484a57bc302	680	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	153:b484a57bc302	681	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	153:b484a57bc302	682
AnnaBridge	153:b484a57bc302	683	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	153:b484a57bc302	684	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	153:b484a57bc302	685
AnnaBridge	153:b484a57bc302	686	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	153:b484a57bc302	687	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	153:b484a57bc302	688
AnnaBridge	153:b484a57bc302	689	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	153:b484a57bc302	690	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	153:b484a57bc302	691
AnnaBridge	153:b484a57bc302	692	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	153:b484a57bc302	693	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	153:b484a57bc302	694	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	153:b484a57bc302	695
AnnaBridge	153:b484a57bc302	696	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
AnnaBridge	153:b484a57bc302	697	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
AnnaBridge	153:b484a57bc302	698
AnnaBridge	153:b484a57bc302	699	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	153:b484a57bc302	700	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	153:b484a57bc302	701
AnnaBridge	153:b484a57bc302	702	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	153:b484a57bc302	703	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	153:b484a57bc302	704
AnnaBridge	153:b484a57bc302	705	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	153:b484a57bc302	706	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	153:b484a57bc302	707
AnnaBridge	153:b484a57bc302	708	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	153:b484a57bc302	709	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	153:b484a57bc302	710
AnnaBridge	153:b484a57bc302	711	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	153:b484a57bc302	712	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	153:b484a57bc302	713
AnnaBridge	153:b484a57bc302	714	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	153:b484a57bc302	715	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	153:b484a57bc302	716	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	153:b484a57bc302	717
AnnaBridge	153:b484a57bc302	718	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	153:b484a57bc302	719	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	153:b484a57bc302	720
AnnaBridge	153:b484a57bc302	721	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	153:b484a57bc302	722	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	153:b484a57bc302	723
AnnaBridge	153:b484a57bc302	724	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	153:b484a57bc302	725	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	153:b484a57bc302	726
AnnaBridge	153:b484a57bc302	727	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	153:b484a57bc302	728	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	153:b484a57bc302	729
AnnaBridge	153:b484a57bc302	730	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	153:b484a57bc302	731	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	153:b484a57bc302	732
AnnaBridge	153:b484a57bc302	733	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	153:b484a57bc302	734	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
AnnaBridge	153:b484a57bc302	735	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
AnnaBridge	153:b484a57bc302	736
AnnaBridge	153:b484a57bc302	737	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
AnnaBridge	153:b484a57bc302	738	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
AnnaBridge	153:b484a57bc302	739
AnnaBridge	153:b484a57bc302	740	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
AnnaBridge	153:b484a57bc302	741	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
AnnaBridge	153:b484a57bc302	742
AnnaBridge	153:b484a57bc302	743	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	153:b484a57bc302	744	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
AnnaBridge	153:b484a57bc302	745	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
AnnaBridge	153:b484a57bc302	746
AnnaBridge	153:b484a57bc302	747	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
AnnaBridge	153:b484a57bc302	748	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
AnnaBridge	153:b484a57bc302	749
AnnaBridge	153:b484a57bc302	750	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
AnnaBridge	153:b484a57bc302	751	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
AnnaBridge	153:b484a57bc302	752
AnnaBridge	153:b484a57bc302	753	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
AnnaBridge	153:b484a57bc302	754	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
AnnaBridge	153:b484a57bc302	755
AnnaBridge	153:b484a57bc302	756	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
AnnaBridge	153:b484a57bc302	757	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
AnnaBridge	153:b484a57bc302	758
AnnaBridge	153:b484a57bc302	759	/* SCB Cache Level ID Register Definitions */
AnnaBridge	153:b484a57bc302	760	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
AnnaBridge	153:b484a57bc302	761	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
AnnaBridge	153:b484a57bc302	762
AnnaBridge	153:b484a57bc302	763	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
AnnaBridge	153:b484a57bc302	764	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
AnnaBridge	153:b484a57bc302	765
AnnaBridge	153:b484a57bc302	766	/* SCB Cache Type Register Definitions */
AnnaBridge	153:b484a57bc302	767	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
AnnaBridge	153:b484a57bc302	768	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
AnnaBridge	153:b484a57bc302	769
AnnaBridge	153:b484a57bc302	770	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
AnnaBridge	153:b484a57bc302	771	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
AnnaBridge	153:b484a57bc302	772
AnnaBridge	153:b484a57bc302	773	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
AnnaBridge	153:b484a57bc302	774	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
AnnaBridge	153:b484a57bc302	775
AnnaBridge	153:b484a57bc302	776	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
AnnaBridge	153:b484a57bc302	777	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
AnnaBridge	153:b484a57bc302	778
AnnaBridge	153:b484a57bc302	779	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
AnnaBridge	153:b484a57bc302	780	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
AnnaBridge	153:b484a57bc302	781
AnnaBridge	153:b484a57bc302	782	/* SCB Cache Size ID Register Definitions */
AnnaBridge	153:b484a57bc302	783	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
AnnaBridge	153:b484a57bc302	784	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
AnnaBridge	153:b484a57bc302	785
AnnaBridge	153:b484a57bc302	786	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
AnnaBridge	153:b484a57bc302	787	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
AnnaBridge	153:b484a57bc302	788
AnnaBridge	153:b484a57bc302	789	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
AnnaBridge	153:b484a57bc302	790	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
AnnaBridge	153:b484a57bc302	791
AnnaBridge	153:b484a57bc302	792	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
AnnaBridge	153:b484a57bc302	793	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
AnnaBridge	153:b484a57bc302	794
AnnaBridge	153:b484a57bc302	795	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
AnnaBridge	153:b484a57bc302	796	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
AnnaBridge	153:b484a57bc302	797
AnnaBridge	153:b484a57bc302	798	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
AnnaBridge	153:b484a57bc302	799	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
AnnaBridge	153:b484a57bc302	800
AnnaBridge	153:b484a57bc302	801	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
AnnaBridge	153:b484a57bc302	802	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
AnnaBridge	153:b484a57bc302	803
AnnaBridge	153:b484a57bc302	804	/* SCB Cache Size Selection Register Definitions */
AnnaBridge	153:b484a57bc302	805	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
AnnaBridge	153:b484a57bc302	806	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
AnnaBridge	153:b484a57bc302	807
AnnaBridge	153:b484a57bc302	808	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
AnnaBridge	153:b484a57bc302	809	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
AnnaBridge	153:b484a57bc302	810
AnnaBridge	153:b484a57bc302	811	/* SCB Software Triggered Interrupt Register Definitions */
AnnaBridge	153:b484a57bc302	812	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
AnnaBridge	153:b484a57bc302	813	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
AnnaBridge	153:b484a57bc302	814
AnnaBridge	153:b484a57bc302	815	/* SCB D-Cache Invalidate by Set-way Register Definitions */
AnnaBridge	153:b484a57bc302	816	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
AnnaBridge	153:b484a57bc302	817	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
AnnaBridge	153:b484a57bc302	818
AnnaBridge	153:b484a57bc302	819	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
AnnaBridge	153:b484a57bc302	820	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
AnnaBridge	153:b484a57bc302	821
AnnaBridge	153:b484a57bc302	822	/* SCB D-Cache Clean by Set-way Register Definitions */
AnnaBridge	153:b484a57bc302	823	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
AnnaBridge	153:b484a57bc302	824	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
AnnaBridge	153:b484a57bc302	825
AnnaBridge	153:b484a57bc302	826	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
AnnaBridge	153:b484a57bc302	827	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
AnnaBridge	153:b484a57bc302	828
AnnaBridge	153:b484a57bc302	829	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
AnnaBridge	153:b484a57bc302	830	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
AnnaBridge	153:b484a57bc302	831	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
AnnaBridge	153:b484a57bc302	832
AnnaBridge	153:b484a57bc302	833	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
AnnaBridge	153:b484a57bc302	834	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
AnnaBridge	153:b484a57bc302	835
AnnaBridge	153:b484a57bc302	836	/* Instruction Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	153:b484a57bc302	837	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
AnnaBridge	153:b484a57bc302	838	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
AnnaBridge	153:b484a57bc302	839
AnnaBridge	153:b484a57bc302	840	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
AnnaBridge	153:b484a57bc302	841	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
AnnaBridge	153:b484a57bc302	842
AnnaBridge	153:b484a57bc302	843	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
AnnaBridge	153:b484a57bc302	844	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
AnnaBridge	153:b484a57bc302	845
AnnaBridge	153:b484a57bc302	846	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
AnnaBridge	153:b484a57bc302	847	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
AnnaBridge	153:b484a57bc302	848
AnnaBridge	153:b484a57bc302	849	/* Data Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	153:b484a57bc302	850	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
AnnaBridge	153:b484a57bc302	851	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
AnnaBridge	153:b484a57bc302	852
AnnaBridge	153:b484a57bc302	853	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
AnnaBridge	153:b484a57bc302	854	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
AnnaBridge	153:b484a57bc302	855
AnnaBridge	153:b484a57bc302	856	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
AnnaBridge	153:b484a57bc302	857	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
AnnaBridge	153:b484a57bc302	858
AnnaBridge	153:b484a57bc302	859	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
AnnaBridge	153:b484a57bc302	860	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
AnnaBridge	153:b484a57bc302	861
AnnaBridge	153:b484a57bc302	862	/* AHBP Control Register Definitions */
AnnaBridge	153:b484a57bc302	863	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
AnnaBridge	153:b484a57bc302	864	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
AnnaBridge	153:b484a57bc302	865
AnnaBridge	153:b484a57bc302	866	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
AnnaBridge	153:b484a57bc302	867	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
AnnaBridge	153:b484a57bc302	868
AnnaBridge	153:b484a57bc302	869	/* L1 Cache Control Register Definitions */
AnnaBridge	153:b484a57bc302	870	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
AnnaBridge	153:b484a57bc302	871	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
AnnaBridge	153:b484a57bc302	872
AnnaBridge	153:b484a57bc302	873	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
AnnaBridge	153:b484a57bc302	874	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
AnnaBridge	153:b484a57bc302	875
AnnaBridge	153:b484a57bc302	876	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
AnnaBridge	153:b484a57bc302	877	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
AnnaBridge	153:b484a57bc302	878
AnnaBridge	153:b484a57bc302	879	/* AHBS Control Register Definitions */
AnnaBridge	153:b484a57bc302	880	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
AnnaBridge	153:b484a57bc302	881	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
AnnaBridge	153:b484a57bc302	882
AnnaBridge	153:b484a57bc302	883	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
AnnaBridge	153:b484a57bc302	884	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
AnnaBridge	153:b484a57bc302	885
AnnaBridge	153:b484a57bc302	886	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
AnnaBridge	153:b484a57bc302	887	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
AnnaBridge	153:b484a57bc302	888
AnnaBridge	153:b484a57bc302	889	/* Auxiliary Bus Fault Status Register Definitions */
AnnaBridge	153:b484a57bc302	890	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
AnnaBridge	153:b484a57bc302	891	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
AnnaBridge	153:b484a57bc302	892
AnnaBridge	153:b484a57bc302	893	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
AnnaBridge	153:b484a57bc302	894	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
AnnaBridge	153:b484a57bc302	895
AnnaBridge	153:b484a57bc302	896	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
AnnaBridge	153:b484a57bc302	897	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
AnnaBridge	153:b484a57bc302	898
AnnaBridge	153:b484a57bc302	899	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
AnnaBridge	153:b484a57bc302	900	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
AnnaBridge	153:b484a57bc302	901
AnnaBridge	153:b484a57bc302	902	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
AnnaBridge	153:b484a57bc302	903	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
AnnaBridge	153:b484a57bc302	904
AnnaBridge	153:b484a57bc302	905	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
AnnaBridge	153:b484a57bc302	906	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
AnnaBridge	153:b484a57bc302	907
AnnaBridge	153:b484a57bc302	908	/@} end of group CMSIS_SCB /
AnnaBridge	153:b484a57bc302	909
AnnaBridge	153:b484a57bc302	910
AnnaBridge	153:b484a57bc302	911	/**
AnnaBridge	153:b484a57bc302	912	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	913	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	153:b484a57bc302	914	\brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge	153:b484a57bc302	915	@{
AnnaBridge	153:b484a57bc302	916	*/
AnnaBridge	153:b484a57bc302	917
AnnaBridge	153:b484a57bc302	918	/**
AnnaBridge	153:b484a57bc302	919	\brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge	153:b484a57bc302	920	*/
AnnaBridge	153:b484a57bc302	921	typedef struct
AnnaBridge	153:b484a57bc302	922	{
AnnaBridge	153:b484a57bc302	923	uint32_t RESERVED0[1U];
AnnaBridge	153:b484a57bc302	924	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	153:b484a57bc302	925	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
AnnaBridge	153:b484a57bc302	926	} SCnSCB_Type;
AnnaBridge	153:b484a57bc302	927
AnnaBridge	153:b484a57bc302	928	/* Interrupt Controller Type Register Definitions */
AnnaBridge	153:b484a57bc302	929	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
AnnaBridge	153:b484a57bc302	930	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
AnnaBridge	153:b484a57bc302	931
AnnaBridge	153:b484a57bc302	932	/* Auxiliary Control Register Definitions */
AnnaBridge	153:b484a57bc302	933	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /!< ACTLR: DISITMATBFLUSH Position /
AnnaBridge	153:b484a57bc302	934	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
AnnaBridge	153:b484a57bc302	935
AnnaBridge	153:b484a57bc302	936	#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /!< ACTLR: DISRAMODE Position /
AnnaBridge	153:b484a57bc302	937	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
AnnaBridge	153:b484a57bc302	938
AnnaBridge	153:b484a57bc302	939	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /!< ACTLR: FPEXCODIS Position /
AnnaBridge	153:b484a57bc302	940	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
AnnaBridge	153:b484a57bc302	941
AnnaBridge	153:b484a57bc302	942	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
AnnaBridge	153:b484a57bc302	943	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
AnnaBridge	153:b484a57bc302	944
AnnaBridge	153:b484a57bc302	945	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
AnnaBridge	153:b484a57bc302	946	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
AnnaBridge	153:b484a57bc302	947
AnnaBridge	153:b484a57bc302	948	/@} end of group CMSIS_SCnotSCB /
AnnaBridge	153:b484a57bc302	949
AnnaBridge	153:b484a57bc302	950
AnnaBridge	153:b484a57bc302	951	/**
AnnaBridge	153:b484a57bc302	952	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	953	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	153:b484a57bc302	954	\brief Type definitions for the System Timer Registers.
AnnaBridge	153:b484a57bc302	955	@{
AnnaBridge	153:b484a57bc302	956	*/
AnnaBridge	153:b484a57bc302	957
AnnaBridge	153:b484a57bc302	958	/**
AnnaBridge	153:b484a57bc302	959	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	153:b484a57bc302	960	*/
AnnaBridge	153:b484a57bc302	961	typedef struct
AnnaBridge	153:b484a57bc302	962	{
AnnaBridge	153:b484a57bc302	963	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	153:b484a57bc302	964	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	153:b484a57bc302	965	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	153:b484a57bc302	966	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	153:b484a57bc302	967	} SysTick_Type;
AnnaBridge	153:b484a57bc302	968
AnnaBridge	153:b484a57bc302	969	/* SysTick Control / Status Register Definitions */
AnnaBridge	153:b484a57bc302	970	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	153:b484a57bc302	971	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	153:b484a57bc302	972
AnnaBridge	153:b484a57bc302	973	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	153:b484a57bc302	974	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	153:b484a57bc302	975
AnnaBridge	153:b484a57bc302	976	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	153:b484a57bc302	977	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	153:b484a57bc302	978
AnnaBridge	153:b484a57bc302	979	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	153:b484a57bc302	980	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	153:b484a57bc302	981
AnnaBridge	153:b484a57bc302	982	/* SysTick Reload Register Definitions */
AnnaBridge	153:b484a57bc302	983	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	153:b484a57bc302	984	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	153:b484a57bc302	985
AnnaBridge	153:b484a57bc302	986	/* SysTick Current Register Definitions */
AnnaBridge	153:b484a57bc302	987	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	153:b484a57bc302	988	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	153:b484a57bc302	989
AnnaBridge	153:b484a57bc302	990	/* SysTick Calibration Register Definitions */
AnnaBridge	153:b484a57bc302	991	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	153:b484a57bc302	992	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	153:b484a57bc302	993
AnnaBridge	153:b484a57bc302	994	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	153:b484a57bc302	995	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	153:b484a57bc302	996
AnnaBridge	153:b484a57bc302	997	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	153:b484a57bc302	998	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	153:b484a57bc302	999
AnnaBridge	153:b484a57bc302	1000	/@} end of group CMSIS_SysTick /
AnnaBridge	153:b484a57bc302	1001
AnnaBridge	153:b484a57bc302	1002
AnnaBridge	153:b484a57bc302	1003	/**
AnnaBridge	153:b484a57bc302	1004	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1005	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	153:b484a57bc302	1006	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge	153:b484a57bc302	1007	@{
AnnaBridge	153:b484a57bc302	1008	*/
AnnaBridge	153:b484a57bc302	1009
AnnaBridge	153:b484a57bc302	1010	/**
AnnaBridge	153:b484a57bc302	1011	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge	153:b484a57bc302	1012	*/
AnnaBridge	153:b484a57bc302	1013	typedef struct
AnnaBridge	153:b484a57bc302	1014	{
AnnaBridge	153:b484a57bc302	1015	__OM union
AnnaBridge	153:b484a57bc302	1016	{
AnnaBridge	153:b484a57bc302	1017	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	153:b484a57bc302	1018	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	153:b484a57bc302	1019	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	153:b484a57bc302	1020	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	153:b484a57bc302	1021	uint32_t RESERVED0[864U];
AnnaBridge	153:b484a57bc302	1022	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	153:b484a57bc302	1023	uint32_t RESERVED1[15U];
AnnaBridge	153:b484a57bc302	1024	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	153:b484a57bc302	1025	uint32_t RESERVED2[15U];
AnnaBridge	153:b484a57bc302	1026	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	153:b484a57bc302	1027	uint32_t RESERVED3[29U];
AnnaBridge	153:b484a57bc302	1028	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	153:b484a57bc302	1029	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	153:b484a57bc302	1030	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	153:b484a57bc302	1031	uint32_t RESERVED4[43U];
AnnaBridge	153:b484a57bc302	1032	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	153:b484a57bc302	1033	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	153:b484a57bc302	1034	uint32_t RESERVED5[6U];
AnnaBridge	153:b484a57bc302	1035	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	153:b484a57bc302	1036	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	153:b484a57bc302	1037	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	153:b484a57bc302	1038	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	153:b484a57bc302	1039	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	153:b484a57bc302	1040	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	153:b484a57bc302	1041	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	153:b484a57bc302	1042	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	153:b484a57bc302	1043	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	153:b484a57bc302	1044	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	153:b484a57bc302	1045	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	153:b484a57bc302	1046	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
AnnaBridge	153:b484a57bc302	1047	} ITM_Type;
AnnaBridge	153:b484a57bc302	1048
AnnaBridge	153:b484a57bc302	1049	/* ITM Trace Privilege Register Definitions */
AnnaBridge	153:b484a57bc302	1050	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
Anna Bridge	169:a7c7b631e539	1051	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
AnnaBridge	153:b484a57bc302	1052
AnnaBridge	153:b484a57bc302	1053	/* ITM Trace Control Register Definitions */
AnnaBridge	153:b484a57bc302	1054	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
AnnaBridge	153:b484a57bc302	1055	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
AnnaBridge	153:b484a57bc302	1056
AnnaBridge	153:b484a57bc302	1057	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
AnnaBridge	153:b484a57bc302	1058	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
AnnaBridge	153:b484a57bc302	1059
AnnaBridge	153:b484a57bc302	1060	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
AnnaBridge	153:b484a57bc302	1061	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
AnnaBridge	153:b484a57bc302	1062
AnnaBridge	153:b484a57bc302	1063	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
AnnaBridge	153:b484a57bc302	1064	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
AnnaBridge	153:b484a57bc302	1065
AnnaBridge	153:b484a57bc302	1066	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
AnnaBridge	153:b484a57bc302	1067	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
AnnaBridge	153:b484a57bc302	1068
AnnaBridge	153:b484a57bc302	1069	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
AnnaBridge	153:b484a57bc302	1070	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
AnnaBridge	153:b484a57bc302	1071
AnnaBridge	153:b484a57bc302	1072	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
AnnaBridge	153:b484a57bc302	1073	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
AnnaBridge	153:b484a57bc302	1074
AnnaBridge	153:b484a57bc302	1075	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
AnnaBridge	153:b484a57bc302	1076	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
AnnaBridge	153:b484a57bc302	1077
AnnaBridge	153:b484a57bc302	1078	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
AnnaBridge	153:b484a57bc302	1079	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
AnnaBridge	153:b484a57bc302	1080
AnnaBridge	153:b484a57bc302	1081	/* ITM Integration Write Register Definitions */
AnnaBridge	153:b484a57bc302	1082	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
AnnaBridge	153:b484a57bc302	1083	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
AnnaBridge	153:b484a57bc302	1084
AnnaBridge	153:b484a57bc302	1085	/* ITM Integration Read Register Definitions */
AnnaBridge	153:b484a57bc302	1086	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
AnnaBridge	153:b484a57bc302	1087	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
AnnaBridge	153:b484a57bc302	1088
AnnaBridge	153:b484a57bc302	1089	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	153:b484a57bc302	1090	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
AnnaBridge	153:b484a57bc302	1091	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
AnnaBridge	153:b484a57bc302	1092
AnnaBridge	153:b484a57bc302	1093	/* ITM Lock Status Register Definitions */
AnnaBridge	153:b484a57bc302	1094	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
AnnaBridge	153:b484a57bc302	1095	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
AnnaBridge	153:b484a57bc302	1096
AnnaBridge	153:b484a57bc302	1097	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
AnnaBridge	153:b484a57bc302	1098	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
AnnaBridge	153:b484a57bc302	1099
AnnaBridge	153:b484a57bc302	1100	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
AnnaBridge	153:b484a57bc302	1101	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
AnnaBridge	153:b484a57bc302	1102
AnnaBridge	153:b484a57bc302	1103	/@}/ /* end of group CMSIS_ITM */
AnnaBridge	153:b484a57bc302	1104
AnnaBridge	153:b484a57bc302	1105
AnnaBridge	153:b484a57bc302	1106	/**
AnnaBridge	153:b484a57bc302	1107	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1108	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	153:b484a57bc302	1109	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	153:b484a57bc302	1110	@{
AnnaBridge	153:b484a57bc302	1111	*/
AnnaBridge	153:b484a57bc302	1112
AnnaBridge	153:b484a57bc302	1113	/**
AnnaBridge	153:b484a57bc302	1114	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	153:b484a57bc302	1115	*/
AnnaBridge	153:b484a57bc302	1116	typedef struct
AnnaBridge	153:b484a57bc302	1117	{
AnnaBridge	153:b484a57bc302	1118	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	153:b484a57bc302	1119	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	153:b484a57bc302	1120	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	153:b484a57bc302	1121	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	153:b484a57bc302	1122	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	153:b484a57bc302	1123	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	153:b484a57bc302	1124	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	153:b484a57bc302	1125	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	153:b484a57bc302	1126	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	153:b484a57bc302	1127	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
AnnaBridge	153:b484a57bc302	1128	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	153:b484a57bc302	1129	uint32_t RESERVED0[1U];
AnnaBridge	153:b484a57bc302	1130	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	153:b484a57bc302	1131	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
AnnaBridge	153:b484a57bc302	1132	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	153:b484a57bc302	1133	uint32_t RESERVED1[1U];
AnnaBridge	153:b484a57bc302	1134	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	153:b484a57bc302	1135	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
AnnaBridge	153:b484a57bc302	1136	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	153:b484a57bc302	1137	uint32_t RESERVED2[1U];
AnnaBridge	153:b484a57bc302	1138	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	153:b484a57bc302	1139	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
AnnaBridge	153:b484a57bc302	1140	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	153:b484a57bc302	1141	uint32_t RESERVED3[981U];
AnnaBridge	153:b484a57bc302	1142	__OM uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
AnnaBridge	153:b484a57bc302	1143	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
AnnaBridge	153:b484a57bc302	1144	} DWT_Type;
AnnaBridge	153:b484a57bc302	1145
AnnaBridge	153:b484a57bc302	1146	/* DWT Control Register Definitions */
AnnaBridge	153:b484a57bc302	1147	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	153:b484a57bc302	1148	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	153:b484a57bc302	1149
AnnaBridge	153:b484a57bc302	1150	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	153:b484a57bc302	1151	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	153:b484a57bc302	1152
AnnaBridge	153:b484a57bc302	1153	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	153:b484a57bc302	1154	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	153:b484a57bc302	1155
AnnaBridge	153:b484a57bc302	1156	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	153:b484a57bc302	1157	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	153:b484a57bc302	1158
AnnaBridge	153:b484a57bc302	1159	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	153:b484a57bc302	1160	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	153:b484a57bc302	1161
AnnaBridge	153:b484a57bc302	1162	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
AnnaBridge	153:b484a57bc302	1163	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
AnnaBridge	153:b484a57bc302	1164
AnnaBridge	153:b484a57bc302	1165	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
AnnaBridge	153:b484a57bc302	1166	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
AnnaBridge	153:b484a57bc302	1167
AnnaBridge	153:b484a57bc302	1168	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
AnnaBridge	153:b484a57bc302	1169	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
AnnaBridge	153:b484a57bc302	1170
AnnaBridge	153:b484a57bc302	1171	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
AnnaBridge	153:b484a57bc302	1172	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
AnnaBridge	153:b484a57bc302	1173
AnnaBridge	153:b484a57bc302	1174	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
AnnaBridge	153:b484a57bc302	1175	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
AnnaBridge	153:b484a57bc302	1176
AnnaBridge	153:b484a57bc302	1177	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
AnnaBridge	153:b484a57bc302	1178	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
AnnaBridge	153:b484a57bc302	1179
AnnaBridge	153:b484a57bc302	1180	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
AnnaBridge	153:b484a57bc302	1181	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
AnnaBridge	153:b484a57bc302	1182
AnnaBridge	153:b484a57bc302	1183	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
AnnaBridge	153:b484a57bc302	1184	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
AnnaBridge	153:b484a57bc302	1185
AnnaBridge	153:b484a57bc302	1186	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
AnnaBridge	153:b484a57bc302	1187	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
AnnaBridge	153:b484a57bc302	1188
AnnaBridge	153:b484a57bc302	1189	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
AnnaBridge	153:b484a57bc302	1190	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
AnnaBridge	153:b484a57bc302	1191
AnnaBridge	153:b484a57bc302	1192	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
AnnaBridge	153:b484a57bc302	1193	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
AnnaBridge	153:b484a57bc302	1194
AnnaBridge	153:b484a57bc302	1195	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
AnnaBridge	153:b484a57bc302	1196	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
AnnaBridge	153:b484a57bc302	1197
AnnaBridge	153:b484a57bc302	1198	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
AnnaBridge	153:b484a57bc302	1199	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
AnnaBridge	153:b484a57bc302	1200
AnnaBridge	153:b484a57bc302	1201	/* DWT CPI Count Register Definitions */
AnnaBridge	153:b484a57bc302	1202	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
AnnaBridge	153:b484a57bc302	1203	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
AnnaBridge	153:b484a57bc302	1204
AnnaBridge	153:b484a57bc302	1205	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	153:b484a57bc302	1206	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
AnnaBridge	153:b484a57bc302	1207	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
AnnaBridge	153:b484a57bc302	1208
AnnaBridge	153:b484a57bc302	1209	/* DWT Sleep Count Register Definitions */
AnnaBridge	153:b484a57bc302	1210	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
AnnaBridge	153:b484a57bc302	1211	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
AnnaBridge	153:b484a57bc302	1212
AnnaBridge	153:b484a57bc302	1213	/* DWT LSU Count Register Definitions */
AnnaBridge	153:b484a57bc302	1214	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
AnnaBridge	153:b484a57bc302	1215	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
AnnaBridge	153:b484a57bc302	1216
AnnaBridge	153:b484a57bc302	1217	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	153:b484a57bc302	1218	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
AnnaBridge	153:b484a57bc302	1219	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
AnnaBridge	153:b484a57bc302	1220
AnnaBridge	153:b484a57bc302	1221	/* DWT Comparator Mask Register Definitions */
AnnaBridge	153:b484a57bc302	1222	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
AnnaBridge	153:b484a57bc302	1223	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
AnnaBridge	153:b484a57bc302	1224
AnnaBridge	153:b484a57bc302	1225	/* DWT Comparator Function Register Definitions */
AnnaBridge	153:b484a57bc302	1226	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	153:b484a57bc302	1227	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	153:b484a57bc302	1228
AnnaBridge	153:b484a57bc302	1229	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
AnnaBridge	153:b484a57bc302	1230	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
AnnaBridge	153:b484a57bc302	1231
AnnaBridge	153:b484a57bc302	1232	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
AnnaBridge	153:b484a57bc302	1233	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
AnnaBridge	153:b484a57bc302	1234
AnnaBridge	153:b484a57bc302	1235	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	153:b484a57bc302	1236	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	153:b484a57bc302	1237
AnnaBridge	153:b484a57bc302	1238	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
AnnaBridge	153:b484a57bc302	1239	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
AnnaBridge	153:b484a57bc302	1240
AnnaBridge	153:b484a57bc302	1241	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
AnnaBridge	153:b484a57bc302	1242	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
AnnaBridge	153:b484a57bc302	1243
AnnaBridge	153:b484a57bc302	1244	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
AnnaBridge	153:b484a57bc302	1245	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
AnnaBridge	153:b484a57bc302	1246
AnnaBridge	153:b484a57bc302	1247	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
AnnaBridge	153:b484a57bc302	1248	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
AnnaBridge	153:b484a57bc302	1249
AnnaBridge	153:b484a57bc302	1250	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
AnnaBridge	153:b484a57bc302	1251	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
AnnaBridge	153:b484a57bc302	1252
AnnaBridge	153:b484a57bc302	1253	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	153:b484a57bc302	1254
AnnaBridge	153:b484a57bc302	1255
AnnaBridge	153:b484a57bc302	1256	/**
AnnaBridge	153:b484a57bc302	1257	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1258	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	153:b484a57bc302	1259	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	153:b484a57bc302	1260	@{
AnnaBridge	153:b484a57bc302	1261	*/
AnnaBridge	153:b484a57bc302	1262
AnnaBridge	153:b484a57bc302	1263	/**
AnnaBridge	153:b484a57bc302	1264	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	153:b484a57bc302	1265	*/
AnnaBridge	153:b484a57bc302	1266	typedef struct
AnnaBridge	153:b484a57bc302	1267	{
AnnaBridge	153:b484a57bc302	1268	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	153:b484a57bc302	1269	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	153:b484a57bc302	1270	uint32_t RESERVED0[2U];
AnnaBridge	153:b484a57bc302	1271	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	153:b484a57bc302	1272	uint32_t RESERVED1[55U];
AnnaBridge	153:b484a57bc302	1273	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	153:b484a57bc302	1274	uint32_t RESERVED2[131U];
AnnaBridge	153:b484a57bc302	1275	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	153:b484a57bc302	1276	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	153:b484a57bc302	1277	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	153:b484a57bc302	1278	uint32_t RESERVED3[759U];
AnnaBridge	153:b484a57bc302	1279	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	153:b484a57bc302	1280	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	153:b484a57bc302	1281	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	153:b484a57bc302	1282	uint32_t RESERVED4[1U];
AnnaBridge	153:b484a57bc302	1283	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	153:b484a57bc302	1284	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	153:b484a57bc302	1285	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	153:b484a57bc302	1286	uint32_t RESERVED5[39U];
AnnaBridge	153:b484a57bc302	1287	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	153:b484a57bc302	1288	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	153:b484a57bc302	1289	uint32_t RESERVED7[8U];
AnnaBridge	153:b484a57bc302	1290	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	153:b484a57bc302	1291	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	153:b484a57bc302	1292	} TPI_Type;
AnnaBridge	153:b484a57bc302	1293
AnnaBridge	153:b484a57bc302	1294	/* TPI Asynchronous Clock Prescaler Register Definitions */
Anna Bridge	169:a7c7b631e539	1295	#define TPI_ACPR_PRESCALER_Pos 0U /!< @Deprecated TPI ACPR: PRESCALER Position /
Anna Bridge	169:a7c7b631e539	1296	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< @Deprecated TPI ACPR: PRESCALER Mask /
Anna Bridge	169:a7c7b631e539	1297
Anna Bridge	169:a7c7b631e539	1298	#define TPI_ACPR_SWOSCALER_Pos 0U /!< TPI ACPR: SWOSCALER Position /
Anna Bridge	169:a7c7b631e539	1299	#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/) /!< TPI ACPR: SWOSCALER Mask /
AnnaBridge	153:b484a57bc302	1300
AnnaBridge	153:b484a57bc302	1301	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	153:b484a57bc302	1302	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	153:b484a57bc302	1303	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	153:b484a57bc302	1304
AnnaBridge	153:b484a57bc302	1305	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	153:b484a57bc302	1306	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	153:b484a57bc302	1307	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	153:b484a57bc302	1308
AnnaBridge	153:b484a57bc302	1309	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	153:b484a57bc302	1310	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	153:b484a57bc302	1311
AnnaBridge	153:b484a57bc302	1312	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	153:b484a57bc302	1313	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	153:b484a57bc302	1314
AnnaBridge	153:b484a57bc302	1315	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	153:b484a57bc302	1316	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	153:b484a57bc302	1317
AnnaBridge	153:b484a57bc302	1318	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	153:b484a57bc302	1319	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	153:b484a57bc302	1320	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	153:b484a57bc302	1321
AnnaBridge	153:b484a57bc302	1322	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	153:b484a57bc302	1323	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	153:b484a57bc302	1324
AnnaBridge	153:b484a57bc302	1325	/* TPI TRIGGER Register Definitions */
AnnaBridge	153:b484a57bc302	1326	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	153:b484a57bc302	1327	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	153:b484a57bc302	1328
AnnaBridge	153:b484a57bc302	1329	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	153:b484a57bc302	1330	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	153:b484a57bc302	1331	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	153:b484a57bc302	1332
AnnaBridge	153:b484a57bc302	1333	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	153:b484a57bc302	1334	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	153:b484a57bc302	1335
AnnaBridge	153:b484a57bc302	1336	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	153:b484a57bc302	1337	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	153:b484a57bc302	1338
AnnaBridge	153:b484a57bc302	1339	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	153:b484a57bc302	1340	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	153:b484a57bc302	1341
AnnaBridge	153:b484a57bc302	1342	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
AnnaBridge	153:b484a57bc302	1343	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	153:b484a57bc302	1344
AnnaBridge	153:b484a57bc302	1345	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
AnnaBridge	153:b484a57bc302	1346	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	153:b484a57bc302	1347
AnnaBridge	153:b484a57bc302	1348	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
AnnaBridge	153:b484a57bc302	1349	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	153:b484a57bc302	1350
AnnaBridge	153:b484a57bc302	1351	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	153:b484a57bc302	1352	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
AnnaBridge	153:b484a57bc302	1353	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
AnnaBridge	153:b484a57bc302	1354
AnnaBridge	153:b484a57bc302	1355	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	153:b484a57bc302	1356	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	153:b484a57bc302	1357	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	153:b484a57bc302	1358
AnnaBridge	153:b484a57bc302	1359	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	153:b484a57bc302	1360	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	153:b484a57bc302	1361
AnnaBridge	153:b484a57bc302	1362	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	153:b484a57bc302	1363	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	153:b484a57bc302	1364
AnnaBridge	153:b484a57bc302	1365	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	153:b484a57bc302	1366	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	153:b484a57bc302	1367
AnnaBridge	153:b484a57bc302	1368	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
AnnaBridge	153:b484a57bc302	1369	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	153:b484a57bc302	1370
AnnaBridge	153:b484a57bc302	1371	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
AnnaBridge	153:b484a57bc302	1372	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	153:b484a57bc302	1373
AnnaBridge	153:b484a57bc302	1374	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
AnnaBridge	153:b484a57bc302	1375	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	153:b484a57bc302	1376
AnnaBridge	153:b484a57bc302	1377	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	153:b484a57bc302	1378	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
AnnaBridge	153:b484a57bc302	1379	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
AnnaBridge	153:b484a57bc302	1380
AnnaBridge	153:b484a57bc302	1381	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	153:b484a57bc302	1382	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	153:b484a57bc302	1383	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	153:b484a57bc302	1384
AnnaBridge	153:b484a57bc302	1385	/* TPI DEVID Register Definitions */
AnnaBridge	153:b484a57bc302	1386	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	153:b484a57bc302	1387	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	153:b484a57bc302	1388
AnnaBridge	153:b484a57bc302	1389	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	153:b484a57bc302	1390	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	153:b484a57bc302	1391
AnnaBridge	153:b484a57bc302	1392	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	153:b484a57bc302	1393	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	153:b484a57bc302	1394
AnnaBridge	153:b484a57bc302	1395	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
AnnaBridge	153:b484a57bc302	1396	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	153:b484a57bc302	1397
AnnaBridge	153:b484a57bc302	1398	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	153:b484a57bc302	1399	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	153:b484a57bc302	1400
AnnaBridge	153:b484a57bc302	1401	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	153:b484a57bc302	1402	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	153:b484a57bc302	1403
AnnaBridge	153:b484a57bc302	1404	/* TPI DEVTYPE Register Definitions */
AnnaBridge	153:b484a57bc302	1405	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	153:b484a57bc302	1406	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	153:b484a57bc302	1407
AnnaBridge	153:b484a57bc302	1408	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	153:b484a57bc302	1409	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	153:b484a57bc302	1410
AnnaBridge	153:b484a57bc302	1411	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	153:b484a57bc302	1412
AnnaBridge	153:b484a57bc302	1413
AnnaBridge	153:b484a57bc302	1414	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	1415	/**
AnnaBridge	153:b484a57bc302	1416	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1417	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	153:b484a57bc302	1418	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	153:b484a57bc302	1419	@{
AnnaBridge	153:b484a57bc302	1420	*/
AnnaBridge	153:b484a57bc302	1421
AnnaBridge	153:b484a57bc302	1422	/**
AnnaBridge	153:b484a57bc302	1423	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	153:b484a57bc302	1424	*/
AnnaBridge	153:b484a57bc302	1425	typedef struct
AnnaBridge	153:b484a57bc302	1426	{
AnnaBridge	153:b484a57bc302	1427	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	153:b484a57bc302	1428	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	153:b484a57bc302	1429	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
AnnaBridge	153:b484a57bc302	1430	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	153:b484a57bc302	1431	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
AnnaBridge	153:b484a57bc302	1432	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
AnnaBridge	153:b484a57bc302	1433	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
AnnaBridge	153:b484a57bc302	1434	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
AnnaBridge	153:b484a57bc302	1435	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
AnnaBridge	153:b484a57bc302	1436	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
AnnaBridge	153:b484a57bc302	1437	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
AnnaBridge	153:b484a57bc302	1438	} MPU_Type;
AnnaBridge	153:b484a57bc302	1439
Anna Bridge	160:5571c4ff569f	1440	#define MPU_TYPE_RALIASES 4U
Anna Bridge	160:5571c4ff569f	1441
AnnaBridge	153:b484a57bc302	1442	/* MPU Type Register Definitions */
AnnaBridge	153:b484a57bc302	1443	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	153:b484a57bc302	1444	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	153:b484a57bc302	1445
AnnaBridge	153:b484a57bc302	1446	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	153:b484a57bc302	1447	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	153:b484a57bc302	1448
AnnaBridge	153:b484a57bc302	1449	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	153:b484a57bc302	1450	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	153:b484a57bc302	1451
AnnaBridge	153:b484a57bc302	1452	/* MPU Control Register Definitions */
AnnaBridge	153:b484a57bc302	1453	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	153:b484a57bc302	1454	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	153:b484a57bc302	1455
AnnaBridge	153:b484a57bc302	1456	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	153:b484a57bc302	1457	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	153:b484a57bc302	1458
AnnaBridge	153:b484a57bc302	1459	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	153:b484a57bc302	1460	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	153:b484a57bc302	1461
AnnaBridge	153:b484a57bc302	1462	/* MPU Region Number Register Definitions */
AnnaBridge	153:b484a57bc302	1463	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	153:b484a57bc302	1464	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	153:b484a57bc302	1465
AnnaBridge	153:b484a57bc302	1466	/* MPU Region Base Address Register Definitions */
AnnaBridge	153:b484a57bc302	1467	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
AnnaBridge	153:b484a57bc302	1468	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
AnnaBridge	153:b484a57bc302	1469
AnnaBridge	153:b484a57bc302	1470	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
AnnaBridge	153:b484a57bc302	1471	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
AnnaBridge	153:b484a57bc302	1472
AnnaBridge	153:b484a57bc302	1473	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
AnnaBridge	153:b484a57bc302	1474	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
AnnaBridge	153:b484a57bc302	1475
AnnaBridge	153:b484a57bc302	1476	/* MPU Region Attribute and Size Register Definitions */
AnnaBridge	153:b484a57bc302	1477	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
AnnaBridge	153:b484a57bc302	1478	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
AnnaBridge	153:b484a57bc302	1479
AnnaBridge	153:b484a57bc302	1480	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
AnnaBridge	153:b484a57bc302	1481	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
AnnaBridge	153:b484a57bc302	1482
AnnaBridge	153:b484a57bc302	1483	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
AnnaBridge	153:b484a57bc302	1484	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
AnnaBridge	153:b484a57bc302	1485
AnnaBridge	153:b484a57bc302	1486	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
AnnaBridge	153:b484a57bc302	1487	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
AnnaBridge	153:b484a57bc302	1488
AnnaBridge	153:b484a57bc302	1489	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
AnnaBridge	153:b484a57bc302	1490	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
AnnaBridge	153:b484a57bc302	1491
AnnaBridge	153:b484a57bc302	1492	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
AnnaBridge	153:b484a57bc302	1493	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
AnnaBridge	153:b484a57bc302	1494
AnnaBridge	153:b484a57bc302	1495	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
AnnaBridge	153:b484a57bc302	1496	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
AnnaBridge	153:b484a57bc302	1497
AnnaBridge	153:b484a57bc302	1498	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
AnnaBridge	153:b484a57bc302	1499	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
AnnaBridge	153:b484a57bc302	1500
AnnaBridge	153:b484a57bc302	1501	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
AnnaBridge	153:b484a57bc302	1502	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
AnnaBridge	153:b484a57bc302	1503
AnnaBridge	153:b484a57bc302	1504	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
AnnaBridge	153:b484a57bc302	1505	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
AnnaBridge	153:b484a57bc302	1506
AnnaBridge	153:b484a57bc302	1507	/@} end of group CMSIS_MPU /
AnnaBridge	153:b484a57bc302	1508	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
AnnaBridge	153:b484a57bc302	1509
AnnaBridge	153:b484a57bc302	1510
AnnaBridge	153:b484a57bc302	1511	/**
AnnaBridge	153:b484a57bc302	1512	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1513	\defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge	153:b484a57bc302	1514	\brief Type definitions for the Floating Point Unit (FPU)
AnnaBridge	153:b484a57bc302	1515	@{
AnnaBridge	153:b484a57bc302	1516	*/
AnnaBridge	153:b484a57bc302	1517
AnnaBridge	153:b484a57bc302	1518	/**
AnnaBridge	153:b484a57bc302	1519	\brief Structure type to access the Floating Point Unit (FPU).
AnnaBridge	153:b484a57bc302	1520	*/
AnnaBridge	153:b484a57bc302	1521	typedef struct
AnnaBridge	153:b484a57bc302	1522	{
AnnaBridge	153:b484a57bc302	1523	uint32_t RESERVED0[1U];
AnnaBridge	153:b484a57bc302	1524	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
AnnaBridge	153:b484a57bc302	1525	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
AnnaBridge	153:b484a57bc302	1526	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
AnnaBridge	153:b484a57bc302	1527	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
AnnaBridge	153:b484a57bc302	1528	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
AnnaBridge	153:b484a57bc302	1529	__IM uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
AnnaBridge	153:b484a57bc302	1530	} FPU_Type;
AnnaBridge	153:b484a57bc302	1531
AnnaBridge	153:b484a57bc302	1532	/* Floating-Point Context Control Register Definitions */
AnnaBridge	153:b484a57bc302	1533	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
AnnaBridge	153:b484a57bc302	1534	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
AnnaBridge	153:b484a57bc302	1535
AnnaBridge	153:b484a57bc302	1536	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
AnnaBridge	153:b484a57bc302	1537	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
AnnaBridge	153:b484a57bc302	1538
AnnaBridge	153:b484a57bc302	1539	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
AnnaBridge	153:b484a57bc302	1540	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
AnnaBridge	153:b484a57bc302	1541
AnnaBridge	153:b484a57bc302	1542	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
AnnaBridge	153:b484a57bc302	1543	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
AnnaBridge	153:b484a57bc302	1544
AnnaBridge	153:b484a57bc302	1545	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
AnnaBridge	153:b484a57bc302	1546	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
AnnaBridge	153:b484a57bc302	1547
AnnaBridge	153:b484a57bc302	1548	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
AnnaBridge	153:b484a57bc302	1549	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
AnnaBridge	153:b484a57bc302	1550
AnnaBridge	153:b484a57bc302	1551	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
AnnaBridge	153:b484a57bc302	1552	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
AnnaBridge	153:b484a57bc302	1553
AnnaBridge	153:b484a57bc302	1554	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
AnnaBridge	153:b484a57bc302	1555	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
AnnaBridge	153:b484a57bc302	1556
AnnaBridge	153:b484a57bc302	1557	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
AnnaBridge	153:b484a57bc302	1558	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
AnnaBridge	153:b484a57bc302	1559
AnnaBridge	153:b484a57bc302	1560	/* Floating-Point Context Address Register Definitions */
AnnaBridge	153:b484a57bc302	1561	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
AnnaBridge	153:b484a57bc302	1562	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
AnnaBridge	153:b484a57bc302	1563
AnnaBridge	153:b484a57bc302	1564	/* Floating-Point Default Status Control Register Definitions */
AnnaBridge	153:b484a57bc302	1565	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
AnnaBridge	153:b484a57bc302	1566	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
AnnaBridge	153:b484a57bc302	1567
AnnaBridge	153:b484a57bc302	1568	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
AnnaBridge	153:b484a57bc302	1569	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
AnnaBridge	153:b484a57bc302	1570
AnnaBridge	153:b484a57bc302	1571	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
AnnaBridge	153:b484a57bc302	1572	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
AnnaBridge	153:b484a57bc302	1573
AnnaBridge	153:b484a57bc302	1574	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
AnnaBridge	153:b484a57bc302	1575	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
AnnaBridge	153:b484a57bc302	1576
AnnaBridge	153:b484a57bc302	1577	/* Media and FP Feature Register 0 Definitions */
AnnaBridge	153:b484a57bc302	1578	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
AnnaBridge	153:b484a57bc302	1579	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
AnnaBridge	153:b484a57bc302	1580
AnnaBridge	153:b484a57bc302	1581	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
AnnaBridge	153:b484a57bc302	1582	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
AnnaBridge	153:b484a57bc302	1583
AnnaBridge	153:b484a57bc302	1584	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
AnnaBridge	153:b484a57bc302	1585	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
AnnaBridge	153:b484a57bc302	1586
AnnaBridge	153:b484a57bc302	1587	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
AnnaBridge	153:b484a57bc302	1588	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
AnnaBridge	153:b484a57bc302	1589
AnnaBridge	153:b484a57bc302	1590	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
AnnaBridge	153:b484a57bc302	1591	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
AnnaBridge	153:b484a57bc302	1592
AnnaBridge	153:b484a57bc302	1593	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
AnnaBridge	153:b484a57bc302	1594	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
AnnaBridge	153:b484a57bc302	1595
AnnaBridge	153:b484a57bc302	1596	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
AnnaBridge	153:b484a57bc302	1597	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
AnnaBridge	153:b484a57bc302	1598
AnnaBridge	153:b484a57bc302	1599	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
AnnaBridge	153:b484a57bc302	1600	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
AnnaBridge	153:b484a57bc302	1601
AnnaBridge	153:b484a57bc302	1602	/* Media and FP Feature Register 1 Definitions */
AnnaBridge	153:b484a57bc302	1603	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
AnnaBridge	153:b484a57bc302	1604	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
AnnaBridge	153:b484a57bc302	1605
AnnaBridge	153:b484a57bc302	1606	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
AnnaBridge	153:b484a57bc302	1607	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
AnnaBridge	153:b484a57bc302	1608
AnnaBridge	153:b484a57bc302	1609	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
AnnaBridge	153:b484a57bc302	1610	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
AnnaBridge	153:b484a57bc302	1611
AnnaBridge	153:b484a57bc302	1612	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
AnnaBridge	153:b484a57bc302	1613	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
AnnaBridge	153:b484a57bc302	1614
AnnaBridge	153:b484a57bc302	1615	/* Media and FP Feature Register 2 Definitions */
AnnaBridge	153:b484a57bc302	1616
AnnaBridge	153:b484a57bc302	1617	/@} end of group CMSIS_FPU /
AnnaBridge	153:b484a57bc302	1618
AnnaBridge	153:b484a57bc302	1619
AnnaBridge	153:b484a57bc302	1620	/**
AnnaBridge	153:b484a57bc302	1621	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1622	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	153:b484a57bc302	1623	\brief Type definitions for the Core Debug Registers
AnnaBridge	153:b484a57bc302	1624	@{
AnnaBridge	153:b484a57bc302	1625	*/
AnnaBridge	153:b484a57bc302	1626
AnnaBridge	153:b484a57bc302	1627	/**
AnnaBridge	153:b484a57bc302	1628	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	153:b484a57bc302	1629	*/
AnnaBridge	153:b484a57bc302	1630	typedef struct
AnnaBridge	153:b484a57bc302	1631	{
AnnaBridge	153:b484a57bc302	1632	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	153:b484a57bc302	1633	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	153:b484a57bc302	1634	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	153:b484a57bc302	1635	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	153:b484a57bc302	1636	} CoreDebug_Type;
AnnaBridge	153:b484a57bc302	1637
AnnaBridge	153:b484a57bc302	1638	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	153:b484a57bc302	1639	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	153:b484a57bc302	1640	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	153:b484a57bc302	1641
AnnaBridge	153:b484a57bc302	1642	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	153:b484a57bc302	1643	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	153:b484a57bc302	1644
AnnaBridge	153:b484a57bc302	1645	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	153:b484a57bc302	1646	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	153:b484a57bc302	1647
AnnaBridge	153:b484a57bc302	1648	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	153:b484a57bc302	1649	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	153:b484a57bc302	1650
AnnaBridge	153:b484a57bc302	1651	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	153:b484a57bc302	1652	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	153:b484a57bc302	1653
AnnaBridge	153:b484a57bc302	1654	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	153:b484a57bc302	1655	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	153:b484a57bc302	1656
AnnaBridge	153:b484a57bc302	1657	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	153:b484a57bc302	1658	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	153:b484a57bc302	1659
AnnaBridge	153:b484a57bc302	1660	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
AnnaBridge	153:b484a57bc302	1661	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
AnnaBridge	153:b484a57bc302	1662
AnnaBridge	153:b484a57bc302	1663	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	153:b484a57bc302	1664	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	153:b484a57bc302	1665
AnnaBridge	153:b484a57bc302	1666	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	153:b484a57bc302	1667	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	153:b484a57bc302	1668
AnnaBridge	153:b484a57bc302	1669	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	153:b484a57bc302	1670	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	153:b484a57bc302	1671
AnnaBridge	153:b484a57bc302	1672	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	153:b484a57bc302	1673	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	153:b484a57bc302	1674
AnnaBridge	153:b484a57bc302	1675	/* Debug Core Register Selector Register Definitions */
AnnaBridge	153:b484a57bc302	1676	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	153:b484a57bc302	1677	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	153:b484a57bc302	1678
AnnaBridge	153:b484a57bc302	1679	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	153:b484a57bc302	1680	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	153:b484a57bc302	1681
AnnaBridge	153:b484a57bc302	1682	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	153:b484a57bc302	1683	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
AnnaBridge	153:b484a57bc302	1684	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
AnnaBridge	153:b484a57bc302	1685
AnnaBridge	153:b484a57bc302	1686	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
AnnaBridge	153:b484a57bc302	1687	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
AnnaBridge	153:b484a57bc302	1688
AnnaBridge	153:b484a57bc302	1689	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
AnnaBridge	153:b484a57bc302	1690	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
AnnaBridge	153:b484a57bc302	1691
AnnaBridge	153:b484a57bc302	1692	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
AnnaBridge	153:b484a57bc302	1693	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
AnnaBridge	153:b484a57bc302	1694
AnnaBridge	153:b484a57bc302	1695	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
AnnaBridge	153:b484a57bc302	1696	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
AnnaBridge	153:b484a57bc302	1697
AnnaBridge	153:b484a57bc302	1698	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	153:b484a57bc302	1699	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	153:b484a57bc302	1700
AnnaBridge	153:b484a57bc302	1701	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
AnnaBridge	153:b484a57bc302	1702	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
AnnaBridge	153:b484a57bc302	1703
AnnaBridge	153:b484a57bc302	1704	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
AnnaBridge	153:b484a57bc302	1705	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
AnnaBridge	153:b484a57bc302	1706
AnnaBridge	153:b484a57bc302	1707	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
AnnaBridge	153:b484a57bc302	1708	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
AnnaBridge	153:b484a57bc302	1709
AnnaBridge	153:b484a57bc302	1710	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
AnnaBridge	153:b484a57bc302	1711	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
AnnaBridge	153:b484a57bc302	1712
AnnaBridge	153:b484a57bc302	1713	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
AnnaBridge	153:b484a57bc302	1714	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
AnnaBridge	153:b484a57bc302	1715
AnnaBridge	153:b484a57bc302	1716	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
AnnaBridge	153:b484a57bc302	1717	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
AnnaBridge	153:b484a57bc302	1718
AnnaBridge	153:b484a57bc302	1719	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	153:b484a57bc302	1720	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	153:b484a57bc302	1721
AnnaBridge	153:b484a57bc302	1722	/@} end of group CMSIS_CoreDebug /
AnnaBridge	153:b484a57bc302	1723
AnnaBridge	153:b484a57bc302	1724
AnnaBridge	153:b484a57bc302	1725	/**
AnnaBridge	153:b484a57bc302	1726	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1727	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	153:b484a57bc302	1728	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	153:b484a57bc302	1729	@{
AnnaBridge	153:b484a57bc302	1730	*/
AnnaBridge	153:b484a57bc302	1731
AnnaBridge	153:b484a57bc302	1732	/**
AnnaBridge	153:b484a57bc302	1733	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	153:b484a57bc302	1734	\param[in] field Name of the register bit field.
AnnaBridge	153:b484a57bc302	1735	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	153:b484a57bc302	1736	\return Masked and shifted value.
AnnaBridge	153:b484a57bc302	1737	*/
AnnaBridge	153:b484a57bc302	1738	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	153:b484a57bc302	1739
AnnaBridge	153:b484a57bc302	1740	/**
AnnaBridge	153:b484a57bc302	1741	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	153:b484a57bc302	1742	\param[in] field Name of the register bit field.
AnnaBridge	153:b484a57bc302	1743	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	153:b484a57bc302	1744	\return Masked and shifted bit field value.
AnnaBridge	153:b484a57bc302	1745	*/
AnnaBridge	153:b484a57bc302	1746	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	153:b484a57bc302	1747
AnnaBridge	153:b484a57bc302	1748	/@} end of group CMSIS_core_bitfield /
AnnaBridge	153:b484a57bc302	1749
AnnaBridge	153:b484a57bc302	1750
AnnaBridge	153:b484a57bc302	1751	/**
AnnaBridge	153:b484a57bc302	1752	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1753	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	153:b484a57bc302	1754	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	153:b484a57bc302	1755	@{
AnnaBridge	153:b484a57bc302	1756	*/
AnnaBridge	153:b484a57bc302	1757
AnnaBridge	153:b484a57bc302	1758	/* Memory mapping of Core Hardware */
AnnaBridge	153:b484a57bc302	1759	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	153:b484a57bc302	1760	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	153:b484a57bc302	1761	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	153:b484a57bc302	1762	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	153:b484a57bc302	1763	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	153:b484a57bc302	1764	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	153:b484a57bc302	1765	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	153:b484a57bc302	1766	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	153:b484a57bc302	1767
AnnaBridge	153:b484a57bc302	1768	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	153:b484a57bc302	1769	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	153:b484a57bc302	1770	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	153:b484a57bc302	1771	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	153:b484a57bc302	1772	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	153:b484a57bc302	1773	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	153:b484a57bc302	1774	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	153:b484a57bc302	1775	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
AnnaBridge	153:b484a57bc302	1776
AnnaBridge	153:b484a57bc302	1777	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	1778	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	153:b484a57bc302	1779	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	153:b484a57bc302	1780	#endif
AnnaBridge	153:b484a57bc302	1781
AnnaBridge	153:b484a57bc302	1782	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
AnnaBridge	153:b484a57bc302	1783	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
AnnaBridge	153:b484a57bc302	1784
AnnaBridge	153:b484a57bc302	1785	/@} /
AnnaBridge	153:b484a57bc302	1786
AnnaBridge	153:b484a57bc302	1787
AnnaBridge	153:b484a57bc302	1788
AnnaBridge	153:b484a57bc302	1789	/*******************************************************************************
AnnaBridge	153:b484a57bc302	1790	* Hardware Abstraction Layer
AnnaBridge	153:b484a57bc302	1791	Core Function Interface contains:
AnnaBridge	153:b484a57bc302	1792	- Core NVIC Functions
AnnaBridge	153:b484a57bc302	1793	- Core SysTick Functions
AnnaBridge	153:b484a57bc302	1794	- Core Debug Functions
AnnaBridge	153:b484a57bc302	1795	- Core Register Access Functions
AnnaBridge	153:b484a57bc302	1796	******************************************************************************/
AnnaBridge	153:b484a57bc302	1797	/**
AnnaBridge	153:b484a57bc302	1798	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	153:b484a57bc302	1799	*/
AnnaBridge	153:b484a57bc302	1800
AnnaBridge	153:b484a57bc302	1801
AnnaBridge	153:b484a57bc302	1802
AnnaBridge	153:b484a57bc302	1803	/* ########################## NVIC functions #################################### */
AnnaBridge	153:b484a57bc302	1804	/**
AnnaBridge	153:b484a57bc302	1805	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	153:b484a57bc302	1806	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	153:b484a57bc302	1807	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	153:b484a57bc302	1808	@{
AnnaBridge	153:b484a57bc302	1809	*/
AnnaBridge	153:b484a57bc302	1810
AnnaBridge	153:b484a57bc302	1811	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	153:b484a57bc302	1812	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	153:b484a57bc302	1813	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	153:b484a57bc302	1814	#endif
AnnaBridge	153:b484a57bc302	1815	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	153:b484a57bc302	1816	#else
AnnaBridge	153:b484a57bc302	1817	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge	153:b484a57bc302	1818	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge	153:b484a57bc302	1819	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	153:b484a57bc302	1820	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	153:b484a57bc302	1821	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	153:b484a57bc302	1822	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	153:b484a57bc302	1823	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	153:b484a57bc302	1824	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	153:b484a57bc302	1825	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	153:b484a57bc302	1826	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	153:b484a57bc302	1827	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	153:b484a57bc302	1828	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	153:b484a57bc302	1829	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	153:b484a57bc302	1830
AnnaBridge	153:b484a57bc302	1831	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	153:b484a57bc302	1832	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	153:b484a57bc302	1833	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	153:b484a57bc302	1834	#endif
AnnaBridge	153:b484a57bc302	1835	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	153:b484a57bc302	1836	#else
AnnaBridge	153:b484a57bc302	1837	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	153:b484a57bc302	1838	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	153:b484a57bc302	1839	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	153:b484a57bc302	1840
AnnaBridge	153:b484a57bc302	1841	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	153:b484a57bc302	1842
AnnaBridge	153:b484a57bc302	1843
AnnaBridge	153:b484a57bc302	1844
AnnaBridge	153:b484a57bc302	1845	/**
AnnaBridge	153:b484a57bc302	1846	\brief Set Priority Grouping
AnnaBridge	153:b484a57bc302	1847	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	153:b484a57bc302	1848	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	153:b484a57bc302	1849	Only values from 0..7 are used.
AnnaBridge	153:b484a57bc302	1850	In case of a conflict between priority grouping and available
AnnaBridge	153:b484a57bc302	1851	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	153:b484a57bc302	1852	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	153:b484a57bc302	1853	*/
AnnaBridge	153:b484a57bc302	1854	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge	153:b484a57bc302	1855	{
AnnaBridge	153:b484a57bc302	1856	uint32_t reg_value;
AnnaBridge	153:b484a57bc302	1857	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	153:b484a57bc302	1858
AnnaBridge	153:b484a57bc302	1859	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	153:b484a57bc302	1860	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	153:b484a57bc302	1861	reg_value = (reg_value \|
AnnaBridge	153:b484a57bc302	1862	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	169:a7c7b631e539	1863	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
AnnaBridge	153:b484a57bc302	1864	SCB->AIRCR = reg_value;
AnnaBridge	153:b484a57bc302	1865	}
AnnaBridge	153:b484a57bc302	1866
AnnaBridge	153:b484a57bc302	1867
AnnaBridge	153:b484a57bc302	1868	/**
AnnaBridge	153:b484a57bc302	1869	\brief Get Priority Grouping
AnnaBridge	153:b484a57bc302	1870	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	153:b484a57bc302	1871	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	153:b484a57bc302	1872	*/
AnnaBridge	153:b484a57bc302	1873	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge	153:b484a57bc302	1874	{
AnnaBridge	153:b484a57bc302	1875	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	153:b484a57bc302	1876	}
AnnaBridge	153:b484a57bc302	1877
AnnaBridge	153:b484a57bc302	1878
AnnaBridge	153:b484a57bc302	1879	/**
AnnaBridge	153:b484a57bc302	1880	\brief Enable Interrupt
AnnaBridge	153:b484a57bc302	1881	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	153:b484a57bc302	1882	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	1883	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	1884	*/
AnnaBridge	153:b484a57bc302	1885	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	1886	{
AnnaBridge	153:b484a57bc302	1887	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	1888	{
Anna Bridge	169:a7c7b631e539	1889	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	153:b484a57bc302	1890	}
AnnaBridge	153:b484a57bc302	1891	}
AnnaBridge	153:b484a57bc302	1892
AnnaBridge	153:b484a57bc302	1893
AnnaBridge	153:b484a57bc302	1894	/**
AnnaBridge	153:b484a57bc302	1895	\brief Get Interrupt Enable status
AnnaBridge	153:b484a57bc302	1896	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	153:b484a57bc302	1897	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	1898	\return 0 Interrupt is not enabled.
AnnaBridge	153:b484a57bc302	1899	\return 1 Interrupt is enabled.
AnnaBridge	153:b484a57bc302	1900	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	1901	*/
AnnaBridge	153:b484a57bc302	1902	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	1903	{
AnnaBridge	153:b484a57bc302	1904	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	1905	{
Anna Bridge	169:a7c7b631e539	1906	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	153:b484a57bc302	1907	}
AnnaBridge	153:b484a57bc302	1908	else
AnnaBridge	153:b484a57bc302	1909	{
AnnaBridge	153:b484a57bc302	1910	return(0U);
AnnaBridge	153:b484a57bc302	1911	}
AnnaBridge	153:b484a57bc302	1912	}
AnnaBridge	153:b484a57bc302	1913
AnnaBridge	153:b484a57bc302	1914
AnnaBridge	153:b484a57bc302	1915	/**
AnnaBridge	153:b484a57bc302	1916	\brief Disable Interrupt
AnnaBridge	153:b484a57bc302	1917	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	153:b484a57bc302	1918	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	1919	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	1920	*/
AnnaBridge	153:b484a57bc302	1921	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	1922	{
AnnaBridge	153:b484a57bc302	1923	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	1924	{
Anna Bridge	169:a7c7b631e539	1925	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	153:b484a57bc302	1926	__DSB();
AnnaBridge	153:b484a57bc302	1927	__ISB();
AnnaBridge	153:b484a57bc302	1928	}
AnnaBridge	153:b484a57bc302	1929	}
AnnaBridge	153:b484a57bc302	1930
AnnaBridge	153:b484a57bc302	1931
AnnaBridge	153:b484a57bc302	1932	/**
AnnaBridge	153:b484a57bc302	1933	\brief Get Pending Interrupt
AnnaBridge	153:b484a57bc302	1934	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	153:b484a57bc302	1935	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	1936	\return 0 Interrupt status is not pending.
AnnaBridge	153:b484a57bc302	1937	\return 1 Interrupt status is pending.
AnnaBridge	153:b484a57bc302	1938	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	1939	*/
AnnaBridge	153:b484a57bc302	1940	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	1941	{
AnnaBridge	153:b484a57bc302	1942	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	1943	{
Anna Bridge	169:a7c7b631e539	1944	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	153:b484a57bc302	1945	}
AnnaBridge	153:b484a57bc302	1946	else
AnnaBridge	153:b484a57bc302	1947	{
AnnaBridge	153:b484a57bc302	1948	return(0U);
AnnaBridge	153:b484a57bc302	1949	}
AnnaBridge	153:b484a57bc302	1950	}
AnnaBridge	153:b484a57bc302	1951
AnnaBridge	153:b484a57bc302	1952
AnnaBridge	153:b484a57bc302	1953	/**
AnnaBridge	153:b484a57bc302	1954	\brief Set Pending Interrupt
AnnaBridge	153:b484a57bc302	1955	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	153:b484a57bc302	1956	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	1957	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	1958	*/
AnnaBridge	153:b484a57bc302	1959	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	1960	{
AnnaBridge	153:b484a57bc302	1961	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	1962	{
Anna Bridge	169:a7c7b631e539	1963	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	153:b484a57bc302	1964	}
AnnaBridge	153:b484a57bc302	1965	}
AnnaBridge	153:b484a57bc302	1966
AnnaBridge	153:b484a57bc302	1967
AnnaBridge	153:b484a57bc302	1968	/**
AnnaBridge	153:b484a57bc302	1969	\brief Clear Pending Interrupt
AnnaBridge	153:b484a57bc302	1970	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	153:b484a57bc302	1971	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	1972	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	1973	*/
AnnaBridge	153:b484a57bc302	1974	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	1975	{
AnnaBridge	153:b484a57bc302	1976	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	1977	{
Anna Bridge	169:a7c7b631e539	1978	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	153:b484a57bc302	1979	}
AnnaBridge	153:b484a57bc302	1980	}
AnnaBridge	153:b484a57bc302	1981
AnnaBridge	153:b484a57bc302	1982
AnnaBridge	153:b484a57bc302	1983	/**
AnnaBridge	153:b484a57bc302	1984	\brief Get Active Interrupt
AnnaBridge	153:b484a57bc302	1985	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	153:b484a57bc302	1986	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	1987	\return 0 Interrupt status is not active.
AnnaBridge	153:b484a57bc302	1988	\return 1 Interrupt status is active.
AnnaBridge	153:b484a57bc302	1989	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	1990	*/
AnnaBridge	153:b484a57bc302	1991	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	1992	{
AnnaBridge	153:b484a57bc302	1993	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	1994	{
Anna Bridge	169:a7c7b631e539	1995	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	153:b484a57bc302	1996	}
AnnaBridge	153:b484a57bc302	1997	else
AnnaBridge	153:b484a57bc302	1998	{
AnnaBridge	153:b484a57bc302	1999	return(0U);
AnnaBridge	153:b484a57bc302	2000	}
AnnaBridge	153:b484a57bc302	2001	}
AnnaBridge	153:b484a57bc302	2002
AnnaBridge	153:b484a57bc302	2003
AnnaBridge	153:b484a57bc302	2004	/**
AnnaBridge	153:b484a57bc302	2005	\brief Set Interrupt Priority
AnnaBridge	153:b484a57bc302	2006	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	153:b484a57bc302	2007	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	153:b484a57bc302	2008	or negative to specify a processor exception.
AnnaBridge	153:b484a57bc302	2009	\param [in] IRQn Interrupt number.
AnnaBridge	153:b484a57bc302	2010	\param [in] priority Priority to set.
AnnaBridge	153:b484a57bc302	2011	\note The priority cannot be set for every processor exception.
AnnaBridge	153:b484a57bc302	2012	*/
AnnaBridge	153:b484a57bc302	2013	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	153:b484a57bc302	2014	{
AnnaBridge	153:b484a57bc302	2015	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2016	{
Anna Bridge	169:a7c7b631e539	2017	NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	153:b484a57bc302	2018	}
AnnaBridge	153:b484a57bc302	2019	else
AnnaBridge	153:b484a57bc302	2020	{
Anna Bridge	169:a7c7b631e539	2021	SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	153:b484a57bc302	2022	}
AnnaBridge	153:b484a57bc302	2023	}
AnnaBridge	153:b484a57bc302	2024
AnnaBridge	153:b484a57bc302	2025
AnnaBridge	153:b484a57bc302	2026	/**
AnnaBridge	153:b484a57bc302	2027	\brief Get Interrupt Priority
AnnaBridge	153:b484a57bc302	2028	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	153:b484a57bc302	2029	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	153:b484a57bc302	2030	or negative to specify a processor exception.
AnnaBridge	153:b484a57bc302	2031	\param [in] IRQn Interrupt number.
AnnaBridge	153:b484a57bc302	2032	\return Interrupt Priority.
AnnaBridge	153:b484a57bc302	2033	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	153:b484a57bc302	2034	*/
AnnaBridge	153:b484a57bc302	2035	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2036	{
AnnaBridge	153:b484a57bc302	2037
AnnaBridge	153:b484a57bc302	2038	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2039	{
Anna Bridge	169:a7c7b631e539	2040	return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	153:b484a57bc302	2041	}
AnnaBridge	153:b484a57bc302	2042	else
AnnaBridge	153:b484a57bc302	2043	{
Anna Bridge	169:a7c7b631e539	2044	return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	153:b484a57bc302	2045	}
AnnaBridge	153:b484a57bc302	2046	}
AnnaBridge	153:b484a57bc302	2047
AnnaBridge	153:b484a57bc302	2048
AnnaBridge	153:b484a57bc302	2049	/**
AnnaBridge	153:b484a57bc302	2050	\brief Encode Priority
AnnaBridge	153:b484a57bc302	2051	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	153:b484a57bc302	2052	preemptive priority value, and subpriority value.
AnnaBridge	153:b484a57bc302	2053	In case of a conflict between priority grouping and available
AnnaBridge	153:b484a57bc302	2054	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	153:b484a57bc302	2055	\param [in] PriorityGroup Used priority group.
AnnaBridge	153:b484a57bc302	2056	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	153:b484a57bc302	2057	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	153:b484a57bc302	2058	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	153:b484a57bc302	2059	*/
AnnaBridge	153:b484a57bc302	2060	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	153:b484a57bc302	2061	{
AnnaBridge	153:b484a57bc302	2062	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	153:b484a57bc302	2063	uint32_t PreemptPriorityBits;
AnnaBridge	153:b484a57bc302	2064	uint32_t SubPriorityBits;
AnnaBridge	153:b484a57bc302	2065
AnnaBridge	153:b484a57bc302	2066	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	153:b484a57bc302	2067	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	153:b484a57bc302	2068
AnnaBridge	153:b484a57bc302	2069	return (
AnnaBridge	153:b484a57bc302	2070	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	153:b484a57bc302	2071	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	153:b484a57bc302	2072	);
AnnaBridge	153:b484a57bc302	2073	}
AnnaBridge	153:b484a57bc302	2074
AnnaBridge	153:b484a57bc302	2075
AnnaBridge	153:b484a57bc302	2076	/**
AnnaBridge	153:b484a57bc302	2077	\brief Decode Priority
AnnaBridge	153:b484a57bc302	2078	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	153:b484a57bc302	2079	preemptive priority value and subpriority value.
AnnaBridge	153:b484a57bc302	2080	In case of a conflict between priority grouping and available
AnnaBridge	153:b484a57bc302	2081	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	153:b484a57bc302	2082	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	153:b484a57bc302	2083	\param [in] PriorityGroup Used priority group.
AnnaBridge	153:b484a57bc302	2084	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	153:b484a57bc302	2085	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	153:b484a57bc302	2086	*/
AnnaBridge	153:b484a57bc302	2087	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge	153:b484a57bc302	2088	{
AnnaBridge	153:b484a57bc302	2089	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	153:b484a57bc302	2090	uint32_t PreemptPriorityBits;
AnnaBridge	153:b484a57bc302	2091	uint32_t SubPriorityBits;
AnnaBridge	153:b484a57bc302	2092
AnnaBridge	153:b484a57bc302	2093	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	153:b484a57bc302	2094	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	153:b484a57bc302	2095
AnnaBridge	153:b484a57bc302	2096	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	153:b484a57bc302	2097	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	153:b484a57bc302	2098	}
AnnaBridge	153:b484a57bc302	2099
AnnaBridge	153:b484a57bc302	2100
AnnaBridge	153:b484a57bc302	2101	/**
AnnaBridge	153:b484a57bc302	2102	\brief Set Interrupt Vector
AnnaBridge	153:b484a57bc302	2103	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	153:b484a57bc302	2104	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	153:b484a57bc302	2105	or negative to specify a processor exception.
AnnaBridge	153:b484a57bc302	2106	VTOR must been relocated to SRAM before.
AnnaBridge	153:b484a57bc302	2107	\param [in] IRQn Interrupt number
AnnaBridge	153:b484a57bc302	2108	\param [in] vector Address of interrupt handler function
AnnaBridge	153:b484a57bc302	2109	*/
AnnaBridge	153:b484a57bc302	2110	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	153:b484a57bc302	2111	{
AnnaBridge	153:b484a57bc302	2112	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	153:b484a57bc302	2113	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	153:b484a57bc302	2114	}
AnnaBridge	153:b484a57bc302	2115
AnnaBridge	153:b484a57bc302	2116
AnnaBridge	153:b484a57bc302	2117	/**
AnnaBridge	153:b484a57bc302	2118	\brief Get Interrupt Vector
AnnaBridge	153:b484a57bc302	2119	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	153:b484a57bc302	2120	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	153:b484a57bc302	2121	or negative to specify a processor exception.
AnnaBridge	153:b484a57bc302	2122	\param [in] IRQn Interrupt number.
AnnaBridge	153:b484a57bc302	2123	\return Address of interrupt handler function
AnnaBridge	153:b484a57bc302	2124	*/
AnnaBridge	153:b484a57bc302	2125	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2126	{
AnnaBridge	153:b484a57bc302	2127	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	153:b484a57bc302	2128	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	153:b484a57bc302	2129	}
AnnaBridge	153:b484a57bc302	2130
AnnaBridge	153:b484a57bc302	2131
AnnaBridge	153:b484a57bc302	2132	/**
AnnaBridge	153:b484a57bc302	2133	\brief System Reset
AnnaBridge	153:b484a57bc302	2134	\details Initiates a system reset request to reset the MCU.
AnnaBridge	153:b484a57bc302	2135	*/
AnnaBridge	153:b484a57bc302	2136	__STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	153:b484a57bc302	2137	{
AnnaBridge	153:b484a57bc302	2138	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	153:b484a57bc302	2139	buffered write are completed before reset */
AnnaBridge	153:b484a57bc302	2140	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	153:b484a57bc302	2141	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
AnnaBridge	153:b484a57bc302	2142	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge	153:b484a57bc302	2143	__DSB(); /* Ensure completion of memory access */
AnnaBridge	153:b484a57bc302	2144
AnnaBridge	153:b484a57bc302	2145	for(;;) /* wait until reset */
AnnaBridge	153:b484a57bc302	2146	{
AnnaBridge	153:b484a57bc302	2147	__NOP();
AnnaBridge	153:b484a57bc302	2148	}
AnnaBridge	153:b484a57bc302	2149	}
AnnaBridge	153:b484a57bc302	2150
AnnaBridge	153:b484a57bc302	2151	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	153:b484a57bc302	2152
Anna Bridge	160:5571c4ff569f	2153	/* ########################## MPU functions #################################### */
Anna Bridge	160:5571c4ff569f	2154
Anna Bridge	160:5571c4ff569f	2155	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	2156
Anna Bridge	160:5571c4ff569f	2157	#include "mpu_armv7.h"
Anna Bridge	160:5571c4ff569f	2158
Anna Bridge	160:5571c4ff569f	2159	#endif
AnnaBridge	153:b484a57bc302	2160
AnnaBridge	153:b484a57bc302	2161	/* ########################## FPU functions #################################### */
AnnaBridge	153:b484a57bc302	2162	/**
AnnaBridge	153:b484a57bc302	2163	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	153:b484a57bc302	2164	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	153:b484a57bc302	2165	\brief Function that provides FPU type.
AnnaBridge	153:b484a57bc302	2166	@{
AnnaBridge	153:b484a57bc302	2167	*/
AnnaBridge	153:b484a57bc302	2168
AnnaBridge	153:b484a57bc302	2169	/**
AnnaBridge	153:b484a57bc302	2170	\brief get FPU type
AnnaBridge	153:b484a57bc302	2171	\details returns the FPU type
AnnaBridge	153:b484a57bc302	2172	\returns
AnnaBridge	153:b484a57bc302	2173	- \b 0: No FPU
AnnaBridge	153:b484a57bc302	2174	- \b 1: Single precision FPU
AnnaBridge	153:b484a57bc302	2175	- \b 2: Double + Single precision FPU
AnnaBridge	153:b484a57bc302	2176	*/
AnnaBridge	153:b484a57bc302	2177	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	153:b484a57bc302	2178	{
AnnaBridge	153:b484a57bc302	2179	uint32_t mvfr0;
AnnaBridge	153:b484a57bc302	2180
AnnaBridge	153:b484a57bc302	2181	mvfr0 = SCB->MVFR0;
AnnaBridge	153:b484a57bc302	2182	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
AnnaBridge	153:b484a57bc302	2183	{
AnnaBridge	153:b484a57bc302	2184	return 2U; /* Double + Single precision FPU */
AnnaBridge	153:b484a57bc302	2185	}
AnnaBridge	153:b484a57bc302	2186	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge	153:b484a57bc302	2187	{
AnnaBridge	153:b484a57bc302	2188	return 1U; /* Single precision FPU */
AnnaBridge	153:b484a57bc302	2189	}
AnnaBridge	153:b484a57bc302	2190	else
AnnaBridge	153:b484a57bc302	2191	{
AnnaBridge	153:b484a57bc302	2192	return 0U; /* No FPU */
AnnaBridge	153:b484a57bc302	2193	}
AnnaBridge	153:b484a57bc302	2194	}
AnnaBridge	153:b484a57bc302	2195
AnnaBridge	153:b484a57bc302	2196
AnnaBridge	153:b484a57bc302	2197	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	153:b484a57bc302	2198
AnnaBridge	153:b484a57bc302	2199
AnnaBridge	153:b484a57bc302	2200
AnnaBridge	153:b484a57bc302	2201	/* ########################## Cache functions #################################### */
AnnaBridge	153:b484a57bc302	2202	/**
AnnaBridge	153:b484a57bc302	2203	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	153:b484a57bc302	2204	\defgroup CMSIS_Core_CacheFunctions Cache Functions
AnnaBridge	153:b484a57bc302	2205	\brief Functions that configure Instruction and Data cache.
AnnaBridge	153:b484a57bc302	2206	@{
AnnaBridge	153:b484a57bc302	2207	*/
AnnaBridge	153:b484a57bc302	2208
AnnaBridge	153:b484a57bc302	2209	/* Cache Size ID Register Macros */
AnnaBridge	153:b484a57bc302	2210	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
AnnaBridge	153:b484a57bc302	2211	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
AnnaBridge	153:b484a57bc302	2212
AnnaBridge	153:b484a57bc302	2213
AnnaBridge	153:b484a57bc302	2214	/**
AnnaBridge	153:b484a57bc302	2215	\brief Enable I-Cache
AnnaBridge	153:b484a57bc302	2216	\details Turns on I-Cache
AnnaBridge	153:b484a57bc302	2217	*/
AnnaBridge	153:b484a57bc302	2218	__STATIC_INLINE void SCB_EnableICache (void)
AnnaBridge	153:b484a57bc302	2219	{
AnnaBridge	153:b484a57bc302	2220	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2221	__DSB();
AnnaBridge	153:b484a57bc302	2222	__ISB();
AnnaBridge	153:b484a57bc302	2223	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
AnnaBridge	153:b484a57bc302	2224	__DSB();
AnnaBridge	153:b484a57bc302	2225	__ISB();
AnnaBridge	153:b484a57bc302	2226	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
AnnaBridge	153:b484a57bc302	2227	__DSB();
AnnaBridge	153:b484a57bc302	2228	__ISB();
AnnaBridge	153:b484a57bc302	2229	#endif
AnnaBridge	153:b484a57bc302	2230	}
AnnaBridge	153:b484a57bc302	2231
AnnaBridge	153:b484a57bc302	2232
AnnaBridge	153:b484a57bc302	2233	/**
AnnaBridge	153:b484a57bc302	2234	\brief Disable I-Cache
AnnaBridge	153:b484a57bc302	2235	\details Turns off I-Cache
AnnaBridge	153:b484a57bc302	2236	*/
AnnaBridge	153:b484a57bc302	2237	__STATIC_INLINE void SCB_DisableICache (void)
AnnaBridge	153:b484a57bc302	2238	{
AnnaBridge	153:b484a57bc302	2239	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2240	__DSB();
AnnaBridge	153:b484a57bc302	2241	__ISB();
AnnaBridge	153:b484a57bc302	2242	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
AnnaBridge	153:b484a57bc302	2243	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
AnnaBridge	153:b484a57bc302	2244	__DSB();
AnnaBridge	153:b484a57bc302	2245	__ISB();
AnnaBridge	153:b484a57bc302	2246	#endif
AnnaBridge	153:b484a57bc302	2247	}
AnnaBridge	153:b484a57bc302	2248
AnnaBridge	153:b484a57bc302	2249
AnnaBridge	153:b484a57bc302	2250	/**
AnnaBridge	153:b484a57bc302	2251	\brief Invalidate I-Cache
AnnaBridge	153:b484a57bc302	2252	\details Invalidates I-Cache
AnnaBridge	153:b484a57bc302	2253	*/
AnnaBridge	153:b484a57bc302	2254	__STATIC_INLINE void SCB_InvalidateICache (void)
AnnaBridge	153:b484a57bc302	2255	{
AnnaBridge	153:b484a57bc302	2256	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2257	__DSB();
AnnaBridge	153:b484a57bc302	2258	__ISB();
AnnaBridge	153:b484a57bc302	2259	SCB->ICIALLU = 0UL;
AnnaBridge	153:b484a57bc302	2260	__DSB();
AnnaBridge	153:b484a57bc302	2261	__ISB();
AnnaBridge	153:b484a57bc302	2262	#endif
AnnaBridge	153:b484a57bc302	2263	}
AnnaBridge	153:b484a57bc302	2264
AnnaBridge	153:b484a57bc302	2265
AnnaBridge	153:b484a57bc302	2266	/**
AnnaBridge	153:b484a57bc302	2267	\brief Enable D-Cache
AnnaBridge	153:b484a57bc302	2268	\details Turns on D-Cache
AnnaBridge	153:b484a57bc302	2269	*/
AnnaBridge	153:b484a57bc302	2270	__STATIC_INLINE void SCB_EnableDCache (void)
AnnaBridge	153:b484a57bc302	2271	{
AnnaBridge	153:b484a57bc302	2272	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2273	uint32_t ccsidr;
AnnaBridge	153:b484a57bc302	2274	uint32_t sets;
AnnaBridge	153:b484a57bc302	2275	uint32_t ways;
AnnaBridge	153:b484a57bc302	2276
AnnaBridge	153:b484a57bc302	2277	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	153:b484a57bc302	2278	__DSB();
AnnaBridge	153:b484a57bc302	2279
AnnaBridge	153:b484a57bc302	2280	ccsidr = SCB->CCSIDR;
AnnaBridge	153:b484a57bc302	2281
AnnaBridge	153:b484a57bc302	2282	/* invalidate D-Cache */
AnnaBridge	153:b484a57bc302	2283	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	153:b484a57bc302	2284	do {
AnnaBridge	153:b484a57bc302	2285	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	153:b484a57bc302	2286	do {
AnnaBridge	153:b484a57bc302	2287	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
AnnaBridge	153:b484a57bc302	2288	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
AnnaBridge	153:b484a57bc302	2289	#if defined ( __CC_ARM )
AnnaBridge	153:b484a57bc302	2290	__schedule_barrier();
AnnaBridge	153:b484a57bc302	2291	#endif
AnnaBridge	153:b484a57bc302	2292	} while (ways-- != 0U);
AnnaBridge	153:b484a57bc302	2293	} while(sets-- != 0U);
AnnaBridge	153:b484a57bc302	2294	__DSB();
AnnaBridge	153:b484a57bc302	2295
AnnaBridge	153:b484a57bc302	2296	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
AnnaBridge	153:b484a57bc302	2297
AnnaBridge	153:b484a57bc302	2298	__DSB();
AnnaBridge	153:b484a57bc302	2299	__ISB();
AnnaBridge	153:b484a57bc302	2300	#endif
AnnaBridge	153:b484a57bc302	2301	}
AnnaBridge	153:b484a57bc302	2302
AnnaBridge	153:b484a57bc302	2303
AnnaBridge	153:b484a57bc302	2304	/**
AnnaBridge	153:b484a57bc302	2305	\brief Disable D-Cache
AnnaBridge	153:b484a57bc302	2306	\details Turns off D-Cache
AnnaBridge	153:b484a57bc302	2307	*/
AnnaBridge	153:b484a57bc302	2308	__STATIC_INLINE void SCB_DisableDCache (void)
AnnaBridge	153:b484a57bc302	2309	{
AnnaBridge	153:b484a57bc302	2310	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2311	register uint32_t ccsidr;
AnnaBridge	153:b484a57bc302	2312	register uint32_t sets;
AnnaBridge	153:b484a57bc302	2313	register uint32_t ways;
AnnaBridge	153:b484a57bc302	2314
AnnaBridge	153:b484a57bc302	2315	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	153:b484a57bc302	2316	__DSB();
AnnaBridge	153:b484a57bc302	2317
AnnaBridge	153:b484a57bc302	2318	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
AnnaBridge	153:b484a57bc302	2319	__DSB();
AnnaBridge	153:b484a57bc302	2320
AnnaBridge	153:b484a57bc302	2321	ccsidr = SCB->CCSIDR;
AnnaBridge	153:b484a57bc302	2322
AnnaBridge	153:b484a57bc302	2323	/* clean & invalidate D-Cache */
AnnaBridge	153:b484a57bc302	2324	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	153:b484a57bc302	2325	do {
AnnaBridge	153:b484a57bc302	2326	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	153:b484a57bc302	2327	do {
AnnaBridge	153:b484a57bc302	2328	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
AnnaBridge	153:b484a57bc302	2329	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
AnnaBridge	153:b484a57bc302	2330	#if defined ( __CC_ARM )
AnnaBridge	153:b484a57bc302	2331	__schedule_barrier();
AnnaBridge	153:b484a57bc302	2332	#endif
AnnaBridge	153:b484a57bc302	2333	} while (ways-- != 0U);
AnnaBridge	153:b484a57bc302	2334	} while(sets-- != 0U);
AnnaBridge	153:b484a57bc302	2335
AnnaBridge	153:b484a57bc302	2336	__DSB();
AnnaBridge	153:b484a57bc302	2337	__ISB();
AnnaBridge	153:b484a57bc302	2338	#endif
AnnaBridge	153:b484a57bc302	2339	}
AnnaBridge	153:b484a57bc302	2340
AnnaBridge	153:b484a57bc302	2341
AnnaBridge	153:b484a57bc302	2342	/**
AnnaBridge	153:b484a57bc302	2343	\brief Invalidate D-Cache
AnnaBridge	153:b484a57bc302	2344	\details Invalidates D-Cache
AnnaBridge	153:b484a57bc302	2345	*/
AnnaBridge	153:b484a57bc302	2346	__STATIC_INLINE void SCB_InvalidateDCache (void)
AnnaBridge	153:b484a57bc302	2347	{
AnnaBridge	153:b484a57bc302	2348	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2349	uint32_t ccsidr;
AnnaBridge	153:b484a57bc302	2350	uint32_t sets;
AnnaBridge	153:b484a57bc302	2351	uint32_t ways;
AnnaBridge	153:b484a57bc302	2352
AnnaBridge	153:b484a57bc302	2353	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	153:b484a57bc302	2354	__DSB();
AnnaBridge	153:b484a57bc302	2355
AnnaBridge	153:b484a57bc302	2356	ccsidr = SCB->CCSIDR;
AnnaBridge	153:b484a57bc302	2357
AnnaBridge	153:b484a57bc302	2358	/* invalidate D-Cache */
AnnaBridge	153:b484a57bc302	2359	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	153:b484a57bc302	2360	do {
AnnaBridge	153:b484a57bc302	2361	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	153:b484a57bc302	2362	do {
AnnaBridge	153:b484a57bc302	2363	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
AnnaBridge	153:b484a57bc302	2364	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
AnnaBridge	153:b484a57bc302	2365	#if defined ( __CC_ARM )
AnnaBridge	153:b484a57bc302	2366	__schedule_barrier();
AnnaBridge	153:b484a57bc302	2367	#endif
AnnaBridge	153:b484a57bc302	2368	} while (ways-- != 0U);
AnnaBridge	153:b484a57bc302	2369	} while(sets-- != 0U);
AnnaBridge	153:b484a57bc302	2370
AnnaBridge	153:b484a57bc302	2371	__DSB();
AnnaBridge	153:b484a57bc302	2372	__ISB();
AnnaBridge	153:b484a57bc302	2373	#endif
AnnaBridge	153:b484a57bc302	2374	}
AnnaBridge	153:b484a57bc302	2375
AnnaBridge	153:b484a57bc302	2376
AnnaBridge	153:b484a57bc302	2377	/**
AnnaBridge	153:b484a57bc302	2378	\brief Clean D-Cache
AnnaBridge	153:b484a57bc302	2379	\details Cleans D-Cache
AnnaBridge	153:b484a57bc302	2380	*/
AnnaBridge	153:b484a57bc302	2381	__STATIC_INLINE void SCB_CleanDCache (void)
AnnaBridge	153:b484a57bc302	2382	{
AnnaBridge	153:b484a57bc302	2383	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2384	uint32_t ccsidr;
AnnaBridge	153:b484a57bc302	2385	uint32_t sets;
AnnaBridge	153:b484a57bc302	2386	uint32_t ways;
AnnaBridge	153:b484a57bc302	2387
AnnaBridge	153:b484a57bc302	2388	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	153:b484a57bc302	2389	__DSB();
AnnaBridge	153:b484a57bc302	2390
AnnaBridge	153:b484a57bc302	2391	ccsidr = SCB->CCSIDR;
AnnaBridge	153:b484a57bc302	2392
AnnaBridge	153:b484a57bc302	2393	/* clean D-Cache */
AnnaBridge	153:b484a57bc302	2394	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	153:b484a57bc302	2395	do {
AnnaBridge	153:b484a57bc302	2396	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	153:b484a57bc302	2397	do {
AnnaBridge	153:b484a57bc302	2398	SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) \|
AnnaBridge	153:b484a57bc302	2399	((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
AnnaBridge	153:b484a57bc302	2400	#if defined ( __CC_ARM )
AnnaBridge	153:b484a57bc302	2401	__schedule_barrier();
AnnaBridge	153:b484a57bc302	2402	#endif
AnnaBridge	153:b484a57bc302	2403	} while (ways-- != 0U);
AnnaBridge	153:b484a57bc302	2404	} while(sets-- != 0U);
AnnaBridge	153:b484a57bc302	2405
AnnaBridge	153:b484a57bc302	2406	__DSB();
AnnaBridge	153:b484a57bc302	2407	__ISB();
AnnaBridge	153:b484a57bc302	2408	#endif
AnnaBridge	153:b484a57bc302	2409	}
AnnaBridge	153:b484a57bc302	2410
AnnaBridge	153:b484a57bc302	2411
AnnaBridge	153:b484a57bc302	2412	/**
AnnaBridge	153:b484a57bc302	2413	\brief Clean & Invalidate D-Cache
AnnaBridge	153:b484a57bc302	2414	\details Cleans and Invalidates D-Cache
AnnaBridge	153:b484a57bc302	2415	*/
AnnaBridge	153:b484a57bc302	2416	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
AnnaBridge	153:b484a57bc302	2417	{
AnnaBridge	153:b484a57bc302	2418	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2419	uint32_t ccsidr;
AnnaBridge	153:b484a57bc302	2420	uint32_t sets;
AnnaBridge	153:b484a57bc302	2421	uint32_t ways;
AnnaBridge	153:b484a57bc302	2422
AnnaBridge	153:b484a57bc302	2423	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	153:b484a57bc302	2424	__DSB();
AnnaBridge	153:b484a57bc302	2425
AnnaBridge	153:b484a57bc302	2426	ccsidr = SCB->CCSIDR;
AnnaBridge	153:b484a57bc302	2427
AnnaBridge	153:b484a57bc302	2428	/* clean & invalidate D-Cache */
AnnaBridge	153:b484a57bc302	2429	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	153:b484a57bc302	2430	do {
AnnaBridge	153:b484a57bc302	2431	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	153:b484a57bc302	2432	do {
AnnaBridge	153:b484a57bc302	2433	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
AnnaBridge	153:b484a57bc302	2434	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
AnnaBridge	153:b484a57bc302	2435	#if defined ( __CC_ARM )
AnnaBridge	153:b484a57bc302	2436	__schedule_barrier();
AnnaBridge	153:b484a57bc302	2437	#endif
AnnaBridge	153:b484a57bc302	2438	} while (ways-- != 0U);
AnnaBridge	153:b484a57bc302	2439	} while(sets-- != 0U);
AnnaBridge	153:b484a57bc302	2440
AnnaBridge	153:b484a57bc302	2441	__DSB();
AnnaBridge	153:b484a57bc302	2442	__ISB();
AnnaBridge	153:b484a57bc302	2443	#endif
AnnaBridge	153:b484a57bc302	2444	}
AnnaBridge	153:b484a57bc302	2445
AnnaBridge	153:b484a57bc302	2446
AnnaBridge	153:b484a57bc302	2447	/**
AnnaBridge	153:b484a57bc302	2448	\brief D-Cache Invalidate by address
AnnaBridge	153:b484a57bc302	2449	\details Invalidates D-Cache for the given address
AnnaBridge	153:b484a57bc302	2450	\param[in] addr address (aligned to 32-byte boundary)
AnnaBridge	153:b484a57bc302	2451	\param[in] dsize size of memory block (in number of bytes)
AnnaBridge	153:b484a57bc302	2452	*/
AnnaBridge	153:b484a57bc302	2453	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge	153:b484a57bc302	2454	{
AnnaBridge	153:b484a57bc302	2455	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2456	int32_t op_size = dsize;
AnnaBridge	153:b484a57bc302	2457	uint32_t op_addr = (uint32_t)addr;
AnnaBridge	153:b484a57bc302	2458	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
AnnaBridge	153:b484a57bc302	2459
AnnaBridge	153:b484a57bc302	2460	__DSB();
AnnaBridge	153:b484a57bc302	2461
AnnaBridge	153:b484a57bc302	2462	while (op_size > 0) {
AnnaBridge	153:b484a57bc302	2463	SCB->DCIMVAC = op_addr;
AnnaBridge	153:b484a57bc302	2464	op_addr += (uint32_t)linesize;
AnnaBridge	153:b484a57bc302	2465	op_size -= linesize;
AnnaBridge	153:b484a57bc302	2466	}
AnnaBridge	153:b484a57bc302	2467
AnnaBridge	153:b484a57bc302	2468	__DSB();
AnnaBridge	153:b484a57bc302	2469	__ISB();
AnnaBridge	153:b484a57bc302	2470	#endif
AnnaBridge	153:b484a57bc302	2471	}
AnnaBridge	153:b484a57bc302	2472
AnnaBridge	153:b484a57bc302	2473
AnnaBridge	153:b484a57bc302	2474	/**
AnnaBridge	153:b484a57bc302	2475	\brief D-Cache Clean by address
AnnaBridge	153:b484a57bc302	2476	\details Cleans D-Cache for the given address
AnnaBridge	153:b484a57bc302	2477	\param[in] addr address (aligned to 32-byte boundary)
AnnaBridge	153:b484a57bc302	2478	\param[in] dsize size of memory block (in number of bytes)
AnnaBridge	153:b484a57bc302	2479	*/
AnnaBridge	153:b484a57bc302	2480	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge	153:b484a57bc302	2481	{
AnnaBridge	153:b484a57bc302	2482	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2483	int32_t op_size = dsize;
AnnaBridge	153:b484a57bc302	2484	uint32_t op_addr = (uint32_t) addr;
AnnaBridge	153:b484a57bc302	2485	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
AnnaBridge	153:b484a57bc302	2486
AnnaBridge	153:b484a57bc302	2487	__DSB();
AnnaBridge	153:b484a57bc302	2488
AnnaBridge	153:b484a57bc302	2489	while (op_size > 0) {
AnnaBridge	153:b484a57bc302	2490	SCB->DCCMVAC = op_addr;
AnnaBridge	153:b484a57bc302	2491	op_addr += (uint32_t)linesize;
AnnaBridge	153:b484a57bc302	2492	op_size -= linesize;
AnnaBridge	153:b484a57bc302	2493	}
AnnaBridge	153:b484a57bc302	2494
AnnaBridge	153:b484a57bc302	2495	__DSB();
AnnaBridge	153:b484a57bc302	2496	__ISB();
AnnaBridge	153:b484a57bc302	2497	#endif
AnnaBridge	153:b484a57bc302	2498	}
AnnaBridge	153:b484a57bc302	2499
AnnaBridge	153:b484a57bc302	2500
AnnaBridge	153:b484a57bc302	2501	/**
AnnaBridge	153:b484a57bc302	2502	\brief D-Cache Clean and Invalidate by address
AnnaBridge	153:b484a57bc302	2503	\details Cleans and invalidates D_Cache for the given address
AnnaBridge	153:b484a57bc302	2504	\param[in] addr address (aligned to 32-byte boundary)
AnnaBridge	153:b484a57bc302	2505	\param[in] dsize size of memory block (in number of bytes)
AnnaBridge	153:b484a57bc302	2506	*/
AnnaBridge	153:b484a57bc302	2507	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge	153:b484a57bc302	2508	{
AnnaBridge	153:b484a57bc302	2509	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2510	int32_t op_size = dsize;
AnnaBridge	153:b484a57bc302	2511	uint32_t op_addr = (uint32_t) addr;
AnnaBridge	153:b484a57bc302	2512	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
AnnaBridge	153:b484a57bc302	2513
AnnaBridge	153:b484a57bc302	2514	__DSB();
AnnaBridge	153:b484a57bc302	2515
AnnaBridge	153:b484a57bc302	2516	while (op_size > 0) {
AnnaBridge	153:b484a57bc302	2517	SCB->DCCIMVAC = op_addr;
AnnaBridge	153:b484a57bc302	2518	op_addr += (uint32_t)linesize;
AnnaBridge	153:b484a57bc302	2519	op_size -= linesize;
AnnaBridge	153:b484a57bc302	2520	}
AnnaBridge	153:b484a57bc302	2521
AnnaBridge	153:b484a57bc302	2522	__DSB();
AnnaBridge	153:b484a57bc302	2523	__ISB();
AnnaBridge	153:b484a57bc302	2524	#endif
AnnaBridge	153:b484a57bc302	2525	}
AnnaBridge	153:b484a57bc302	2526
AnnaBridge	153:b484a57bc302	2527
AnnaBridge	153:b484a57bc302	2528	/@} end of CMSIS_Core_CacheFunctions /
AnnaBridge	153:b484a57bc302	2529
AnnaBridge	153:b484a57bc302	2530
AnnaBridge	153:b484a57bc302	2531
AnnaBridge	153:b484a57bc302	2532	/* ################################## SysTick function ############################################ */
AnnaBridge	153:b484a57bc302	2533	/**
AnnaBridge	153:b484a57bc302	2534	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	153:b484a57bc302	2535	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	153:b484a57bc302	2536	\brief Functions that configure the System.
AnnaBridge	153:b484a57bc302	2537	@{
AnnaBridge	153:b484a57bc302	2538	*/
AnnaBridge	153:b484a57bc302	2539
AnnaBridge	153:b484a57bc302	2540	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	153:b484a57bc302	2541
AnnaBridge	153:b484a57bc302	2542	/**
AnnaBridge	153:b484a57bc302	2543	\brief System Tick Configuration
AnnaBridge	153:b484a57bc302	2544	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	153:b484a57bc302	2545	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	153:b484a57bc302	2546	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	153:b484a57bc302	2547	\return 0 Function succeeded.
AnnaBridge	153:b484a57bc302	2548	\return 1 Function failed.
AnnaBridge	153:b484a57bc302	2549	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	153:b484a57bc302	2550	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	153:b484a57bc302	2551	must contain a vendor-specific implementation of this function.
AnnaBridge	153:b484a57bc302	2552	*/
AnnaBridge	153:b484a57bc302	2553	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	153:b484a57bc302	2554	{
AnnaBridge	153:b484a57bc302	2555	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	153:b484a57bc302	2556	{
AnnaBridge	153:b484a57bc302	2557	return (1UL); /* Reload value impossible */
AnnaBridge	153:b484a57bc302	2558	}
AnnaBridge	153:b484a57bc302	2559
AnnaBridge	153:b484a57bc302	2560	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	153:b484a57bc302	2561	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	153:b484a57bc302	2562	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	153:b484a57bc302	2563	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	153:b484a57bc302	2564	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	153:b484a57bc302	2565	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	153:b484a57bc302	2566	return (0UL); /* Function successful */
AnnaBridge	153:b484a57bc302	2567	}
AnnaBridge	153:b484a57bc302	2568
AnnaBridge	153:b484a57bc302	2569	#endif
AnnaBridge	153:b484a57bc302	2570
AnnaBridge	153:b484a57bc302	2571	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	153:b484a57bc302	2572
AnnaBridge	153:b484a57bc302	2573
AnnaBridge	153:b484a57bc302	2574
AnnaBridge	153:b484a57bc302	2575	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	153:b484a57bc302	2576	/**
AnnaBridge	153:b484a57bc302	2577	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	153:b484a57bc302	2578	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	153:b484a57bc302	2579	\brief Functions that access the ITM debug interface.
AnnaBridge	153:b484a57bc302	2580	@{
AnnaBridge	153:b484a57bc302	2581	*/
AnnaBridge	153:b484a57bc302	2582
AnnaBridge	153:b484a57bc302	2583	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	153:b484a57bc302	2584	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
AnnaBridge	153:b484a57bc302	2585
AnnaBridge	153:b484a57bc302	2586
AnnaBridge	153:b484a57bc302	2587	/**
AnnaBridge	153:b484a57bc302	2588	\brief ITM Send Character
AnnaBridge	153:b484a57bc302	2589	\details Transmits a character via the ITM channel 0, and
AnnaBridge	153:b484a57bc302	2590	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	153:b484a57bc302	2591	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	153:b484a57bc302	2592	\param [in] ch Character to transmit.
AnnaBridge	153:b484a57bc302	2593	\returns Character to transmit.
AnnaBridge	153:b484a57bc302	2594	*/
AnnaBridge	153:b484a57bc302	2595	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge	153:b484a57bc302	2596	{
AnnaBridge	153:b484a57bc302	2597	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge	153:b484a57bc302	2598	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge	153:b484a57bc302	2599	{
AnnaBridge	153:b484a57bc302	2600	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	153:b484a57bc302	2601	{
AnnaBridge	153:b484a57bc302	2602	__NOP();
AnnaBridge	153:b484a57bc302	2603	}
AnnaBridge	153:b484a57bc302	2604	ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge	153:b484a57bc302	2605	}
AnnaBridge	153:b484a57bc302	2606	return (ch);
AnnaBridge	153:b484a57bc302	2607	}
AnnaBridge	153:b484a57bc302	2608
AnnaBridge	153:b484a57bc302	2609
AnnaBridge	153:b484a57bc302	2610	/**
AnnaBridge	153:b484a57bc302	2611	\brief ITM Receive Character
AnnaBridge	153:b484a57bc302	2612	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	153:b484a57bc302	2613	\return Received character.
AnnaBridge	153:b484a57bc302	2614	\return -1 No character pending.
AnnaBridge	153:b484a57bc302	2615	*/
AnnaBridge	153:b484a57bc302	2616	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	153:b484a57bc302	2617	{
AnnaBridge	153:b484a57bc302	2618	int32_t ch = -1; /* no character available */
AnnaBridge	153:b484a57bc302	2619
AnnaBridge	153:b484a57bc302	2620	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	153:b484a57bc302	2621	{
AnnaBridge	153:b484a57bc302	2622	ch = ITM_RxBuffer;
AnnaBridge	153:b484a57bc302	2623	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge	153:b484a57bc302	2624	}
AnnaBridge	153:b484a57bc302	2625
AnnaBridge	153:b484a57bc302	2626	return (ch);
AnnaBridge	153:b484a57bc302	2627	}
AnnaBridge	153:b484a57bc302	2628
AnnaBridge	153:b484a57bc302	2629
AnnaBridge	153:b484a57bc302	2630	/**
AnnaBridge	153:b484a57bc302	2631	\brief ITM Check Character
AnnaBridge	153:b484a57bc302	2632	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	153:b484a57bc302	2633	\return 0 No character available.
AnnaBridge	153:b484a57bc302	2634	\return 1 Character available.
AnnaBridge	153:b484a57bc302	2635	*/
AnnaBridge	153:b484a57bc302	2636	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	153:b484a57bc302	2637	{
AnnaBridge	153:b484a57bc302	2638
AnnaBridge	153:b484a57bc302	2639	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	153:b484a57bc302	2640	{
AnnaBridge	153:b484a57bc302	2641	return (0); /* no character available */
AnnaBridge	153:b484a57bc302	2642	}
AnnaBridge	153:b484a57bc302	2643	else
AnnaBridge	153:b484a57bc302	2644	{
AnnaBridge	153:b484a57bc302	2645	return (1); /* character available */
AnnaBridge	153:b484a57bc302	2646	}
AnnaBridge	153:b484a57bc302	2647	}
AnnaBridge	153:b484a57bc302	2648
AnnaBridge	153:b484a57bc302	2649	/@} end of CMSIS_core_DebugFunctions /
AnnaBridge	153:b484a57bc302	2650
AnnaBridge	153:b484a57bc302	2651
AnnaBridge	153:b484a57bc302	2652
AnnaBridge	153:b484a57bc302	2653
AnnaBridge	153:b484a57bc302	2654	#ifdef __cplusplus
AnnaBridge	153:b484a57bc302	2655	}
AnnaBridge	153:b484a57bc302	2656	#endif
AnnaBridge	153:b484a57bc302	2657
AnnaBridge	153:b484a57bc302	2658	#endif /* __CORE_CM7_H_DEPENDANT */
AnnaBridge	153:b484a57bc302	2659
AnnaBridge	153:b484a57bc302	2660	#endif /* __CMSIS_GENERIC */