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TARGET_LPC546XX/core_armv8mml.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:: AnnaBridge
Date:: Thu Sep 06 13:39:34 2018 +0100
Revision:: 170:e95d10626187
Parent:: 169:a7c7b631e539

mbed library. Release version 163

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	153:b484a57bc302	1	/************************************************************************//
AnnaBridge	153:b484a57bc302	2	* @file core_armv8mml.h
Anna Bridge	169:a7c7b631e539	3	* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
Anna Bridge	169:a7c7b631e539	4	* @version V5.0.4
Anna Bridge	169:a7c7b631e539	5	* @date 10. January 2018
AnnaBridge	153:b484a57bc302	6	******************************************************************************/
AnnaBridge	153:b484a57bc302	7	/*
Anna Bridge	169:a7c7b631e539	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge	153:b484a57bc302	9	*
AnnaBridge	153:b484a57bc302	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	153:b484a57bc302	11	*
AnnaBridge	153:b484a57bc302	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	153:b484a57bc302	13	* not use this file except in compliance with the License.
AnnaBridge	153:b484a57bc302	14	* You may obtain a copy of the License at
AnnaBridge	153:b484a57bc302	15	*
AnnaBridge	153:b484a57bc302	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	153:b484a57bc302	17	*
AnnaBridge	153:b484a57bc302	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	153:b484a57bc302	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	153:b484a57bc302	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	153:b484a57bc302	21	* See the License for the specific language governing permissions and
AnnaBridge	153:b484a57bc302	22	* limitations under the License.
AnnaBridge	153:b484a57bc302	23	*/
AnnaBridge	153:b484a57bc302	24
AnnaBridge	153:b484a57bc302	25	#if defined ( __ICCARM__ )
Anna Bridge	169:a7c7b631e539	26	#pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge	169:a7c7b631e539	27	#elif defined (__clang__)
AnnaBridge	153:b484a57bc302	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	153:b484a57bc302	29	#endif
AnnaBridge	153:b484a57bc302	30
AnnaBridge	153:b484a57bc302	31	#ifndef __CORE_ARMV8MML_H_GENERIC
AnnaBridge	153:b484a57bc302	32	#define __CORE_ARMV8MML_H_GENERIC
AnnaBridge	153:b484a57bc302	33
AnnaBridge	153:b484a57bc302	34	#include <stdint.h>
AnnaBridge	153:b484a57bc302	35
AnnaBridge	153:b484a57bc302	36	#ifdef __cplusplus
AnnaBridge	153:b484a57bc302	37	extern "C" {
AnnaBridge	153:b484a57bc302	38	#endif
AnnaBridge	153:b484a57bc302	39
AnnaBridge	153:b484a57bc302	40	/**
AnnaBridge	153:b484a57bc302	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	153:b484a57bc302	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	153:b484a57bc302	43
AnnaBridge	153:b484a57bc302	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	153:b484a57bc302	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	153:b484a57bc302	46
AnnaBridge	153:b484a57bc302	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	153:b484a57bc302	48	Unions are used for effective representation of core registers.
AnnaBridge	153:b484a57bc302	49
AnnaBridge	153:b484a57bc302	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	153:b484a57bc302	51	Function-like macros are used to allow more efficient code.
AnnaBridge	153:b484a57bc302	52	*/
AnnaBridge	153:b484a57bc302	53
AnnaBridge	153:b484a57bc302	54
AnnaBridge	153:b484a57bc302	55	/*******************************************************************************
AnnaBridge	153:b484a57bc302	56	* CMSIS definitions
AnnaBridge	153:b484a57bc302	57	******************************************************************************/
AnnaBridge	153:b484a57bc302	58	/**
AnnaBridge	153:b484a57bc302	59	\ingroup Cortex_ARMv8MML
AnnaBridge	153:b484a57bc302	60	@{
AnnaBridge	153:b484a57bc302	61	*/
AnnaBridge	153:b484a57bc302	62
Anna Bridge	160:5571c4ff569f	63	#include "cmsis_version.h"
Anna Bridge	160:5571c4ff569f	64
Anna Bridge	169:a7c7b631e539	65	/* CMSIS Armv8MML definitions */
Anna Bridge	160:5571c4ff569f	66	#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
Anna Bridge	160:5571c4ff569f	67	#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
AnnaBridge	153:b484a57bc302	68	#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) \| \
Anna Bridge	160:5571c4ff569f	69	__ARMv8MML_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
AnnaBridge	153:b484a57bc302	70
AnnaBridge	153:b484a57bc302	71	#define __CORTEX_M (81U) /!< Cortex-M Core /
AnnaBridge	153:b484a57bc302	72
AnnaBridge	153:b484a57bc302	73	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	153:b484a57bc302	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge	153:b484a57bc302	75	*/
AnnaBridge	153:b484a57bc302	76	#if defined ( __CC_ARM )
AnnaBridge	153:b484a57bc302	77	#if defined __TARGET_FPU_VFP
AnnaBridge	153:b484a57bc302	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	79	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	80	#else
AnnaBridge	153:b484a57bc302	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	82	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	83	#endif
AnnaBridge	153:b484a57bc302	84	#else
AnnaBridge	153:b484a57bc302	85	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	86	#endif
AnnaBridge	153:b484a57bc302	87
Anna Bridge	160:5571c4ff569f	88	#if defined(__ARM_FEATURE_DSP)
Anna Bridge	160:5571c4ff569f	89	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	90	#define __DSP_USED 1U
Anna Bridge	160:5571c4ff569f	91	#else
Anna Bridge	160:5571c4ff569f	92	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge	160:5571c4ff569f	93	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	94	#endif
Anna Bridge	160:5571c4ff569f	95	#else
Anna Bridge	160:5571c4ff569f	96	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	97	#endif
Anna Bridge	160:5571c4ff569f	98
AnnaBridge	153:b484a57bc302	99	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	153:b484a57bc302	100	#if defined __ARM_PCS_VFP
AnnaBridge	153:b484a57bc302	101	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	102	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	103	#else
AnnaBridge	153:b484a57bc302	104	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	105	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	106	#endif
AnnaBridge	153:b484a57bc302	107	#else
AnnaBridge	153:b484a57bc302	108	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	109	#endif
AnnaBridge	153:b484a57bc302	110
Anna Bridge	160:5571c4ff569f	111	#if defined(__ARM_FEATURE_DSP)
Anna Bridge	160:5571c4ff569f	112	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	113	#define __DSP_USED 1U
Anna Bridge	160:5571c4ff569f	114	#else
Anna Bridge	160:5571c4ff569f	115	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge	160:5571c4ff569f	116	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	117	#endif
Anna Bridge	160:5571c4ff569f	118	#else
Anna Bridge	160:5571c4ff569f	119	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	120	#endif
Anna Bridge	160:5571c4ff569f	121
AnnaBridge	153:b484a57bc302	122	#elif defined ( __GNUC__ )
AnnaBridge	153:b484a57bc302	123	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	153:b484a57bc302	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	125	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	126	#else
AnnaBridge	153:b484a57bc302	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	128	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	129	#endif
AnnaBridge	153:b484a57bc302	130	#else
AnnaBridge	153:b484a57bc302	131	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	132	#endif
Anna Bridge	160:5571c4ff569f	133
Anna Bridge	160:5571c4ff569f	134	#if defined(__ARM_FEATURE_DSP)
Anna Bridge	160:5571c4ff569f	135	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	136	#define __DSP_USED 1U
Anna Bridge	160:5571c4ff569f	137	#else
Anna Bridge	160:5571c4ff569f	138	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge	160:5571c4ff569f	139	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	140	#endif
Anna Bridge	160:5571c4ff569f	141	#else
Anna Bridge	160:5571c4ff569f	142	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	143	#endif
Anna Bridge	160:5571c4ff569f	144
AnnaBridge	153:b484a57bc302	145	#elif defined ( __ICCARM__ )
AnnaBridge	153:b484a57bc302	146	#if defined __ARMVFP__
AnnaBridge	153:b484a57bc302	147	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	148	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	149	#else
AnnaBridge	153:b484a57bc302	150	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	151	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	152	#endif
AnnaBridge	153:b484a57bc302	153	#else
AnnaBridge	153:b484a57bc302	154	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	155	#endif
AnnaBridge	153:b484a57bc302	156
Anna Bridge	160:5571c4ff569f	157	#if defined(__ARM_FEATURE_DSP)
Anna Bridge	160:5571c4ff569f	158	#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	159	#define __DSP_USED 1U
Anna Bridge	160:5571c4ff569f	160	#else
Anna Bridge	160:5571c4ff569f	161	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge	160:5571c4ff569f	162	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	163	#endif
Anna Bridge	160:5571c4ff569f	164	#else
Anna Bridge	160:5571c4ff569f	165	#define __DSP_USED 0U
Anna Bridge	160:5571c4ff569f	166	#endif
Anna Bridge	160:5571c4ff569f	167
AnnaBridge	153:b484a57bc302	168	#elif defined ( __TI_ARM__ )
AnnaBridge	153:b484a57bc302	169	#if defined __TI_VFP_SUPPORT__
AnnaBridge	153:b484a57bc302	170	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	171	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	172	#else
AnnaBridge	153:b484a57bc302	173	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	174	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	175	#endif
AnnaBridge	153:b484a57bc302	176	#else
AnnaBridge	153:b484a57bc302	177	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	178	#endif
AnnaBridge	153:b484a57bc302	179
AnnaBridge	153:b484a57bc302	180	#elif defined ( __TASKING__ )
AnnaBridge	153:b484a57bc302	181	#if defined __FPU_VFP__
AnnaBridge	153:b484a57bc302	182	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	183	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	184	#else
AnnaBridge	153:b484a57bc302	185	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	186	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	187	#endif
AnnaBridge	153:b484a57bc302	188	#else
AnnaBridge	153:b484a57bc302	189	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	190	#endif
AnnaBridge	153:b484a57bc302	191
AnnaBridge	153:b484a57bc302	192	#elif defined ( __CSMC__ )
AnnaBridge	153:b484a57bc302	193	#if ( __CSMC__ & 0x400U)
AnnaBridge	153:b484a57bc302	194	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	195	#define __FPU_USED 1U
AnnaBridge	153:b484a57bc302	196	#else
AnnaBridge	153:b484a57bc302	197	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	153:b484a57bc302	198	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	199	#endif
AnnaBridge	153:b484a57bc302	200	#else
AnnaBridge	153:b484a57bc302	201	#define __FPU_USED 0U
AnnaBridge	153:b484a57bc302	202	#endif
AnnaBridge	153:b484a57bc302	203
AnnaBridge	153:b484a57bc302	204	#endif
AnnaBridge	153:b484a57bc302	205
AnnaBridge	153:b484a57bc302	206	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	153:b484a57bc302	207
AnnaBridge	153:b484a57bc302	208
AnnaBridge	153:b484a57bc302	209	#ifdef __cplusplus
AnnaBridge	153:b484a57bc302	210	}
AnnaBridge	153:b484a57bc302	211	#endif
AnnaBridge	153:b484a57bc302	212
AnnaBridge	153:b484a57bc302	213	#endif /* __CORE_ARMV8MML_H_GENERIC */
AnnaBridge	153:b484a57bc302	214
AnnaBridge	153:b484a57bc302	215	#ifndef __CMSIS_GENERIC
AnnaBridge	153:b484a57bc302	216
AnnaBridge	153:b484a57bc302	217	#ifndef __CORE_ARMV8MML_H_DEPENDANT
AnnaBridge	153:b484a57bc302	218	#define __CORE_ARMV8MML_H_DEPENDANT
AnnaBridge	153:b484a57bc302	219
AnnaBridge	153:b484a57bc302	220	#ifdef __cplusplus
AnnaBridge	153:b484a57bc302	221	extern "C" {
AnnaBridge	153:b484a57bc302	222	#endif
AnnaBridge	153:b484a57bc302	223
AnnaBridge	153:b484a57bc302	224	/* check device defines and use defaults */
AnnaBridge	153:b484a57bc302	225	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	153:b484a57bc302	226	#ifndef __ARMv8MML_REV
AnnaBridge	153:b484a57bc302	227	#define __ARMv8MML_REV 0x0000U
AnnaBridge	153:b484a57bc302	228	#warning "__ARMv8MML_REV not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	229	#endif
AnnaBridge	153:b484a57bc302	230
AnnaBridge	153:b484a57bc302	231	#ifndef __FPU_PRESENT
AnnaBridge	153:b484a57bc302	232	#define __FPU_PRESENT 0U
AnnaBridge	153:b484a57bc302	233	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	234	#endif
AnnaBridge	153:b484a57bc302	235
AnnaBridge	153:b484a57bc302	236	#ifndef __MPU_PRESENT
AnnaBridge	153:b484a57bc302	237	#define __MPU_PRESENT 0U
AnnaBridge	153:b484a57bc302	238	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	239	#endif
AnnaBridge	153:b484a57bc302	240
AnnaBridge	153:b484a57bc302	241	#ifndef __SAUREGION_PRESENT
AnnaBridge	153:b484a57bc302	242	#define __SAUREGION_PRESENT 0U
AnnaBridge	153:b484a57bc302	243	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	244	#endif
AnnaBridge	153:b484a57bc302	245
AnnaBridge	153:b484a57bc302	246	#ifndef __DSP_PRESENT
AnnaBridge	153:b484a57bc302	247	#define __DSP_PRESENT 0U
AnnaBridge	153:b484a57bc302	248	#warning "__DSP_PRESENT not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	249	#endif
AnnaBridge	153:b484a57bc302	250
AnnaBridge	153:b484a57bc302	251	#ifndef __NVIC_PRIO_BITS
AnnaBridge	153:b484a57bc302	252	#define __NVIC_PRIO_BITS 3U
AnnaBridge	153:b484a57bc302	253	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	254	#endif
AnnaBridge	153:b484a57bc302	255
AnnaBridge	153:b484a57bc302	256	#ifndef __Vendor_SysTickConfig
AnnaBridge	153:b484a57bc302	257	#define __Vendor_SysTickConfig 0U
AnnaBridge	153:b484a57bc302	258	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	153:b484a57bc302	259	#endif
AnnaBridge	153:b484a57bc302	260	#endif
AnnaBridge	153:b484a57bc302	261
AnnaBridge	153:b484a57bc302	262	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	153:b484a57bc302	263	/**
AnnaBridge	153:b484a57bc302	264	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	153:b484a57bc302	265
AnnaBridge	153:b484a57bc302	266	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	153:b484a57bc302	267	\li to specify the access to peripheral variables.
AnnaBridge	153:b484a57bc302	268	\li for automatic generation of peripheral register debug information.
AnnaBridge	153:b484a57bc302	269	*/
AnnaBridge	153:b484a57bc302	270	#ifdef __cplusplus
AnnaBridge	153:b484a57bc302	271	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	153:b484a57bc302	272	#else
AnnaBridge	153:b484a57bc302	273	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	153:b484a57bc302	274	#endif
AnnaBridge	153:b484a57bc302	275	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	153:b484a57bc302	276	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	153:b484a57bc302	277
AnnaBridge	153:b484a57bc302	278	/* following defines should be used for structure members */
AnnaBridge	153:b484a57bc302	279	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	153:b484a57bc302	280	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	153:b484a57bc302	281	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	153:b484a57bc302	282
AnnaBridge	153:b484a57bc302	283	/@} end of group ARMv8MML /
AnnaBridge	153:b484a57bc302	284
AnnaBridge	153:b484a57bc302	285
AnnaBridge	153:b484a57bc302	286
AnnaBridge	153:b484a57bc302	287	/*******************************************************************************
AnnaBridge	153:b484a57bc302	288	* Register Abstraction
AnnaBridge	153:b484a57bc302	289	Core Register contain:
AnnaBridge	153:b484a57bc302	290	- Core Register
AnnaBridge	153:b484a57bc302	291	- Core NVIC Register
AnnaBridge	153:b484a57bc302	292	- Core SCB Register
AnnaBridge	153:b484a57bc302	293	- Core SysTick Register
AnnaBridge	153:b484a57bc302	294	- Core Debug Register
AnnaBridge	153:b484a57bc302	295	- Core MPU Register
AnnaBridge	153:b484a57bc302	296	- Core SAU Register
AnnaBridge	153:b484a57bc302	297	- Core FPU Register
AnnaBridge	153:b484a57bc302	298	******************************************************************************/
AnnaBridge	153:b484a57bc302	299	/**
AnnaBridge	153:b484a57bc302	300	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	153:b484a57bc302	301	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	153:b484a57bc302	302	*/
AnnaBridge	153:b484a57bc302	303
AnnaBridge	153:b484a57bc302	304	/**
AnnaBridge	153:b484a57bc302	305	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	306	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	153:b484a57bc302	307	\brief Core Register type definitions.
AnnaBridge	153:b484a57bc302	308	@{
AnnaBridge	153:b484a57bc302	309	*/
AnnaBridge	153:b484a57bc302	310
AnnaBridge	153:b484a57bc302	311	/**
AnnaBridge	153:b484a57bc302	312	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	153:b484a57bc302	313	*/
AnnaBridge	153:b484a57bc302	314	typedef union
AnnaBridge	153:b484a57bc302	315	{
AnnaBridge	153:b484a57bc302	316	struct
AnnaBridge	153:b484a57bc302	317	{
AnnaBridge	153:b484a57bc302	318	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
AnnaBridge	153:b484a57bc302	319	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	153:b484a57bc302	320	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
AnnaBridge	153:b484a57bc302	321	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	153:b484a57bc302	322	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	153:b484a57bc302	323	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	153:b484a57bc302	324	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	153:b484a57bc302	325	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	153:b484a57bc302	326	} b; /!< Structure used for bit access /
AnnaBridge	153:b484a57bc302	327	uint32_t w; /!< Type used for word access /
AnnaBridge	153:b484a57bc302	328	} APSR_Type;
AnnaBridge	153:b484a57bc302	329
AnnaBridge	153:b484a57bc302	330	/* APSR Register Definitions */
AnnaBridge	153:b484a57bc302	331	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	153:b484a57bc302	332	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	153:b484a57bc302	333
AnnaBridge	153:b484a57bc302	334	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	153:b484a57bc302	335	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	153:b484a57bc302	336
AnnaBridge	153:b484a57bc302	337	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	153:b484a57bc302	338	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	153:b484a57bc302	339
AnnaBridge	153:b484a57bc302	340	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	153:b484a57bc302	341	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	153:b484a57bc302	342
AnnaBridge	153:b484a57bc302	343	#define APSR_Q_Pos 27U /!< APSR: Q Position /
AnnaBridge	153:b484a57bc302	344	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
AnnaBridge	153:b484a57bc302	345
AnnaBridge	153:b484a57bc302	346	#define APSR_GE_Pos 16U /!< APSR: GE Position /
AnnaBridge	153:b484a57bc302	347	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
AnnaBridge	153:b484a57bc302	348
AnnaBridge	153:b484a57bc302	349
AnnaBridge	153:b484a57bc302	350	/**
AnnaBridge	153:b484a57bc302	351	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	153:b484a57bc302	352	*/
AnnaBridge	153:b484a57bc302	353	typedef union
AnnaBridge	153:b484a57bc302	354	{
AnnaBridge	153:b484a57bc302	355	struct
AnnaBridge	153:b484a57bc302	356	{
AnnaBridge	153:b484a57bc302	357	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	153:b484a57bc302	358	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	153:b484a57bc302	359	} b; /!< Structure used for bit access /
AnnaBridge	153:b484a57bc302	360	uint32_t w; /!< Type used for word access /
AnnaBridge	153:b484a57bc302	361	} IPSR_Type;
AnnaBridge	153:b484a57bc302	362
AnnaBridge	153:b484a57bc302	363	/* IPSR Register Definitions */
AnnaBridge	153:b484a57bc302	364	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	153:b484a57bc302	365	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	153:b484a57bc302	366
AnnaBridge	153:b484a57bc302	367
AnnaBridge	153:b484a57bc302	368	/**
AnnaBridge	153:b484a57bc302	369	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	153:b484a57bc302	370	*/
AnnaBridge	153:b484a57bc302	371	typedef union
AnnaBridge	153:b484a57bc302	372	{
AnnaBridge	153:b484a57bc302	373	struct
AnnaBridge	153:b484a57bc302	374	{
AnnaBridge	153:b484a57bc302	375	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	153:b484a57bc302	376	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
AnnaBridge	153:b484a57bc302	377	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	153:b484a57bc302	378	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
AnnaBridge	153:b484a57bc302	379	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
AnnaBridge	153:b484a57bc302	380	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
AnnaBridge	153:b484a57bc302	381	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	153:b484a57bc302	382	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	153:b484a57bc302	383	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	153:b484a57bc302	384	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	153:b484a57bc302	385	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	153:b484a57bc302	386	} b; /!< Structure used for bit access /
AnnaBridge	153:b484a57bc302	387	uint32_t w; /!< Type used for word access /
AnnaBridge	153:b484a57bc302	388	} xPSR_Type;
AnnaBridge	153:b484a57bc302	389
AnnaBridge	153:b484a57bc302	390	/* xPSR Register Definitions */
AnnaBridge	153:b484a57bc302	391	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	153:b484a57bc302	392	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	153:b484a57bc302	393
AnnaBridge	153:b484a57bc302	394	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	153:b484a57bc302	395	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	153:b484a57bc302	396
AnnaBridge	153:b484a57bc302	397	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	153:b484a57bc302	398	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	153:b484a57bc302	399
AnnaBridge	153:b484a57bc302	400	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	153:b484a57bc302	401	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	153:b484a57bc302	402
AnnaBridge	153:b484a57bc302	403	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
AnnaBridge	153:b484a57bc302	404	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
AnnaBridge	153:b484a57bc302	405
AnnaBridge	153:b484a57bc302	406	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
AnnaBridge	153:b484a57bc302	407	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
AnnaBridge	153:b484a57bc302	408
AnnaBridge	153:b484a57bc302	409	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	153:b484a57bc302	410	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	153:b484a57bc302	411
AnnaBridge	153:b484a57bc302	412	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
AnnaBridge	153:b484a57bc302	413	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
AnnaBridge	153:b484a57bc302	414
AnnaBridge	153:b484a57bc302	415	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	153:b484a57bc302	416	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	153:b484a57bc302	417
AnnaBridge	153:b484a57bc302	418
AnnaBridge	153:b484a57bc302	419	/**
AnnaBridge	153:b484a57bc302	420	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	153:b484a57bc302	421	*/
AnnaBridge	153:b484a57bc302	422	typedef union
AnnaBridge	153:b484a57bc302	423	{
AnnaBridge	153:b484a57bc302	424	struct
AnnaBridge	153:b484a57bc302	425	{
AnnaBridge	153:b484a57bc302	426	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	153:b484a57bc302	427	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
AnnaBridge	153:b484a57bc302	428	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
AnnaBridge	153:b484a57bc302	429	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
AnnaBridge	153:b484a57bc302	430	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
AnnaBridge	153:b484a57bc302	431	} b; /!< Structure used for bit access /
AnnaBridge	153:b484a57bc302	432	uint32_t w; /!< Type used for word access /
AnnaBridge	153:b484a57bc302	433	} CONTROL_Type;
AnnaBridge	153:b484a57bc302	434
AnnaBridge	153:b484a57bc302	435	/* CONTROL Register Definitions */
AnnaBridge	153:b484a57bc302	436	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
AnnaBridge	153:b484a57bc302	437	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
AnnaBridge	153:b484a57bc302	438
AnnaBridge	153:b484a57bc302	439	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
AnnaBridge	153:b484a57bc302	440	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
AnnaBridge	153:b484a57bc302	441
AnnaBridge	153:b484a57bc302	442	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	153:b484a57bc302	443	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	153:b484a57bc302	444
AnnaBridge	153:b484a57bc302	445	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	153:b484a57bc302	446	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	153:b484a57bc302	447
AnnaBridge	153:b484a57bc302	448	/@} end of group CMSIS_CORE /
AnnaBridge	153:b484a57bc302	449
AnnaBridge	153:b484a57bc302	450
AnnaBridge	153:b484a57bc302	451	/**
AnnaBridge	153:b484a57bc302	452	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	453	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	153:b484a57bc302	454	\brief Type definitions for the NVIC Registers
AnnaBridge	153:b484a57bc302	455	@{
AnnaBridge	153:b484a57bc302	456	*/
AnnaBridge	153:b484a57bc302	457
AnnaBridge	153:b484a57bc302	458	/**
AnnaBridge	153:b484a57bc302	459	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	153:b484a57bc302	460	*/
AnnaBridge	153:b484a57bc302	461	typedef struct
AnnaBridge	153:b484a57bc302	462	{
AnnaBridge	153:b484a57bc302	463	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	153:b484a57bc302	464	uint32_t RESERVED0[16U];
AnnaBridge	153:b484a57bc302	465	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	153:b484a57bc302	466	uint32_t RSERVED1[16U];
AnnaBridge	153:b484a57bc302	467	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	153:b484a57bc302	468	uint32_t RESERVED2[16U];
AnnaBridge	153:b484a57bc302	469	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	153:b484a57bc302	470	uint32_t RESERVED3[16U];
AnnaBridge	153:b484a57bc302	471	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	153:b484a57bc302	472	uint32_t RESERVED4[16U];
AnnaBridge	153:b484a57bc302	473	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
AnnaBridge	153:b484a57bc302	474	uint32_t RESERVED5[16U];
AnnaBridge	153:b484a57bc302	475	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	153:b484a57bc302	476	uint32_t RESERVED6[580U];
AnnaBridge	153:b484a57bc302	477	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
AnnaBridge	153:b484a57bc302	478	} NVIC_Type;
AnnaBridge	153:b484a57bc302	479
AnnaBridge	153:b484a57bc302	480	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	153:b484a57bc302	481	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
AnnaBridge	153:b484a57bc302	482	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
AnnaBridge	153:b484a57bc302	483
AnnaBridge	153:b484a57bc302	484	/@} end of group CMSIS_NVIC /
AnnaBridge	153:b484a57bc302	485
AnnaBridge	153:b484a57bc302	486
AnnaBridge	153:b484a57bc302	487	/**
AnnaBridge	153:b484a57bc302	488	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	489	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	153:b484a57bc302	490	\brief Type definitions for the System Control Block Registers
AnnaBridge	153:b484a57bc302	491	@{
AnnaBridge	153:b484a57bc302	492	*/
AnnaBridge	153:b484a57bc302	493
AnnaBridge	153:b484a57bc302	494	/**
AnnaBridge	153:b484a57bc302	495	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	153:b484a57bc302	496	*/
AnnaBridge	153:b484a57bc302	497	typedef struct
AnnaBridge	153:b484a57bc302	498	{
AnnaBridge	153:b484a57bc302	499	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	153:b484a57bc302	500	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	153:b484a57bc302	501	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	153:b484a57bc302	502	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	153:b484a57bc302	503	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	153:b484a57bc302	504	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	153:b484a57bc302	505	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	153:b484a57bc302	506	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	153:b484a57bc302	507	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	153:b484a57bc302	508	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	153:b484a57bc302	509	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	153:b484a57bc302	510	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	153:b484a57bc302	511	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	153:b484a57bc302	512	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	153:b484a57bc302	513	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	153:b484a57bc302	514	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	153:b484a57bc302	515	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	153:b484a57bc302	516	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	153:b484a57bc302	517	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	153:b484a57bc302	518	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
AnnaBridge	153:b484a57bc302	519	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
AnnaBridge	153:b484a57bc302	520	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
AnnaBridge	153:b484a57bc302	521	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
AnnaBridge	153:b484a57bc302	522	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	153:b484a57bc302	523	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
AnnaBridge	153:b484a57bc302	524	uint32_t RESERVED3[92U];
AnnaBridge	153:b484a57bc302	525	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
AnnaBridge	153:b484a57bc302	526	uint32_t RESERVED4[15U];
AnnaBridge	153:b484a57bc302	527	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
AnnaBridge	153:b484a57bc302	528	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
Anna Bridge	160:5571c4ff569f	529	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
AnnaBridge	153:b484a57bc302	530	uint32_t RESERVED5[1U];
AnnaBridge	153:b484a57bc302	531	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
AnnaBridge	153:b484a57bc302	532	uint32_t RESERVED6[1U];
AnnaBridge	153:b484a57bc302	533	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
AnnaBridge	153:b484a57bc302	534	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
AnnaBridge	153:b484a57bc302	535	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
AnnaBridge	153:b484a57bc302	536	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
AnnaBridge	153:b484a57bc302	537	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
AnnaBridge	153:b484a57bc302	538	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
AnnaBridge	153:b484a57bc302	539	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
AnnaBridge	153:b484a57bc302	540	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
AnnaBridge	153:b484a57bc302	541	uint32_t RESERVED7[6U];
AnnaBridge	153:b484a57bc302	542	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
AnnaBridge	153:b484a57bc302	543	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
AnnaBridge	153:b484a57bc302	544	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
AnnaBridge	153:b484a57bc302	545	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
AnnaBridge	153:b484a57bc302	546	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
AnnaBridge	153:b484a57bc302	547	uint32_t RESERVED8[1U];
AnnaBridge	153:b484a57bc302	548	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
AnnaBridge	153:b484a57bc302	549	} SCB_Type;
AnnaBridge	153:b484a57bc302	550
AnnaBridge	153:b484a57bc302	551	/* SCB CPUID Register Definitions */
AnnaBridge	153:b484a57bc302	552	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	153:b484a57bc302	553	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	153:b484a57bc302	554
AnnaBridge	153:b484a57bc302	555	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	153:b484a57bc302	556	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	153:b484a57bc302	557
AnnaBridge	153:b484a57bc302	558	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	153:b484a57bc302	559	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	153:b484a57bc302	560
AnnaBridge	153:b484a57bc302	561	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	153:b484a57bc302	562	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	153:b484a57bc302	563
AnnaBridge	153:b484a57bc302	564	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	153:b484a57bc302	565	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	153:b484a57bc302	566
AnnaBridge	153:b484a57bc302	567	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	153:b484a57bc302	568	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
AnnaBridge	153:b484a57bc302	569	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
AnnaBridge	153:b484a57bc302	570
AnnaBridge	153:b484a57bc302	571	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
AnnaBridge	153:b484a57bc302	572	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
AnnaBridge	153:b484a57bc302	573
AnnaBridge	153:b484a57bc302	574	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	153:b484a57bc302	575	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	153:b484a57bc302	576
AnnaBridge	153:b484a57bc302	577	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	153:b484a57bc302	578	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	153:b484a57bc302	579
AnnaBridge	153:b484a57bc302	580	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	153:b484a57bc302	581	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	153:b484a57bc302	582
AnnaBridge	153:b484a57bc302	583	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	153:b484a57bc302	584	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	153:b484a57bc302	585
AnnaBridge	153:b484a57bc302	586	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
AnnaBridge	153:b484a57bc302	587	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
AnnaBridge	153:b484a57bc302	588
AnnaBridge	153:b484a57bc302	589	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	153:b484a57bc302	590	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	153:b484a57bc302	591
AnnaBridge	153:b484a57bc302	592	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	153:b484a57bc302	593	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	153:b484a57bc302	594
AnnaBridge	153:b484a57bc302	595	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	153:b484a57bc302	596	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	153:b484a57bc302	597
AnnaBridge	153:b484a57bc302	598	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	153:b484a57bc302	599	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	153:b484a57bc302	600
AnnaBridge	153:b484a57bc302	601	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	153:b484a57bc302	602	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	153:b484a57bc302	603
AnnaBridge	153:b484a57bc302	604	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	153:b484a57bc302	605	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	153:b484a57bc302	606	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	153:b484a57bc302	607
AnnaBridge	153:b484a57bc302	608	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	153:b484a57bc302	609	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	153:b484a57bc302	610	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	153:b484a57bc302	611
AnnaBridge	153:b484a57bc302	612	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	153:b484a57bc302	613	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	153:b484a57bc302	614
AnnaBridge	153:b484a57bc302	615	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	153:b484a57bc302	616	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	153:b484a57bc302	617
AnnaBridge	153:b484a57bc302	618	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
AnnaBridge	153:b484a57bc302	619	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
AnnaBridge	153:b484a57bc302	620
AnnaBridge	153:b484a57bc302	621	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
AnnaBridge	153:b484a57bc302	622	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
AnnaBridge	153:b484a57bc302	623
AnnaBridge	153:b484a57bc302	624	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
AnnaBridge	153:b484a57bc302	625	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
AnnaBridge	153:b484a57bc302	626
AnnaBridge	153:b484a57bc302	627	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
AnnaBridge	153:b484a57bc302	628	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
AnnaBridge	153:b484a57bc302	629
AnnaBridge	153:b484a57bc302	630	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	153:b484a57bc302	631	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	153:b484a57bc302	632
AnnaBridge	153:b484a57bc302	633	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	153:b484a57bc302	634	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	153:b484a57bc302	635
AnnaBridge	153:b484a57bc302	636	/* SCB System Control Register Definitions */
AnnaBridge	153:b484a57bc302	637	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	153:b484a57bc302	638	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	153:b484a57bc302	639
AnnaBridge	153:b484a57bc302	640	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
AnnaBridge	153:b484a57bc302	641	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
AnnaBridge	153:b484a57bc302	642
AnnaBridge	153:b484a57bc302	643	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	153:b484a57bc302	644	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	153:b484a57bc302	645
AnnaBridge	153:b484a57bc302	646	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	153:b484a57bc302	647	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	153:b484a57bc302	648
AnnaBridge	153:b484a57bc302	649	/* SCB Configuration Control Register Definitions */
AnnaBridge	153:b484a57bc302	650	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
AnnaBridge	153:b484a57bc302	651	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
AnnaBridge	153:b484a57bc302	652
AnnaBridge	153:b484a57bc302	653	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
AnnaBridge	153:b484a57bc302	654	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
AnnaBridge	153:b484a57bc302	655
AnnaBridge	153:b484a57bc302	656	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
AnnaBridge	153:b484a57bc302	657	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
AnnaBridge	153:b484a57bc302	658
AnnaBridge	153:b484a57bc302	659	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
AnnaBridge	153:b484a57bc302	660	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
AnnaBridge	153:b484a57bc302	661
AnnaBridge	153:b484a57bc302	662	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	153:b484a57bc302	663	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	153:b484a57bc302	664
AnnaBridge	153:b484a57bc302	665	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	153:b484a57bc302	666	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	153:b484a57bc302	667
AnnaBridge	153:b484a57bc302	668	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	153:b484a57bc302	669	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	153:b484a57bc302	670
AnnaBridge	153:b484a57bc302	671	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	153:b484a57bc302	672	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	153:b484a57bc302	673
AnnaBridge	153:b484a57bc302	674	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	153:b484a57bc302	675	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
AnnaBridge	153:b484a57bc302	676	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
AnnaBridge	153:b484a57bc302	677
AnnaBridge	153:b484a57bc302	678	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
AnnaBridge	153:b484a57bc302	679	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
AnnaBridge	153:b484a57bc302	680
AnnaBridge	153:b484a57bc302	681	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
AnnaBridge	153:b484a57bc302	682	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
AnnaBridge	153:b484a57bc302	683
AnnaBridge	153:b484a57bc302	684	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
AnnaBridge	153:b484a57bc302	685	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
AnnaBridge	153:b484a57bc302	686
AnnaBridge	153:b484a57bc302	687	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
AnnaBridge	153:b484a57bc302	688	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
AnnaBridge	153:b484a57bc302	689
AnnaBridge	153:b484a57bc302	690	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
AnnaBridge	153:b484a57bc302	691	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
AnnaBridge	153:b484a57bc302	692
AnnaBridge	153:b484a57bc302	693	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	153:b484a57bc302	694	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	153:b484a57bc302	695
AnnaBridge	153:b484a57bc302	696	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
AnnaBridge	153:b484a57bc302	697	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
AnnaBridge	153:b484a57bc302	698
AnnaBridge	153:b484a57bc302	699	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
AnnaBridge	153:b484a57bc302	700	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
AnnaBridge	153:b484a57bc302	701
AnnaBridge	153:b484a57bc302	702	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
AnnaBridge	153:b484a57bc302	703	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
AnnaBridge	153:b484a57bc302	704
AnnaBridge	153:b484a57bc302	705	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	153:b484a57bc302	706	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	153:b484a57bc302	707
AnnaBridge	153:b484a57bc302	708	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	153:b484a57bc302	709	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	153:b484a57bc302	710
AnnaBridge	153:b484a57bc302	711	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
AnnaBridge	153:b484a57bc302	712	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
AnnaBridge	153:b484a57bc302	713
AnnaBridge	153:b484a57bc302	714	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	153:b484a57bc302	715	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	153:b484a57bc302	716
AnnaBridge	153:b484a57bc302	717	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
AnnaBridge	153:b484a57bc302	718	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
AnnaBridge	153:b484a57bc302	719
AnnaBridge	153:b484a57bc302	720	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
AnnaBridge	153:b484a57bc302	721	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
AnnaBridge	153:b484a57bc302	722
AnnaBridge	153:b484a57bc302	723	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
AnnaBridge	153:b484a57bc302	724	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
AnnaBridge	153:b484a57bc302	725
AnnaBridge	153:b484a57bc302	726	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
AnnaBridge	153:b484a57bc302	727	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
AnnaBridge	153:b484a57bc302	728
AnnaBridge	153:b484a57bc302	729	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
AnnaBridge	153:b484a57bc302	730	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
AnnaBridge	153:b484a57bc302	731
AnnaBridge	153:b484a57bc302	732	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
AnnaBridge	153:b484a57bc302	733	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
AnnaBridge	153:b484a57bc302	734
AnnaBridge	153:b484a57bc302	735	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	153:b484a57bc302	736	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
AnnaBridge	153:b484a57bc302	737	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
AnnaBridge	153:b484a57bc302	738
AnnaBridge	153:b484a57bc302	739	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
AnnaBridge	153:b484a57bc302	740	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
AnnaBridge	153:b484a57bc302	741
AnnaBridge	153:b484a57bc302	742	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
AnnaBridge	153:b484a57bc302	743	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
AnnaBridge	153:b484a57bc302	744
AnnaBridge	153:b484a57bc302	745	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	153:b484a57bc302	746	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	153:b484a57bc302	747	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	153:b484a57bc302	748
AnnaBridge	153:b484a57bc302	749	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
AnnaBridge	153:b484a57bc302	750	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
AnnaBridge	153:b484a57bc302	751
AnnaBridge	153:b484a57bc302	752	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	153:b484a57bc302	753	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	153:b484a57bc302	754
AnnaBridge	153:b484a57bc302	755	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	153:b484a57bc302	756	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	153:b484a57bc302	757
AnnaBridge	153:b484a57bc302	758	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	153:b484a57bc302	759	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	153:b484a57bc302	760
AnnaBridge	153:b484a57bc302	761	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	153:b484a57bc302	762	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	153:b484a57bc302	763
AnnaBridge	153:b484a57bc302	764	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	153:b484a57bc302	765	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	153:b484a57bc302	766	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	153:b484a57bc302	767
AnnaBridge	153:b484a57bc302	768	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
AnnaBridge	153:b484a57bc302	769	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
AnnaBridge	153:b484a57bc302	770
AnnaBridge	153:b484a57bc302	771	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	153:b484a57bc302	772	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	153:b484a57bc302	773
AnnaBridge	153:b484a57bc302	774	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	153:b484a57bc302	775	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	153:b484a57bc302	776
AnnaBridge	153:b484a57bc302	777	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	153:b484a57bc302	778	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	153:b484a57bc302	779
AnnaBridge	153:b484a57bc302	780	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	153:b484a57bc302	781	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	153:b484a57bc302	782
AnnaBridge	153:b484a57bc302	783	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	153:b484a57bc302	784	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	153:b484a57bc302	785
AnnaBridge	153:b484a57bc302	786	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	153:b484a57bc302	787	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	153:b484a57bc302	788	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	153:b484a57bc302	789
AnnaBridge	153:b484a57bc302	790	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	153:b484a57bc302	791	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	153:b484a57bc302	792
AnnaBridge	153:b484a57bc302	793	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
AnnaBridge	153:b484a57bc302	794	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
AnnaBridge	153:b484a57bc302	795
AnnaBridge	153:b484a57bc302	796	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	153:b484a57bc302	797	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	153:b484a57bc302	798
AnnaBridge	153:b484a57bc302	799	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	153:b484a57bc302	800	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	153:b484a57bc302	801
AnnaBridge	153:b484a57bc302	802	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	153:b484a57bc302	803	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	153:b484a57bc302	804
AnnaBridge	153:b484a57bc302	805	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	153:b484a57bc302	806	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	153:b484a57bc302	807
AnnaBridge	153:b484a57bc302	808	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	153:b484a57bc302	809	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
AnnaBridge	153:b484a57bc302	810	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
AnnaBridge	153:b484a57bc302	811
AnnaBridge	153:b484a57bc302	812	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
AnnaBridge	153:b484a57bc302	813	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
AnnaBridge	153:b484a57bc302	814
AnnaBridge	153:b484a57bc302	815	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
AnnaBridge	153:b484a57bc302	816	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
AnnaBridge	153:b484a57bc302	817
AnnaBridge	153:b484a57bc302	818	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	153:b484a57bc302	819	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
AnnaBridge	153:b484a57bc302	820	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
AnnaBridge	153:b484a57bc302	821
AnnaBridge	153:b484a57bc302	822	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
AnnaBridge	153:b484a57bc302	823	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
AnnaBridge	153:b484a57bc302	824
AnnaBridge	153:b484a57bc302	825	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
AnnaBridge	153:b484a57bc302	826	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
AnnaBridge	153:b484a57bc302	827
AnnaBridge	153:b484a57bc302	828	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
AnnaBridge	153:b484a57bc302	829	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
AnnaBridge	153:b484a57bc302	830
AnnaBridge	153:b484a57bc302	831	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
AnnaBridge	153:b484a57bc302	832	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
AnnaBridge	153:b484a57bc302	833
AnnaBridge	153:b484a57bc302	834	/* SCB Non-Secure Access Control Register Definitions */
AnnaBridge	153:b484a57bc302	835	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
AnnaBridge	153:b484a57bc302	836	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
AnnaBridge	153:b484a57bc302	837
AnnaBridge	153:b484a57bc302	838	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
AnnaBridge	153:b484a57bc302	839	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
AnnaBridge	153:b484a57bc302	840
AnnaBridge	153:b484a57bc302	841	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
AnnaBridge	153:b484a57bc302	842	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
AnnaBridge	153:b484a57bc302	843
AnnaBridge	153:b484a57bc302	844	/* SCB Cache Level ID Register Definitions */
AnnaBridge	153:b484a57bc302	845	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
AnnaBridge	153:b484a57bc302	846	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
AnnaBridge	153:b484a57bc302	847
AnnaBridge	153:b484a57bc302	848	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
AnnaBridge	153:b484a57bc302	849	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
AnnaBridge	153:b484a57bc302	850
AnnaBridge	153:b484a57bc302	851	/* SCB Cache Type Register Definitions */
AnnaBridge	153:b484a57bc302	852	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
AnnaBridge	153:b484a57bc302	853	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
AnnaBridge	153:b484a57bc302	854
AnnaBridge	153:b484a57bc302	855	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
AnnaBridge	153:b484a57bc302	856	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
AnnaBridge	153:b484a57bc302	857
AnnaBridge	153:b484a57bc302	858	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
AnnaBridge	153:b484a57bc302	859	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
AnnaBridge	153:b484a57bc302	860
AnnaBridge	153:b484a57bc302	861	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
AnnaBridge	153:b484a57bc302	862	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
AnnaBridge	153:b484a57bc302	863
AnnaBridge	153:b484a57bc302	864	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
AnnaBridge	153:b484a57bc302	865	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
AnnaBridge	153:b484a57bc302	866
AnnaBridge	153:b484a57bc302	867	/* SCB Cache Size ID Register Definitions */
AnnaBridge	153:b484a57bc302	868	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
AnnaBridge	153:b484a57bc302	869	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
AnnaBridge	153:b484a57bc302	870
AnnaBridge	153:b484a57bc302	871	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
AnnaBridge	153:b484a57bc302	872	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
AnnaBridge	153:b484a57bc302	873
AnnaBridge	153:b484a57bc302	874	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
AnnaBridge	153:b484a57bc302	875	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
AnnaBridge	153:b484a57bc302	876
AnnaBridge	153:b484a57bc302	877	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
AnnaBridge	153:b484a57bc302	878	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
AnnaBridge	153:b484a57bc302	879
AnnaBridge	153:b484a57bc302	880	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
AnnaBridge	153:b484a57bc302	881	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
AnnaBridge	153:b484a57bc302	882
AnnaBridge	153:b484a57bc302	883	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
AnnaBridge	153:b484a57bc302	884	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
AnnaBridge	153:b484a57bc302	885
AnnaBridge	153:b484a57bc302	886	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
AnnaBridge	153:b484a57bc302	887	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
AnnaBridge	153:b484a57bc302	888
AnnaBridge	153:b484a57bc302	889	/* SCB Cache Size Selection Register Definitions */
AnnaBridge	153:b484a57bc302	890	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
AnnaBridge	153:b484a57bc302	891	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
AnnaBridge	153:b484a57bc302	892
AnnaBridge	153:b484a57bc302	893	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
AnnaBridge	153:b484a57bc302	894	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
AnnaBridge	153:b484a57bc302	895
AnnaBridge	153:b484a57bc302	896	/* SCB Software Triggered Interrupt Register Definitions */
AnnaBridge	153:b484a57bc302	897	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
AnnaBridge	153:b484a57bc302	898	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
AnnaBridge	153:b484a57bc302	899
AnnaBridge	153:b484a57bc302	900	/* SCB D-Cache Invalidate by Set-way Register Definitions */
AnnaBridge	153:b484a57bc302	901	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
AnnaBridge	153:b484a57bc302	902	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
AnnaBridge	153:b484a57bc302	903
AnnaBridge	153:b484a57bc302	904	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
AnnaBridge	153:b484a57bc302	905	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
AnnaBridge	153:b484a57bc302	906
AnnaBridge	153:b484a57bc302	907	/* SCB D-Cache Clean by Set-way Register Definitions */
AnnaBridge	153:b484a57bc302	908	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
AnnaBridge	153:b484a57bc302	909	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
AnnaBridge	153:b484a57bc302	910
AnnaBridge	153:b484a57bc302	911	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
AnnaBridge	153:b484a57bc302	912	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
AnnaBridge	153:b484a57bc302	913
AnnaBridge	153:b484a57bc302	914	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
AnnaBridge	153:b484a57bc302	915	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
AnnaBridge	153:b484a57bc302	916	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
AnnaBridge	153:b484a57bc302	917
AnnaBridge	153:b484a57bc302	918	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
AnnaBridge	153:b484a57bc302	919	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
AnnaBridge	153:b484a57bc302	920
AnnaBridge	153:b484a57bc302	921	/* Instruction Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	153:b484a57bc302	922	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
AnnaBridge	153:b484a57bc302	923	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
AnnaBridge	153:b484a57bc302	924
AnnaBridge	153:b484a57bc302	925	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
AnnaBridge	153:b484a57bc302	926	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
AnnaBridge	153:b484a57bc302	927
AnnaBridge	153:b484a57bc302	928	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
AnnaBridge	153:b484a57bc302	929	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
AnnaBridge	153:b484a57bc302	930
AnnaBridge	153:b484a57bc302	931	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
AnnaBridge	153:b484a57bc302	932	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
AnnaBridge	153:b484a57bc302	933
AnnaBridge	153:b484a57bc302	934	/* Data Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	153:b484a57bc302	935	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
AnnaBridge	153:b484a57bc302	936	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
AnnaBridge	153:b484a57bc302	937
AnnaBridge	153:b484a57bc302	938	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
AnnaBridge	153:b484a57bc302	939	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
AnnaBridge	153:b484a57bc302	940
AnnaBridge	153:b484a57bc302	941	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
AnnaBridge	153:b484a57bc302	942	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
AnnaBridge	153:b484a57bc302	943
AnnaBridge	153:b484a57bc302	944	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
AnnaBridge	153:b484a57bc302	945	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
AnnaBridge	153:b484a57bc302	946
AnnaBridge	153:b484a57bc302	947	/* AHBP Control Register Definitions */
AnnaBridge	153:b484a57bc302	948	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
AnnaBridge	153:b484a57bc302	949	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
AnnaBridge	153:b484a57bc302	950
AnnaBridge	153:b484a57bc302	951	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
AnnaBridge	153:b484a57bc302	952	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
AnnaBridge	153:b484a57bc302	953
AnnaBridge	153:b484a57bc302	954	/* L1 Cache Control Register Definitions */
AnnaBridge	153:b484a57bc302	955	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
AnnaBridge	153:b484a57bc302	956	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
AnnaBridge	153:b484a57bc302	957
AnnaBridge	153:b484a57bc302	958	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
AnnaBridge	153:b484a57bc302	959	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
AnnaBridge	153:b484a57bc302	960
AnnaBridge	153:b484a57bc302	961	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
AnnaBridge	153:b484a57bc302	962	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
AnnaBridge	153:b484a57bc302	963
AnnaBridge	153:b484a57bc302	964	/* AHBS Control Register Definitions */
AnnaBridge	153:b484a57bc302	965	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
AnnaBridge	153:b484a57bc302	966	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
AnnaBridge	153:b484a57bc302	967
AnnaBridge	153:b484a57bc302	968	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
AnnaBridge	153:b484a57bc302	969	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
AnnaBridge	153:b484a57bc302	970
AnnaBridge	153:b484a57bc302	971	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
AnnaBridge	153:b484a57bc302	972	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
AnnaBridge	153:b484a57bc302	973
AnnaBridge	153:b484a57bc302	974	/* Auxiliary Bus Fault Status Register Definitions */
AnnaBridge	153:b484a57bc302	975	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
AnnaBridge	153:b484a57bc302	976	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
AnnaBridge	153:b484a57bc302	977
AnnaBridge	153:b484a57bc302	978	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
AnnaBridge	153:b484a57bc302	979	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
AnnaBridge	153:b484a57bc302	980
AnnaBridge	153:b484a57bc302	981	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
AnnaBridge	153:b484a57bc302	982	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
AnnaBridge	153:b484a57bc302	983
AnnaBridge	153:b484a57bc302	984	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
AnnaBridge	153:b484a57bc302	985	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
AnnaBridge	153:b484a57bc302	986
AnnaBridge	153:b484a57bc302	987	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
AnnaBridge	153:b484a57bc302	988	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
AnnaBridge	153:b484a57bc302	989
AnnaBridge	153:b484a57bc302	990	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
AnnaBridge	153:b484a57bc302	991	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
AnnaBridge	153:b484a57bc302	992
AnnaBridge	153:b484a57bc302	993	/@} end of group CMSIS_SCB /
AnnaBridge	153:b484a57bc302	994
AnnaBridge	153:b484a57bc302	995
AnnaBridge	153:b484a57bc302	996	/**
AnnaBridge	153:b484a57bc302	997	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	998	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	153:b484a57bc302	999	\brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge	153:b484a57bc302	1000	@{
AnnaBridge	153:b484a57bc302	1001	*/
AnnaBridge	153:b484a57bc302	1002
AnnaBridge	153:b484a57bc302	1003	/**
AnnaBridge	153:b484a57bc302	1004	\brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge	153:b484a57bc302	1005	*/
AnnaBridge	153:b484a57bc302	1006	typedef struct
AnnaBridge	153:b484a57bc302	1007	{
AnnaBridge	153:b484a57bc302	1008	uint32_t RESERVED0[1U];
AnnaBridge	153:b484a57bc302	1009	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	153:b484a57bc302	1010	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
AnnaBridge	153:b484a57bc302	1011	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
AnnaBridge	153:b484a57bc302	1012	} SCnSCB_Type;
AnnaBridge	153:b484a57bc302	1013
AnnaBridge	153:b484a57bc302	1014	/* Interrupt Controller Type Register Definitions */
AnnaBridge	153:b484a57bc302	1015	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
AnnaBridge	153:b484a57bc302	1016	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
AnnaBridge	153:b484a57bc302	1017
AnnaBridge	153:b484a57bc302	1018	/@} end of group CMSIS_SCnotSCB /
AnnaBridge	153:b484a57bc302	1019
AnnaBridge	153:b484a57bc302	1020
AnnaBridge	153:b484a57bc302	1021	/**
AnnaBridge	153:b484a57bc302	1022	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1023	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	153:b484a57bc302	1024	\brief Type definitions for the System Timer Registers.
AnnaBridge	153:b484a57bc302	1025	@{
AnnaBridge	153:b484a57bc302	1026	*/
AnnaBridge	153:b484a57bc302	1027
AnnaBridge	153:b484a57bc302	1028	/**
AnnaBridge	153:b484a57bc302	1029	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	153:b484a57bc302	1030	*/
AnnaBridge	153:b484a57bc302	1031	typedef struct
AnnaBridge	153:b484a57bc302	1032	{
AnnaBridge	153:b484a57bc302	1033	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	153:b484a57bc302	1034	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	153:b484a57bc302	1035	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	153:b484a57bc302	1036	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	153:b484a57bc302	1037	} SysTick_Type;
AnnaBridge	153:b484a57bc302	1038
AnnaBridge	153:b484a57bc302	1039	/* SysTick Control / Status Register Definitions */
AnnaBridge	153:b484a57bc302	1040	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	153:b484a57bc302	1041	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	153:b484a57bc302	1042
AnnaBridge	153:b484a57bc302	1043	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	153:b484a57bc302	1044	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	153:b484a57bc302	1045
AnnaBridge	153:b484a57bc302	1046	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	153:b484a57bc302	1047	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	153:b484a57bc302	1048
AnnaBridge	153:b484a57bc302	1049	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	153:b484a57bc302	1050	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	153:b484a57bc302	1051
AnnaBridge	153:b484a57bc302	1052	/* SysTick Reload Register Definitions */
AnnaBridge	153:b484a57bc302	1053	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	153:b484a57bc302	1054	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	153:b484a57bc302	1055
AnnaBridge	153:b484a57bc302	1056	/* SysTick Current Register Definitions */
AnnaBridge	153:b484a57bc302	1057	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	153:b484a57bc302	1058	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	153:b484a57bc302	1059
AnnaBridge	153:b484a57bc302	1060	/* SysTick Calibration Register Definitions */
AnnaBridge	153:b484a57bc302	1061	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	153:b484a57bc302	1062	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	153:b484a57bc302	1063
AnnaBridge	153:b484a57bc302	1064	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	153:b484a57bc302	1065	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	153:b484a57bc302	1066
AnnaBridge	153:b484a57bc302	1067	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	153:b484a57bc302	1068	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	153:b484a57bc302	1069
AnnaBridge	153:b484a57bc302	1070	/@} end of group CMSIS_SysTick /
AnnaBridge	153:b484a57bc302	1071
AnnaBridge	153:b484a57bc302	1072
AnnaBridge	153:b484a57bc302	1073	/**
AnnaBridge	153:b484a57bc302	1074	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1075	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	153:b484a57bc302	1076	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge	153:b484a57bc302	1077	@{
AnnaBridge	153:b484a57bc302	1078	*/
AnnaBridge	153:b484a57bc302	1079
AnnaBridge	153:b484a57bc302	1080	/**
AnnaBridge	153:b484a57bc302	1081	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge	153:b484a57bc302	1082	*/
AnnaBridge	153:b484a57bc302	1083	typedef struct
AnnaBridge	153:b484a57bc302	1084	{
AnnaBridge	153:b484a57bc302	1085	__OM union
AnnaBridge	153:b484a57bc302	1086	{
AnnaBridge	153:b484a57bc302	1087	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	153:b484a57bc302	1088	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	153:b484a57bc302	1089	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	153:b484a57bc302	1090	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	153:b484a57bc302	1091	uint32_t RESERVED0[864U];
AnnaBridge	153:b484a57bc302	1092	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	153:b484a57bc302	1093	uint32_t RESERVED1[15U];
AnnaBridge	153:b484a57bc302	1094	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	153:b484a57bc302	1095	uint32_t RESERVED2[15U];
AnnaBridge	153:b484a57bc302	1096	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	153:b484a57bc302	1097	uint32_t RESERVED3[29U];
AnnaBridge	153:b484a57bc302	1098	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	153:b484a57bc302	1099	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	153:b484a57bc302	1100	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	153:b484a57bc302	1101	uint32_t RESERVED4[43U];
AnnaBridge	153:b484a57bc302	1102	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	153:b484a57bc302	1103	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	153:b484a57bc302	1104	uint32_t RESERVED5[1U];
AnnaBridge	153:b484a57bc302	1105	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
AnnaBridge	153:b484a57bc302	1106	uint32_t RESERVED6[4U];
AnnaBridge	153:b484a57bc302	1107	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	153:b484a57bc302	1108	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	153:b484a57bc302	1109	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	153:b484a57bc302	1110	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	153:b484a57bc302	1111	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	153:b484a57bc302	1112	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	153:b484a57bc302	1113	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	153:b484a57bc302	1114	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	153:b484a57bc302	1115	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	153:b484a57bc302	1116	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	153:b484a57bc302	1117	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	153:b484a57bc302	1118	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
AnnaBridge	153:b484a57bc302	1119	} ITM_Type;
AnnaBridge	153:b484a57bc302	1120
AnnaBridge	153:b484a57bc302	1121	/* ITM Stimulus Port Register Definitions */
AnnaBridge	153:b484a57bc302	1122	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
AnnaBridge	153:b484a57bc302	1123	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
AnnaBridge	153:b484a57bc302	1124
AnnaBridge	153:b484a57bc302	1125	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
AnnaBridge	153:b484a57bc302	1126	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
AnnaBridge	153:b484a57bc302	1127
AnnaBridge	153:b484a57bc302	1128	/* ITM Trace Privilege Register Definitions */
AnnaBridge	153:b484a57bc302	1129	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
AnnaBridge	153:b484a57bc302	1130	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
AnnaBridge	153:b484a57bc302	1131
AnnaBridge	153:b484a57bc302	1132	/* ITM Trace Control Register Definitions */
AnnaBridge	153:b484a57bc302	1133	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
AnnaBridge	153:b484a57bc302	1134	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
AnnaBridge	153:b484a57bc302	1135
AnnaBridge	153:b484a57bc302	1136	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
AnnaBridge	153:b484a57bc302	1137	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
AnnaBridge	153:b484a57bc302	1138
AnnaBridge	153:b484a57bc302	1139	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
AnnaBridge	153:b484a57bc302	1140	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
AnnaBridge	153:b484a57bc302	1141
AnnaBridge	153:b484a57bc302	1142	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
AnnaBridge	153:b484a57bc302	1143	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
AnnaBridge	153:b484a57bc302	1144
AnnaBridge	153:b484a57bc302	1145	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
AnnaBridge	153:b484a57bc302	1146	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
AnnaBridge	153:b484a57bc302	1147
AnnaBridge	153:b484a57bc302	1148	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
AnnaBridge	153:b484a57bc302	1149	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
AnnaBridge	153:b484a57bc302	1150
AnnaBridge	153:b484a57bc302	1151	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
AnnaBridge	153:b484a57bc302	1152	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
AnnaBridge	153:b484a57bc302	1153
AnnaBridge	153:b484a57bc302	1154	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
AnnaBridge	153:b484a57bc302	1155	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
AnnaBridge	153:b484a57bc302	1156
AnnaBridge	153:b484a57bc302	1157	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
AnnaBridge	153:b484a57bc302	1158	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
AnnaBridge	153:b484a57bc302	1159
AnnaBridge	153:b484a57bc302	1160	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
AnnaBridge	153:b484a57bc302	1161	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
AnnaBridge	153:b484a57bc302	1162
AnnaBridge	153:b484a57bc302	1163	/* ITM Integration Write Register Definitions */
AnnaBridge	153:b484a57bc302	1164	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
AnnaBridge	153:b484a57bc302	1165	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
AnnaBridge	153:b484a57bc302	1166
AnnaBridge	153:b484a57bc302	1167	/* ITM Integration Read Register Definitions */
AnnaBridge	153:b484a57bc302	1168	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
AnnaBridge	153:b484a57bc302	1169	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
AnnaBridge	153:b484a57bc302	1170
AnnaBridge	153:b484a57bc302	1171	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	153:b484a57bc302	1172	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
AnnaBridge	153:b484a57bc302	1173	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
AnnaBridge	153:b484a57bc302	1174
AnnaBridge	153:b484a57bc302	1175	/* ITM Lock Status Register Definitions */
AnnaBridge	153:b484a57bc302	1176	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
AnnaBridge	153:b484a57bc302	1177	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
AnnaBridge	153:b484a57bc302	1178
AnnaBridge	153:b484a57bc302	1179	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
AnnaBridge	153:b484a57bc302	1180	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
AnnaBridge	153:b484a57bc302	1181
AnnaBridge	153:b484a57bc302	1182	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
AnnaBridge	153:b484a57bc302	1183	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
AnnaBridge	153:b484a57bc302	1184
AnnaBridge	153:b484a57bc302	1185	/@}/ /* end of group CMSIS_ITM */
AnnaBridge	153:b484a57bc302	1186
AnnaBridge	153:b484a57bc302	1187
AnnaBridge	153:b484a57bc302	1188	/**
AnnaBridge	153:b484a57bc302	1189	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1190	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	153:b484a57bc302	1191	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	153:b484a57bc302	1192	@{
AnnaBridge	153:b484a57bc302	1193	*/
AnnaBridge	153:b484a57bc302	1194
AnnaBridge	153:b484a57bc302	1195	/**
AnnaBridge	153:b484a57bc302	1196	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	153:b484a57bc302	1197	*/
AnnaBridge	153:b484a57bc302	1198	typedef struct
AnnaBridge	153:b484a57bc302	1199	{
AnnaBridge	153:b484a57bc302	1200	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	153:b484a57bc302	1201	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	153:b484a57bc302	1202	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	153:b484a57bc302	1203	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	153:b484a57bc302	1204	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	153:b484a57bc302	1205	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	153:b484a57bc302	1206	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	153:b484a57bc302	1207	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	153:b484a57bc302	1208	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	153:b484a57bc302	1209	uint32_t RESERVED1[1U];
AnnaBridge	153:b484a57bc302	1210	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	153:b484a57bc302	1211	uint32_t RESERVED2[1U];
AnnaBridge	153:b484a57bc302	1212	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	153:b484a57bc302	1213	uint32_t RESERVED3[1U];
AnnaBridge	153:b484a57bc302	1214	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	153:b484a57bc302	1215	uint32_t RESERVED4[1U];
AnnaBridge	153:b484a57bc302	1216	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	153:b484a57bc302	1217	uint32_t RESERVED5[1U];
AnnaBridge	153:b484a57bc302	1218	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	153:b484a57bc302	1219	uint32_t RESERVED6[1U];
AnnaBridge	153:b484a57bc302	1220	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	153:b484a57bc302	1221	uint32_t RESERVED7[1U];
AnnaBridge	153:b484a57bc302	1222	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	153:b484a57bc302	1223	uint32_t RESERVED8[1U];
AnnaBridge	153:b484a57bc302	1224	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
AnnaBridge	153:b484a57bc302	1225	uint32_t RESERVED9[1U];
AnnaBridge	153:b484a57bc302	1226	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
AnnaBridge	153:b484a57bc302	1227	uint32_t RESERVED10[1U];
AnnaBridge	153:b484a57bc302	1228	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
AnnaBridge	153:b484a57bc302	1229	uint32_t RESERVED11[1U];
AnnaBridge	153:b484a57bc302	1230	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
AnnaBridge	153:b484a57bc302	1231	uint32_t RESERVED12[1U];
AnnaBridge	153:b484a57bc302	1232	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
AnnaBridge	153:b484a57bc302	1233	uint32_t RESERVED13[1U];
AnnaBridge	153:b484a57bc302	1234	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
AnnaBridge	153:b484a57bc302	1235	uint32_t RESERVED14[1U];
AnnaBridge	153:b484a57bc302	1236	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
AnnaBridge	153:b484a57bc302	1237	uint32_t RESERVED15[1U];
AnnaBridge	153:b484a57bc302	1238	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
AnnaBridge	153:b484a57bc302	1239	uint32_t RESERVED16[1U];
AnnaBridge	153:b484a57bc302	1240	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
AnnaBridge	153:b484a57bc302	1241	uint32_t RESERVED17[1U];
AnnaBridge	153:b484a57bc302	1242	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
AnnaBridge	153:b484a57bc302	1243	uint32_t RESERVED18[1U];
AnnaBridge	153:b484a57bc302	1244	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
AnnaBridge	153:b484a57bc302	1245	uint32_t RESERVED19[1U];
AnnaBridge	153:b484a57bc302	1246	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
AnnaBridge	153:b484a57bc302	1247	uint32_t RESERVED20[1U];
AnnaBridge	153:b484a57bc302	1248	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
AnnaBridge	153:b484a57bc302	1249	uint32_t RESERVED21[1U];
AnnaBridge	153:b484a57bc302	1250	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
AnnaBridge	153:b484a57bc302	1251	uint32_t RESERVED22[1U];
AnnaBridge	153:b484a57bc302	1252	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
AnnaBridge	153:b484a57bc302	1253	uint32_t RESERVED23[1U];
AnnaBridge	153:b484a57bc302	1254	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
AnnaBridge	153:b484a57bc302	1255	uint32_t RESERVED24[1U];
AnnaBridge	153:b484a57bc302	1256	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
AnnaBridge	153:b484a57bc302	1257	uint32_t RESERVED25[1U];
AnnaBridge	153:b484a57bc302	1258	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
AnnaBridge	153:b484a57bc302	1259	uint32_t RESERVED26[1U];
AnnaBridge	153:b484a57bc302	1260	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
AnnaBridge	153:b484a57bc302	1261	uint32_t RESERVED27[1U];
AnnaBridge	153:b484a57bc302	1262	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
AnnaBridge	153:b484a57bc302	1263	uint32_t RESERVED28[1U];
AnnaBridge	153:b484a57bc302	1264	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
AnnaBridge	153:b484a57bc302	1265	uint32_t RESERVED29[1U];
AnnaBridge	153:b484a57bc302	1266	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
AnnaBridge	153:b484a57bc302	1267	uint32_t RESERVED30[1U];
AnnaBridge	153:b484a57bc302	1268	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
AnnaBridge	153:b484a57bc302	1269	uint32_t RESERVED31[1U];
AnnaBridge	153:b484a57bc302	1270	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
AnnaBridge	153:b484a57bc302	1271	uint32_t RESERVED32[934U];
AnnaBridge	153:b484a57bc302	1272	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
AnnaBridge	153:b484a57bc302	1273	uint32_t RESERVED33[1U];
AnnaBridge	153:b484a57bc302	1274	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
AnnaBridge	153:b484a57bc302	1275	} DWT_Type;
AnnaBridge	153:b484a57bc302	1276
AnnaBridge	153:b484a57bc302	1277	/* DWT Control Register Definitions */
AnnaBridge	153:b484a57bc302	1278	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	153:b484a57bc302	1279	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	153:b484a57bc302	1280
AnnaBridge	153:b484a57bc302	1281	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	153:b484a57bc302	1282	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	153:b484a57bc302	1283
AnnaBridge	153:b484a57bc302	1284	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	153:b484a57bc302	1285	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	153:b484a57bc302	1286
AnnaBridge	153:b484a57bc302	1287	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	153:b484a57bc302	1288	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	153:b484a57bc302	1289
AnnaBridge	153:b484a57bc302	1290	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	153:b484a57bc302	1291	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	153:b484a57bc302	1292
AnnaBridge	153:b484a57bc302	1293	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
AnnaBridge	153:b484a57bc302	1294	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
AnnaBridge	153:b484a57bc302	1295
AnnaBridge	153:b484a57bc302	1296	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
AnnaBridge	153:b484a57bc302	1297	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
AnnaBridge	153:b484a57bc302	1298
AnnaBridge	153:b484a57bc302	1299	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
AnnaBridge	153:b484a57bc302	1300	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
AnnaBridge	153:b484a57bc302	1301
AnnaBridge	153:b484a57bc302	1302	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
AnnaBridge	153:b484a57bc302	1303	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
AnnaBridge	153:b484a57bc302	1304
AnnaBridge	153:b484a57bc302	1305	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
AnnaBridge	153:b484a57bc302	1306	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
AnnaBridge	153:b484a57bc302	1307
AnnaBridge	153:b484a57bc302	1308	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
AnnaBridge	153:b484a57bc302	1309	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
AnnaBridge	153:b484a57bc302	1310
AnnaBridge	153:b484a57bc302	1311	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
AnnaBridge	153:b484a57bc302	1312	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
AnnaBridge	153:b484a57bc302	1313
AnnaBridge	153:b484a57bc302	1314	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
AnnaBridge	153:b484a57bc302	1315	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
AnnaBridge	153:b484a57bc302	1316
AnnaBridge	153:b484a57bc302	1317	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
AnnaBridge	153:b484a57bc302	1318	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
AnnaBridge	153:b484a57bc302	1319
AnnaBridge	153:b484a57bc302	1320	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
AnnaBridge	153:b484a57bc302	1321	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
AnnaBridge	153:b484a57bc302	1322
AnnaBridge	153:b484a57bc302	1323	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
AnnaBridge	153:b484a57bc302	1324	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
AnnaBridge	153:b484a57bc302	1325
AnnaBridge	153:b484a57bc302	1326	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
AnnaBridge	153:b484a57bc302	1327	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
AnnaBridge	153:b484a57bc302	1328
AnnaBridge	153:b484a57bc302	1329	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
AnnaBridge	153:b484a57bc302	1330	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
AnnaBridge	153:b484a57bc302	1331
AnnaBridge	153:b484a57bc302	1332	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
AnnaBridge	153:b484a57bc302	1333	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
AnnaBridge	153:b484a57bc302	1334
AnnaBridge	153:b484a57bc302	1335	/* DWT CPI Count Register Definitions */
AnnaBridge	153:b484a57bc302	1336	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
AnnaBridge	153:b484a57bc302	1337	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
AnnaBridge	153:b484a57bc302	1338
AnnaBridge	153:b484a57bc302	1339	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	153:b484a57bc302	1340	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
AnnaBridge	153:b484a57bc302	1341	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
AnnaBridge	153:b484a57bc302	1342
AnnaBridge	153:b484a57bc302	1343	/* DWT Sleep Count Register Definitions */
AnnaBridge	153:b484a57bc302	1344	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
AnnaBridge	153:b484a57bc302	1345	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
AnnaBridge	153:b484a57bc302	1346
AnnaBridge	153:b484a57bc302	1347	/* DWT LSU Count Register Definitions */
AnnaBridge	153:b484a57bc302	1348	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
AnnaBridge	153:b484a57bc302	1349	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
AnnaBridge	153:b484a57bc302	1350
AnnaBridge	153:b484a57bc302	1351	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	153:b484a57bc302	1352	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
AnnaBridge	153:b484a57bc302	1353	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
AnnaBridge	153:b484a57bc302	1354
AnnaBridge	153:b484a57bc302	1355	/* DWT Comparator Function Register Definitions */
AnnaBridge	153:b484a57bc302	1356	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
AnnaBridge	153:b484a57bc302	1357	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
AnnaBridge	153:b484a57bc302	1358
AnnaBridge	153:b484a57bc302	1359	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	153:b484a57bc302	1360	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	153:b484a57bc302	1361
AnnaBridge	153:b484a57bc302	1362	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	153:b484a57bc302	1363	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	153:b484a57bc302	1364
AnnaBridge	153:b484a57bc302	1365	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
AnnaBridge	153:b484a57bc302	1366	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
AnnaBridge	153:b484a57bc302	1367
AnnaBridge	153:b484a57bc302	1368	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
AnnaBridge	153:b484a57bc302	1369	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
AnnaBridge	153:b484a57bc302	1370
AnnaBridge	153:b484a57bc302	1371	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	153:b484a57bc302	1372
AnnaBridge	153:b484a57bc302	1373
AnnaBridge	153:b484a57bc302	1374	/**
AnnaBridge	153:b484a57bc302	1375	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1376	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	153:b484a57bc302	1377	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	153:b484a57bc302	1378	@{
AnnaBridge	153:b484a57bc302	1379	*/
AnnaBridge	153:b484a57bc302	1380
AnnaBridge	153:b484a57bc302	1381	/**
AnnaBridge	153:b484a57bc302	1382	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	153:b484a57bc302	1383	*/
AnnaBridge	153:b484a57bc302	1384	typedef struct
AnnaBridge	153:b484a57bc302	1385	{
AnnaBridge	153:b484a57bc302	1386	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	153:b484a57bc302	1387	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	153:b484a57bc302	1388	uint32_t RESERVED0[2U];
AnnaBridge	153:b484a57bc302	1389	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	153:b484a57bc302	1390	uint32_t RESERVED1[55U];
AnnaBridge	153:b484a57bc302	1391	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	153:b484a57bc302	1392	uint32_t RESERVED2[131U];
AnnaBridge	153:b484a57bc302	1393	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	153:b484a57bc302	1394	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	153:b484a57bc302	1395	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	153:b484a57bc302	1396	uint32_t RESERVED3[759U];
AnnaBridge	153:b484a57bc302	1397	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	153:b484a57bc302	1398	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	153:b484a57bc302	1399	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	153:b484a57bc302	1400	uint32_t RESERVED4[1U];
AnnaBridge	153:b484a57bc302	1401	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	153:b484a57bc302	1402	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	153:b484a57bc302	1403	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	153:b484a57bc302	1404	uint32_t RESERVED5[39U];
AnnaBridge	153:b484a57bc302	1405	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	153:b484a57bc302	1406	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	153:b484a57bc302	1407	uint32_t RESERVED7[8U];
AnnaBridge	153:b484a57bc302	1408	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	153:b484a57bc302	1409	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	153:b484a57bc302	1410	} TPI_Type;
AnnaBridge	153:b484a57bc302	1411
AnnaBridge	153:b484a57bc302	1412	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	153:b484a57bc302	1413	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
AnnaBridge	153:b484a57bc302	1414	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
AnnaBridge	153:b484a57bc302	1415
AnnaBridge	153:b484a57bc302	1416	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	153:b484a57bc302	1417	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	153:b484a57bc302	1418	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	153:b484a57bc302	1419
AnnaBridge	153:b484a57bc302	1420	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	153:b484a57bc302	1421	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	153:b484a57bc302	1422	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	153:b484a57bc302	1423
AnnaBridge	153:b484a57bc302	1424	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	153:b484a57bc302	1425	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	153:b484a57bc302	1426
AnnaBridge	153:b484a57bc302	1427	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	153:b484a57bc302	1428	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	153:b484a57bc302	1429
AnnaBridge	153:b484a57bc302	1430	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	153:b484a57bc302	1431	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	153:b484a57bc302	1432
AnnaBridge	153:b484a57bc302	1433	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	153:b484a57bc302	1434	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	153:b484a57bc302	1435	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	153:b484a57bc302	1436
AnnaBridge	153:b484a57bc302	1437	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	153:b484a57bc302	1438	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	153:b484a57bc302	1439
AnnaBridge	153:b484a57bc302	1440	/* TPI TRIGGER Register Definitions */
AnnaBridge	153:b484a57bc302	1441	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	153:b484a57bc302	1442	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	153:b484a57bc302	1443
AnnaBridge	153:b484a57bc302	1444	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	153:b484a57bc302	1445	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	153:b484a57bc302	1446	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	153:b484a57bc302	1447
AnnaBridge	153:b484a57bc302	1448	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	153:b484a57bc302	1449	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	153:b484a57bc302	1450
AnnaBridge	153:b484a57bc302	1451	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	153:b484a57bc302	1452	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	153:b484a57bc302	1453
AnnaBridge	153:b484a57bc302	1454	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	153:b484a57bc302	1455	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	153:b484a57bc302	1456
AnnaBridge	153:b484a57bc302	1457	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
AnnaBridge	153:b484a57bc302	1458	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	153:b484a57bc302	1459
AnnaBridge	153:b484a57bc302	1460	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
AnnaBridge	153:b484a57bc302	1461	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	153:b484a57bc302	1462
AnnaBridge	153:b484a57bc302	1463	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
AnnaBridge	153:b484a57bc302	1464	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	153:b484a57bc302	1465
AnnaBridge	153:b484a57bc302	1466	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	153:b484a57bc302	1467	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
AnnaBridge	153:b484a57bc302	1468	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
AnnaBridge	153:b484a57bc302	1469
AnnaBridge	153:b484a57bc302	1470	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	153:b484a57bc302	1471	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	153:b484a57bc302	1472	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	153:b484a57bc302	1473
AnnaBridge	153:b484a57bc302	1474	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	153:b484a57bc302	1475	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	153:b484a57bc302	1476
AnnaBridge	153:b484a57bc302	1477	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	153:b484a57bc302	1478	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	153:b484a57bc302	1479
AnnaBridge	153:b484a57bc302	1480	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	153:b484a57bc302	1481	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	153:b484a57bc302	1482
AnnaBridge	153:b484a57bc302	1483	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
AnnaBridge	153:b484a57bc302	1484	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	153:b484a57bc302	1485
AnnaBridge	153:b484a57bc302	1486	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
AnnaBridge	153:b484a57bc302	1487	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	153:b484a57bc302	1488
AnnaBridge	153:b484a57bc302	1489	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
AnnaBridge	153:b484a57bc302	1490	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	153:b484a57bc302	1491
AnnaBridge	153:b484a57bc302	1492	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	153:b484a57bc302	1493	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
AnnaBridge	153:b484a57bc302	1494	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
AnnaBridge	153:b484a57bc302	1495
AnnaBridge	153:b484a57bc302	1496	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	153:b484a57bc302	1497	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	153:b484a57bc302	1498	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	153:b484a57bc302	1499
AnnaBridge	153:b484a57bc302	1500	/* TPI DEVID Register Definitions */
AnnaBridge	153:b484a57bc302	1501	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	153:b484a57bc302	1502	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	153:b484a57bc302	1503
AnnaBridge	153:b484a57bc302	1504	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	153:b484a57bc302	1505	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	153:b484a57bc302	1506
AnnaBridge	153:b484a57bc302	1507	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	153:b484a57bc302	1508	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	153:b484a57bc302	1509
AnnaBridge	153:b484a57bc302	1510	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
AnnaBridge	153:b484a57bc302	1511	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	153:b484a57bc302	1512
AnnaBridge	153:b484a57bc302	1513	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	153:b484a57bc302	1514	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	153:b484a57bc302	1515
AnnaBridge	153:b484a57bc302	1516	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	153:b484a57bc302	1517	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	153:b484a57bc302	1518
AnnaBridge	153:b484a57bc302	1519	/* TPI DEVTYPE Register Definitions */
AnnaBridge	153:b484a57bc302	1520	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	153:b484a57bc302	1521	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	153:b484a57bc302	1522
AnnaBridge	153:b484a57bc302	1523	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	153:b484a57bc302	1524	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	153:b484a57bc302	1525
AnnaBridge	153:b484a57bc302	1526	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	153:b484a57bc302	1527
AnnaBridge	153:b484a57bc302	1528
AnnaBridge	153:b484a57bc302	1529	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	1530	/**
AnnaBridge	153:b484a57bc302	1531	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1532	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	153:b484a57bc302	1533	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	153:b484a57bc302	1534	@{
AnnaBridge	153:b484a57bc302	1535	*/
AnnaBridge	153:b484a57bc302	1536
AnnaBridge	153:b484a57bc302	1537	/**
AnnaBridge	153:b484a57bc302	1538	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	153:b484a57bc302	1539	*/
AnnaBridge	153:b484a57bc302	1540	typedef struct
AnnaBridge	153:b484a57bc302	1541	{
AnnaBridge	153:b484a57bc302	1542	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	153:b484a57bc302	1543	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	153:b484a57bc302	1544	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
AnnaBridge	153:b484a57bc302	1545	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	153:b484a57bc302	1546	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
AnnaBridge	153:b484a57bc302	1547	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
AnnaBridge	153:b484a57bc302	1548	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
AnnaBridge	153:b484a57bc302	1549	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
AnnaBridge	153:b484a57bc302	1550	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
AnnaBridge	153:b484a57bc302	1551	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
AnnaBridge	153:b484a57bc302	1552	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
AnnaBridge	153:b484a57bc302	1553	uint32_t RESERVED0[1];
Anna Bridge	160:5571c4ff569f	1554	union {
Anna Bridge	160:5571c4ff569f	1555	__IOM uint32_t MAIR[2];
Anna Bridge	160:5571c4ff569f	1556	struct {
AnnaBridge	153:b484a57bc302	1557	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
AnnaBridge	153:b484a57bc302	1558	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
Anna Bridge	160:5571c4ff569f	1559	};
Anna Bridge	160:5571c4ff569f	1560	};
AnnaBridge	153:b484a57bc302	1561	} MPU_Type;
AnnaBridge	153:b484a57bc302	1562
Anna Bridge	160:5571c4ff569f	1563	#define MPU_TYPE_RALIASES 4U
Anna Bridge	160:5571c4ff569f	1564
AnnaBridge	153:b484a57bc302	1565	/* MPU Type Register Definitions */
AnnaBridge	153:b484a57bc302	1566	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	153:b484a57bc302	1567	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	153:b484a57bc302	1568
AnnaBridge	153:b484a57bc302	1569	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	153:b484a57bc302	1570	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	153:b484a57bc302	1571
AnnaBridge	153:b484a57bc302	1572	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	153:b484a57bc302	1573	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	153:b484a57bc302	1574
AnnaBridge	153:b484a57bc302	1575	/* MPU Control Register Definitions */
AnnaBridge	153:b484a57bc302	1576	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	153:b484a57bc302	1577	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	153:b484a57bc302	1578
AnnaBridge	153:b484a57bc302	1579	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	153:b484a57bc302	1580	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	153:b484a57bc302	1581
AnnaBridge	153:b484a57bc302	1582	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	153:b484a57bc302	1583	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	153:b484a57bc302	1584
AnnaBridge	153:b484a57bc302	1585	/* MPU Region Number Register Definitions */
AnnaBridge	153:b484a57bc302	1586	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	153:b484a57bc302	1587	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	153:b484a57bc302	1588
AnnaBridge	153:b484a57bc302	1589	/* MPU Region Base Address Register Definitions */
AnnaBridge	153:b484a57bc302	1590	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
AnnaBridge	153:b484a57bc302	1591	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
AnnaBridge	153:b484a57bc302	1592
AnnaBridge	153:b484a57bc302	1593	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
AnnaBridge	153:b484a57bc302	1594	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
AnnaBridge	153:b484a57bc302	1595
AnnaBridge	153:b484a57bc302	1596	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
AnnaBridge	153:b484a57bc302	1597	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
AnnaBridge	153:b484a57bc302	1598
AnnaBridge	153:b484a57bc302	1599	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
AnnaBridge	153:b484a57bc302	1600	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
AnnaBridge	153:b484a57bc302	1601
AnnaBridge	153:b484a57bc302	1602	/* MPU Region Limit Address Register Definitions */
AnnaBridge	153:b484a57bc302	1603	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
AnnaBridge	153:b484a57bc302	1604	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
AnnaBridge	153:b484a57bc302	1605
AnnaBridge	153:b484a57bc302	1606	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
AnnaBridge	153:b484a57bc302	1607	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
AnnaBridge	153:b484a57bc302	1608
AnnaBridge	153:b484a57bc302	1609	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
AnnaBridge	153:b484a57bc302	1610	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
AnnaBridge	153:b484a57bc302	1611
AnnaBridge	153:b484a57bc302	1612	/* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge	153:b484a57bc302	1613	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
AnnaBridge	153:b484a57bc302	1614	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
AnnaBridge	153:b484a57bc302	1615
AnnaBridge	153:b484a57bc302	1616	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
AnnaBridge	153:b484a57bc302	1617	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
AnnaBridge	153:b484a57bc302	1618
AnnaBridge	153:b484a57bc302	1619	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
AnnaBridge	153:b484a57bc302	1620	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
AnnaBridge	153:b484a57bc302	1621
AnnaBridge	153:b484a57bc302	1622	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
AnnaBridge	153:b484a57bc302	1623	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
AnnaBridge	153:b484a57bc302	1624
AnnaBridge	153:b484a57bc302	1625	/* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge	153:b484a57bc302	1626	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
AnnaBridge	153:b484a57bc302	1627	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
AnnaBridge	153:b484a57bc302	1628
AnnaBridge	153:b484a57bc302	1629	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
AnnaBridge	153:b484a57bc302	1630	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
AnnaBridge	153:b484a57bc302	1631
AnnaBridge	153:b484a57bc302	1632	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
AnnaBridge	153:b484a57bc302	1633	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
AnnaBridge	153:b484a57bc302	1634
AnnaBridge	153:b484a57bc302	1635	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
AnnaBridge	153:b484a57bc302	1636	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
AnnaBridge	153:b484a57bc302	1637
AnnaBridge	153:b484a57bc302	1638	/@} end of group CMSIS_MPU /
AnnaBridge	153:b484a57bc302	1639	#endif
AnnaBridge	153:b484a57bc302	1640
AnnaBridge	153:b484a57bc302	1641
AnnaBridge	153:b484a57bc302	1642	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	153:b484a57bc302	1643	/**
AnnaBridge	153:b484a57bc302	1644	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1645	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge	153:b484a57bc302	1646	\brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge	153:b484a57bc302	1647	@{
AnnaBridge	153:b484a57bc302	1648	*/
AnnaBridge	153:b484a57bc302	1649
AnnaBridge	153:b484a57bc302	1650	/**
AnnaBridge	153:b484a57bc302	1651	\brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge	153:b484a57bc302	1652	*/
AnnaBridge	153:b484a57bc302	1653	typedef struct
AnnaBridge	153:b484a57bc302	1654	{
AnnaBridge	153:b484a57bc302	1655	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
AnnaBridge	153:b484a57bc302	1656	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
AnnaBridge	153:b484a57bc302	1657	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	1658	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
AnnaBridge	153:b484a57bc302	1659	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
AnnaBridge	153:b484a57bc302	1660	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
AnnaBridge	153:b484a57bc302	1661	#else
AnnaBridge	153:b484a57bc302	1662	uint32_t RESERVED0[3];
AnnaBridge	153:b484a57bc302	1663	#endif
AnnaBridge	153:b484a57bc302	1664	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
AnnaBridge	153:b484a57bc302	1665	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
AnnaBridge	153:b484a57bc302	1666	} SAU_Type;
AnnaBridge	153:b484a57bc302	1667
AnnaBridge	153:b484a57bc302	1668	/* SAU Control Register Definitions */
AnnaBridge	153:b484a57bc302	1669	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
AnnaBridge	153:b484a57bc302	1670	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
AnnaBridge	153:b484a57bc302	1671
AnnaBridge	153:b484a57bc302	1672	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
AnnaBridge	153:b484a57bc302	1673	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
AnnaBridge	153:b484a57bc302	1674
AnnaBridge	153:b484a57bc302	1675	/* SAU Type Register Definitions */
AnnaBridge	153:b484a57bc302	1676	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
AnnaBridge	153:b484a57bc302	1677	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
AnnaBridge	153:b484a57bc302	1678
AnnaBridge	153:b484a57bc302	1679	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	1680	/* SAU Region Number Register Definitions */
AnnaBridge	153:b484a57bc302	1681	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
AnnaBridge	153:b484a57bc302	1682	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
AnnaBridge	153:b484a57bc302	1683
AnnaBridge	153:b484a57bc302	1684	/* SAU Region Base Address Register Definitions */
AnnaBridge	153:b484a57bc302	1685	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
AnnaBridge	153:b484a57bc302	1686	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
AnnaBridge	153:b484a57bc302	1687
AnnaBridge	153:b484a57bc302	1688	/* SAU Region Limit Address Register Definitions */
AnnaBridge	153:b484a57bc302	1689	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
AnnaBridge	153:b484a57bc302	1690	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
AnnaBridge	153:b484a57bc302	1691
AnnaBridge	153:b484a57bc302	1692	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
AnnaBridge	153:b484a57bc302	1693	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
AnnaBridge	153:b484a57bc302	1694
AnnaBridge	153:b484a57bc302	1695	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
AnnaBridge	153:b484a57bc302	1696	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
AnnaBridge	153:b484a57bc302	1697
AnnaBridge	153:b484a57bc302	1698	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge	153:b484a57bc302	1699
AnnaBridge	153:b484a57bc302	1700	/* Secure Fault Status Register Definitions */
AnnaBridge	153:b484a57bc302	1701	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
AnnaBridge	153:b484a57bc302	1702	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
AnnaBridge	153:b484a57bc302	1703
AnnaBridge	153:b484a57bc302	1704	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
AnnaBridge	153:b484a57bc302	1705	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
AnnaBridge	153:b484a57bc302	1706
AnnaBridge	153:b484a57bc302	1707	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
AnnaBridge	153:b484a57bc302	1708	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
AnnaBridge	153:b484a57bc302	1709
AnnaBridge	153:b484a57bc302	1710	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
AnnaBridge	153:b484a57bc302	1711	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
AnnaBridge	153:b484a57bc302	1712
AnnaBridge	153:b484a57bc302	1713	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
AnnaBridge	153:b484a57bc302	1714	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
AnnaBridge	153:b484a57bc302	1715
AnnaBridge	153:b484a57bc302	1716	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
AnnaBridge	153:b484a57bc302	1717	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
AnnaBridge	153:b484a57bc302	1718
AnnaBridge	153:b484a57bc302	1719	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
AnnaBridge	153:b484a57bc302	1720	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
AnnaBridge	153:b484a57bc302	1721
AnnaBridge	153:b484a57bc302	1722	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
AnnaBridge	153:b484a57bc302	1723	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
AnnaBridge	153:b484a57bc302	1724
AnnaBridge	153:b484a57bc302	1725	/@} end of group CMSIS_SAU /
AnnaBridge	153:b484a57bc302	1726	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	153:b484a57bc302	1727
AnnaBridge	153:b484a57bc302	1728
AnnaBridge	153:b484a57bc302	1729	/**
AnnaBridge	153:b484a57bc302	1730	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1731	\defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge	153:b484a57bc302	1732	\brief Type definitions for the Floating Point Unit (FPU)
AnnaBridge	153:b484a57bc302	1733	@{
AnnaBridge	153:b484a57bc302	1734	*/
AnnaBridge	153:b484a57bc302	1735
AnnaBridge	153:b484a57bc302	1736	/**
AnnaBridge	153:b484a57bc302	1737	\brief Structure type to access the Floating Point Unit (FPU).
AnnaBridge	153:b484a57bc302	1738	*/
AnnaBridge	153:b484a57bc302	1739	typedef struct
AnnaBridge	153:b484a57bc302	1740	{
AnnaBridge	153:b484a57bc302	1741	uint32_t RESERVED0[1U];
AnnaBridge	153:b484a57bc302	1742	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
AnnaBridge	153:b484a57bc302	1743	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
AnnaBridge	153:b484a57bc302	1744	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
AnnaBridge	153:b484a57bc302	1745	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
AnnaBridge	153:b484a57bc302	1746	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
AnnaBridge	153:b484a57bc302	1747	} FPU_Type;
AnnaBridge	153:b484a57bc302	1748
AnnaBridge	153:b484a57bc302	1749	/* Floating-Point Context Control Register Definitions */
AnnaBridge	153:b484a57bc302	1750	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
AnnaBridge	153:b484a57bc302	1751	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
AnnaBridge	153:b484a57bc302	1752
AnnaBridge	153:b484a57bc302	1753	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
AnnaBridge	153:b484a57bc302	1754	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
AnnaBridge	153:b484a57bc302	1755
AnnaBridge	153:b484a57bc302	1756	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
AnnaBridge	153:b484a57bc302	1757	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
AnnaBridge	153:b484a57bc302	1758
AnnaBridge	153:b484a57bc302	1759	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
AnnaBridge	153:b484a57bc302	1760	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
AnnaBridge	153:b484a57bc302	1761
AnnaBridge	153:b484a57bc302	1762	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
AnnaBridge	153:b484a57bc302	1763	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
AnnaBridge	153:b484a57bc302	1764
AnnaBridge	153:b484a57bc302	1765	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
AnnaBridge	153:b484a57bc302	1766	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
AnnaBridge	153:b484a57bc302	1767
AnnaBridge	153:b484a57bc302	1768	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
AnnaBridge	153:b484a57bc302	1769	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
AnnaBridge	153:b484a57bc302	1770
AnnaBridge	153:b484a57bc302	1771	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
AnnaBridge	153:b484a57bc302	1772	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
AnnaBridge	153:b484a57bc302	1773
AnnaBridge	153:b484a57bc302	1774	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
AnnaBridge	153:b484a57bc302	1775	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
AnnaBridge	153:b484a57bc302	1776
AnnaBridge	153:b484a57bc302	1777	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
AnnaBridge	153:b484a57bc302	1778	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
AnnaBridge	153:b484a57bc302	1779
AnnaBridge	153:b484a57bc302	1780	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
AnnaBridge	153:b484a57bc302	1781	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
AnnaBridge	153:b484a57bc302	1782
AnnaBridge	153:b484a57bc302	1783	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
AnnaBridge	153:b484a57bc302	1784	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
AnnaBridge	153:b484a57bc302	1785
AnnaBridge	153:b484a57bc302	1786	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
AnnaBridge	153:b484a57bc302	1787	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
AnnaBridge	153:b484a57bc302	1788
AnnaBridge	153:b484a57bc302	1789	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
AnnaBridge	153:b484a57bc302	1790	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
AnnaBridge	153:b484a57bc302	1791
AnnaBridge	153:b484a57bc302	1792	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
AnnaBridge	153:b484a57bc302	1793	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
AnnaBridge	153:b484a57bc302	1794
AnnaBridge	153:b484a57bc302	1795	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
AnnaBridge	153:b484a57bc302	1796	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
AnnaBridge	153:b484a57bc302	1797
AnnaBridge	153:b484a57bc302	1798	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
AnnaBridge	153:b484a57bc302	1799	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
AnnaBridge	153:b484a57bc302	1800
AnnaBridge	153:b484a57bc302	1801	/* Floating-Point Context Address Register Definitions */
AnnaBridge	153:b484a57bc302	1802	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
AnnaBridge	153:b484a57bc302	1803	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
AnnaBridge	153:b484a57bc302	1804
AnnaBridge	153:b484a57bc302	1805	/* Floating-Point Default Status Control Register Definitions */
AnnaBridge	153:b484a57bc302	1806	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
AnnaBridge	153:b484a57bc302	1807	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
AnnaBridge	153:b484a57bc302	1808
AnnaBridge	153:b484a57bc302	1809	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
AnnaBridge	153:b484a57bc302	1810	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
AnnaBridge	153:b484a57bc302	1811
AnnaBridge	153:b484a57bc302	1812	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
AnnaBridge	153:b484a57bc302	1813	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
AnnaBridge	153:b484a57bc302	1814
AnnaBridge	153:b484a57bc302	1815	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
AnnaBridge	153:b484a57bc302	1816	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
AnnaBridge	153:b484a57bc302	1817
AnnaBridge	153:b484a57bc302	1818	/* Media and FP Feature Register 0 Definitions */
AnnaBridge	153:b484a57bc302	1819	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
AnnaBridge	153:b484a57bc302	1820	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
AnnaBridge	153:b484a57bc302	1821
AnnaBridge	153:b484a57bc302	1822	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
AnnaBridge	153:b484a57bc302	1823	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
AnnaBridge	153:b484a57bc302	1824
AnnaBridge	153:b484a57bc302	1825	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
AnnaBridge	153:b484a57bc302	1826	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
AnnaBridge	153:b484a57bc302	1827
AnnaBridge	153:b484a57bc302	1828	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
AnnaBridge	153:b484a57bc302	1829	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
AnnaBridge	153:b484a57bc302	1830
AnnaBridge	153:b484a57bc302	1831	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
AnnaBridge	153:b484a57bc302	1832	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
AnnaBridge	153:b484a57bc302	1833
AnnaBridge	153:b484a57bc302	1834	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
AnnaBridge	153:b484a57bc302	1835	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
AnnaBridge	153:b484a57bc302	1836
AnnaBridge	153:b484a57bc302	1837	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
AnnaBridge	153:b484a57bc302	1838	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
AnnaBridge	153:b484a57bc302	1839
AnnaBridge	153:b484a57bc302	1840	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
AnnaBridge	153:b484a57bc302	1841	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
AnnaBridge	153:b484a57bc302	1842
AnnaBridge	153:b484a57bc302	1843	/* Media and FP Feature Register 1 Definitions */
AnnaBridge	153:b484a57bc302	1844	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
AnnaBridge	153:b484a57bc302	1845	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
AnnaBridge	153:b484a57bc302	1846
AnnaBridge	153:b484a57bc302	1847	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
AnnaBridge	153:b484a57bc302	1848	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
AnnaBridge	153:b484a57bc302	1849
AnnaBridge	153:b484a57bc302	1850	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
AnnaBridge	153:b484a57bc302	1851	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
AnnaBridge	153:b484a57bc302	1852
AnnaBridge	153:b484a57bc302	1853	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
AnnaBridge	153:b484a57bc302	1854	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
AnnaBridge	153:b484a57bc302	1855
AnnaBridge	153:b484a57bc302	1856	/@} end of group CMSIS_FPU /
AnnaBridge	153:b484a57bc302	1857
AnnaBridge	153:b484a57bc302	1858
AnnaBridge	153:b484a57bc302	1859	/**
AnnaBridge	153:b484a57bc302	1860	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1861	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	153:b484a57bc302	1862	\brief Type definitions for the Core Debug Registers
AnnaBridge	153:b484a57bc302	1863	@{
AnnaBridge	153:b484a57bc302	1864	*/
AnnaBridge	153:b484a57bc302	1865
AnnaBridge	153:b484a57bc302	1866	/**
AnnaBridge	153:b484a57bc302	1867	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	153:b484a57bc302	1868	*/
AnnaBridge	153:b484a57bc302	1869	typedef struct
AnnaBridge	153:b484a57bc302	1870	{
AnnaBridge	153:b484a57bc302	1871	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	153:b484a57bc302	1872	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	153:b484a57bc302	1873	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	153:b484a57bc302	1874	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	153:b484a57bc302	1875	uint32_t RESERVED4[1U];
AnnaBridge	153:b484a57bc302	1876	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
AnnaBridge	153:b484a57bc302	1877	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
AnnaBridge	153:b484a57bc302	1878	} CoreDebug_Type;
AnnaBridge	153:b484a57bc302	1879
AnnaBridge	153:b484a57bc302	1880	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	153:b484a57bc302	1881	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	153:b484a57bc302	1882	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	153:b484a57bc302	1883
AnnaBridge	153:b484a57bc302	1884	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
AnnaBridge	153:b484a57bc302	1885	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
AnnaBridge	153:b484a57bc302	1886
AnnaBridge	153:b484a57bc302	1887	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	153:b484a57bc302	1888	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	153:b484a57bc302	1889
AnnaBridge	153:b484a57bc302	1890	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	153:b484a57bc302	1891	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	153:b484a57bc302	1892
AnnaBridge	153:b484a57bc302	1893	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	153:b484a57bc302	1894	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	153:b484a57bc302	1895
AnnaBridge	153:b484a57bc302	1896	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	153:b484a57bc302	1897	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	153:b484a57bc302	1898
AnnaBridge	153:b484a57bc302	1899	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	153:b484a57bc302	1900	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	153:b484a57bc302	1901
AnnaBridge	153:b484a57bc302	1902	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	153:b484a57bc302	1903	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	153:b484a57bc302	1904
AnnaBridge	153:b484a57bc302	1905	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
AnnaBridge	153:b484a57bc302	1906	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
AnnaBridge	153:b484a57bc302	1907
AnnaBridge	153:b484a57bc302	1908	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	153:b484a57bc302	1909	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	153:b484a57bc302	1910
AnnaBridge	153:b484a57bc302	1911	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	153:b484a57bc302	1912	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	153:b484a57bc302	1913
AnnaBridge	153:b484a57bc302	1914	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	153:b484a57bc302	1915	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	153:b484a57bc302	1916
AnnaBridge	153:b484a57bc302	1917	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	153:b484a57bc302	1918	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	153:b484a57bc302	1919
AnnaBridge	153:b484a57bc302	1920	/* Debug Core Register Selector Register Definitions */
AnnaBridge	153:b484a57bc302	1921	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	153:b484a57bc302	1922	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	153:b484a57bc302	1923
AnnaBridge	153:b484a57bc302	1924	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	153:b484a57bc302	1925	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	153:b484a57bc302	1926
AnnaBridge	153:b484a57bc302	1927	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	153:b484a57bc302	1928	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
AnnaBridge	153:b484a57bc302	1929	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
AnnaBridge	153:b484a57bc302	1930
AnnaBridge	153:b484a57bc302	1931	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
AnnaBridge	153:b484a57bc302	1932	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
AnnaBridge	153:b484a57bc302	1933
AnnaBridge	153:b484a57bc302	1934	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
AnnaBridge	153:b484a57bc302	1935	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
AnnaBridge	153:b484a57bc302	1936
AnnaBridge	153:b484a57bc302	1937	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
AnnaBridge	153:b484a57bc302	1938	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
AnnaBridge	153:b484a57bc302	1939
AnnaBridge	153:b484a57bc302	1940	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
AnnaBridge	153:b484a57bc302	1941	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
AnnaBridge	153:b484a57bc302	1942
AnnaBridge	153:b484a57bc302	1943	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	153:b484a57bc302	1944	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	153:b484a57bc302	1945
AnnaBridge	153:b484a57bc302	1946	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
AnnaBridge	153:b484a57bc302	1947	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
AnnaBridge	153:b484a57bc302	1948
AnnaBridge	153:b484a57bc302	1949	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
AnnaBridge	153:b484a57bc302	1950	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
AnnaBridge	153:b484a57bc302	1951
AnnaBridge	153:b484a57bc302	1952	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
AnnaBridge	153:b484a57bc302	1953	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
AnnaBridge	153:b484a57bc302	1954
AnnaBridge	153:b484a57bc302	1955	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
AnnaBridge	153:b484a57bc302	1956	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
AnnaBridge	153:b484a57bc302	1957
AnnaBridge	153:b484a57bc302	1958	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
AnnaBridge	153:b484a57bc302	1959	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
AnnaBridge	153:b484a57bc302	1960
AnnaBridge	153:b484a57bc302	1961	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
AnnaBridge	153:b484a57bc302	1962	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
AnnaBridge	153:b484a57bc302	1963
AnnaBridge	153:b484a57bc302	1964	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	153:b484a57bc302	1965	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	153:b484a57bc302	1966
AnnaBridge	153:b484a57bc302	1967	/* Debug Authentication Control Register Definitions */
AnnaBridge	153:b484a57bc302	1968	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
AnnaBridge	153:b484a57bc302	1969	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
AnnaBridge	153:b484a57bc302	1970
AnnaBridge	153:b484a57bc302	1971	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
AnnaBridge	153:b484a57bc302	1972	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
AnnaBridge	153:b484a57bc302	1973
AnnaBridge	153:b484a57bc302	1974	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
AnnaBridge	153:b484a57bc302	1975	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
AnnaBridge	153:b484a57bc302	1976
AnnaBridge	153:b484a57bc302	1977	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
AnnaBridge	153:b484a57bc302	1978	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
AnnaBridge	153:b484a57bc302	1979
AnnaBridge	153:b484a57bc302	1980	/* Debug Security Control and Status Register Definitions */
AnnaBridge	153:b484a57bc302	1981	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
AnnaBridge	153:b484a57bc302	1982	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
AnnaBridge	153:b484a57bc302	1983
AnnaBridge	153:b484a57bc302	1984	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
AnnaBridge	153:b484a57bc302	1985	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
AnnaBridge	153:b484a57bc302	1986
AnnaBridge	153:b484a57bc302	1987	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
AnnaBridge	153:b484a57bc302	1988	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
AnnaBridge	153:b484a57bc302	1989
AnnaBridge	153:b484a57bc302	1990	/@} end of group CMSIS_CoreDebug /
AnnaBridge	153:b484a57bc302	1991
AnnaBridge	153:b484a57bc302	1992
AnnaBridge	153:b484a57bc302	1993	/**
AnnaBridge	153:b484a57bc302	1994	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	1995	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	153:b484a57bc302	1996	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	153:b484a57bc302	1997	@{
AnnaBridge	153:b484a57bc302	1998	*/
AnnaBridge	153:b484a57bc302	1999
AnnaBridge	153:b484a57bc302	2000	/**
AnnaBridge	153:b484a57bc302	2001	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	153:b484a57bc302	2002	\param[in] field Name of the register bit field.
AnnaBridge	153:b484a57bc302	2003	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	153:b484a57bc302	2004	\return Masked and shifted value.
AnnaBridge	153:b484a57bc302	2005	*/
AnnaBridge	153:b484a57bc302	2006	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	153:b484a57bc302	2007
AnnaBridge	153:b484a57bc302	2008	/**
AnnaBridge	153:b484a57bc302	2009	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	153:b484a57bc302	2010	\param[in] field Name of the register bit field.
AnnaBridge	153:b484a57bc302	2011	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	153:b484a57bc302	2012	\return Masked and shifted bit field value.
AnnaBridge	153:b484a57bc302	2013	*/
AnnaBridge	153:b484a57bc302	2014	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	153:b484a57bc302	2015
AnnaBridge	153:b484a57bc302	2016	/@} end of group CMSIS_core_bitfield /
AnnaBridge	153:b484a57bc302	2017
AnnaBridge	153:b484a57bc302	2018
AnnaBridge	153:b484a57bc302	2019	/**
AnnaBridge	153:b484a57bc302	2020	\ingroup CMSIS_core_register
AnnaBridge	153:b484a57bc302	2021	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	153:b484a57bc302	2022	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	153:b484a57bc302	2023	@{
AnnaBridge	153:b484a57bc302	2024	*/
AnnaBridge	153:b484a57bc302	2025
AnnaBridge	153:b484a57bc302	2026	/* Memory mapping of Core Hardware */
AnnaBridge	153:b484a57bc302	2027	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	153:b484a57bc302	2028	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	153:b484a57bc302	2029	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	153:b484a57bc302	2030	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	153:b484a57bc302	2031	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	153:b484a57bc302	2032	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	153:b484a57bc302	2033	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	153:b484a57bc302	2034	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	153:b484a57bc302	2035
AnnaBridge	153:b484a57bc302	2036	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	153:b484a57bc302	2037	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	153:b484a57bc302	2038	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	153:b484a57bc302	2039	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	153:b484a57bc302	2040	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	153:b484a57bc302	2041	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	153:b484a57bc302	2042	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	153:b484a57bc302	2043	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
AnnaBridge	153:b484a57bc302	2044
AnnaBridge	153:b484a57bc302	2045	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2046	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	153:b484a57bc302	2047	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	153:b484a57bc302	2048	#endif
AnnaBridge	153:b484a57bc302	2049
AnnaBridge	153:b484a57bc302	2050	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	153:b484a57bc302	2051	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
AnnaBridge	153:b484a57bc302	2052	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
AnnaBridge	153:b484a57bc302	2053	#endif
AnnaBridge	153:b484a57bc302	2054
AnnaBridge	153:b484a57bc302	2055	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
AnnaBridge	153:b484a57bc302	2056	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
AnnaBridge	153:b484a57bc302	2057
AnnaBridge	153:b484a57bc302	2058	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	153:b484a57bc302	2059	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
AnnaBridge	153:b484a57bc302	2060	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
AnnaBridge	153:b484a57bc302	2061	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
AnnaBridge	153:b484a57bc302	2062	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
AnnaBridge	153:b484a57bc302	2063	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
AnnaBridge	153:b484a57bc302	2064
AnnaBridge	153:b484a57bc302	2065	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
AnnaBridge	153:b484a57bc302	2066	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
AnnaBridge	153:b484a57bc302	2067	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
AnnaBridge	153:b484a57bc302	2068	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
AnnaBridge	153:b484a57bc302	2069	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
AnnaBridge	153:b484a57bc302	2070
AnnaBridge	153:b484a57bc302	2071	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	153:b484a57bc302	2072	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
AnnaBridge	153:b484a57bc302	2073	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
AnnaBridge	153:b484a57bc302	2074	#endif
AnnaBridge	153:b484a57bc302	2075
AnnaBridge	153:b484a57bc302	2076	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
AnnaBridge	153:b484a57bc302	2077	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
AnnaBridge	153:b484a57bc302	2078
AnnaBridge	153:b484a57bc302	2079	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	153:b484a57bc302	2080	/@} /
AnnaBridge	153:b484a57bc302	2081
AnnaBridge	153:b484a57bc302	2082
AnnaBridge	153:b484a57bc302	2083
AnnaBridge	153:b484a57bc302	2084	/*******************************************************************************
AnnaBridge	153:b484a57bc302	2085	* Hardware Abstraction Layer
AnnaBridge	153:b484a57bc302	2086	Core Function Interface contains:
AnnaBridge	153:b484a57bc302	2087	- Core NVIC Functions
AnnaBridge	153:b484a57bc302	2088	- Core SysTick Functions
AnnaBridge	153:b484a57bc302	2089	- Core Debug Functions
AnnaBridge	153:b484a57bc302	2090	- Core Register Access Functions
AnnaBridge	153:b484a57bc302	2091	******************************************************************************/
AnnaBridge	153:b484a57bc302	2092	/**
AnnaBridge	153:b484a57bc302	2093	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	153:b484a57bc302	2094	*/
AnnaBridge	153:b484a57bc302	2095
AnnaBridge	153:b484a57bc302	2096
AnnaBridge	153:b484a57bc302	2097
AnnaBridge	153:b484a57bc302	2098	/* ########################## NVIC functions #################################### */
AnnaBridge	153:b484a57bc302	2099	/**
AnnaBridge	153:b484a57bc302	2100	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	153:b484a57bc302	2101	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	153:b484a57bc302	2102	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	153:b484a57bc302	2103	@{
AnnaBridge	153:b484a57bc302	2104	*/
AnnaBridge	153:b484a57bc302	2105
AnnaBridge	153:b484a57bc302	2106	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	153:b484a57bc302	2107	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	153:b484a57bc302	2108	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	153:b484a57bc302	2109	#endif
AnnaBridge	153:b484a57bc302	2110	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	153:b484a57bc302	2111	#else
AnnaBridge	153:b484a57bc302	2112	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge	153:b484a57bc302	2113	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge	153:b484a57bc302	2114	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	153:b484a57bc302	2115	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	153:b484a57bc302	2116	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	153:b484a57bc302	2117	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	153:b484a57bc302	2118	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	153:b484a57bc302	2119	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	153:b484a57bc302	2120	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	153:b484a57bc302	2121	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	153:b484a57bc302	2122	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	153:b484a57bc302	2123	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	153:b484a57bc302	2124	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	153:b484a57bc302	2125
AnnaBridge	153:b484a57bc302	2126	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	153:b484a57bc302	2127	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	153:b484a57bc302	2128	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	153:b484a57bc302	2129	#endif
AnnaBridge	153:b484a57bc302	2130	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	153:b484a57bc302	2131	#else
AnnaBridge	153:b484a57bc302	2132	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	153:b484a57bc302	2133	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	153:b484a57bc302	2134	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	153:b484a57bc302	2135
AnnaBridge	153:b484a57bc302	2136	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	153:b484a57bc302	2137
AnnaBridge	153:b484a57bc302	2138
AnnaBridge	153:b484a57bc302	2139
AnnaBridge	153:b484a57bc302	2140	/**
AnnaBridge	153:b484a57bc302	2141	\brief Set Priority Grouping
AnnaBridge	153:b484a57bc302	2142	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	153:b484a57bc302	2143	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	153:b484a57bc302	2144	Only values from 0..7 are used.
AnnaBridge	153:b484a57bc302	2145	In case of a conflict between priority grouping and available
AnnaBridge	153:b484a57bc302	2146	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	153:b484a57bc302	2147	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	153:b484a57bc302	2148	*/
AnnaBridge	153:b484a57bc302	2149	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge	153:b484a57bc302	2150	{
AnnaBridge	153:b484a57bc302	2151	uint32_t reg_value;
AnnaBridge	153:b484a57bc302	2152	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	153:b484a57bc302	2153
AnnaBridge	153:b484a57bc302	2154	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	153:b484a57bc302	2155	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	153:b484a57bc302	2156	reg_value = (reg_value \|
AnnaBridge	153:b484a57bc302	2157	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	153:b484a57bc302	2158	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
AnnaBridge	153:b484a57bc302	2159	SCB->AIRCR = reg_value;
AnnaBridge	153:b484a57bc302	2160	}
AnnaBridge	153:b484a57bc302	2161
AnnaBridge	153:b484a57bc302	2162
AnnaBridge	153:b484a57bc302	2163	/**
AnnaBridge	153:b484a57bc302	2164	\brief Get Priority Grouping
AnnaBridge	153:b484a57bc302	2165	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	153:b484a57bc302	2166	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	153:b484a57bc302	2167	*/
AnnaBridge	153:b484a57bc302	2168	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge	153:b484a57bc302	2169	{
AnnaBridge	153:b484a57bc302	2170	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	153:b484a57bc302	2171	}
AnnaBridge	153:b484a57bc302	2172
AnnaBridge	153:b484a57bc302	2173
AnnaBridge	153:b484a57bc302	2174	/**
AnnaBridge	153:b484a57bc302	2175	\brief Enable Interrupt
AnnaBridge	153:b484a57bc302	2176	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	153:b484a57bc302	2177	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2178	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2179	*/
AnnaBridge	153:b484a57bc302	2180	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2181	{
AnnaBridge	153:b484a57bc302	2182	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2183	{
Anna Bridge	169:a7c7b631e539	2184	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	153:b484a57bc302	2185	}
AnnaBridge	153:b484a57bc302	2186	}
AnnaBridge	153:b484a57bc302	2187
AnnaBridge	153:b484a57bc302	2188
AnnaBridge	153:b484a57bc302	2189	/**
AnnaBridge	153:b484a57bc302	2190	\brief Get Interrupt Enable status
AnnaBridge	153:b484a57bc302	2191	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	153:b484a57bc302	2192	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2193	\return 0 Interrupt is not enabled.
AnnaBridge	153:b484a57bc302	2194	\return 1 Interrupt is enabled.
AnnaBridge	153:b484a57bc302	2195	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2196	*/
AnnaBridge	153:b484a57bc302	2197	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2198	{
AnnaBridge	153:b484a57bc302	2199	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2200	{
Anna Bridge	169:a7c7b631e539	2201	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	153:b484a57bc302	2202	}
AnnaBridge	153:b484a57bc302	2203	else
AnnaBridge	153:b484a57bc302	2204	{
AnnaBridge	153:b484a57bc302	2205	return(0U);
AnnaBridge	153:b484a57bc302	2206	}
AnnaBridge	153:b484a57bc302	2207	}
AnnaBridge	153:b484a57bc302	2208
AnnaBridge	153:b484a57bc302	2209
AnnaBridge	153:b484a57bc302	2210	/**
AnnaBridge	153:b484a57bc302	2211	\brief Disable Interrupt
AnnaBridge	153:b484a57bc302	2212	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	153:b484a57bc302	2213	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2214	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2215	*/
AnnaBridge	153:b484a57bc302	2216	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2217	{
AnnaBridge	153:b484a57bc302	2218	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2219	{
Anna Bridge	169:a7c7b631e539	2220	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	153:b484a57bc302	2221	__DSB();
AnnaBridge	153:b484a57bc302	2222	__ISB();
AnnaBridge	153:b484a57bc302	2223	}
AnnaBridge	153:b484a57bc302	2224	}
AnnaBridge	153:b484a57bc302	2225
AnnaBridge	153:b484a57bc302	2226
AnnaBridge	153:b484a57bc302	2227	/**
AnnaBridge	153:b484a57bc302	2228	\brief Get Pending Interrupt
AnnaBridge	153:b484a57bc302	2229	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	153:b484a57bc302	2230	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2231	\return 0 Interrupt status is not pending.
AnnaBridge	153:b484a57bc302	2232	\return 1 Interrupt status is pending.
AnnaBridge	153:b484a57bc302	2233	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2234	*/
AnnaBridge	153:b484a57bc302	2235	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2236	{
AnnaBridge	153:b484a57bc302	2237	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2238	{
Anna Bridge	169:a7c7b631e539	2239	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	153:b484a57bc302	2240	}
AnnaBridge	153:b484a57bc302	2241	else
AnnaBridge	153:b484a57bc302	2242	{
AnnaBridge	153:b484a57bc302	2243	return(0U);
AnnaBridge	153:b484a57bc302	2244	}
AnnaBridge	153:b484a57bc302	2245	}
AnnaBridge	153:b484a57bc302	2246
AnnaBridge	153:b484a57bc302	2247
AnnaBridge	153:b484a57bc302	2248	/**
AnnaBridge	153:b484a57bc302	2249	\brief Set Pending Interrupt
AnnaBridge	153:b484a57bc302	2250	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	153:b484a57bc302	2251	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2252	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2253	*/
AnnaBridge	153:b484a57bc302	2254	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2255	{
AnnaBridge	153:b484a57bc302	2256	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2257	{
Anna Bridge	169:a7c7b631e539	2258	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	153:b484a57bc302	2259	}
AnnaBridge	153:b484a57bc302	2260	}
AnnaBridge	153:b484a57bc302	2261
AnnaBridge	153:b484a57bc302	2262
AnnaBridge	153:b484a57bc302	2263	/**
AnnaBridge	153:b484a57bc302	2264	\brief Clear Pending Interrupt
AnnaBridge	153:b484a57bc302	2265	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	153:b484a57bc302	2266	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2267	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2268	*/
AnnaBridge	153:b484a57bc302	2269	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2270	{
AnnaBridge	153:b484a57bc302	2271	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2272	{
Anna Bridge	169:a7c7b631e539	2273	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	153:b484a57bc302	2274	}
AnnaBridge	153:b484a57bc302	2275	}
AnnaBridge	153:b484a57bc302	2276
AnnaBridge	153:b484a57bc302	2277
AnnaBridge	153:b484a57bc302	2278	/**
AnnaBridge	153:b484a57bc302	2279	\brief Get Active Interrupt
AnnaBridge	153:b484a57bc302	2280	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	153:b484a57bc302	2281	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2282	\return 0 Interrupt status is not active.
AnnaBridge	153:b484a57bc302	2283	\return 1 Interrupt status is active.
AnnaBridge	153:b484a57bc302	2284	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2285	*/
AnnaBridge	153:b484a57bc302	2286	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2287	{
AnnaBridge	153:b484a57bc302	2288	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2289	{
Anna Bridge	169:a7c7b631e539	2290	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	153:b484a57bc302	2291	}
AnnaBridge	153:b484a57bc302	2292	else
AnnaBridge	153:b484a57bc302	2293	{
AnnaBridge	153:b484a57bc302	2294	return(0U);
AnnaBridge	153:b484a57bc302	2295	}
AnnaBridge	153:b484a57bc302	2296	}
AnnaBridge	153:b484a57bc302	2297
AnnaBridge	153:b484a57bc302	2298
AnnaBridge	153:b484a57bc302	2299	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	153:b484a57bc302	2300	/**
AnnaBridge	153:b484a57bc302	2301	\brief Get Interrupt Target State
AnnaBridge	153:b484a57bc302	2302	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	153:b484a57bc302	2303	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2304	\return 0 if interrupt is assigned to Secure
AnnaBridge	153:b484a57bc302	2305	\return 1 if interrupt is assigned to Non Secure
AnnaBridge	153:b484a57bc302	2306	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2307	*/
AnnaBridge	153:b484a57bc302	2308	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2309	{
AnnaBridge	153:b484a57bc302	2310	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2311	{
Anna Bridge	169:a7c7b631e539	2312	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	153:b484a57bc302	2313	}
AnnaBridge	153:b484a57bc302	2314	else
AnnaBridge	153:b484a57bc302	2315	{
AnnaBridge	153:b484a57bc302	2316	return(0U);
AnnaBridge	153:b484a57bc302	2317	}
AnnaBridge	153:b484a57bc302	2318	}
AnnaBridge	153:b484a57bc302	2319
AnnaBridge	153:b484a57bc302	2320
AnnaBridge	153:b484a57bc302	2321	/**
AnnaBridge	153:b484a57bc302	2322	\brief Set Interrupt Target State
AnnaBridge	153:b484a57bc302	2323	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	153:b484a57bc302	2324	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2325	\return 0 if interrupt is assigned to Secure
AnnaBridge	153:b484a57bc302	2326	1 if interrupt is assigned to Non Secure
AnnaBridge	153:b484a57bc302	2327	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2328	*/
AnnaBridge	153:b484a57bc302	2329	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2330	{
AnnaBridge	153:b484a57bc302	2331	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2332	{
Anna Bridge	169:a7c7b631e539	2333	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge	169:a7c7b631e539	2334	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	153:b484a57bc302	2335	}
AnnaBridge	153:b484a57bc302	2336	else
AnnaBridge	153:b484a57bc302	2337	{
AnnaBridge	153:b484a57bc302	2338	return(0U);
AnnaBridge	153:b484a57bc302	2339	}
AnnaBridge	153:b484a57bc302	2340	}
AnnaBridge	153:b484a57bc302	2341
AnnaBridge	153:b484a57bc302	2342
AnnaBridge	153:b484a57bc302	2343	/**
AnnaBridge	153:b484a57bc302	2344	\brief Clear Interrupt Target State
AnnaBridge	153:b484a57bc302	2345	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	153:b484a57bc302	2346	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2347	\return 0 if interrupt is assigned to Secure
AnnaBridge	153:b484a57bc302	2348	1 if interrupt is assigned to Non Secure
AnnaBridge	153:b484a57bc302	2349	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2350	*/
AnnaBridge	153:b484a57bc302	2351	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2352	{
AnnaBridge	153:b484a57bc302	2353	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2354	{
Anna Bridge	169:a7c7b631e539	2355	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge	169:a7c7b631e539	2356	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	153:b484a57bc302	2357	}
AnnaBridge	153:b484a57bc302	2358	else
AnnaBridge	153:b484a57bc302	2359	{
AnnaBridge	153:b484a57bc302	2360	return(0U);
AnnaBridge	153:b484a57bc302	2361	}
AnnaBridge	153:b484a57bc302	2362	}
AnnaBridge	153:b484a57bc302	2363	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	153:b484a57bc302	2364
AnnaBridge	153:b484a57bc302	2365
AnnaBridge	153:b484a57bc302	2366	/**
AnnaBridge	153:b484a57bc302	2367	\brief Set Interrupt Priority
AnnaBridge	153:b484a57bc302	2368	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	153:b484a57bc302	2369	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	153:b484a57bc302	2370	or negative to specify a processor exception.
AnnaBridge	153:b484a57bc302	2371	\param [in] IRQn Interrupt number.
AnnaBridge	153:b484a57bc302	2372	\param [in] priority Priority to set.
AnnaBridge	153:b484a57bc302	2373	\note The priority cannot be set for every processor exception.
AnnaBridge	153:b484a57bc302	2374	*/
AnnaBridge	153:b484a57bc302	2375	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	153:b484a57bc302	2376	{
AnnaBridge	153:b484a57bc302	2377	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2378	{
Anna Bridge	169:a7c7b631e539	2379	NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	153:b484a57bc302	2380	}
AnnaBridge	153:b484a57bc302	2381	else
AnnaBridge	153:b484a57bc302	2382	{
Anna Bridge	169:a7c7b631e539	2383	SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	153:b484a57bc302	2384	}
AnnaBridge	153:b484a57bc302	2385	}
AnnaBridge	153:b484a57bc302	2386
AnnaBridge	153:b484a57bc302	2387
AnnaBridge	153:b484a57bc302	2388	/**
AnnaBridge	153:b484a57bc302	2389	\brief Get Interrupt Priority
AnnaBridge	153:b484a57bc302	2390	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	153:b484a57bc302	2391	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	153:b484a57bc302	2392	or negative to specify a processor exception.
AnnaBridge	153:b484a57bc302	2393	\param [in] IRQn Interrupt number.
AnnaBridge	153:b484a57bc302	2394	\return Interrupt Priority.
AnnaBridge	153:b484a57bc302	2395	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	153:b484a57bc302	2396	*/
AnnaBridge	153:b484a57bc302	2397	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2398	{
AnnaBridge	153:b484a57bc302	2399
AnnaBridge	153:b484a57bc302	2400	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2401	{
Anna Bridge	169:a7c7b631e539	2402	return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	153:b484a57bc302	2403	}
AnnaBridge	153:b484a57bc302	2404	else
AnnaBridge	153:b484a57bc302	2405	{
Anna Bridge	169:a7c7b631e539	2406	return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	153:b484a57bc302	2407	}
AnnaBridge	153:b484a57bc302	2408	}
AnnaBridge	153:b484a57bc302	2409
AnnaBridge	153:b484a57bc302	2410
AnnaBridge	153:b484a57bc302	2411	/**
AnnaBridge	153:b484a57bc302	2412	\brief Encode Priority
AnnaBridge	153:b484a57bc302	2413	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	153:b484a57bc302	2414	preemptive priority value, and subpriority value.
AnnaBridge	153:b484a57bc302	2415	In case of a conflict between priority grouping and available
AnnaBridge	153:b484a57bc302	2416	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	153:b484a57bc302	2417	\param [in] PriorityGroup Used priority group.
AnnaBridge	153:b484a57bc302	2418	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	153:b484a57bc302	2419	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	153:b484a57bc302	2420	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	153:b484a57bc302	2421	*/
AnnaBridge	153:b484a57bc302	2422	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	153:b484a57bc302	2423	{
AnnaBridge	153:b484a57bc302	2424	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	153:b484a57bc302	2425	uint32_t PreemptPriorityBits;
AnnaBridge	153:b484a57bc302	2426	uint32_t SubPriorityBits;
AnnaBridge	153:b484a57bc302	2427
AnnaBridge	153:b484a57bc302	2428	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	153:b484a57bc302	2429	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	153:b484a57bc302	2430
AnnaBridge	153:b484a57bc302	2431	return (
AnnaBridge	153:b484a57bc302	2432	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	153:b484a57bc302	2433	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	153:b484a57bc302	2434	);
AnnaBridge	153:b484a57bc302	2435	}
AnnaBridge	153:b484a57bc302	2436
AnnaBridge	153:b484a57bc302	2437
AnnaBridge	153:b484a57bc302	2438	/**
AnnaBridge	153:b484a57bc302	2439	\brief Decode Priority
AnnaBridge	153:b484a57bc302	2440	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	153:b484a57bc302	2441	preemptive priority value and subpriority value.
AnnaBridge	153:b484a57bc302	2442	In case of a conflict between priority grouping and available
AnnaBridge	153:b484a57bc302	2443	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	153:b484a57bc302	2444	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	153:b484a57bc302	2445	\param [in] PriorityGroup Used priority group.
AnnaBridge	153:b484a57bc302	2446	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	153:b484a57bc302	2447	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	153:b484a57bc302	2448	*/
AnnaBridge	153:b484a57bc302	2449	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge	153:b484a57bc302	2450	{
AnnaBridge	153:b484a57bc302	2451	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	153:b484a57bc302	2452	uint32_t PreemptPriorityBits;
AnnaBridge	153:b484a57bc302	2453	uint32_t SubPriorityBits;
AnnaBridge	153:b484a57bc302	2454
AnnaBridge	153:b484a57bc302	2455	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	153:b484a57bc302	2456	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	153:b484a57bc302	2457
AnnaBridge	153:b484a57bc302	2458	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	153:b484a57bc302	2459	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	153:b484a57bc302	2460	}
AnnaBridge	153:b484a57bc302	2461
AnnaBridge	153:b484a57bc302	2462
AnnaBridge	153:b484a57bc302	2463	/**
AnnaBridge	153:b484a57bc302	2464	\brief Set Interrupt Vector
AnnaBridge	153:b484a57bc302	2465	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	153:b484a57bc302	2466	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	153:b484a57bc302	2467	or negative to specify a processor exception.
AnnaBridge	153:b484a57bc302	2468	VTOR must been relocated to SRAM before.
AnnaBridge	153:b484a57bc302	2469	\param [in] IRQn Interrupt number
AnnaBridge	153:b484a57bc302	2470	\param [in] vector Address of interrupt handler function
AnnaBridge	153:b484a57bc302	2471	*/
AnnaBridge	153:b484a57bc302	2472	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	153:b484a57bc302	2473	{
AnnaBridge	153:b484a57bc302	2474	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	153:b484a57bc302	2475	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	153:b484a57bc302	2476	}
AnnaBridge	153:b484a57bc302	2477
AnnaBridge	153:b484a57bc302	2478
AnnaBridge	153:b484a57bc302	2479	/**
AnnaBridge	153:b484a57bc302	2480	\brief Get Interrupt Vector
AnnaBridge	153:b484a57bc302	2481	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	153:b484a57bc302	2482	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	153:b484a57bc302	2483	or negative to specify a processor exception.
AnnaBridge	153:b484a57bc302	2484	\param [in] IRQn Interrupt number.
AnnaBridge	153:b484a57bc302	2485	\return Address of interrupt handler function
AnnaBridge	153:b484a57bc302	2486	*/
AnnaBridge	153:b484a57bc302	2487	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2488	{
AnnaBridge	153:b484a57bc302	2489	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	153:b484a57bc302	2490	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	153:b484a57bc302	2491	}
AnnaBridge	153:b484a57bc302	2492
AnnaBridge	153:b484a57bc302	2493
AnnaBridge	153:b484a57bc302	2494	/**
AnnaBridge	153:b484a57bc302	2495	\brief System Reset
AnnaBridge	153:b484a57bc302	2496	\details Initiates a system reset request to reset the MCU.
AnnaBridge	153:b484a57bc302	2497	*/
AnnaBridge	153:b484a57bc302	2498	__STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	153:b484a57bc302	2499	{
AnnaBridge	153:b484a57bc302	2500	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	153:b484a57bc302	2501	buffered write are completed before reset */
AnnaBridge	153:b484a57bc302	2502	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	153:b484a57bc302	2503	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
AnnaBridge	153:b484a57bc302	2504	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge	153:b484a57bc302	2505	__DSB(); /* Ensure completion of memory access */
AnnaBridge	153:b484a57bc302	2506
AnnaBridge	153:b484a57bc302	2507	for(;;) /* wait until reset */
AnnaBridge	153:b484a57bc302	2508	{
AnnaBridge	153:b484a57bc302	2509	__NOP();
AnnaBridge	153:b484a57bc302	2510	}
AnnaBridge	153:b484a57bc302	2511	}
AnnaBridge	153:b484a57bc302	2512
AnnaBridge	153:b484a57bc302	2513	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	153:b484a57bc302	2514	/**
AnnaBridge	153:b484a57bc302	2515	\brief Set Priority Grouping (non-secure)
AnnaBridge	153:b484a57bc302	2516	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
AnnaBridge	153:b484a57bc302	2517	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	153:b484a57bc302	2518	Only values from 0..7 are used.
AnnaBridge	153:b484a57bc302	2519	In case of a conflict between priority grouping and available
AnnaBridge	153:b484a57bc302	2520	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	153:b484a57bc302	2521	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	153:b484a57bc302	2522	*/
AnnaBridge	153:b484a57bc302	2523	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
AnnaBridge	153:b484a57bc302	2524	{
AnnaBridge	153:b484a57bc302	2525	uint32_t reg_value;
AnnaBridge	153:b484a57bc302	2526	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	153:b484a57bc302	2527
AnnaBridge	153:b484a57bc302	2528	reg_value = SCB_NS->AIRCR; /* read old register configuration */
AnnaBridge	153:b484a57bc302	2529	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	153:b484a57bc302	2530	reg_value = (reg_value \|
AnnaBridge	153:b484a57bc302	2531	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	153:b484a57bc302	2532	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
AnnaBridge	153:b484a57bc302	2533	SCB_NS->AIRCR = reg_value;
AnnaBridge	153:b484a57bc302	2534	}
AnnaBridge	153:b484a57bc302	2535
AnnaBridge	153:b484a57bc302	2536
AnnaBridge	153:b484a57bc302	2537	/**
AnnaBridge	153:b484a57bc302	2538	\brief Get Priority Grouping (non-secure)
AnnaBridge	153:b484a57bc302	2539	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
AnnaBridge	153:b484a57bc302	2540	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	153:b484a57bc302	2541	*/
AnnaBridge	153:b484a57bc302	2542	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
AnnaBridge	153:b484a57bc302	2543	{
AnnaBridge	153:b484a57bc302	2544	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	153:b484a57bc302	2545	}
AnnaBridge	153:b484a57bc302	2546
AnnaBridge	153:b484a57bc302	2547
AnnaBridge	153:b484a57bc302	2548	/**
AnnaBridge	153:b484a57bc302	2549	\brief Enable Interrupt (non-secure)
AnnaBridge	153:b484a57bc302	2550	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	153:b484a57bc302	2551	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2552	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2553	*/
AnnaBridge	153:b484a57bc302	2554	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2555	{
AnnaBridge	153:b484a57bc302	2556	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2557	{
Anna Bridge	169:a7c7b631e539	2558	NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	153:b484a57bc302	2559	}
AnnaBridge	153:b484a57bc302	2560	}
AnnaBridge	153:b484a57bc302	2561
AnnaBridge	153:b484a57bc302	2562
AnnaBridge	153:b484a57bc302	2563	/**
AnnaBridge	153:b484a57bc302	2564	\brief Get Interrupt Enable status (non-secure)
AnnaBridge	153:b484a57bc302	2565	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	153:b484a57bc302	2566	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2567	\return 0 Interrupt is not enabled.
AnnaBridge	153:b484a57bc302	2568	\return 1 Interrupt is enabled.
AnnaBridge	153:b484a57bc302	2569	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2570	*/
AnnaBridge	153:b484a57bc302	2571	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2572	{
AnnaBridge	153:b484a57bc302	2573	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2574	{
Anna Bridge	169:a7c7b631e539	2575	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	153:b484a57bc302	2576	}
AnnaBridge	153:b484a57bc302	2577	else
AnnaBridge	153:b484a57bc302	2578	{
AnnaBridge	153:b484a57bc302	2579	return(0U);
AnnaBridge	153:b484a57bc302	2580	}
AnnaBridge	153:b484a57bc302	2581	}
AnnaBridge	153:b484a57bc302	2582
AnnaBridge	153:b484a57bc302	2583
AnnaBridge	153:b484a57bc302	2584	/**
AnnaBridge	153:b484a57bc302	2585	\brief Disable Interrupt (non-secure)
AnnaBridge	153:b484a57bc302	2586	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	153:b484a57bc302	2587	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2588	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2589	*/
AnnaBridge	153:b484a57bc302	2590	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2591	{
AnnaBridge	153:b484a57bc302	2592	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2593	{
Anna Bridge	169:a7c7b631e539	2594	NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	153:b484a57bc302	2595	}
AnnaBridge	153:b484a57bc302	2596	}
AnnaBridge	153:b484a57bc302	2597
AnnaBridge	153:b484a57bc302	2598
AnnaBridge	153:b484a57bc302	2599	/**
AnnaBridge	153:b484a57bc302	2600	\brief Get Pending Interrupt (non-secure)
AnnaBridge	153:b484a57bc302	2601	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge	153:b484a57bc302	2602	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2603	\return 0 Interrupt status is not pending.
AnnaBridge	153:b484a57bc302	2604	\return 1 Interrupt status is pending.
AnnaBridge	153:b484a57bc302	2605	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2606	*/
AnnaBridge	153:b484a57bc302	2607	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2608	{
AnnaBridge	153:b484a57bc302	2609	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2610	{
Anna Bridge	169:a7c7b631e539	2611	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	153:b484a57bc302	2612	}
AnnaBridge	153:b484a57bc302	2613	else
AnnaBridge	153:b484a57bc302	2614	{
AnnaBridge	153:b484a57bc302	2615	return(0U);
AnnaBridge	153:b484a57bc302	2616	}
AnnaBridge	153:b484a57bc302	2617	}
AnnaBridge	153:b484a57bc302	2618
AnnaBridge	153:b484a57bc302	2619
AnnaBridge	153:b484a57bc302	2620	/**
AnnaBridge	153:b484a57bc302	2621	\brief Set Pending Interrupt (non-secure)
AnnaBridge	153:b484a57bc302	2622	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	153:b484a57bc302	2623	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2624	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2625	*/
AnnaBridge	153:b484a57bc302	2626	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2627	{
AnnaBridge	153:b484a57bc302	2628	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2629	{
Anna Bridge	169:a7c7b631e539	2630	NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	153:b484a57bc302	2631	}
AnnaBridge	153:b484a57bc302	2632	}
AnnaBridge	153:b484a57bc302	2633
AnnaBridge	153:b484a57bc302	2634
AnnaBridge	153:b484a57bc302	2635	/**
AnnaBridge	153:b484a57bc302	2636	\brief Clear Pending Interrupt (non-secure)
AnnaBridge	153:b484a57bc302	2637	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	153:b484a57bc302	2638	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2639	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2640	*/
AnnaBridge	153:b484a57bc302	2641	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2642	{
AnnaBridge	153:b484a57bc302	2643	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2644	{
Anna Bridge	169:a7c7b631e539	2645	NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	153:b484a57bc302	2646	}
AnnaBridge	153:b484a57bc302	2647	}
AnnaBridge	153:b484a57bc302	2648
AnnaBridge	153:b484a57bc302	2649
AnnaBridge	153:b484a57bc302	2650	/**
AnnaBridge	153:b484a57bc302	2651	\brief Get Active Interrupt (non-secure)
AnnaBridge	153:b484a57bc302	2652	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge	153:b484a57bc302	2653	\param [in] IRQn Device specific interrupt number.
AnnaBridge	153:b484a57bc302	2654	\return 0 Interrupt status is not active.
AnnaBridge	153:b484a57bc302	2655	\return 1 Interrupt status is active.
AnnaBridge	153:b484a57bc302	2656	\note IRQn must not be negative.
AnnaBridge	153:b484a57bc302	2657	*/
AnnaBridge	153:b484a57bc302	2658	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2659	{
AnnaBridge	153:b484a57bc302	2660	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2661	{
Anna Bridge	169:a7c7b631e539	2662	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	153:b484a57bc302	2663	}
AnnaBridge	153:b484a57bc302	2664	else
AnnaBridge	153:b484a57bc302	2665	{
AnnaBridge	153:b484a57bc302	2666	return(0U);
AnnaBridge	153:b484a57bc302	2667	}
AnnaBridge	153:b484a57bc302	2668	}
AnnaBridge	153:b484a57bc302	2669
AnnaBridge	153:b484a57bc302	2670
AnnaBridge	153:b484a57bc302	2671	/**
AnnaBridge	153:b484a57bc302	2672	\brief Set Interrupt Priority (non-secure)
AnnaBridge	153:b484a57bc302	2673	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	153:b484a57bc302	2674	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	153:b484a57bc302	2675	or negative to specify a processor exception.
AnnaBridge	153:b484a57bc302	2676	\param [in] IRQn Interrupt number.
AnnaBridge	153:b484a57bc302	2677	\param [in] priority Priority to set.
AnnaBridge	153:b484a57bc302	2678	\note The priority cannot be set for every non-secure processor exception.
AnnaBridge	153:b484a57bc302	2679	*/
AnnaBridge	153:b484a57bc302	2680	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	153:b484a57bc302	2681	{
AnnaBridge	153:b484a57bc302	2682	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2683	{
Anna Bridge	169:a7c7b631e539	2684	NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	153:b484a57bc302	2685	}
AnnaBridge	153:b484a57bc302	2686	else
AnnaBridge	153:b484a57bc302	2687	{
Anna Bridge	169:a7c7b631e539	2688	SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	153:b484a57bc302	2689	}
AnnaBridge	153:b484a57bc302	2690	}
AnnaBridge	153:b484a57bc302	2691
AnnaBridge	153:b484a57bc302	2692
AnnaBridge	153:b484a57bc302	2693	/**
AnnaBridge	153:b484a57bc302	2694	\brief Get Interrupt Priority (non-secure)
AnnaBridge	153:b484a57bc302	2695	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	153:b484a57bc302	2696	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	153:b484a57bc302	2697	or negative to specify a processor exception.
AnnaBridge	153:b484a57bc302	2698	\param [in] IRQn Interrupt number.
AnnaBridge	153:b484a57bc302	2699	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	153:b484a57bc302	2700	*/
AnnaBridge	153:b484a57bc302	2701	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge	153:b484a57bc302	2702	{
AnnaBridge	153:b484a57bc302	2703
AnnaBridge	153:b484a57bc302	2704	if ((int32_t)(IRQn) >= 0)
AnnaBridge	153:b484a57bc302	2705	{
Anna Bridge	169:a7c7b631e539	2706	return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	153:b484a57bc302	2707	}
AnnaBridge	153:b484a57bc302	2708	else
AnnaBridge	153:b484a57bc302	2709	{
Anna Bridge	169:a7c7b631e539	2710	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	153:b484a57bc302	2711	}
AnnaBridge	153:b484a57bc302	2712	}
AnnaBridge	153:b484a57bc302	2713	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	153:b484a57bc302	2714
AnnaBridge	153:b484a57bc302	2715	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	153:b484a57bc302	2716
Anna Bridge	160:5571c4ff569f	2717	/* ########################## MPU functions #################################### */
Anna Bridge	160:5571c4ff569f	2718
Anna Bridge	160:5571c4ff569f	2719	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	2720
Anna Bridge	160:5571c4ff569f	2721	#include "mpu_armv8.h"
Anna Bridge	160:5571c4ff569f	2722
Anna Bridge	160:5571c4ff569f	2723	#endif
AnnaBridge	153:b484a57bc302	2724
AnnaBridge	153:b484a57bc302	2725	/* ########################## FPU functions #################################### */
AnnaBridge	153:b484a57bc302	2726	/**
AnnaBridge	153:b484a57bc302	2727	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	153:b484a57bc302	2728	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	153:b484a57bc302	2729	\brief Function that provides FPU type.
AnnaBridge	153:b484a57bc302	2730	@{
AnnaBridge	153:b484a57bc302	2731	*/
AnnaBridge	153:b484a57bc302	2732
AnnaBridge	153:b484a57bc302	2733	/**
AnnaBridge	153:b484a57bc302	2734	\brief get FPU type
AnnaBridge	153:b484a57bc302	2735	\details returns the FPU type
AnnaBridge	153:b484a57bc302	2736	\returns
AnnaBridge	153:b484a57bc302	2737	- \b 0: No FPU
AnnaBridge	153:b484a57bc302	2738	- \b 1: Single precision FPU
AnnaBridge	153:b484a57bc302	2739	- \b 2: Double + Single precision FPU
AnnaBridge	153:b484a57bc302	2740	*/
AnnaBridge	153:b484a57bc302	2741	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	153:b484a57bc302	2742	{
AnnaBridge	153:b484a57bc302	2743	uint32_t mvfr0;
AnnaBridge	153:b484a57bc302	2744
AnnaBridge	153:b484a57bc302	2745	mvfr0 = FPU->MVFR0;
AnnaBridge	153:b484a57bc302	2746	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
AnnaBridge	153:b484a57bc302	2747	{
AnnaBridge	153:b484a57bc302	2748	return 2U; /* Double + Single precision FPU */
AnnaBridge	153:b484a57bc302	2749	}
AnnaBridge	153:b484a57bc302	2750	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge	153:b484a57bc302	2751	{
AnnaBridge	153:b484a57bc302	2752	return 1U; /* Single precision FPU */
AnnaBridge	153:b484a57bc302	2753	}
AnnaBridge	153:b484a57bc302	2754	else
AnnaBridge	153:b484a57bc302	2755	{
AnnaBridge	153:b484a57bc302	2756	return 0U; /* No FPU */
AnnaBridge	153:b484a57bc302	2757	}
AnnaBridge	153:b484a57bc302	2758	}
AnnaBridge	153:b484a57bc302	2759
AnnaBridge	153:b484a57bc302	2760
AnnaBridge	153:b484a57bc302	2761	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	153:b484a57bc302	2762
AnnaBridge	153:b484a57bc302	2763
AnnaBridge	153:b484a57bc302	2764
AnnaBridge	153:b484a57bc302	2765	/* ########################## SAU functions #################################### */
AnnaBridge	153:b484a57bc302	2766	/**
AnnaBridge	153:b484a57bc302	2767	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	153:b484a57bc302	2768	\defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge	153:b484a57bc302	2769	\brief Functions that configure the SAU.
AnnaBridge	153:b484a57bc302	2770	@{
AnnaBridge	153:b484a57bc302	2771	*/
AnnaBridge	153:b484a57bc302	2772
AnnaBridge	153:b484a57bc302	2773	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	153:b484a57bc302	2774
AnnaBridge	153:b484a57bc302	2775	/**
AnnaBridge	153:b484a57bc302	2776	\brief Enable SAU
AnnaBridge	153:b484a57bc302	2777	\details Enables the Security Attribution Unit (SAU).
AnnaBridge	153:b484a57bc302	2778	*/
AnnaBridge	153:b484a57bc302	2779	__STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge	153:b484a57bc302	2780	{
AnnaBridge	153:b484a57bc302	2781	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
AnnaBridge	153:b484a57bc302	2782	}
AnnaBridge	153:b484a57bc302	2783
AnnaBridge	153:b484a57bc302	2784
AnnaBridge	153:b484a57bc302	2785
AnnaBridge	153:b484a57bc302	2786	/**
AnnaBridge	153:b484a57bc302	2787	\brief Disable SAU
AnnaBridge	153:b484a57bc302	2788	\details Disables the Security Attribution Unit (SAU).
AnnaBridge	153:b484a57bc302	2789	*/
AnnaBridge	153:b484a57bc302	2790	__STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge	153:b484a57bc302	2791	{
AnnaBridge	153:b484a57bc302	2792	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge	153:b484a57bc302	2793	}
AnnaBridge	153:b484a57bc302	2794
AnnaBridge	153:b484a57bc302	2795	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	153:b484a57bc302	2796
AnnaBridge	153:b484a57bc302	2797	/@} end of CMSIS_Core_SAUFunctions /
AnnaBridge	153:b484a57bc302	2798
AnnaBridge	153:b484a57bc302	2799
AnnaBridge	153:b484a57bc302	2800
AnnaBridge	153:b484a57bc302	2801
AnnaBridge	153:b484a57bc302	2802	/* ################################## SysTick function ############################################ */
AnnaBridge	153:b484a57bc302	2803	/**
AnnaBridge	153:b484a57bc302	2804	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	153:b484a57bc302	2805	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	153:b484a57bc302	2806	\brief Functions that configure the System.
AnnaBridge	153:b484a57bc302	2807	@{
AnnaBridge	153:b484a57bc302	2808	*/
AnnaBridge	153:b484a57bc302	2809
AnnaBridge	153:b484a57bc302	2810	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	153:b484a57bc302	2811
AnnaBridge	153:b484a57bc302	2812	/**
AnnaBridge	153:b484a57bc302	2813	\brief System Tick Configuration
AnnaBridge	153:b484a57bc302	2814	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	153:b484a57bc302	2815	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	153:b484a57bc302	2816	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	153:b484a57bc302	2817	\return 0 Function succeeded.
AnnaBridge	153:b484a57bc302	2818	\return 1 Function failed.
AnnaBridge	153:b484a57bc302	2819	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	153:b484a57bc302	2820	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	153:b484a57bc302	2821	must contain a vendor-specific implementation of this function.
AnnaBridge	153:b484a57bc302	2822	*/
AnnaBridge	153:b484a57bc302	2823	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	153:b484a57bc302	2824	{
AnnaBridge	153:b484a57bc302	2825	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	153:b484a57bc302	2826	{
AnnaBridge	153:b484a57bc302	2827	return (1UL); /* Reload value impossible */
AnnaBridge	153:b484a57bc302	2828	}
AnnaBridge	153:b484a57bc302	2829
AnnaBridge	153:b484a57bc302	2830	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	153:b484a57bc302	2831	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	153:b484a57bc302	2832	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	153:b484a57bc302	2833	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	153:b484a57bc302	2834	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	153:b484a57bc302	2835	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	153:b484a57bc302	2836	return (0UL); /* Function successful */
AnnaBridge	153:b484a57bc302	2837	}
AnnaBridge	153:b484a57bc302	2838
AnnaBridge	153:b484a57bc302	2839	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	153:b484a57bc302	2840	/**
AnnaBridge	153:b484a57bc302	2841	\brief System Tick Configuration (non-secure)
AnnaBridge	153:b484a57bc302	2842	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge	153:b484a57bc302	2843	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	153:b484a57bc302	2844	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	153:b484a57bc302	2845	\return 0 Function succeeded.
AnnaBridge	153:b484a57bc302	2846	\return 1 Function failed.
AnnaBridge	153:b484a57bc302	2847	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	153:b484a57bc302	2848	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	153:b484a57bc302	2849	must contain a vendor-specific implementation of this function.
AnnaBridge	153:b484a57bc302	2850
AnnaBridge	153:b484a57bc302	2851	*/
AnnaBridge	153:b484a57bc302	2852	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge	153:b484a57bc302	2853	{
AnnaBridge	153:b484a57bc302	2854	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	153:b484a57bc302	2855	{
AnnaBridge	153:b484a57bc302	2856	return (1UL); /* Reload value impossible */
AnnaBridge	153:b484a57bc302	2857	}
AnnaBridge	153:b484a57bc302	2858
AnnaBridge	153:b484a57bc302	2859	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	153:b484a57bc302	2860	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	153:b484a57bc302	2861	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	153:b484a57bc302	2862	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	153:b484a57bc302	2863	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	153:b484a57bc302	2864	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	153:b484a57bc302	2865	return (0UL); /* Function successful */
AnnaBridge	153:b484a57bc302	2866	}
AnnaBridge	153:b484a57bc302	2867	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	153:b484a57bc302	2868
AnnaBridge	153:b484a57bc302	2869	#endif
AnnaBridge	153:b484a57bc302	2870
AnnaBridge	153:b484a57bc302	2871	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	153:b484a57bc302	2872
AnnaBridge	153:b484a57bc302	2873
AnnaBridge	153:b484a57bc302	2874
AnnaBridge	153:b484a57bc302	2875	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	153:b484a57bc302	2876	/**
AnnaBridge	153:b484a57bc302	2877	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	153:b484a57bc302	2878	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	153:b484a57bc302	2879	\brief Functions that access the ITM debug interface.
AnnaBridge	153:b484a57bc302	2880	@{
AnnaBridge	153:b484a57bc302	2881	*/
AnnaBridge	153:b484a57bc302	2882
AnnaBridge	153:b484a57bc302	2883	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	153:b484a57bc302	2884	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
AnnaBridge	153:b484a57bc302	2885
AnnaBridge	153:b484a57bc302	2886
AnnaBridge	153:b484a57bc302	2887	/**
AnnaBridge	153:b484a57bc302	2888	\brief ITM Send Character
AnnaBridge	153:b484a57bc302	2889	\details Transmits a character via the ITM channel 0, and
AnnaBridge	153:b484a57bc302	2890	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	153:b484a57bc302	2891	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	153:b484a57bc302	2892	\param [in] ch Character to transmit.
AnnaBridge	153:b484a57bc302	2893	\returns Character to transmit.
AnnaBridge	153:b484a57bc302	2894	*/
AnnaBridge	153:b484a57bc302	2895	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge	153:b484a57bc302	2896	{
AnnaBridge	153:b484a57bc302	2897	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge	153:b484a57bc302	2898	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge	153:b484a57bc302	2899	{
AnnaBridge	153:b484a57bc302	2900	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	153:b484a57bc302	2901	{
AnnaBridge	153:b484a57bc302	2902	__NOP();
AnnaBridge	153:b484a57bc302	2903	}
AnnaBridge	153:b484a57bc302	2904	ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge	153:b484a57bc302	2905	}
AnnaBridge	153:b484a57bc302	2906	return (ch);
AnnaBridge	153:b484a57bc302	2907	}
AnnaBridge	153:b484a57bc302	2908
AnnaBridge	153:b484a57bc302	2909
AnnaBridge	153:b484a57bc302	2910	/**
AnnaBridge	153:b484a57bc302	2911	\brief ITM Receive Character
AnnaBridge	153:b484a57bc302	2912	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	153:b484a57bc302	2913	\return Received character.
AnnaBridge	153:b484a57bc302	2914	\return -1 No character pending.
AnnaBridge	153:b484a57bc302	2915	*/
AnnaBridge	153:b484a57bc302	2916	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	153:b484a57bc302	2917	{
AnnaBridge	153:b484a57bc302	2918	int32_t ch = -1; /* no character available */
AnnaBridge	153:b484a57bc302	2919
AnnaBridge	153:b484a57bc302	2920	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	153:b484a57bc302	2921	{
AnnaBridge	153:b484a57bc302	2922	ch = ITM_RxBuffer;
AnnaBridge	153:b484a57bc302	2923	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge	153:b484a57bc302	2924	}
AnnaBridge	153:b484a57bc302	2925
AnnaBridge	153:b484a57bc302	2926	return (ch);
AnnaBridge	153:b484a57bc302	2927	}
AnnaBridge	153:b484a57bc302	2928
AnnaBridge	153:b484a57bc302	2929
AnnaBridge	153:b484a57bc302	2930	/**
AnnaBridge	153:b484a57bc302	2931	\brief ITM Check Character
AnnaBridge	153:b484a57bc302	2932	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	153:b484a57bc302	2933	\return 0 No character available.
AnnaBridge	153:b484a57bc302	2934	\return 1 Character available.
AnnaBridge	153:b484a57bc302	2935	*/
AnnaBridge	153:b484a57bc302	2936	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	153:b484a57bc302	2937	{
AnnaBridge	153:b484a57bc302	2938
AnnaBridge	153:b484a57bc302	2939	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	153:b484a57bc302	2940	{
AnnaBridge	153:b484a57bc302	2941	return (0); /* no character available */
AnnaBridge	153:b484a57bc302	2942	}
AnnaBridge	153:b484a57bc302	2943	else
AnnaBridge	153:b484a57bc302	2944	{
AnnaBridge	153:b484a57bc302	2945	return (1); /* character available */
AnnaBridge	153:b484a57bc302	2946	}
AnnaBridge	153:b484a57bc302	2947	}
AnnaBridge	153:b484a57bc302	2948
AnnaBridge	153:b484a57bc302	2949	/@} end of CMSIS_core_DebugFunctions /
AnnaBridge	153:b484a57bc302	2950
AnnaBridge	153:b484a57bc302	2951
AnnaBridge	153:b484a57bc302	2952
AnnaBridge	153:b484a57bc302	2953
AnnaBridge	153:b484a57bc302	2954	#ifdef __cplusplus
AnnaBridge	153:b484a57bc302	2955	}
AnnaBridge	153:b484a57bc302	2956	#endif
AnnaBridge	153:b484a57bc302	2957
AnnaBridge	153:b484a57bc302	2958	#endif /* __CORE_ARMV8MML_H_DEPENDANT */
AnnaBridge	153:b484a57bc302	2959
AnnaBridge	153:b484a57bc302	2960	#endif /* __CMSIS_GENERIC */