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TARGET_LPC1549/TARGET_NXP/TARGET_LPC15XX/device/LPC15xx.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:: AnnaBridge
Date:: Thu Sep 06 13:39:34 2018 +0100
Revision:: 170:e95d10626187
Parent:: 128:9bcdf88f62b0

mbed library. Release version 163

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	128:9bcdf88f62b0	1
<>	128:9bcdf88f62b0	2	/**************************************************************************************************//
<>	128:9bcdf88f62b0	3	* @file LPC15xx.h
<>	128:9bcdf88f62b0	4	*
<>	128:9bcdf88f62b0	5	* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
<>	128:9bcdf88f62b0	6	* LPC15xx from .
<>	128:9bcdf88f62b0	7	*
<>	128:9bcdf88f62b0	8	* @version V0.3
<>	128:9bcdf88f62b0	9	* @date 17. July 2013
<>	128:9bcdf88f62b0	10	*
<>	128:9bcdf88f62b0	11	* @note Generated with SVDConv V2.80
<>	128:9bcdf88f62b0	12	* from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
<>	128:9bcdf88f62b0	13	*
<>	128:9bcdf88f62b0	14	* modified by Keil
<>	128:9bcdf88f62b0	15	* modified by ytsuboi
<>	128:9bcdf88f62b0	16	*******************************************************************************************************/
<>	128:9bcdf88f62b0	17
<>	128:9bcdf88f62b0	18
<>	128:9bcdf88f62b0	19
<>	128:9bcdf88f62b0	20	/** @addtogroup (null)
<>	128:9bcdf88f62b0	21	* @{
<>	128:9bcdf88f62b0	22	*/
<>	128:9bcdf88f62b0	23
<>	128:9bcdf88f62b0	24	/** @addtogroup LPC15xx
<>	128:9bcdf88f62b0	25	* @{
<>	128:9bcdf88f62b0	26	*/
<>	128:9bcdf88f62b0	27
<>	128:9bcdf88f62b0	28	#ifndef LPC15XX_H
<>	128:9bcdf88f62b0	29	#define LPC15XX_H
<>	128:9bcdf88f62b0	30
<>	128:9bcdf88f62b0	31	#ifdef __cplusplus
<>	128:9bcdf88f62b0	32	extern "C" {
<>	128:9bcdf88f62b0	33	#endif
<>	128:9bcdf88f62b0	34
<>	128:9bcdf88f62b0	35
<>	128:9bcdf88f62b0	36	/* ------------------------- Interrupt Number Definition ------------------------ */
<>	128:9bcdf88f62b0	37
<>	128:9bcdf88f62b0	38	typedef enum {
<>	128:9bcdf88f62b0	39	/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
<>	128:9bcdf88f62b0	40	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
<>	128:9bcdf88f62b0	41	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
<>	128:9bcdf88f62b0	42	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
<>	128:9bcdf88f62b0	43	MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
<>	128:9bcdf88f62b0	44	and No Match */
<>	128:9bcdf88f62b0	45	BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
<>	128:9bcdf88f62b0	46	related Fault */
<>	128:9bcdf88f62b0	47	UsageFault_IRQn = -10, /!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition /
<>	128:9bcdf88f62b0	48	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
<>	128:9bcdf88f62b0	49	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
<>	128:9bcdf88f62b0	50	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
<>	128:9bcdf88f62b0	51	SysTick_IRQn = -1, /!< 15 System Tick Timer /
<>	128:9bcdf88f62b0	52	/* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
<>	128:9bcdf88f62b0	53	WDT_IRQn = 0, /!< 0 WDT /
<>	128:9bcdf88f62b0	54	BOD_IRQn = 1, /!< 1 BOD /
<>	128:9bcdf88f62b0	55	FLASH_IRQn = 2, /!< 2 FLASH /
<>	128:9bcdf88f62b0	56	EE_IRQn = 3, /!< 3 EE /
<>	128:9bcdf88f62b0	57	DMA_IRQn = 4, /!< 4 DMA /
<>	128:9bcdf88f62b0	58	GINT0_IRQn = 5, /!< 5 GINT0 /
<>	128:9bcdf88f62b0	59	GINT1_IRQn = 6, /!< 6 GINT1 /
<>	128:9bcdf88f62b0	60	PIN_INT0_IRQn = 7, /!< 7 PIN_INT0 /
<>	128:9bcdf88f62b0	61	PIN_INT1_IRQn = 8, /!< 8 PIN_INT1 /
<>	128:9bcdf88f62b0	62	PIN_INT2_IRQn = 9, /!< 9 PIN_INT2 /
<>	128:9bcdf88f62b0	63	PIN_INT3_IRQn = 10, /!< 10 PIN_INT3 /
<>	128:9bcdf88f62b0	64	PIN_INT4_IRQn = 11, /!< 11 PIN_INT4 /
<>	128:9bcdf88f62b0	65	PIN_INT5_IRQn = 12, /!< 12 PIN_INT5 /
<>	128:9bcdf88f62b0	66	PIN_INT6_IRQn = 13, /!< 13 PIN_INT6 /
<>	128:9bcdf88f62b0	67	PIN_INT7_IRQn = 14, /!< 14 PIN_INT7 /
<>	128:9bcdf88f62b0	68	RIT_IRQn = 15, /!< 15 RIT /
<>	128:9bcdf88f62b0	69	SCT0_IRQn = 16, /!< 16 SCT0 /
<>	128:9bcdf88f62b0	70	SCT1_IRQn = 17, /!< 17 SCT1 /
<>	128:9bcdf88f62b0	71	SCT2_IRQn = 18, /!< 18 SCT2 /
<>	128:9bcdf88f62b0	72	SCT3_IRQn = 19, /!< 19 SCT3 /
<>	128:9bcdf88f62b0	73	MRT_IRQn = 20, /!< 20 MRT /
<>	128:9bcdf88f62b0	74	UART0_IRQn = 21, /!< 21 UART0 /
<>	128:9bcdf88f62b0	75	UART1_IRQn = 22, /!< 22 UART1 /
<>	128:9bcdf88f62b0	76	UART2_IRQn = 23, /!< 23 UART2 /
<>	128:9bcdf88f62b0	77	I2C0_IRQn = 24, /!< 24 I2C0 /
<>	128:9bcdf88f62b0	78	SPI0_IRQn = 25, /!< 25 SPI0 /
<>	128:9bcdf88f62b0	79	SPI1_IRQn = 26, /!< 26 SPI1 /
<>	128:9bcdf88f62b0	80	C_CAN0_IRQn = 27, /!< 27 C_CAN0 /
<>	128:9bcdf88f62b0	81	USB_IRQ_IRQn = 28, /!< 28 USB_IRQ /
<>	128:9bcdf88f62b0	82	USB_FIQ_IRQn = 29, /!< 29 USB_FIQ /
<>	128:9bcdf88f62b0	83	USBWAKEUP_IRQn = 30, /!< 30 USBWAKEUP /
<>	128:9bcdf88f62b0	84	ADC0_SEQA_IRQn = 31, /!< 31 ADC0_SEQA /
<>	128:9bcdf88f62b0	85	ADC0_SEQB_IRQn = 32, /!< 32 ADC0_SEQB /
<>	128:9bcdf88f62b0	86	ADC0_THCMP_IRQn = 33, /!< 33 ADC0_THCMP /
<>	128:9bcdf88f62b0	87	ADC0_OVR_IRQn = 34, /!< 34 ADC0_OVR /
<>	128:9bcdf88f62b0	88	ADC1_SEQA_IRQn = 35, /!< 35 ADC1_SEQA /
<>	128:9bcdf88f62b0	89	ADC1_SEQB_IRQn = 36, /!< 36 ADC1_SEQB /
<>	128:9bcdf88f62b0	90	ADC1_THCMP_IRQn = 37, /!< 37 ADC1_THCMP /
<>	128:9bcdf88f62b0	91	ADC1_OVR_IRQn = 38, /!< 38 ADC1_OVR /
<>	128:9bcdf88f62b0	92	DAC_IRQn = 39, /!< 39 DAC /
<>	128:9bcdf88f62b0	93	CMP0_IRQn = 40, /!< 40 CMP0 /
<>	128:9bcdf88f62b0	94	CMP1_IRQn = 41, /!< 41 CMP1 /
<>	128:9bcdf88f62b0	95	CMP2_IRQn = 42, /!< 42 CMP2 /
<>	128:9bcdf88f62b0	96	CMP3_IRQn = 43, /!< 43 CMP3 /
<>	128:9bcdf88f62b0	97	QEI_IRQn = 44, /!< 44 QEI /
<>	128:9bcdf88f62b0	98	RTC_ALARM_IRQn = 45, /!< 45 RTC_ALARM /
<>	128:9bcdf88f62b0	99	RTC_WAKE_IRQn = 46 /!< 46 RTC_WAKE /
<>	128:9bcdf88f62b0	100	} IRQn_Type;
<>	128:9bcdf88f62b0	101
<>	128:9bcdf88f62b0	102
<>	128:9bcdf88f62b0	103	/** @addtogroup Configuration_of_CMSIS
<>	128:9bcdf88f62b0	104	* @{
<>	128:9bcdf88f62b0	105	*/
<>	128:9bcdf88f62b0	106
<>	128:9bcdf88f62b0	107
<>	128:9bcdf88f62b0	108	/* ================================================================================ */
<>	128:9bcdf88f62b0	109	/* ================ Processor and Core Peripheral Section ================ */
<>	128:9bcdf88f62b0	110	/* ================================================================================ */
<>	128:9bcdf88f62b0	111
<>	128:9bcdf88f62b0	112	/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
<>	128:9bcdf88f62b0	113	#define __CM3_REV 0x0201 /!< Cortex-M3 Core Revision /
<>	128:9bcdf88f62b0	114	#define __MPU_PRESENT 0 /!< MPU present or not /
<>	128:9bcdf88f62b0	115	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
<>	128:9bcdf88f62b0	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
<>	128:9bcdf88f62b0	117	/** @} / / End of group Configuration_of_CMSIS */
<>	128:9bcdf88f62b0	118
<>	128:9bcdf88f62b0	119	#include "core_cm3.h" /!< Cortex-M3 processor and core peripherals /
<>	128:9bcdf88f62b0	120	#include "system_LPC15xx.h" /!< LPC15xx System /
<>	128:9bcdf88f62b0	121
<>	128:9bcdf88f62b0	122
<>	128:9bcdf88f62b0	123	/* ================================================================================ */
<>	128:9bcdf88f62b0	124	/* ================ Device Specific Peripheral Section ================ */
<>	128:9bcdf88f62b0	125	/* ================================================================================ */
<>	128:9bcdf88f62b0	126
<>	128:9bcdf88f62b0	127
<>	128:9bcdf88f62b0	128	/** @addtogroup Device_Peripheral_Registers
<>	128:9bcdf88f62b0	129	* @{
<>	128:9bcdf88f62b0	130	*/
<>	128:9bcdf88f62b0	131
<>	128:9bcdf88f62b0	132
<>	128:9bcdf88f62b0	133	/* ------------------- Start of section using anonymous unions ------------------ */
<>	128:9bcdf88f62b0	134	#if defined(__CC_ARM)
<>	128:9bcdf88f62b0	135	#pragma push
<>	128:9bcdf88f62b0	136	#pragma anon_unions
<>	128:9bcdf88f62b0	137	#elif defined(__ICCARM__)
<>	128:9bcdf88f62b0	138	#pragma language=extended
<>	128:9bcdf88f62b0	139	#elif defined(__GNUC__)
<>	128:9bcdf88f62b0	140	/* anonymous unions are enabled by default */
<>	128:9bcdf88f62b0	141	#elif defined(__TMS470__)
<>	128:9bcdf88f62b0	142	/* anonymous unions are enabled by default */
<>	128:9bcdf88f62b0	143	#elif defined(__TASKING__)
<>	128:9bcdf88f62b0	144	#pragma warning 586
<>	128:9bcdf88f62b0	145	#else
<>	128:9bcdf88f62b0	146	#warning Not supported compiler type
<>	128:9bcdf88f62b0	147	#endif
<>	128:9bcdf88f62b0	148
<>	128:9bcdf88f62b0	149
<>	128:9bcdf88f62b0	150
<>	128:9bcdf88f62b0	151	/* ================================================================================ */
<>	128:9bcdf88f62b0	152	/* ================ GPIO_PORT ================ */
<>	128:9bcdf88f62b0	153	/* ================================================================================ */
<>	128:9bcdf88f62b0	154
<>	128:9bcdf88f62b0	155
<>	128:9bcdf88f62b0	156	/**
<>	128:9bcdf88f62b0	157	* @brief General Purpose I/O (GPIO) (GPIO_PORT)
<>	128:9bcdf88f62b0	158	*/
<>	128:9bcdf88f62b0	159
<>	128:9bcdf88f62b0	160	typedef struct { /!< GPIO_PORT Structure /
<>	128:9bcdf88f62b0	161	__IO uint8_t B[76]; /!< Byte pin registers /
<>	128:9bcdf88f62b0	162	__I uint32_t RESERVED0[1005];
<>	128:9bcdf88f62b0	163	__IO uint32_t W[76]; /!< Word pin registers /
<>	128:9bcdf88f62b0	164	__I uint32_t RESERVED1[948];
<>	128:9bcdf88f62b0	165	__IO uint32_t DIR[3]; /!< Port Direction registers /
<>	128:9bcdf88f62b0	166	__I uint32_t RESERVED2[29];
<>	128:9bcdf88f62b0	167	__IO uint32_t MASK[3]; /!< Port Mask register /
<>	128:9bcdf88f62b0	168	__I uint32_t RESERVED3[29];
<>	128:9bcdf88f62b0	169	__IO uint32_t PIN[3]; /!< Port pin register /
<>	128:9bcdf88f62b0	170	__I uint32_t RESERVED4[29];
<>	128:9bcdf88f62b0	171	__IO uint32_t MPIN[3]; /!< Masked port register /
<>	128:9bcdf88f62b0	172	__I uint32_t RESERVED5[29];
<>	128:9bcdf88f62b0	173	__IO uint32_t SET[3]; /!< Write: Set port register Read: port output bits /
<>	128:9bcdf88f62b0	174	__I uint32_t RESERVED6[29];
<>	128:9bcdf88f62b0	175	__O uint32_t CLR[3]; /!< Clear port /
<>	128:9bcdf88f62b0	176	__I uint32_t RESERVED7[29];
<>	128:9bcdf88f62b0	177	__O uint32_t NOT[3]; /!< Toggle port /
<>	128:9bcdf88f62b0	178	} LPC_GPIO_PORT_Type;
<>	128:9bcdf88f62b0	179
<>	128:9bcdf88f62b0	180
<>	128:9bcdf88f62b0	181	/* ================================================================================ */
<>	128:9bcdf88f62b0	182	/* ================ DMA ================ */
<>	128:9bcdf88f62b0	183	/* ================================================================================ */
<>	128:9bcdf88f62b0	184
<>	128:9bcdf88f62b0	185
<>	128:9bcdf88f62b0	186	/**
<>	128:9bcdf88f62b0	187	* @brief DMA controller (DMA)
<>	128:9bcdf88f62b0	188	*/
<>	128:9bcdf88f62b0	189
<>	128:9bcdf88f62b0	190	typedef struct { /!< DMA Structure /
<>	128:9bcdf88f62b0	191	__IO uint32_t CTRL; /!< DMA control. /
<>	128:9bcdf88f62b0	192	__I uint32_t INTSTAT; /!< Interrupt status. /
<>	128:9bcdf88f62b0	193	__IO uint32_t SRAMBASE; /!< SRAM address of the channel configuration table. /
<>	128:9bcdf88f62b0	194	__I uint32_t RESERVED0[5];
<>	128:9bcdf88f62b0	195	__IO uint32_t ENABLESET0; /!< Channel Enable read and Set for all DMA channels. /
<>	128:9bcdf88f62b0	196	__I uint32_t RESERVED1;
<>	128:9bcdf88f62b0	197	__O uint32_t ENABLECLR0; /!< Channel Enable Clear for all DMA channels. /
<>	128:9bcdf88f62b0	198	__I uint32_t RESERVED2;
<>	128:9bcdf88f62b0	199	__I uint32_t ACTIVE0; /!< Channel Active status for all DMA channels. /
<>	128:9bcdf88f62b0	200	__I uint32_t RESERVED3;
<>	128:9bcdf88f62b0	201	__I uint32_t BUSY0; /!< Channel Busy status for all DMA channels. /
<>	128:9bcdf88f62b0	202	__I uint32_t RESERVED4;
<>	128:9bcdf88f62b0	203	__IO uint32_t ERRINT0; /!< Error Interrupt status for all DMA channels. /
<>	128:9bcdf88f62b0	204	__I uint32_t RESERVED5;
<>	128:9bcdf88f62b0	205	__IO uint32_t INTENSET0; /!< Interrupt Enable read and Set for all DMA channels. /
<>	128:9bcdf88f62b0	206	__I uint32_t RESERVED6;
<>	128:9bcdf88f62b0	207	__O uint32_t INTENCLR0; /!< Interrupt Enable Clear for all DMA channels. /
<>	128:9bcdf88f62b0	208	__I uint32_t RESERVED7;
<>	128:9bcdf88f62b0	209	__IO uint32_t INTA0; /!< Interrupt A status for all DMA channels. /
<>	128:9bcdf88f62b0	210	__I uint32_t RESERVED8;
<>	128:9bcdf88f62b0	211	__IO uint32_t INTB0; /!< Interrupt B status for all DMA channels. /
<>	128:9bcdf88f62b0	212	__I uint32_t RESERVED9;
<>	128:9bcdf88f62b0	213	__O uint32_t SETVALID0; /!< Set ValidPending control bits for all DMA channels. /
<>	128:9bcdf88f62b0	214	__I uint32_t RESERVED10;
<>	128:9bcdf88f62b0	215	__O uint32_t SETTRIG0; /!< Set Trigger control bits for all DMA channels. /
<>	128:9bcdf88f62b0	216	__I uint32_t RESERVED11;
<>	128:9bcdf88f62b0	217	__O uint32_t ABORT0; /!< Channel Abort control for all DMA channels. /
<>	128:9bcdf88f62b0	218	__I uint32_t RESERVED12[225];
<>	128:9bcdf88f62b0	219	__IO uint32_t CFG0; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	220	__I uint32_t CTLSTAT0; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	221	__IO uint32_t XFERCFG0; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	222	__I uint32_t RESERVED13;
<>	128:9bcdf88f62b0	223	__IO uint32_t CFG1; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	224	__I uint32_t CTLSTAT1; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	225	__IO uint32_t XFERCFG1; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	226	__I uint32_t RESERVED14;
<>	128:9bcdf88f62b0	227	__IO uint32_t CFG2; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	228	__I uint32_t CTLSTAT2; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	229	__IO uint32_t XFERCFG2; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	230	__I uint32_t RESERVED15;
<>	128:9bcdf88f62b0	231	__IO uint32_t CFG3; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	232	__I uint32_t CTLSTAT3; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	233	__IO uint32_t XFERCFG3; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	234	__I uint32_t RESERVED16;
<>	128:9bcdf88f62b0	235	__IO uint32_t CFG4; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	236	__I uint32_t CTLSTAT4; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	237	__IO uint32_t XFERCFG4; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	238	__I uint32_t RESERVED17;
<>	128:9bcdf88f62b0	239	__IO uint32_t CFG5; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	240	__I uint32_t CTLSTAT5; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	241	__IO uint32_t XFERCFG5; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	242	__I uint32_t RESERVED18;
<>	128:9bcdf88f62b0	243	__IO uint32_t CFG6; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	244	__I uint32_t CTLSTAT6; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	245	__IO uint32_t XFERCFG6; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	246	__I uint32_t RESERVED19;
<>	128:9bcdf88f62b0	247	__IO uint32_t CFG7; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	248	__I uint32_t CTLSTAT7; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	249	__IO uint32_t XFERCFG7; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	250	__I uint32_t RESERVED20;
<>	128:9bcdf88f62b0	251	__IO uint32_t CFG8; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	252	__I uint32_t CTLSTAT8; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	253	__IO uint32_t XFERCFG8; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	254	__I uint32_t RESERVED21;
<>	128:9bcdf88f62b0	255	__IO uint32_t CFG9; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	256	__I uint32_t CTLSTAT9; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	257	__IO uint32_t XFERCFG9; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	258	__I uint32_t RESERVED22;
<>	128:9bcdf88f62b0	259	__IO uint32_t CFG10; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	260	__I uint32_t CTLSTAT10; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	261	__IO uint32_t XFERCFG10; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	262	__I uint32_t RESERVED23;
<>	128:9bcdf88f62b0	263	__IO uint32_t CFG11; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	264	__I uint32_t CTLSTAT11; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	265	__IO uint32_t XFERCFG11; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	266	__I uint32_t RESERVED24;
<>	128:9bcdf88f62b0	267	__IO uint32_t CFG12; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	268	__I uint32_t CTLSTAT12; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	269	__IO uint32_t XFERCFG12; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	270	__I uint32_t RESERVED25;
<>	128:9bcdf88f62b0	271	__IO uint32_t CFG13; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	272	__I uint32_t CTLSTAT13; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	273	__IO uint32_t XFERCFG13; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	274	__I uint32_t RESERVED26;
<>	128:9bcdf88f62b0	275	__IO uint32_t CFG14; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	276	__I uint32_t CTLSTAT14; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	277	__IO uint32_t XFERCFG14; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	278	__I uint32_t RESERVED27;
<>	128:9bcdf88f62b0	279	__IO uint32_t CFG15; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	280	__I uint32_t CTLSTAT15; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	281	__IO uint32_t XFERCFG15; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	282	__I uint32_t RESERVED28;
<>	128:9bcdf88f62b0	283	__IO uint32_t CFG16; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	284	__I uint32_t CTLSTAT16; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	285	__IO uint32_t XFERCFG16; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	286	__I uint32_t RESERVED29;
<>	128:9bcdf88f62b0	287	__IO uint32_t CFG17; /!< Configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	288	__I uint32_t CTLSTAT17; /!< Control and status register for DMA channel 0. /
<>	128:9bcdf88f62b0	289	__IO uint32_t XFERCFG17; /!< Transfer configuration register for DMA channel 0. /
<>	128:9bcdf88f62b0	290	} LPC_DMA_Type;
<>	128:9bcdf88f62b0	291
<>	128:9bcdf88f62b0	292
<>	128:9bcdf88f62b0	293	/* ================================================================================ */
<>	128:9bcdf88f62b0	294	/* ================ USB ================ */
<>	128:9bcdf88f62b0	295	/* ================================================================================ */
<>	128:9bcdf88f62b0	296
<>	128:9bcdf88f62b0	297
<>	128:9bcdf88f62b0	298	/**
<>	128:9bcdf88f62b0	299	* @brief USB device controller (USB)
<>	128:9bcdf88f62b0	300	*/
<>	128:9bcdf88f62b0	301
<>	128:9bcdf88f62b0	302	typedef struct { /!< USB Structure /
<>	128:9bcdf88f62b0	303	__IO uint32_t DEVCMDSTAT; /!< USB Device Command/Status register /
<>	128:9bcdf88f62b0	304	__IO uint32_t INFO; /!< USB Info register /
<>	128:9bcdf88f62b0	305	__IO uint32_t EPLISTSTART; /!< USB EP Command/Status List start address /
<>	128:9bcdf88f62b0	306	__IO uint32_t DATABUFSTART; /!< USB Data buffer start address /
<>	128:9bcdf88f62b0	307	__IO uint32_t LPM; /!< Link Power Management register /
<>	128:9bcdf88f62b0	308	__IO uint32_t EPSKIP; /!< USB Endpoint skip /
<>	128:9bcdf88f62b0	309	__IO uint32_t EPINUSE; /!< USB Endpoint Buffer in use /
<>	128:9bcdf88f62b0	310	__IO uint32_t EPBUFCFG; /!< USB Endpoint Buffer Configuration register /
<>	128:9bcdf88f62b0	311	__IO uint32_t INTSTAT; /!< USB interrupt status register /
<>	128:9bcdf88f62b0	312	__IO uint32_t INTEN; /!< USB interrupt enable register /
<>	128:9bcdf88f62b0	313	__IO uint32_t INTSETSTAT; /!< USB set interrupt status register /
<>	128:9bcdf88f62b0	314	__IO uint32_t INTROUTING; /!< USB interrupt routing register /
<>	128:9bcdf88f62b0	315	__I uint32_t RESERVED0;
<>	128:9bcdf88f62b0	316	__I uint32_t EPTOGGLE; /!< USB Endpoint toggle register /
<>	128:9bcdf88f62b0	317	} LPC_USB_Type;
<>	128:9bcdf88f62b0	318
<>	128:9bcdf88f62b0	319
<>	128:9bcdf88f62b0	320	/* ================================================================================ */
<>	128:9bcdf88f62b0	321	/* ================ CRC ================ */
<>	128:9bcdf88f62b0	322	/* ================================================================================ */
<>	128:9bcdf88f62b0	323
<>	128:9bcdf88f62b0	324
<>	128:9bcdf88f62b0	325	/**
<>	128:9bcdf88f62b0	326	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
<>	128:9bcdf88f62b0	327	*/
<>	128:9bcdf88f62b0	328
<>	128:9bcdf88f62b0	329	typedef struct { /!< CRC Structure /
<>	128:9bcdf88f62b0	330	__IO uint32_t MODE; /!< CRC mode register /
<>	128:9bcdf88f62b0	331	__IO uint32_t SEED; /!< CRC seed register /
<>	128:9bcdf88f62b0	332
<>	128:9bcdf88f62b0	333	union {
<>	128:9bcdf88f62b0	334	__O uint32_t WR_DATA; /!< CRC data register /
<>	128:9bcdf88f62b0	335	__I uint32_t SUM; /!< CRC checksum register /
<>	128:9bcdf88f62b0	336	};
<>	128:9bcdf88f62b0	337	} LPC_CRC_Type;
<>	128:9bcdf88f62b0	338
<>	128:9bcdf88f62b0	339
<>	128:9bcdf88f62b0	340	/* ================================================================================ */
<>	128:9bcdf88f62b0	341	/* ================ SCT0 ================ */
<>	128:9bcdf88f62b0	342	/* ================================================================================ */
<>	128:9bcdf88f62b0	343
<>	128:9bcdf88f62b0	344
<>	128:9bcdf88f62b0	345	/**
<>	128:9bcdf88f62b0	346	* @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
<>	128:9bcdf88f62b0	347	*/
<>	128:9bcdf88f62b0	348
<>	128:9bcdf88f62b0	349	typedef struct { /!< SCT0 Structure /
<>	128:9bcdf88f62b0	350	__IO uint32_t CONFIG; /!< SCT configuration register /
<>	128:9bcdf88f62b0	351	__IO uint32_t CTRL; /!< SCT control register /
<>	128:9bcdf88f62b0	352	__IO uint32_t LIMIT; /!< SCT limit register /
<>	128:9bcdf88f62b0	353	__IO uint32_t HALT; /!< SCT halt condition register /
<>	128:9bcdf88f62b0	354	__IO uint32_t STOP; /!< SCT stop condition register /
<>	128:9bcdf88f62b0	355	__IO uint32_t START; /!< SCT start condition register /
<>	128:9bcdf88f62b0	356	__IO uint32_t DITHER; /!< SCT dither condition register /
<>	128:9bcdf88f62b0	357	__I uint32_t RESERVED0[9];
<>	128:9bcdf88f62b0	358	__IO uint32_t COUNT; /!< SCT counter register /
<>	128:9bcdf88f62b0	359	__IO uint32_t STATE; /!< SCT state register /
<>	128:9bcdf88f62b0	360	__I uint32_t INPUT; /!< SCT input register /
<>	128:9bcdf88f62b0	361	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
<>	128:9bcdf88f62b0	362	__IO uint32_t OUTPUT; /!< SCT output register /
<>	128:9bcdf88f62b0	363	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
<>	128:9bcdf88f62b0	364	__IO uint32_t RES; /!< SCT conflict resolution register /
<>	128:9bcdf88f62b0	365	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
<>	128:9bcdf88f62b0	366	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
<>	128:9bcdf88f62b0	367	__I uint32_t RESERVED1[35];
<>	128:9bcdf88f62b0	368	__IO uint32_t EVEN; /!< SCT event enable register /
<>	128:9bcdf88f62b0	369	__IO uint32_t EVFLAG; /!< SCT event flag register /
<>	128:9bcdf88f62b0	370	__IO uint32_t CONEN; /!< SCT conflict enable register /
<>	128:9bcdf88f62b0	371	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
<>	128:9bcdf88f62b0	372
<>	128:9bcdf88f62b0	373	union {
<>	128:9bcdf88f62b0	374	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	375	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	376	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	377	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	378	};
<>	128:9bcdf88f62b0	379
<>	128:9bcdf88f62b0	380	union {
<>	128:9bcdf88f62b0	381	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	382	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	383	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	384	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	385	};
<>	128:9bcdf88f62b0	386
<>	128:9bcdf88f62b0	387	union {
<>	128:9bcdf88f62b0	388	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	389	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	390	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	391	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	392	};
<>	128:9bcdf88f62b0	393
<>	128:9bcdf88f62b0	394	union {
<>	128:9bcdf88f62b0	395	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	396	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	397	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	398	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	399	};
<>	128:9bcdf88f62b0	400
<>	128:9bcdf88f62b0	401	union {
<>	128:9bcdf88f62b0	402	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	403	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	404	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	405	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	406	};
<>	128:9bcdf88f62b0	407
<>	128:9bcdf88f62b0	408	union {
<>	128:9bcdf88f62b0	409	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	410	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	411	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	412	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	413	};
<>	128:9bcdf88f62b0	414
<>	128:9bcdf88f62b0	415	union {
<>	128:9bcdf88f62b0	416	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	417	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	418	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	419	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	420	};
<>	128:9bcdf88f62b0	421
<>	128:9bcdf88f62b0	422	union {
<>	128:9bcdf88f62b0	423	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	424	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	425	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	426	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	427	};
<>	128:9bcdf88f62b0	428
<>	128:9bcdf88f62b0	429	union {
<>	128:9bcdf88f62b0	430	__I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	431	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	432	__IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	433	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	434	};
<>	128:9bcdf88f62b0	435
<>	128:9bcdf88f62b0	436	union {
<>	128:9bcdf88f62b0	437	__IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	438	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	439	__I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	440	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	441	};
<>	128:9bcdf88f62b0	442
<>	128:9bcdf88f62b0	443	union {
<>	128:9bcdf88f62b0	444	__IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	445	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	446	__I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	447	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	448	};
<>	128:9bcdf88f62b0	449
<>	128:9bcdf88f62b0	450	union {
<>	128:9bcdf88f62b0	451	__IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	452	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	453	__I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	454	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	455	};
<>	128:9bcdf88f62b0	456
<>	128:9bcdf88f62b0	457	union {
<>	128:9bcdf88f62b0	458	__IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	459	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	460	__I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	461	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	462	};
<>	128:9bcdf88f62b0	463
<>	128:9bcdf88f62b0	464	union {
<>	128:9bcdf88f62b0	465	__IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	466	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	467	__I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	468	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	469	};
<>	128:9bcdf88f62b0	470
<>	128:9bcdf88f62b0	471	union {
<>	128:9bcdf88f62b0	472	__I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	473	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	474	__IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	475	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	476	};
<>	128:9bcdf88f62b0	477
<>	128:9bcdf88f62b0	478	union {
<>	128:9bcdf88f62b0	479	__IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
<>	128:9bcdf88f62b0	480	to REGMODE15 = 0 */
<>	128:9bcdf88f62b0	481	__I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
<>	128:9bcdf88f62b0	482	REGMODE15 = 1 */
<>	128:9bcdf88f62b0	483	};
<>	128:9bcdf88f62b0	484	__IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
<>	128:9bcdf88f62b0	485	0 to 5. */
<>	128:9bcdf88f62b0	486	__IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
<>	128:9bcdf88f62b0	487	0 to 5. */
<>	128:9bcdf88f62b0	488	__IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
<>	128:9bcdf88f62b0	489	0 to 5. */
<>	128:9bcdf88f62b0	490	__IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
<>	128:9bcdf88f62b0	491	0 to 5. */
<>	128:9bcdf88f62b0	492	__IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
<>	128:9bcdf88f62b0	493	0 to 5. */
<>	128:9bcdf88f62b0	494	__IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
<>	128:9bcdf88f62b0	495	0 to 5. */
<>	128:9bcdf88f62b0	496	__I uint32_t RESERVED2[42];
<>	128:9bcdf88f62b0	497
<>	128:9bcdf88f62b0	498	union {
<>	128:9bcdf88f62b0	499	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	500	= 1 */
<>	128:9bcdf88f62b0	501	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	502	= 0 */
<>	128:9bcdf88f62b0	503	};
<>	128:9bcdf88f62b0	504
<>	128:9bcdf88f62b0	505	union {
<>	128:9bcdf88f62b0	506	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	507	= 0 */
<>	128:9bcdf88f62b0	508	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	509	= 1 */
<>	128:9bcdf88f62b0	510	};
<>	128:9bcdf88f62b0	511
<>	128:9bcdf88f62b0	512	union {
<>	128:9bcdf88f62b0	513	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	514	= 0 */
<>	128:9bcdf88f62b0	515	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	516	= 1 */
<>	128:9bcdf88f62b0	517	};
<>	128:9bcdf88f62b0	518
<>	128:9bcdf88f62b0	519	union {
<>	128:9bcdf88f62b0	520	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	521	= 1 */
<>	128:9bcdf88f62b0	522	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	523	= 0 */
<>	128:9bcdf88f62b0	524	};
<>	128:9bcdf88f62b0	525
<>	128:9bcdf88f62b0	526	union {
<>	128:9bcdf88f62b0	527	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	528	= 1 */
<>	128:9bcdf88f62b0	529	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	530	= 0 */
<>	128:9bcdf88f62b0	531	};
<>	128:9bcdf88f62b0	532
<>	128:9bcdf88f62b0	533	union {
<>	128:9bcdf88f62b0	534	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	535	= 1 */
<>	128:9bcdf88f62b0	536	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	537	= 0 */
<>	128:9bcdf88f62b0	538	};
<>	128:9bcdf88f62b0	539
<>	128:9bcdf88f62b0	540	union {
<>	128:9bcdf88f62b0	541	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	542	= 0 */
<>	128:9bcdf88f62b0	543	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	544	= 1 */
<>	128:9bcdf88f62b0	545	};
<>	128:9bcdf88f62b0	546
<>	128:9bcdf88f62b0	547	union {
<>	128:9bcdf88f62b0	548	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	549	= 0 */
<>	128:9bcdf88f62b0	550	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	551	= 1 */
<>	128:9bcdf88f62b0	552	};
<>	128:9bcdf88f62b0	553
<>	128:9bcdf88f62b0	554	union {
<>	128:9bcdf88f62b0	555	__IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	556	= 1 */
<>	128:9bcdf88f62b0	557	__IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	558	= 0 */
<>	128:9bcdf88f62b0	559	};
<>	128:9bcdf88f62b0	560
<>	128:9bcdf88f62b0	561	union {
<>	128:9bcdf88f62b0	562	__IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	563	= 1 */
<>	128:9bcdf88f62b0	564	__IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	565	= 0 */
<>	128:9bcdf88f62b0	566	};
<>	128:9bcdf88f62b0	567
<>	128:9bcdf88f62b0	568	union {
<>	128:9bcdf88f62b0	569	__IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	570	= 1 */
<>	128:9bcdf88f62b0	571	__IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	572	= 0 */
<>	128:9bcdf88f62b0	573	};
<>	128:9bcdf88f62b0	574
<>	128:9bcdf88f62b0	575	union {
<>	128:9bcdf88f62b0	576	__IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	577	= 1 */
<>	128:9bcdf88f62b0	578	__IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	579	= 0 */
<>	128:9bcdf88f62b0	580	};
<>	128:9bcdf88f62b0	581
<>	128:9bcdf88f62b0	582	union {
<>	128:9bcdf88f62b0	583	__IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	584	= 0 */
<>	128:9bcdf88f62b0	585	__IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	586	= 1 */
<>	128:9bcdf88f62b0	587	};
<>	128:9bcdf88f62b0	588
<>	128:9bcdf88f62b0	589	union {
<>	128:9bcdf88f62b0	590	__IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	591	= 0 */
<>	128:9bcdf88f62b0	592	__IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	593	= 1 */
<>	128:9bcdf88f62b0	594	};
<>	128:9bcdf88f62b0	595
<>	128:9bcdf88f62b0	596	union {
<>	128:9bcdf88f62b0	597	__IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	598	= 1 */
<>	128:9bcdf88f62b0	599	__IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	600	= 0 */
<>	128:9bcdf88f62b0	601	};
<>	128:9bcdf88f62b0	602
<>	128:9bcdf88f62b0	603	union {
<>	128:9bcdf88f62b0	604	__IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
<>	128:9bcdf88f62b0	605	= 1 */
<>	128:9bcdf88f62b0	606	__IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
<>	128:9bcdf88f62b0	607	= 0 */
<>	128:9bcdf88f62b0	608	};
<>	128:9bcdf88f62b0	609	__IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
<>	128:9bcdf88f62b0	610	registers 0 to 5. */
<>	128:9bcdf88f62b0	611	__IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
<>	128:9bcdf88f62b0	612	registers 0 to 5. */
<>	128:9bcdf88f62b0	613	__IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
<>	128:9bcdf88f62b0	614	registers 0 to 5. */
<>	128:9bcdf88f62b0	615	__IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
<>	128:9bcdf88f62b0	616	registers 0 to 5. */
<>	128:9bcdf88f62b0	617	__IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
<>	128:9bcdf88f62b0	618	registers 0 to 5. */
<>	128:9bcdf88f62b0	619	__IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
<>	128:9bcdf88f62b0	620	registers 0 to 5. */
<>	128:9bcdf88f62b0	621	__I uint32_t RESERVED3[42];
<>	128:9bcdf88f62b0	622	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	623	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	624	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	625	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	626	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	627	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	628	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	629	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	630	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	631	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	632	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	633	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	634	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	635	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	636	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	637	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	638	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	639	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	640	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	641	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	642	__IO uint32_t EV10_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	643	__IO uint32_t EV10_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	644	__IO uint32_t EV11_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	645	__IO uint32_t EV11_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	646	__IO uint32_t EV12_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	647	__IO uint32_t EV12_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	648	__IO uint32_t EV13_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	649	__IO uint32_t EV13_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	650	__IO uint32_t EV14_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	651	__IO uint32_t EV14_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	652	__IO uint32_t EV15_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	653	__IO uint32_t EV15_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	654	__I uint32_t RESERVED4[96];
<>	128:9bcdf88f62b0	655	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	656	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	657	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	658	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	659	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	660	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	661	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	662	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	663	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	664	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	665	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	666	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	667	__IO uint32_t OUT6_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	668	__IO uint32_t OUT6_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	669	__IO uint32_t OUT7_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	670	__IO uint32_t OUT7_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	671	__IO uint32_t OUT8_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	672	__IO uint32_t OUT8_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	673	__IO uint32_t OUT9_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	674	__IO uint32_t OUT9_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	675	} LPC_SCT0_Type;
<>	128:9bcdf88f62b0	676
<>	128:9bcdf88f62b0	677
<>	128:9bcdf88f62b0	678	/* ================================================================================ */
<>	128:9bcdf88f62b0	679	/* ================ SCT2 ================ */
<>	128:9bcdf88f62b0	680	/* ================================================================================ */
<>	128:9bcdf88f62b0	681
<>	128:9bcdf88f62b0	682
<>	128:9bcdf88f62b0	683	/**
<>	128:9bcdf88f62b0	684	* @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
<>	128:9bcdf88f62b0	685	*/
<>	128:9bcdf88f62b0	686
<>	128:9bcdf88f62b0	687	typedef struct { /!< SCT2 Structure /
<>	128:9bcdf88f62b0	688	__IO uint32_t CONFIG; /!< SCT configuration register /
<>	128:9bcdf88f62b0	689	__IO uint32_t CTRL; /!< SCT control register /
<>	128:9bcdf88f62b0	690	__IO uint32_t LIMIT; /!< SCT limit register /
<>	128:9bcdf88f62b0	691	__IO uint32_t HALT; /!< SCT halt condition register /
<>	128:9bcdf88f62b0	692	__IO uint32_t STOP; /!< SCT stop condition register /
<>	128:9bcdf88f62b0	693	__IO uint32_t START; /!< SCT start condition register /
<>	128:9bcdf88f62b0	694	__I uint32_t RESERVED0[10];
<>	128:9bcdf88f62b0	695	__IO uint32_t COUNT; /!< SCT counter register /
<>	128:9bcdf88f62b0	696	__IO uint32_t STATE; /!< SCT state register /
<>	128:9bcdf88f62b0	697	__I uint32_t INPUT; /!< SCT input register /
<>	128:9bcdf88f62b0	698	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
<>	128:9bcdf88f62b0	699	__IO uint32_t OUTPUT; /!< SCT output register /
<>	128:9bcdf88f62b0	700	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
<>	128:9bcdf88f62b0	701	__IO uint32_t RES; /!< SCT conflict resolution register /
<>	128:9bcdf88f62b0	702	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
<>	128:9bcdf88f62b0	703	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
<>	128:9bcdf88f62b0	704	__I uint32_t RESERVED1[35];
<>	128:9bcdf88f62b0	705	__IO uint32_t EVEN; /!< SCT event enable register /
<>	128:9bcdf88f62b0	706	__IO uint32_t EVFLAG; /!< SCT event flag register /
<>	128:9bcdf88f62b0	707	__IO uint32_t CONEN; /!< SCT conflict enable register /
<>	128:9bcdf88f62b0	708	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
<>	128:9bcdf88f62b0	709
<>	128:9bcdf88f62b0	710	union {
<>	128:9bcdf88f62b0	711	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	128:9bcdf88f62b0	712	= 1 */
<>	128:9bcdf88f62b0	713	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	128:9bcdf88f62b0	714	REGMODE7 = 0 */
<>	128:9bcdf88f62b0	715	};
<>	128:9bcdf88f62b0	716
<>	128:9bcdf88f62b0	717	union {
<>	128:9bcdf88f62b0	718	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	128:9bcdf88f62b0	719	= 1 */
<>	128:9bcdf88f62b0	720	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	128:9bcdf88f62b0	721	REGMODE7 = 0 */
<>	128:9bcdf88f62b0	722	};
<>	128:9bcdf88f62b0	723
<>	128:9bcdf88f62b0	724	union {
<>	128:9bcdf88f62b0	725	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	128:9bcdf88f62b0	726	= 1 */
<>	128:9bcdf88f62b0	727	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	128:9bcdf88f62b0	728	REGMODE7 = 0 */
<>	128:9bcdf88f62b0	729	};
<>	128:9bcdf88f62b0	730
<>	128:9bcdf88f62b0	731	union {
<>	128:9bcdf88f62b0	732	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	128:9bcdf88f62b0	733	REGMODE7 = 0 */
<>	128:9bcdf88f62b0	734	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	128:9bcdf88f62b0	735	= 1 */
<>	128:9bcdf88f62b0	736	};
<>	128:9bcdf88f62b0	737
<>	128:9bcdf88f62b0	738	union {
<>	128:9bcdf88f62b0	739	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	128:9bcdf88f62b0	740	= 1 */
<>	128:9bcdf88f62b0	741	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	128:9bcdf88f62b0	742	REGMODE7 = 0 */
<>	128:9bcdf88f62b0	743	};
<>	128:9bcdf88f62b0	744
<>	128:9bcdf88f62b0	745	union {
<>	128:9bcdf88f62b0	746	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	128:9bcdf88f62b0	747	REGMODE7 = 0 */
<>	128:9bcdf88f62b0	748	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	128:9bcdf88f62b0	749	= 1 */
<>	128:9bcdf88f62b0	750	};
<>	128:9bcdf88f62b0	751
<>	128:9bcdf88f62b0	752	union {
<>	128:9bcdf88f62b0	753	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	128:9bcdf88f62b0	754	= 1 */
<>	128:9bcdf88f62b0	755	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	128:9bcdf88f62b0	756	REGMODE7 = 0 */
<>	128:9bcdf88f62b0	757	};
<>	128:9bcdf88f62b0	758
<>	128:9bcdf88f62b0	759	union {
<>	128:9bcdf88f62b0	760	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
<>	128:9bcdf88f62b0	761	= 1 */
<>	128:9bcdf88f62b0	762	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
<>	128:9bcdf88f62b0	763	REGMODE7 = 0 */
<>	128:9bcdf88f62b0	764	};
<>	128:9bcdf88f62b0	765	__I uint32_t RESERVED2[56];
<>	128:9bcdf88f62b0	766
<>	128:9bcdf88f62b0	767	union {
<>	128:9bcdf88f62b0	768	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	128:9bcdf88f62b0	769	= 1 */
<>	128:9bcdf88f62b0	770	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	128:9bcdf88f62b0	771	= 0 */
<>	128:9bcdf88f62b0	772	};
<>	128:9bcdf88f62b0	773
<>	128:9bcdf88f62b0	774	union {
<>	128:9bcdf88f62b0	775	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	128:9bcdf88f62b0	776	= 1 */
<>	128:9bcdf88f62b0	777	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	128:9bcdf88f62b0	778	= 0 */
<>	128:9bcdf88f62b0	779	};
<>	128:9bcdf88f62b0	780
<>	128:9bcdf88f62b0	781	union {
<>	128:9bcdf88f62b0	782	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	128:9bcdf88f62b0	783	= 1 */
<>	128:9bcdf88f62b0	784	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	128:9bcdf88f62b0	785	= 0 */
<>	128:9bcdf88f62b0	786	};
<>	128:9bcdf88f62b0	787
<>	128:9bcdf88f62b0	788	union {
<>	128:9bcdf88f62b0	789	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	128:9bcdf88f62b0	790	= 0 */
<>	128:9bcdf88f62b0	791	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	128:9bcdf88f62b0	792	= 1 */
<>	128:9bcdf88f62b0	793	};
<>	128:9bcdf88f62b0	794
<>	128:9bcdf88f62b0	795	union {
<>	128:9bcdf88f62b0	796	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	128:9bcdf88f62b0	797	= 1 */
<>	128:9bcdf88f62b0	798	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	128:9bcdf88f62b0	799	= 0 */
<>	128:9bcdf88f62b0	800	};
<>	128:9bcdf88f62b0	801
<>	128:9bcdf88f62b0	802	union {
<>	128:9bcdf88f62b0	803	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	128:9bcdf88f62b0	804	= 0 */
<>	128:9bcdf88f62b0	805	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	128:9bcdf88f62b0	806	= 1 */
<>	128:9bcdf88f62b0	807	};
<>	128:9bcdf88f62b0	808
<>	128:9bcdf88f62b0	809	union {
<>	128:9bcdf88f62b0	810	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	128:9bcdf88f62b0	811	= 1 */
<>	128:9bcdf88f62b0	812	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	128:9bcdf88f62b0	813	= 0 */
<>	128:9bcdf88f62b0	814	};
<>	128:9bcdf88f62b0	815
<>	128:9bcdf88f62b0	816	union {
<>	128:9bcdf88f62b0	817	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
<>	128:9bcdf88f62b0	818	= 1 */
<>	128:9bcdf88f62b0	819	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
<>	128:9bcdf88f62b0	820	= 0 */
<>	128:9bcdf88f62b0	821	};
<>	128:9bcdf88f62b0	822	__I uint32_t RESERVED3[56];
<>	128:9bcdf88f62b0	823	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	824	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	825	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	826	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	827	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	828	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	829	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	830	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	831	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	832	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	833	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	834	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	835	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	836	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	837	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	838	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	839	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	840	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	841	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
<>	128:9bcdf88f62b0	842	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
<>	128:9bcdf88f62b0	843	__I uint32_t RESERVED4[108];
<>	128:9bcdf88f62b0	844	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	845	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	846	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	847	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	848	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	849	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	850	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	851	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	852	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	853	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	854	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
<>	128:9bcdf88f62b0	855	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
<>	128:9bcdf88f62b0	856	} LPC_SCT2_Type;
<>	128:9bcdf88f62b0	857
<>	128:9bcdf88f62b0	858
<>	128:9bcdf88f62b0	859	/* ================================================================================ */
<>	128:9bcdf88f62b0	860	/* ================ ADC0 ================ */
<>	128:9bcdf88f62b0	861	/* ================================================================================ */
<>	128:9bcdf88f62b0	862
<>	128:9bcdf88f62b0	863
<>	128:9bcdf88f62b0	864	/**
<>	128:9bcdf88f62b0	865	* @brief 12-bit ADC controller ADC0/1 (ADC0)
<>	128:9bcdf88f62b0	866	*/
<>	128:9bcdf88f62b0	867
<>	128:9bcdf88f62b0	868	typedef struct { /!< ADC0 Structure /
<>	128:9bcdf88f62b0	869	__IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
<>	128:9bcdf88f62b0	870	bits for each sequence and the A/D power-down bit. */
<>	128:9bcdf88f62b0	871	__IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
<>	128:9bcdf88f62b0	872	internal source for various channels */
<>	128:9bcdf88f62b0	873	__IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
<>	128:9bcdf88f62b0	874	and channel selection for conversion sequence-A. Also specifies
<>	128:9bcdf88f62b0	875	interrupt mode for sequence-A. */
<>	128:9bcdf88f62b0	876	__IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
<>	128:9bcdf88f62b0	877	and channel selection for conversion sequence-B. Also specifies
<>	128:9bcdf88f62b0	878	interrupt mode for sequence-B. */
<>	128:9bcdf88f62b0	879	__IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
<>	128:9bcdf88f62b0	880	the result of the most recent A/D conversion performed under
<>	128:9bcdf88f62b0	881	sequence-A */
<>	128:9bcdf88f62b0	882	__IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
<>	128:9bcdf88f62b0	883	the result of the most recent A/D conversion performed under
<>	128:9bcdf88f62b0	884	sequence-B */
<>	128:9bcdf88f62b0	885	__I uint32_t RESERVED0[2];
<>	128:9bcdf88f62b0	886	__I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
<>	128:9bcdf88f62b0	887	of the most recent conversion completed on channel 0. */
<>	128:9bcdf88f62b0	888	__IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
<>	128:9bcdf88f62b0	889	level for automatic threshold comparison for any channels linked
<>	128:9bcdf88f62b0	890	to threshold pair 0. */
<>	128:9bcdf88f62b0	891	__IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
<>	128:9bcdf88f62b0	892	level for automatic threshold comparison for any channels linked
<>	128:9bcdf88f62b0	893	to threshold pair 1. */
<>	128:9bcdf88f62b0	894	__IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
<>	128:9bcdf88f62b0	895	level for automatic threshold comparison for any channels linked
<>	128:9bcdf88f62b0	896	to threshold pair 0. */
<>	128:9bcdf88f62b0	897	__IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
<>	128:9bcdf88f62b0	898	level for automatic threshold comparison for any channels linked
<>	128:9bcdf88f62b0	899	to threshold pair 1. */
<>	128:9bcdf88f62b0	900	__I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
<>	128:9bcdf88f62b0	901	threshold compare registers are to be used for each channel */
<>	128:9bcdf88f62b0	902	__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
<>	128:9bcdf88f62b0	903	bits that enable the sequence-A, sequence-B, threshold compare
<>	128:9bcdf88f62b0	904	and data overrun interrupts to be generated. */
<>	128:9bcdf88f62b0	905	__I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
<>	128:9bcdf88f62b0	906	and the individual component overrun and threshold-compare flags.
<>	128:9bcdf88f62b0	907	(The overrun bits replicate information stored in the result
<>	128:9bcdf88f62b0	908	registers). */
<>	128:9bcdf88f62b0	909	__IO uint32_t TRM; /!< ADC trim register. /
<>	128:9bcdf88f62b0	910	} LPC_ADC0_Type;
<>	128:9bcdf88f62b0	911
<>	128:9bcdf88f62b0	912
<>	128:9bcdf88f62b0	913	/* ================================================================================ */
<>	128:9bcdf88f62b0	914	/* ================ DAC ================ */
<>	128:9bcdf88f62b0	915	/* ================================================================================ */
<>	128:9bcdf88f62b0	916
<>	128:9bcdf88f62b0	917
<>	128:9bcdf88f62b0	918	/**
<>	128:9bcdf88f62b0	919	* @brief 12-bit DAC Modification (DAC)
<>	128:9bcdf88f62b0	920	*/
<>	128:9bcdf88f62b0	921
<>	128:9bcdf88f62b0	922	typedef struct { /!< DAC Structure /
<>	128:9bcdf88f62b0	923	__IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
<>	128:9bcdf88f62b0	924	value to be converted to analog. */
<>	128:9bcdf88f62b0	925	__IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
<>	128:9bcdf88f62b0	926	DAC operation and the interrupt/dma request flag. */
<>	128:9bcdf88f62b0	927	__IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
<>	128:9bcdf88f62b0	928	value for the internal DAC DMA/Interrupt timer. */
<>	128:9bcdf88f62b0	929	} LPC_DAC_Type;
<>	128:9bcdf88f62b0	930
<>	128:9bcdf88f62b0	931
<>	128:9bcdf88f62b0	932	/* ================================================================================ */
<>	128:9bcdf88f62b0	933	/* ================ ACMP ================ */
<>	128:9bcdf88f62b0	934	/* ================================================================================ */
<>	128:9bcdf88f62b0	935
<>	128:9bcdf88f62b0	936
<>	128:9bcdf88f62b0	937	/**
<>	128:9bcdf88f62b0	938	* @brief Analog comparators ACMP0/1/2/3 (ACMP)
<>	128:9bcdf88f62b0	939	*/
<>	128:9bcdf88f62b0	940
<>	128:9bcdf88f62b0	941	typedef struct { /!< ACMP Structure /
<>	128:9bcdf88f62b0	942	__IO uint32_t CTRL; /!< Comparator block control register /
<>	128:9bcdf88f62b0	943	__IO uint32_t CMP0; /!< Comparator 0 source control /
<>	128:9bcdf88f62b0	944	__IO uint32_t CMPFILTR0; /!< Comparator 0 pin filter set-up /
<>	128:9bcdf88f62b0	945	__IO uint32_t CMP1; /!< Comparator 1 source control /
<>	128:9bcdf88f62b0	946	__IO uint32_t CMPFILTR1; /!< Comparator 0 pin filter set-up /
<>	128:9bcdf88f62b0	947	__IO uint32_t CMP2; /!< Comparator 2 source control /
<>	128:9bcdf88f62b0	948	__IO uint32_t CMPFILTR2; /!< Comparator 0 pin filter set-up /
<>	128:9bcdf88f62b0	949	__IO uint32_t CMP3; /!< Comparator 3 source control /
<>	128:9bcdf88f62b0	950	__IO uint32_t CMPFILTR3; /!< Comparator 0 pin filter set-up /
<>	128:9bcdf88f62b0	951	} LPC_ACMP_Type;
<>	128:9bcdf88f62b0	952
<>	128:9bcdf88f62b0	953
<>	128:9bcdf88f62b0	954	/* ================================================================================ */
<>	128:9bcdf88f62b0	955	/* ================ INMUX ================ */
<>	128:9bcdf88f62b0	956	/* ================================================================================ */
<>	128:9bcdf88f62b0	957
<>	128:9bcdf88f62b0	958
<>	128:9bcdf88f62b0	959	/**
<>	128:9bcdf88f62b0	960	* @brief Input multiplexing (INMUX) (INMUX)
<>	128:9bcdf88f62b0	961	*/
<>	128:9bcdf88f62b0	962
<>	128:9bcdf88f62b0	963	typedef struct { /!< INMUX Structure /
<>	128:9bcdf88f62b0	964	__IO uint32_t SCT0_INMUX[7]; /!< Pinmux register for SCT0 input 0 /
<>	128:9bcdf88f62b0	965	__I uint32_t RESERVED0;
<>	128:9bcdf88f62b0	966	__IO uint32_t SCT1_INMUX[7]; /!< Pinmux register for SCT1 input 0 /
<>	128:9bcdf88f62b0	967	__I uint32_t RESERVED1;
<>	128:9bcdf88f62b0	968	__IO uint32_t SCT2_INMUX[3]; /!< Pinmux register for SCT2 input 0 /
<>	128:9bcdf88f62b0	969	__I uint32_t RESERVED2[5];
<>	128:9bcdf88f62b0	970	__IO uint32_t SCT3_INMUX[3]; /!< Pinmux register for SCT3 input 0 /
<>	128:9bcdf88f62b0	971	__I uint32_t RESERVED3[21];
<>	128:9bcdf88f62b0	972	__IO uint32_t PINTSEL[8]; /!< Pin interrupt select register 0 /
<>	128:9bcdf88f62b0	973	__IO uint32_t DMA_ITRIG_INMUX[18]; /!< Trigger input for DMA channel 0 select register. /
<>	128:9bcdf88f62b0	974	__I uint32_t RESERVED4[14];
<>	128:9bcdf88f62b0	975	__IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
<>	128:9bcdf88f62b0	976	clock */
<>	128:9bcdf88f62b0	977	__IO uint32_t FREQMEAS_TARGET; /!< Clock selection for frequency measurement function target clock /
<>	128:9bcdf88f62b0	978	} LPC_INMUX_Type;
<>	128:9bcdf88f62b0	979
<>	128:9bcdf88f62b0	980
<>	128:9bcdf88f62b0	981	/* ================================================================================ */
<>	128:9bcdf88f62b0	982	/* ================ RTC ================ */
<>	128:9bcdf88f62b0	983	/* ================================================================================ */
<>	128:9bcdf88f62b0	984
<>	128:9bcdf88f62b0	985
<>	128:9bcdf88f62b0	986	/**
<>	128:9bcdf88f62b0	987	* @brief Real-Time Clock (RTC) (RTC)
<>	128:9bcdf88f62b0	988	*/
<>	128:9bcdf88f62b0	989
<>	128:9bcdf88f62b0	990	typedef struct { /!< RTC Structure /
<>	128:9bcdf88f62b0	991	__IO uint32_t CTRL; /!< RTC control register /
<>	128:9bcdf88f62b0	992	__IO uint32_t MATCH; /!< RTC match register /
<>	128:9bcdf88f62b0	993	__IO uint32_t COUNT; /!< RTC counter register /
<>	128:9bcdf88f62b0	994	__IO uint32_t WAKE; /!< RTC high-resolution/wake-up timer control register /
<>	128:9bcdf88f62b0	995	} LPC_RTC_Type;
<>	128:9bcdf88f62b0	996
<>	128:9bcdf88f62b0	997
<>	128:9bcdf88f62b0	998	/* ================================================================================ */
<>	128:9bcdf88f62b0	999	/* ================ WWDT ================ */
<>	128:9bcdf88f62b0	1000	/* ================================================================================ */
<>	128:9bcdf88f62b0	1001
<>	128:9bcdf88f62b0	1002
<>	128:9bcdf88f62b0	1003	/**
<>	128:9bcdf88f62b0	1004	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
<>	128:9bcdf88f62b0	1005	*/
<>	128:9bcdf88f62b0	1006
<>	128:9bcdf88f62b0	1007	typedef struct { /!< WWDT Structure /
<>	128:9bcdf88f62b0	1008	__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
<>	128:9bcdf88f62b0	1009	and status of the Watchdog Timer. */
<>	128:9bcdf88f62b0	1010	__IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
<>	128:9bcdf88f62b0	1011	the time-out value. */
<>	128:9bcdf88f62b0	1012	__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
<>	128:9bcdf88f62b0	1013	to this register reloads the Watchdog timer with the value contained
<>	128:9bcdf88f62b0	1014	in WDTC. */
<>	128:9bcdf88f62b0	1015	__I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
<>	128:9bcdf88f62b0	1016	the current value of the Watchdog timer. */
<>	128:9bcdf88f62b0	1017	__I uint32_t RESERVED0;
<>	128:9bcdf88f62b0	1018	__IO uint32_t WARNINT; /!< Watchdog Warning Interrupt compare value. /
<>	128:9bcdf88f62b0	1019	__IO uint32_t WINDOW; /!< Watchdog Window compare value. /
<>	128:9bcdf88f62b0	1020	} LPC_WWDT_Type;
<>	128:9bcdf88f62b0	1021
<>	128:9bcdf88f62b0	1022
<>	128:9bcdf88f62b0	1023	/* ================================================================================ */
<>	128:9bcdf88f62b0	1024	/* ================ SWM ================ */
<>	128:9bcdf88f62b0	1025	/* ================================================================================ */
<>	128:9bcdf88f62b0	1026
<>	128:9bcdf88f62b0	1027
<>	128:9bcdf88f62b0	1028	/**
<>	128:9bcdf88f62b0	1029	* @brief Switch Matrix (SWM) (SWM)
<>	128:9bcdf88f62b0	1030	*/
<>	128:9bcdf88f62b0	1031
<>	128:9bcdf88f62b0	1032	typedef struct { /!< SWM Structure /
<>	128:9bcdf88f62b0	1033	union {
<>	128:9bcdf88f62b0	1034	__IO uint32_t PINASSIGN[16];
<>	128:9bcdf88f62b0	1035	struct {
<>	128:9bcdf88f62b0	1036	__IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
<>	128:9bcdf88f62b0	1037	U0_RTS, U0_CTS. */
<>	128:9bcdf88f62b0	1038	__IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
<>	128:9bcdf88f62b0	1039	U1_RXD, U1_RTS. */
<>	128:9bcdf88f62b0	1040	__IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
<>	128:9bcdf88f62b0	1041	U2_TXD, U2_RXD. */
<>	128:9bcdf88f62b0	1042	__IO uint32_t PINASSIGN3; /!< Pin assign register 3. Assign movable function . /
<>	128:9bcdf88f62b0	1043	__IO uint32_t PINASSIGN4; /!< Pin assign register 4. Assign movable functions /
<>	128:9bcdf88f62b0	1044	__IO uint32_t PINASSIGN5; /!< Pin assign register 5. Assign movable functions /
<>	128:9bcdf88f62b0	1045	__IO uint32_t PINASSIGN6; /!< Pin assign register 6. Assign movable functions /
<>	128:9bcdf88f62b0	1046	__IO uint32_t PINASSIGN7; /!< Pin assign register 7. Assign movable functions /
<>	128:9bcdf88f62b0	1047	__IO uint32_t PINASSIGN8; /!< Pin assign register 8. Assign movable functions /
<>	128:9bcdf88f62b0	1048	__IO uint32_t PINASSIGN9; /!< Pin assign register 9. Assign movable functions /
<>	128:9bcdf88f62b0	1049	__IO uint32_t PINASSIGN10; /!< Pin assign register 10. Assign movable functions /
<>	128:9bcdf88f62b0	1050	__IO uint32_t PINASSIGN11; /!< Pin assign register 11. Assign movable functions /
<>	128:9bcdf88f62b0	1051	__IO uint32_t PINASSIGN12; /!< Pin assign register 12. Assign movable functions /
<>	128:9bcdf88f62b0	1052	__IO uint32_t PINASSIGN13; /!< Pin assign register 13. Assign movable functions /
<>	128:9bcdf88f62b0	1053	__IO uint32_t PINASSIGN14; /!< Pin assign register 14. Assign movable functions /
<>	128:9bcdf88f62b0	1054	__IO uint32_t PINASSIGN15; /!< Pin assign register 15. Assign movable functions /
<>	128:9bcdf88f62b0	1055	};
<>	128:9bcdf88f62b0	1056	};
<>	128:9bcdf88f62b0	1057	__I uint32_t RESERVED0[96];
<>	128:9bcdf88f62b0	1058	__IO uint32_t PINENABLE0; /!< Pin enable register 0. Enables fixed-pin functions /
<>	128:9bcdf88f62b0	1059	__IO uint32_t PINENABLE1; /!< Pin enable register 0. Enables fixed-pin functions /
<>	128:9bcdf88f62b0	1060	} LPC_SWM_Type;
<>	128:9bcdf88f62b0	1061
<>	128:9bcdf88f62b0	1062
<>	128:9bcdf88f62b0	1063	/* ================================================================================ */
<>	128:9bcdf88f62b0	1064	/* ================ PMU ================ */
<>	128:9bcdf88f62b0	1065	/* ================================================================================ */
<>	128:9bcdf88f62b0	1066
<>	128:9bcdf88f62b0	1067
<>	128:9bcdf88f62b0	1068	/**
<>	128:9bcdf88f62b0	1069	* @brief Power Management Unit (PMU) (PMU)
<>	128:9bcdf88f62b0	1070	*/
<>	128:9bcdf88f62b0	1071
<>	128:9bcdf88f62b0	1072	typedef struct { /!< PMU Structure /
<>	128:9bcdf88f62b0	1073	__IO uint32_t PCON; /!< Power control register /
<>	128:9bcdf88f62b0	1074	__IO uint32_t GPREG0; /!< General purpose register 0 /
<>	128:9bcdf88f62b0	1075	__IO uint32_t GPREG1; /!< General purpose register 0 /
<>	128:9bcdf88f62b0	1076	__IO uint32_t GPREG2; /!< General purpose register 0 /
<>	128:9bcdf88f62b0	1077	__IO uint32_t GPREG3; /!< General purpose register 0 /
<>	128:9bcdf88f62b0	1078	__IO uint32_t DPDCTRL; /!< Deep power-down control register /
<>	128:9bcdf88f62b0	1079	} LPC_PMU_Type;
<>	128:9bcdf88f62b0	1080
<>	128:9bcdf88f62b0	1081
<>	128:9bcdf88f62b0	1082	/* ================================================================================ */
<>	128:9bcdf88f62b0	1083	/* ================ USART0 ================ */
<>	128:9bcdf88f62b0	1084	/* ================================================================================ */
<>	128:9bcdf88f62b0	1085
<>	128:9bcdf88f62b0	1086
<>	128:9bcdf88f62b0	1087	/**
<>	128:9bcdf88f62b0	1088	* @brief USART0 (USART0)
<>	128:9bcdf88f62b0	1089	*/
<>	128:9bcdf88f62b0	1090
<>	128:9bcdf88f62b0	1091	typedef struct { /!< USART0 Structure /
<>	128:9bcdf88f62b0	1092	__IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
<>	128:9bcdf88f62b0	1093	that typically are not changed during operation. */
<>	128:9bcdf88f62b0	1094	__IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
<>	128:9bcdf88f62b0	1095	likely to change during operation. */
<>	128:9bcdf88f62b0	1096	__IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
<>	128:9bcdf88f62b0	1097	here. Writing ones clears some bits in the register. Some bits
<>	128:9bcdf88f62b0	1098	can be cleared by writing a 1 to them. */
<>	128:9bcdf88f62b0	1099	__IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
<>	128:9bcdf88f62b0	1100	interrupt enable bit for each potential USART interrupt. A complete
<>	128:9bcdf88f62b0	1101	value may be read from this register. Writing a 1 to any implemented
<>	128:9bcdf88f62b0	1102	bit position causes that bit to be set. */
<>	128:9bcdf88f62b0	1103	__O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
<>	128:9bcdf88f62b0	1104	of bits in the INTENSET register. Writing a 1 to any implemented
<>	128:9bcdf88f62b0	1105	bit position causes the corresponding bit to be cleared. */
<>	128:9bcdf88f62b0	1106	__I uint32_t RXDATA; /!< Receiver Data register. Contains the last character received. /
<>	128:9bcdf88f62b0	1107	__I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
<>	128:9bcdf88f62b0	1108	received with the current USART receive status. Allows DMA or
<>	128:9bcdf88f62b0	1109	software to recover incoming data and status together. */
<>	128:9bcdf88f62b0	1110	__IO uint32_t TXDATA; /!< Transmit Data register. Data to be transmitted is written here. /
<>	128:9bcdf88f62b0	1111	__IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
<>	128:9bcdf88f62b0	1112	value. */
<>	128:9bcdf88f62b0	1113	__I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
<>	128:9bcdf88f62b0	1114	enabled. */
<>	128:9bcdf88f62b0	1115	} LPC_USART0_Type;
<>	128:9bcdf88f62b0	1116
<>	128:9bcdf88f62b0	1117
<>	128:9bcdf88f62b0	1118	/* ================================================================================ */
<>	128:9bcdf88f62b0	1119	/* ================ SPI0 ================ */
<>	128:9bcdf88f62b0	1120	/* ================================================================================ */
<>	128:9bcdf88f62b0	1121
<>	128:9bcdf88f62b0	1122
<>	128:9bcdf88f62b0	1123	/**
<>	128:9bcdf88f62b0	1124	* @brief SPI0 (SPI0)
<>	128:9bcdf88f62b0	1125	*/
<>	128:9bcdf88f62b0	1126
<>	128:9bcdf88f62b0	1127	typedef struct { /!< SPI0 Structure /
<>	128:9bcdf88f62b0	1128	__IO uint32_t CFG; /!< SPI Configuration register /
<>	128:9bcdf88f62b0	1129	__IO uint32_t DLY; /!< SPI Delay register /
<>	128:9bcdf88f62b0	1130	__IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
<>	128:9bcdf88f62b0	1131	to that bit position */
<>	128:9bcdf88f62b0	1132	__IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
<>	128:9bcdf88f62b0	1133	from this register. Writing a 1 to any implemented bit position
<>	128:9bcdf88f62b0	1134	causes that bit to be set. */
<>	128:9bcdf88f62b0	1135	__O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
<>	128:9bcdf88f62b0	1136	position causes the corresponding bit in INTENSET to be cleared. */
<>	128:9bcdf88f62b0	1137	__I uint32_t RXDAT; /!< SPI Receive Data /
<>	128:9bcdf88f62b0	1138	__IO uint32_t TXDATCTL; /!< SPI Transmit Data with Control /
<>	128:9bcdf88f62b0	1139	__IO uint32_t TXDAT; /!< SPI Transmit Data with Control /
<>	128:9bcdf88f62b0	1140	__IO uint32_t TXCTL; /!< SPI Transmit Control /
<>	128:9bcdf88f62b0	1141	__IO uint32_t DIV; /!< SPI clock Divider /
<>	128:9bcdf88f62b0	1142	__I uint32_t INTSTAT; /!< SPI Interrupt Status /
<>	128:9bcdf88f62b0	1143	} LPC_SPI0_Type;
<>	128:9bcdf88f62b0	1144
<>	128:9bcdf88f62b0	1145
<>	128:9bcdf88f62b0	1146	/* ================================================================================ */
<>	128:9bcdf88f62b0	1147	/* ================ I2C0 ================ */
<>	128:9bcdf88f62b0	1148	/* ================================================================================ */
<>	128:9bcdf88f62b0	1149
<>	128:9bcdf88f62b0	1150
<>	128:9bcdf88f62b0	1151	/**
<>	128:9bcdf88f62b0	1152	* @brief I2C-bus interface (I2C0)
<>	128:9bcdf88f62b0	1153	*/
<>	128:9bcdf88f62b0	1154
<>	128:9bcdf88f62b0	1155	typedef struct { /!< I2C0 Structure /
<>	128:9bcdf88f62b0	1156	__IO uint32_t CFG; /!< Configuration for shared functions. /
<>	128:9bcdf88f62b0	1157	__IO uint32_t STAT; /!< Status register for Master, Slave, and Monitor functions. /
<>	128:9bcdf88f62b0	1158	__IO uint32_t INTENSET; /!< Interrupt Enable Set and read register. /
<>	128:9bcdf88f62b0	1159	__O uint32_t INTENCLR; /!< Interrupt Enable Clear register. /
<>	128:9bcdf88f62b0	1160	__IO uint32_t TIMEOUT; /!< Time-out value register. /
<>	128:9bcdf88f62b0	1161	__IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
<>	128:9bcdf88f62b0	1162	what time increments are used for the MSTTIME and SLVTIME registers. */
<>	128:9bcdf88f62b0	1163	__I uint32_t INTSTAT; /!< Interrupt Status register for Master, Slave, and Monitor functions. /
<>	128:9bcdf88f62b0	1164	__I uint32_t RESERVED0;
<>	128:9bcdf88f62b0	1165	__IO uint32_t MSTCTL; /!< Master control register. /
<>	128:9bcdf88f62b0	1166	__IO uint32_t MSTTIME; /!< Master timing configuration. /
<>	128:9bcdf88f62b0	1167	__IO uint32_t MSTDAT; /!< Combined Master receiver and transmitter data register. /
<>	128:9bcdf88f62b0	1168	__I uint32_t RESERVED1[5];
<>	128:9bcdf88f62b0	1169	__IO uint32_t SLVCTL; /!< Slave control register. /
<>	128:9bcdf88f62b0	1170	__IO uint32_t SLVDAT; /!< Combined Slave receiver and transmitter data register. /
<>	128:9bcdf88f62b0	1171	__IO uint32_t SLVADR0; /!< Slave address 0. /
<>	128:9bcdf88f62b0	1172	__IO uint32_t SLVADR1; /!< Slave address 0. /
<>	128:9bcdf88f62b0	1173	__IO uint32_t SLVADR2; /!< Slave address 0. /
<>	128:9bcdf88f62b0	1174	__IO uint32_t SLVADR3; /!< Slave address 0. /
<>	128:9bcdf88f62b0	1175	__IO uint32_t SLVQUAL0; /!< Slave Qualification for address 0. /
<>	128:9bcdf88f62b0	1176	__I uint32_t RESERVED2[9];
<>	128:9bcdf88f62b0	1177	__I uint32_t MONRXDAT; /!< Monitor receiver data register. /
<>	128:9bcdf88f62b0	1178	} LPC_I2C0_Type;
<>	128:9bcdf88f62b0	1179
<>	128:9bcdf88f62b0	1180
<>	128:9bcdf88f62b0	1181	/* ================================================================================ */
<>	128:9bcdf88f62b0	1182	/* ================ QEI ================ */
<>	128:9bcdf88f62b0	1183	/* ================================================================================ */
<>	128:9bcdf88f62b0	1184
<>	128:9bcdf88f62b0	1185
<>	128:9bcdf88f62b0	1186	/**
<>	128:9bcdf88f62b0	1187	* @brief Quadrature Encoder Interface (QEI) (QEI)
<>	128:9bcdf88f62b0	1188	*/
<>	128:9bcdf88f62b0	1189
<>	128:9bcdf88f62b0	1190	typedef struct { /!< QEI Structure /
<>	128:9bcdf88f62b0	1191	__O uint32_t CON; /!< Control register /
<>	128:9bcdf88f62b0	1192	__I uint32_t STAT; /!< Encoder status register /
<>	128:9bcdf88f62b0	1193	__IO uint32_t CONF; /!< Configuration register /
<>	128:9bcdf88f62b0	1194	__I uint32_t POS; /!< Position register /
<>	128:9bcdf88f62b0	1195	__IO uint32_t MAXPOS; /!< Maximum position register /
<>	128:9bcdf88f62b0	1196	__IO uint32_t CMPOS0; /!< position compare register 0 /
<>	128:9bcdf88f62b0	1197	__IO uint32_t CMPOS1; /!< position compare register 1 /
<>	128:9bcdf88f62b0	1198	__IO uint32_t CMPOS2; /!< position compare register 2 /
<>	128:9bcdf88f62b0	1199	__I uint32_t INXCNT; /!< Index count register /
<>	128:9bcdf88f62b0	1200	__IO uint32_t INXCMP0; /!< Index compare register 0 /
<>	128:9bcdf88f62b0	1201	__IO uint32_t LOAD; /!< Velocity timer reload register /
<>	128:9bcdf88f62b0	1202	__I uint32_t TIME; /!< Velocity timer register /
<>	128:9bcdf88f62b0	1203	__I uint32_t VEL; /!< Velocity counter register /
<>	128:9bcdf88f62b0	1204	__I uint32_t CAP; /!< Velocity capture register /
<>	128:9bcdf88f62b0	1205	__IO uint32_t VELCOMP; /!< Velocity compare register /
<>	128:9bcdf88f62b0	1206	__IO uint32_t FILTERPHA; /!< Digital filter register on input phase A (QEI_A) /
<>	128:9bcdf88f62b0	1207	__IO uint32_t FILTERPHB; /!< Digital filter register on input phase B (QEI_B) /
<>	128:9bcdf88f62b0	1208	__IO uint32_t FILTERINX; /!< Digital filter register on input index (QEI_IDX) /
<>	128:9bcdf88f62b0	1209	__IO uint32_t WINDOW; /!< Index acceptance window register /
<>	128:9bcdf88f62b0	1210	__IO uint32_t INXCMP1; /!< Index compare register 1 /
<>	128:9bcdf88f62b0	1211	__IO uint32_t INXCMP2; /!< Index compare register 2 /
<>	128:9bcdf88f62b0	1212	__I uint32_t RESERVED0[993];
<>	128:9bcdf88f62b0	1213	__O uint32_t IEC; /!< Interrupt enable clear register /
<>	128:9bcdf88f62b0	1214	__O uint32_t IES; /!< Interrupt enable set register /
<>	128:9bcdf88f62b0	1215	__I uint32_t INTSTAT; /!< Interrupt status register /
<>	128:9bcdf88f62b0	1216	__O uint32_t IE; /!< Interrupt enable clear register /
<>	128:9bcdf88f62b0	1217	__O uint32_t CLR; /!< Interrupt status clear register /
<>	128:9bcdf88f62b0	1218	__O uint32_t SET; /!< Interrupt status set register /
<>	128:9bcdf88f62b0	1219	} LPC_QEI_Type;
<>	128:9bcdf88f62b0	1220
<>	128:9bcdf88f62b0	1221
<>	128:9bcdf88f62b0	1222	/* ================================================================================ */
<>	128:9bcdf88f62b0	1223	/* ================ SYSCON ================ */
<>	128:9bcdf88f62b0	1224	/* ================================================================================ */
<>	128:9bcdf88f62b0	1225
<>	128:9bcdf88f62b0	1226
<>	128:9bcdf88f62b0	1227	/**
<>	128:9bcdf88f62b0	1228	* @brief System configuration (SYSCON) (SYSCON)
<>	128:9bcdf88f62b0	1229	*/
<>	128:9bcdf88f62b0	1230
<>	128:9bcdf88f62b0	1231	typedef struct { /!< SYSCON Structure /
<>	128:9bcdf88f62b0	1232	__IO uint32_t SYSMEMREMAP; /!< System memory remap /
<>	128:9bcdf88f62b0	1233	__I uint32_t RESERVED0[4];
<>	128:9bcdf88f62b0	1234	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration /
<>	128:9bcdf88f62b0	1235	__I uint32_t RESERVED1;
<>	128:9bcdf88f62b0	1236	__IO uint32_t NMISRC; /!< NMI Source Control /
<>	128:9bcdf88f62b0	1237	__I uint32_t RESERVED2[8];
<>	128:9bcdf88f62b0	1238	__IO uint32_t SYSRSTSTAT; /!< System reset status register /
<>	128:9bcdf88f62b0	1239	__IO uint32_t PRESETCTRL0; /!< Peripheral reset control 0 /
<>	128:9bcdf88f62b0	1240	__IO uint32_t PRESETCTRL1; /!< Peripheral reset control 1 /
<>	128:9bcdf88f62b0	1241	__I uint32_t PIOPORCAP0; /!< POR captured PIO status 0 /
<>	128:9bcdf88f62b0	1242	__I uint32_t PIOPORCAP1; /!< POR captured PIO status 1 /
<>	128:9bcdf88f62b0	1243	__I uint32_t PIOPORCAP2; /!< POR captured PIO status 2 /
<>	128:9bcdf88f62b0	1244	__I uint32_t RESERVED3[10];
<>	128:9bcdf88f62b0	1245	__IO uint32_t MAINCLKSELA; /!< Main clock source select A /
<>	128:9bcdf88f62b0	1246	__IO uint32_t MAINCLKSELB; /!< Main clock source select B /
<>	128:9bcdf88f62b0	1247	__IO uint32_t USBCLKSEL; /!< USB clock source select /
<>	128:9bcdf88f62b0	1248	__IO uint32_t ADCASYNCCLKSEL; /!< ADC asynchronous clock source select /
<>	128:9bcdf88f62b0	1249	__I uint32_t RESERVED4;
<>	128:9bcdf88f62b0	1250	__IO uint32_t CLKOUTSELA; /!< CLKOUT clock source select A /
<>	128:9bcdf88f62b0	1251	__IO uint32_t CLKOUTSELB; /!< CLKOUT clock source select B /
<>	128:9bcdf88f62b0	1252	__I uint32_t RESERVED5;
<>	128:9bcdf88f62b0	1253	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select /
<>	128:9bcdf88f62b0	1254	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select /
<>	128:9bcdf88f62b0	1255	__IO uint32_t SCTPLLCLKSEL; /!< SCT PLL clock source select /
<>	128:9bcdf88f62b0	1256	__I uint32_t RESERVED6[5];
<>	128:9bcdf88f62b0	1257	__IO uint32_t SYSAHBCLKDIV; /!< System clock divider /
<>	128:9bcdf88f62b0	1258	__IO uint32_t SYSAHBCLKCTRL0; /!< System clock control 0 /
<>	128:9bcdf88f62b0	1259	__IO uint32_t SYSAHBCLKCTRL1; /!< System clock control 1 /
<>	128:9bcdf88f62b0	1260	__IO uint32_t SYSTICKCLKDIV; /!< SYSTICK clock divider /
<>	128:9bcdf88f62b0	1261	__IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
<>	128:9bcdf88f62b0	1262	baud rate generator. */
<>	128:9bcdf88f62b0	1263	__IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
<>	128:9bcdf88f62b0	1264	filter */
<>	128:9bcdf88f62b0	1265	__IO uint32_t TRACECLKDIV; /!< ARM trace clock divider /
<>	128:9bcdf88f62b0	1266	__I uint32_t RESERVED7[4];
<>	128:9bcdf88f62b0	1267	__IO uint32_t USBCLKDIV; /!< USB clock divider /
<>	128:9bcdf88f62b0	1268	__IO uint32_t ADCASYNCCLKDIV; /!< Asynchronous ADC clock divider /
<>	128:9bcdf88f62b0	1269	__I uint32_t RESERVED8;
<>	128:9bcdf88f62b0	1270	__IO uint32_t CLKOUTDIV; /!< CLKOUT clock divider /
<>	128:9bcdf88f62b0	1271	__I uint32_t RESERVED9[11];
<>	128:9bcdf88f62b0	1272	__IO uint32_t FRGCTRL; /!< USART fractional baud rate generator control /
<>	128:9bcdf88f62b0	1273	__IO uint32_t USBCLKCTRL; /!< USB clock control /
<>	128:9bcdf88f62b0	1274	__IO uint32_t USBCLKST; /!< USB clock status /
<>	128:9bcdf88f62b0	1275	__I uint32_t RESERVED10[19];
<>	128:9bcdf88f62b0	1276	__IO uint32_t BODCTRL; /!< Brown-Out Detect /
<>	128:9bcdf88f62b0	1277	__I uint32_t RESERVED11;
<>	128:9bcdf88f62b0	1278	__IO uint32_t SYSOSCCTRL; /!< System oscillator control /
<>	128:9bcdf88f62b0	1279	__I uint32_t RESERVED12;
<>	128:9bcdf88f62b0	1280	__IO uint32_t RTCOSCCTRL; /!< RTC oscillator control /
<>	128:9bcdf88f62b0	1281	__I uint32_t RESERVED13;
<>	128:9bcdf88f62b0	1282	__IO uint32_t SYSPLLCTRL; /!< System PLL control /
<>	128:9bcdf88f62b0	1283	__I uint32_t SYSPLLSTAT; /!< System PLL status /
<>	128:9bcdf88f62b0	1284	__IO uint32_t USBPLLCTRL; /!< USB PLL control /
<>	128:9bcdf88f62b0	1285	__I uint32_t USBPLLSTAT; /!< USB PLL status /
<>	128:9bcdf88f62b0	1286	__IO uint32_t SCTPLLCTRL; /!< SCT PLL control /
<>	128:9bcdf88f62b0	1287	__I uint32_t SCTPLLSTAT; /!< SCT PLL status /
<>	128:9bcdf88f62b0	1288	__I uint32_t RESERVED14[21];
<>	128:9bcdf88f62b0	1289	__IO uint32_t PDAWAKECFG; /!< Power-down states for wake-up from deep-sleep /
<>	128:9bcdf88f62b0	1290	__IO uint32_t PDRUNCFG; /!< Power configuration register /
<>	128:9bcdf88f62b0	1291	__I uint32_t RESERVED15[3];
<>	128:9bcdf88f62b0	1292	__IO uint32_t STARTERP0; /!< Start logic 0 wake-up enable register /
<>	128:9bcdf88f62b0	1293	__IO uint32_t STARTERP1; /!< Start logic 1 wake-up enable register /
<>	128:9bcdf88f62b0	1294	} LPC_SYSCON_Type;
<>	128:9bcdf88f62b0	1295
<>	128:9bcdf88f62b0	1296
<>	128:9bcdf88f62b0	1297	/* ================================================================================ */
<>	128:9bcdf88f62b0	1298	/* ================ MRT ================ */
<>	128:9bcdf88f62b0	1299	/* ================================================================================ */
<>	128:9bcdf88f62b0	1300
<>	128:9bcdf88f62b0	1301
<>	128:9bcdf88f62b0	1302	/**
<>	128:9bcdf88f62b0	1303	* @brief Multi-Rate Timer (MRT) (MRT)
<>	128:9bcdf88f62b0	1304	*/
<>	128:9bcdf88f62b0	1305
<>	128:9bcdf88f62b0	1306	typedef struct { /!< MRT Structure /
<>	128:9bcdf88f62b0	1307	__IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
<>	128:9bcdf88f62b0	1308	the TIMER0 register. */
<>	128:9bcdf88f62b0	1309	__I uint32_t TIMER0; /!< MRT0 Timer register. This register reads the value of the down-counter. /
<>	128:9bcdf88f62b0	1310	__IO uint32_t CTRL0; /!< MRT0 Control register. This register controls the MRT0 modes. /
<>	128:9bcdf88f62b0	1311	__IO uint32_t STAT0; /!< MRT0 Status register. /
<>	128:9bcdf88f62b0	1312	__IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
<>	128:9bcdf88f62b0	1313	the TIMER0 register. */
<>	128:9bcdf88f62b0	1314	__I uint32_t TIMER1; /!< MRT0 Timer register. This register reads the value of the down-counter. /
<>	128:9bcdf88f62b0	1315	__IO uint32_t CTRL1; /!< MRT0 Control register. This register controls the MRT0 modes. /
<>	128:9bcdf88f62b0	1316	__IO uint32_t STAT1; /!< MRT0 Status register. /
<>	128:9bcdf88f62b0	1317	__IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
<>	128:9bcdf88f62b0	1318	the TIMER0 register. */
<>	128:9bcdf88f62b0	1319	__I uint32_t TIMER2; /!< MRT0 Timer register. This register reads the value of the down-counter. /
<>	128:9bcdf88f62b0	1320	__IO uint32_t CTRL2; /!< MRT0 Control register. This register controls the MRT0 modes. /
<>	128:9bcdf88f62b0	1321	__IO uint32_t STAT2; /!< MRT0 Status register. /
<>	128:9bcdf88f62b0	1322	__IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
<>	128:9bcdf88f62b0	1323	the TIMER0 register. */
<>	128:9bcdf88f62b0	1324	__I uint32_t TIMER3; /!< MRT0 Timer register. This register reads the value of the down-counter. /
<>	128:9bcdf88f62b0	1325	__IO uint32_t CTRL3; /!< MRT0 Control register. This register controls the MRT0 modes. /
<>	128:9bcdf88f62b0	1326	__IO uint32_t STAT3; /!< MRT0 Status register. /
<>	128:9bcdf88f62b0	1327	__I uint32_t RESERVED0[45];
<>	128:9bcdf88f62b0	1328	__I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
<>	128:9bcdf88f62b0	1329	first idle channel. */
<>	128:9bcdf88f62b0	1330	__IO uint32_t IRQ_FLAG; /!< Global interrupt flag register /
<>	128:9bcdf88f62b0	1331	} LPC_MRT_Type;
<>	128:9bcdf88f62b0	1332
<>	128:9bcdf88f62b0	1333
<>	128:9bcdf88f62b0	1334	/* ================================================================================ */
<>	128:9bcdf88f62b0	1335	/* ================ PINT ================ */
<>	128:9bcdf88f62b0	1336	/* ================================================================================ */
<>	128:9bcdf88f62b0	1337
<>	128:9bcdf88f62b0	1338
<>	128:9bcdf88f62b0	1339	/**
<>	128:9bcdf88f62b0	1340	* @brief Pin interruptand pattern match (PINT) (PINT)
<>	128:9bcdf88f62b0	1341	*/
<>	128:9bcdf88f62b0	1342
<>	128:9bcdf88f62b0	1343	typedef struct { /!< PINT Structure /
<>	128:9bcdf88f62b0	1344	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
<>	128:9bcdf88f62b0	1345	__IO uint32_t IENR; /!< Pin interrupt level or rising edge interrupt enable register /
<>	128:9bcdf88f62b0	1346	__O uint32_t SIENR; /!< Pin interrupt level or rising edge interrupt set register /
<>	128:9bcdf88f62b0	1347	__O uint32_t CIENR; /!< Pin interrupt level (rising edge interrupt) clear register /
<>	128:9bcdf88f62b0	1348	__IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
<>	128:9bcdf88f62b0	1349	register */
<>	128:9bcdf88f62b0	1350	__O uint32_t SIENF; /!< Pin interrupt active level or falling edge interrupt set register /
<>	128:9bcdf88f62b0	1351	__O uint32_t CIENF; /!< Pin interrupt active level or falling edge interrupt clear register /
<>	128:9bcdf88f62b0	1352	__IO uint32_t RISE; /!< Pin interrupt rising edge register /
<>	128:9bcdf88f62b0	1353	__IO uint32_t FALL; /!< Pin interrupt falling edge register /
<>	128:9bcdf88f62b0	1354	__IO uint32_t IST; /!< Pin interrupt status register /
<>	128:9bcdf88f62b0	1355	__IO uint32_t PMCTRL; /!< Pattern match interrupt control register /
<>	128:9bcdf88f62b0	1356	__IO uint32_t PMSRC; /!< Pattern match interrupt bit-slice source register /
<>	128:9bcdf88f62b0	1357	__IO uint32_t PMCFG; /!< Pattern match interrupt bit slice configuration register /
<>	128:9bcdf88f62b0	1358	} LPC_PINT_Type;
<>	128:9bcdf88f62b0	1359
<>	128:9bcdf88f62b0	1360
<>	128:9bcdf88f62b0	1361	/* ================================================================================ */
<>	128:9bcdf88f62b0	1362	/* ================ GINT0 ================ */
<>	128:9bcdf88f62b0	1363	/* ================================================================================ */
<>	128:9bcdf88f62b0	1364
<>	128:9bcdf88f62b0	1365
<>	128:9bcdf88f62b0	1366	/**
<>	128:9bcdf88f62b0	1367	* @brief Group interrupt 0/1 (GINT0/1) (GINT0)
<>	128:9bcdf88f62b0	1368	*/
<>	128:9bcdf88f62b0	1369
<>	128:9bcdf88f62b0	1370	typedef struct { /!< GINT0 Structure /
<>	128:9bcdf88f62b0	1371	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
<>	128:9bcdf88f62b0	1372	__I uint32_t RESERVED0[7];
<>	128:9bcdf88f62b0	1373	__IO uint32_t PORT_POL[3]; /!< GPIO grouped interrupt port 0 polarity register /
<>	128:9bcdf88f62b0	1374	__I uint32_t RESERVED1[5];
<>	128:9bcdf88f62b0	1375	__IO uint32_t PORT_ENA[3]; /!< GPIO grouped interrupt port 0 enable register /
<>	128:9bcdf88f62b0	1376	} LPC_GINT0_Type;
<>	128:9bcdf88f62b0	1377
<>	128:9bcdf88f62b0	1378
<>	128:9bcdf88f62b0	1379	/* ================================================================================ */
<>	128:9bcdf88f62b0	1380	/* ================ RIT ================ */
<>	128:9bcdf88f62b0	1381	/* ================================================================================ */
<>	128:9bcdf88f62b0	1382
<>	128:9bcdf88f62b0	1383
<>	128:9bcdf88f62b0	1384	/**
<>	128:9bcdf88f62b0	1385	* @brief Repetitive Interrupt Timer (RIT) (RIT)
<>	128:9bcdf88f62b0	1386	*/
<>	128:9bcdf88f62b0	1387
<>	128:9bcdf88f62b0	1388	typedef struct { /!< RIT Structure /
<>	128:9bcdf88f62b0	1389	__IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
<>	128:9bcdf88f62b0	1390	value. */
<>	128:9bcdf88f62b0	1391	__IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
<>	128:9bcdf88f62b0	1392	value. A 1 written to any bit will force a compare on the corresponding
<>	128:9bcdf88f62b0	1393	bit of the counter and compare register. */
<>	128:9bcdf88f62b0	1394	__IO uint32_t CTRL; /!< Control register. /
<>	128:9bcdf88f62b0	1395	__IO uint32_t COUNTER; /!< Counter LSB register. 32 LSBs of the counter. /
<>	128:9bcdf88f62b0	1396	__IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
<>	128:9bcdf88f62b0	1397	value. */
<>	128:9bcdf88f62b0	1398	__IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
<>	128:9bcdf88f62b0	1399	value. A 1 written to any bit will force a compare on the corresponding
<>	128:9bcdf88f62b0	1400	bit of the counter and compare register. */
<>	128:9bcdf88f62b0	1401	__I uint32_t RESERVED0;
<>	128:9bcdf88f62b0	1402	__IO uint32_t COUNTER_H; /!< Counter MSB register. 16 MSBs of the counter. /
<>	128:9bcdf88f62b0	1403	} LPC_RIT_Type;
<>	128:9bcdf88f62b0	1404
<>	128:9bcdf88f62b0	1405
<>	128:9bcdf88f62b0	1406	/* ================================================================================ */
<>	128:9bcdf88f62b0	1407	/* ================ SCTIPU ================ */
<>	128:9bcdf88f62b0	1408	/* ================================================================================ */
<>	128:9bcdf88f62b0	1409
<>	128:9bcdf88f62b0	1410
<>	128:9bcdf88f62b0	1411	/**
<>	128:9bcdf88f62b0	1412	* @brief SCT Input Processing Unit (IPU) (SCTIPU)
<>	128:9bcdf88f62b0	1413	*/
<>	128:9bcdf88f62b0	1414
<>	128:9bcdf88f62b0	1415	typedef struct { /!< SCTIPU Structure /
<>	128:9bcdf88f62b0	1416	__IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
<>	128:9bcdf88f62b0	1417	latch/sample-enable mux selects, and sample overrride bits for
<>	128:9bcdf88f62b0	1418	the SAMPLE module. */
<>	128:9bcdf88f62b0	1419	__I uint32_t RESERVED0[7];
<>	128:9bcdf88f62b0	1420	__IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
<>	128:9bcdf88f62b0	1421	to ORed Abort Output 0. */
<>	128:9bcdf88f62b0	1422	__IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
<>	128:9bcdf88f62b0	1423	input source caused abort output 0. */
<>	128:9bcdf88f62b0	1424	__I uint32_t RESERVED1[6];
<>	128:9bcdf88f62b0	1425	__IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
<>	128:9bcdf88f62b0	1426	to ORed Abort Output 0. */
<>	128:9bcdf88f62b0	1427	__IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
<>	128:9bcdf88f62b0	1428	input source caused abort output 0. */
<>	128:9bcdf88f62b0	1429	__I uint32_t RESERVED2[6];
<>	128:9bcdf88f62b0	1430	__IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
<>	128:9bcdf88f62b0	1431	to ORed Abort Output 0. */
<>	128:9bcdf88f62b0	1432	__IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
<>	128:9bcdf88f62b0	1433	input source caused abort output 0. */
<>	128:9bcdf88f62b0	1434	__I uint32_t RESERVED3[6];
<>	128:9bcdf88f62b0	1435	__IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
<>	128:9bcdf88f62b0	1436	to ORed Abort Output 0. */
<>	128:9bcdf88f62b0	1437	__IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
<>	128:9bcdf88f62b0	1438	input source caused abort output 0. */
<>	128:9bcdf88f62b0	1439	} LPC_SCTIPU_Type;
<>	128:9bcdf88f62b0	1440
<>	128:9bcdf88f62b0	1441
<>	128:9bcdf88f62b0	1442	/* ================================================================================ */
<>	128:9bcdf88f62b0	1443	/* ================ FLASHCTRL ================ */
<>	128:9bcdf88f62b0	1444	/* ================================================================================ */
<>	128:9bcdf88f62b0	1445
<>	128:9bcdf88f62b0	1446
<>	128:9bcdf88f62b0	1447	/**
<>	128:9bcdf88f62b0	1448	* @brief Flash controller (FLASHCTRL)
<>	128:9bcdf88f62b0	1449	*/
<>	128:9bcdf88f62b0	1450
<>	128:9bcdf88f62b0	1451	typedef struct { /!< FLASHCTRL Structure /
<>	128:9bcdf88f62b0	1452	__I uint32_t RESERVED0[8];
<>	128:9bcdf88f62b0	1453	__IO uint32_t FMSSTART; /!< Signature start address register /
<>	128:9bcdf88f62b0	1454	__IO uint32_t FMSSTOP; /!< Signature stop-address register /
<>	128:9bcdf88f62b0	1455	__I uint32_t RESERVED1;
<>	128:9bcdf88f62b0	1456	__I uint32_t FMSW0; /!< Signature word /
<>	128:9bcdf88f62b0	1457	} LPC_FLASHCTRL_Type;
<>	128:9bcdf88f62b0	1458
<>	128:9bcdf88f62b0	1459
<>	128:9bcdf88f62b0	1460	/* ================================================================================ */
<>	128:9bcdf88f62b0	1461	/* ================ C_CAN0 ================ */
<>	128:9bcdf88f62b0	1462	/* ================================================================================ */
<>	128:9bcdf88f62b0	1463
<>	128:9bcdf88f62b0	1464
<>	128:9bcdf88f62b0	1465	/**
<>	128:9bcdf88f62b0	1466	* @brief Controller Area Network C_CAN0 (C_CAN0)
<>	128:9bcdf88f62b0	1467	*/
<>	128:9bcdf88f62b0	1468
<>	128:9bcdf88f62b0	1469	typedef struct { /!< C_CAN0 Structure /
<>	128:9bcdf88f62b0	1470	__IO uint32_t CANCNTL; /!< CAN control /
<>	128:9bcdf88f62b0	1471	__IO uint32_t CANSTAT; /!< Status register /
<>	128:9bcdf88f62b0	1472	__I uint32_t CANEC; /!< Error counter /
<>	128:9bcdf88f62b0	1473	__IO uint32_t CANBT; /!< Bit timing register /
<>	128:9bcdf88f62b0	1474	__I uint32_t CANINT; /!< Interrupt register /
<>	128:9bcdf88f62b0	1475	__IO uint32_t CANTEST; /!< Test register /
<>	128:9bcdf88f62b0	1476	__IO uint32_t CANBRPE; /!< Baud rate prescaler extension register /
<>	128:9bcdf88f62b0	1477	__I uint32_t RESERVED0;
<>	128:9bcdf88f62b0	1478	__IO uint32_t CANIF1_CMDREQ; /!< Message interface 1 command request /
<>	128:9bcdf88f62b0	1479
<>	128:9bcdf88f62b0	1480	union {
<>	128:9bcdf88f62b0	1481	__IO uint32_t CANIF1_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
<>	128:9bcdf88f62b0	1482	__IO uint32_t CANIF1_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
<>	128:9bcdf88f62b0	1483	};
<>	128:9bcdf88f62b0	1484	__IO uint32_t CANIF1_MSK1; /!< Message interface 1 mask 1 /
<>	128:9bcdf88f62b0	1485	__IO uint32_t CANIF1_MSK2; /!< Message interface 1 mask 2 /
<>	128:9bcdf88f62b0	1486	__IO uint32_t CANIF1_ARB1; /!< Message interface 1 arbitration 1 /
<>	128:9bcdf88f62b0	1487	__IO uint32_t CANIF1_ARB2; /!< Message interface 1 arbitration 2 /
<>	128:9bcdf88f62b0	1488	__IO uint32_t CANIF1_MCTRL; /!< Message interface 1 message control /
<>	128:9bcdf88f62b0	1489	__IO uint32_t CANIF1_DA1; /!< Message interface 1 data A1 /
<>	128:9bcdf88f62b0	1490	__IO uint32_t CANIF1_DA2; /!< Message interface 1 data A2 /
<>	128:9bcdf88f62b0	1491	__IO uint32_t CANIF1_DB1; /!< Message interface 1 data B1 /
<>	128:9bcdf88f62b0	1492	__IO uint32_t CANIF1_DB2; /!< Message interface 1 data B2 /
<>	128:9bcdf88f62b0	1493	__I uint32_t RESERVED1[13];
<>	128:9bcdf88f62b0	1494	__IO uint32_t CANIF2_CMDREQ; /!< Message interface 1 command request /
<>	128:9bcdf88f62b0	1495
<>	128:9bcdf88f62b0	1496	union {
<>	128:9bcdf88f62b0	1497	__IO uint32_t CANIF2_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
<>	128:9bcdf88f62b0	1498	__IO uint32_t CANIF2_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
<>	128:9bcdf88f62b0	1499	};
<>	128:9bcdf88f62b0	1500	__IO uint32_t CANIF2_MSK1; /!< Message interface 1 mask 1 /
<>	128:9bcdf88f62b0	1501	__IO uint32_t CANIF2_MSK2; /!< Message interface 1 mask 2 /
<>	128:9bcdf88f62b0	1502	__IO uint32_t CANIF2_ARB1; /!< Message interface 1 arbitration 1 /
<>	128:9bcdf88f62b0	1503	__IO uint32_t CANIF2_ARB2; /!< Message interface 1 arbitration 2 /
<>	128:9bcdf88f62b0	1504	__IO uint32_t CANIF2_MCTRL; /!< Message interface 1 message control /
<>	128:9bcdf88f62b0	1505	__IO uint32_t CANIF2_DA1; /!< Message interface 2 data A1 /
<>	128:9bcdf88f62b0	1506	__IO uint32_t CANIF2_DA2; /!< Message interface 2 data A2 /
<>	128:9bcdf88f62b0	1507	__IO uint32_t CANIF2_DB1; /!< Message interface 2 data B1 /
<>	128:9bcdf88f62b0	1508	__IO uint32_t CANIF2_DB2; /!< Message interface 2 data B2 /
<>	128:9bcdf88f62b0	1509	__I uint32_t RESERVED2[21];
<>	128:9bcdf88f62b0	1510	__I uint32_t CANTXREQ1; /!< Transmission request 1 /
<>	128:9bcdf88f62b0	1511	__I uint32_t CANTXREQ2; /!< Transmission request 2 /
<>	128:9bcdf88f62b0	1512	__I uint32_t RESERVED3[6];
<>	128:9bcdf88f62b0	1513	__I uint32_t CANND1; /!< New data 1 /
<>	128:9bcdf88f62b0	1514	__I uint32_t CANND2; /!< New data 2 /
<>	128:9bcdf88f62b0	1515	__I uint32_t RESERVED4[6];
<>	128:9bcdf88f62b0	1516	__I uint32_t CANIR1; /!< Interrupt pending 1 /
<>	128:9bcdf88f62b0	1517	__I uint32_t CANIR2; /!< Interrupt pending 2 /
<>	128:9bcdf88f62b0	1518	__I uint32_t RESERVED5[6];
<>	128:9bcdf88f62b0	1519	__I uint32_t CANMSGV1; /!< Message valid 1 /
<>	128:9bcdf88f62b0	1520	__I uint32_t CANMSGV2; /!< Message valid 2 /
<>	128:9bcdf88f62b0	1521	__I uint32_t RESERVED6[6];
<>	128:9bcdf88f62b0	1522	__IO uint32_t CANCLKDIV; /!< Can clock divider register /
<>	128:9bcdf88f62b0	1523	} LPC_C_CAN0_Type;
<>	128:9bcdf88f62b0	1524
<>	128:9bcdf88f62b0	1525
<>	128:9bcdf88f62b0	1526	/* ================================================================================ */
<>	128:9bcdf88f62b0	1527	/* ================ IOCON ================ */
<>	128:9bcdf88f62b0	1528	/* ================================================================================ */
<>	128:9bcdf88f62b0	1529
<>	128:9bcdf88f62b0	1530
<>	128:9bcdf88f62b0	1531	/**
<>	128:9bcdf88f62b0	1532	* @brief I/O pin configuration (IOCON) (IOCON)
<>	128:9bcdf88f62b0	1533	*/
<>	128:9bcdf88f62b0	1534
<>	128:9bcdf88f62b0	1535	typedef struct { /!< IOCON Structure /
<>	128:9bcdf88f62b0	1536	__IO uint32_t PIO0_0; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1537	__IO uint32_t PIO0_1; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1538	__IO uint32_t PIO0_2; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1539	__IO uint32_t PIO0_3; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1540	__IO uint32_t PIO0_4; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1541	__IO uint32_t PIO0_5; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1542	__IO uint32_t PIO0_6; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1543	__IO uint32_t PIO0_7; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1544	__IO uint32_t PIO0_8; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1545	__IO uint32_t PIO0_9; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1546	__IO uint32_t PIO0_10; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1547	__IO uint32_t PIO0_11; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1548	__IO uint32_t PIO0_12; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1549	__IO uint32_t PIO0_13; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1550	__IO uint32_t PIO0_14; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1551	__IO uint32_t PIO0_15; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1552	__IO uint32_t PIO0_16; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1553	__IO uint32_t PIO0_17; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1554	__IO uint32_t PIO0_18; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1555	__IO uint32_t PIO0_19; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1556	__IO uint32_t PIO0_20; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1557	__IO uint32_t PIO0_21; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
<>	128:9bcdf88f62b0	1558	__IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
<>	128:9bcdf88f62b0	1559	the I2C-bus SCL function. */
<>	128:9bcdf88f62b0	1560	__IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
<>	128:9bcdf88f62b0	1561	the I2C-bus SCL function. */
<>	128:9bcdf88f62b0	1562	__IO uint32_t PIO0_24; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	128:9bcdf88f62b0	1563	__IO uint32_t PIO0_25; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	128:9bcdf88f62b0	1564	__IO uint32_t PIO0_26; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	128:9bcdf88f62b0	1565	__IO uint32_t PIO0_27; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	128:9bcdf88f62b0	1566	__IO uint32_t PIO0_28; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	128:9bcdf88f62b0	1567	__IO uint32_t PIO0_29; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	128:9bcdf88f62b0	1568	__IO uint32_t PIO0_30; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	128:9bcdf88f62b0	1569	__IO uint32_t PIO0_31; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
<>	128:9bcdf88f62b0	1570	__IO uint32_t PIO1_0; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1571	__IO uint32_t PIO1_1; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1572	__IO uint32_t PIO1_2; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1573	__IO uint32_t PIO1_3; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1574	__IO uint32_t PIO1_4; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1575	__IO uint32_t PIO1_5; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1576	__IO uint32_t PIO1_6; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1577	__IO uint32_t PIO1_7; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1578	__IO uint32_t PIO1_8; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1579	__IO uint32_t PIO1_9; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1580	__IO uint32_t PIO1_10; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1581	__IO uint32_t PIO1_11; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1582	__IO uint32_t PIO1_12; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1583	__IO uint32_t PIO1_13; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1584	__IO uint32_t PIO1_14; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1585	__IO uint32_t PIO1_15; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1586	__IO uint32_t PIO1_16; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1587	__IO uint32_t PIO1_17; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1588	__IO uint32_t PIO1_18; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1589	__IO uint32_t PIO1_19; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1590	__IO uint32_t PIO1_20; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1591	__IO uint32_t PIO1_21; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1592	__IO uint32_t PIO1_22; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1593	__IO uint32_t PIO1_23; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1594	__IO uint32_t PIO1_24; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1595	__IO uint32_t PIO1_25; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1596	__IO uint32_t PIO1_26; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1597	__IO uint32_t PIO1_27; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1598	__IO uint32_t PIO1_28; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1599	__IO uint32_t PIO1_29; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1600	__IO uint32_t PIO1_30; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1601	__IO uint32_t PIO1_31; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
<>	128:9bcdf88f62b0	1602	__IO uint32_t PIO2_0; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	128:9bcdf88f62b0	1603	__IO uint32_t PIO2_1; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	128:9bcdf88f62b0	1604	__IO uint32_t PIO2_2; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	128:9bcdf88f62b0	1605	__IO uint32_t PIO2_3; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	128:9bcdf88f62b0	1606	__IO uint32_t PIO2_4; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	128:9bcdf88f62b0	1607	__IO uint32_t PIO2_5; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	128:9bcdf88f62b0	1608	__IO uint32_t PIO2_6; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	128:9bcdf88f62b0	1609	__IO uint32_t PIO2_7; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	128:9bcdf88f62b0	1610	__IO uint32_t PIO2_8; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	128:9bcdf88f62b0	1611	__IO uint32_t PIO2_9; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	128:9bcdf88f62b0	1612	__IO uint32_t PIO2_10; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	128:9bcdf88f62b0	1613	__IO uint32_t PIO2_11; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
<>	128:9bcdf88f62b0	1614	} LPC_IOCON_Type;
<>	128:9bcdf88f62b0	1615
<>	128:9bcdf88f62b0	1616
<>	128:9bcdf88f62b0	1617	/* -------------------- End of section using anonymous unions ------------------- */
<>	128:9bcdf88f62b0	1618	#if defined(__CC_ARM)
<>	128:9bcdf88f62b0	1619	#pragma pop
<>	128:9bcdf88f62b0	1620	#elif defined(__ICCARM__)
<>	128:9bcdf88f62b0	1621	/* leave anonymous unions enabled */
<>	128:9bcdf88f62b0	1622	#elif defined(__GNUC__)
<>	128:9bcdf88f62b0	1623	/* anonymous unions are enabled by default */
<>	128:9bcdf88f62b0	1624	#elif defined(__TMS470__)
<>	128:9bcdf88f62b0	1625	/* anonymous unions are enabled by default */
<>	128:9bcdf88f62b0	1626	#elif defined(__TASKING__)
<>	128:9bcdf88f62b0	1627	#pragma warning restore
<>	128:9bcdf88f62b0	1628	#else
<>	128:9bcdf88f62b0	1629	#warning Not supported compiler type
<>	128:9bcdf88f62b0	1630	#endif
<>	128:9bcdf88f62b0	1631
<>	128:9bcdf88f62b0	1632
<>	128:9bcdf88f62b0	1633
<>	128:9bcdf88f62b0	1634
<>	128:9bcdf88f62b0	1635	/* ================================================================================ */
<>	128:9bcdf88f62b0	1636	/* ================ Peripheral memory map ================ */
<>	128:9bcdf88f62b0	1637	/* ================================================================================ */
<>	128:9bcdf88f62b0	1638
<>	128:9bcdf88f62b0	1639	#define LPC_GPIO_PORT_BASE 0x1C000000UL
<>	128:9bcdf88f62b0	1640	#define LPC_DMA_BASE 0x1C004000UL
<>	128:9bcdf88f62b0	1641	#define LPC_USB_BASE 0x1C00C000UL
<>	128:9bcdf88f62b0	1642	#define LPC_CRC_BASE 0x1C010000UL
<>	128:9bcdf88f62b0	1643	#define LPC_SCT0_BASE 0x1C018000UL
<>	128:9bcdf88f62b0	1644	#define LPC_SCT1_BASE 0x1C01C000UL
<>	128:9bcdf88f62b0	1645	#define LPC_SCT2_BASE 0x1C020000UL
<>	128:9bcdf88f62b0	1646	#define LPC_SCT3_BASE 0x1C024000UL
<>	128:9bcdf88f62b0	1647	#define LPC_ADC0_BASE 0x40000000UL
<>	128:9bcdf88f62b0	1648	#define LPC_DAC_BASE 0x40004000UL
<>	128:9bcdf88f62b0	1649	#define LPC_ACMP_BASE 0x40008000UL
<>	128:9bcdf88f62b0	1650	#define LPC_INMUX_BASE 0x40014000UL
<>	128:9bcdf88f62b0	1651	#define LPC_RTC_BASE 0x40028000UL
<>	128:9bcdf88f62b0	1652	#define LPC_WWDT_BASE 0x4002C000UL
<>	128:9bcdf88f62b0	1653	#define LPC_SWM_BASE 0x40038000UL
<>	128:9bcdf88f62b0	1654	#define LPC_PMU_BASE 0x4003C000UL
<>	128:9bcdf88f62b0	1655	#define LPC_USART0_BASE 0x40040000UL
<>	128:9bcdf88f62b0	1656	#define LPC_USART1_BASE 0x40044000UL
<>	128:9bcdf88f62b0	1657	#define LPC_SPI0_BASE 0x40048000UL
<>	128:9bcdf88f62b0	1658	#define LPC_SPI1_BASE 0x4004C000UL
<>	128:9bcdf88f62b0	1659	#define LPC_I2C0_BASE 0x40050000UL
<>	128:9bcdf88f62b0	1660	#define LPC_QEI_BASE 0x40058000UL
<>	128:9bcdf88f62b0	1661	#define LPC_SYSCON_BASE 0x40074000UL
<>	128:9bcdf88f62b0	1662	#define LPC_ADC1_BASE 0x40080000UL
<>	128:9bcdf88f62b0	1663	#define LPC_MRT_BASE 0x400A0000UL
<>	128:9bcdf88f62b0	1664	#define LPC_PINT_BASE 0x400A4000UL
<>	128:9bcdf88f62b0	1665	#define LPC_GINT0_BASE 0x400A8000UL
<>	128:9bcdf88f62b0	1666	#define LPC_GINT1_BASE 0x400AC000UL
<>	128:9bcdf88f62b0	1667	#define LPC_RIT_BASE 0x400B4000UL
<>	128:9bcdf88f62b0	1668	#define LPC_SCTIPU_BASE 0x400B8000UL
<>	128:9bcdf88f62b0	1669	#define LPC_FLASHCTRL_BASE 0x400BC000UL
<>	128:9bcdf88f62b0	1670	#define LPC_USART2_BASE 0x400C0000UL
<>	128:9bcdf88f62b0	1671	#define LPC_C_CAN0_BASE 0x400F0000UL
<>	128:9bcdf88f62b0	1672	#define LPC_IOCON_BASE 0x400F8000UL
<>	128:9bcdf88f62b0	1673
<>	128:9bcdf88f62b0	1674
<>	128:9bcdf88f62b0	1675	/* ================================================================================ */
<>	128:9bcdf88f62b0	1676	/* ================ Peripheral declaration ================ */
<>	128:9bcdf88f62b0	1677	/* ================================================================================ */
<>	128:9bcdf88f62b0	1678
<>	128:9bcdf88f62b0	1679	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
<>	128:9bcdf88f62b0	1680	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
<>	128:9bcdf88f62b0	1681	#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
<>	128:9bcdf88f62b0	1682	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
<>	128:9bcdf88f62b0	1683	#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
<>	128:9bcdf88f62b0	1684	#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
<>	128:9bcdf88f62b0	1685	#define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
<>	128:9bcdf88f62b0	1686	#define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
<>	128:9bcdf88f62b0	1687	#define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
<>	128:9bcdf88f62b0	1688	#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
<>	128:9bcdf88f62b0	1689	#define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
<>	128:9bcdf88f62b0	1690	#define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
<>	128:9bcdf88f62b0	1691	#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
<>	128:9bcdf88f62b0	1692	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
<>	128:9bcdf88f62b0	1693	#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
<>	128:9bcdf88f62b0	1694	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
<>	128:9bcdf88f62b0	1695	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
<>	128:9bcdf88f62b0	1696	#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
<>	128:9bcdf88f62b0	1697	#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
<>	128:9bcdf88f62b0	1698	#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
<>	128:9bcdf88f62b0	1699	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
<>	128:9bcdf88f62b0	1700	#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
<>	128:9bcdf88f62b0	1701	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
<>	128:9bcdf88f62b0	1702	#define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
<>	128:9bcdf88f62b0	1703	#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
<>	128:9bcdf88f62b0	1704	#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
<>	128:9bcdf88f62b0	1705	#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
<>	128:9bcdf88f62b0	1706	#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
<>	128:9bcdf88f62b0	1707	#define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
<>	128:9bcdf88f62b0	1708	#define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
<>	128:9bcdf88f62b0	1709	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
<>	128:9bcdf88f62b0	1710	#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
<>	128:9bcdf88f62b0	1711	#define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
<>	128:9bcdf88f62b0	1712	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
<>	128:9bcdf88f62b0	1713
<>	128:9bcdf88f62b0	1714
<>	128:9bcdf88f62b0	1715	/** @} / / End of group Device_Peripheral_Registers */
<>	128:9bcdf88f62b0	1716	/** @} / / End of group LPC15xx */
<>	128:9bcdf88f62b0	1717	/** @} / / End of group (null) */
<>	128:9bcdf88f62b0	1718
<>	128:9bcdf88f62b0	1719	#ifdef __cplusplus
<>	128:9bcdf88f62b0	1720	}
<>	128:9bcdf88f62b0	1721	#endif
<>	128:9bcdf88f62b0	1722
<>	128:9bcdf88f62b0	1723
<>	128:9bcdf88f62b0	1724	#endif /* LPC15XX_H */
<>	128:9bcdf88f62b0	1725