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TARGET_KL05Z/TARGET_Freescale/TARGET_KLXX/clk_freqs.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:39:34 2018 +0100
Revision:
170:e95d10626187
Parent:
156:ff21514d8981 
mbed library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /* mbed Microcontroller Library
AnnaBridge 156:ff21514d8981 2 * Copyright (c) 2006-2013 ARM Limited
AnnaBridge 156:ff21514d8981 3 *
AnnaBridge 156:ff21514d8981 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 156:ff21514d8981 5 * you may not use this file except in compliance with the License.
AnnaBridge 156:ff21514d8981 6 * You may obtain a copy of the License at
AnnaBridge 156:ff21514d8981 7 *
AnnaBridge 156:ff21514d8981 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 156:ff21514d8981 9 *
AnnaBridge 156:ff21514d8981 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 156:ff21514d8981 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 156:ff21514d8981 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 156:ff21514d8981 13 * See the License for the specific language governing permissions and
AnnaBridge 156:ff21514d8981 14 * limitations under the License.
AnnaBridge 156:ff21514d8981 15 */
AnnaBridge 156:ff21514d8981 16 #ifndef MBED_CLK_FREQS_H
AnnaBridge 156:ff21514d8981 17 #define MBED_CLK_FREQS_H
AnnaBridge 156:ff21514d8981 18
AnnaBridge 156:ff21514d8981 19 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 20 extern "C" {
AnnaBridge 156:ff21514d8981 21 #endif
AnnaBridge 156:ff21514d8981 22
AnnaBridge 156:ff21514d8981 23 #include "PeripheralPins.h"
AnnaBridge 156:ff21514d8981 24
AnnaBridge 156:ff21514d8981 25 //Get the peripheral bus clock frequency
AnnaBridge 156:ff21514d8981 26 static inline uint32_t bus_frequency(void) {
AnnaBridge 156:ff21514d8981 27 return (SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1));
AnnaBridge 156:ff21514d8981 28 }
AnnaBridge 156:ff21514d8981 29
AnnaBridge 156:ff21514d8981 30 #if defined(TARGET_KL43Z)
AnnaBridge 156:ff21514d8981 31
AnnaBridge 156:ff21514d8981 32 static inline uint32_t extosc_frequency(void) {
AnnaBridge 156:ff21514d8981 33 return CPU_XTAL_CLK_HZ;
AnnaBridge 156:ff21514d8981 34 }
AnnaBridge 156:ff21514d8981 35
AnnaBridge 156:ff21514d8981 36 static inline uint32_t fastirc_frequency(void) {
AnnaBridge 156:ff21514d8981 37 return CPU_INT_FAST_CLK_HZ;
AnnaBridge 156:ff21514d8981 38 }
AnnaBridge 156:ff21514d8981 39
AnnaBridge 156:ff21514d8981 40 static inline uint32_t mcgirc_frequency(void) {
AnnaBridge 156:ff21514d8981 41 uint32_t mcgirc_clock = 0;
AnnaBridge 156:ff21514d8981 42
AnnaBridge 156:ff21514d8981 43 if (MCG->C1 & MCG_C1_IREFSTEN_MASK) {
AnnaBridge 156:ff21514d8981 44 mcgirc_clock = (MCG->C2 & MCG_C2_IRCS_MASK) ? 8000000u : 2000000u;
AnnaBridge 156:ff21514d8981 45 mcgirc_clock /= 1u + ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT);
AnnaBridge 156:ff21514d8981 46 mcgirc_clock /= 1u + (MCG->MC & MCG_MC_LIRC_DIV2_MASK);
AnnaBridge 156:ff21514d8981 47 }
AnnaBridge 156:ff21514d8981 48
AnnaBridge 156:ff21514d8981 49 return mcgirc_clock;
AnnaBridge 156:ff21514d8981 50 }
AnnaBridge 156:ff21514d8981 51
AnnaBridge 156:ff21514d8981 52 #else
AnnaBridge 156:ff21514d8981 53
AnnaBridge 156:ff21514d8981 54 //Get external oscillator (crystal) frequency
AnnaBridge 156:ff21514d8981 55 static uint32_t extosc_frequency(void) {
AnnaBridge 156:ff21514d8981 56 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
AnnaBridge 156:ff21514d8981 57
AnnaBridge 156:ff21514d8981 58 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
AnnaBridge 156:ff21514d8981 59 return MCGClock;
AnnaBridge 156:ff21514d8981 60
AnnaBridge 156:ff21514d8981 61 uint32_t divider, multiplier;
AnnaBridge 156:ff21514d8981 62 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
AnnaBridge 156:ff21514d8981 63 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
AnnaBridge 156:ff21514d8981 64 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
AnnaBridge 156:ff21514d8981 65 #endif
AnnaBridge 156:ff21514d8981 66 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
AnnaBridge 156:ff21514d8981 67 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
AnnaBridge 156:ff21514d8981 68 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
AnnaBridge 156:ff21514d8981 69 divider <<= 5u;
AnnaBridge 156:ff21514d8981 70 /* Select correct multiplier to calculate the MCG output clock */
AnnaBridge 156:ff21514d8981 71 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
AnnaBridge 156:ff21514d8981 72 case 0x0u:
AnnaBridge 156:ff21514d8981 73 multiplier = 640u;
AnnaBridge 156:ff21514d8981 74 break;
AnnaBridge 156:ff21514d8981 75 case 0x20u:
AnnaBridge 156:ff21514d8981 76 multiplier = 1280u;
AnnaBridge 156:ff21514d8981 77 break;
AnnaBridge 156:ff21514d8981 78 case 0x40u:
AnnaBridge 156:ff21514d8981 79 multiplier = 1920u;
AnnaBridge 156:ff21514d8981 80 break;
AnnaBridge 156:ff21514d8981 81 case 0x60u:
AnnaBridge 156:ff21514d8981 82 multiplier = 2560u;
AnnaBridge 156:ff21514d8981 83 break;
AnnaBridge 156:ff21514d8981 84 case 0x80u:
AnnaBridge 156:ff21514d8981 85 multiplier = 732u;
AnnaBridge 156:ff21514d8981 86 break;
AnnaBridge 156:ff21514d8981 87 case 0xA0u:
AnnaBridge 156:ff21514d8981 88 multiplier = 1464u;
AnnaBridge 156:ff21514d8981 89 break;
AnnaBridge 156:ff21514d8981 90 case 0xC0u:
AnnaBridge 156:ff21514d8981 91 multiplier = 2197u;
AnnaBridge 156:ff21514d8981 92 break;
AnnaBridge 156:ff21514d8981 93 case 0xE0u:
AnnaBridge 156:ff21514d8981 94 default:
AnnaBridge 156:ff21514d8981 95 multiplier = 2929u;
AnnaBridge 156:ff21514d8981 96 break;
AnnaBridge 156:ff21514d8981 97 }
AnnaBridge 156:ff21514d8981 98
AnnaBridge 156:ff21514d8981 99 return MCGClock * divider / multiplier;
AnnaBridge 156:ff21514d8981 100 }
AnnaBridge 156:ff21514d8981 101 #ifdef MCG_C5_PLLCLKEN0_MASK
AnnaBridge 156:ff21514d8981 102 } else { //PLL is selected
AnnaBridge 156:ff21514d8981 103 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
AnnaBridge 156:ff21514d8981 104 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
AnnaBridge 156:ff21514d8981 105 return MCGClock * divider / multiplier;
AnnaBridge 156:ff21514d8981 106 }
AnnaBridge 156:ff21514d8981 107 }
AnnaBridge 156:ff21514d8981 108 #endif
AnnaBridge 156:ff21514d8981 109
AnnaBridge 156:ff21514d8981 110 //In all other cases either there is no crystal or we cannot determine it
AnnaBridge 156:ff21514d8981 111 //For example when the FLL is running on the internal reference, and there is also an
AnnaBridge 156:ff21514d8981 112 //external crystal. However these are unlikely situations
AnnaBridge 156:ff21514d8981 113 return 0;
AnnaBridge 156:ff21514d8981 114 }
AnnaBridge 156:ff21514d8981 115
AnnaBridge 156:ff21514d8981 116 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
AnnaBridge 156:ff21514d8981 117 static uint32_t mcgpllfll_frequency(void) {
AnnaBridge 156:ff21514d8981 118 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
AnnaBridge 156:ff21514d8981 119 return 0;
AnnaBridge 156:ff21514d8981 120
AnnaBridge 156:ff21514d8981 121 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
AnnaBridge 156:ff21514d8981 122 #ifdef MCG_C5_PLLCLKEN0_MASK
AnnaBridge 156:ff21514d8981 123 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
AnnaBridge 156:ff21514d8981 124 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
AnnaBridge 156:ff21514d8981 125 #endif
AnnaBridge 156:ff21514d8981 126 return MCGClock;
AnnaBridge 156:ff21514d8981 127 #ifdef MCG_C5_PLLCLKEN0_MASK
AnnaBridge 156:ff21514d8981 128 } else { //PLL is selected
AnnaBridge 156:ff21514d8981 129 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
AnnaBridge 156:ff21514d8981 130 return (MCGClock >> 1);
AnnaBridge 156:ff21514d8981 131 }
AnnaBridge 156:ff21514d8981 132 #endif
AnnaBridge 156:ff21514d8981 133
AnnaBridge 156:ff21514d8981 134 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
AnnaBridge 156:ff21514d8981 135 //for the peripherals, this is however an unlikely setup
AnnaBridge 156:ff21514d8981 136 }
AnnaBridge 156:ff21514d8981 137
AnnaBridge 156:ff21514d8981 138 #endif
AnnaBridge 156:ff21514d8981 139
AnnaBridge 156:ff21514d8981 140 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 141 }
AnnaBridge 156:ff21514d8981 142 #endif
AnnaBridge 156:ff21514d8981 143
AnnaBridge 156:ff21514d8981 144 #endif