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TARGET_GR_LYCHEE/cmsis_gcc.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:39:34 2018 +0100
Revision:
170:e95d10626187
Parent:
169:a7c7b631e539 
mbed library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 /**************************************************************************//**
AnnaBridge 161:aa5281ff4a02 2 * @file cmsis_gcc.h
AnnaBridge 161:aa5281ff4a02 3 * @brief CMSIS compiler specific macros, functions, instructions
AnnaBridge 161:aa5281ff4a02 4 * @version V1.0.1
AnnaBridge 161:aa5281ff4a02 5 * @date 07. Sep 2017
AnnaBridge 161:aa5281ff4a02 6 ******************************************************************************/
AnnaBridge 161:aa5281ff4a02 7 /*
AnnaBridge 161:aa5281ff4a02 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 161:aa5281ff4a02 9 *
AnnaBridge 161:aa5281ff4a02 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 161:aa5281ff4a02 11 *
AnnaBridge 161:aa5281ff4a02 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 161:aa5281ff4a02 13 * not use this file except in compliance with the License.
AnnaBridge 161:aa5281ff4a02 14 * You may obtain a copy of the License at
AnnaBridge 161:aa5281ff4a02 15 *
AnnaBridge 161:aa5281ff4a02 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 161:aa5281ff4a02 17 *
AnnaBridge 161:aa5281ff4a02 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 161:aa5281ff4a02 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 161:aa5281ff4a02 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 161:aa5281ff4a02 21 * See the License for the specific language governing permissions and
AnnaBridge 161:aa5281ff4a02 22 * limitations under the License.
AnnaBridge 161:aa5281ff4a02 23 */
AnnaBridge 161:aa5281ff4a02 24
AnnaBridge 161:aa5281ff4a02 25 #ifndef __CMSIS_GCC_H
AnnaBridge 161:aa5281ff4a02 26 #define __CMSIS_GCC_H
AnnaBridge 161:aa5281ff4a02 27
AnnaBridge 161:aa5281ff4a02 28 /* ignore some GCC warnings */
AnnaBridge 161:aa5281ff4a02 29 #pragma GCC diagnostic push
AnnaBridge 161:aa5281ff4a02 30 #pragma GCC diagnostic ignored "-Wsign-conversion"
AnnaBridge 161:aa5281ff4a02 31 #pragma GCC diagnostic ignored "-Wconversion"
AnnaBridge 161:aa5281ff4a02 32 #pragma GCC diagnostic ignored "-Wunused-parameter"
AnnaBridge 161:aa5281ff4a02 33
AnnaBridge 161:aa5281ff4a02 34 /* Fallback for __has_builtin */
AnnaBridge 161:aa5281ff4a02 35 #ifndef __has_builtin
AnnaBridge 161:aa5281ff4a02 36 #define __has_builtin(x) (0)
AnnaBridge 161:aa5281ff4a02 37 #endif
AnnaBridge 161:aa5281ff4a02 38
AnnaBridge 161:aa5281ff4a02 39 /* CMSIS compiler specific defines */
AnnaBridge 161:aa5281ff4a02 40 #ifndef __ASM
AnnaBridge 161:aa5281ff4a02 41 #define __ASM asm
AnnaBridge 161:aa5281ff4a02 42 #endif
AnnaBridge 161:aa5281ff4a02 43 #ifndef __INLINE
AnnaBridge 161:aa5281ff4a02 44 #define __INLINE inline
AnnaBridge 161:aa5281ff4a02 45 #endif
AnnaBridge 161:aa5281ff4a02 46 #ifndef __FORCEINLINE
AnnaBridge 161:aa5281ff4a02 47 #define __FORCEINLINE __attribute__((always_inline))
AnnaBridge 161:aa5281ff4a02 48 #endif
AnnaBridge 161:aa5281ff4a02 49 #ifndef __STATIC_INLINE
AnnaBridge 161:aa5281ff4a02 50 #define __STATIC_INLINE static inline
AnnaBridge 161:aa5281ff4a02 51 #endif
AnnaBridge 161:aa5281ff4a02 52 #ifndef __STATIC_FORCEINLINE
AnnaBridge 161:aa5281ff4a02 53 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
AnnaBridge 161:aa5281ff4a02 54 #endif
AnnaBridge 161:aa5281ff4a02 55 #ifndef __NO_RETURN
AnnaBridge 161:aa5281ff4a02 56 #define __NO_RETURN __attribute__((__noreturn__))
AnnaBridge 161:aa5281ff4a02 57 #endif
AnnaBridge 161:aa5281ff4a02 58 #ifndef CMSIS_DEPRECATED
AnnaBridge 161:aa5281ff4a02 59 #define CMSIS_DEPRECATED __attribute__((deprecated))
AnnaBridge 161:aa5281ff4a02 60 #endif
AnnaBridge 161:aa5281ff4a02 61 #ifndef __USED
AnnaBridge 161:aa5281ff4a02 62 #define __USED __attribute__((used))
AnnaBridge 161:aa5281ff4a02 63 #endif
AnnaBridge 161:aa5281ff4a02 64 #ifndef __WEAK
AnnaBridge 161:aa5281ff4a02 65 #define __WEAK __attribute__((weak))
AnnaBridge 161:aa5281ff4a02 66 #endif
AnnaBridge 161:aa5281ff4a02 67 #ifndef __PACKED
AnnaBridge 161:aa5281ff4a02 68 #define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge 161:aa5281ff4a02 69 #endif
AnnaBridge 161:aa5281ff4a02 70 #ifndef __PACKED_STRUCT
AnnaBridge 161:aa5281ff4a02 71 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge 161:aa5281ff4a02 72 #endif
AnnaBridge 161:aa5281ff4a02 73 #ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge 161:aa5281ff4a02 74 #pragma GCC diagnostic push
AnnaBridge 161:aa5281ff4a02 75 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 161:aa5281ff4a02 76 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
AnnaBridge 161:aa5281ff4a02 77 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge 161:aa5281ff4a02 78 #pragma GCC diagnostic pop
AnnaBridge 161:aa5281ff4a02 79 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 161:aa5281ff4a02 80 #endif
AnnaBridge 161:aa5281ff4a02 81 #ifndef __UNALIGNED_UINT16_READ
AnnaBridge 161:aa5281ff4a02 82 #pragma GCC diagnostic push
AnnaBridge 161:aa5281ff4a02 83 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 161:aa5281ff4a02 84 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
AnnaBridge 161:aa5281ff4a02 85 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge 161:aa5281ff4a02 86 #pragma GCC diagnostic pop
AnnaBridge 161:aa5281ff4a02 87 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
AnnaBridge 161:aa5281ff4a02 88 #endif
AnnaBridge 161:aa5281ff4a02 89 #ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge 161:aa5281ff4a02 90 #pragma GCC diagnostic push
AnnaBridge 161:aa5281ff4a02 91 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 161:aa5281ff4a02 92 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
AnnaBridge 161:aa5281ff4a02 93 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge 161:aa5281ff4a02 94 #pragma GCC diagnostic pop
AnnaBridge 161:aa5281ff4a02 95 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 161:aa5281ff4a02 96 #endif
AnnaBridge 161:aa5281ff4a02 97 #ifndef __UNALIGNED_UINT32_READ
AnnaBridge 161:aa5281ff4a02 98 #pragma GCC diagnostic push
AnnaBridge 161:aa5281ff4a02 99 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 161:aa5281ff4a02 100 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge 161:aa5281ff4a02 101 #pragma GCC diagnostic pop
AnnaBridge 161:aa5281ff4a02 102 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
AnnaBridge 161:aa5281ff4a02 103 #endif
AnnaBridge 161:aa5281ff4a02 104 #ifndef __ALIGNED
AnnaBridge 161:aa5281ff4a02 105 #define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge 161:aa5281ff4a02 106 #endif
AnnaBridge 161:aa5281ff4a02 107
AnnaBridge 161:aa5281ff4a02 108 /* ########################## Core Instruction Access ######################### */
AnnaBridge 161:aa5281ff4a02 109 /**
AnnaBridge 161:aa5281ff4a02 110 \brief No Operation
AnnaBridge 161:aa5281ff4a02 111 */
AnnaBridge 161:aa5281ff4a02 112 #define __NOP() __ASM volatile ("nop")
AnnaBridge 161:aa5281ff4a02 113
AnnaBridge 161:aa5281ff4a02 114 /**
AnnaBridge 161:aa5281ff4a02 115 \brief Wait For Interrupt
AnnaBridge 161:aa5281ff4a02 116 */
AnnaBridge 161:aa5281ff4a02 117 #define __WFI() __ASM volatile ("wfi")
AnnaBridge 161:aa5281ff4a02 118
AnnaBridge 161:aa5281ff4a02 119 /**
AnnaBridge 161:aa5281ff4a02 120 \brief Wait For Event
AnnaBridge 161:aa5281ff4a02 121 */
AnnaBridge 161:aa5281ff4a02 122 #define __WFE() __ASM volatile ("wfe")
AnnaBridge 161:aa5281ff4a02 123
AnnaBridge 161:aa5281ff4a02 124 /**
AnnaBridge 161:aa5281ff4a02 125 \brief Send Event
AnnaBridge 161:aa5281ff4a02 126 */
AnnaBridge 161:aa5281ff4a02 127 #define __SEV() __ASM volatile ("sev")
AnnaBridge 161:aa5281ff4a02 128
AnnaBridge 161:aa5281ff4a02 129 /**
AnnaBridge 161:aa5281ff4a02 130 \brief Instruction Synchronization Barrier
AnnaBridge 161:aa5281ff4a02 131 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge 161:aa5281ff4a02 132 so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge 161:aa5281ff4a02 133 after the instruction has been completed.
AnnaBridge 161:aa5281ff4a02 134 */
AnnaBridge 161:aa5281ff4a02 135 __STATIC_FORCEINLINE void __ISB(void)
AnnaBridge 161:aa5281ff4a02 136 {
AnnaBridge 161:aa5281ff4a02 137 __ASM volatile ("isb 0xF":::"memory");
AnnaBridge 161:aa5281ff4a02 138 }
AnnaBridge 161:aa5281ff4a02 139
AnnaBridge 161:aa5281ff4a02 140
AnnaBridge 161:aa5281ff4a02 141 /**
AnnaBridge 161:aa5281ff4a02 142 \brief Data Synchronization Barrier
AnnaBridge 161:aa5281ff4a02 143 \details Acts as a special kind of Data Memory Barrier.
AnnaBridge 161:aa5281ff4a02 144 It completes when all explicit memory accesses before this instruction complete.
AnnaBridge 161:aa5281ff4a02 145 */
AnnaBridge 161:aa5281ff4a02 146 __STATIC_FORCEINLINE void __DSB(void)
AnnaBridge 161:aa5281ff4a02 147 {
AnnaBridge 161:aa5281ff4a02 148 __ASM volatile ("dsb 0xF":::"memory");
AnnaBridge 161:aa5281ff4a02 149 }
AnnaBridge 161:aa5281ff4a02 150
AnnaBridge 161:aa5281ff4a02 151 /**
AnnaBridge 161:aa5281ff4a02 152 \brief Data Memory Barrier
AnnaBridge 161:aa5281ff4a02 153 \details Ensures the apparent order of the explicit memory operations before
AnnaBridge 161:aa5281ff4a02 154 and after the instruction, without ensuring their completion.
AnnaBridge 161:aa5281ff4a02 155 */
AnnaBridge 161:aa5281ff4a02 156 __STATIC_FORCEINLINE void __DMB(void)
AnnaBridge 161:aa5281ff4a02 157 {
AnnaBridge 161:aa5281ff4a02 158 __ASM volatile ("dmb 0xF":::"memory");
AnnaBridge 161:aa5281ff4a02 159 }
AnnaBridge 161:aa5281ff4a02 160
AnnaBridge 161:aa5281ff4a02 161 /**
AnnaBridge 161:aa5281ff4a02 162 \brief Reverse byte order (32 bit)
AnnaBridge 161:aa5281ff4a02 163 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
AnnaBridge 161:aa5281ff4a02 164 \param [in] value Value to reverse
AnnaBridge 161:aa5281ff4a02 165 \return Reversed value
AnnaBridge 161:aa5281ff4a02 166 */
AnnaBridge 161:aa5281ff4a02 167 __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
AnnaBridge 161:aa5281ff4a02 168 {
AnnaBridge 161:aa5281ff4a02 169 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
AnnaBridge 161:aa5281ff4a02 170 return __builtin_bswap32(value);
AnnaBridge 161:aa5281ff4a02 171 #else
AnnaBridge 161:aa5281ff4a02 172 uint32_t result;
AnnaBridge 161:aa5281ff4a02 173
AnnaBridge 161:aa5281ff4a02 174 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 161:aa5281ff4a02 175 return result;
AnnaBridge 161:aa5281ff4a02 176 #endif
AnnaBridge 161:aa5281ff4a02 177 }
AnnaBridge 161:aa5281ff4a02 178
AnnaBridge 161:aa5281ff4a02 179 /**
AnnaBridge 161:aa5281ff4a02 180 \brief Reverse byte order (16 bit)
AnnaBridge 161:aa5281ff4a02 181 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
AnnaBridge 161:aa5281ff4a02 182 \param [in] value Value to reverse
AnnaBridge 161:aa5281ff4a02 183 \return Reversed value
AnnaBridge 161:aa5281ff4a02 184 */
AnnaBridge 161:aa5281ff4a02 185 #ifndef __NO_EMBEDDED_ASM
AnnaBridge 161:aa5281ff4a02 186 __attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
AnnaBridge 161:aa5281ff4a02 187 {
AnnaBridge 161:aa5281ff4a02 188 uint32_t result;
AnnaBridge 161:aa5281ff4a02 189 __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
AnnaBridge 161:aa5281ff4a02 190 return result;
AnnaBridge 161:aa5281ff4a02 191 }
AnnaBridge 161:aa5281ff4a02 192 #endif
AnnaBridge 161:aa5281ff4a02 193
AnnaBridge 161:aa5281ff4a02 194 /**
AnnaBridge 161:aa5281ff4a02 195 \brief Reverse byte order (16 bit)
AnnaBridge 161:aa5281ff4a02 196 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
AnnaBridge 161:aa5281ff4a02 197 \param [in] value Value to reverse
AnnaBridge 161:aa5281ff4a02 198 \return Reversed value
AnnaBridge 161:aa5281ff4a02 199 */
AnnaBridge 161:aa5281ff4a02 200 __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
AnnaBridge 161:aa5281ff4a02 201 {
AnnaBridge 161:aa5281ff4a02 202 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 161:aa5281ff4a02 203 return (int16_t)__builtin_bswap16(value);
AnnaBridge 161:aa5281ff4a02 204 #else
AnnaBridge 161:aa5281ff4a02 205 int16_t result;
AnnaBridge 161:aa5281ff4a02 206
AnnaBridge 161:aa5281ff4a02 207 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 161:aa5281ff4a02 208 return result;
AnnaBridge 161:aa5281ff4a02 209 #endif
AnnaBridge 161:aa5281ff4a02 210 }
AnnaBridge 161:aa5281ff4a02 211
AnnaBridge 161:aa5281ff4a02 212 /**
AnnaBridge 161:aa5281ff4a02 213 \brief Rotate Right in unsigned value (32 bit)
AnnaBridge 161:aa5281ff4a02 214 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge 161:aa5281ff4a02 215 \param [in] op1 Value to rotate
AnnaBridge 161:aa5281ff4a02 216 \param [in] op2 Number of Bits to rotate
AnnaBridge 161:aa5281ff4a02 217 \return Rotated value
AnnaBridge 161:aa5281ff4a02 218 */
AnnaBridge 161:aa5281ff4a02 219 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge 161:aa5281ff4a02 220 {
AnnaBridge 161:aa5281ff4a02 221 op2 %= 32U;
AnnaBridge 161:aa5281ff4a02 222 if (op2 == 0U) {
AnnaBridge 161:aa5281ff4a02 223 return op1;
AnnaBridge 161:aa5281ff4a02 224 }
AnnaBridge 161:aa5281ff4a02 225 return (op1 >> op2) | (op1 << (32U - op2));
AnnaBridge 161:aa5281ff4a02 226 }
AnnaBridge 161:aa5281ff4a02 227
AnnaBridge 161:aa5281ff4a02 228
AnnaBridge 161:aa5281ff4a02 229 /**
AnnaBridge 161:aa5281ff4a02 230 \brief Breakpoint
AnnaBridge 161:aa5281ff4a02 231 \param [in] value is ignored by the processor.
AnnaBridge 161:aa5281ff4a02 232 If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge 161:aa5281ff4a02 233 */
AnnaBridge 161:aa5281ff4a02 234 #define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge 161:aa5281ff4a02 235
AnnaBridge 161:aa5281ff4a02 236 /**
AnnaBridge 161:aa5281ff4a02 237 \brief Reverse bit order of value
AnnaBridge 161:aa5281ff4a02 238 \details Reverses the bit order of the given value.
AnnaBridge 161:aa5281ff4a02 239 \param [in] value Value to reverse
AnnaBridge 161:aa5281ff4a02 240 \return Reversed value
AnnaBridge 161:aa5281ff4a02 241 */
AnnaBridge 161:aa5281ff4a02 242 __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
AnnaBridge 161:aa5281ff4a02 243 {
AnnaBridge 161:aa5281ff4a02 244 uint32_t result;
AnnaBridge 161:aa5281ff4a02 245
AnnaBridge 161:aa5281ff4a02 246 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 161:aa5281ff4a02 247 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 161:aa5281ff4a02 248 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 161:aa5281ff4a02 249 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
AnnaBridge 161:aa5281ff4a02 250 #else
AnnaBridge 161:aa5281ff4a02 251 int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
AnnaBridge 161:aa5281ff4a02 252
AnnaBridge 161:aa5281ff4a02 253 result = value; /* r will be reversed bits of v; first get LSB of v */
AnnaBridge 161:aa5281ff4a02 254 for (value >>= 1U; value; value >>= 1U)
AnnaBridge 161:aa5281ff4a02 255 {
AnnaBridge 161:aa5281ff4a02 256 result <<= 1U;
AnnaBridge 161:aa5281ff4a02 257 result |= value & 1U;
AnnaBridge 161:aa5281ff4a02 258 s--;
AnnaBridge 161:aa5281ff4a02 259 }
AnnaBridge 161:aa5281ff4a02 260 result <<= s; /* shift when v's highest bits are zero */
AnnaBridge 161:aa5281ff4a02 261 #endif
AnnaBridge 161:aa5281ff4a02 262 return result;
AnnaBridge 161:aa5281ff4a02 263 }
AnnaBridge 161:aa5281ff4a02 264
AnnaBridge 161:aa5281ff4a02 265 /**
AnnaBridge 161:aa5281ff4a02 266 \brief Count leading zeros
AnnaBridge 161:aa5281ff4a02 267 \param [in] value Value to count the leading zeros
AnnaBridge 161:aa5281ff4a02 268 \return number of leading zeros in value
AnnaBridge 161:aa5281ff4a02 269 */
AnnaBridge 161:aa5281ff4a02 270 #define __CLZ (uint8_t)__builtin_clz
AnnaBridge 161:aa5281ff4a02 271
AnnaBridge 161:aa5281ff4a02 272 /**
AnnaBridge 161:aa5281ff4a02 273 \brief LDR Exclusive (8 bit)
AnnaBridge 161:aa5281ff4a02 274 \details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge 161:aa5281ff4a02 275 \param [in] ptr Pointer to data
AnnaBridge 161:aa5281ff4a02 276 \return value of type uint8_t at (*ptr)
AnnaBridge 161:aa5281ff4a02 277 */
AnnaBridge 161:aa5281ff4a02 278 __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
AnnaBridge 161:aa5281ff4a02 279 {
AnnaBridge 161:aa5281ff4a02 280 uint32_t result;
AnnaBridge 161:aa5281ff4a02 281
AnnaBridge 161:aa5281ff4a02 282 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 161:aa5281ff4a02 283 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge 161:aa5281ff4a02 284 #else
AnnaBridge 161:aa5281ff4a02 285 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge 161:aa5281ff4a02 286 accepted by assembler. So has to use following less efficient pattern.
AnnaBridge 161:aa5281ff4a02 287 */
AnnaBridge 161:aa5281ff4a02 288 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge 161:aa5281ff4a02 289 #endif
AnnaBridge 161:aa5281ff4a02 290 return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge 161:aa5281ff4a02 291 }
AnnaBridge 161:aa5281ff4a02 292
AnnaBridge 161:aa5281ff4a02 293
AnnaBridge 161:aa5281ff4a02 294 /**
AnnaBridge 161:aa5281ff4a02 295 \brief LDR Exclusive (16 bit)
AnnaBridge 161:aa5281ff4a02 296 \details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge 161:aa5281ff4a02 297 \param [in] ptr Pointer to data
AnnaBridge 161:aa5281ff4a02 298 \return value of type uint16_t at (*ptr)
AnnaBridge 161:aa5281ff4a02 299 */
AnnaBridge 161:aa5281ff4a02 300 __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
AnnaBridge 161:aa5281ff4a02 301 {
AnnaBridge 161:aa5281ff4a02 302 uint32_t result;
AnnaBridge 161:aa5281ff4a02 303
AnnaBridge 161:aa5281ff4a02 304 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 161:aa5281ff4a02 305 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge 161:aa5281ff4a02 306 #else
AnnaBridge 161:aa5281ff4a02 307 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge 161:aa5281ff4a02 308 accepted by assembler. So has to use following less efficient pattern.
AnnaBridge 161:aa5281ff4a02 309 */
AnnaBridge 161:aa5281ff4a02 310 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge 161:aa5281ff4a02 311 #endif
AnnaBridge 161:aa5281ff4a02 312 return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge 161:aa5281ff4a02 313 }
AnnaBridge 161:aa5281ff4a02 314
AnnaBridge 161:aa5281ff4a02 315
AnnaBridge 161:aa5281ff4a02 316 /**
AnnaBridge 161:aa5281ff4a02 317 \brief LDR Exclusive (32 bit)
AnnaBridge 161:aa5281ff4a02 318 \details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge 161:aa5281ff4a02 319 \param [in] ptr Pointer to data
AnnaBridge 161:aa5281ff4a02 320 \return value of type uint32_t at (*ptr)
AnnaBridge 161:aa5281ff4a02 321 */
AnnaBridge 161:aa5281ff4a02 322 __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
AnnaBridge 161:aa5281ff4a02 323 {
AnnaBridge 161:aa5281ff4a02 324 uint32_t result;
AnnaBridge 161:aa5281ff4a02 325
AnnaBridge 161:aa5281ff4a02 326 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge 161:aa5281ff4a02 327 return(result);
AnnaBridge 161:aa5281ff4a02 328 }
AnnaBridge 161:aa5281ff4a02 329
AnnaBridge 161:aa5281ff4a02 330
AnnaBridge 161:aa5281ff4a02 331 /**
AnnaBridge 161:aa5281ff4a02 332 \brief STR Exclusive (8 bit)
AnnaBridge 161:aa5281ff4a02 333 \details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge 161:aa5281ff4a02 334 \param [in] value Value to store
AnnaBridge 161:aa5281ff4a02 335 \param [in] ptr Pointer to location
AnnaBridge 161:aa5281ff4a02 336 \return 0 Function succeeded
AnnaBridge 161:aa5281ff4a02 337 \return 1 Function failed
AnnaBridge 161:aa5281ff4a02 338 */
AnnaBridge 161:aa5281ff4a02 339 __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
AnnaBridge 161:aa5281ff4a02 340 {
AnnaBridge 161:aa5281ff4a02 341 uint32_t result;
AnnaBridge 161:aa5281ff4a02 342
AnnaBridge 161:aa5281ff4a02 343 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge 161:aa5281ff4a02 344 return(result);
AnnaBridge 161:aa5281ff4a02 345 }
AnnaBridge 161:aa5281ff4a02 346
AnnaBridge 161:aa5281ff4a02 347
AnnaBridge 161:aa5281ff4a02 348 /**
AnnaBridge 161:aa5281ff4a02 349 \brief STR Exclusive (16 bit)
AnnaBridge 161:aa5281ff4a02 350 \details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge 161:aa5281ff4a02 351 \param [in] value Value to store
AnnaBridge 161:aa5281ff4a02 352 \param [in] ptr Pointer to location
AnnaBridge 161:aa5281ff4a02 353 \return 0 Function succeeded
AnnaBridge 161:aa5281ff4a02 354 \return 1 Function failed
AnnaBridge 161:aa5281ff4a02 355 */
AnnaBridge 161:aa5281ff4a02 356 __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
AnnaBridge 161:aa5281ff4a02 357 {
AnnaBridge 161:aa5281ff4a02 358 uint32_t result;
AnnaBridge 161:aa5281ff4a02 359
AnnaBridge 161:aa5281ff4a02 360 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge 161:aa5281ff4a02 361 return(result);
AnnaBridge 161:aa5281ff4a02 362 }
AnnaBridge 161:aa5281ff4a02 363
AnnaBridge 161:aa5281ff4a02 364
AnnaBridge 161:aa5281ff4a02 365 /**
AnnaBridge 161:aa5281ff4a02 366 \brief STR Exclusive (32 bit)
AnnaBridge 161:aa5281ff4a02 367 \details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge 161:aa5281ff4a02 368 \param [in] value Value to store
AnnaBridge 161:aa5281ff4a02 369 \param [in] ptr Pointer to location
AnnaBridge 161:aa5281ff4a02 370 \return 0 Function succeeded
AnnaBridge 161:aa5281ff4a02 371 \return 1 Function failed
AnnaBridge 161:aa5281ff4a02 372 */
AnnaBridge 161:aa5281ff4a02 373 __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
AnnaBridge 161:aa5281ff4a02 374 {
AnnaBridge 161:aa5281ff4a02 375 uint32_t result;
AnnaBridge 161:aa5281ff4a02 376
AnnaBridge 161:aa5281ff4a02 377 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
AnnaBridge 161:aa5281ff4a02 378 return(result);
AnnaBridge 161:aa5281ff4a02 379 }
AnnaBridge 161:aa5281ff4a02 380
AnnaBridge 161:aa5281ff4a02 381
AnnaBridge 161:aa5281ff4a02 382 /**
AnnaBridge 161:aa5281ff4a02 383 \brief Remove the exclusive lock
AnnaBridge 161:aa5281ff4a02 384 \details Removes the exclusive lock which is created by LDREX.
AnnaBridge 161:aa5281ff4a02 385 */
AnnaBridge 161:aa5281ff4a02 386 __STATIC_FORCEINLINE void __CLREX(void)
AnnaBridge 161:aa5281ff4a02 387 {
AnnaBridge 161:aa5281ff4a02 388 __ASM volatile ("clrex" ::: "memory");
AnnaBridge 161:aa5281ff4a02 389 }
AnnaBridge 161:aa5281ff4a02 390
AnnaBridge 161:aa5281ff4a02 391 /**
AnnaBridge 161:aa5281ff4a02 392 \brief Signed Saturate
AnnaBridge 161:aa5281ff4a02 393 \details Saturates a signed value.
AnnaBridge 161:aa5281ff4a02 394 \param [in] value Value to be saturated
AnnaBridge 161:aa5281ff4a02 395 \param [in] sat Bit position to saturate to (1..32)
AnnaBridge 161:aa5281ff4a02 396 \return Saturated value
AnnaBridge 161:aa5281ff4a02 397 */
AnnaBridge 161:aa5281ff4a02 398 #define __SSAT(ARG1,ARG2) \
AnnaBridge 161:aa5281ff4a02 399 __extension__ \
AnnaBridge 161:aa5281ff4a02 400 ({ \
AnnaBridge 161:aa5281ff4a02 401 int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 161:aa5281ff4a02 402 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 161:aa5281ff4a02 403 __RES; \
AnnaBridge 161:aa5281ff4a02 404 })
AnnaBridge 161:aa5281ff4a02 405
AnnaBridge 161:aa5281ff4a02 406
AnnaBridge 161:aa5281ff4a02 407 /**
AnnaBridge 161:aa5281ff4a02 408 \brief Unsigned Saturate
AnnaBridge 161:aa5281ff4a02 409 \details Saturates an unsigned value.
AnnaBridge 161:aa5281ff4a02 410 \param [in] value Value to be saturated
AnnaBridge 161:aa5281ff4a02 411 \param [in] sat Bit position to saturate to (0..31)
AnnaBridge 161:aa5281ff4a02 412 \return Saturated value
AnnaBridge 161:aa5281ff4a02 413 */
AnnaBridge 161:aa5281ff4a02 414 #define __USAT(ARG1,ARG2) \
AnnaBridge 161:aa5281ff4a02 415 __extension__ \
AnnaBridge 161:aa5281ff4a02 416 ({ \
AnnaBridge 161:aa5281ff4a02 417 uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 161:aa5281ff4a02 418 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 161:aa5281ff4a02 419 __RES; \
AnnaBridge 161:aa5281ff4a02 420 })
AnnaBridge 161:aa5281ff4a02 421
AnnaBridge 161:aa5281ff4a02 422 /* ########################### Core Function Access ########################### */
AnnaBridge 161:aa5281ff4a02 423
AnnaBridge 161:aa5281ff4a02 424 /**
AnnaBridge 161:aa5281ff4a02 425 \brief Enable IRQ Interrupts
AnnaBridge 161:aa5281ff4a02 426 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge 161:aa5281ff4a02 427 Can only be executed in Privileged modes.
AnnaBridge 161:aa5281ff4a02 428 */
AnnaBridge 161:aa5281ff4a02 429 __STATIC_FORCEINLINE void __enable_irq(void)
AnnaBridge 161:aa5281ff4a02 430 {
AnnaBridge 161:aa5281ff4a02 431 __ASM volatile ("cpsie i" : : : "memory");
AnnaBridge 161:aa5281ff4a02 432 }
AnnaBridge 161:aa5281ff4a02 433
AnnaBridge 161:aa5281ff4a02 434 /**
AnnaBridge 161:aa5281ff4a02 435 \brief Disable IRQ Interrupts
AnnaBridge 161:aa5281ff4a02 436 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge 161:aa5281ff4a02 437 Can only be executed in Privileged modes.
AnnaBridge 161:aa5281ff4a02 438 */
AnnaBridge 161:aa5281ff4a02 439 __STATIC_FORCEINLINE void __disable_irq(void)
AnnaBridge 161:aa5281ff4a02 440 {
AnnaBridge 161:aa5281ff4a02 441 __ASM volatile ("cpsid i" : : : "memory");
AnnaBridge 161:aa5281ff4a02 442 }
AnnaBridge 161:aa5281ff4a02 443
AnnaBridge 161:aa5281ff4a02 444 /**
AnnaBridge 161:aa5281ff4a02 445 \brief Get FPSCR
AnnaBridge 161:aa5281ff4a02 446 \details Returns the current value of the Floating Point Status/Control register.
AnnaBridge 161:aa5281ff4a02 447 \return Floating Point Status/Control register value
AnnaBridge 161:aa5281ff4a02 448 */
AnnaBridge 161:aa5281ff4a02 449 __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
AnnaBridge 161:aa5281ff4a02 450 {
AnnaBridge 161:aa5281ff4a02 451 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 161:aa5281ff4a02 452 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 161:aa5281ff4a02 453 #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
AnnaBridge 161:aa5281ff4a02 454 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
AnnaBridge 161:aa5281ff4a02 455 return __builtin_arm_get_fpscr();
AnnaBridge 161:aa5281ff4a02 456 #else
AnnaBridge 161:aa5281ff4a02 457 uint32_t result;
AnnaBridge 161:aa5281ff4a02 458
AnnaBridge 161:aa5281ff4a02 459 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
AnnaBridge 161:aa5281ff4a02 460 return(result);
AnnaBridge 161:aa5281ff4a02 461 #endif
AnnaBridge 161:aa5281ff4a02 462 #else
AnnaBridge 161:aa5281ff4a02 463 return(0U);
AnnaBridge 161:aa5281ff4a02 464 #endif
AnnaBridge 161:aa5281ff4a02 465 }
AnnaBridge 161:aa5281ff4a02 466
AnnaBridge 161:aa5281ff4a02 467 /**
AnnaBridge 161:aa5281ff4a02 468 \brief Set FPSCR
AnnaBridge 161:aa5281ff4a02 469 \details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge 161:aa5281ff4a02 470 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 161:aa5281ff4a02 471 */
AnnaBridge 161:aa5281ff4a02 472 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 161:aa5281ff4a02 473 {
AnnaBridge 161:aa5281ff4a02 474 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 161:aa5281ff4a02 475 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 161:aa5281ff4a02 476 #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
AnnaBridge 161:aa5281ff4a02 477 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
AnnaBridge 161:aa5281ff4a02 478 __builtin_arm_set_fpscr(fpscr);
AnnaBridge 161:aa5281ff4a02 479 #else
AnnaBridge 161:aa5281ff4a02 480 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
AnnaBridge 161:aa5281ff4a02 481 #endif
AnnaBridge 161:aa5281ff4a02 482 #else
AnnaBridge 161:aa5281ff4a02 483 (void)fpscr;
AnnaBridge 161:aa5281ff4a02 484 #endif
AnnaBridge 161:aa5281ff4a02 485 }
AnnaBridge 161:aa5281ff4a02 486
AnnaBridge 161:aa5281ff4a02 487 /** \brief Get CPSR Register
AnnaBridge 161:aa5281ff4a02 488 \return CPSR Register value
AnnaBridge 161:aa5281ff4a02 489 */
AnnaBridge 161:aa5281ff4a02 490 __STATIC_FORCEINLINE uint32_t __get_CPSR(void)
AnnaBridge 161:aa5281ff4a02 491 {
AnnaBridge 161:aa5281ff4a02 492 uint32_t result;
AnnaBridge 161:aa5281ff4a02 493 __ASM volatile("MRS %0, cpsr" : "=r" (result) );
AnnaBridge 161:aa5281ff4a02 494 return(result);
AnnaBridge 161:aa5281ff4a02 495 }
AnnaBridge 161:aa5281ff4a02 496
AnnaBridge 161:aa5281ff4a02 497 /** \brief Set CPSR Register
AnnaBridge 161:aa5281ff4a02 498 \param [in] cpsr CPSR value to set
AnnaBridge 161:aa5281ff4a02 499 */
AnnaBridge 161:aa5281ff4a02 500 __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
AnnaBridge 161:aa5281ff4a02 501 {
AnnaBridge 161:aa5281ff4a02 502 __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
AnnaBridge 161:aa5281ff4a02 503 }
AnnaBridge 161:aa5281ff4a02 504
AnnaBridge 161:aa5281ff4a02 505 /** \brief Get Mode
AnnaBridge 161:aa5281ff4a02 506 \return Processor Mode
AnnaBridge 161:aa5281ff4a02 507 */
AnnaBridge 161:aa5281ff4a02 508 __STATIC_FORCEINLINE uint32_t __get_mode(void)
AnnaBridge 161:aa5281ff4a02 509 {
AnnaBridge 161:aa5281ff4a02 510 return (__get_CPSR() & 0x1FU);
AnnaBridge 161:aa5281ff4a02 511 }
AnnaBridge 161:aa5281ff4a02 512
AnnaBridge 161:aa5281ff4a02 513 /** \brief Set Mode
AnnaBridge 161:aa5281ff4a02 514 \param [in] mode Mode value to set
AnnaBridge 161:aa5281ff4a02 515 */
AnnaBridge 161:aa5281ff4a02 516 __STATIC_FORCEINLINE void __set_mode(uint32_t mode)
AnnaBridge 161:aa5281ff4a02 517 {
AnnaBridge 161:aa5281ff4a02 518 __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
AnnaBridge 161:aa5281ff4a02 519 }
AnnaBridge 161:aa5281ff4a02 520
AnnaBridge 161:aa5281ff4a02 521 /** \brief Get Stack Pointer
AnnaBridge 161:aa5281ff4a02 522 \return Stack Pointer value
AnnaBridge 161:aa5281ff4a02 523 */
AnnaBridge 161:aa5281ff4a02 524 __STATIC_FORCEINLINE uint32_t __get_SP(void)
AnnaBridge 161:aa5281ff4a02 525 {
AnnaBridge 161:aa5281ff4a02 526 uint32_t result;
AnnaBridge 161:aa5281ff4a02 527 __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
AnnaBridge 161:aa5281ff4a02 528 return result;
AnnaBridge 161:aa5281ff4a02 529 }
AnnaBridge 161:aa5281ff4a02 530
AnnaBridge 161:aa5281ff4a02 531 /** \brief Set Stack Pointer
AnnaBridge 161:aa5281ff4a02 532 \param [in] stack Stack Pointer value to set
AnnaBridge 161:aa5281ff4a02 533 */
AnnaBridge 161:aa5281ff4a02 534 __STATIC_FORCEINLINE void __set_SP(uint32_t stack)
AnnaBridge 161:aa5281ff4a02 535 {
AnnaBridge 161:aa5281ff4a02 536 __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
AnnaBridge 161:aa5281ff4a02 537 }
AnnaBridge 161:aa5281ff4a02 538
AnnaBridge 161:aa5281ff4a02 539 /** \brief Get USR/SYS Stack Pointer
AnnaBridge 161:aa5281ff4a02 540 \return USR/SYS Stack Pointer value
AnnaBridge 161:aa5281ff4a02 541 */
AnnaBridge 161:aa5281ff4a02 542 __STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
AnnaBridge 161:aa5281ff4a02 543 {
AnnaBridge 161:aa5281ff4a02 544 uint32_t cpsr = __get_CPSR();
AnnaBridge 161:aa5281ff4a02 545 uint32_t result;
AnnaBridge 161:aa5281ff4a02 546 __ASM volatile(
AnnaBridge 161:aa5281ff4a02 547 "CPS #0x1F \n"
AnnaBridge 161:aa5281ff4a02 548 "MOV %0, sp " : "=r"(result) : : "memory"
AnnaBridge 161:aa5281ff4a02 549 );
AnnaBridge 161:aa5281ff4a02 550 __set_CPSR(cpsr);
AnnaBridge 161:aa5281ff4a02 551 __ISB();
AnnaBridge 161:aa5281ff4a02 552 return result;
AnnaBridge 161:aa5281ff4a02 553 }
AnnaBridge 161:aa5281ff4a02 554
AnnaBridge 161:aa5281ff4a02 555 /** \brief Set USR/SYS Stack Pointer
AnnaBridge 161:aa5281ff4a02 556 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 161:aa5281ff4a02 557 */
AnnaBridge 161:aa5281ff4a02 558 __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
AnnaBridge 161:aa5281ff4a02 559 {
AnnaBridge 161:aa5281ff4a02 560 uint32_t cpsr = __get_CPSR();
AnnaBridge 161:aa5281ff4a02 561 __ASM volatile(
AnnaBridge 161:aa5281ff4a02 562 "CPS #0x1F \n"
AnnaBridge 161:aa5281ff4a02 563 "MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
AnnaBridge 161:aa5281ff4a02 564 );
AnnaBridge 161:aa5281ff4a02 565 __set_CPSR(cpsr);
AnnaBridge 161:aa5281ff4a02 566 __ISB();
AnnaBridge 161:aa5281ff4a02 567 }
AnnaBridge 161:aa5281ff4a02 568
AnnaBridge 161:aa5281ff4a02 569 /** \brief Get FPEXC
AnnaBridge 161:aa5281ff4a02 570 \return Floating Point Exception Control register value
AnnaBridge 161:aa5281ff4a02 571 */
AnnaBridge 161:aa5281ff4a02 572 __STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
AnnaBridge 161:aa5281ff4a02 573 {
AnnaBridge 161:aa5281ff4a02 574 #if (__FPU_PRESENT == 1)
AnnaBridge 161:aa5281ff4a02 575 uint32_t result;
AnnaBridge 161:aa5281ff4a02 576 __ASM volatile("VMRS %0, fpexc" : "=r" (result) );
AnnaBridge 161:aa5281ff4a02 577 return(result);
AnnaBridge 161:aa5281ff4a02 578 #else
AnnaBridge 161:aa5281ff4a02 579 return(0);
AnnaBridge 161:aa5281ff4a02 580 #endif
AnnaBridge 161:aa5281ff4a02 581 }
AnnaBridge 161:aa5281ff4a02 582
AnnaBridge 161:aa5281ff4a02 583 /** \brief Set FPEXC
AnnaBridge 161:aa5281ff4a02 584 \param [in] fpexc Floating Point Exception Control value to set
AnnaBridge 161:aa5281ff4a02 585 */
AnnaBridge 161:aa5281ff4a02 586 __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 161:aa5281ff4a02 587 {
AnnaBridge 161:aa5281ff4a02 588 #if (__FPU_PRESENT == 1)
AnnaBridge 161:aa5281ff4a02 589 __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
AnnaBridge 161:aa5281ff4a02 590 #endif
AnnaBridge 161:aa5281ff4a02 591 }
AnnaBridge 161:aa5281ff4a02 592
AnnaBridge 161:aa5281ff4a02 593 /*
AnnaBridge 161:aa5281ff4a02 594 * Include common core functions to access Coprocessor 15 registers
AnnaBridge 161:aa5281ff4a02 595 */
AnnaBridge 161:aa5281ff4a02 596
AnnaBridge 161:aa5281ff4a02 597 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
AnnaBridge 161:aa5281ff4a02 598 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
AnnaBridge 161:aa5281ff4a02 599 #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
AnnaBridge 161:aa5281ff4a02 600 #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
AnnaBridge 161:aa5281ff4a02 601
AnnaBridge 161:aa5281ff4a02 602 #include "cmsis_cp15.h"
AnnaBridge 161:aa5281ff4a02 603
AnnaBridge 161:aa5281ff4a02 604 /** \brief Enable Floating Point Unit
AnnaBridge 161:aa5281ff4a02 605
AnnaBridge 161:aa5281ff4a02 606 Critical section, called from undef handler, so systick is disabled
AnnaBridge 161:aa5281ff4a02 607 */
AnnaBridge 161:aa5281ff4a02 608 __STATIC_INLINE void __FPU_Enable(void)
AnnaBridge 161:aa5281ff4a02 609 {
AnnaBridge 161:aa5281ff4a02 610 __ASM volatile(
AnnaBridge 161:aa5281ff4a02 611 //Permit access to VFP/NEON, registers by modifying CPACR
AnnaBridge 161:aa5281ff4a02 612 " MRC p15,0,R1,c1,c0,2 \n"
AnnaBridge 161:aa5281ff4a02 613 " ORR R1,R1,#0x00F00000 \n"
AnnaBridge 161:aa5281ff4a02 614 " MCR p15,0,R1,c1,c0,2 \n"
AnnaBridge 161:aa5281ff4a02 615
AnnaBridge 161:aa5281ff4a02 616 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
AnnaBridge 161:aa5281ff4a02 617 " ISB \n"
AnnaBridge 161:aa5281ff4a02 618
AnnaBridge 161:aa5281ff4a02 619 //Enable VFP/NEON
AnnaBridge 161:aa5281ff4a02 620 " VMRS R1,FPEXC \n"
AnnaBridge 161:aa5281ff4a02 621 " ORR R1,R1,#0x40000000 \n"
AnnaBridge 161:aa5281ff4a02 622 " VMSR FPEXC,R1 \n"
AnnaBridge 161:aa5281ff4a02 623
AnnaBridge 161:aa5281ff4a02 624 //Initialise VFP/NEON registers to 0
AnnaBridge 161:aa5281ff4a02 625 " MOV R2,#0 \n"
AnnaBridge 161:aa5281ff4a02 626
AnnaBridge 161:aa5281ff4a02 627 //Initialise D16 registers to 0
AnnaBridge 161:aa5281ff4a02 628 " VMOV D0, R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 629 " VMOV D1, R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 630 " VMOV D2, R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 631 " VMOV D3, R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 632 " VMOV D4, R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 633 " VMOV D5, R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 634 " VMOV D6, R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 635 " VMOV D7, R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 636 " VMOV D8, R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 637 " VMOV D9, R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 638 " VMOV D10,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 639 " VMOV D11,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 640 " VMOV D12,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 641 " VMOV D13,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 642 " VMOV D14,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 643 " VMOV D15,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 644
Anna Bridge 169:a7c7b631e539 645 #if (defined(__ARM_NEON) && (__ARM_NEON == 1))
AnnaBridge 161:aa5281ff4a02 646 //Initialise D32 registers to 0
AnnaBridge 161:aa5281ff4a02 647 " VMOV D16,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 648 " VMOV D17,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 649 " VMOV D18,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 650 " VMOV D19,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 651 " VMOV D20,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 652 " VMOV D21,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 653 " VMOV D22,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 654 " VMOV D23,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 655 " VMOV D24,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 656 " VMOV D25,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 657 " VMOV D26,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 658 " VMOV D27,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 659 " VMOV D28,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 660 " VMOV D29,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 661 " VMOV D30,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 662 " VMOV D31,R2,R2 \n"
AnnaBridge 161:aa5281ff4a02 663 #endif
AnnaBridge 161:aa5281ff4a02 664
AnnaBridge 161:aa5281ff4a02 665 //Initialise FPSCR to a known state
AnnaBridge 161:aa5281ff4a02 666 " VMRS R2,FPSCR \n"
AnnaBridge 161:aa5281ff4a02 667 " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
AnnaBridge 161:aa5281ff4a02 668 " AND R2,R2,R3 \n"
AnnaBridge 161:aa5281ff4a02 669 " VMSR FPSCR,R2 "
AnnaBridge 161:aa5281ff4a02 670 );
AnnaBridge 161:aa5281ff4a02 671 }
AnnaBridge 161:aa5281ff4a02 672
AnnaBridge 161:aa5281ff4a02 673 #pragma GCC diagnostic pop
AnnaBridge 161:aa5281ff4a02 674
AnnaBridge 161:aa5281ff4a02 675 #endif /* __CMSIS_GCC_H */