mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_DISCO_L496AG/mpu_armv8.h@170:e95d10626187, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:39:34 2018 +0100
Revision:
170:e95d10626187
Parent:
169:a7c7b631e539 
mbed library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 165:d1b4690b3f8b 1 /******************************************************************************
AnnaBridge 165:d1b4690b3f8b 2 * @file mpu_armv8.h
Anna Bridge 169:a7c7b631e539 3 * @brief CMSIS MPU API for Armv8-M MPU
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.4
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
AnnaBridge 165:d1b4690b3f8b 6 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
AnnaBridge 165:d1b4690b3f8b 9 *
AnnaBridge 165:d1b4690b3f8b 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 165:d1b4690b3f8b 11 *
AnnaBridge 165:d1b4690b3f8b 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 165:d1b4690b3f8b 13 * not use this file except in compliance with the License.
AnnaBridge 165:d1b4690b3f8b 14 * You may obtain a copy of the License at
AnnaBridge 165:d1b4690b3f8b 15 *
AnnaBridge 165:d1b4690b3f8b 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 165:d1b4690b3f8b 17 *
AnnaBridge 165:d1b4690b3f8b 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 165:d1b4690b3f8b 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 165:d1b4690b3f8b 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 165:d1b4690b3f8b 21 * See the License for the specific language governing permissions and
AnnaBridge 165:d1b4690b3f8b 22 * limitations under the License.
AnnaBridge 165:d1b4690b3f8b 23 */
Anna Bridge 169:a7c7b631e539 24
Anna Bridge 169:a7c7b631e539 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
Anna Bridge 169:a7c7b631e539 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 169:a7c7b631e539 29 #endif
Anna Bridge 169:a7c7b631e539 30
AnnaBridge 165:d1b4690b3f8b 31 #ifndef ARM_MPU_ARMV8_H
AnnaBridge 165:d1b4690b3f8b 32 #define ARM_MPU_ARMV8_H
AnnaBridge 165:d1b4690b3f8b 33
AnnaBridge 165:d1b4690b3f8b 34 /** \brief Attribute for device memory (outer only) */
AnnaBridge 165:d1b4690b3f8b 35 #define ARM_MPU_ATTR_DEVICE ( 0U )
AnnaBridge 165:d1b4690b3f8b 36
AnnaBridge 165:d1b4690b3f8b 37 /** \brief Attribute for non-cacheable, normal memory */
AnnaBridge 165:d1b4690b3f8b 38 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
AnnaBridge 165:d1b4690b3f8b 39
AnnaBridge 165:d1b4690b3f8b 40 /** \brief Attribute for normal memory (outer and inner)
AnnaBridge 165:d1b4690b3f8b 41 * \param NT Non-Transient: Set to 1 for non-transient data.
AnnaBridge 165:d1b4690b3f8b 42 * \param WB Write-Back: Set to 1 to use write-back update policy.
AnnaBridge 165:d1b4690b3f8b 43 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
AnnaBridge 165:d1b4690b3f8b 44 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
AnnaBridge 165:d1b4690b3f8b 45 */
AnnaBridge 165:d1b4690b3f8b 46 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
AnnaBridge 165:d1b4690b3f8b 47 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
AnnaBridge 165:d1b4690b3f8b 48
AnnaBridge 165:d1b4690b3f8b 49 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
AnnaBridge 165:d1b4690b3f8b 50 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
AnnaBridge 165:d1b4690b3f8b 51
AnnaBridge 165:d1b4690b3f8b 52 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
AnnaBridge 165:d1b4690b3f8b 53 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
AnnaBridge 165:d1b4690b3f8b 54
AnnaBridge 165:d1b4690b3f8b 55 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
AnnaBridge 165:d1b4690b3f8b 56 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
AnnaBridge 165:d1b4690b3f8b 57
AnnaBridge 165:d1b4690b3f8b 58 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
AnnaBridge 165:d1b4690b3f8b 59 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
AnnaBridge 165:d1b4690b3f8b 60
AnnaBridge 165:d1b4690b3f8b 61 /** \brief Memory Attribute
AnnaBridge 165:d1b4690b3f8b 62 * \param O Outer memory attributes
AnnaBridge 165:d1b4690b3f8b 63 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
AnnaBridge 165:d1b4690b3f8b 64 */
AnnaBridge 165:d1b4690b3f8b 65 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
AnnaBridge 165:d1b4690b3f8b 66
AnnaBridge 165:d1b4690b3f8b 67 /** \brief Normal memory non-shareable */
AnnaBridge 165:d1b4690b3f8b 68 #define ARM_MPU_SH_NON (0U)
AnnaBridge 165:d1b4690b3f8b 69
AnnaBridge 165:d1b4690b3f8b 70 /** \brief Normal memory outer shareable */
AnnaBridge 165:d1b4690b3f8b 71 #define ARM_MPU_SH_OUTER (2U)
AnnaBridge 165:d1b4690b3f8b 72
AnnaBridge 165:d1b4690b3f8b 73 /** \brief Normal memory inner shareable */
AnnaBridge 165:d1b4690b3f8b 74 #define ARM_MPU_SH_INNER (3U)
AnnaBridge 165:d1b4690b3f8b 75
AnnaBridge 165:d1b4690b3f8b 76 /** \brief Memory access permissions
AnnaBridge 165:d1b4690b3f8b 77 * \param RO Read-Only: Set to 1 for read-only memory.
AnnaBridge 165:d1b4690b3f8b 78 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
AnnaBridge 165:d1b4690b3f8b 79 */
AnnaBridge 165:d1b4690b3f8b 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
AnnaBridge 165:d1b4690b3f8b 81
AnnaBridge 165:d1b4690b3f8b 82 /** \brief Region Base Address Register value
AnnaBridge 165:d1b4690b3f8b 83 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
AnnaBridge 165:d1b4690b3f8b 84 * \param SH Defines the Shareability domain for this memory region.
AnnaBridge 165:d1b4690b3f8b 85 * \param RO Read-Only: Set to 1 for a read-only memory region.
AnnaBridge 165:d1b4690b3f8b 86 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
AnnaBridge 165:d1b4690b3f8b 87 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
AnnaBridge 165:d1b4690b3f8b 88 */
AnnaBridge 165:d1b4690b3f8b 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
AnnaBridge 165:d1b4690b3f8b 90 ((BASE & MPU_RBAR_BASE_Pos) | \
AnnaBridge 165:d1b4690b3f8b 91 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
AnnaBridge 165:d1b4690b3f8b 92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
AnnaBridge 165:d1b4690b3f8b 93 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
AnnaBridge 165:d1b4690b3f8b 94
AnnaBridge 165:d1b4690b3f8b 95 /** \brief Region Limit Address Register value
AnnaBridge 165:d1b4690b3f8b 96 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
AnnaBridge 165:d1b4690b3f8b 97 * \param IDX The attribute index to be associated with this memory region.
AnnaBridge 165:d1b4690b3f8b 98 */
AnnaBridge 165:d1b4690b3f8b 99 #define ARM_MPU_RLAR(LIMIT, IDX) \
AnnaBridge 165:d1b4690b3f8b 100 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
AnnaBridge 165:d1b4690b3f8b 101 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
AnnaBridge 165:d1b4690b3f8b 102 (MPU_RLAR_EN_Msk))
AnnaBridge 165:d1b4690b3f8b 103
AnnaBridge 165:d1b4690b3f8b 104 /**
AnnaBridge 165:d1b4690b3f8b 105 * Struct for a single MPU Region
AnnaBridge 165:d1b4690b3f8b 106 */
Anna Bridge 169:a7c7b631e539 107 typedef struct {
AnnaBridge 165:d1b4690b3f8b 108 uint32_t RBAR; /*!< Region Base Address Register value */
AnnaBridge 165:d1b4690b3f8b 109 uint32_t RLAR; /*!< Region Limit Address Register value */
AnnaBridge 165:d1b4690b3f8b 110 } ARM_MPU_Region_t;
AnnaBridge 165:d1b4690b3f8b 111
AnnaBridge 165:d1b4690b3f8b 112 /** Enable the MPU.
AnnaBridge 165:d1b4690b3f8b 113 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 165:d1b4690b3f8b 114 */
AnnaBridge 165:d1b4690b3f8b 115 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
AnnaBridge 165:d1b4690b3f8b 116 {
AnnaBridge 165:d1b4690b3f8b 117 __DSB();
AnnaBridge 165:d1b4690b3f8b 118 __ISB();
AnnaBridge 165:d1b4690b3f8b 119 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 165:d1b4690b3f8b 120 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 165:d1b4690b3f8b 121 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 165:d1b4690b3f8b 122 #endif
AnnaBridge 165:d1b4690b3f8b 123 }
AnnaBridge 165:d1b4690b3f8b 124
AnnaBridge 165:d1b4690b3f8b 125 /** Disable the MPU.
AnnaBridge 165:d1b4690b3f8b 126 */
AnnaBridge 165:d1b4690b3f8b 127 __STATIC_INLINE void ARM_MPU_Disable(void)
AnnaBridge 165:d1b4690b3f8b 128 {
AnnaBridge 165:d1b4690b3f8b 129 __DSB();
AnnaBridge 165:d1b4690b3f8b 130 __ISB();
AnnaBridge 165:d1b4690b3f8b 131 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 165:d1b4690b3f8b 132 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 165:d1b4690b3f8b 133 #endif
AnnaBridge 165:d1b4690b3f8b 134 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 165:d1b4690b3f8b 135 }
AnnaBridge 165:d1b4690b3f8b 136
AnnaBridge 165:d1b4690b3f8b 137 #ifdef MPU_NS
AnnaBridge 165:d1b4690b3f8b 138 /** Enable the Non-secure MPU.
AnnaBridge 165:d1b4690b3f8b 139 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 165:d1b4690b3f8b 140 */
AnnaBridge 165:d1b4690b3f8b 141 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
AnnaBridge 165:d1b4690b3f8b 142 {
AnnaBridge 165:d1b4690b3f8b 143 __DSB();
AnnaBridge 165:d1b4690b3f8b 144 __ISB();
AnnaBridge 165:d1b4690b3f8b 145 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 165:d1b4690b3f8b 146 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 165:d1b4690b3f8b 147 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 165:d1b4690b3f8b 148 #endif
AnnaBridge 165:d1b4690b3f8b 149 }
AnnaBridge 165:d1b4690b3f8b 150
AnnaBridge 165:d1b4690b3f8b 151 /** Disable the Non-secure MPU.
AnnaBridge 165:d1b4690b3f8b 152 */
AnnaBridge 165:d1b4690b3f8b 153 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
AnnaBridge 165:d1b4690b3f8b 154 {
AnnaBridge 165:d1b4690b3f8b 155 __DSB();
AnnaBridge 165:d1b4690b3f8b 156 __ISB();
AnnaBridge 165:d1b4690b3f8b 157 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 165:d1b4690b3f8b 158 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 165:d1b4690b3f8b 159 #endif
AnnaBridge 165:d1b4690b3f8b 160 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 165:d1b4690b3f8b 161 }
AnnaBridge 165:d1b4690b3f8b 162 #endif
AnnaBridge 165:d1b4690b3f8b 163
AnnaBridge 165:d1b4690b3f8b 164 /** Set the memory attribute encoding to the given MPU.
AnnaBridge 165:d1b4690b3f8b 165 * \param mpu Pointer to the MPU to be configured.
AnnaBridge 165:d1b4690b3f8b 166 * \param idx The attribute index to be set [0-7]
AnnaBridge 165:d1b4690b3f8b 167 * \param attr The attribute value to be set.
AnnaBridge 165:d1b4690b3f8b 168 */
AnnaBridge 165:d1b4690b3f8b 169 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
AnnaBridge 165:d1b4690b3f8b 170 {
AnnaBridge 165:d1b4690b3f8b 171 const uint8_t reg = idx / 4U;
AnnaBridge 165:d1b4690b3f8b 172 const uint32_t pos = ((idx % 4U) * 8U);
AnnaBridge 165:d1b4690b3f8b 173 const uint32_t mask = 0xFFU << pos;
AnnaBridge 165:d1b4690b3f8b 174
Anna Bridge 169:a7c7b631e539 175 if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
AnnaBridge 165:d1b4690b3f8b 176 return; // invalid index
AnnaBridge 165:d1b4690b3f8b 177 }
AnnaBridge 165:d1b4690b3f8b 178
Anna Bridge 169:a7c7b631e539 179 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
AnnaBridge 165:d1b4690b3f8b 180 }
AnnaBridge 165:d1b4690b3f8b 181
AnnaBridge 165:d1b4690b3f8b 182 /** Set the memory attribute encoding.
AnnaBridge 165:d1b4690b3f8b 183 * \param idx The attribute index to be set [0-7]
AnnaBridge 165:d1b4690b3f8b 184 * \param attr The attribute value to be set.
AnnaBridge 165:d1b4690b3f8b 185 */
AnnaBridge 165:d1b4690b3f8b 186 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
AnnaBridge 165:d1b4690b3f8b 187 {
AnnaBridge 165:d1b4690b3f8b 188 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
AnnaBridge 165:d1b4690b3f8b 189 }
AnnaBridge 165:d1b4690b3f8b 190
AnnaBridge 165:d1b4690b3f8b 191 #ifdef MPU_NS
AnnaBridge 165:d1b4690b3f8b 192 /** Set the memory attribute encoding to the Non-secure MPU.
AnnaBridge 165:d1b4690b3f8b 193 * \param idx The attribute index to be set [0-7]
AnnaBridge 165:d1b4690b3f8b 194 * \param attr The attribute value to be set.
AnnaBridge 165:d1b4690b3f8b 195 */
AnnaBridge 165:d1b4690b3f8b 196 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
AnnaBridge 165:d1b4690b3f8b 197 {
AnnaBridge 165:d1b4690b3f8b 198 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
AnnaBridge 165:d1b4690b3f8b 199 }
AnnaBridge 165:d1b4690b3f8b 200 #endif
AnnaBridge 165:d1b4690b3f8b 201
AnnaBridge 165:d1b4690b3f8b 202 /** Clear and disable the given MPU region of the given MPU.
AnnaBridge 165:d1b4690b3f8b 203 * \param mpu Pointer to MPU to be used.
AnnaBridge 165:d1b4690b3f8b 204 * \param rnr Region number to be cleared.
AnnaBridge 165:d1b4690b3f8b 205 */
AnnaBridge 165:d1b4690b3f8b 206 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
AnnaBridge 165:d1b4690b3f8b 207 {
Anna Bridge 169:a7c7b631e539 208 mpu->RNR = rnr;
Anna Bridge 169:a7c7b631e539 209 mpu->RLAR = 0U;
AnnaBridge 165:d1b4690b3f8b 210 }
AnnaBridge 165:d1b4690b3f8b 211
AnnaBridge 165:d1b4690b3f8b 212 /** Clear and disable the given MPU region.
AnnaBridge 165:d1b4690b3f8b 213 * \param rnr Region number to be cleared.
AnnaBridge 165:d1b4690b3f8b 214 */
AnnaBridge 165:d1b4690b3f8b 215 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
AnnaBridge 165:d1b4690b3f8b 216 {
AnnaBridge 165:d1b4690b3f8b 217 ARM_MPU_ClrRegionEx(MPU, rnr);
AnnaBridge 165:d1b4690b3f8b 218 }
AnnaBridge 165:d1b4690b3f8b 219
AnnaBridge 165:d1b4690b3f8b 220 #ifdef MPU_NS
AnnaBridge 165:d1b4690b3f8b 221 /** Clear and disable the given Non-secure MPU region.
AnnaBridge 165:d1b4690b3f8b 222 * \param rnr Region number to be cleared.
AnnaBridge 165:d1b4690b3f8b 223 */
AnnaBridge 165:d1b4690b3f8b 224 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
AnnaBridge 165:d1b4690b3f8b 225 {
AnnaBridge 165:d1b4690b3f8b 226 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
AnnaBridge 165:d1b4690b3f8b 227 }
AnnaBridge 165:d1b4690b3f8b 228 #endif
AnnaBridge 165:d1b4690b3f8b 229
AnnaBridge 165:d1b4690b3f8b 230 /** Configure the given MPU region of the given MPU.
AnnaBridge 165:d1b4690b3f8b 231 * \param mpu Pointer to MPU to be used.
AnnaBridge 165:d1b4690b3f8b 232 * \param rnr Region number to be configured.
AnnaBridge 165:d1b4690b3f8b 233 * \param rbar Value for RBAR register.
AnnaBridge 165:d1b4690b3f8b 234 * \param rlar Value for RLAR register.
AnnaBridge 165:d1b4690b3f8b 235 */
AnnaBridge 165:d1b4690b3f8b 236 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 165:d1b4690b3f8b 237 {
Anna Bridge 169:a7c7b631e539 238 mpu->RNR = rnr;
Anna Bridge 169:a7c7b631e539 239 mpu->RBAR = rbar;
Anna Bridge 169:a7c7b631e539 240 mpu->RLAR = rlar;
AnnaBridge 165:d1b4690b3f8b 241 }
AnnaBridge 165:d1b4690b3f8b 242
AnnaBridge 165:d1b4690b3f8b 243 /** Configure the given MPU region.
AnnaBridge 165:d1b4690b3f8b 244 * \param rnr Region number to be configured.
AnnaBridge 165:d1b4690b3f8b 245 * \param rbar Value for RBAR register.
AnnaBridge 165:d1b4690b3f8b 246 * \param rlar Value for RLAR register.
AnnaBridge 165:d1b4690b3f8b 247 */
AnnaBridge 165:d1b4690b3f8b 248 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 165:d1b4690b3f8b 249 {
AnnaBridge 165:d1b4690b3f8b 250 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
AnnaBridge 165:d1b4690b3f8b 251 }
AnnaBridge 165:d1b4690b3f8b 252
AnnaBridge 165:d1b4690b3f8b 253 #ifdef MPU_NS
AnnaBridge 165:d1b4690b3f8b 254 /** Configure the given Non-secure MPU region.
AnnaBridge 165:d1b4690b3f8b 255 * \param rnr Region number to be configured.
AnnaBridge 165:d1b4690b3f8b 256 * \param rbar Value for RBAR register.
AnnaBridge 165:d1b4690b3f8b 257 * \param rlar Value for RLAR register.
AnnaBridge 165:d1b4690b3f8b 258 */
AnnaBridge 165:d1b4690b3f8b 259 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 165:d1b4690b3f8b 260 {
AnnaBridge 165:d1b4690b3f8b 261 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
AnnaBridge 165:d1b4690b3f8b 262 }
AnnaBridge 165:d1b4690b3f8b 263 #endif
AnnaBridge 165:d1b4690b3f8b 264
AnnaBridge 165:d1b4690b3f8b 265 /** Memcopy with strictly ordered memory access, e.g. for register targets.
AnnaBridge 165:d1b4690b3f8b 266 * \param dst Destination data is copied to.
AnnaBridge 165:d1b4690b3f8b 267 * \param src Source data is copied from.
AnnaBridge 165:d1b4690b3f8b 268 * \param len Amount of data words to be copied.
AnnaBridge 165:d1b4690b3f8b 269 */
AnnaBridge 165:d1b4690b3f8b 270 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
AnnaBridge 165:d1b4690b3f8b 271 {
AnnaBridge 165:d1b4690b3f8b 272 uint32_t i;
AnnaBridge 165:d1b4690b3f8b 273 for (i = 0U; i < len; ++i)
AnnaBridge 165:d1b4690b3f8b 274 {
AnnaBridge 165:d1b4690b3f8b 275 dst[i] = src[i];
AnnaBridge 165:d1b4690b3f8b 276 }
AnnaBridge 165:d1b4690b3f8b 277 }
AnnaBridge 165:d1b4690b3f8b 278
AnnaBridge 165:d1b4690b3f8b 279 /** Load the given number of MPU regions from a table to the given MPU.
AnnaBridge 165:d1b4690b3f8b 280 * \param mpu Pointer to the MPU registers to be used.
AnnaBridge 165:d1b4690b3f8b 281 * \param rnr First region number to be configured.
AnnaBridge 165:d1b4690b3f8b 282 * \param table Pointer to the MPU configuration table.
AnnaBridge 165:d1b4690b3f8b 283 * \param cnt Amount of regions to be configured.
AnnaBridge 165:d1b4690b3f8b 284 */
AnnaBridge 165:d1b4690b3f8b 285 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 165:d1b4690b3f8b 286 {
Anna Bridge 169:a7c7b631e539 287 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
AnnaBridge 165:d1b4690b3f8b 288 if (cnt == 1U) {
AnnaBridge 165:d1b4690b3f8b 289 mpu->RNR = rnr;
AnnaBridge 165:d1b4690b3f8b 290 orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
AnnaBridge 165:d1b4690b3f8b 291 } else {
AnnaBridge 165:d1b4690b3f8b 292 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
AnnaBridge 165:d1b4690b3f8b 293 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
AnnaBridge 165:d1b4690b3f8b 294
AnnaBridge 165:d1b4690b3f8b 295 mpu->RNR = rnrBase;
Anna Bridge 169:a7c7b631e539 296 while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
AnnaBridge 165:d1b4690b3f8b 297 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
AnnaBridge 165:d1b4690b3f8b 298 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
Anna Bridge 169:a7c7b631e539 299 table += c;
Anna Bridge 169:a7c7b631e539 300 cnt -= c;
Anna Bridge 169:a7c7b631e539 301 rnrOffset = 0U;
Anna Bridge 169:a7c7b631e539 302 rnrBase += MPU_TYPE_RALIASES;
Anna Bridge 169:a7c7b631e539 303 mpu->RNR = rnrBase;
AnnaBridge 165:d1b4690b3f8b 304 }
Anna Bridge 169:a7c7b631e539 305
Anna Bridge 169:a7c7b631e539 306 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
AnnaBridge 165:d1b4690b3f8b 307 }
AnnaBridge 165:d1b4690b3f8b 308 }
AnnaBridge 165:d1b4690b3f8b 309
AnnaBridge 165:d1b4690b3f8b 310 /** Load the given number of MPU regions from a table.
AnnaBridge 165:d1b4690b3f8b 311 * \param rnr First region number to be configured.
AnnaBridge 165:d1b4690b3f8b 312 * \param table Pointer to the MPU configuration table.
AnnaBridge 165:d1b4690b3f8b 313 * \param cnt Amount of regions to be configured.
AnnaBridge 165:d1b4690b3f8b 314 */
AnnaBridge 165:d1b4690b3f8b 315 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 165:d1b4690b3f8b 316 {
AnnaBridge 165:d1b4690b3f8b 317 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
AnnaBridge 165:d1b4690b3f8b 318 }
AnnaBridge 165:d1b4690b3f8b 319
AnnaBridge 165:d1b4690b3f8b 320 #ifdef MPU_NS
AnnaBridge 165:d1b4690b3f8b 321 /** Load the given number of MPU regions from a table to the Non-secure MPU.
AnnaBridge 165:d1b4690b3f8b 322 * \param rnr First region number to be configured.
AnnaBridge 165:d1b4690b3f8b 323 * \param table Pointer to the MPU configuration table.
AnnaBridge 165:d1b4690b3f8b 324 * \param cnt Amount of regions to be configured.
AnnaBridge 165:d1b4690b3f8b 325 */
AnnaBridge 165:d1b4690b3f8b 326 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 165:d1b4690b3f8b 327 {
AnnaBridge 165:d1b4690b3f8b 328 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
AnnaBridge 165:d1b4690b3f8b 329 }
AnnaBridge 165:d1b4690b3f8b 330 #endif
AnnaBridge 165:d1b4690b3f8b 331
AnnaBridge 165:d1b4690b3f8b 332 #endif
AnnaBridge 165:d1b4690b3f8b 333