The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
TARGET_VBLUNO52/core_ca.h@157:e7ca05fa8600, 2017-11-09 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 09 11:14:10 2017 +0000
- Revision:
- 157:e7ca05fa8600
- Parent:
- 148:fd96258d940d
Release 155 of the mbed library.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 148:fd96258d940d | 1 | /**************************************************************************//** |
Kojto | 148:fd96258d940d | 2 | * @file core_ca.h |
Kojto | 148:fd96258d940d | 3 | * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File |
Kojto | 148:fd96258d940d | 4 | * @version V1.00 |
Kojto | 148:fd96258d940d | 5 | * @date 22. Feb 2017 |
Kojto | 148:fd96258d940d | 6 | ******************************************************************************/ |
Kojto | 148:fd96258d940d | 7 | /* |
Kojto | 148:fd96258d940d | 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. |
Kojto | 148:fd96258d940d | 9 | * |
Kojto | 148:fd96258d940d | 10 | * SPDX-License-Identifier: Apache-2.0 |
Kojto | 148:fd96258d940d | 11 | * |
Kojto | 148:fd96258d940d | 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
Kojto | 148:fd96258d940d | 13 | * not use this file except in compliance with the License. |
Kojto | 148:fd96258d940d | 14 | * You may obtain a copy of the License at |
Kojto | 148:fd96258d940d | 15 | * |
Kojto | 148:fd96258d940d | 16 | * www.apache.org/licenses/LICENSE-2.0 |
Kojto | 148:fd96258d940d | 17 | * |
Kojto | 148:fd96258d940d | 18 | * Unless required by applicable law or agreed to in writing, software |
Kojto | 148:fd96258d940d | 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
Kojto | 148:fd96258d940d | 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
Kojto | 148:fd96258d940d | 21 | * See the License for the specific language governing permissions and |
Kojto | 148:fd96258d940d | 22 | * limitations under the License. |
Kojto | 148:fd96258d940d | 23 | */ |
Kojto | 148:fd96258d940d | 24 | |
Kojto | 148:fd96258d940d | 25 | #if defined ( __ICCARM__ ) |
Kojto | 148:fd96258d940d | 26 | #pragma system_include /* treat file as system include file for MISRA check */ |
Kojto | 148:fd96258d940d | 27 | #endif |
Kojto | 148:fd96258d940d | 28 | |
Kojto | 148:fd96258d940d | 29 | #ifdef __cplusplus |
Kojto | 148:fd96258d940d | 30 | extern "C" { |
Kojto | 148:fd96258d940d | 31 | #endif |
Kojto | 148:fd96258d940d | 32 | |
Kojto | 148:fd96258d940d | 33 | #ifndef __CORE_CA_H_GENERIC |
Kojto | 148:fd96258d940d | 34 | #define __CORE_CA_H_GENERIC |
Kojto | 148:fd96258d940d | 35 | |
Kojto | 148:fd96258d940d | 36 | |
Kojto | 148:fd96258d940d | 37 | /******************************************************************************* |
Kojto | 148:fd96258d940d | 38 | * CMSIS definitions |
Kojto | 148:fd96258d940d | 39 | ******************************************************************************/ |
Kojto | 148:fd96258d940d | 40 | |
Kojto | 148:fd96258d940d | 41 | /* CMSIS CA definitions */ |
Kojto | 148:fd96258d940d | 42 | #define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS HAL main version */ |
Kojto | 148:fd96258d940d | 43 | #define __CA_CMSIS_VERSION_SUB (0U) /*!< \brief [15:0] CMSIS HAL sub version */ |
Kojto | 148:fd96258d940d | 44 | #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ |
Kojto | 148:fd96258d940d | 45 | __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS HAL version number */ |
Kojto | 148:fd96258d940d | 46 | |
Kojto | 148:fd96258d940d | 47 | #if defined ( __CC_ARM ) |
Kojto | 148:fd96258d940d | 48 | #if defined __TARGET_FPU_VFP |
Kojto | 148:fd96258d940d | 49 | #if (__FPU_PRESENT == 1) |
Kojto | 148:fd96258d940d | 50 | #define __FPU_USED 1U |
Kojto | 148:fd96258d940d | 51 | #else |
Kojto | 148:fd96258d940d | 52 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 148:fd96258d940d | 53 | #define __FPU_USED 0U |
Kojto | 148:fd96258d940d | 54 | #endif |
Kojto | 148:fd96258d940d | 55 | #else |
Kojto | 148:fd96258d940d | 56 | #define __FPU_USED 0U |
Kojto | 148:fd96258d940d | 57 | #endif |
Kojto | 148:fd96258d940d | 58 | |
Kojto | 148:fd96258d940d | 59 | #elif defined ( __ICCARM__ ) |
Kojto | 148:fd96258d940d | 60 | #if defined __ARMVFP__ |
Kojto | 148:fd96258d940d | 61 | #if (__FPU_PRESENT == 1) |
Kojto | 148:fd96258d940d | 62 | #define __FPU_USED 1U |
Kojto | 148:fd96258d940d | 63 | #else |
Kojto | 148:fd96258d940d | 64 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 148:fd96258d940d | 65 | #define __FPU_USED 0U |
Kojto | 148:fd96258d940d | 66 | #endif |
Kojto | 148:fd96258d940d | 67 | #else |
Kojto | 148:fd96258d940d | 68 | #define __FPU_USED 0U |
Kojto | 148:fd96258d940d | 69 | #endif |
Kojto | 148:fd96258d940d | 70 | |
Kojto | 148:fd96258d940d | 71 | #elif defined ( __TMS470__ ) |
Kojto | 148:fd96258d940d | 72 | #if defined __TI_VFP_SUPPORT__ |
Kojto | 148:fd96258d940d | 73 | #if (__FPU_PRESENT == 1) |
Kojto | 148:fd96258d940d | 74 | #define __FPU_USED 1U |
Kojto | 148:fd96258d940d | 75 | #else |
Kojto | 148:fd96258d940d | 76 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 148:fd96258d940d | 77 | #define __FPU_USED 0U |
Kojto | 148:fd96258d940d | 78 | #endif |
Kojto | 148:fd96258d940d | 79 | #else |
Kojto | 148:fd96258d940d | 80 | #define __FPU_USED 0U |
Kojto | 148:fd96258d940d | 81 | #endif |
Kojto | 148:fd96258d940d | 82 | |
Kojto | 148:fd96258d940d | 83 | #elif defined ( __GNUC__ ) |
Kojto | 148:fd96258d940d | 84 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
Kojto | 148:fd96258d940d | 85 | #if (__FPU_PRESENT == 1) |
Kojto | 148:fd96258d940d | 86 | #define __FPU_USED 1U |
Kojto | 148:fd96258d940d | 87 | #else |
Kojto | 148:fd96258d940d | 88 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 148:fd96258d940d | 89 | #define __FPU_USED 0U |
Kojto | 148:fd96258d940d | 90 | #endif |
Kojto | 148:fd96258d940d | 91 | #else |
Kojto | 148:fd96258d940d | 92 | #define __FPU_USED 0U |
Kojto | 148:fd96258d940d | 93 | #endif |
Kojto | 148:fd96258d940d | 94 | |
Kojto | 148:fd96258d940d | 95 | #elif defined ( __TASKING__ ) |
Kojto | 148:fd96258d940d | 96 | #if defined __FPU_VFP__ |
Kojto | 148:fd96258d940d | 97 | #if (__FPU_PRESENT == 1) |
Kojto | 148:fd96258d940d | 98 | #define __FPU_USED 1U |
Kojto | 148:fd96258d940d | 99 | #else |
Kojto | 148:fd96258d940d | 100 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 148:fd96258d940d | 101 | #define __FPU_USED 0U |
Kojto | 148:fd96258d940d | 102 | #endif |
Kojto | 148:fd96258d940d | 103 | #else |
Kojto | 148:fd96258d940d | 104 | #define __FPU_USED 0U |
Kojto | 148:fd96258d940d | 105 | #endif |
Kojto | 148:fd96258d940d | 106 | #endif |
Kojto | 148:fd96258d940d | 107 | |
Kojto | 148:fd96258d940d | 108 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
Kojto | 148:fd96258d940d | 109 | |
Kojto | 148:fd96258d940d | 110 | #ifdef __cplusplus |
Kojto | 148:fd96258d940d | 111 | } |
Kojto | 148:fd96258d940d | 112 | #endif |
Kojto | 148:fd96258d940d | 113 | |
Kojto | 148:fd96258d940d | 114 | #endif /* __CORE_CA_H_GENERIC */ |
Kojto | 148:fd96258d940d | 115 | |
Kojto | 148:fd96258d940d | 116 | #ifndef __CMSIS_GENERIC |
Kojto | 148:fd96258d940d | 117 | |
Kojto | 148:fd96258d940d | 118 | #ifndef __CORE_CA_H_DEPENDANT |
Kojto | 148:fd96258d940d | 119 | #define __CORE_CA_H_DEPENDANT |
Kojto | 148:fd96258d940d | 120 | |
Kojto | 148:fd96258d940d | 121 | #ifdef __cplusplus |
Kojto | 148:fd96258d940d | 122 | extern "C" { |
Kojto | 148:fd96258d940d | 123 | #endif |
Kojto | 148:fd96258d940d | 124 | |
Kojto | 148:fd96258d940d | 125 | /* check device defines and use defaults */ |
Kojto | 148:fd96258d940d | 126 | #if defined __CHECK_DEVICE_DEFINES |
Kojto | 148:fd96258d940d | 127 | #ifndef __CA_REV |
Kojto | 148:fd96258d940d | 128 | #define __CA_REV 0x0000U |
Kojto | 148:fd96258d940d | 129 | #warning "__CA_REV not defined in device header file; using default!" |
Kojto | 148:fd96258d940d | 130 | #endif |
Kojto | 148:fd96258d940d | 131 | |
Kojto | 148:fd96258d940d | 132 | #ifndef __FPU_PRESENT |
Kojto | 148:fd96258d940d | 133 | #define __FPU_PRESENT 0U |
Kojto | 148:fd96258d940d | 134 | #warning "__FPU_PRESENT not defined in device header file; using default!" |
Kojto | 148:fd96258d940d | 135 | #endif |
Kojto | 148:fd96258d940d | 136 | |
Kojto | 148:fd96258d940d | 137 | #ifndef __MPU_PRESENT |
Kojto | 148:fd96258d940d | 138 | #define __MPU_PRESENT 0U |
Kojto | 148:fd96258d940d | 139 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
Kojto | 148:fd96258d940d | 140 | #endif |
Kojto | 148:fd96258d940d | 141 | |
Kojto | 148:fd96258d940d | 142 | #ifndef __GIC_PRESENT |
Kojto | 148:fd96258d940d | 143 | #define __GIC_PRESENT 1U |
Kojto | 148:fd96258d940d | 144 | #warning "__GIC_PRESENT not defined in device header file; using default!" |
Kojto | 148:fd96258d940d | 145 | #endif |
Kojto | 148:fd96258d940d | 146 | |
Kojto | 148:fd96258d940d | 147 | #ifndef __TIM_PRESENT |
Kojto | 148:fd96258d940d | 148 | #define __TIM_PRESENT 1U |
Kojto | 148:fd96258d940d | 149 | #warning "__TIM_PRESENT not defined in device header file; using default!" |
Kojto | 148:fd96258d940d | 150 | #endif |
Kojto | 148:fd96258d940d | 151 | |
Kojto | 148:fd96258d940d | 152 | #ifndef __L2C_PRESENT |
Kojto | 148:fd96258d940d | 153 | #define __L2C_PRESENT 0U |
Kojto | 148:fd96258d940d | 154 | #warning "__L2C_PRESENT not defined in device header file; using default!" |
Kojto | 148:fd96258d940d | 155 | #endif |
Kojto | 148:fd96258d940d | 156 | #endif |
Kojto | 148:fd96258d940d | 157 | |
Kojto | 148:fd96258d940d | 158 | /* IO definitions (access restrictions to peripheral registers) */ |
Kojto | 148:fd96258d940d | 159 | #ifdef __cplusplus |
Kojto | 148:fd96258d940d | 160 | #define __I volatile /*!< \brief Defines 'read only' permissions */ |
Kojto | 148:fd96258d940d | 161 | #else |
Kojto | 148:fd96258d940d | 162 | #define __I volatile const /*!< \brief Defines 'read only' permissions */ |
Kojto | 148:fd96258d940d | 163 | #endif |
Kojto | 148:fd96258d940d | 164 | #define __O volatile /*!< \brief Defines 'write only' permissions */ |
Kojto | 148:fd96258d940d | 165 | #define __IO volatile /*!< \brief Defines 'read / write' permissions */ |
Kojto | 148:fd96258d940d | 166 | |
Kojto | 148:fd96258d940d | 167 | /* following defines should be used for structure members */ |
Kojto | 148:fd96258d940d | 168 | #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ |
Kojto | 148:fd96258d940d | 169 | #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ |
Kojto | 148:fd96258d940d | 170 | #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ |
Kojto | 148:fd96258d940d | 171 | |
Kojto | 148:fd96258d940d | 172 | |
Kojto | 148:fd96258d940d | 173 | /******************************************************************************* |
Kojto | 148:fd96258d940d | 174 | * Register Abstraction |
Kojto | 148:fd96258d940d | 175 | Core Register contain: |
Kojto | 148:fd96258d940d | 176 | - CPSR |
Kojto | 148:fd96258d940d | 177 | - CP15 Registers |
Kojto | 148:fd96258d940d | 178 | - L2C-310 Cache Controller |
Kojto | 148:fd96258d940d | 179 | - Generic Interrupt Controller Distributor |
Kojto | 148:fd96258d940d | 180 | - Generic Interrupt Controller Interface |
Kojto | 148:fd96258d940d | 181 | ******************************************************************************/ |
Kojto | 148:fd96258d940d | 182 | |
Kojto | 148:fd96258d940d | 183 | /* Core Register CPSR */ |
Kojto | 148:fd96258d940d | 184 | typedef union |
Kojto | 148:fd96258d940d | 185 | { |
Kojto | 148:fd96258d940d | 186 | struct |
Kojto | 148:fd96258d940d | 187 | { |
Kojto | 148:fd96258d940d | 188 | uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ |
Kojto | 148:fd96258d940d | 189 | uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ |
Kojto | 148:fd96258d940d | 190 | uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ |
Kojto | 148:fd96258d940d | 191 | uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ |
Kojto | 148:fd96258d940d | 192 | uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ |
Kojto | 148:fd96258d940d | 193 | uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ |
Kojto | 148:fd96258d940d | 194 | uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ |
Kojto | 148:fd96258d940d | 195 | uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ |
Kojto | 148:fd96258d940d | 196 | uint32_t _reserved0:4; /*!< \brief bit: 20..23 Reserved */ |
Kojto | 148:fd96258d940d | 197 | uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ |
Kojto | 148:fd96258d940d | 198 | uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ |
Kojto | 148:fd96258d940d | 199 | uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ |
Kojto | 148:fd96258d940d | 200 | uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ |
Kojto | 148:fd96258d940d | 201 | uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ |
Kojto | 148:fd96258d940d | 202 | uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ |
Kojto | 148:fd96258d940d | 203 | uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ |
Kojto | 148:fd96258d940d | 204 | } b; /*!< \brief Structure used for bit access */ |
Kojto | 148:fd96258d940d | 205 | uint32_t w; /*!< \brief Type used for word access */ |
Kojto | 148:fd96258d940d | 206 | } CPSR_Type; |
Kojto | 148:fd96258d940d | 207 | |
Kojto | 148:fd96258d940d | 208 | /* CPSR Register Definitions */ |
Kojto | 148:fd96258d940d | 209 | #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ |
Kojto | 148:fd96258d940d | 210 | #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ |
Kojto | 148:fd96258d940d | 211 | |
Kojto | 148:fd96258d940d | 212 | #define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ |
Kojto | 148:fd96258d940d | 213 | #define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ |
Kojto | 148:fd96258d940d | 214 | |
Kojto | 148:fd96258d940d | 215 | #define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ |
Kojto | 148:fd96258d940d | 216 | #define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ |
Kojto | 148:fd96258d940d | 217 | |
Kojto | 148:fd96258d940d | 218 | #define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ |
Kojto | 148:fd96258d940d | 219 | #define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ |
Kojto | 148:fd96258d940d | 220 | |
Kojto | 148:fd96258d940d | 221 | #define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ |
Kojto | 148:fd96258d940d | 222 | #define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ |
Kojto | 148:fd96258d940d | 223 | |
Kojto | 148:fd96258d940d | 224 | #define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ |
Kojto | 148:fd96258d940d | 225 | #define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ |
Kojto | 148:fd96258d940d | 226 | |
Kojto | 148:fd96258d940d | 227 | #define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ |
Kojto | 148:fd96258d940d | 228 | #define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ |
Kojto | 148:fd96258d940d | 229 | |
Kojto | 148:fd96258d940d | 230 | #define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ |
Kojto | 148:fd96258d940d | 231 | #define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ |
Kojto | 148:fd96258d940d | 232 | |
Kojto | 148:fd96258d940d | 233 | #define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ |
Kojto | 148:fd96258d940d | 234 | #define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ |
Kojto | 148:fd96258d940d | 235 | |
Kojto | 148:fd96258d940d | 236 | #define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ |
Kojto | 148:fd96258d940d | 237 | #define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ |
Kojto | 148:fd96258d940d | 238 | |
Kojto | 148:fd96258d940d | 239 | #define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ |
Kojto | 148:fd96258d940d | 240 | #define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ |
Kojto | 148:fd96258d940d | 241 | |
Kojto | 148:fd96258d940d | 242 | #define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ |
Kojto | 148:fd96258d940d | 243 | #define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ |
Kojto | 148:fd96258d940d | 244 | |
Kojto | 148:fd96258d940d | 245 | #define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ |
Kojto | 148:fd96258d940d | 246 | #define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ |
Kojto | 148:fd96258d940d | 247 | |
Kojto | 148:fd96258d940d | 248 | #define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ |
Kojto | 148:fd96258d940d | 249 | #define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ |
Kojto | 148:fd96258d940d | 250 | |
Kojto | 148:fd96258d940d | 251 | #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ |
Kojto | 148:fd96258d940d | 252 | #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ |
Kojto | 148:fd96258d940d | 253 | |
Kojto | 148:fd96258d940d | 254 | /* CP15 Register SCTLR */ |
Kojto | 148:fd96258d940d | 255 | typedef union |
Kojto | 148:fd96258d940d | 256 | { |
Kojto | 148:fd96258d940d | 257 | struct |
Kojto | 148:fd96258d940d | 258 | { |
Kojto | 148:fd96258d940d | 259 | uint32_t M:1; /*!< \brief bit: 0 MMU enable */ |
Kojto | 148:fd96258d940d | 260 | uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ |
Kojto | 148:fd96258d940d | 261 | uint32_t C:1; /*!< \brief bit: 2 Cache enable */ |
Kojto | 148:fd96258d940d | 262 | uint32_t _reserved0:2; /*!< \brief bit: 3.. 4 Reserved */ |
Kojto | 148:fd96258d940d | 263 | uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ |
Kojto | 148:fd96258d940d | 264 | uint32_t _reserved1:1; /*!< \brief bit: 6 Reserved */ |
Kojto | 148:fd96258d940d | 265 | uint32_t B:1; /*!< \brief bit: 7 Endianness model */ |
Kojto | 148:fd96258d940d | 266 | uint32_t _reserved2:2; /*!< \brief bit: 8.. 9 Reserved */ |
Kojto | 148:fd96258d940d | 267 | uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ |
Kojto | 148:fd96258d940d | 268 | uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ |
Kojto | 148:fd96258d940d | 269 | uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ |
Kojto | 148:fd96258d940d | 270 | uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ |
Kojto | 148:fd96258d940d | 271 | uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ |
Kojto | 148:fd96258d940d | 272 | uint32_t _reserved3:2; /*!< \brief bit:15..16 Reserved */ |
Kojto | 148:fd96258d940d | 273 | uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ |
Kojto | 148:fd96258d940d | 274 | uint32_t _reserved4:1; /*!< \brief bit: 18 Reserved */ |
Kojto | 148:fd96258d940d | 275 | uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ |
Kojto | 148:fd96258d940d | 276 | uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ |
Kojto | 148:fd96258d940d | 277 | uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ |
Kojto | 148:fd96258d940d | 278 | uint32_t U:1; /*!< \brief bit: 22 Alignment model */ |
Kojto | 148:fd96258d940d | 279 | uint32_t _reserved5:1; /*!< \brief bit: 23 Reserved */ |
Kojto | 148:fd96258d940d | 280 | uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ |
Kojto | 148:fd96258d940d | 281 | uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ |
Kojto | 148:fd96258d940d | 282 | uint32_t _reserved6:1; /*!< \brief bit: 26 Reserved */ |
Kojto | 148:fd96258d940d | 283 | uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ |
Kojto | 148:fd96258d940d | 284 | uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ |
Kojto | 148:fd96258d940d | 285 | uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ |
Kojto | 148:fd96258d940d | 286 | uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ |
Kojto | 148:fd96258d940d | 287 | uint32_t _reserved7:1; /*!< \brief bit: 31 Reserved */ |
Kojto | 148:fd96258d940d | 288 | } b; /*!< \brief Structure used for bit access */ |
Kojto | 148:fd96258d940d | 289 | uint32_t w; /*!< \brief Type used for word access */ |
Kojto | 148:fd96258d940d | 290 | } SCTLR_Type; |
Kojto | 148:fd96258d940d | 291 | |
Kojto | 148:fd96258d940d | 292 | #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ |
Kojto | 148:fd96258d940d | 293 | #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ |
Kojto | 148:fd96258d940d | 294 | |
Kojto | 148:fd96258d940d | 295 | #define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ |
Kojto | 148:fd96258d940d | 296 | #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ |
Kojto | 148:fd96258d940d | 297 | |
Kojto | 148:fd96258d940d | 298 | #define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ |
Kojto | 148:fd96258d940d | 299 | #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ |
Kojto | 148:fd96258d940d | 300 | |
Kojto | 148:fd96258d940d | 301 | #define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ |
Kojto | 148:fd96258d940d | 302 | #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ |
Kojto | 148:fd96258d940d | 303 | |
Kojto | 148:fd96258d940d | 304 | #define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ |
Kojto | 148:fd96258d940d | 305 | #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ |
Kojto | 148:fd96258d940d | 306 | |
Kojto | 148:fd96258d940d | 307 | #define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ |
Kojto | 148:fd96258d940d | 308 | #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ |
Kojto | 148:fd96258d940d | 309 | |
Kojto | 148:fd96258d940d | 310 | #define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ |
Kojto | 148:fd96258d940d | 311 | #define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ |
Kojto | 148:fd96258d940d | 312 | |
Kojto | 148:fd96258d940d | 313 | #define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ |
Kojto | 148:fd96258d940d | 314 | #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ |
Kojto | 148:fd96258d940d | 315 | |
Kojto | 148:fd96258d940d | 316 | #define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ |
Kojto | 148:fd96258d940d | 317 | #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ |
Kojto | 148:fd96258d940d | 318 | |
Kojto | 148:fd96258d940d | 319 | #define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ |
Kojto | 148:fd96258d940d | 320 | #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ |
Kojto | 148:fd96258d940d | 321 | |
Kojto | 148:fd96258d940d | 322 | #define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ |
Kojto | 148:fd96258d940d | 323 | #define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ |
Kojto | 148:fd96258d940d | 324 | |
Kojto | 148:fd96258d940d | 325 | #define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ |
Kojto | 148:fd96258d940d | 326 | #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ |
Kojto | 148:fd96258d940d | 327 | |
Kojto | 148:fd96258d940d | 328 | #define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ |
Kojto | 148:fd96258d940d | 329 | #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ |
Kojto | 148:fd96258d940d | 330 | |
Kojto | 148:fd96258d940d | 331 | #define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ |
Kojto | 148:fd96258d940d | 332 | #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ |
Kojto | 148:fd96258d940d | 333 | |
Kojto | 148:fd96258d940d | 334 | #define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ |
Kojto | 148:fd96258d940d | 335 | #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ |
Kojto | 148:fd96258d940d | 336 | |
Kojto | 148:fd96258d940d | 337 | #define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ |
Kojto | 148:fd96258d940d | 338 | #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ |
Kojto | 148:fd96258d940d | 339 | |
Kojto | 148:fd96258d940d | 340 | #define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ |
Kojto | 148:fd96258d940d | 341 | #define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ |
Kojto | 148:fd96258d940d | 342 | |
Kojto | 148:fd96258d940d | 343 | #define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ |
Kojto | 148:fd96258d940d | 344 | #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ |
Kojto | 148:fd96258d940d | 345 | |
Kojto | 148:fd96258d940d | 346 | #define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ |
Kojto | 148:fd96258d940d | 347 | #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ |
Kojto | 148:fd96258d940d | 348 | |
Kojto | 148:fd96258d940d | 349 | #define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ |
Kojto | 148:fd96258d940d | 350 | #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ |
Kojto | 148:fd96258d940d | 351 | |
Kojto | 148:fd96258d940d | 352 | #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ |
Kojto | 148:fd96258d940d | 353 | #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ |
Kojto | 148:fd96258d940d | 354 | |
Kojto | 148:fd96258d940d | 355 | /* CP15 Register CPACR */ |
Kojto | 148:fd96258d940d | 356 | typedef union |
Kojto | 148:fd96258d940d | 357 | { |
Kojto | 148:fd96258d940d | 358 | struct |
Kojto | 148:fd96258d940d | 359 | { |
Kojto | 148:fd96258d940d | 360 | uint32_t _reserved0:20; /*!< \brief bit: 0..19 Reserved */ |
Kojto | 148:fd96258d940d | 361 | uint32_t cp10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ |
Kojto | 148:fd96258d940d | 362 | uint32_t cp11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ |
Kojto | 148:fd96258d940d | 363 | uint32_t _reserved1:6; /*!< \brief bit:24..29 Reserved */ |
Kojto | 148:fd96258d940d | 364 | uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ |
Kojto | 148:fd96258d940d | 365 | uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ |
Kojto | 148:fd96258d940d | 366 | } b; /*!< \brief Structure used for bit access */ |
Kojto | 148:fd96258d940d | 367 | uint32_t w; /*!< \brief Type used for word access */ |
Kojto | 148:fd96258d940d | 368 | } CPACR_Type; |
Kojto | 148:fd96258d940d | 369 | |
Kojto | 148:fd96258d940d | 370 | #define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ |
Kojto | 148:fd96258d940d | 371 | #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ |
Kojto | 148:fd96258d940d | 372 | |
Kojto | 148:fd96258d940d | 373 | #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ |
Kojto | 148:fd96258d940d | 374 | #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ |
Kojto | 148:fd96258d940d | 375 | |
Kojto | 148:fd96258d940d | 376 | #define CPACR_cp11_Pos 22U /*!< \brief CPACR: cp11 Position */ |
Kojto | 148:fd96258d940d | 377 | #define CPACR_cp11_Msk (3UL << CPACR_cp11_Pos) /*!< \brief CPACR: cp11 Mask */ |
Kojto | 148:fd96258d940d | 378 | |
Kojto | 148:fd96258d940d | 379 | #define CPACR_cp10_Pos 20U /*!< \brief CPACR: cp10 Position */ |
Kojto | 148:fd96258d940d | 380 | #define CPACR_cp10_Msk (3UL << CPACR_cp10_Pos) /*!< \brief CPACR: cp10 Mask */ |
Kojto | 148:fd96258d940d | 381 | |
Kojto | 148:fd96258d940d | 382 | /* CP15 Register DFSR */ |
Kojto | 148:fd96258d940d | 383 | typedef union |
Kojto | 148:fd96258d940d | 384 | { |
Kojto | 148:fd96258d940d | 385 | struct |
Kojto | 148:fd96258d940d | 386 | { |
Kojto | 148:fd96258d940d | 387 | uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ |
Kojto | 148:fd96258d940d | 388 | uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ |
Kojto | 148:fd96258d940d | 389 | uint32_t _reserved0:2; /*!< \brief bit: 8.. 9 Reserved */ |
Kojto | 148:fd96258d940d | 390 | uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ |
Kojto | 148:fd96258d940d | 391 | uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ |
Kojto | 148:fd96258d940d | 392 | uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ |
Kojto | 148:fd96258d940d | 393 | uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ |
Kojto | 148:fd96258d940d | 394 | uint32_t _reserved1:18; /*!< \brief bit:14..31 Reserved */ |
Kojto | 148:fd96258d940d | 395 | } b; /*!< \brief Structure used for bit access */ |
Kojto | 148:fd96258d940d | 396 | uint32_t w; /*!< \brief Type used for word access */ |
Kojto | 148:fd96258d940d | 397 | } DFSR_Type; |
Kojto | 148:fd96258d940d | 398 | |
Kojto | 148:fd96258d940d | 399 | #define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ |
Kojto | 148:fd96258d940d | 400 | #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ |
Kojto | 148:fd96258d940d | 401 | |
Kojto | 148:fd96258d940d | 402 | #define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ |
Kojto | 148:fd96258d940d | 403 | #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ |
Kojto | 148:fd96258d940d | 404 | |
Kojto | 148:fd96258d940d | 405 | #define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ |
Kojto | 148:fd96258d940d | 406 | #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ |
Kojto | 148:fd96258d940d | 407 | |
Kojto | 148:fd96258d940d | 408 | #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ |
Kojto | 148:fd96258d940d | 409 | #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ |
Kojto | 148:fd96258d940d | 410 | |
Kojto | 148:fd96258d940d | 411 | #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ |
Kojto | 148:fd96258d940d | 412 | #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ |
Kojto | 148:fd96258d940d | 413 | |
Kojto | 148:fd96258d940d | 414 | #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ |
Kojto | 148:fd96258d940d | 415 | #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ |
Kojto | 148:fd96258d940d | 416 | |
Kojto | 148:fd96258d940d | 417 | /* CP15 Register IFSR */ |
Kojto | 148:fd96258d940d | 418 | typedef union |
Kojto | 148:fd96258d940d | 419 | { |
Kojto | 148:fd96258d940d | 420 | struct |
Kojto | 148:fd96258d940d | 421 | { |
Kojto | 148:fd96258d940d | 422 | uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ |
Kojto | 148:fd96258d940d | 423 | uint32_t _reserved0:6; /*!< \brief bit: 4.. 9 Reserved */ |
Kojto | 148:fd96258d940d | 424 | uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ |
Kojto | 148:fd96258d940d | 425 | uint32_t _reserved1:1; /*!< \brief bit: 11 Reserved */ |
Kojto | 148:fd96258d940d | 426 | uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ |
Kojto | 148:fd96258d940d | 427 | uint32_t _reserved2:19; /*!< \brief bit:13..31 Reserved */ |
Kojto | 148:fd96258d940d | 428 | } b; /*!< \brief Structure used for bit access */ |
Kojto | 148:fd96258d940d | 429 | uint32_t w; /*!< \brief Type used for word access */ |
Kojto | 148:fd96258d940d | 430 | } IFSR_Type; |
Kojto | 148:fd96258d940d | 431 | |
Kojto | 148:fd96258d940d | 432 | #define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ |
Kojto | 148:fd96258d940d | 433 | #define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ |
Kojto | 148:fd96258d940d | 434 | |
Kojto | 148:fd96258d940d | 435 | #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ |
Kojto | 148:fd96258d940d | 436 | #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ |
Kojto | 148:fd96258d940d | 437 | |
Kojto | 148:fd96258d940d | 438 | #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ |
Kojto | 148:fd96258d940d | 439 | #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ |
Kojto | 148:fd96258d940d | 440 | |
Kojto | 148:fd96258d940d | 441 | /* CP15 Register ISR */ |
Kojto | 148:fd96258d940d | 442 | typedef union |
Kojto | 148:fd96258d940d | 443 | { |
Kojto | 148:fd96258d940d | 444 | struct |
Kojto | 148:fd96258d940d | 445 | { |
Kojto | 148:fd96258d940d | 446 | uint32_t _reserved0:6; /*!< \brief bit: 0.. 5 Reserved */ |
Kojto | 148:fd96258d940d | 447 | uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ |
Kojto | 148:fd96258d940d | 448 | uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ |
Kojto | 148:fd96258d940d | 449 | uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ |
Kojto | 148:fd96258d940d | 450 | uint32_t _reserved1:23; /*!< \brief bit:14..31 Reserved */ |
Kojto | 148:fd96258d940d | 451 | } b; /*!< \brief Structure used for bit access */ |
Kojto | 148:fd96258d940d | 452 | uint32_t w; /*!< \brief Type used for word access */ |
Kojto | 148:fd96258d940d | 453 | } ISR_Type; |
Kojto | 148:fd96258d940d | 454 | |
Kojto | 148:fd96258d940d | 455 | #define ISR_A_Pos 13U /*!< \brief ISR: A Position */ |
Kojto | 148:fd96258d940d | 456 | #define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ |
Kojto | 148:fd96258d940d | 457 | |
Kojto | 148:fd96258d940d | 458 | #define ISR_I_Pos 12U /*!< \brief ISR: I Position */ |
Kojto | 148:fd96258d940d | 459 | #define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ |
Kojto | 148:fd96258d940d | 460 | |
Kojto | 148:fd96258d940d | 461 | #define ISR_F_Pos 11U /*!< \brief ISR: F Position */ |
Kojto | 148:fd96258d940d | 462 | #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ |
Kojto | 148:fd96258d940d | 463 | |
Kojto | 148:fd96258d940d | 464 | |
Kojto | 148:fd96258d940d | 465 | /** |
Kojto | 148:fd96258d940d | 466 | \brief Union type to access the L2C_310 Cache Controller. |
Kojto | 148:fd96258d940d | 467 | */ |
Kojto | 148:fd96258d940d | 468 | #if (__L2C_PRESENT == 1U) |
Kojto | 148:fd96258d940d | 469 | typedef struct |
Kojto | 148:fd96258d940d | 470 | { |
Kojto | 148:fd96258d940d | 471 | __I uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 Cache ID Register */ |
Kojto | 148:fd96258d940d | 472 | __I uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 Cache Type Register */ |
Kojto | 148:fd96258d940d | 473 | uint32_t RESERVED0[0x3e]; |
Kojto | 148:fd96258d940d | 474 | __IO uint32_t CONTROL; /*!< \brief Offset: 0x0100 Control Register */ |
Kojto | 148:fd96258d940d | 475 | __IO uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 Auxiliary Control */ |
Kojto | 148:fd96258d940d | 476 | uint32_t RESERVED1[0x3e]; |
Kojto | 148:fd96258d940d | 477 | __IO uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 Event Counter Control */ |
Kojto | 148:fd96258d940d | 478 | __IO uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 Event Counter 1 Configuration */ |
Kojto | 148:fd96258d940d | 479 | __IO uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 Event Counter 1 Configuration */ |
Kojto | 148:fd96258d940d | 480 | uint32_t RESERVED2[0x2]; |
Kojto | 148:fd96258d940d | 481 | __IO uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 Interrupt Mask */ |
Kojto | 148:fd96258d940d | 482 | __I uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 Masked Interrupt Status */ |
Kojto | 148:fd96258d940d | 483 | __I uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c Raw Interrupt Status */ |
Kojto | 148:fd96258d940d | 484 | __O uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 Interrupt Clear */ |
Kojto | 148:fd96258d940d | 485 | uint32_t RESERVED3[0x143]; |
Kojto | 148:fd96258d940d | 486 | __IO uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 Cache Sync */ |
Kojto | 148:fd96258d940d | 487 | uint32_t RESERVED4[0xf]; |
Kojto | 148:fd96258d940d | 488 | __IO uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 Invalidate Line By PA */ |
Kojto | 148:fd96258d940d | 489 | uint32_t RESERVED6[2]; |
Kojto | 148:fd96258d940d | 490 | __IO uint32_t INV_WAY; /*!< \brief Offset: 0x077c Invalidate by Way */ |
Kojto | 148:fd96258d940d | 491 | uint32_t RESERVED5[0xc]; |
Kojto | 148:fd96258d940d | 492 | __IO uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 Clean Line by PA */ |
Kojto | 148:fd96258d940d | 493 | uint32_t RESERVED7[1]; |
Kojto | 148:fd96258d940d | 494 | __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 Clean Line by Index/Way */ |
Kojto | 148:fd96258d940d | 495 | __IO uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc Clean by Way */ |
Kojto | 148:fd96258d940d | 496 | uint32_t RESERVED8[0xc]; |
Kojto | 148:fd96258d940d | 497 | __IO uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 Clean and Invalidate Line by PA */ |
Kojto | 148:fd96258d940d | 498 | uint32_t RESERVED9[1]; |
Kojto | 148:fd96258d940d | 499 | __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 Clean and Invalidate Line by Index/Way */ |
Kojto | 148:fd96258d940d | 500 | __IO uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc Clean and Invalidate by Way */ |
Kojto | 148:fd96258d940d | 501 | uint32_t RESERVED10[0x40]; |
Kojto | 148:fd96258d940d | 502 | __IO uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 Data Lockdown 0 by Way */ |
Kojto | 148:fd96258d940d | 503 | __IO uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 Instruction Lockdown 0 by Way */ |
Kojto | 148:fd96258d940d | 504 | __IO uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 Data Lockdown 1 by Way */ |
Kojto | 148:fd96258d940d | 505 | __IO uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c Instruction Lockdown 1 by Way */ |
Kojto | 148:fd96258d940d | 506 | __IO uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 Data Lockdown 2 by Way */ |
Kojto | 148:fd96258d940d | 507 | __IO uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 Instruction Lockdown 2 by Way */ |
Kojto | 148:fd96258d940d | 508 | __IO uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 Data Lockdown 3 by Way */ |
Kojto | 148:fd96258d940d | 509 | __IO uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c Instruction Lockdown 3 by Way */ |
Kojto | 148:fd96258d940d | 510 | __IO uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 Data Lockdown 4 by Way */ |
Kojto | 148:fd96258d940d | 511 | __IO uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 Instruction Lockdown 4 by Way */ |
Kojto | 148:fd96258d940d | 512 | __IO uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 Data Lockdown 5 by Way */ |
Kojto | 148:fd96258d940d | 513 | __IO uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c Instruction Lockdown 5 by Way */ |
Kojto | 148:fd96258d940d | 514 | __IO uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 Data Lockdown 5 by Way */ |
Kojto | 148:fd96258d940d | 515 | __IO uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 Instruction Lockdown 5 by Way */ |
Kojto | 148:fd96258d940d | 516 | __IO uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 Data Lockdown 6 by Way */ |
Kojto | 148:fd96258d940d | 517 | __IO uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c Instruction Lockdown 6 by Way */ |
Kojto | 148:fd96258d940d | 518 | uint32_t RESERVED11[0x4]; |
Kojto | 148:fd96258d940d | 519 | __IO uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 Lockdown by Line Enable */ |
Kojto | 148:fd96258d940d | 520 | __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 Unlock All Lines by Way */ |
Kojto | 148:fd96258d940d | 521 | uint32_t RESERVED12[0xaa]; |
Kojto | 148:fd96258d940d | 522 | __IO uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 Address Filtering Start */ |
Kojto | 148:fd96258d940d | 523 | __IO uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 Address Filtering End */ |
Kojto | 148:fd96258d940d | 524 | uint32_t RESERVED13[0xce]; |
Kojto | 148:fd96258d940d | 525 | __IO uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 Debug Control Register */ |
Kojto | 148:fd96258d940d | 526 | } L2C_310_TypeDef; |
Kojto | 148:fd96258d940d | 527 | |
Kojto | 148:fd96258d940d | 528 | #define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 Declaration */ |
Kojto | 148:fd96258d940d | 529 | #endif |
Kojto | 148:fd96258d940d | 530 | |
Kojto | 148:fd96258d940d | 531 | #if (__GIC_PRESENT == 1U) |
Kojto | 148:fd96258d940d | 532 | /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) |
Kojto | 148:fd96258d940d | 533 | */ |
Kojto | 148:fd96258d940d | 534 | typedef struct |
Kojto | 148:fd96258d940d | 535 | { |
Kojto | 148:fd96258d940d | 536 | __IO uint32_t ICDDCR; |
Kojto | 148:fd96258d940d | 537 | __I uint32_t ICDICTR; |
Kojto | 148:fd96258d940d | 538 | __I uint32_t ICDIIDR; |
Kojto | 148:fd96258d940d | 539 | uint32_t RESERVED0[29]; |
Kojto | 148:fd96258d940d | 540 | __IO uint32_t ICDISR[32]; |
Kojto | 148:fd96258d940d | 541 | __IO uint32_t ICDISER[32]; |
Kojto | 148:fd96258d940d | 542 | __IO uint32_t ICDICER[32]; |
Kojto | 148:fd96258d940d | 543 | __IO uint32_t ICDISPR[32]; |
Kojto | 148:fd96258d940d | 544 | __IO uint32_t ICDICPR[32]; |
Kojto | 148:fd96258d940d | 545 | __I uint32_t ICDABR[32]; |
Kojto | 148:fd96258d940d | 546 | uint32_t RESERVED1[32]; |
Kojto | 148:fd96258d940d | 547 | __IO uint32_t ICDIPR[256]; |
Kojto | 148:fd96258d940d | 548 | __IO uint32_t ICDIPTR[256]; |
Kojto | 148:fd96258d940d | 549 | __IO uint32_t ICDICFR[64]; |
Kojto | 148:fd96258d940d | 550 | uint32_t RESERVED2[128]; |
Kojto | 148:fd96258d940d | 551 | __IO uint32_t ICDSGIR; |
Kojto | 148:fd96258d940d | 552 | } GICDistributor_Type; |
Kojto | 148:fd96258d940d | 553 | |
Kojto | 148:fd96258d940d | 554 | #define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */ |
Kojto | 148:fd96258d940d | 555 | |
Kojto | 148:fd96258d940d | 556 | /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) |
Kojto | 148:fd96258d940d | 557 | */ |
Kojto | 148:fd96258d940d | 558 | typedef struct |
Kojto | 148:fd96258d940d | 559 | { |
Kojto | 148:fd96258d940d | 560 | __IO uint32_t ICCICR; //!< \brief +0x000 - RW - CPU Interface Control Register |
Kojto | 148:fd96258d940d | 561 | __IO uint32_t ICCPMR; //!< \brief +0x004 - RW - Interrupt Priority Mask Register |
Kojto | 148:fd96258d940d | 562 | __IO uint32_t ICCBPR; //!< \brief +0x008 - RW - Binary Point Register |
Kojto | 148:fd96258d940d | 563 | __I uint32_t ICCIAR; //!< \brief +0x00C - RO - Interrupt Acknowledge Register |
Kojto | 148:fd96258d940d | 564 | __IO uint32_t ICCEOIR; //!< \brief +0x010 - WO - End of Interrupt Register |
Kojto | 148:fd96258d940d | 565 | __I uint32_t ICCRPR; //!< \brief +0x014 - RO - Running Priority Register |
Kojto | 148:fd96258d940d | 566 | __I uint32_t ICCHPIR; //!< \brief +0x018 - RO - Highest Pending Interrupt Register |
Kojto | 148:fd96258d940d | 567 | __IO uint32_t ICCABPR; //!< \brief +0x01C - RW - Aliased Binary Point Register |
Kojto | 148:fd96258d940d | 568 | uint32_t RESERVED[55]; |
Kojto | 148:fd96258d940d | 569 | __I uint32_t ICCIIDR; //!< \brief +0x0FC - RO - CPU Interface Identification Register |
Kojto | 148:fd96258d940d | 570 | } GICInterface_Type; |
Kojto | 148:fd96258d940d | 571 | |
Kojto | 148:fd96258d940d | 572 | #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */ |
Kojto | 148:fd96258d940d | 573 | #endif |
Kojto | 148:fd96258d940d | 574 | |
Kojto | 148:fd96258d940d | 575 | #if (__TIM_PRESENT == 1U) |
Kojto | 148:fd96258d940d | 576 | #if ((__CORTEX_A == 5U)||(__CORTEX_A == 9U)) |
Kojto | 148:fd96258d940d | 577 | /** \brief Structure type to access the Private Timer |
Kojto | 148:fd96258d940d | 578 | */ |
Kojto | 148:fd96258d940d | 579 | typedef struct |
Kojto | 148:fd96258d940d | 580 | { |
Kojto | 148:fd96258d940d | 581 | __IO uint32_t LOAD; //!< \brief +0x000 - RW - Private Timer Load Register |
Kojto | 148:fd96258d940d | 582 | __IO uint32_t COUNTER; //!< \brief +0x004 - RW - Private Timer Counter Register |
Kojto | 148:fd96258d940d | 583 | __IO uint32_t CONTROL; //!< \brief +0x008 - RW - Private Timer Control Register |
Kojto | 148:fd96258d940d | 584 | __IO uint32_t ISR; //!< \brief +0x00C - RO - Private Timer Interrupt Status Register |
Kojto | 148:fd96258d940d | 585 | uint32_t RESERVED[8]; |
Kojto | 148:fd96258d940d | 586 | __IO uint32_t WLOAD; //!< \brief +0x020 - RW - Watchdog Load Register |
Kojto | 148:fd96258d940d | 587 | __IO uint32_t WCOUNTER; //!< \brief +0x024 - RW - Watchdog Counter Register |
Kojto | 148:fd96258d940d | 588 | __IO uint32_t WCONTROL; //!< \brief +0x028 - RW - Watchdog Control Register |
Kojto | 148:fd96258d940d | 589 | __IO uint32_t WISR; //!< \brief +0x02C - RW - Watchdog Interrupt Status Register |
Kojto | 148:fd96258d940d | 590 | __IO uint32_t WRESET; //!< \brief +0x030 - RW - Watchdog Reset Status Register |
Kojto | 148:fd96258d940d | 591 | __I uint32_t WDISABLE; //!< \brief +0x0FC - RO - Watchdog Disable Register |
Kojto | 148:fd96258d940d | 592 | } Timer_Type; |
Kojto | 148:fd96258d940d | 593 | #define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer configuration struct */ |
Kojto | 148:fd96258d940d | 594 | #endif |
Kojto | 148:fd96258d940d | 595 | #endif |
Kojto | 148:fd96258d940d | 596 | |
Kojto | 148:fd96258d940d | 597 | /******************************************************************************* |
Kojto | 148:fd96258d940d | 598 | * Hardware Abstraction Layer |
Kojto | 148:fd96258d940d | 599 | Core Function Interface contains: |
Kojto | 148:fd96258d940d | 600 | - L1 Cache Functions |
Kojto | 148:fd96258d940d | 601 | - L2C-310 Cache Controller Functions |
Kojto | 148:fd96258d940d | 602 | - PL1 Timer Functions |
Kojto | 148:fd96258d940d | 603 | - GIC Functions |
Kojto | 148:fd96258d940d | 604 | - MMU Functions |
Kojto | 148:fd96258d940d | 605 | ******************************************************************************/ |
Kojto | 148:fd96258d940d | 606 | |
Kojto | 148:fd96258d940d | 607 | /* ########################## L1 Cache functions ################################# */ |
Kojto | 148:fd96258d940d | 608 | |
Kojto | 148:fd96258d940d | 609 | /** \brief Enable Caches |
Kojto | 148:fd96258d940d | 610 | |
Kojto | 148:fd96258d940d | 611 | Enable Caches |
Kojto | 148:fd96258d940d | 612 | */ |
Kojto | 148:fd96258d940d | 613 | __STATIC_INLINE void L1C_EnableCaches(void) { |
Kojto | 148:fd96258d940d | 614 | // Set I bit 12 to enable I Cache |
Kojto | 148:fd96258d940d | 615 | // Set C bit 2 to enable D Cache |
Kojto | 148:fd96258d940d | 616 | __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); |
Kojto | 148:fd96258d940d | 617 | } |
Kojto | 148:fd96258d940d | 618 | |
Kojto | 148:fd96258d940d | 619 | /** \brief Disable Caches |
Kojto | 148:fd96258d940d | 620 | |
Kojto | 148:fd96258d940d | 621 | Disable Caches |
Kojto | 148:fd96258d940d | 622 | */ |
Kojto | 148:fd96258d940d | 623 | __STATIC_INLINE void L1C_DisableCaches(void) { |
Kojto | 148:fd96258d940d | 624 | // Clear I bit 12 to disable I Cache |
Kojto | 148:fd96258d940d | 625 | // Clear C bit 2 to disable D Cache |
Kojto | 148:fd96258d940d | 626 | __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2)); |
Kojto | 148:fd96258d940d | 627 | __ISB(); |
Kojto | 148:fd96258d940d | 628 | } |
Kojto | 148:fd96258d940d | 629 | |
Kojto | 148:fd96258d940d | 630 | /** \brief Enable BTAC |
Kojto | 148:fd96258d940d | 631 | |
Kojto | 148:fd96258d940d | 632 | Enable BTAC |
Kojto | 148:fd96258d940d | 633 | */ |
Kojto | 148:fd96258d940d | 634 | __STATIC_INLINE void L1C_EnableBTAC(void) { |
Kojto | 148:fd96258d940d | 635 | // Set Z bit 11 to enable branch prediction |
Kojto | 148:fd96258d940d | 636 | __set_SCTLR( __get_SCTLR() | (1 << 11)); |
Kojto | 148:fd96258d940d | 637 | __ISB(); |
Kojto | 148:fd96258d940d | 638 | } |
Kojto | 148:fd96258d940d | 639 | |
Kojto | 148:fd96258d940d | 640 | /** \brief Disable BTAC |
Kojto | 148:fd96258d940d | 641 | |
Kojto | 148:fd96258d940d | 642 | Disable BTAC |
Kojto | 148:fd96258d940d | 643 | */ |
Kojto | 148:fd96258d940d | 644 | __STATIC_INLINE void L1C_DisableBTAC(void) { |
Kojto | 148:fd96258d940d | 645 | // Clear Z bit 11 to disable branch prediction |
Kojto | 148:fd96258d940d | 646 | __set_SCTLR( __get_SCTLR() & ~(1 << 11)); |
Kojto | 148:fd96258d940d | 647 | } |
Kojto | 148:fd96258d940d | 648 | |
Kojto | 148:fd96258d940d | 649 | /** \brief Invalidate entire branch predictor array |
Kojto | 148:fd96258d940d | 650 | |
Kojto | 148:fd96258d940d | 651 | BPIALL. Branch Predictor Invalidate All. |
Kojto | 148:fd96258d940d | 652 | */ |
Kojto | 148:fd96258d940d | 653 | |
Kojto | 148:fd96258d940d | 654 | __STATIC_INLINE void L1C_InvalidateBTAC(void) { |
Kojto | 148:fd96258d940d | 655 | __set_BPIALL(0); |
Kojto | 148:fd96258d940d | 656 | __DSB(); //ensure completion of the invalidation |
Kojto | 148:fd96258d940d | 657 | __ISB(); //ensure instruction fetch path sees new state |
Kojto | 148:fd96258d940d | 658 | } |
Kojto | 148:fd96258d940d | 659 | |
Kojto | 148:fd96258d940d | 660 | /** \brief Invalidate the whole I$ |
Kojto | 148:fd96258d940d | 661 | |
Kojto | 148:fd96258d940d | 662 | ICIALLU. Instruction Cache Invalidate All to PoU |
Kojto | 148:fd96258d940d | 663 | */ |
Kojto | 148:fd96258d940d | 664 | __STATIC_INLINE void L1C_InvalidateICacheAll(void) { |
Kojto | 148:fd96258d940d | 665 | __set_ICIALLU(0); |
Kojto | 148:fd96258d940d | 666 | __DSB(); //ensure completion of the invalidation |
Kojto | 148:fd96258d940d | 667 | __ISB(); //ensure instruction fetch path sees new I cache state |
Kojto | 148:fd96258d940d | 668 | } |
Kojto | 148:fd96258d940d | 669 | |
Kojto | 148:fd96258d940d | 670 | /** \brief Clean D$ by MVA |
Kojto | 148:fd96258d940d | 671 | |
Kojto | 148:fd96258d940d | 672 | DCCMVAC. Data cache clean by MVA to PoC |
Kojto | 148:fd96258d940d | 673 | */ |
Kojto | 148:fd96258d940d | 674 | __STATIC_INLINE void L1C_CleanDCacheMVA(void *va) { |
Kojto | 148:fd96258d940d | 675 | __set_DCCMVAC((uint32_t)va); |
Kojto | 148:fd96258d940d | 676 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
Kojto | 148:fd96258d940d | 677 | } |
Kojto | 148:fd96258d940d | 678 | |
Kojto | 148:fd96258d940d | 679 | /** \brief Invalidate D$ by MVA |
Kojto | 148:fd96258d940d | 680 | |
Kojto | 148:fd96258d940d | 681 | DCIMVAC. Data cache invalidate by MVA to PoC |
Kojto | 148:fd96258d940d | 682 | */ |
Kojto | 148:fd96258d940d | 683 | __STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) { |
Kojto | 148:fd96258d940d | 684 | __set_DCIMVAC((uint32_t)va); |
Kojto | 148:fd96258d940d | 685 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
Kojto | 148:fd96258d940d | 686 | } |
Kojto | 148:fd96258d940d | 687 | |
Kojto | 148:fd96258d940d | 688 | /** \brief Clean and Invalidate D$ by MVA |
Kojto | 148:fd96258d940d | 689 | |
Kojto | 148:fd96258d940d | 690 | DCCIMVAC. Data cache clean and invalidate by MVA to PoC |
Kojto | 148:fd96258d940d | 691 | */ |
Kojto | 148:fd96258d940d | 692 | __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) { |
Kojto | 148:fd96258d940d | 693 | __set_DCCIMVAC((uint32_t)va); |
Kojto | 148:fd96258d940d | 694 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
Kojto | 148:fd96258d940d | 695 | } |
Kojto | 148:fd96258d940d | 696 | |
Kojto | 148:fd96258d940d | 697 | /** \brief Clean and Invalidate the entire data or unified cache |
Kojto | 148:fd96258d940d | 698 | |
Kojto | 148:fd96258d940d | 699 | Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. |
Kojto | 148:fd96258d940d | 700 | */ |
Kojto | 148:fd96258d940d | 701 | __STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) { |
Kojto | 148:fd96258d940d | 702 | __L1C_CleanInvalidateCache(op); // compiler specific call |
Kojto | 148:fd96258d940d | 703 | } |
Kojto | 148:fd96258d940d | 704 | |
Kojto | 148:fd96258d940d | 705 | |
Kojto | 148:fd96258d940d | 706 | /** \brief Invalidate the whole D$ |
Kojto | 148:fd96258d940d | 707 | |
Kojto | 148:fd96258d940d | 708 | DCISW. Invalidate by Set/Way |
Kojto | 148:fd96258d940d | 709 | */ |
Kojto | 148:fd96258d940d | 710 | |
Kojto | 148:fd96258d940d | 711 | __STATIC_INLINE void L1C_InvalidateDCacheAll(void) { |
Kojto | 148:fd96258d940d | 712 | L1C_CleanInvalidateCache(0); |
Kojto | 148:fd96258d940d | 713 | } |
Kojto | 148:fd96258d940d | 714 | |
Kojto | 148:fd96258d940d | 715 | /** \brief Clean the whole D$ |
Kojto | 148:fd96258d940d | 716 | |
Kojto | 148:fd96258d940d | 717 | DCCSW. Clean by Set/Way |
Kojto | 148:fd96258d940d | 718 | */ |
Kojto | 148:fd96258d940d | 719 | |
Kojto | 148:fd96258d940d | 720 | __STATIC_INLINE void L1C_CleanDCacheAll(void) { |
Kojto | 148:fd96258d940d | 721 | L1C_CleanInvalidateCache(1); |
Kojto | 148:fd96258d940d | 722 | } |
Kojto | 148:fd96258d940d | 723 | |
Kojto | 148:fd96258d940d | 724 | /** \brief Clean and invalidate the whole D$ |
Kojto | 148:fd96258d940d | 725 | |
Kojto | 148:fd96258d940d | 726 | DCCISW. Clean and Invalidate by Set/Way |
Kojto | 148:fd96258d940d | 727 | */ |
Kojto | 148:fd96258d940d | 728 | |
Kojto | 148:fd96258d940d | 729 | __STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) { |
Kojto | 148:fd96258d940d | 730 | L1C_CleanInvalidateCache(2); |
Kojto | 148:fd96258d940d | 731 | } |
Kojto | 148:fd96258d940d | 732 | |
Kojto | 148:fd96258d940d | 733 | |
Kojto | 148:fd96258d940d | 734 | /* ########################## L2 Cache functions ################################# */ |
Kojto | 148:fd96258d940d | 735 | #if (__L2C_PRESENT == 1U) |
Kojto | 148:fd96258d940d | 736 | //Cache Sync operation |
Kojto | 148:fd96258d940d | 737 | __STATIC_INLINE void L2C_Sync(void) |
Kojto | 148:fd96258d940d | 738 | { |
Kojto | 148:fd96258d940d | 739 | L2C_310->CACHE_SYNC = 0x0; |
Kojto | 148:fd96258d940d | 740 | } |
Kojto | 148:fd96258d940d | 741 | |
Kojto | 148:fd96258d940d | 742 | //return Cache controller cache ID |
Kojto | 148:fd96258d940d | 743 | __STATIC_INLINE int L2C_GetID (void) |
Kojto | 148:fd96258d940d | 744 | { |
Kojto | 148:fd96258d940d | 745 | return L2C_310->CACHE_ID; |
Kojto | 148:fd96258d940d | 746 | } |
Kojto | 148:fd96258d940d | 747 | |
Kojto | 148:fd96258d940d | 748 | //return Cache controller cache Type |
Kojto | 148:fd96258d940d | 749 | __STATIC_INLINE int L2C_GetType (void) |
Kojto | 148:fd96258d940d | 750 | { |
Kojto | 148:fd96258d940d | 751 | return L2C_310->CACHE_TYPE; |
Kojto | 148:fd96258d940d | 752 | } |
Kojto | 148:fd96258d940d | 753 | |
Kojto | 148:fd96258d940d | 754 | //Invalidate all cache by way |
Kojto | 148:fd96258d940d | 755 | __STATIC_INLINE void L2C_InvAllByWay (void) |
Kojto | 148:fd96258d940d | 756 | { |
Kojto | 148:fd96258d940d | 757 | unsigned int assoc; |
Kojto | 148:fd96258d940d | 758 | |
Kojto | 148:fd96258d940d | 759 | if (L2C_310->AUX_CNT & (1<<16)) |
Kojto | 148:fd96258d940d | 760 | assoc = 16; |
Kojto | 148:fd96258d940d | 761 | else |
Kojto | 148:fd96258d940d | 762 | assoc = 8; |
Kojto | 148:fd96258d940d | 763 | |
Kojto | 148:fd96258d940d | 764 | L2C_310->INV_WAY = (1 << assoc) - 1; |
Kojto | 148:fd96258d940d | 765 | while(L2C_310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate |
Kojto | 148:fd96258d940d | 766 | |
Kojto | 148:fd96258d940d | 767 | L2C_Sync(); |
Kojto | 148:fd96258d940d | 768 | } |
Kojto | 148:fd96258d940d | 769 | |
Kojto | 148:fd96258d940d | 770 | //Clean and Invalidate all cache by way |
Kojto | 148:fd96258d940d | 771 | __STATIC_INLINE void L2C_CleanInvAllByWay (void) |
Kojto | 148:fd96258d940d | 772 | { |
Kojto | 148:fd96258d940d | 773 | unsigned int assoc; |
Kojto | 148:fd96258d940d | 774 | |
Kojto | 148:fd96258d940d | 775 | if (L2C_310->AUX_CNT & (1<<16)) |
Kojto | 148:fd96258d940d | 776 | assoc = 16; |
Kojto | 148:fd96258d940d | 777 | else |
Kojto | 148:fd96258d940d | 778 | assoc = 8; |
Kojto | 148:fd96258d940d | 779 | |
Kojto | 148:fd96258d940d | 780 | L2C_310->CLEAN_INV_WAY = (1 << assoc) - 1; |
Kojto | 148:fd96258d940d | 781 | while(L2C_310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate |
Kojto | 148:fd96258d940d | 782 | |
Kojto | 148:fd96258d940d | 783 | L2C_Sync(); |
Kojto | 148:fd96258d940d | 784 | } |
Kojto | 148:fd96258d940d | 785 | |
Kojto | 148:fd96258d940d | 786 | //Enable Cache |
Kojto | 148:fd96258d940d | 787 | __STATIC_INLINE void L2C_Enable(void) |
Kojto | 148:fd96258d940d | 788 | { |
Kojto | 148:fd96258d940d | 789 | L2C_310->CONTROL = 0; |
Kojto | 148:fd96258d940d | 790 | L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; |
Kojto | 148:fd96258d940d | 791 | L2C_310->DEBUG_CONTROL = 0; |
Kojto | 148:fd96258d940d | 792 | L2C_310->DATA_LOCK_0_WAY = 0; |
Kojto | 148:fd96258d940d | 793 | L2C_310->CACHE_SYNC = 0; |
Kojto | 148:fd96258d940d | 794 | L2C_310->CONTROL = 0x01; |
Kojto | 148:fd96258d940d | 795 | L2C_Sync(); |
Kojto | 148:fd96258d940d | 796 | } |
Kojto | 148:fd96258d940d | 797 | //Disable Cache |
Kojto | 148:fd96258d940d | 798 | __STATIC_INLINE void L2C_Disable(void) |
Kojto | 148:fd96258d940d | 799 | { |
Kojto | 148:fd96258d940d | 800 | L2C_310->CONTROL = 0x00; |
Kojto | 148:fd96258d940d | 801 | L2C_Sync(); |
Kojto | 148:fd96258d940d | 802 | } |
Kojto | 148:fd96258d940d | 803 | |
Kojto | 148:fd96258d940d | 804 | //Invalidate cache by physical address |
Kojto | 148:fd96258d940d | 805 | __STATIC_INLINE void L2C_InvPa (void *pa) |
Kojto | 148:fd96258d940d | 806 | { |
Kojto | 148:fd96258d940d | 807 | L2C_310->INV_LINE_PA = (unsigned int)pa; |
Kojto | 148:fd96258d940d | 808 | L2C_Sync(); |
Kojto | 148:fd96258d940d | 809 | } |
Kojto | 148:fd96258d940d | 810 | |
Kojto | 148:fd96258d940d | 811 | //Clean cache by physical address |
Kojto | 148:fd96258d940d | 812 | __STATIC_INLINE void L2C_CleanPa (void *pa) |
Kojto | 148:fd96258d940d | 813 | { |
Kojto | 148:fd96258d940d | 814 | L2C_310->CLEAN_LINE_PA = (unsigned int)pa; |
Kojto | 148:fd96258d940d | 815 | L2C_Sync(); |
Kojto | 148:fd96258d940d | 816 | } |
Kojto | 148:fd96258d940d | 817 | |
Kojto | 148:fd96258d940d | 818 | //Clean and invalidate cache by physical address |
Kojto | 148:fd96258d940d | 819 | __STATIC_INLINE void L2C_CleanInvPa (void *pa) |
Kojto | 148:fd96258d940d | 820 | { |
Kojto | 148:fd96258d940d | 821 | L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; |
Kojto | 148:fd96258d940d | 822 | L2C_Sync(); |
Kojto | 148:fd96258d940d | 823 | } |
Kojto | 148:fd96258d940d | 824 | #endif |
Kojto | 148:fd96258d940d | 825 | |
Kojto | 148:fd96258d940d | 826 | /* ########################## GIC functions ###################################### */ |
Kojto | 148:fd96258d940d | 827 | #if (__GIC_PRESENT == 1U) |
Kojto | 148:fd96258d940d | 828 | |
Kojto | 148:fd96258d940d | 829 | __STATIC_INLINE void GIC_EnableDistributor(void) |
Kojto | 148:fd96258d940d | 830 | { |
Kojto | 148:fd96258d940d | 831 | GICDistributor->ICDDCR |= 1; //enable distributor |
Kojto | 148:fd96258d940d | 832 | } |
Kojto | 148:fd96258d940d | 833 | |
Kojto | 148:fd96258d940d | 834 | __STATIC_INLINE void GIC_DisableDistributor(void) |
Kojto | 148:fd96258d940d | 835 | { |
Kojto | 148:fd96258d940d | 836 | GICDistributor->ICDDCR &=~1; //disable distributor |
Kojto | 148:fd96258d940d | 837 | } |
Kojto | 148:fd96258d940d | 838 | |
Kojto | 148:fd96258d940d | 839 | __STATIC_INLINE uint32_t GIC_DistributorInfo(void) |
Kojto | 148:fd96258d940d | 840 | { |
Kojto | 148:fd96258d940d | 841 | return (uint32_t)(GICDistributor->ICDICTR); |
Kojto | 148:fd96258d940d | 842 | } |
Kojto | 148:fd96258d940d | 843 | |
Kojto | 148:fd96258d940d | 844 | __STATIC_INLINE uint32_t GIC_DistributorImplementer(void) |
Kojto | 148:fd96258d940d | 845 | { |
Kojto | 148:fd96258d940d | 846 | return (uint32_t)(GICDistributor->ICDIIDR); |
Kojto | 148:fd96258d940d | 847 | } |
Kojto | 148:fd96258d940d | 848 | |
Kojto | 148:fd96258d940d | 849 | __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) |
Kojto | 148:fd96258d940d | 850 | { |
Kojto | 148:fd96258d940d | 851 | char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]); |
Kojto | 148:fd96258d940d | 852 | field += IRQn % 4; |
Kojto | 148:fd96258d940d | 853 | *field = (char)cpu_target & 0xf; |
Kojto | 148:fd96258d940d | 854 | } |
Kojto | 148:fd96258d940d | 855 | |
Kojto | 148:fd96258d940d | 856 | __STATIC_INLINE void GIC_SetICDICFR (const uint32_t *ICDICFRn) |
Kojto | 148:fd96258d940d | 857 | { |
Kojto | 148:fd96258d940d | 858 | uint32_t i, num_irq; |
Kojto | 148:fd96258d940d | 859 | |
Kojto | 148:fd96258d940d | 860 | //Get the maximum number of interrupts that the GIC supports |
Kojto | 148:fd96258d940d | 861 | num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); |
Kojto | 148:fd96258d940d | 862 | |
Kojto | 148:fd96258d940d | 863 | for (i = 0; i < (num_irq/16); i++) |
Kojto | 148:fd96258d940d | 864 | { |
Kojto | 148:fd96258d940d | 865 | GICDistributor->ICDISPR[i] = *ICDICFRn++; |
Kojto | 148:fd96258d940d | 866 | } |
Kojto | 148:fd96258d940d | 867 | } |
Kojto | 148:fd96258d940d | 868 | |
Kojto | 148:fd96258d940d | 869 | __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) |
Kojto | 148:fd96258d940d | 870 | { |
Kojto | 148:fd96258d940d | 871 | char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]); |
Kojto | 148:fd96258d940d | 872 | field += IRQn % 4; |
Kojto | 148:fd96258d940d | 873 | return ((uint32_t)*field & 0xf); |
Kojto | 148:fd96258d940d | 874 | } |
Kojto | 148:fd96258d940d | 875 | |
Kojto | 148:fd96258d940d | 876 | __STATIC_INLINE void GIC_EnableInterface(void) |
Kojto | 148:fd96258d940d | 877 | { |
Kojto | 148:fd96258d940d | 878 | GICInterface->ICCICR |= 1; //enable interface |
Kojto | 148:fd96258d940d | 879 | } |
Kojto | 148:fd96258d940d | 880 | |
Kojto | 148:fd96258d940d | 881 | __STATIC_INLINE void GIC_DisableInterface(void) |
Kojto | 148:fd96258d940d | 882 | { |
Kojto | 148:fd96258d940d | 883 | GICInterface->ICCICR &=~1; //disable distributor |
Kojto | 148:fd96258d940d | 884 | } |
Kojto | 148:fd96258d940d | 885 | |
Kojto | 148:fd96258d940d | 886 | __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) |
Kojto | 148:fd96258d940d | 887 | { |
Kojto | 148:fd96258d940d | 888 | return (IRQn_Type)(GICInterface->ICCIAR); |
Kojto | 148:fd96258d940d | 889 | } |
Kojto | 148:fd96258d940d | 890 | |
Kojto | 148:fd96258d940d | 891 | __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) |
Kojto | 148:fd96258d940d | 892 | { |
Kojto | 148:fd96258d940d | 893 | GICInterface->ICCEOIR = IRQn; |
Kojto | 148:fd96258d940d | 894 | } |
Kojto | 148:fd96258d940d | 895 | |
Kojto | 148:fd96258d940d | 896 | __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) |
Kojto | 148:fd96258d940d | 897 | { |
Kojto | 148:fd96258d940d | 898 | GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32); |
Kojto | 148:fd96258d940d | 899 | } |
Kojto | 148:fd96258d940d | 900 | |
Kojto | 148:fd96258d940d | 901 | __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) |
Kojto | 148:fd96258d940d | 902 | { |
Kojto | 148:fd96258d940d | 903 | GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32); |
Kojto | 148:fd96258d940d | 904 | } |
Kojto | 148:fd96258d940d | 905 | |
Kojto | 148:fd96258d940d | 906 | __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) |
Kojto | 148:fd96258d940d | 907 | { |
Kojto | 148:fd96258d940d | 908 | GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32); |
Kojto | 148:fd96258d940d | 909 | } |
Kojto | 148:fd96258d940d | 910 | |
Kojto | 148:fd96258d940d | 911 | __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) |
Kojto | 148:fd96258d940d | 912 | { |
Kojto | 148:fd96258d940d | 913 | GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32); |
Kojto | 148:fd96258d940d | 914 | } |
Kojto | 148:fd96258d940d | 915 | |
Kojto | 148:fd96258d940d | 916 | __STATIC_INLINE void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model) |
Kojto | 148:fd96258d940d | 917 | { |
Kojto | 148:fd96258d940d | 918 | // Word-size read/writes must be used to access this register |
Kojto | 148:fd96258d940d | 919 | volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]); |
Kojto | 148:fd96258d940d | 920 | unsigned bit_shift = (IRQn % 16)<<1; |
Kojto | 148:fd96258d940d | 921 | unsigned int save_word; |
Kojto | 148:fd96258d940d | 922 | |
Kojto | 148:fd96258d940d | 923 | save_word = *field; |
Kojto | 148:fd96258d940d | 924 | save_word &= (~(3 << bit_shift)); |
Kojto | 148:fd96258d940d | 925 | |
Kojto | 148:fd96258d940d | 926 | *field = (save_word | (((edge_level<<1) | model) << bit_shift)); |
Kojto | 148:fd96258d940d | 927 | } |
Kojto | 148:fd96258d940d | 928 | |
Kojto | 148:fd96258d940d | 929 | __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
Kojto | 148:fd96258d940d | 930 | { |
Kojto | 148:fd96258d940d | 931 | char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]); |
Kojto | 148:fd96258d940d | 932 | field += IRQn % 4; |
Kojto | 148:fd96258d940d | 933 | *field = (char)priority; |
Kojto | 148:fd96258d940d | 934 | } |
Kojto | 148:fd96258d940d | 935 | |
Kojto | 148:fd96258d940d | 936 | __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) |
Kojto | 148:fd96258d940d | 937 | { |
Kojto | 148:fd96258d940d | 938 | char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]); |
Kojto | 148:fd96258d940d | 939 | field += IRQn % 4; |
Kojto | 148:fd96258d940d | 940 | return (uint32_t)*field; |
Kojto | 148:fd96258d940d | 941 | } |
Kojto | 148:fd96258d940d | 942 | |
Kojto | 148:fd96258d940d | 943 | __STATIC_INLINE void GIC_InterfacePriorityMask(uint32_t priority) |
Kojto | 148:fd96258d940d | 944 | { |
Kojto | 148:fd96258d940d | 945 | GICInterface->ICCPMR = priority & 0xff; //set priority mask |
Kojto | 148:fd96258d940d | 946 | } |
Kojto | 148:fd96258d940d | 947 | |
Kojto | 148:fd96258d940d | 948 | __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) |
Kojto | 148:fd96258d940d | 949 | { |
Kojto | 148:fd96258d940d | 950 | GICInterface->ICCBPR = binary_point & 0x07; //set binary point |
Kojto | 148:fd96258d940d | 951 | } |
Kojto | 148:fd96258d940d | 952 | |
Kojto | 148:fd96258d940d | 953 | __STATIC_INLINE uint32_t GIC_GetBinaryPoint(uint32_t binary_point) |
Kojto | 148:fd96258d940d | 954 | { |
Kojto | 148:fd96258d940d | 955 | return (uint32_t)GICInterface->ICCBPR; |
Kojto | 148:fd96258d940d | 956 | } |
Kojto | 148:fd96258d940d | 957 | |
Kojto | 148:fd96258d940d | 958 | __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) |
Kojto | 148:fd96258d940d | 959 | { |
Kojto | 148:fd96258d940d | 960 | uint32_t pending, active; |
Kojto | 148:fd96258d940d | 961 | |
Kojto | 148:fd96258d940d | 962 | active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1; |
Kojto | 148:fd96258d940d | 963 | pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1; |
Kojto | 148:fd96258d940d | 964 | |
Kojto | 148:fd96258d940d | 965 | return ((active<<1) | pending); |
Kojto | 148:fd96258d940d | 966 | } |
Kojto | 148:fd96258d940d | 967 | |
Kojto | 148:fd96258d940d | 968 | __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) |
Kojto | 148:fd96258d940d | 969 | { |
Kojto | 148:fd96258d940d | 970 | GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf); |
Kojto | 148:fd96258d940d | 971 | } |
Kojto | 148:fd96258d940d | 972 | |
Kojto | 148:fd96258d940d | 973 | __STATIC_INLINE void GIC_DistInit(void) |
Kojto | 148:fd96258d940d | 974 | { |
Kojto | 148:fd96258d940d | 975 | IRQn_Type i; |
Kojto | 148:fd96258d940d | 976 | uint32_t num_irq = 0; |
Kojto | 148:fd96258d940d | 977 | uint32_t priority_field; |
Kojto | 148:fd96258d940d | 978 | |
Kojto | 148:fd96258d940d | 979 | //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, |
Kojto | 148:fd96258d940d | 980 | //configuring all of the interrupts as Secure. |
Kojto | 148:fd96258d940d | 981 | |
Kojto | 148:fd96258d940d | 982 | //Disable interrupt forwarding |
Kojto | 148:fd96258d940d | 983 | GIC_DisableDistributor(); |
Kojto | 148:fd96258d940d | 984 | //Get the maximum number of interrupts that the GIC supports |
Kojto | 148:fd96258d940d | 985 | num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); |
Kojto | 148:fd96258d940d | 986 | |
Kojto | 148:fd96258d940d | 987 | /* Priority level is implementation defined. |
Kojto | 148:fd96258d940d | 988 | To determine the number of priority bits implemented write 0xFF to an ICDIPR |
Kojto | 148:fd96258d940d | 989 | priority field and read back the value stored.*/ |
Kojto | 148:fd96258d940d | 990 | GIC_SetPriority((IRQn_Type)0, 0xff); |
Kojto | 148:fd96258d940d | 991 | priority_field = GIC_GetPriority((IRQn_Type)0); |
Kojto | 148:fd96258d940d | 992 | |
Kojto | 148:fd96258d940d | 993 | for (i = (IRQn_Type)32; i < num_irq; i++) |
Kojto | 148:fd96258d940d | 994 | { |
Kojto | 148:fd96258d940d | 995 | //Disable the SPI interrupt |
Kojto | 148:fd96258d940d | 996 | GIC_DisableIRQ(i); |
Kojto | 148:fd96258d940d | 997 | //Set level-sensitive and 1-N model |
Kojto | 148:fd96258d940d | 998 | GIC_SetLevelModel(i, 0, 1); |
Kojto | 148:fd96258d940d | 999 | //Set priority |
Kojto | 148:fd96258d940d | 1000 | GIC_SetPriority(i, priority_field/2); |
Kojto | 148:fd96258d940d | 1001 | //Set target list to CPU0 |
Kojto | 148:fd96258d940d | 1002 | GIC_SetTarget(i, 1); |
Kojto | 148:fd96258d940d | 1003 | } |
Kojto | 148:fd96258d940d | 1004 | //Enable distributor |
Kojto | 148:fd96258d940d | 1005 | GIC_EnableDistributor(); |
Kojto | 148:fd96258d940d | 1006 | } |
Kojto | 148:fd96258d940d | 1007 | |
Kojto | 148:fd96258d940d | 1008 | __STATIC_INLINE void GIC_CPUInterfaceInit(void) |
Kojto | 148:fd96258d940d | 1009 | { |
Kojto | 148:fd96258d940d | 1010 | IRQn_Type i; |
Kojto | 148:fd96258d940d | 1011 | uint32_t priority_field; |
Kojto | 148:fd96258d940d | 1012 | |
Kojto | 148:fd96258d940d | 1013 | //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, |
Kojto | 148:fd96258d940d | 1014 | //configuring all of the interrupts as Secure. |
Kojto | 148:fd96258d940d | 1015 | |
Kojto | 148:fd96258d940d | 1016 | //Disable interrupt forwarding |
Kojto | 148:fd96258d940d | 1017 | GIC_DisableInterface(); |
Kojto | 148:fd96258d940d | 1018 | |
Kojto | 148:fd96258d940d | 1019 | /* Priority level is implementation defined. |
Kojto | 148:fd96258d940d | 1020 | To determine the number of priority bits implemented write 0xFF to an ICDIPR |
Kojto | 148:fd96258d940d | 1021 | priority field and read back the value stored.*/ |
Kojto | 148:fd96258d940d | 1022 | GIC_SetPriority((IRQn_Type)0, 0xff); |
Kojto | 148:fd96258d940d | 1023 | priority_field = GIC_GetPriority((IRQn_Type)0); |
Kojto | 148:fd96258d940d | 1024 | |
Kojto | 148:fd96258d940d | 1025 | //SGI and PPI |
Kojto | 148:fd96258d940d | 1026 | for (i = (IRQn_Type)0; i < 32; i++) |
Kojto | 148:fd96258d940d | 1027 | { |
Kojto | 148:fd96258d940d | 1028 | //Set level-sensitive and 1-N model for PPI |
Kojto | 148:fd96258d940d | 1029 | if(i > 15) |
Kojto | 148:fd96258d940d | 1030 | GIC_SetLevelModel(i, 0, 1); |
Kojto | 148:fd96258d940d | 1031 | //Disable SGI and PPI interrupts |
Kojto | 148:fd96258d940d | 1032 | GIC_DisableIRQ(i); |
Kojto | 148:fd96258d940d | 1033 | //Set priority |
Kojto | 148:fd96258d940d | 1034 | GIC_SetPriority(i, priority_field/2); |
Kojto | 148:fd96258d940d | 1035 | } |
Kojto | 148:fd96258d940d | 1036 | //Enable interface |
Kojto | 148:fd96258d940d | 1037 | GIC_EnableInterface(); |
Kojto | 148:fd96258d940d | 1038 | //Set binary point to 0 |
Kojto | 148:fd96258d940d | 1039 | GIC_SetBinaryPoint(0); |
Kojto | 148:fd96258d940d | 1040 | //Set priority mask |
Kojto | 148:fd96258d940d | 1041 | GIC_InterfacePriorityMask(0xff); |
Kojto | 148:fd96258d940d | 1042 | } |
Kojto | 148:fd96258d940d | 1043 | |
Kojto | 148:fd96258d940d | 1044 | __STATIC_INLINE void GIC_Enable(void) |
Kojto | 148:fd96258d940d | 1045 | { |
Kojto | 148:fd96258d940d | 1046 | GIC_DistInit(); |
Kojto | 148:fd96258d940d | 1047 | GIC_CPUInterfaceInit(); //per CPU |
Kojto | 148:fd96258d940d | 1048 | } |
Kojto | 148:fd96258d940d | 1049 | #endif |
Kojto | 148:fd96258d940d | 1050 | |
Kojto | 148:fd96258d940d | 1051 | /* ########################## Generic Timer functions ############################ */ |
Kojto | 148:fd96258d940d | 1052 | #if (__TIM_PRESENT == 1U) |
Kojto | 148:fd96258d940d | 1053 | |
Kojto | 148:fd96258d940d | 1054 | /* PL1 Physical Timer */ |
Kojto | 148:fd96258d940d | 1055 | #if (__CORTEX_A == 7U) |
Kojto | 148:fd96258d940d | 1056 | __STATIC_INLINE void PL1_SetLoadValue(uint32_t value) { |
Kojto | 148:fd96258d940d | 1057 | __set_CNTP_TVAL(value); |
Kojto | 148:fd96258d940d | 1058 | __ISB(); |
Kojto | 148:fd96258d940d | 1059 | } |
Kojto | 148:fd96258d940d | 1060 | |
Kojto | 148:fd96258d940d | 1061 | __STATIC_INLINE uint32_t PL1_GetCurrentValue() { |
Kojto | 148:fd96258d940d | 1062 | return(__get_CNTP_TVAL()); |
Kojto | 148:fd96258d940d | 1063 | } |
Kojto | 148:fd96258d940d | 1064 | |
Kojto | 148:fd96258d940d | 1065 | __STATIC_INLINE void PL1_SetControl(uint32_t value) { |
Kojto | 148:fd96258d940d | 1066 | __set_CNTP_CTL(value); |
Kojto | 148:fd96258d940d | 1067 | __ISB(); |
Kojto | 148:fd96258d940d | 1068 | } |
Kojto | 148:fd96258d940d | 1069 | |
Kojto | 148:fd96258d940d | 1070 | /* Private Timer */ |
Kojto | 148:fd96258d940d | 1071 | #elif ((__CORTEX_A == 5U)||(__CORTEX_A == 9U)) |
Kojto | 148:fd96258d940d | 1072 | __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) { |
Kojto | 148:fd96258d940d | 1073 | PTIM->LOAD = value; |
Kojto | 148:fd96258d940d | 1074 | } |
Kojto | 148:fd96258d940d | 1075 | |
Kojto | 148:fd96258d940d | 1076 | __STATIC_INLINE uint32_t PTIM_GetLoadValue() { |
Kojto | 148:fd96258d940d | 1077 | return(PTIM->LOAD); |
Kojto | 148:fd96258d940d | 1078 | } |
Kojto | 148:fd96258d940d | 1079 | |
Kojto | 148:fd96258d940d | 1080 | __STATIC_INLINE uint32_t PTIM_GetCurrentValue() { |
Kojto | 148:fd96258d940d | 1081 | return(PTIM->COUNTER); |
Kojto | 148:fd96258d940d | 1082 | } |
Kojto | 148:fd96258d940d | 1083 | |
Kojto | 148:fd96258d940d | 1084 | __STATIC_INLINE void PTIM_SetControl(uint32_t value) { |
Kojto | 148:fd96258d940d | 1085 | PTIM->CONTROL = value; |
Kojto | 148:fd96258d940d | 1086 | } |
Kojto | 148:fd96258d940d | 1087 | |
Kojto | 148:fd96258d940d | 1088 | __STATIC_INLINE uint32_t PTIM_GetControl(void) { |
Kojto | 148:fd96258d940d | 1089 | return(PTIM->CONTROL); |
Kojto | 148:fd96258d940d | 1090 | } |
Kojto | 148:fd96258d940d | 1091 | |
Kojto | 148:fd96258d940d | 1092 | __STATIC_INLINE void PTIM_ClearEventFlag(void) { |
Kojto | 148:fd96258d940d | 1093 | PTIM->ISR = 1; |
Kojto | 148:fd96258d940d | 1094 | } |
Kojto | 148:fd96258d940d | 1095 | #endif |
Kojto | 148:fd96258d940d | 1096 | #endif |
Kojto | 148:fd96258d940d | 1097 | |
Kojto | 148:fd96258d940d | 1098 | /* ########################## MMU functions ###################################### */ |
Kojto | 148:fd96258d940d | 1099 | |
Kojto | 148:fd96258d940d | 1100 | #define SECTION_DESCRIPTOR (0x2) |
Kojto | 148:fd96258d940d | 1101 | #define SECTION_MASK (0xFFFFFFFC) |
Kojto | 148:fd96258d940d | 1102 | |
Kojto | 148:fd96258d940d | 1103 | #define SECTION_TEXCB_MASK (0xFFFF8FF3) |
Kojto | 148:fd96258d940d | 1104 | #define SECTION_B_SHIFT (2) |
Kojto | 148:fd96258d940d | 1105 | #define SECTION_C_SHIFT (3) |
Kojto | 148:fd96258d940d | 1106 | #define SECTION_TEX0_SHIFT (12) |
Kojto | 148:fd96258d940d | 1107 | #define SECTION_TEX1_SHIFT (13) |
Kojto | 148:fd96258d940d | 1108 | #define SECTION_TEX2_SHIFT (14) |
Kojto | 148:fd96258d940d | 1109 | |
Kojto | 148:fd96258d940d | 1110 | #define SECTION_XN_MASK (0xFFFFFFEF) |
Kojto | 148:fd96258d940d | 1111 | #define SECTION_XN_SHIFT (4) |
Kojto | 148:fd96258d940d | 1112 | |
Kojto | 148:fd96258d940d | 1113 | #define SECTION_DOMAIN_MASK (0xFFFFFE1F) |
Kojto | 148:fd96258d940d | 1114 | #define SECTION_DOMAIN_SHIFT (5) |
Kojto | 148:fd96258d940d | 1115 | |
Kojto | 148:fd96258d940d | 1116 | #define SECTION_P_MASK (0xFFFFFDFF) |
Kojto | 148:fd96258d940d | 1117 | #define SECTION_P_SHIFT (9) |
Kojto | 148:fd96258d940d | 1118 | |
Kojto | 148:fd96258d940d | 1119 | #define SECTION_AP_MASK (0xFFFF73FF) |
Kojto | 148:fd96258d940d | 1120 | #define SECTION_AP_SHIFT (10) |
Kojto | 148:fd96258d940d | 1121 | #define SECTION_AP2_SHIFT (15) |
Kojto | 148:fd96258d940d | 1122 | |
Kojto | 148:fd96258d940d | 1123 | #define SECTION_S_MASK (0xFFFEFFFF) |
Kojto | 148:fd96258d940d | 1124 | #define SECTION_S_SHIFT (16) |
Kojto | 148:fd96258d940d | 1125 | |
Kojto | 148:fd96258d940d | 1126 | #define SECTION_NG_MASK (0xFFFDFFFF) |
Kojto | 148:fd96258d940d | 1127 | #define SECTION_NG_SHIFT (17) |
Kojto | 148:fd96258d940d | 1128 | |
Kojto | 148:fd96258d940d | 1129 | #define SECTION_NS_MASK (0xFFF7FFFF) |
Kojto | 148:fd96258d940d | 1130 | #define SECTION_NS_SHIFT (19) |
Kojto | 148:fd96258d940d | 1131 | |
Kojto | 148:fd96258d940d | 1132 | #define PAGE_L1_DESCRIPTOR (0x1) |
Kojto | 148:fd96258d940d | 1133 | #define PAGE_L1_MASK (0xFFFFFFFC) |
Kojto | 148:fd96258d940d | 1134 | |
Kojto | 148:fd96258d940d | 1135 | #define PAGE_L2_4K_DESC (0x2) |
Kojto | 148:fd96258d940d | 1136 | #define PAGE_L2_4K_MASK (0xFFFFFFFD) |
Kojto | 148:fd96258d940d | 1137 | |
Kojto | 148:fd96258d940d | 1138 | #define PAGE_L2_64K_DESC (0x1) |
Kojto | 148:fd96258d940d | 1139 | #define PAGE_L2_64K_MASK (0xFFFFFFFC) |
Kojto | 148:fd96258d940d | 1140 | |
Kojto | 148:fd96258d940d | 1141 | #define PAGE_4K_TEXCB_MASK (0xFFFFFE33) |
Kojto | 148:fd96258d940d | 1142 | #define PAGE_4K_B_SHIFT (2) |
Kojto | 148:fd96258d940d | 1143 | #define PAGE_4K_C_SHIFT (3) |
Kojto | 148:fd96258d940d | 1144 | #define PAGE_4K_TEX0_SHIFT (6) |
Kojto | 148:fd96258d940d | 1145 | #define PAGE_4K_TEX1_SHIFT (7) |
Kojto | 148:fd96258d940d | 1146 | #define PAGE_4K_TEX2_SHIFT (8) |
Kojto | 148:fd96258d940d | 1147 | |
Kojto | 148:fd96258d940d | 1148 | #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) |
Kojto | 148:fd96258d940d | 1149 | #define PAGE_64K_B_SHIFT (2) |
Kojto | 148:fd96258d940d | 1150 | #define PAGE_64K_C_SHIFT (3) |
Kojto | 148:fd96258d940d | 1151 | #define PAGE_64K_TEX0_SHIFT (12) |
Kojto | 148:fd96258d940d | 1152 | #define PAGE_64K_TEX1_SHIFT (13) |
Kojto | 148:fd96258d940d | 1153 | #define PAGE_64K_TEX2_SHIFT (14) |
Kojto | 148:fd96258d940d | 1154 | |
Kojto | 148:fd96258d940d | 1155 | #define PAGE_TEXCB_MASK (0xFFFF8FF3) |
Kojto | 148:fd96258d940d | 1156 | #define PAGE_B_SHIFT (2) |
Kojto | 148:fd96258d940d | 1157 | #define PAGE_C_SHIFT (3) |
Kojto | 148:fd96258d940d | 1158 | #define PAGE_TEX_SHIFT (12) |
Kojto | 148:fd96258d940d | 1159 | |
Kojto | 148:fd96258d940d | 1160 | #define PAGE_XN_4K_MASK (0xFFFFFFFE) |
Kojto | 148:fd96258d940d | 1161 | #define PAGE_XN_4K_SHIFT (0) |
Kojto | 148:fd96258d940d | 1162 | #define PAGE_XN_64K_MASK (0xFFFF7FFF) |
Kojto | 148:fd96258d940d | 1163 | #define PAGE_XN_64K_SHIFT (15) |
Kojto | 148:fd96258d940d | 1164 | |
Kojto | 148:fd96258d940d | 1165 | #define PAGE_DOMAIN_MASK (0xFFFFFE1F) |
Kojto | 148:fd96258d940d | 1166 | #define PAGE_DOMAIN_SHIFT (5) |
Kojto | 148:fd96258d940d | 1167 | |
Kojto | 148:fd96258d940d | 1168 | #define PAGE_P_MASK (0xFFFFFDFF) |
Kojto | 148:fd96258d940d | 1169 | #define PAGE_P_SHIFT (9) |
Kojto | 148:fd96258d940d | 1170 | |
Kojto | 148:fd96258d940d | 1171 | #define PAGE_AP_MASK (0xFFFFFDCF) |
Kojto | 148:fd96258d940d | 1172 | #define PAGE_AP_SHIFT (4) |
Kojto | 148:fd96258d940d | 1173 | #define PAGE_AP2_SHIFT (9) |
Kojto | 148:fd96258d940d | 1174 | |
Kojto | 148:fd96258d940d | 1175 | #define PAGE_S_MASK (0xFFFFFBFF) |
Kojto | 148:fd96258d940d | 1176 | #define PAGE_S_SHIFT (10) |
Kojto | 148:fd96258d940d | 1177 | |
Kojto | 148:fd96258d940d | 1178 | #define PAGE_NG_MASK (0xFFFFF7FF) |
Kojto | 148:fd96258d940d | 1179 | #define PAGE_NG_SHIFT (11) |
Kojto | 148:fd96258d940d | 1180 | |
Kojto | 148:fd96258d940d | 1181 | #define PAGE_NS_MASK (0xFFFFFFF7) |
Kojto | 148:fd96258d940d | 1182 | #define PAGE_NS_SHIFT (3) |
Kojto | 148:fd96258d940d | 1183 | |
Kojto | 148:fd96258d940d | 1184 | #define OFFSET_1M (0x00100000) |
Kojto | 148:fd96258d940d | 1185 | #define OFFSET_64K (0x00010000) |
Kojto | 148:fd96258d940d | 1186 | #define OFFSET_4K (0x00001000) |
Kojto | 148:fd96258d940d | 1187 | |
Kojto | 148:fd96258d940d | 1188 | #define DESCRIPTOR_FAULT (0x00000000) |
Kojto | 148:fd96258d940d | 1189 | |
Kojto | 148:fd96258d940d | 1190 | /* Attributes enumerations */ |
Kojto | 148:fd96258d940d | 1191 | |
Kojto | 148:fd96258d940d | 1192 | /* Region size attributes */ |
Kojto | 148:fd96258d940d | 1193 | typedef enum |
Kojto | 148:fd96258d940d | 1194 | { |
Kojto | 148:fd96258d940d | 1195 | SECTION, |
Kojto | 148:fd96258d940d | 1196 | PAGE_4k, |
Kojto | 148:fd96258d940d | 1197 | PAGE_64k, |
Kojto | 148:fd96258d940d | 1198 | } mmu_region_size_Type; |
Kojto | 148:fd96258d940d | 1199 | |
Kojto | 148:fd96258d940d | 1200 | /* Region type attributes */ |
Kojto | 148:fd96258d940d | 1201 | typedef enum |
Kojto | 148:fd96258d940d | 1202 | { |
Kojto | 148:fd96258d940d | 1203 | NORMAL, |
Kojto | 148:fd96258d940d | 1204 | DEVICE, |
Kojto | 148:fd96258d940d | 1205 | SHARED_DEVICE, |
Kojto | 148:fd96258d940d | 1206 | NON_SHARED_DEVICE, |
Kojto | 148:fd96258d940d | 1207 | STRONGLY_ORDERED |
Kojto | 148:fd96258d940d | 1208 | } mmu_memory_Type; |
Kojto | 148:fd96258d940d | 1209 | |
Kojto | 148:fd96258d940d | 1210 | /* Region cacheability attributes */ |
Kojto | 148:fd96258d940d | 1211 | typedef enum |
Kojto | 148:fd96258d940d | 1212 | { |
Kojto | 148:fd96258d940d | 1213 | NON_CACHEABLE, |
Kojto | 148:fd96258d940d | 1214 | WB_WA, |
Kojto | 148:fd96258d940d | 1215 | WT, |
Kojto | 148:fd96258d940d | 1216 | WB_NO_WA, |
Kojto | 148:fd96258d940d | 1217 | } mmu_cacheability_Type; |
Kojto | 148:fd96258d940d | 1218 | |
Kojto | 148:fd96258d940d | 1219 | /* Region parity check attributes */ |
Kojto | 148:fd96258d940d | 1220 | typedef enum |
Kojto | 148:fd96258d940d | 1221 | { |
Kojto | 148:fd96258d940d | 1222 | ECC_DISABLED, |
Kojto | 148:fd96258d940d | 1223 | ECC_ENABLED, |
Kojto | 148:fd96258d940d | 1224 | } mmu_ecc_check_Type; |
Kojto | 148:fd96258d940d | 1225 | |
Kojto | 148:fd96258d940d | 1226 | /* Region execution attributes */ |
Kojto | 148:fd96258d940d | 1227 | typedef enum |
Kojto | 148:fd96258d940d | 1228 | { |
Kojto | 148:fd96258d940d | 1229 | EXECUTE, |
Kojto | 148:fd96258d940d | 1230 | NON_EXECUTE, |
Kojto | 148:fd96258d940d | 1231 | } mmu_execute_Type; |
Kojto | 148:fd96258d940d | 1232 | |
Kojto | 148:fd96258d940d | 1233 | /* Region global attributes */ |
Kojto | 148:fd96258d940d | 1234 | typedef enum |
Kojto | 148:fd96258d940d | 1235 | { |
Kojto | 148:fd96258d940d | 1236 | GLOBAL, |
Kojto | 148:fd96258d940d | 1237 | NON_GLOBAL, |
Kojto | 148:fd96258d940d | 1238 | } mmu_global_Type; |
Kojto | 148:fd96258d940d | 1239 | |
Kojto | 148:fd96258d940d | 1240 | /* Region shareability attributes */ |
Kojto | 148:fd96258d940d | 1241 | typedef enum |
Kojto | 148:fd96258d940d | 1242 | { |
Kojto | 148:fd96258d940d | 1243 | NON_SHARED, |
Kojto | 148:fd96258d940d | 1244 | SHARED, |
Kojto | 148:fd96258d940d | 1245 | } mmu_shared_Type; |
Kojto | 148:fd96258d940d | 1246 | |
Kojto | 148:fd96258d940d | 1247 | /* Region security attributes */ |
Kojto | 148:fd96258d940d | 1248 | typedef enum |
Kojto | 148:fd96258d940d | 1249 | { |
Kojto | 148:fd96258d940d | 1250 | SECURE, |
Kojto | 148:fd96258d940d | 1251 | NON_SECURE, |
Kojto | 148:fd96258d940d | 1252 | } mmu_secure_Type; |
Kojto | 148:fd96258d940d | 1253 | |
Kojto | 148:fd96258d940d | 1254 | /* Region access attributes */ |
Kojto | 148:fd96258d940d | 1255 | typedef enum |
Kojto | 148:fd96258d940d | 1256 | { |
Kojto | 148:fd96258d940d | 1257 | NO_ACCESS, |
Kojto | 148:fd96258d940d | 1258 | RW, |
Kojto | 148:fd96258d940d | 1259 | READ, |
Kojto | 148:fd96258d940d | 1260 | } mmu_access_Type; |
Kojto | 148:fd96258d940d | 1261 | |
Kojto | 148:fd96258d940d | 1262 | /* Memory Region definition */ |
Kojto | 148:fd96258d940d | 1263 | typedef struct RegionStruct { |
Kojto | 148:fd96258d940d | 1264 | mmu_region_size_Type rg_t; |
Kojto | 148:fd96258d940d | 1265 | mmu_memory_Type mem_t; |
Kojto | 148:fd96258d940d | 1266 | uint8_t domain; |
Kojto | 148:fd96258d940d | 1267 | mmu_cacheability_Type inner_norm_t; |
Kojto | 148:fd96258d940d | 1268 | mmu_cacheability_Type outer_norm_t; |
Kojto | 148:fd96258d940d | 1269 | mmu_ecc_check_Type e_t; |
Kojto | 148:fd96258d940d | 1270 | mmu_execute_Type xn_t; |
Kojto | 148:fd96258d940d | 1271 | mmu_global_Type g_t; |
Kojto | 148:fd96258d940d | 1272 | mmu_secure_Type sec_t; |
Kojto | 148:fd96258d940d | 1273 | mmu_access_Type priv_t; |
Kojto | 148:fd96258d940d | 1274 | mmu_access_Type user_t; |
Kojto | 148:fd96258d940d | 1275 | mmu_shared_Type sh_t; |
Kojto | 148:fd96258d940d | 1276 | |
Kojto | 148:fd96258d940d | 1277 | } mmu_region_attributes_Type; |
Kojto | 148:fd96258d940d | 1278 | |
Kojto | 148:fd96258d940d | 1279 | //Following macros define the descriptors and attributes |
Kojto | 148:fd96258d940d | 1280 | //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 |
Kojto | 148:fd96258d940d | 1281 | #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ |
Kojto | 148:fd96258d940d | 1282 | region.domain = 0x0; \ |
Kojto | 148:fd96258d940d | 1283 | region.e_t = ECC_DISABLED; \ |
Kojto | 148:fd96258d940d | 1284 | region.g_t = GLOBAL; \ |
Kojto | 148:fd96258d940d | 1285 | region.inner_norm_t = WB_WA; \ |
Kojto | 148:fd96258d940d | 1286 | region.outer_norm_t = WB_WA; \ |
Kojto | 148:fd96258d940d | 1287 | region.mem_t = NORMAL; \ |
Kojto | 148:fd96258d940d | 1288 | region.sec_t = SECURE; \ |
Kojto | 148:fd96258d940d | 1289 | region.xn_t = EXECUTE; \ |
Kojto | 148:fd96258d940d | 1290 | region.priv_t = RW; \ |
Kojto | 148:fd96258d940d | 1291 | region.user_t = RW; \ |
Kojto | 148:fd96258d940d | 1292 | region.sh_t = NON_SHARED; \ |
Kojto | 148:fd96258d940d | 1293 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
Kojto | 148:fd96258d940d | 1294 | |
Kojto | 148:fd96258d940d | 1295 | //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 |
Kojto | 148:fd96258d940d | 1296 | #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ |
Kojto | 148:fd96258d940d | 1297 | region.domain = 0x0; \ |
Kojto | 148:fd96258d940d | 1298 | region.e_t = ECC_DISABLED; \ |
Kojto | 148:fd96258d940d | 1299 | region.g_t = GLOBAL; \ |
Kojto | 148:fd96258d940d | 1300 | region.inner_norm_t = WB_WA; \ |
Kojto | 148:fd96258d940d | 1301 | region.outer_norm_t = WB_WA; \ |
Kojto | 148:fd96258d940d | 1302 | region.mem_t = NORMAL; \ |
Kojto | 148:fd96258d940d | 1303 | region.sec_t = SECURE; \ |
Kojto | 148:fd96258d940d | 1304 | region.xn_t = EXECUTE; \ |
Kojto | 148:fd96258d940d | 1305 | region.priv_t = READ; \ |
Kojto | 148:fd96258d940d | 1306 | region.user_t = READ; \ |
Kojto | 148:fd96258d940d | 1307 | region.sh_t = NON_SHARED; \ |
Kojto | 148:fd96258d940d | 1308 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
Kojto | 148:fd96258d940d | 1309 | |
Kojto | 148:fd96258d940d | 1310 | //Sect_Normal_RO. Sect_Normal_Cod, but not executable |
Kojto | 148:fd96258d940d | 1311 | #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ |
Kojto | 148:fd96258d940d | 1312 | region.domain = 0x0; \ |
Kojto | 148:fd96258d940d | 1313 | region.e_t = ECC_DISABLED; \ |
Kojto | 148:fd96258d940d | 1314 | region.g_t = GLOBAL; \ |
Kojto | 148:fd96258d940d | 1315 | region.inner_norm_t = WB_WA; \ |
Kojto | 148:fd96258d940d | 1316 | region.outer_norm_t = WB_WA; \ |
Kojto | 148:fd96258d940d | 1317 | region.mem_t = NORMAL; \ |
Kojto | 148:fd96258d940d | 1318 | region.sec_t = SECURE; \ |
Kojto | 148:fd96258d940d | 1319 | region.xn_t = NON_EXECUTE; \ |
Kojto | 148:fd96258d940d | 1320 | region.priv_t = READ; \ |
Kojto | 148:fd96258d940d | 1321 | region.user_t = READ; \ |
Kojto | 148:fd96258d940d | 1322 | region.sh_t = NON_SHARED; \ |
Kojto | 148:fd96258d940d | 1323 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
Kojto | 148:fd96258d940d | 1324 | |
Kojto | 148:fd96258d940d | 1325 | //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable |
Kojto | 148:fd96258d940d | 1326 | #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ |
Kojto | 148:fd96258d940d | 1327 | region.domain = 0x0; \ |
Kojto | 148:fd96258d940d | 1328 | region.e_t = ECC_DISABLED; \ |
Kojto | 148:fd96258d940d | 1329 | region.g_t = GLOBAL; \ |
Kojto | 148:fd96258d940d | 1330 | region.inner_norm_t = WB_WA; \ |
Kojto | 148:fd96258d940d | 1331 | region.outer_norm_t = WB_WA; \ |
Kojto | 148:fd96258d940d | 1332 | region.mem_t = NORMAL; \ |
Kojto | 148:fd96258d940d | 1333 | region.sec_t = SECURE; \ |
Kojto | 148:fd96258d940d | 1334 | region.xn_t = NON_EXECUTE; \ |
Kojto | 148:fd96258d940d | 1335 | region.priv_t = RW; \ |
Kojto | 148:fd96258d940d | 1336 | region.user_t = RW; \ |
Kojto | 148:fd96258d940d | 1337 | region.sh_t = NON_SHARED; \ |
Kojto | 148:fd96258d940d | 1338 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
Kojto | 148:fd96258d940d | 1339 | //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 |
Kojto | 148:fd96258d940d | 1340 | #define section_so(descriptor_l1, region) region.rg_t = SECTION; \ |
Kojto | 148:fd96258d940d | 1341 | region.domain = 0x0; \ |
Kojto | 148:fd96258d940d | 1342 | region.e_t = ECC_DISABLED; \ |
Kojto | 148:fd96258d940d | 1343 | region.g_t = GLOBAL; \ |
Kojto | 148:fd96258d940d | 1344 | region.inner_norm_t = NON_CACHEABLE; \ |
Kojto | 148:fd96258d940d | 1345 | region.outer_norm_t = NON_CACHEABLE; \ |
Kojto | 148:fd96258d940d | 1346 | region.mem_t = STRONGLY_ORDERED; \ |
Kojto | 148:fd96258d940d | 1347 | region.sec_t = SECURE; \ |
Kojto | 148:fd96258d940d | 1348 | region.xn_t = NON_EXECUTE; \ |
Kojto | 148:fd96258d940d | 1349 | region.priv_t = RW; \ |
Kojto | 148:fd96258d940d | 1350 | region.user_t = RW; \ |
Kojto | 148:fd96258d940d | 1351 | region.sh_t = NON_SHARED; \ |
Kojto | 148:fd96258d940d | 1352 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
Kojto | 148:fd96258d940d | 1353 | |
Kojto | 148:fd96258d940d | 1354 | //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 |
Kojto | 148:fd96258d940d | 1355 | #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ |
Kojto | 148:fd96258d940d | 1356 | region.domain = 0x0; \ |
Kojto | 148:fd96258d940d | 1357 | region.e_t = ECC_DISABLED; \ |
Kojto | 148:fd96258d940d | 1358 | region.g_t = GLOBAL; \ |
Kojto | 148:fd96258d940d | 1359 | region.inner_norm_t = NON_CACHEABLE; \ |
Kojto | 148:fd96258d940d | 1360 | region.outer_norm_t = NON_CACHEABLE; \ |
Kojto | 148:fd96258d940d | 1361 | region.mem_t = STRONGLY_ORDERED; \ |
Kojto | 148:fd96258d940d | 1362 | region.sec_t = SECURE; \ |
Kojto | 148:fd96258d940d | 1363 | region.xn_t = NON_EXECUTE; \ |
Kojto | 148:fd96258d940d | 1364 | region.priv_t = READ; \ |
Kojto | 148:fd96258d940d | 1365 | region.user_t = READ; \ |
Kojto | 148:fd96258d940d | 1366 | region.sh_t = NON_SHARED; \ |
Kojto | 148:fd96258d940d | 1367 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
Kojto | 148:fd96258d940d | 1368 | |
Kojto | 148:fd96258d940d | 1369 | //Sect_Device_RW. Sect_Device_RO, but writeable |
Kojto | 148:fd96258d940d | 1370 | #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ |
Kojto | 148:fd96258d940d | 1371 | region.domain = 0x0; \ |
Kojto | 148:fd96258d940d | 1372 | region.e_t = ECC_DISABLED; \ |
Kojto | 148:fd96258d940d | 1373 | region.g_t = GLOBAL; \ |
Kojto | 148:fd96258d940d | 1374 | region.inner_norm_t = NON_CACHEABLE; \ |
Kojto | 148:fd96258d940d | 1375 | region.outer_norm_t = NON_CACHEABLE; \ |
Kojto | 148:fd96258d940d | 1376 | region.mem_t = STRONGLY_ORDERED; \ |
Kojto | 148:fd96258d940d | 1377 | region.sec_t = SECURE; \ |
Kojto | 148:fd96258d940d | 1378 | region.xn_t = NON_EXECUTE; \ |
Kojto | 148:fd96258d940d | 1379 | region.priv_t = RW; \ |
Kojto | 148:fd96258d940d | 1380 | region.user_t = RW; \ |
Kojto | 148:fd96258d940d | 1381 | region.sh_t = NON_SHARED; \ |
Kojto | 148:fd96258d940d | 1382 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
Kojto | 148:fd96258d940d | 1383 | //Page_4k_Device_RW. Shared device, not executable, rw, domain 0 |
Kojto | 148:fd96258d940d | 1384 | #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ |
Kojto | 148:fd96258d940d | 1385 | region.domain = 0x0; \ |
Kojto | 148:fd96258d940d | 1386 | region.e_t = ECC_DISABLED; \ |
Kojto | 148:fd96258d940d | 1387 | region.g_t = GLOBAL; \ |
Kojto | 148:fd96258d940d | 1388 | region.inner_norm_t = NON_CACHEABLE; \ |
Kojto | 148:fd96258d940d | 1389 | region.outer_norm_t = NON_CACHEABLE; \ |
Kojto | 148:fd96258d940d | 1390 | region.mem_t = SHARED_DEVICE; \ |
Kojto | 148:fd96258d940d | 1391 | region.sec_t = SECURE; \ |
Kojto | 148:fd96258d940d | 1392 | region.xn_t = NON_EXECUTE; \ |
Kojto | 148:fd96258d940d | 1393 | region.priv_t = RW; \ |
Kojto | 148:fd96258d940d | 1394 | region.user_t = RW; \ |
Kojto | 148:fd96258d940d | 1395 | region.sh_t = NON_SHARED; \ |
Kojto | 148:fd96258d940d | 1396 | MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); |
Kojto | 148:fd96258d940d | 1397 | |
Kojto | 148:fd96258d940d | 1398 | //Page_64k_Device_RW. Shared device, not executable, rw, domain 0 |
Kojto | 148:fd96258d940d | 1399 | #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ |
Kojto | 148:fd96258d940d | 1400 | region.domain = 0x0; \ |
Kojto | 148:fd96258d940d | 1401 | region.e_t = ECC_DISABLED; \ |
Kojto | 148:fd96258d940d | 1402 | region.g_t = GLOBAL; \ |
Kojto | 148:fd96258d940d | 1403 | region.inner_norm_t = NON_CACHEABLE; \ |
Kojto | 148:fd96258d940d | 1404 | region.outer_norm_t = NON_CACHEABLE; \ |
Kojto | 148:fd96258d940d | 1405 | region.mem_t = SHARED_DEVICE; \ |
Kojto | 148:fd96258d940d | 1406 | region.sec_t = SECURE; \ |
Kojto | 148:fd96258d940d | 1407 | region.xn_t = NON_EXECUTE; \ |
Kojto | 148:fd96258d940d | 1408 | region.priv_t = RW; \ |
Kojto | 148:fd96258d940d | 1409 | region.user_t = RW; \ |
Kojto | 148:fd96258d940d | 1410 | region.sh_t = NON_SHARED; \ |
Kojto | 148:fd96258d940d | 1411 | MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); |
Kojto | 148:fd96258d940d | 1412 | |
Kojto | 148:fd96258d940d | 1413 | /** \brief Set section execution-never attribute |
Kojto | 148:fd96258d940d | 1414 | |
Kojto | 148:fd96258d940d | 1415 | \param [out] descriptor_l1 L1 descriptor. |
Kojto | 148:fd96258d940d | 1416 | \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. |
Kojto | 148:fd96258d940d | 1417 | |
Kojto | 148:fd96258d940d | 1418 | \return 0 |
Kojto | 148:fd96258d940d | 1419 | */ |
Kojto | 148:fd96258d940d | 1420 | __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) |
Kojto | 148:fd96258d940d | 1421 | { |
Kojto | 148:fd96258d940d | 1422 | *descriptor_l1 &= SECTION_XN_MASK; |
Kojto | 148:fd96258d940d | 1423 | *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); |
Kojto | 148:fd96258d940d | 1424 | return 0; |
Kojto | 148:fd96258d940d | 1425 | } |
Kojto | 148:fd96258d940d | 1426 | |
Kojto | 148:fd96258d940d | 1427 | /** \brief Set section domain |
Kojto | 148:fd96258d940d | 1428 | |
Kojto | 148:fd96258d940d | 1429 | \param [out] descriptor_l1 L1 descriptor. |
Kojto | 148:fd96258d940d | 1430 | \param [in] domain Section domain |
Kojto | 148:fd96258d940d | 1431 | |
Kojto | 148:fd96258d940d | 1432 | \return 0 |
Kojto | 148:fd96258d940d | 1433 | */ |
Kojto | 148:fd96258d940d | 1434 | __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) |
Kojto | 148:fd96258d940d | 1435 | { |
Kojto | 148:fd96258d940d | 1436 | *descriptor_l1 &= SECTION_DOMAIN_MASK; |
Kojto | 148:fd96258d940d | 1437 | *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); |
Kojto | 148:fd96258d940d | 1438 | return 0; |
Kojto | 148:fd96258d940d | 1439 | } |
Kojto | 148:fd96258d940d | 1440 | |
Kojto | 148:fd96258d940d | 1441 | /** \brief Set section parity check |
Kojto | 148:fd96258d940d | 1442 | |
Kojto | 148:fd96258d940d | 1443 | \param [out] descriptor_l1 L1 descriptor. |
Kojto | 148:fd96258d940d | 1444 | \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED |
Kojto | 148:fd96258d940d | 1445 | |
Kojto | 148:fd96258d940d | 1446 | \return 0 |
Kojto | 148:fd96258d940d | 1447 | */ |
Kojto | 148:fd96258d940d | 1448 | __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) |
Kojto | 148:fd96258d940d | 1449 | { |
Kojto | 148:fd96258d940d | 1450 | *descriptor_l1 &= SECTION_P_MASK; |
Kojto | 148:fd96258d940d | 1451 | *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); |
Kojto | 148:fd96258d940d | 1452 | return 0; |
Kojto | 148:fd96258d940d | 1453 | } |
Kojto | 148:fd96258d940d | 1454 | |
Kojto | 148:fd96258d940d | 1455 | /** \brief Set section access privileges |
Kojto | 148:fd96258d940d | 1456 | |
Kojto | 148:fd96258d940d | 1457 | \param [out] descriptor_l1 L1 descriptor. |
Kojto | 148:fd96258d940d | 1458 | \param [in] user User Level Access: NO_ACCESS, RW, READ |
Kojto | 148:fd96258d940d | 1459 | \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ |
Kojto | 148:fd96258d940d | 1460 | \param [in] afe Access flag enable |
Kojto | 148:fd96258d940d | 1461 | |
Kojto | 148:fd96258d940d | 1462 | \return 0 |
Kojto | 148:fd96258d940d | 1463 | */ |
Kojto | 148:fd96258d940d | 1464 | __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) |
Kojto | 148:fd96258d940d | 1465 | { |
Kojto | 148:fd96258d940d | 1466 | uint32_t ap = 0; |
Kojto | 148:fd96258d940d | 1467 | |
Kojto | 148:fd96258d940d | 1468 | if (afe == 0) { //full access |
Kojto | 148:fd96258d940d | 1469 | if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } |
Kojto | 148:fd96258d940d | 1470 | else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } |
Kojto | 148:fd96258d940d | 1471 | else if ((priv == RW) && (user == READ)) { ap = 0x2; } |
Kojto | 148:fd96258d940d | 1472 | else if ((priv == RW) && (user == RW)) { ap = 0x3; } |
Kojto | 148:fd96258d940d | 1473 | else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } |
Kojto | 148:fd96258d940d | 1474 | else if ((priv == READ) && (user == READ)) { ap = 0x7; } |
Kojto | 148:fd96258d940d | 1475 | } |
Kojto | 148:fd96258d940d | 1476 | |
Kojto | 148:fd96258d940d | 1477 | else { //Simplified access |
Kojto | 148:fd96258d940d | 1478 | if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } |
Kojto | 148:fd96258d940d | 1479 | else if ((priv == RW) && (user == RW)) { ap = 0x3; } |
Kojto | 148:fd96258d940d | 1480 | else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } |
Kojto | 148:fd96258d940d | 1481 | else if ((priv == READ) && (user == READ)) { ap = 0x7; } |
Kojto | 148:fd96258d940d | 1482 | } |
Kojto | 148:fd96258d940d | 1483 | |
Kojto | 148:fd96258d940d | 1484 | *descriptor_l1 &= SECTION_AP_MASK; |
Kojto | 148:fd96258d940d | 1485 | *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; |
Kojto | 148:fd96258d940d | 1486 | *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; |
Kojto | 148:fd96258d940d | 1487 | |
Kojto | 148:fd96258d940d | 1488 | return 0; |
Kojto | 148:fd96258d940d | 1489 | } |
Kojto | 148:fd96258d940d | 1490 | |
Kojto | 148:fd96258d940d | 1491 | /** \brief Set section shareability |
Kojto | 148:fd96258d940d | 1492 | |
Kojto | 148:fd96258d940d | 1493 | \param [out] descriptor_l1 L1 descriptor. |
Kojto | 148:fd96258d940d | 1494 | \param [in] s_bit Section shareability: NON_SHARED, SHARED |
Kojto | 148:fd96258d940d | 1495 | |
Kojto | 148:fd96258d940d | 1496 | \return 0 |
Kojto | 148:fd96258d940d | 1497 | */ |
Kojto | 148:fd96258d940d | 1498 | __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) |
Kojto | 148:fd96258d940d | 1499 | { |
Kojto | 148:fd96258d940d | 1500 | *descriptor_l1 &= SECTION_S_MASK; |
Kojto | 148:fd96258d940d | 1501 | *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); |
Kojto | 148:fd96258d940d | 1502 | return 0; |
Kojto | 148:fd96258d940d | 1503 | } |
Kojto | 148:fd96258d940d | 1504 | |
Kojto | 148:fd96258d940d | 1505 | /** \brief Set section Global attribute |
Kojto | 148:fd96258d940d | 1506 | |
Kojto | 148:fd96258d940d | 1507 | \param [out] descriptor_l1 L1 descriptor. |
Kojto | 148:fd96258d940d | 1508 | \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL |
Kojto | 148:fd96258d940d | 1509 | |
Kojto | 148:fd96258d940d | 1510 | \return 0 |
Kojto | 148:fd96258d940d | 1511 | */ |
Kojto | 148:fd96258d940d | 1512 | __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) |
Kojto | 148:fd96258d940d | 1513 | { |
Kojto | 148:fd96258d940d | 1514 | *descriptor_l1 &= SECTION_NG_MASK; |
Kojto | 148:fd96258d940d | 1515 | *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); |
Kojto | 148:fd96258d940d | 1516 | return 0; |
Kojto | 148:fd96258d940d | 1517 | } |
Kojto | 148:fd96258d940d | 1518 | |
Kojto | 148:fd96258d940d | 1519 | /** \brief Set section Security attribute |
Kojto | 148:fd96258d940d | 1520 | |
Kojto | 148:fd96258d940d | 1521 | \param [out] descriptor_l1 L1 descriptor. |
Kojto | 148:fd96258d940d | 1522 | \param [in] s_bit Section Security attribute: SECURE, NON_SECURE |
Kojto | 148:fd96258d940d | 1523 | |
Kojto | 148:fd96258d940d | 1524 | \return 0 |
Kojto | 148:fd96258d940d | 1525 | */ |
Kojto | 148:fd96258d940d | 1526 | __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) |
Kojto | 148:fd96258d940d | 1527 | { |
Kojto | 148:fd96258d940d | 1528 | *descriptor_l1 &= SECTION_NS_MASK; |
Kojto | 148:fd96258d940d | 1529 | *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); |
Kojto | 148:fd96258d940d | 1530 | return 0; |
Kojto | 148:fd96258d940d | 1531 | } |
Kojto | 148:fd96258d940d | 1532 | |
Kojto | 148:fd96258d940d | 1533 | /* Page 4k or 64k */ |
Kojto | 148:fd96258d940d | 1534 | /** \brief Set 4k/64k page execution-never attribute |
Kojto | 148:fd96258d940d | 1535 | |
Kojto | 148:fd96258d940d | 1536 | \param [out] descriptor_l2 L2 descriptor. |
Kojto | 148:fd96258d940d | 1537 | \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. |
Kojto | 148:fd96258d940d | 1538 | \param [in] page Page size: PAGE_4k, PAGE_64k, |
Kojto | 148:fd96258d940d | 1539 | |
Kojto | 148:fd96258d940d | 1540 | \return 0 |
Kojto | 148:fd96258d940d | 1541 | */ |
Kojto | 148:fd96258d940d | 1542 | __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) |
Kojto | 148:fd96258d940d | 1543 | { |
Kojto | 148:fd96258d940d | 1544 | if (page == PAGE_4k) |
Kojto | 148:fd96258d940d | 1545 | { |
Kojto | 148:fd96258d940d | 1546 | *descriptor_l2 &= PAGE_XN_4K_MASK; |
Kojto | 148:fd96258d940d | 1547 | *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); |
Kojto | 148:fd96258d940d | 1548 | } |
Kojto | 148:fd96258d940d | 1549 | else |
Kojto | 148:fd96258d940d | 1550 | { |
Kojto | 148:fd96258d940d | 1551 | *descriptor_l2 &= PAGE_XN_64K_MASK; |
Kojto | 148:fd96258d940d | 1552 | *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); |
Kojto | 148:fd96258d940d | 1553 | } |
Kojto | 148:fd96258d940d | 1554 | return 0; |
Kojto | 148:fd96258d940d | 1555 | } |
Kojto | 148:fd96258d940d | 1556 | |
Kojto | 148:fd96258d940d | 1557 | /** \brief Set 4k/64k page domain |
Kojto | 148:fd96258d940d | 1558 | |
Kojto | 148:fd96258d940d | 1559 | \param [out] descriptor_l1 L1 descriptor. |
Kojto | 148:fd96258d940d | 1560 | \param [in] domain Page domain |
Kojto | 148:fd96258d940d | 1561 | |
Kojto | 148:fd96258d940d | 1562 | \return 0 |
Kojto | 148:fd96258d940d | 1563 | */ |
Kojto | 148:fd96258d940d | 1564 | __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) |
Kojto | 148:fd96258d940d | 1565 | { |
Kojto | 148:fd96258d940d | 1566 | *descriptor_l1 &= PAGE_DOMAIN_MASK; |
Kojto | 148:fd96258d940d | 1567 | *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); |
Kojto | 148:fd96258d940d | 1568 | return 0; |
Kojto | 148:fd96258d940d | 1569 | } |
Kojto | 148:fd96258d940d | 1570 | |
Kojto | 148:fd96258d940d | 1571 | /** \brief Set 4k/64k page parity check |
Kojto | 148:fd96258d940d | 1572 | |
Kojto | 148:fd96258d940d | 1573 | \param [out] descriptor_l1 L1 descriptor. |
Kojto | 148:fd96258d940d | 1574 | \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED |
Kojto | 148:fd96258d940d | 1575 | |
Kojto | 148:fd96258d940d | 1576 | \return 0 |
Kojto | 148:fd96258d940d | 1577 | */ |
Kojto | 148:fd96258d940d | 1578 | __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) |
Kojto | 148:fd96258d940d | 1579 | { |
Kojto | 148:fd96258d940d | 1580 | *descriptor_l1 &= SECTION_P_MASK; |
Kojto | 148:fd96258d940d | 1581 | *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); |
Kojto | 148:fd96258d940d | 1582 | return 0; |
Kojto | 148:fd96258d940d | 1583 | } |
Kojto | 148:fd96258d940d | 1584 | |
Kojto | 148:fd96258d940d | 1585 | /** \brief Set 4k/64k page access privileges |
Kojto | 148:fd96258d940d | 1586 | |
Kojto | 148:fd96258d940d | 1587 | \param [out] descriptor_l2 L2 descriptor. |
Kojto | 148:fd96258d940d | 1588 | \param [in] user User Level Access: NO_ACCESS, RW, READ |
Kojto | 148:fd96258d940d | 1589 | \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ |
Kojto | 148:fd96258d940d | 1590 | \param [in] afe Access flag enable |
Kojto | 148:fd96258d940d | 1591 | |
Kojto | 148:fd96258d940d | 1592 | \return 0 |
Kojto | 148:fd96258d940d | 1593 | */ |
Kojto | 148:fd96258d940d | 1594 | __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) |
Kojto | 148:fd96258d940d | 1595 | { |
Kojto | 148:fd96258d940d | 1596 | uint32_t ap = 0; |
Kojto | 148:fd96258d940d | 1597 | |
Kojto | 148:fd96258d940d | 1598 | if (afe == 0) { //full access |
Kojto | 148:fd96258d940d | 1599 | if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } |
Kojto | 148:fd96258d940d | 1600 | else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } |
Kojto | 148:fd96258d940d | 1601 | else if ((priv == RW) && (user == READ)) { ap = 0x2; } |
Kojto | 148:fd96258d940d | 1602 | else if ((priv == RW) && (user == RW)) { ap = 0x3; } |
Kojto | 148:fd96258d940d | 1603 | else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } |
Kojto | 148:fd96258d940d | 1604 | else if ((priv == READ) && (user == READ)) { ap = 0x6; } |
Kojto | 148:fd96258d940d | 1605 | } |
Kojto | 148:fd96258d940d | 1606 | |
Kojto | 148:fd96258d940d | 1607 | else { //Simplified access |
Kojto | 148:fd96258d940d | 1608 | if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } |
Kojto | 148:fd96258d940d | 1609 | else if ((priv == RW) && (user == RW)) { ap = 0x3; } |
Kojto | 148:fd96258d940d | 1610 | else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } |
Kojto | 148:fd96258d940d | 1611 | else if ((priv == READ) && (user == READ)) { ap = 0x7; } |
Kojto | 148:fd96258d940d | 1612 | } |
Kojto | 148:fd96258d940d | 1613 | |
Kojto | 148:fd96258d940d | 1614 | *descriptor_l2 &= PAGE_AP_MASK; |
Kojto | 148:fd96258d940d | 1615 | *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; |
Kojto | 148:fd96258d940d | 1616 | *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; |
Kojto | 148:fd96258d940d | 1617 | |
Kojto | 148:fd96258d940d | 1618 | return 0; |
Kojto | 148:fd96258d940d | 1619 | } |
Kojto | 148:fd96258d940d | 1620 | |
Kojto | 148:fd96258d940d | 1621 | /** \brief Set 4k/64k page shareability |
Kojto | 148:fd96258d940d | 1622 | |
Kojto | 148:fd96258d940d | 1623 | \param [out] descriptor_l2 L2 descriptor. |
Kojto | 148:fd96258d940d | 1624 | \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED |
Kojto | 148:fd96258d940d | 1625 | |
Kojto | 148:fd96258d940d | 1626 | \return 0 |
Kojto | 148:fd96258d940d | 1627 | */ |
Kojto | 148:fd96258d940d | 1628 | __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) |
Kojto | 148:fd96258d940d | 1629 | { |
Kojto | 148:fd96258d940d | 1630 | *descriptor_l2 &= PAGE_S_MASK; |
Kojto | 148:fd96258d940d | 1631 | *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); |
Kojto | 148:fd96258d940d | 1632 | return 0; |
Kojto | 148:fd96258d940d | 1633 | } |
Kojto | 148:fd96258d940d | 1634 | |
Kojto | 148:fd96258d940d | 1635 | /** \brief Set 4k/64k page Global attribute |
Kojto | 148:fd96258d940d | 1636 | |
Kojto | 148:fd96258d940d | 1637 | \param [out] descriptor_l2 L2 descriptor. |
Kojto | 148:fd96258d940d | 1638 | \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL |
Kojto | 148:fd96258d940d | 1639 | |
Kojto | 148:fd96258d940d | 1640 | \return 0 |
Kojto | 148:fd96258d940d | 1641 | */ |
Kojto | 148:fd96258d940d | 1642 | __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) |
Kojto | 148:fd96258d940d | 1643 | { |
Kojto | 148:fd96258d940d | 1644 | *descriptor_l2 &= PAGE_NG_MASK; |
Kojto | 148:fd96258d940d | 1645 | *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); |
Kojto | 148:fd96258d940d | 1646 | return 0; |
Kojto | 148:fd96258d940d | 1647 | } |
Kojto | 148:fd96258d940d | 1648 | |
Kojto | 148:fd96258d940d | 1649 | /** \brief Set 4k/64k page Security attribute |
Kojto | 148:fd96258d940d | 1650 | |
Kojto | 148:fd96258d940d | 1651 | \param [out] descriptor_l1 L1 descriptor. |
Kojto | 148:fd96258d940d | 1652 | \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE |
Kojto | 148:fd96258d940d | 1653 | |
Kojto | 148:fd96258d940d | 1654 | \return 0 |
Kojto | 148:fd96258d940d | 1655 | */ |
Kojto | 148:fd96258d940d | 1656 | __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) |
Kojto | 148:fd96258d940d | 1657 | { |
Kojto | 148:fd96258d940d | 1658 | *descriptor_l1 &= PAGE_NS_MASK; |
Kojto | 148:fd96258d940d | 1659 | *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); |
Kojto | 148:fd96258d940d | 1660 | return 0; |
Kojto | 148:fd96258d940d | 1661 | } |
Kojto | 148:fd96258d940d | 1662 | |
Kojto | 148:fd96258d940d | 1663 | /** \brief Set Section memory attributes |
Kojto | 148:fd96258d940d | 1664 | |
Kojto | 148:fd96258d940d | 1665 | \param [out] descriptor_l1 L1 descriptor. |
Kojto | 148:fd96258d940d | 1666 | \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED |
Kojto | 148:fd96258d940d | 1667 | \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, |
Kojto | 148:fd96258d940d | 1668 | \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, |
Kojto | 148:fd96258d940d | 1669 | |
Kojto | 148:fd96258d940d | 1670 | \return 0 |
Kojto | 148:fd96258d940d | 1671 | */ |
Kojto | 148:fd96258d940d | 1672 | __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) |
Kojto | 148:fd96258d940d | 1673 | { |
Kojto | 148:fd96258d940d | 1674 | *descriptor_l1 &= SECTION_TEXCB_MASK; |
Kojto | 148:fd96258d940d | 1675 | |
Kojto | 148:fd96258d940d | 1676 | if (STRONGLY_ORDERED == mem) |
Kojto | 148:fd96258d940d | 1677 | { |
Kojto | 148:fd96258d940d | 1678 | return 0; |
Kojto | 148:fd96258d940d | 1679 | } |
Kojto | 148:fd96258d940d | 1680 | else if (SHARED_DEVICE == mem) |
Kojto | 148:fd96258d940d | 1681 | { |
Kojto | 148:fd96258d940d | 1682 | *descriptor_l1 |= (1 << SECTION_B_SHIFT); |
Kojto | 148:fd96258d940d | 1683 | } |
Kojto | 148:fd96258d940d | 1684 | else if (NON_SHARED_DEVICE == mem) |
Kojto | 148:fd96258d940d | 1685 | { |
Kojto | 148:fd96258d940d | 1686 | *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); |
Kojto | 148:fd96258d940d | 1687 | } |
Kojto | 148:fd96258d940d | 1688 | else if (NORMAL == mem) |
Kojto | 148:fd96258d940d | 1689 | { |
Kojto | 148:fd96258d940d | 1690 | *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; |
Kojto | 148:fd96258d940d | 1691 | switch(inner) |
Kojto | 148:fd96258d940d | 1692 | { |
Kojto | 148:fd96258d940d | 1693 | case NON_CACHEABLE: |
Kojto | 148:fd96258d940d | 1694 | break; |
Kojto | 148:fd96258d940d | 1695 | case WB_WA: |
Kojto | 148:fd96258d940d | 1696 | *descriptor_l1 |= (1 << SECTION_B_SHIFT); |
Kojto | 148:fd96258d940d | 1697 | break; |
Kojto | 148:fd96258d940d | 1698 | case WT: |
Kojto | 148:fd96258d940d | 1699 | *descriptor_l1 |= 1 << SECTION_C_SHIFT; |
Kojto | 148:fd96258d940d | 1700 | break; |
Kojto | 148:fd96258d940d | 1701 | case WB_NO_WA: |
Kojto | 148:fd96258d940d | 1702 | *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); |
Kojto | 148:fd96258d940d | 1703 | break; |
Kojto | 148:fd96258d940d | 1704 | } |
Kojto | 148:fd96258d940d | 1705 | switch(outer) |
Kojto | 148:fd96258d940d | 1706 | { |
Kojto | 148:fd96258d940d | 1707 | case NON_CACHEABLE: |
Kojto | 148:fd96258d940d | 1708 | break; |
Kojto | 148:fd96258d940d | 1709 | case WB_WA: |
Kojto | 148:fd96258d940d | 1710 | *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); |
Kojto | 148:fd96258d940d | 1711 | break; |
Kojto | 148:fd96258d940d | 1712 | case WT: |
Kojto | 148:fd96258d940d | 1713 | *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; |
Kojto | 148:fd96258d940d | 1714 | break; |
Kojto | 148:fd96258d940d | 1715 | case WB_NO_WA: |
Kojto | 148:fd96258d940d | 1716 | *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); |
Kojto | 148:fd96258d940d | 1717 | break; |
Kojto | 148:fd96258d940d | 1718 | } |
Kojto | 148:fd96258d940d | 1719 | } |
Kojto | 148:fd96258d940d | 1720 | return 0; |
Kojto | 148:fd96258d940d | 1721 | } |
Kojto | 148:fd96258d940d | 1722 | |
Kojto | 148:fd96258d940d | 1723 | /** \brief Set 4k/64k page memory attributes |
Kojto | 148:fd96258d940d | 1724 | |
Kojto | 148:fd96258d940d | 1725 | \param [out] descriptor_l2 L2 descriptor. |
Kojto | 148:fd96258d940d | 1726 | \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED |
Kojto | 148:fd96258d940d | 1727 | \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, |
Kojto | 148:fd96258d940d | 1728 | \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, |
Kojto | 148:fd96258d940d | 1729 | \param [in] page Page size |
Kojto | 148:fd96258d940d | 1730 | |
Kojto | 148:fd96258d940d | 1731 | \return 0 |
Kojto | 148:fd96258d940d | 1732 | */ |
Kojto | 148:fd96258d940d | 1733 | __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) |
Kojto | 148:fd96258d940d | 1734 | { |
Kojto | 148:fd96258d940d | 1735 | *descriptor_l2 &= PAGE_4K_TEXCB_MASK; |
Kojto | 148:fd96258d940d | 1736 | |
Kojto | 148:fd96258d940d | 1737 | if (page == PAGE_64k) |
Kojto | 148:fd96258d940d | 1738 | { |
Kojto | 148:fd96258d940d | 1739 | //same as section |
Kojto | 148:fd96258d940d | 1740 | MMU_MemorySection(descriptor_l2, mem, outer, inner); |
Kojto | 148:fd96258d940d | 1741 | } |
Kojto | 148:fd96258d940d | 1742 | else |
Kojto | 148:fd96258d940d | 1743 | { |
Kojto | 148:fd96258d940d | 1744 | if (STRONGLY_ORDERED == mem) |
Kojto | 148:fd96258d940d | 1745 | { |
Kojto | 148:fd96258d940d | 1746 | return 0; |
Kojto | 148:fd96258d940d | 1747 | } |
Kojto | 148:fd96258d940d | 1748 | else if (SHARED_DEVICE == mem) |
Kojto | 148:fd96258d940d | 1749 | { |
Kojto | 148:fd96258d940d | 1750 | *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); |
Kojto | 148:fd96258d940d | 1751 | } |
Kojto | 148:fd96258d940d | 1752 | else if (NON_SHARED_DEVICE == mem) |
Kojto | 148:fd96258d940d | 1753 | { |
Kojto | 148:fd96258d940d | 1754 | *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); |
Kojto | 148:fd96258d940d | 1755 | } |
Kojto | 148:fd96258d940d | 1756 | else if (NORMAL == mem) |
Kojto | 148:fd96258d940d | 1757 | { |
Kojto | 148:fd96258d940d | 1758 | *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; |
Kojto | 148:fd96258d940d | 1759 | switch(inner) |
Kojto | 148:fd96258d940d | 1760 | { |
Kojto | 148:fd96258d940d | 1761 | case NON_CACHEABLE: |
Kojto | 148:fd96258d940d | 1762 | break; |
Kojto | 148:fd96258d940d | 1763 | case WB_WA: |
Kojto | 148:fd96258d940d | 1764 | *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); |
Kojto | 148:fd96258d940d | 1765 | break; |
Kojto | 148:fd96258d940d | 1766 | case WT: |
Kojto | 148:fd96258d940d | 1767 | *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; |
Kojto | 148:fd96258d940d | 1768 | break; |
Kojto | 148:fd96258d940d | 1769 | case WB_NO_WA: |
Kojto | 148:fd96258d940d | 1770 | *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); |
Kojto | 148:fd96258d940d | 1771 | break; |
Kojto | 148:fd96258d940d | 1772 | } |
Kojto | 148:fd96258d940d | 1773 | switch(outer) |
Kojto | 148:fd96258d940d | 1774 | { |
Kojto | 148:fd96258d940d | 1775 | case NON_CACHEABLE: |
Kojto | 148:fd96258d940d | 1776 | break; |
Kojto | 148:fd96258d940d | 1777 | case WB_WA: |
Kojto | 148:fd96258d940d | 1778 | *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); |
Kojto | 148:fd96258d940d | 1779 | break; |
Kojto | 148:fd96258d940d | 1780 | case WT: |
Kojto | 148:fd96258d940d | 1781 | *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; |
Kojto | 148:fd96258d940d | 1782 | break; |
Kojto | 148:fd96258d940d | 1783 | case WB_NO_WA: |
Kojto | 148:fd96258d940d | 1784 | *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); |
Kojto | 148:fd96258d940d | 1785 | break; |
Kojto | 148:fd96258d940d | 1786 | } |
Kojto | 148:fd96258d940d | 1787 | } |
Kojto | 148:fd96258d940d | 1788 | } |
Kojto | 148:fd96258d940d | 1789 | |
Kojto | 148:fd96258d940d | 1790 | return 0; |
Kojto | 148:fd96258d940d | 1791 | } |
Kojto | 148:fd96258d940d | 1792 | |
Kojto | 148:fd96258d940d | 1793 | /** \brief Create a L1 section descriptor |
Kojto | 148:fd96258d940d | 1794 | |
Kojto | 148:fd96258d940d | 1795 | \param [out] descriptor L1 descriptor |
Kojto | 148:fd96258d940d | 1796 | \param [in] reg Section attributes |
Kojto | 148:fd96258d940d | 1797 | |
Kojto | 148:fd96258d940d | 1798 | \return 0 |
Kojto | 148:fd96258d940d | 1799 | */ |
Kojto | 148:fd96258d940d | 1800 | __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) |
Kojto | 148:fd96258d940d | 1801 | { |
Kojto | 148:fd96258d940d | 1802 | *descriptor = 0; |
Kojto | 148:fd96258d940d | 1803 | |
Kojto | 148:fd96258d940d | 1804 | MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); |
Kojto | 148:fd96258d940d | 1805 | MMU_XNSection(descriptor,reg.xn_t); |
Kojto | 148:fd96258d940d | 1806 | MMU_DomainSection(descriptor, reg.domain); |
Kojto | 148:fd96258d940d | 1807 | MMU_PSection(descriptor, reg.e_t); |
Kojto | 148:fd96258d940d | 1808 | MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1); |
Kojto | 148:fd96258d940d | 1809 | MMU_SharedSection(descriptor,reg.sh_t); |
Kojto | 148:fd96258d940d | 1810 | MMU_GlobalSection(descriptor,reg.g_t); |
Kojto | 148:fd96258d940d | 1811 | MMU_SecureSection(descriptor,reg.sec_t); |
Kojto | 148:fd96258d940d | 1812 | *descriptor &= SECTION_MASK; |
Kojto | 148:fd96258d940d | 1813 | *descriptor |= SECTION_DESCRIPTOR; |
Kojto | 148:fd96258d940d | 1814 | |
Kojto | 148:fd96258d940d | 1815 | return 0; |
Kojto | 148:fd96258d940d | 1816 | } |
Kojto | 148:fd96258d940d | 1817 | |
Kojto | 148:fd96258d940d | 1818 | |
Kojto | 148:fd96258d940d | 1819 | /** \brief Create a L1 and L2 4k/64k page descriptor |
Kojto | 148:fd96258d940d | 1820 | |
Kojto | 148:fd96258d940d | 1821 | \param [out] descriptor L1 descriptor |
Kojto | 148:fd96258d940d | 1822 | \param [out] descriptor2 L2 descriptor |
Kojto | 148:fd96258d940d | 1823 | \param [in] reg 4k/64k page attributes |
Kojto | 148:fd96258d940d | 1824 | |
Kojto | 148:fd96258d940d | 1825 | \return 0 |
Kojto | 148:fd96258d940d | 1826 | */ |
Kojto | 148:fd96258d940d | 1827 | __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) |
Kojto | 148:fd96258d940d | 1828 | { |
Kojto | 148:fd96258d940d | 1829 | *descriptor = 0; |
Kojto | 148:fd96258d940d | 1830 | *descriptor2 = 0; |
Kojto | 148:fd96258d940d | 1831 | |
Kojto | 148:fd96258d940d | 1832 | switch (reg.rg_t) |
Kojto | 148:fd96258d940d | 1833 | { |
Kojto | 148:fd96258d940d | 1834 | case PAGE_4k: |
Kojto | 148:fd96258d940d | 1835 | MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); |
Kojto | 148:fd96258d940d | 1836 | MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); |
Kojto | 148:fd96258d940d | 1837 | MMU_DomainPage(descriptor, reg.domain); |
Kojto | 148:fd96258d940d | 1838 | MMU_PPage(descriptor, reg.e_t); |
Kojto | 148:fd96258d940d | 1839 | MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); |
Kojto | 148:fd96258d940d | 1840 | MMU_SharedPage(descriptor2,reg.sh_t); |
Kojto | 148:fd96258d940d | 1841 | MMU_GlobalPage(descriptor2,reg.g_t); |
Kojto | 148:fd96258d940d | 1842 | MMU_SecurePage(descriptor,reg.sec_t); |
Kojto | 148:fd96258d940d | 1843 | *descriptor &= PAGE_L1_MASK; |
Kojto | 148:fd96258d940d | 1844 | *descriptor |= PAGE_L1_DESCRIPTOR; |
Kojto | 148:fd96258d940d | 1845 | *descriptor2 &= PAGE_L2_4K_MASK; |
Kojto | 148:fd96258d940d | 1846 | *descriptor2 |= PAGE_L2_4K_DESC; |
Kojto | 148:fd96258d940d | 1847 | break; |
Kojto | 148:fd96258d940d | 1848 | |
Kojto | 148:fd96258d940d | 1849 | case PAGE_64k: |
Kojto | 148:fd96258d940d | 1850 | MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); |
Kojto | 148:fd96258d940d | 1851 | MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); |
Kojto | 148:fd96258d940d | 1852 | MMU_DomainPage(descriptor, reg.domain); |
Kojto | 148:fd96258d940d | 1853 | MMU_PPage(descriptor, reg.e_t); |
Kojto | 148:fd96258d940d | 1854 | MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); |
Kojto | 148:fd96258d940d | 1855 | MMU_SharedPage(descriptor2,reg.sh_t); |
Kojto | 148:fd96258d940d | 1856 | MMU_GlobalPage(descriptor2,reg.g_t); |
Kojto | 148:fd96258d940d | 1857 | MMU_SecurePage(descriptor,reg.sec_t); |
Kojto | 148:fd96258d940d | 1858 | *descriptor &= PAGE_L1_MASK; |
Kojto | 148:fd96258d940d | 1859 | *descriptor |= PAGE_L1_DESCRIPTOR; |
Kojto | 148:fd96258d940d | 1860 | *descriptor2 &= PAGE_L2_64K_MASK; |
Kojto | 148:fd96258d940d | 1861 | *descriptor2 |= PAGE_L2_64K_DESC; |
Kojto | 148:fd96258d940d | 1862 | break; |
Kojto | 148:fd96258d940d | 1863 | |
Kojto | 148:fd96258d940d | 1864 | case SECTION: |
Kojto | 148:fd96258d940d | 1865 | //error |
Kojto | 148:fd96258d940d | 1866 | break; |
Kojto | 148:fd96258d940d | 1867 | } |
Kojto | 148:fd96258d940d | 1868 | |
Kojto | 148:fd96258d940d | 1869 | return 0; |
Kojto | 148:fd96258d940d | 1870 | } |
Kojto | 148:fd96258d940d | 1871 | |
Kojto | 148:fd96258d940d | 1872 | /** \brief Create a 1MB Section |
Kojto | 148:fd96258d940d | 1873 | |
Kojto | 148:fd96258d940d | 1874 | \param [in] ttb Translation table base address |
Kojto | 148:fd96258d940d | 1875 | \param [in] base_address Section base address |
Kojto | 148:fd96258d940d | 1876 | \param [in] count Number of sections to create |
Kojto | 148:fd96258d940d | 1877 | \param [in] descriptor_l1 L1 descriptor (region attributes) |
Kojto | 148:fd96258d940d | 1878 | |
Kojto | 148:fd96258d940d | 1879 | */ |
Kojto | 148:fd96258d940d | 1880 | __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) |
Kojto | 148:fd96258d940d | 1881 | { |
Kojto | 148:fd96258d940d | 1882 | uint32_t offset; |
Kojto | 148:fd96258d940d | 1883 | uint32_t entry; |
Kojto | 148:fd96258d940d | 1884 | uint32_t i; |
Kojto | 148:fd96258d940d | 1885 | |
Kojto | 148:fd96258d940d | 1886 | offset = base_address >> 20; |
Kojto | 148:fd96258d940d | 1887 | entry = (base_address & 0xFFF00000) | descriptor_l1; |
Kojto | 148:fd96258d940d | 1888 | |
Kojto | 148:fd96258d940d | 1889 | //4 bytes aligned |
Kojto | 148:fd96258d940d | 1890 | ttb = ttb + offset; |
Kojto | 148:fd96258d940d | 1891 | |
Kojto | 148:fd96258d940d | 1892 | for (i = 0; i < count; i++ ) |
Kojto | 148:fd96258d940d | 1893 | { |
Kojto | 148:fd96258d940d | 1894 | //4 bytes aligned |
Kojto | 148:fd96258d940d | 1895 | *ttb++ = entry; |
Kojto | 148:fd96258d940d | 1896 | entry += OFFSET_1M; |
Kojto | 148:fd96258d940d | 1897 | } |
Kojto | 148:fd96258d940d | 1898 | } |
Kojto | 148:fd96258d940d | 1899 | |
Kojto | 148:fd96258d940d | 1900 | /** \brief Create a 4k page entry |
Kojto | 148:fd96258d940d | 1901 | |
Kojto | 148:fd96258d940d | 1902 | \param [in] ttb L1 table base address |
Kojto | 148:fd96258d940d | 1903 | \param [in] base_address 4k base address |
Kojto | 148:fd96258d940d | 1904 | \param [in] count Number of 4k pages to create |
Kojto | 148:fd96258d940d | 1905 | \param [in] descriptor_l1 L1 descriptor (region attributes) |
Kojto | 148:fd96258d940d | 1906 | \param [in] ttb_l2 L2 table base address |
Kojto | 148:fd96258d940d | 1907 | \param [in] descriptor_l2 L2 descriptor (region attributes) |
Kojto | 148:fd96258d940d | 1908 | |
Kojto | 148:fd96258d940d | 1909 | */ |
Kojto | 148:fd96258d940d | 1910 | __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) |
Kojto | 148:fd96258d940d | 1911 | { |
Kojto | 148:fd96258d940d | 1912 | |
Kojto | 148:fd96258d940d | 1913 | uint32_t offset, offset2; |
Kojto | 148:fd96258d940d | 1914 | uint32_t entry, entry2; |
Kojto | 148:fd96258d940d | 1915 | uint32_t i; |
Kojto | 148:fd96258d940d | 1916 | |
Kojto | 148:fd96258d940d | 1917 | offset = base_address >> 20; |
Kojto | 148:fd96258d940d | 1918 | entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; |
Kojto | 148:fd96258d940d | 1919 | |
Kojto | 148:fd96258d940d | 1920 | //4 bytes aligned |
Kojto | 148:fd96258d940d | 1921 | ttb += offset; |
Kojto | 148:fd96258d940d | 1922 | //create l1_entry |
Kojto | 148:fd96258d940d | 1923 | *ttb = entry; |
Kojto | 148:fd96258d940d | 1924 | |
Kojto | 148:fd96258d940d | 1925 | offset2 = (base_address & 0xff000) >> 12; |
Kojto | 148:fd96258d940d | 1926 | ttb_l2 += offset2; |
Kojto | 148:fd96258d940d | 1927 | entry2 = (base_address & 0xFFFFF000) | descriptor_l2; |
Kojto | 148:fd96258d940d | 1928 | for (i = 0; i < count; i++ ) |
Kojto | 148:fd96258d940d | 1929 | { |
Kojto | 148:fd96258d940d | 1930 | //4 bytes aligned |
Kojto | 148:fd96258d940d | 1931 | *ttb_l2++ = entry2; |
Kojto | 148:fd96258d940d | 1932 | entry2 += OFFSET_4K; |
Kojto | 148:fd96258d940d | 1933 | } |
Kojto | 148:fd96258d940d | 1934 | } |
Kojto | 148:fd96258d940d | 1935 | |
Kojto | 148:fd96258d940d | 1936 | /** \brief Create a 64k page entry |
Kojto | 148:fd96258d940d | 1937 | |
Kojto | 148:fd96258d940d | 1938 | \param [in] ttb L1 table base address |
Kojto | 148:fd96258d940d | 1939 | \param [in] base_address 64k base address |
Kojto | 148:fd96258d940d | 1940 | \param [in] count Number of 64k pages to create |
Kojto | 148:fd96258d940d | 1941 | \param [in] descriptor_l1 L1 descriptor (region attributes) |
Kojto | 148:fd96258d940d | 1942 | \param [in] ttb_l2 L2 table base address |
Kojto | 148:fd96258d940d | 1943 | \param [in] descriptor_l2 L2 descriptor (region attributes) |
Kojto | 148:fd96258d940d | 1944 | |
Kojto | 148:fd96258d940d | 1945 | */ |
Kojto | 148:fd96258d940d | 1946 | __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) |
Kojto | 148:fd96258d940d | 1947 | { |
Kojto | 148:fd96258d940d | 1948 | uint32_t offset, offset2; |
Kojto | 148:fd96258d940d | 1949 | uint32_t entry, entry2; |
Kojto | 148:fd96258d940d | 1950 | uint32_t i,j; |
Kojto | 148:fd96258d940d | 1951 | |
Kojto | 148:fd96258d940d | 1952 | |
Kojto | 148:fd96258d940d | 1953 | offset = base_address >> 20; |
Kojto | 148:fd96258d940d | 1954 | entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; |
Kojto | 148:fd96258d940d | 1955 | |
Kojto | 148:fd96258d940d | 1956 | //4 bytes aligned |
Kojto | 148:fd96258d940d | 1957 | ttb += offset; |
Kojto | 148:fd96258d940d | 1958 | //create l1_entry |
Kojto | 148:fd96258d940d | 1959 | *ttb = entry; |
Kojto | 148:fd96258d940d | 1960 | |
Kojto | 148:fd96258d940d | 1961 | offset2 = (base_address & 0xff000) >> 12; |
Kojto | 148:fd96258d940d | 1962 | ttb_l2 += offset2; |
Kojto | 148:fd96258d940d | 1963 | entry2 = (base_address & 0xFFFF0000) | descriptor_l2; |
Kojto | 148:fd96258d940d | 1964 | for (i = 0; i < count; i++ ) |
Kojto | 148:fd96258d940d | 1965 | { |
Kojto | 148:fd96258d940d | 1966 | //create 16 entries |
Kojto | 148:fd96258d940d | 1967 | for (j = 0; j < 16; j++) |
Kojto | 148:fd96258d940d | 1968 | { |
Kojto | 148:fd96258d940d | 1969 | //4 bytes aligned |
Kojto | 148:fd96258d940d | 1970 | *ttb_l2++ = entry2; |
Kojto | 148:fd96258d940d | 1971 | } |
Kojto | 148:fd96258d940d | 1972 | entry2 += OFFSET_64K; |
Kojto | 148:fd96258d940d | 1973 | } |
Kojto | 148:fd96258d940d | 1974 | } |
Kojto | 148:fd96258d940d | 1975 | |
Kojto | 148:fd96258d940d | 1976 | /** \brief Enable MMU |
Kojto | 148:fd96258d940d | 1977 | |
Kojto | 148:fd96258d940d | 1978 | Enable MMU |
Kojto | 148:fd96258d940d | 1979 | */ |
Kojto | 148:fd96258d940d | 1980 | __STATIC_INLINE void MMU_Enable(void) { |
Kojto | 148:fd96258d940d | 1981 | // Set M bit 0 to enable the MMU |
Kojto | 148:fd96258d940d | 1982 | // Set AFE bit to enable simplified access permissions model |
Kojto | 148:fd96258d940d | 1983 | // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking |
Kojto | 148:fd96258d940d | 1984 | __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); |
Kojto | 148:fd96258d940d | 1985 | __ISB(); |
Kojto | 148:fd96258d940d | 1986 | } |
Kojto | 148:fd96258d940d | 1987 | |
Kojto | 148:fd96258d940d | 1988 | /** \brief Disable MMU |
Kojto | 148:fd96258d940d | 1989 | |
Kojto | 148:fd96258d940d | 1990 | Disable MMU |
Kojto | 148:fd96258d940d | 1991 | */ |
Kojto | 148:fd96258d940d | 1992 | __STATIC_INLINE void MMU_Disable(void) { |
Kojto | 148:fd96258d940d | 1993 | // Clear M bit 0 to disable the MMU |
Kojto | 148:fd96258d940d | 1994 | __set_SCTLR( __get_SCTLR() & ~1); |
Kojto | 148:fd96258d940d | 1995 | __ISB(); |
Kojto | 148:fd96258d940d | 1996 | } |
Kojto | 148:fd96258d940d | 1997 | |
Kojto | 148:fd96258d940d | 1998 | /** \brief Invalidate entire unified TLB |
Kojto | 148:fd96258d940d | 1999 | |
Kojto | 148:fd96258d940d | 2000 | TLBIALL. Invalidate entire unified TLB |
Kojto | 148:fd96258d940d | 2001 | */ |
Kojto | 148:fd96258d940d | 2002 | |
Kojto | 148:fd96258d940d | 2003 | __STATIC_INLINE void MMU_InvalidateTLB(void) { |
Kojto | 148:fd96258d940d | 2004 | __set_TLBIALL(0); |
Kojto | 148:fd96258d940d | 2005 | __DSB(); //ensure completion of the invalidation |
Kojto | 148:fd96258d940d | 2006 | __ISB(); //ensure instruction fetch path sees new state |
Kojto | 148:fd96258d940d | 2007 | } |
Kojto | 148:fd96258d940d | 2008 | |
Kojto | 148:fd96258d940d | 2009 | |
Kojto | 148:fd96258d940d | 2010 | #ifdef __cplusplus |
Kojto | 148:fd96258d940d | 2011 | } |
Kojto | 148:fd96258d940d | 2012 | #endif |
Kojto | 148:fd96258d940d | 2013 | |
Kojto | 148:fd96258d940d | 2014 | #endif /* __CORE_CA_H_DEPENDANT */ |
Kojto | 148:fd96258d940d | 2015 | |
Kojto | 148:fd96258d940d | 2016 | #endif /* __CMSIS_GENERIC */ |