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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_SEEED_TINY_BLE/core_cm0.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
156:ff21514d8981
Child:
160:5571c4ff569f
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 2 * @file core_cm0.h
AnnaBridge 156:ff21514d8981 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
AnnaBridge 156:ff21514d8981 4 * @version V5.0.2
AnnaBridge 156:ff21514d8981 5 * @date 13. February 2017
AnnaBridge 156:ff21514d8981 6 ******************************************************************************/
AnnaBridge 156:ff21514d8981 7 /*
AnnaBridge 156:ff21514d8981 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 156:ff21514d8981 9 *
AnnaBridge 156:ff21514d8981 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 156:ff21514d8981 11 *
AnnaBridge 156:ff21514d8981 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 156:ff21514d8981 13 * not use this file except in compliance with the License.
AnnaBridge 156:ff21514d8981 14 * You may obtain a copy of the License at
AnnaBridge 156:ff21514d8981 15 *
AnnaBridge 156:ff21514d8981 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 156:ff21514d8981 17 *
AnnaBridge 156:ff21514d8981 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 156:ff21514d8981 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 156:ff21514d8981 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 156:ff21514d8981 21 * See the License for the specific language governing permissions and
AnnaBridge 156:ff21514d8981 22 * limitations under the License.
AnnaBridge 156:ff21514d8981 23 */
AnnaBridge 156:ff21514d8981 24
AnnaBridge 156:ff21514d8981 25 #if defined ( __ICCARM__ )
AnnaBridge 156:ff21514d8981 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 156:ff21514d8981 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 156:ff21514d8981 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 156:ff21514d8981 29 #endif
AnnaBridge 156:ff21514d8981 30
AnnaBridge 156:ff21514d8981 31 #ifndef __CORE_CM0_H_GENERIC
AnnaBridge 156:ff21514d8981 32 #define __CORE_CM0_H_GENERIC
AnnaBridge 156:ff21514d8981 33
AnnaBridge 156:ff21514d8981 34 #include <stdint.h>
AnnaBridge 156:ff21514d8981 35
AnnaBridge 156:ff21514d8981 36 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 37 extern "C" {
AnnaBridge 156:ff21514d8981 38 #endif
AnnaBridge 156:ff21514d8981 39
AnnaBridge 156:ff21514d8981 40 /**
AnnaBridge 156:ff21514d8981 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 156:ff21514d8981 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 156:ff21514d8981 43
AnnaBridge 156:ff21514d8981 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 156:ff21514d8981 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 156:ff21514d8981 46
AnnaBridge 156:ff21514d8981 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 156:ff21514d8981 48 Unions are used for effective representation of core registers.
AnnaBridge 156:ff21514d8981 49
AnnaBridge 156:ff21514d8981 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 156:ff21514d8981 51 Function-like macros are used to allow more efficient code.
AnnaBridge 156:ff21514d8981 52 */
AnnaBridge 156:ff21514d8981 53
AnnaBridge 156:ff21514d8981 54
AnnaBridge 156:ff21514d8981 55 /*******************************************************************************
AnnaBridge 156:ff21514d8981 56 * CMSIS definitions
AnnaBridge 156:ff21514d8981 57 ******************************************************************************/
AnnaBridge 156:ff21514d8981 58 /**
AnnaBridge 156:ff21514d8981 59 \ingroup Cortex_M0
AnnaBridge 156:ff21514d8981 60 @{
AnnaBridge 156:ff21514d8981 61 */
AnnaBridge 156:ff21514d8981 62
AnnaBridge 156:ff21514d8981 63 /* CMSIS CM0 definitions */
AnnaBridge 156:ff21514d8981 64 #define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 156:ff21514d8981 65 #define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 156:ff21514d8981 66 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 156:ff21514d8981 67 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 156:ff21514d8981 68
AnnaBridge 156:ff21514d8981 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
AnnaBridge 156:ff21514d8981 70
AnnaBridge 156:ff21514d8981 71 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 156:ff21514d8981 72 This core does not support an FPU at all
AnnaBridge 156:ff21514d8981 73 */
AnnaBridge 156:ff21514d8981 74 #define __FPU_USED 0U
AnnaBridge 156:ff21514d8981 75
AnnaBridge 156:ff21514d8981 76 #if defined ( __CC_ARM )
AnnaBridge 156:ff21514d8981 77 #if defined __TARGET_FPU_VFP
AnnaBridge 156:ff21514d8981 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 156:ff21514d8981 79 #endif
AnnaBridge 156:ff21514d8981 80
AnnaBridge 156:ff21514d8981 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 156:ff21514d8981 82 #if defined __ARM_PCS_VFP
AnnaBridge 156:ff21514d8981 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 156:ff21514d8981 84 #endif
AnnaBridge 156:ff21514d8981 85
AnnaBridge 156:ff21514d8981 86 #elif defined ( __GNUC__ )
AnnaBridge 156:ff21514d8981 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 156:ff21514d8981 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 156:ff21514d8981 89 #endif
AnnaBridge 156:ff21514d8981 90
AnnaBridge 156:ff21514d8981 91 #elif defined ( __ICCARM__ )
AnnaBridge 156:ff21514d8981 92 #if defined __ARMVFP__
AnnaBridge 156:ff21514d8981 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 156:ff21514d8981 94 #endif
AnnaBridge 156:ff21514d8981 95
AnnaBridge 156:ff21514d8981 96 #elif defined ( __TI_ARM__ )
AnnaBridge 156:ff21514d8981 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 156:ff21514d8981 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 156:ff21514d8981 99 #endif
AnnaBridge 156:ff21514d8981 100
AnnaBridge 156:ff21514d8981 101 #elif defined ( __TASKING__ )
AnnaBridge 156:ff21514d8981 102 #if defined __FPU_VFP__
AnnaBridge 156:ff21514d8981 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 156:ff21514d8981 104 #endif
AnnaBridge 156:ff21514d8981 105
AnnaBridge 156:ff21514d8981 106 #elif defined ( __CSMC__ )
AnnaBridge 156:ff21514d8981 107 #if ( __CSMC__ & 0x400U)
AnnaBridge 156:ff21514d8981 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 156:ff21514d8981 109 #endif
AnnaBridge 156:ff21514d8981 110
AnnaBridge 156:ff21514d8981 111 #endif
AnnaBridge 156:ff21514d8981 112
AnnaBridge 156:ff21514d8981 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 156:ff21514d8981 114
AnnaBridge 156:ff21514d8981 115
AnnaBridge 156:ff21514d8981 116 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 117 }
AnnaBridge 156:ff21514d8981 118 #endif
AnnaBridge 156:ff21514d8981 119
AnnaBridge 156:ff21514d8981 120 #endif /* __CORE_CM0_H_GENERIC */
AnnaBridge 156:ff21514d8981 121
AnnaBridge 156:ff21514d8981 122 #ifndef __CMSIS_GENERIC
AnnaBridge 156:ff21514d8981 123
AnnaBridge 156:ff21514d8981 124 #ifndef __CORE_CM0_H_DEPENDANT
AnnaBridge 156:ff21514d8981 125 #define __CORE_CM0_H_DEPENDANT
AnnaBridge 156:ff21514d8981 126
AnnaBridge 156:ff21514d8981 127 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 128 extern "C" {
AnnaBridge 156:ff21514d8981 129 #endif
AnnaBridge 156:ff21514d8981 130
AnnaBridge 156:ff21514d8981 131 /* check device defines and use defaults */
AnnaBridge 156:ff21514d8981 132 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 156:ff21514d8981 133 #ifndef __CM0_REV
AnnaBridge 156:ff21514d8981 134 #define __CM0_REV 0x0000U
AnnaBridge 156:ff21514d8981 135 #warning "__CM0_REV not defined in device header file; using default!"
AnnaBridge 156:ff21514d8981 136 #endif
AnnaBridge 156:ff21514d8981 137
AnnaBridge 156:ff21514d8981 138 #ifndef __NVIC_PRIO_BITS
AnnaBridge 156:ff21514d8981 139 #define __NVIC_PRIO_BITS 2U
AnnaBridge 156:ff21514d8981 140 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 156:ff21514d8981 141 #endif
AnnaBridge 156:ff21514d8981 142
AnnaBridge 156:ff21514d8981 143 #ifndef __Vendor_SysTickConfig
AnnaBridge 156:ff21514d8981 144 #define __Vendor_SysTickConfig 0U
AnnaBridge 156:ff21514d8981 145 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 156:ff21514d8981 146 #endif
AnnaBridge 156:ff21514d8981 147 #endif
AnnaBridge 156:ff21514d8981 148
AnnaBridge 156:ff21514d8981 149 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 156:ff21514d8981 150 /**
AnnaBridge 156:ff21514d8981 151 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 156:ff21514d8981 152
AnnaBridge 156:ff21514d8981 153 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 156:ff21514d8981 154 \li to specify the access to peripheral variables.
AnnaBridge 156:ff21514d8981 155 \li for automatic generation of peripheral register debug information.
AnnaBridge 156:ff21514d8981 156 */
AnnaBridge 156:ff21514d8981 157 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 158 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 156:ff21514d8981 159 #else
AnnaBridge 156:ff21514d8981 160 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 156:ff21514d8981 161 #endif
AnnaBridge 156:ff21514d8981 162 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 156:ff21514d8981 163 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 156:ff21514d8981 164
AnnaBridge 156:ff21514d8981 165 /* following defines should be used for structure members */
AnnaBridge 156:ff21514d8981 166 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 156:ff21514d8981 167 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 156:ff21514d8981 168 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 156:ff21514d8981 169
AnnaBridge 156:ff21514d8981 170 /*@} end of group Cortex_M0 */
AnnaBridge 156:ff21514d8981 171
AnnaBridge 156:ff21514d8981 172
AnnaBridge 156:ff21514d8981 173
AnnaBridge 156:ff21514d8981 174 /*******************************************************************************
AnnaBridge 156:ff21514d8981 175 * Register Abstraction
AnnaBridge 156:ff21514d8981 176 Core Register contain:
AnnaBridge 156:ff21514d8981 177 - Core Register
AnnaBridge 156:ff21514d8981 178 - Core NVIC Register
AnnaBridge 156:ff21514d8981 179 - Core SCB Register
AnnaBridge 156:ff21514d8981 180 - Core SysTick Register
AnnaBridge 156:ff21514d8981 181 ******************************************************************************/
AnnaBridge 156:ff21514d8981 182 /**
AnnaBridge 156:ff21514d8981 183 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 156:ff21514d8981 184 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 156:ff21514d8981 185 */
AnnaBridge 156:ff21514d8981 186
AnnaBridge 156:ff21514d8981 187 /**
AnnaBridge 156:ff21514d8981 188 \ingroup CMSIS_core_register
AnnaBridge 156:ff21514d8981 189 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 156:ff21514d8981 190 \brief Core Register type definitions.
AnnaBridge 156:ff21514d8981 191 @{
AnnaBridge 156:ff21514d8981 192 */
AnnaBridge 156:ff21514d8981 193
AnnaBridge 156:ff21514d8981 194 /**
AnnaBridge 156:ff21514d8981 195 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 156:ff21514d8981 196 */
AnnaBridge 156:ff21514d8981 197 typedef union
AnnaBridge 156:ff21514d8981 198 {
AnnaBridge 156:ff21514d8981 199 struct
AnnaBridge 156:ff21514d8981 200 {
AnnaBridge 156:ff21514d8981 201 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 156:ff21514d8981 202 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 156:ff21514d8981 203 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 156:ff21514d8981 204 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 156:ff21514d8981 205 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 156:ff21514d8981 206 } b; /*!< Structure used for bit access */
AnnaBridge 156:ff21514d8981 207 uint32_t w; /*!< Type used for word access */
AnnaBridge 156:ff21514d8981 208 } APSR_Type;
AnnaBridge 156:ff21514d8981 209
AnnaBridge 156:ff21514d8981 210 /* APSR Register Definitions */
AnnaBridge 156:ff21514d8981 211 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 156:ff21514d8981 212 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 156:ff21514d8981 213
AnnaBridge 156:ff21514d8981 214 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 156:ff21514d8981 215 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 156:ff21514d8981 216
AnnaBridge 156:ff21514d8981 217 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 156:ff21514d8981 218 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 156:ff21514d8981 219
AnnaBridge 156:ff21514d8981 220 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 156:ff21514d8981 221 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 156:ff21514d8981 222
AnnaBridge 156:ff21514d8981 223
AnnaBridge 156:ff21514d8981 224 /**
AnnaBridge 156:ff21514d8981 225 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 156:ff21514d8981 226 */
AnnaBridge 156:ff21514d8981 227 typedef union
AnnaBridge 156:ff21514d8981 228 {
AnnaBridge 156:ff21514d8981 229 struct
AnnaBridge 156:ff21514d8981 230 {
AnnaBridge 156:ff21514d8981 231 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 156:ff21514d8981 232 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 156:ff21514d8981 233 } b; /*!< Structure used for bit access */
AnnaBridge 156:ff21514d8981 234 uint32_t w; /*!< Type used for word access */
AnnaBridge 156:ff21514d8981 235 } IPSR_Type;
AnnaBridge 156:ff21514d8981 236
AnnaBridge 156:ff21514d8981 237 /* IPSR Register Definitions */
AnnaBridge 156:ff21514d8981 238 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 156:ff21514d8981 239 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 156:ff21514d8981 240
AnnaBridge 156:ff21514d8981 241
AnnaBridge 156:ff21514d8981 242 /**
AnnaBridge 156:ff21514d8981 243 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 156:ff21514d8981 244 */
AnnaBridge 156:ff21514d8981 245 typedef union
AnnaBridge 156:ff21514d8981 246 {
AnnaBridge 156:ff21514d8981 247 struct
AnnaBridge 156:ff21514d8981 248 {
AnnaBridge 156:ff21514d8981 249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 156:ff21514d8981 250 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 156:ff21514d8981 251 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 156:ff21514d8981 252 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 156:ff21514d8981 253 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 156:ff21514d8981 254 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 156:ff21514d8981 255 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 156:ff21514d8981 256 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 156:ff21514d8981 257 } b; /*!< Structure used for bit access */
AnnaBridge 156:ff21514d8981 258 uint32_t w; /*!< Type used for word access */
AnnaBridge 156:ff21514d8981 259 } xPSR_Type;
AnnaBridge 156:ff21514d8981 260
AnnaBridge 156:ff21514d8981 261 /* xPSR Register Definitions */
AnnaBridge 156:ff21514d8981 262 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 156:ff21514d8981 263 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 156:ff21514d8981 264
AnnaBridge 156:ff21514d8981 265 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 156:ff21514d8981 266 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 156:ff21514d8981 267
AnnaBridge 156:ff21514d8981 268 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 156:ff21514d8981 269 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 156:ff21514d8981 270
AnnaBridge 156:ff21514d8981 271 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 156:ff21514d8981 272 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 156:ff21514d8981 273
AnnaBridge 156:ff21514d8981 274 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 156:ff21514d8981 275 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 156:ff21514d8981 276
AnnaBridge 156:ff21514d8981 277 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 156:ff21514d8981 278 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 156:ff21514d8981 279
AnnaBridge 156:ff21514d8981 280
AnnaBridge 156:ff21514d8981 281 /**
AnnaBridge 156:ff21514d8981 282 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 156:ff21514d8981 283 */
AnnaBridge 156:ff21514d8981 284 typedef union
AnnaBridge 156:ff21514d8981 285 {
AnnaBridge 156:ff21514d8981 286 struct
AnnaBridge 156:ff21514d8981 287 {
AnnaBridge 156:ff21514d8981 288 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 156:ff21514d8981 289 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 156:ff21514d8981 290 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 156:ff21514d8981 291 } b; /*!< Structure used for bit access */
AnnaBridge 156:ff21514d8981 292 uint32_t w; /*!< Type used for word access */
AnnaBridge 156:ff21514d8981 293 } CONTROL_Type;
AnnaBridge 156:ff21514d8981 294
AnnaBridge 156:ff21514d8981 295 /* CONTROL Register Definitions */
AnnaBridge 156:ff21514d8981 296 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 156:ff21514d8981 297 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 156:ff21514d8981 298
AnnaBridge 156:ff21514d8981 299 /*@} end of group CMSIS_CORE */
AnnaBridge 156:ff21514d8981 300
AnnaBridge 156:ff21514d8981 301
AnnaBridge 156:ff21514d8981 302 /**
AnnaBridge 156:ff21514d8981 303 \ingroup CMSIS_core_register
AnnaBridge 156:ff21514d8981 304 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 156:ff21514d8981 305 \brief Type definitions for the NVIC Registers
AnnaBridge 156:ff21514d8981 306 @{
AnnaBridge 156:ff21514d8981 307 */
AnnaBridge 156:ff21514d8981 308
AnnaBridge 156:ff21514d8981 309 /**
AnnaBridge 156:ff21514d8981 310 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 156:ff21514d8981 311 */
AnnaBridge 156:ff21514d8981 312 typedef struct
AnnaBridge 156:ff21514d8981 313 {
AnnaBridge 156:ff21514d8981 314 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 156:ff21514d8981 315 uint32_t RESERVED0[31U];
AnnaBridge 156:ff21514d8981 316 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 156:ff21514d8981 317 uint32_t RSERVED1[31U];
AnnaBridge 156:ff21514d8981 318 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 156:ff21514d8981 319 uint32_t RESERVED2[31U];
AnnaBridge 156:ff21514d8981 320 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 156:ff21514d8981 321 uint32_t RESERVED3[31U];
AnnaBridge 156:ff21514d8981 322 uint32_t RESERVED4[64U];
AnnaBridge 156:ff21514d8981 323 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 156:ff21514d8981 324 } NVIC_Type;
AnnaBridge 156:ff21514d8981 325
AnnaBridge 156:ff21514d8981 326 /*@} end of group CMSIS_NVIC */
AnnaBridge 156:ff21514d8981 327
AnnaBridge 156:ff21514d8981 328
AnnaBridge 156:ff21514d8981 329 /**
AnnaBridge 156:ff21514d8981 330 \ingroup CMSIS_core_register
AnnaBridge 156:ff21514d8981 331 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 156:ff21514d8981 332 \brief Type definitions for the System Control Block Registers
AnnaBridge 156:ff21514d8981 333 @{
AnnaBridge 156:ff21514d8981 334 */
AnnaBridge 156:ff21514d8981 335
AnnaBridge 156:ff21514d8981 336 /**
AnnaBridge 156:ff21514d8981 337 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 156:ff21514d8981 338 */
AnnaBridge 156:ff21514d8981 339 typedef struct
AnnaBridge 156:ff21514d8981 340 {
AnnaBridge 156:ff21514d8981 341 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 156:ff21514d8981 342 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 156:ff21514d8981 343 uint32_t RESERVED0;
AnnaBridge 156:ff21514d8981 344 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 156:ff21514d8981 345 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 156:ff21514d8981 346 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 156:ff21514d8981 347 uint32_t RESERVED1;
AnnaBridge 156:ff21514d8981 348 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 156:ff21514d8981 349 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 156:ff21514d8981 350 } SCB_Type;
AnnaBridge 156:ff21514d8981 351
AnnaBridge 156:ff21514d8981 352 /* SCB CPUID Register Definitions */
AnnaBridge 156:ff21514d8981 353 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 156:ff21514d8981 354 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 156:ff21514d8981 355
AnnaBridge 156:ff21514d8981 356 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 156:ff21514d8981 357 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 156:ff21514d8981 358
AnnaBridge 156:ff21514d8981 359 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 156:ff21514d8981 360 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 156:ff21514d8981 361
AnnaBridge 156:ff21514d8981 362 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 156:ff21514d8981 363 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 156:ff21514d8981 364
AnnaBridge 156:ff21514d8981 365 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 156:ff21514d8981 366 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 156:ff21514d8981 367
AnnaBridge 156:ff21514d8981 368 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 156:ff21514d8981 369 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 156:ff21514d8981 370 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 156:ff21514d8981 371
AnnaBridge 156:ff21514d8981 372 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 156:ff21514d8981 373 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 156:ff21514d8981 374
AnnaBridge 156:ff21514d8981 375 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 156:ff21514d8981 376 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 156:ff21514d8981 377
AnnaBridge 156:ff21514d8981 378 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 156:ff21514d8981 379 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 156:ff21514d8981 380
AnnaBridge 156:ff21514d8981 381 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 156:ff21514d8981 382 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 156:ff21514d8981 383
AnnaBridge 156:ff21514d8981 384 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 156:ff21514d8981 385 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 156:ff21514d8981 386
AnnaBridge 156:ff21514d8981 387 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 156:ff21514d8981 388 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 156:ff21514d8981 389
AnnaBridge 156:ff21514d8981 390 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 156:ff21514d8981 391 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 156:ff21514d8981 392
AnnaBridge 156:ff21514d8981 393 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 156:ff21514d8981 394 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 156:ff21514d8981 395
AnnaBridge 156:ff21514d8981 396 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 156:ff21514d8981 397 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 156:ff21514d8981 398 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 156:ff21514d8981 399
AnnaBridge 156:ff21514d8981 400 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 156:ff21514d8981 401 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 156:ff21514d8981 402
AnnaBridge 156:ff21514d8981 403 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 156:ff21514d8981 404 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 156:ff21514d8981 405
AnnaBridge 156:ff21514d8981 406 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 156:ff21514d8981 407 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 156:ff21514d8981 408
AnnaBridge 156:ff21514d8981 409 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 156:ff21514d8981 410 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 156:ff21514d8981 411
AnnaBridge 156:ff21514d8981 412 /* SCB System Control Register Definitions */
AnnaBridge 156:ff21514d8981 413 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 156:ff21514d8981 414 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 156:ff21514d8981 415
AnnaBridge 156:ff21514d8981 416 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 156:ff21514d8981 417 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 156:ff21514d8981 418
AnnaBridge 156:ff21514d8981 419 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 156:ff21514d8981 420 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 156:ff21514d8981 421
AnnaBridge 156:ff21514d8981 422 /* SCB Configuration Control Register Definitions */
AnnaBridge 156:ff21514d8981 423 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 156:ff21514d8981 424 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 156:ff21514d8981 425
AnnaBridge 156:ff21514d8981 426 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 156:ff21514d8981 427 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 156:ff21514d8981 428
AnnaBridge 156:ff21514d8981 429 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 156:ff21514d8981 430 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 156:ff21514d8981 431 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 156:ff21514d8981 432
AnnaBridge 156:ff21514d8981 433 /*@} end of group CMSIS_SCB */
AnnaBridge 156:ff21514d8981 434
AnnaBridge 156:ff21514d8981 435
AnnaBridge 156:ff21514d8981 436 /**
AnnaBridge 156:ff21514d8981 437 \ingroup CMSIS_core_register
AnnaBridge 156:ff21514d8981 438 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 156:ff21514d8981 439 \brief Type definitions for the System Timer Registers.
AnnaBridge 156:ff21514d8981 440 @{
AnnaBridge 156:ff21514d8981 441 */
AnnaBridge 156:ff21514d8981 442
AnnaBridge 156:ff21514d8981 443 /**
AnnaBridge 156:ff21514d8981 444 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 156:ff21514d8981 445 */
AnnaBridge 156:ff21514d8981 446 typedef struct
AnnaBridge 156:ff21514d8981 447 {
AnnaBridge 156:ff21514d8981 448 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 156:ff21514d8981 449 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 156:ff21514d8981 450 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 156:ff21514d8981 451 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 156:ff21514d8981 452 } SysTick_Type;
AnnaBridge 156:ff21514d8981 453
AnnaBridge 156:ff21514d8981 454 /* SysTick Control / Status Register Definitions */
AnnaBridge 156:ff21514d8981 455 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 156:ff21514d8981 456 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 156:ff21514d8981 457
AnnaBridge 156:ff21514d8981 458 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 156:ff21514d8981 459 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 156:ff21514d8981 460
AnnaBridge 156:ff21514d8981 461 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 156:ff21514d8981 462 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 156:ff21514d8981 463
AnnaBridge 156:ff21514d8981 464 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 156:ff21514d8981 465 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 156:ff21514d8981 466
AnnaBridge 156:ff21514d8981 467 /* SysTick Reload Register Definitions */
AnnaBridge 156:ff21514d8981 468 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 156:ff21514d8981 469 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 156:ff21514d8981 470
AnnaBridge 156:ff21514d8981 471 /* SysTick Current Register Definitions */
AnnaBridge 156:ff21514d8981 472 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 156:ff21514d8981 473 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 156:ff21514d8981 474
AnnaBridge 156:ff21514d8981 475 /* SysTick Calibration Register Definitions */
AnnaBridge 156:ff21514d8981 476 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 156:ff21514d8981 477 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 156:ff21514d8981 478
AnnaBridge 156:ff21514d8981 479 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 156:ff21514d8981 480 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 156:ff21514d8981 481
AnnaBridge 156:ff21514d8981 482 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 156:ff21514d8981 483 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 156:ff21514d8981 484
AnnaBridge 156:ff21514d8981 485 /*@} end of group CMSIS_SysTick */
AnnaBridge 156:ff21514d8981 486
AnnaBridge 156:ff21514d8981 487
AnnaBridge 156:ff21514d8981 488 /**
AnnaBridge 156:ff21514d8981 489 \ingroup CMSIS_core_register
AnnaBridge 156:ff21514d8981 490 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 156:ff21514d8981 491 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 156:ff21514d8981 492 Therefore they are not covered by the Cortex-M0 header file.
AnnaBridge 156:ff21514d8981 493 @{
AnnaBridge 156:ff21514d8981 494 */
AnnaBridge 156:ff21514d8981 495 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 156:ff21514d8981 496
AnnaBridge 156:ff21514d8981 497
AnnaBridge 156:ff21514d8981 498 /**
AnnaBridge 156:ff21514d8981 499 \ingroup CMSIS_core_register
AnnaBridge 156:ff21514d8981 500 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 156:ff21514d8981 501 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 156:ff21514d8981 502 @{
AnnaBridge 156:ff21514d8981 503 */
AnnaBridge 156:ff21514d8981 504
AnnaBridge 156:ff21514d8981 505 /**
AnnaBridge 156:ff21514d8981 506 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 156:ff21514d8981 507 \param[in] field Name of the register bit field.
AnnaBridge 156:ff21514d8981 508 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 156:ff21514d8981 509 \return Masked and shifted value.
AnnaBridge 156:ff21514d8981 510 */
AnnaBridge 156:ff21514d8981 511 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 156:ff21514d8981 512
AnnaBridge 156:ff21514d8981 513 /**
AnnaBridge 156:ff21514d8981 514 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 156:ff21514d8981 515 \param[in] field Name of the register bit field.
AnnaBridge 156:ff21514d8981 516 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 156:ff21514d8981 517 \return Masked and shifted bit field value.
AnnaBridge 156:ff21514d8981 518 */
AnnaBridge 156:ff21514d8981 519 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 156:ff21514d8981 520
AnnaBridge 156:ff21514d8981 521 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 156:ff21514d8981 522
AnnaBridge 156:ff21514d8981 523
AnnaBridge 156:ff21514d8981 524 /**
AnnaBridge 156:ff21514d8981 525 \ingroup CMSIS_core_register
AnnaBridge 156:ff21514d8981 526 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 156:ff21514d8981 527 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 156:ff21514d8981 528 @{
AnnaBridge 156:ff21514d8981 529 */
AnnaBridge 156:ff21514d8981 530
AnnaBridge 156:ff21514d8981 531 /* Memory mapping of Core Hardware */
AnnaBridge 156:ff21514d8981 532 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 156:ff21514d8981 533 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 156:ff21514d8981 534 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 156:ff21514d8981 535 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 156:ff21514d8981 536
AnnaBridge 156:ff21514d8981 537 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 156:ff21514d8981 538 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 156:ff21514d8981 539 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 156:ff21514d8981 540
AnnaBridge 156:ff21514d8981 541
AnnaBridge 156:ff21514d8981 542 /*@} */
AnnaBridge 156:ff21514d8981 543
AnnaBridge 156:ff21514d8981 544
AnnaBridge 156:ff21514d8981 545
AnnaBridge 156:ff21514d8981 546 /*******************************************************************************
AnnaBridge 156:ff21514d8981 547 * Hardware Abstraction Layer
AnnaBridge 156:ff21514d8981 548 Core Function Interface contains:
AnnaBridge 156:ff21514d8981 549 - Core NVIC Functions
AnnaBridge 156:ff21514d8981 550 - Core SysTick Functions
AnnaBridge 156:ff21514d8981 551 - Core Register Access Functions
AnnaBridge 156:ff21514d8981 552 ******************************************************************************/
AnnaBridge 156:ff21514d8981 553 /**
AnnaBridge 156:ff21514d8981 554 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 156:ff21514d8981 555 */
AnnaBridge 156:ff21514d8981 556
AnnaBridge 156:ff21514d8981 557
AnnaBridge 156:ff21514d8981 558
AnnaBridge 156:ff21514d8981 559 /* ########################## NVIC functions #################################### */
AnnaBridge 156:ff21514d8981 560 /**
AnnaBridge 156:ff21514d8981 561 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 156:ff21514d8981 562 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 156:ff21514d8981 563 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 156:ff21514d8981 564 @{
AnnaBridge 156:ff21514d8981 565 */
AnnaBridge 156:ff21514d8981 566
AnnaBridge 156:ff21514d8981 567 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 156:ff21514d8981 568 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 156:ff21514d8981 569 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 156:ff21514d8981 570 #endif
AnnaBridge 156:ff21514d8981 571 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 156:ff21514d8981 572 #else
AnnaBridge 156:ff21514d8981 573 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 156:ff21514d8981 574 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 156:ff21514d8981 575 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 156:ff21514d8981 576 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 156:ff21514d8981 577 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 156:ff21514d8981 578 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 156:ff21514d8981 579 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 156:ff21514d8981 580 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 156:ff21514d8981 581 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
AnnaBridge 156:ff21514d8981 582 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 156:ff21514d8981 583 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 156:ff21514d8981 584 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 156:ff21514d8981 585 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 156:ff21514d8981 586
AnnaBridge 156:ff21514d8981 587 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 156:ff21514d8981 588 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 156:ff21514d8981 589 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 156:ff21514d8981 590 #endif
AnnaBridge 156:ff21514d8981 591 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 156:ff21514d8981 592 #else
AnnaBridge 156:ff21514d8981 593 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 156:ff21514d8981 594 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 156:ff21514d8981 595 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 156:ff21514d8981 596
AnnaBridge 156:ff21514d8981 597 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 156:ff21514d8981 598
AnnaBridge 156:ff21514d8981 599
AnnaBridge 156:ff21514d8981 600 /* Interrupt Priorities are WORD accessible only under ARMv6M */
AnnaBridge 156:ff21514d8981 601 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 156:ff21514d8981 602 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 156:ff21514d8981 603 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 156:ff21514d8981 604 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 156:ff21514d8981 605
AnnaBridge 156:ff21514d8981 606
AnnaBridge 156:ff21514d8981 607 /**
AnnaBridge 156:ff21514d8981 608 \brief Enable Interrupt
AnnaBridge 156:ff21514d8981 609 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 156:ff21514d8981 610 \param [in] IRQn Device specific interrupt number.
AnnaBridge 156:ff21514d8981 611 \note IRQn must not be negative.
AnnaBridge 156:ff21514d8981 612 */
AnnaBridge 156:ff21514d8981 613 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 156:ff21514d8981 614 {
AnnaBridge 156:ff21514d8981 615 if ((int32_t)(IRQn) >= 0)
AnnaBridge 156:ff21514d8981 616 {
AnnaBridge 156:ff21514d8981 617 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 156:ff21514d8981 618 }
AnnaBridge 156:ff21514d8981 619 }
AnnaBridge 156:ff21514d8981 620
AnnaBridge 156:ff21514d8981 621
AnnaBridge 156:ff21514d8981 622 /**
AnnaBridge 156:ff21514d8981 623 \brief Get Interrupt Enable status
AnnaBridge 156:ff21514d8981 624 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 156:ff21514d8981 625 \param [in] IRQn Device specific interrupt number.
AnnaBridge 156:ff21514d8981 626 \return 0 Interrupt is not enabled.
AnnaBridge 156:ff21514d8981 627 \return 1 Interrupt is enabled.
AnnaBridge 156:ff21514d8981 628 \note IRQn must not be negative.
AnnaBridge 156:ff21514d8981 629 */
AnnaBridge 156:ff21514d8981 630 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 156:ff21514d8981 631 {
AnnaBridge 156:ff21514d8981 632 if ((int32_t)(IRQn) >= 0)
AnnaBridge 156:ff21514d8981 633 {
AnnaBridge 156:ff21514d8981 634 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 156:ff21514d8981 635 }
AnnaBridge 156:ff21514d8981 636 else
AnnaBridge 156:ff21514d8981 637 {
AnnaBridge 156:ff21514d8981 638 return(0U);
AnnaBridge 156:ff21514d8981 639 }
AnnaBridge 156:ff21514d8981 640 }
AnnaBridge 156:ff21514d8981 641
AnnaBridge 156:ff21514d8981 642
AnnaBridge 156:ff21514d8981 643 /**
AnnaBridge 156:ff21514d8981 644 \brief Disable Interrupt
AnnaBridge 156:ff21514d8981 645 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 156:ff21514d8981 646 \param [in] IRQn Device specific interrupt number.
AnnaBridge 156:ff21514d8981 647 \note IRQn must not be negative.
AnnaBridge 156:ff21514d8981 648 */
AnnaBridge 156:ff21514d8981 649 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 156:ff21514d8981 650 {
AnnaBridge 156:ff21514d8981 651 if ((int32_t)(IRQn) >= 0)
AnnaBridge 156:ff21514d8981 652 {
AnnaBridge 156:ff21514d8981 653 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 156:ff21514d8981 654 __DSB();
AnnaBridge 156:ff21514d8981 655 __ISB();
AnnaBridge 156:ff21514d8981 656 }
AnnaBridge 156:ff21514d8981 657 }
AnnaBridge 156:ff21514d8981 658
AnnaBridge 156:ff21514d8981 659
AnnaBridge 156:ff21514d8981 660 /**
AnnaBridge 156:ff21514d8981 661 \brief Get Pending Interrupt
AnnaBridge 156:ff21514d8981 662 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 156:ff21514d8981 663 \param [in] IRQn Device specific interrupt number.
AnnaBridge 156:ff21514d8981 664 \return 0 Interrupt status is not pending.
AnnaBridge 156:ff21514d8981 665 \return 1 Interrupt status is pending.
AnnaBridge 156:ff21514d8981 666 \note IRQn must not be negative.
AnnaBridge 156:ff21514d8981 667 */
AnnaBridge 156:ff21514d8981 668 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 156:ff21514d8981 669 {
AnnaBridge 156:ff21514d8981 670 if ((int32_t)(IRQn) >= 0)
AnnaBridge 156:ff21514d8981 671 {
AnnaBridge 156:ff21514d8981 672 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 156:ff21514d8981 673 }
AnnaBridge 156:ff21514d8981 674 else
AnnaBridge 156:ff21514d8981 675 {
AnnaBridge 156:ff21514d8981 676 return(0U);
AnnaBridge 156:ff21514d8981 677 }
AnnaBridge 156:ff21514d8981 678 }
AnnaBridge 156:ff21514d8981 679
AnnaBridge 156:ff21514d8981 680
AnnaBridge 156:ff21514d8981 681 /**
AnnaBridge 156:ff21514d8981 682 \brief Set Pending Interrupt
AnnaBridge 156:ff21514d8981 683 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 156:ff21514d8981 684 \param [in] IRQn Device specific interrupt number.
AnnaBridge 156:ff21514d8981 685 \note IRQn must not be negative.
AnnaBridge 156:ff21514d8981 686 */
AnnaBridge 156:ff21514d8981 687 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 156:ff21514d8981 688 {
AnnaBridge 156:ff21514d8981 689 if ((int32_t)(IRQn) >= 0)
AnnaBridge 156:ff21514d8981 690 {
AnnaBridge 156:ff21514d8981 691 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 156:ff21514d8981 692 }
AnnaBridge 156:ff21514d8981 693 }
AnnaBridge 156:ff21514d8981 694
AnnaBridge 156:ff21514d8981 695
AnnaBridge 156:ff21514d8981 696 /**
AnnaBridge 156:ff21514d8981 697 \brief Clear Pending Interrupt
AnnaBridge 156:ff21514d8981 698 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 156:ff21514d8981 699 \param [in] IRQn Device specific interrupt number.
AnnaBridge 156:ff21514d8981 700 \note IRQn must not be negative.
AnnaBridge 156:ff21514d8981 701 */
AnnaBridge 156:ff21514d8981 702 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 156:ff21514d8981 703 {
AnnaBridge 156:ff21514d8981 704 if ((int32_t)(IRQn) >= 0)
AnnaBridge 156:ff21514d8981 705 {
AnnaBridge 156:ff21514d8981 706 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 156:ff21514d8981 707 }
AnnaBridge 156:ff21514d8981 708 }
AnnaBridge 156:ff21514d8981 709
AnnaBridge 156:ff21514d8981 710
AnnaBridge 156:ff21514d8981 711 /**
AnnaBridge 156:ff21514d8981 712 \brief Set Interrupt Priority
AnnaBridge 156:ff21514d8981 713 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 156:ff21514d8981 714 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 156:ff21514d8981 715 or negative to specify a processor exception.
AnnaBridge 156:ff21514d8981 716 \param [in] IRQn Interrupt number.
AnnaBridge 156:ff21514d8981 717 \param [in] priority Priority to set.
AnnaBridge 156:ff21514d8981 718 \note The priority cannot be set for every processor exception.
AnnaBridge 156:ff21514d8981 719 */
AnnaBridge 156:ff21514d8981 720 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 156:ff21514d8981 721 {
AnnaBridge 156:ff21514d8981 722 if ((int32_t)(IRQn) >= 0)
AnnaBridge 156:ff21514d8981 723 {
AnnaBridge 156:ff21514d8981 724 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 156:ff21514d8981 725 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 156:ff21514d8981 726 }
AnnaBridge 156:ff21514d8981 727 else
AnnaBridge 156:ff21514d8981 728 {
AnnaBridge 156:ff21514d8981 729 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 156:ff21514d8981 730 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 156:ff21514d8981 731 }
AnnaBridge 156:ff21514d8981 732 }
AnnaBridge 156:ff21514d8981 733
AnnaBridge 156:ff21514d8981 734
AnnaBridge 156:ff21514d8981 735 /**
AnnaBridge 156:ff21514d8981 736 \brief Get Interrupt Priority
AnnaBridge 156:ff21514d8981 737 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 156:ff21514d8981 738 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 156:ff21514d8981 739 or negative to specify a processor exception.
AnnaBridge 156:ff21514d8981 740 \param [in] IRQn Interrupt number.
AnnaBridge 156:ff21514d8981 741 \return Interrupt Priority.
AnnaBridge 156:ff21514d8981 742 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 156:ff21514d8981 743 */
AnnaBridge 156:ff21514d8981 744 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 156:ff21514d8981 745 {
AnnaBridge 156:ff21514d8981 746
AnnaBridge 156:ff21514d8981 747 if ((int32_t)(IRQn) >= 0)
AnnaBridge 156:ff21514d8981 748 {
AnnaBridge 156:ff21514d8981 749 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 156:ff21514d8981 750 }
AnnaBridge 156:ff21514d8981 751 else
AnnaBridge 156:ff21514d8981 752 {
AnnaBridge 156:ff21514d8981 753 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 156:ff21514d8981 754 }
AnnaBridge 156:ff21514d8981 755 }
AnnaBridge 156:ff21514d8981 756
AnnaBridge 156:ff21514d8981 757
AnnaBridge 156:ff21514d8981 758 /**
AnnaBridge 156:ff21514d8981 759 \brief Set Interrupt Vector
AnnaBridge 156:ff21514d8981 760 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 156:ff21514d8981 761 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 156:ff21514d8981 762 or negative to specify a processor exception.
AnnaBridge 156:ff21514d8981 763 Address 0 must be mapped to SRAM.
AnnaBridge 156:ff21514d8981 764 \param [in] IRQn Interrupt number
AnnaBridge 156:ff21514d8981 765 \param [in] vector Address of interrupt handler function
AnnaBridge 156:ff21514d8981 766 */
AnnaBridge 156:ff21514d8981 767 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 156:ff21514d8981 768 {
AnnaBridge 156:ff21514d8981 769 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 156:ff21514d8981 770 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 156:ff21514d8981 771 }
AnnaBridge 156:ff21514d8981 772
AnnaBridge 156:ff21514d8981 773
AnnaBridge 156:ff21514d8981 774 /**
AnnaBridge 156:ff21514d8981 775 \brief Get Interrupt Vector
AnnaBridge 156:ff21514d8981 776 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 156:ff21514d8981 777 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 156:ff21514d8981 778 or negative to specify a processor exception.
AnnaBridge 156:ff21514d8981 779 \param [in] IRQn Interrupt number.
AnnaBridge 156:ff21514d8981 780 \return Address of interrupt handler function
AnnaBridge 156:ff21514d8981 781 */
AnnaBridge 156:ff21514d8981 782 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 156:ff21514d8981 783 {
AnnaBridge 156:ff21514d8981 784 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 156:ff21514d8981 785 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 156:ff21514d8981 786 }
AnnaBridge 156:ff21514d8981 787
AnnaBridge 156:ff21514d8981 788
AnnaBridge 156:ff21514d8981 789 /**
AnnaBridge 156:ff21514d8981 790 \brief System Reset
AnnaBridge 156:ff21514d8981 791 \details Initiates a system reset request to reset the MCU.
AnnaBridge 156:ff21514d8981 792 */
AnnaBridge 156:ff21514d8981 793 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 156:ff21514d8981 794 {
AnnaBridge 156:ff21514d8981 795 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 156:ff21514d8981 796 buffered write are completed before reset */
AnnaBridge 156:ff21514d8981 797 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 156:ff21514d8981 798 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 156:ff21514d8981 799 __DSB(); /* Ensure completion of memory access */
AnnaBridge 156:ff21514d8981 800
AnnaBridge 156:ff21514d8981 801 for(;;) /* wait until reset */
AnnaBridge 156:ff21514d8981 802 {
AnnaBridge 156:ff21514d8981 803 __NOP();
AnnaBridge 156:ff21514d8981 804 }
AnnaBridge 156:ff21514d8981 805 }
AnnaBridge 156:ff21514d8981 806
AnnaBridge 156:ff21514d8981 807 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 156:ff21514d8981 808
AnnaBridge 156:ff21514d8981 809
AnnaBridge 156:ff21514d8981 810 /* ########################## FPU functions #################################### */
AnnaBridge 156:ff21514d8981 811 /**
AnnaBridge 156:ff21514d8981 812 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 156:ff21514d8981 813 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 156:ff21514d8981 814 \brief Function that provides FPU type.
AnnaBridge 156:ff21514d8981 815 @{
AnnaBridge 156:ff21514d8981 816 */
AnnaBridge 156:ff21514d8981 817
AnnaBridge 156:ff21514d8981 818 /**
AnnaBridge 156:ff21514d8981 819 \brief get FPU type
AnnaBridge 156:ff21514d8981 820 \details returns the FPU type
AnnaBridge 156:ff21514d8981 821 \returns
AnnaBridge 156:ff21514d8981 822 - \b 0: No FPU
AnnaBridge 156:ff21514d8981 823 - \b 1: Single precision FPU
AnnaBridge 156:ff21514d8981 824 - \b 2: Double + Single precision FPU
AnnaBridge 156:ff21514d8981 825 */
AnnaBridge 156:ff21514d8981 826 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 156:ff21514d8981 827 {
AnnaBridge 156:ff21514d8981 828 return 0U; /* No FPU */
AnnaBridge 156:ff21514d8981 829 }
AnnaBridge 156:ff21514d8981 830
AnnaBridge 156:ff21514d8981 831
AnnaBridge 156:ff21514d8981 832 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 156:ff21514d8981 833
AnnaBridge 156:ff21514d8981 834
AnnaBridge 156:ff21514d8981 835
AnnaBridge 156:ff21514d8981 836 /* ################################## SysTick function ############################################ */
AnnaBridge 156:ff21514d8981 837 /**
AnnaBridge 156:ff21514d8981 838 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 156:ff21514d8981 839 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 156:ff21514d8981 840 \brief Functions that configure the System.
AnnaBridge 156:ff21514d8981 841 @{
AnnaBridge 156:ff21514d8981 842 */
AnnaBridge 156:ff21514d8981 843
AnnaBridge 156:ff21514d8981 844 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 156:ff21514d8981 845
AnnaBridge 156:ff21514d8981 846 /**
AnnaBridge 156:ff21514d8981 847 \brief System Tick Configuration
AnnaBridge 156:ff21514d8981 848 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 156:ff21514d8981 849 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 156:ff21514d8981 850 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 156:ff21514d8981 851 \return 0 Function succeeded.
AnnaBridge 156:ff21514d8981 852 \return 1 Function failed.
AnnaBridge 156:ff21514d8981 853 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 156:ff21514d8981 854 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 156:ff21514d8981 855 must contain a vendor-specific implementation of this function.
AnnaBridge 156:ff21514d8981 856 */
AnnaBridge 156:ff21514d8981 857 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 156:ff21514d8981 858 {
AnnaBridge 156:ff21514d8981 859 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 156:ff21514d8981 860 {
AnnaBridge 156:ff21514d8981 861 return (1UL); /* Reload value impossible */
AnnaBridge 156:ff21514d8981 862 }
AnnaBridge 156:ff21514d8981 863
AnnaBridge 156:ff21514d8981 864 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 156:ff21514d8981 865 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 156:ff21514d8981 866 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 156:ff21514d8981 867 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 156:ff21514d8981 868 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 156:ff21514d8981 869 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 156:ff21514d8981 870 return (0UL); /* Function successful */
AnnaBridge 156:ff21514d8981 871 }
AnnaBridge 156:ff21514d8981 872
AnnaBridge 156:ff21514d8981 873 #endif
AnnaBridge 156:ff21514d8981 874
AnnaBridge 156:ff21514d8981 875 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 156:ff21514d8981 876
AnnaBridge 156:ff21514d8981 877
AnnaBridge 156:ff21514d8981 878
AnnaBridge 156:ff21514d8981 879
AnnaBridge 156:ff21514d8981 880 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 881 }
AnnaBridge 156:ff21514d8981 882 #endif
AnnaBridge 156:ff21514d8981 883
AnnaBridge 156:ff21514d8981 884 #endif /* __CORE_CM0_H_DEPENDANT */
AnnaBridge 156:ff21514d8981 885
AnnaBridge 156:ff21514d8981 886 #endif /* __CMSIS_GENERIC */