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mbed 2

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TARGET_RZ_A1H/core_cm4_simd.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
92:4fc01daae5a5 
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**************************************************************************//**
bogdanm 92:4fc01daae5a5 2 * @file core_cm4_simd.h
bogdanm 92:4fc01daae5a5 3 * @brief CMSIS Cortex-M4 SIMD Header File
bogdanm 92:4fc01daae5a5 4 * @version V3.20
bogdanm 92:4fc01daae5a5 5 * @date 25. February 2013
bogdanm 92:4fc01daae5a5 6 *
bogdanm 92:4fc01daae5a5 7 * @note
bogdanm 92:4fc01daae5a5 8 *
bogdanm 92:4fc01daae5a5 9 ******************************************************************************/
bogdanm 92:4fc01daae5a5 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 92:4fc01daae5a5 11
bogdanm 92:4fc01daae5a5 12 All rights reserved.
bogdanm 92:4fc01daae5a5 13 Redistribution and use in source and binary forms, with or without
bogdanm 92:4fc01daae5a5 14 modification, are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 - Redistributions of source code must retain the above copyright
bogdanm 92:4fc01daae5a5 16 notice, this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 92:4fc01daae5a5 18 notice, this list of conditions and the following disclaimer in the
bogdanm 92:4fc01daae5a5 19 documentation and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 92:4fc01daae5a5 21 to endorse or promote products derived from this software without
bogdanm 92:4fc01daae5a5 22 specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 92:4fc01daae5a5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 92:4fc01daae5a5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 92:4fc01daae5a5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 92:4fc01daae5a5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 92:4fc01daae5a5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 92:4fc01daae5a5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 92:4fc01daae5a5 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 35 ---------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 36
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 39 extern "C" {
bogdanm 92:4fc01daae5a5 40 #endif
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifndef __CORE_CM4_SIMD_H
bogdanm 92:4fc01daae5a5 43 #define __CORE_CM4_SIMD_H
bogdanm 92:4fc01daae5a5 44
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /*******************************************************************************
bogdanm 92:4fc01daae5a5 47 * Hardware Abstraction Layer
bogdanm 92:4fc01daae5a5 48 ******************************************************************************/
bogdanm 92:4fc01daae5a5 49
bogdanm 92:4fc01daae5a5 50
bogdanm 92:4fc01daae5a5 51 /* ################### Compiler specific Intrinsics ########################### */
bogdanm 92:4fc01daae5a5 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
bogdanm 92:4fc01daae5a5 53 Access to dedicated SIMD instructions
bogdanm 92:4fc01daae5a5 54 @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
bogdanm 92:4fc01daae5a5 58 /* ARM armcc specific functions */
bogdanm 92:4fc01daae5a5 59
bogdanm 92:4fc01daae5a5 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 92:4fc01daae5a5 61 #define __SADD8 __sadd8
bogdanm 92:4fc01daae5a5 62 #define __QADD8 __qadd8
bogdanm 92:4fc01daae5a5 63 #define __SHADD8 __shadd8
bogdanm 92:4fc01daae5a5 64 #define __UADD8 __uadd8
bogdanm 92:4fc01daae5a5 65 #define __UQADD8 __uqadd8
bogdanm 92:4fc01daae5a5 66 #define __UHADD8 __uhadd8
bogdanm 92:4fc01daae5a5 67 #define __SSUB8 __ssub8
bogdanm 92:4fc01daae5a5 68 #define __QSUB8 __qsub8
bogdanm 92:4fc01daae5a5 69 #define __SHSUB8 __shsub8
bogdanm 92:4fc01daae5a5 70 #define __USUB8 __usub8
bogdanm 92:4fc01daae5a5 71 #define __UQSUB8 __uqsub8
bogdanm 92:4fc01daae5a5 72 #define __UHSUB8 __uhsub8
bogdanm 92:4fc01daae5a5 73 #define __SADD16 __sadd16
bogdanm 92:4fc01daae5a5 74 #define __QADD16 __qadd16
bogdanm 92:4fc01daae5a5 75 #define __SHADD16 __shadd16
bogdanm 92:4fc01daae5a5 76 #define __UADD16 __uadd16
bogdanm 92:4fc01daae5a5 77 #define __UQADD16 __uqadd16
bogdanm 92:4fc01daae5a5 78 #define __UHADD16 __uhadd16
bogdanm 92:4fc01daae5a5 79 #define __SSUB16 __ssub16
bogdanm 92:4fc01daae5a5 80 #define __QSUB16 __qsub16
bogdanm 92:4fc01daae5a5 81 #define __SHSUB16 __shsub16
bogdanm 92:4fc01daae5a5 82 #define __USUB16 __usub16
bogdanm 92:4fc01daae5a5 83 #define __UQSUB16 __uqsub16
bogdanm 92:4fc01daae5a5 84 #define __UHSUB16 __uhsub16
bogdanm 92:4fc01daae5a5 85 #define __SASX __sasx
bogdanm 92:4fc01daae5a5 86 #define __QASX __qasx
bogdanm 92:4fc01daae5a5 87 #define __SHASX __shasx
bogdanm 92:4fc01daae5a5 88 #define __UASX __uasx
bogdanm 92:4fc01daae5a5 89 #define __UQASX __uqasx
bogdanm 92:4fc01daae5a5 90 #define __UHASX __uhasx
bogdanm 92:4fc01daae5a5 91 #define __SSAX __ssax
bogdanm 92:4fc01daae5a5 92 #define __QSAX __qsax
bogdanm 92:4fc01daae5a5 93 #define __SHSAX __shsax
bogdanm 92:4fc01daae5a5 94 #define __USAX __usax
bogdanm 92:4fc01daae5a5 95 #define __UQSAX __uqsax
bogdanm 92:4fc01daae5a5 96 #define __UHSAX __uhsax
bogdanm 92:4fc01daae5a5 97 #define __USAD8 __usad8
bogdanm 92:4fc01daae5a5 98 #define __USADA8 __usada8
bogdanm 92:4fc01daae5a5 99 #define __SSAT16 __ssat16
bogdanm 92:4fc01daae5a5 100 #define __USAT16 __usat16
bogdanm 92:4fc01daae5a5 101 #define __UXTB16 __uxtb16
bogdanm 92:4fc01daae5a5 102 #define __UXTAB16 __uxtab16
bogdanm 92:4fc01daae5a5 103 #define __SXTB16 __sxtb16
bogdanm 92:4fc01daae5a5 104 #define __SXTAB16 __sxtab16
bogdanm 92:4fc01daae5a5 105 #define __SMUAD __smuad
bogdanm 92:4fc01daae5a5 106 #define __SMUADX __smuadx
bogdanm 92:4fc01daae5a5 107 #define __SMLAD __smlad
bogdanm 92:4fc01daae5a5 108 #define __SMLADX __smladx
bogdanm 92:4fc01daae5a5 109 #define __SMLALD __smlald
bogdanm 92:4fc01daae5a5 110 #define __SMLALDX __smlaldx
bogdanm 92:4fc01daae5a5 111 #define __SMUSD __smusd
bogdanm 92:4fc01daae5a5 112 #define __SMUSDX __smusdx
bogdanm 92:4fc01daae5a5 113 #define __SMLSD __smlsd
bogdanm 92:4fc01daae5a5 114 #define __SMLSDX __smlsdx
bogdanm 92:4fc01daae5a5 115 #define __SMLSLD __smlsld
bogdanm 92:4fc01daae5a5 116 #define __SMLSLDX __smlsldx
bogdanm 92:4fc01daae5a5 117 #define __SEL __sel
bogdanm 92:4fc01daae5a5 118 #define __QADD __qadd
bogdanm 92:4fc01daae5a5 119 #define __QSUB __qsub
bogdanm 92:4fc01daae5a5 120
bogdanm 92:4fc01daae5a5 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
bogdanm 92:4fc01daae5a5 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
bogdanm 92:4fc01daae5a5 123
bogdanm 92:4fc01daae5a5 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
bogdanm 92:4fc01daae5a5 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
bogdanm 92:4fc01daae5a5 126
bogdanm 92:4fc01daae5a5 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
bogdanm 92:4fc01daae5a5 128 ((int64_t)(ARG3) << 32) ) >> 32))
bogdanm 92:4fc01daae5a5 129
bogdanm 92:4fc01daae5a5 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 92:4fc01daae5a5 131
bogdanm 92:4fc01daae5a5 132
bogdanm 92:4fc01daae5a5 133
bogdanm 92:4fc01daae5a5 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
bogdanm 92:4fc01daae5a5 135 /* IAR iccarm specific functions */
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 92:4fc01daae5a5 138 #include <cmsis_iar.h>
bogdanm 92:4fc01daae5a5 139
bogdanm 92:4fc01daae5a5 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 92:4fc01daae5a5 141
bogdanm 92:4fc01daae5a5 142
bogdanm 92:4fc01daae5a5 143
bogdanm 92:4fc01daae5a5 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
bogdanm 92:4fc01daae5a5 145 /* TI CCS specific functions */
bogdanm 92:4fc01daae5a5 146
bogdanm 92:4fc01daae5a5 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 92:4fc01daae5a5 148 #include <cmsis_ccs.h>
bogdanm 92:4fc01daae5a5 149
bogdanm 92:4fc01daae5a5 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 92:4fc01daae5a5 151
bogdanm 92:4fc01daae5a5 152
bogdanm 92:4fc01daae5a5 153
bogdanm 92:4fc01daae5a5 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
bogdanm 92:4fc01daae5a5 155 /* GNU gcc specific functions */
bogdanm 92:4fc01daae5a5 156
bogdanm 92:4fc01daae5a5 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 92:4fc01daae5a5 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 159 {
bogdanm 92:4fc01daae5a5 160 uint32_t result;
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 163 return(result);
bogdanm 92:4fc01daae5a5 164 }
bogdanm 92:4fc01daae5a5 165
bogdanm 92:4fc01daae5a5 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 167 {
bogdanm 92:4fc01daae5a5 168 uint32_t result;
bogdanm 92:4fc01daae5a5 169
bogdanm 92:4fc01daae5a5 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 171 return(result);
bogdanm 92:4fc01daae5a5 172 }
bogdanm 92:4fc01daae5a5 173
bogdanm 92:4fc01daae5a5 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 175 {
bogdanm 92:4fc01daae5a5 176 uint32_t result;
bogdanm 92:4fc01daae5a5 177
bogdanm 92:4fc01daae5a5 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 179 return(result);
bogdanm 92:4fc01daae5a5 180 }
bogdanm 92:4fc01daae5a5 181
bogdanm 92:4fc01daae5a5 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 183 {
bogdanm 92:4fc01daae5a5 184 uint32_t result;
bogdanm 92:4fc01daae5a5 185
bogdanm 92:4fc01daae5a5 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 187 return(result);
bogdanm 92:4fc01daae5a5 188 }
bogdanm 92:4fc01daae5a5 189
bogdanm 92:4fc01daae5a5 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 191 {
bogdanm 92:4fc01daae5a5 192 uint32_t result;
bogdanm 92:4fc01daae5a5 193
bogdanm 92:4fc01daae5a5 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 195 return(result);
bogdanm 92:4fc01daae5a5 196 }
bogdanm 92:4fc01daae5a5 197
bogdanm 92:4fc01daae5a5 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 199 {
bogdanm 92:4fc01daae5a5 200 uint32_t result;
bogdanm 92:4fc01daae5a5 201
bogdanm 92:4fc01daae5a5 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 203 return(result);
bogdanm 92:4fc01daae5a5 204 }
bogdanm 92:4fc01daae5a5 205
bogdanm 92:4fc01daae5a5 206
bogdanm 92:4fc01daae5a5 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 208 {
bogdanm 92:4fc01daae5a5 209 uint32_t result;
bogdanm 92:4fc01daae5a5 210
bogdanm 92:4fc01daae5a5 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 212 return(result);
bogdanm 92:4fc01daae5a5 213 }
bogdanm 92:4fc01daae5a5 214
bogdanm 92:4fc01daae5a5 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 216 {
bogdanm 92:4fc01daae5a5 217 uint32_t result;
bogdanm 92:4fc01daae5a5 218
bogdanm 92:4fc01daae5a5 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 220 return(result);
bogdanm 92:4fc01daae5a5 221 }
bogdanm 92:4fc01daae5a5 222
bogdanm 92:4fc01daae5a5 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 224 {
bogdanm 92:4fc01daae5a5 225 uint32_t result;
bogdanm 92:4fc01daae5a5 226
bogdanm 92:4fc01daae5a5 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 228 return(result);
bogdanm 92:4fc01daae5a5 229 }
bogdanm 92:4fc01daae5a5 230
bogdanm 92:4fc01daae5a5 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 232 {
bogdanm 92:4fc01daae5a5 233 uint32_t result;
bogdanm 92:4fc01daae5a5 234
bogdanm 92:4fc01daae5a5 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 236 return(result);
bogdanm 92:4fc01daae5a5 237 }
bogdanm 92:4fc01daae5a5 238
bogdanm 92:4fc01daae5a5 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 240 {
bogdanm 92:4fc01daae5a5 241 uint32_t result;
bogdanm 92:4fc01daae5a5 242
bogdanm 92:4fc01daae5a5 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 244 return(result);
bogdanm 92:4fc01daae5a5 245 }
bogdanm 92:4fc01daae5a5 246
bogdanm 92:4fc01daae5a5 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 248 {
bogdanm 92:4fc01daae5a5 249 uint32_t result;
bogdanm 92:4fc01daae5a5 250
bogdanm 92:4fc01daae5a5 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 252 return(result);
bogdanm 92:4fc01daae5a5 253 }
bogdanm 92:4fc01daae5a5 254
bogdanm 92:4fc01daae5a5 255
bogdanm 92:4fc01daae5a5 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 257 {
bogdanm 92:4fc01daae5a5 258 uint32_t result;
bogdanm 92:4fc01daae5a5 259
bogdanm 92:4fc01daae5a5 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 261 return(result);
bogdanm 92:4fc01daae5a5 262 }
bogdanm 92:4fc01daae5a5 263
bogdanm 92:4fc01daae5a5 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 265 {
bogdanm 92:4fc01daae5a5 266 uint32_t result;
bogdanm 92:4fc01daae5a5 267
bogdanm 92:4fc01daae5a5 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 269 return(result);
bogdanm 92:4fc01daae5a5 270 }
bogdanm 92:4fc01daae5a5 271
bogdanm 92:4fc01daae5a5 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 273 {
bogdanm 92:4fc01daae5a5 274 uint32_t result;
bogdanm 92:4fc01daae5a5 275
bogdanm 92:4fc01daae5a5 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 277 return(result);
bogdanm 92:4fc01daae5a5 278 }
bogdanm 92:4fc01daae5a5 279
bogdanm 92:4fc01daae5a5 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 281 {
bogdanm 92:4fc01daae5a5 282 uint32_t result;
bogdanm 92:4fc01daae5a5 283
bogdanm 92:4fc01daae5a5 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 285 return(result);
bogdanm 92:4fc01daae5a5 286 }
bogdanm 92:4fc01daae5a5 287
bogdanm 92:4fc01daae5a5 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 289 {
bogdanm 92:4fc01daae5a5 290 uint32_t result;
bogdanm 92:4fc01daae5a5 291
bogdanm 92:4fc01daae5a5 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 293 return(result);
bogdanm 92:4fc01daae5a5 294 }
bogdanm 92:4fc01daae5a5 295
bogdanm 92:4fc01daae5a5 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 297 {
bogdanm 92:4fc01daae5a5 298 uint32_t result;
bogdanm 92:4fc01daae5a5 299
bogdanm 92:4fc01daae5a5 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 301 return(result);
bogdanm 92:4fc01daae5a5 302 }
bogdanm 92:4fc01daae5a5 303
bogdanm 92:4fc01daae5a5 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 305 {
bogdanm 92:4fc01daae5a5 306 uint32_t result;
bogdanm 92:4fc01daae5a5 307
bogdanm 92:4fc01daae5a5 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 309 return(result);
bogdanm 92:4fc01daae5a5 310 }
bogdanm 92:4fc01daae5a5 311
bogdanm 92:4fc01daae5a5 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 313 {
bogdanm 92:4fc01daae5a5 314 uint32_t result;
bogdanm 92:4fc01daae5a5 315
bogdanm 92:4fc01daae5a5 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 317 return(result);
bogdanm 92:4fc01daae5a5 318 }
bogdanm 92:4fc01daae5a5 319
bogdanm 92:4fc01daae5a5 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 321 {
bogdanm 92:4fc01daae5a5 322 uint32_t result;
bogdanm 92:4fc01daae5a5 323
bogdanm 92:4fc01daae5a5 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 325 return(result);
bogdanm 92:4fc01daae5a5 326 }
bogdanm 92:4fc01daae5a5 327
bogdanm 92:4fc01daae5a5 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 329 {
bogdanm 92:4fc01daae5a5 330 uint32_t result;
bogdanm 92:4fc01daae5a5 331
bogdanm 92:4fc01daae5a5 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 333 return(result);
bogdanm 92:4fc01daae5a5 334 }
bogdanm 92:4fc01daae5a5 335
bogdanm 92:4fc01daae5a5 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 337 {
bogdanm 92:4fc01daae5a5 338 uint32_t result;
bogdanm 92:4fc01daae5a5 339
bogdanm 92:4fc01daae5a5 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 341 return(result);
bogdanm 92:4fc01daae5a5 342 }
bogdanm 92:4fc01daae5a5 343
bogdanm 92:4fc01daae5a5 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 345 {
bogdanm 92:4fc01daae5a5 346 uint32_t result;
bogdanm 92:4fc01daae5a5 347
bogdanm 92:4fc01daae5a5 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 349 return(result);
bogdanm 92:4fc01daae5a5 350 }
bogdanm 92:4fc01daae5a5 351
bogdanm 92:4fc01daae5a5 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 353 {
bogdanm 92:4fc01daae5a5 354 uint32_t result;
bogdanm 92:4fc01daae5a5 355
bogdanm 92:4fc01daae5a5 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 357 return(result);
bogdanm 92:4fc01daae5a5 358 }
bogdanm 92:4fc01daae5a5 359
bogdanm 92:4fc01daae5a5 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 361 {
bogdanm 92:4fc01daae5a5 362 uint32_t result;
bogdanm 92:4fc01daae5a5 363
bogdanm 92:4fc01daae5a5 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 365 return(result);
bogdanm 92:4fc01daae5a5 366 }
bogdanm 92:4fc01daae5a5 367
bogdanm 92:4fc01daae5a5 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 369 {
bogdanm 92:4fc01daae5a5 370 uint32_t result;
bogdanm 92:4fc01daae5a5 371
bogdanm 92:4fc01daae5a5 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 373 return(result);
bogdanm 92:4fc01daae5a5 374 }
bogdanm 92:4fc01daae5a5 375
bogdanm 92:4fc01daae5a5 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 377 {
bogdanm 92:4fc01daae5a5 378 uint32_t result;
bogdanm 92:4fc01daae5a5 379
bogdanm 92:4fc01daae5a5 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 381 return(result);
bogdanm 92:4fc01daae5a5 382 }
bogdanm 92:4fc01daae5a5 383
bogdanm 92:4fc01daae5a5 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 385 {
bogdanm 92:4fc01daae5a5 386 uint32_t result;
bogdanm 92:4fc01daae5a5 387
bogdanm 92:4fc01daae5a5 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 389 return(result);
bogdanm 92:4fc01daae5a5 390 }
bogdanm 92:4fc01daae5a5 391
bogdanm 92:4fc01daae5a5 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 393 {
bogdanm 92:4fc01daae5a5 394 uint32_t result;
bogdanm 92:4fc01daae5a5 395
bogdanm 92:4fc01daae5a5 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 397 return(result);
bogdanm 92:4fc01daae5a5 398 }
bogdanm 92:4fc01daae5a5 399
bogdanm 92:4fc01daae5a5 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 401 {
bogdanm 92:4fc01daae5a5 402 uint32_t result;
bogdanm 92:4fc01daae5a5 403
bogdanm 92:4fc01daae5a5 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 405 return(result);
bogdanm 92:4fc01daae5a5 406 }
bogdanm 92:4fc01daae5a5 407
bogdanm 92:4fc01daae5a5 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 409 {
bogdanm 92:4fc01daae5a5 410 uint32_t result;
bogdanm 92:4fc01daae5a5 411
bogdanm 92:4fc01daae5a5 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 413 return(result);
bogdanm 92:4fc01daae5a5 414 }
bogdanm 92:4fc01daae5a5 415
bogdanm 92:4fc01daae5a5 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 417 {
bogdanm 92:4fc01daae5a5 418 uint32_t result;
bogdanm 92:4fc01daae5a5 419
bogdanm 92:4fc01daae5a5 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 421 return(result);
bogdanm 92:4fc01daae5a5 422 }
bogdanm 92:4fc01daae5a5 423
bogdanm 92:4fc01daae5a5 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 425 {
bogdanm 92:4fc01daae5a5 426 uint32_t result;
bogdanm 92:4fc01daae5a5 427
bogdanm 92:4fc01daae5a5 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 429 return(result);
bogdanm 92:4fc01daae5a5 430 }
bogdanm 92:4fc01daae5a5 431
bogdanm 92:4fc01daae5a5 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 433 {
bogdanm 92:4fc01daae5a5 434 uint32_t result;
bogdanm 92:4fc01daae5a5 435
bogdanm 92:4fc01daae5a5 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 437 return(result);
bogdanm 92:4fc01daae5a5 438 }
bogdanm 92:4fc01daae5a5 439
bogdanm 92:4fc01daae5a5 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 441 {
bogdanm 92:4fc01daae5a5 442 uint32_t result;
bogdanm 92:4fc01daae5a5 443
bogdanm 92:4fc01daae5a5 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 445 return(result);
bogdanm 92:4fc01daae5a5 446 }
bogdanm 92:4fc01daae5a5 447
bogdanm 92:4fc01daae5a5 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 449 {
bogdanm 92:4fc01daae5a5 450 uint32_t result;
bogdanm 92:4fc01daae5a5 451
bogdanm 92:4fc01daae5a5 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 453 return(result);
bogdanm 92:4fc01daae5a5 454 }
bogdanm 92:4fc01daae5a5 455
bogdanm 92:4fc01daae5a5 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 92:4fc01daae5a5 457 {
bogdanm 92:4fc01daae5a5 458 uint32_t result;
bogdanm 92:4fc01daae5a5 459
bogdanm 92:4fc01daae5a5 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 92:4fc01daae5a5 461 return(result);
bogdanm 92:4fc01daae5a5 462 }
bogdanm 92:4fc01daae5a5 463
bogdanm 92:4fc01daae5a5 464 #define __SSAT16(ARG1,ARG2) \
bogdanm 92:4fc01daae5a5 465 ({ \
bogdanm 92:4fc01daae5a5 466 uint32_t __RES, __ARG1 = (ARG1); \
bogdanm 92:4fc01daae5a5 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
bogdanm 92:4fc01daae5a5 468 __RES; \
bogdanm 92:4fc01daae5a5 469 })
bogdanm 92:4fc01daae5a5 470
bogdanm 92:4fc01daae5a5 471 #define __USAT16(ARG1,ARG2) \
bogdanm 92:4fc01daae5a5 472 ({ \
bogdanm 92:4fc01daae5a5 473 uint32_t __RES, __ARG1 = (ARG1); \
bogdanm 92:4fc01daae5a5 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
bogdanm 92:4fc01daae5a5 475 __RES; \
bogdanm 92:4fc01daae5a5 476 })
bogdanm 92:4fc01daae5a5 477
bogdanm 92:4fc01daae5a5 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
bogdanm 92:4fc01daae5a5 479 {
bogdanm 92:4fc01daae5a5 480 uint32_t result;
bogdanm 92:4fc01daae5a5 481
bogdanm 92:4fc01daae5a5 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
bogdanm 92:4fc01daae5a5 483 return(result);
bogdanm 92:4fc01daae5a5 484 }
bogdanm 92:4fc01daae5a5 485
bogdanm 92:4fc01daae5a5 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 487 {
bogdanm 92:4fc01daae5a5 488 uint32_t result;
bogdanm 92:4fc01daae5a5 489
bogdanm 92:4fc01daae5a5 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 491 return(result);
bogdanm 92:4fc01daae5a5 492 }
bogdanm 92:4fc01daae5a5 493
bogdanm 92:4fc01daae5a5 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
bogdanm 92:4fc01daae5a5 495 {
bogdanm 92:4fc01daae5a5 496 uint32_t result;
bogdanm 92:4fc01daae5a5 497
bogdanm 92:4fc01daae5a5 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
bogdanm 92:4fc01daae5a5 499 return(result);
bogdanm 92:4fc01daae5a5 500 }
bogdanm 92:4fc01daae5a5 501
bogdanm 92:4fc01daae5a5 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 503 {
bogdanm 92:4fc01daae5a5 504 uint32_t result;
bogdanm 92:4fc01daae5a5 505
bogdanm 92:4fc01daae5a5 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 507 return(result);
bogdanm 92:4fc01daae5a5 508 }
bogdanm 92:4fc01daae5a5 509
bogdanm 92:4fc01daae5a5 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 511 {
bogdanm 92:4fc01daae5a5 512 uint32_t result;
bogdanm 92:4fc01daae5a5 513
bogdanm 92:4fc01daae5a5 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 515 return(result);
bogdanm 92:4fc01daae5a5 516 }
bogdanm 92:4fc01daae5a5 517
bogdanm 92:4fc01daae5a5 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 519 {
bogdanm 92:4fc01daae5a5 520 uint32_t result;
bogdanm 92:4fc01daae5a5 521
bogdanm 92:4fc01daae5a5 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 523 return(result);
bogdanm 92:4fc01daae5a5 524 }
bogdanm 92:4fc01daae5a5 525
bogdanm 92:4fc01daae5a5 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 92:4fc01daae5a5 527 {
bogdanm 92:4fc01daae5a5 528 uint32_t result;
bogdanm 92:4fc01daae5a5 529
bogdanm 92:4fc01daae5a5 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 92:4fc01daae5a5 531 return(result);
bogdanm 92:4fc01daae5a5 532 }
bogdanm 92:4fc01daae5a5 533
bogdanm 92:4fc01daae5a5 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 92:4fc01daae5a5 535 {
bogdanm 92:4fc01daae5a5 536 uint32_t result;
bogdanm 92:4fc01daae5a5 537
bogdanm 92:4fc01daae5a5 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 92:4fc01daae5a5 539 return(result);
bogdanm 92:4fc01daae5a5 540 }
bogdanm 92:4fc01daae5a5 541
bogdanm 92:4fc01daae5a5 542 #define __SMLALD(ARG1,ARG2,ARG3) \
bogdanm 92:4fc01daae5a5 543 ({ \
bogdanm 92:4fc01daae5a5 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
bogdanm 92:4fc01daae5a5 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
bogdanm 92:4fc01daae5a5 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
bogdanm 92:4fc01daae5a5 547 })
bogdanm 92:4fc01daae5a5 548
bogdanm 92:4fc01daae5a5 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
bogdanm 92:4fc01daae5a5 550 ({ \
bogdanm 92:4fc01daae5a5 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
bogdanm 92:4fc01daae5a5 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
bogdanm 92:4fc01daae5a5 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
bogdanm 92:4fc01daae5a5 554 })
bogdanm 92:4fc01daae5a5 555
bogdanm 92:4fc01daae5a5 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 557 {
bogdanm 92:4fc01daae5a5 558 uint32_t result;
bogdanm 92:4fc01daae5a5 559
bogdanm 92:4fc01daae5a5 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 561 return(result);
bogdanm 92:4fc01daae5a5 562 }
bogdanm 92:4fc01daae5a5 563
bogdanm 92:4fc01daae5a5 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 565 {
bogdanm 92:4fc01daae5a5 566 uint32_t result;
bogdanm 92:4fc01daae5a5 567
bogdanm 92:4fc01daae5a5 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 569 return(result);
bogdanm 92:4fc01daae5a5 570 }
bogdanm 92:4fc01daae5a5 571
bogdanm 92:4fc01daae5a5 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 92:4fc01daae5a5 573 {
bogdanm 92:4fc01daae5a5 574 uint32_t result;
bogdanm 92:4fc01daae5a5 575
bogdanm 92:4fc01daae5a5 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 92:4fc01daae5a5 577 return(result);
bogdanm 92:4fc01daae5a5 578 }
bogdanm 92:4fc01daae5a5 579
bogdanm 92:4fc01daae5a5 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
bogdanm 92:4fc01daae5a5 581 {
bogdanm 92:4fc01daae5a5 582 uint32_t result;
bogdanm 92:4fc01daae5a5 583
bogdanm 92:4fc01daae5a5 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
bogdanm 92:4fc01daae5a5 585 return(result);
bogdanm 92:4fc01daae5a5 586 }
bogdanm 92:4fc01daae5a5 587
bogdanm 92:4fc01daae5a5 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
bogdanm 92:4fc01daae5a5 589 ({ \
bogdanm 92:4fc01daae5a5 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
bogdanm 92:4fc01daae5a5 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
bogdanm 92:4fc01daae5a5 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
bogdanm 92:4fc01daae5a5 593 })
bogdanm 92:4fc01daae5a5 594
bogdanm 92:4fc01daae5a5 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
bogdanm 92:4fc01daae5a5 596 ({ \
bogdanm 92:4fc01daae5a5 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
bogdanm 92:4fc01daae5a5 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
bogdanm 92:4fc01daae5a5 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
bogdanm 92:4fc01daae5a5 600 })
bogdanm 92:4fc01daae5a5 601
bogdanm 92:4fc01daae5a5 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 603 {
bogdanm 92:4fc01daae5a5 604 uint32_t result;
bogdanm 92:4fc01daae5a5 605
bogdanm 92:4fc01daae5a5 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 607 return(result);
bogdanm 92:4fc01daae5a5 608 }
bogdanm 92:4fc01daae5a5 609
bogdanm 92:4fc01daae5a5 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 611 {
bogdanm 92:4fc01daae5a5 612 uint32_t result;
bogdanm 92:4fc01daae5a5 613
bogdanm 92:4fc01daae5a5 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 615 return(result);
bogdanm 92:4fc01daae5a5 616 }
bogdanm 92:4fc01daae5a5 617
bogdanm 92:4fc01daae5a5 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
bogdanm 92:4fc01daae5a5 619 {
bogdanm 92:4fc01daae5a5 620 uint32_t result;
bogdanm 92:4fc01daae5a5 621
bogdanm 92:4fc01daae5a5 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
bogdanm 92:4fc01daae5a5 623 return(result);
bogdanm 92:4fc01daae5a5 624 }
bogdanm 92:4fc01daae5a5 625
bogdanm 92:4fc01daae5a5 626 #define __PKHBT(ARG1,ARG2,ARG3) \
bogdanm 92:4fc01daae5a5 627 ({ \
bogdanm 92:4fc01daae5a5 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
bogdanm 92:4fc01daae5a5 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
bogdanm 92:4fc01daae5a5 630 __RES; \
bogdanm 92:4fc01daae5a5 631 })
bogdanm 92:4fc01daae5a5 632
bogdanm 92:4fc01daae5a5 633 #define __PKHTB(ARG1,ARG2,ARG3) \
bogdanm 92:4fc01daae5a5 634 ({ \
bogdanm 92:4fc01daae5a5 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
bogdanm 92:4fc01daae5a5 636 if (ARG3 == 0) \
bogdanm 92:4fc01daae5a5 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
bogdanm 92:4fc01daae5a5 638 else \
bogdanm 92:4fc01daae5a5 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
bogdanm 92:4fc01daae5a5 640 __RES; \
bogdanm 92:4fc01daae5a5 641 })
bogdanm 92:4fc01daae5a5 642
bogdanm 92:4fc01daae5a5 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
bogdanm 92:4fc01daae5a5 644 {
bogdanm 92:4fc01daae5a5 645 int32_t result;
bogdanm 92:4fc01daae5a5 646
bogdanm 92:4fc01daae5a5 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
bogdanm 92:4fc01daae5a5 648 return(result);
bogdanm 92:4fc01daae5a5 649 }
bogdanm 92:4fc01daae5a5 650
bogdanm 92:4fc01daae5a5 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 92:4fc01daae5a5 652
bogdanm 92:4fc01daae5a5 653
bogdanm 92:4fc01daae5a5 654
bogdanm 92:4fc01daae5a5 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
bogdanm 92:4fc01daae5a5 656 /* TASKING carm specific functions */
bogdanm 92:4fc01daae5a5 657
bogdanm 92:4fc01daae5a5 658
bogdanm 92:4fc01daae5a5 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 92:4fc01daae5a5 660 /* not yet supported */
bogdanm 92:4fc01daae5a5 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
bogdanm 92:4fc01daae5a5 662
bogdanm 92:4fc01daae5a5 663
bogdanm 92:4fc01daae5a5 664 #endif
bogdanm 92:4fc01daae5a5 665
bogdanm 92:4fc01daae5a5 666 /*@} end of group CMSIS_SIMD_intrinsics */
bogdanm 92:4fc01daae5a5 667
bogdanm 92:4fc01daae5a5 668
bogdanm 92:4fc01daae5a5 669 #endif /* __CORE_CM4_SIMD_H */
bogdanm 92:4fc01daae5a5 670
bogdanm 92:4fc01daae5a5 671 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 672 }
bogdanm 92:4fc01daae5a5 673 #endif