mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_RZ_A1H/core_caFunc.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
156:ff21514d8981 
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 2 * @file core_caFunc.h
AnnaBridge 156:ff21514d8981 3 * @brief CMSIS Cortex-A Core Function Access Header File
AnnaBridge 156:ff21514d8981 4 * @version V3.10
AnnaBridge 156:ff21514d8981 5 * @date 30 Oct 2013
AnnaBridge 156:ff21514d8981 6 *
AnnaBridge 156:ff21514d8981 7 * @note
AnnaBridge 156:ff21514d8981 8 *
AnnaBridge 156:ff21514d8981 9 ******************************************************************************/
AnnaBridge 156:ff21514d8981 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
AnnaBridge 156:ff21514d8981 11
AnnaBridge 156:ff21514d8981 12 All rights reserved.
AnnaBridge 156:ff21514d8981 13 Redistribution and use in source and binary forms, with or without
AnnaBridge 156:ff21514d8981 14 modification, are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 15 - Redistributions of source code must retain the above copyright
AnnaBridge 156:ff21514d8981 16 notice, this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 17 - Redistributions in binary form must reproduce the above copyright
AnnaBridge 156:ff21514d8981 18 notice, this list of conditions and the following disclaimer in the
AnnaBridge 156:ff21514d8981 19 documentation and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 20 - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 156:ff21514d8981 21 to endorse or promote products derived from this software without
AnnaBridge 156:ff21514d8981 22 specific prior written permission.
AnnaBridge 156:ff21514d8981 23 *
AnnaBridge 156:ff21514d8981 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 156:ff21514d8981 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 156:ff21514d8981 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 156:ff21514d8981 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 156:ff21514d8981 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 156:ff21514d8981 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 156:ff21514d8981 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 156:ff21514d8981 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 156:ff21514d8981 34 POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 35 ---------------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 36
AnnaBridge 156:ff21514d8981 37
AnnaBridge 156:ff21514d8981 38 #ifndef __CORE_CAFUNC_H__
AnnaBridge 156:ff21514d8981 39 #define __CORE_CAFUNC_H__
AnnaBridge 156:ff21514d8981 40
AnnaBridge 156:ff21514d8981 41
AnnaBridge 156:ff21514d8981 42 /* ########################### Core Function Access ########################### */
AnnaBridge 156:ff21514d8981 43 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 156:ff21514d8981 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge 156:ff21514d8981 45 @{
AnnaBridge 156:ff21514d8981 46 */
AnnaBridge 156:ff21514d8981 47
AnnaBridge 156:ff21514d8981 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
AnnaBridge 156:ff21514d8981 49 /* ARM armcc specific functions */
AnnaBridge 156:ff21514d8981 50
AnnaBridge 156:ff21514d8981 51 #if (__ARMCC_VERSION < 400677)
AnnaBridge 156:ff21514d8981 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
AnnaBridge 156:ff21514d8981 53 #endif
AnnaBridge 156:ff21514d8981 54
AnnaBridge 156:ff21514d8981 55 #define MODE_USR 0x10
AnnaBridge 156:ff21514d8981 56 #define MODE_FIQ 0x11
AnnaBridge 156:ff21514d8981 57 #define MODE_IRQ 0x12
AnnaBridge 156:ff21514d8981 58 #define MODE_SVC 0x13
AnnaBridge 156:ff21514d8981 59 #define MODE_MON 0x16
AnnaBridge 156:ff21514d8981 60 #define MODE_ABT 0x17
AnnaBridge 156:ff21514d8981 61 #define MODE_HYP 0x1A
AnnaBridge 156:ff21514d8981 62 #define MODE_UND 0x1B
AnnaBridge 156:ff21514d8981 63 #define MODE_SYS 0x1F
AnnaBridge 156:ff21514d8981 64
AnnaBridge 156:ff21514d8981 65 /** \brief Get APSR Register
AnnaBridge 156:ff21514d8981 66
AnnaBridge 156:ff21514d8981 67 This function returns the content of the APSR Register.
AnnaBridge 156:ff21514d8981 68
AnnaBridge 156:ff21514d8981 69 \return APSR Register value
AnnaBridge 156:ff21514d8981 70 */
AnnaBridge 156:ff21514d8981 71 __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge 156:ff21514d8981 72 {
AnnaBridge 156:ff21514d8981 73 register uint32_t __regAPSR __ASM("apsr");
AnnaBridge 156:ff21514d8981 74 return(__regAPSR);
AnnaBridge 156:ff21514d8981 75 }
AnnaBridge 156:ff21514d8981 76
AnnaBridge 156:ff21514d8981 77
AnnaBridge 156:ff21514d8981 78 /** \brief Get CPSR Register
AnnaBridge 156:ff21514d8981 79
AnnaBridge 156:ff21514d8981 80 This function returns the content of the CPSR Register.
AnnaBridge 156:ff21514d8981 81
AnnaBridge 156:ff21514d8981 82 \return CPSR Register value
AnnaBridge 156:ff21514d8981 83 */
AnnaBridge 156:ff21514d8981 84 __STATIC_INLINE uint32_t __get_CPSR(void)
AnnaBridge 156:ff21514d8981 85 {
AnnaBridge 156:ff21514d8981 86 register uint32_t __regCPSR __ASM("cpsr");
AnnaBridge 156:ff21514d8981 87 return(__regCPSR);
AnnaBridge 156:ff21514d8981 88 }
AnnaBridge 156:ff21514d8981 89
AnnaBridge 156:ff21514d8981 90 /** \brief Set Stack Pointer
AnnaBridge 156:ff21514d8981 91
AnnaBridge 156:ff21514d8981 92 This function assigns the given value to the current stack pointer.
AnnaBridge 156:ff21514d8981 93
AnnaBridge 156:ff21514d8981 94 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 156:ff21514d8981 95 */
AnnaBridge 156:ff21514d8981 96 register uint32_t __regSP __ASM("sp");
AnnaBridge 156:ff21514d8981 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
AnnaBridge 156:ff21514d8981 98 {
AnnaBridge 156:ff21514d8981 99 __regSP = topOfStack;
AnnaBridge 156:ff21514d8981 100 }
AnnaBridge 156:ff21514d8981 101
AnnaBridge 156:ff21514d8981 102
AnnaBridge 156:ff21514d8981 103 /** \brief Get link register
AnnaBridge 156:ff21514d8981 104
AnnaBridge 156:ff21514d8981 105 This function returns the value of the link register
AnnaBridge 156:ff21514d8981 106
AnnaBridge 156:ff21514d8981 107 \return Value of link register
AnnaBridge 156:ff21514d8981 108 */
AnnaBridge 156:ff21514d8981 109 register uint32_t __reglr __ASM("lr");
AnnaBridge 156:ff21514d8981 110 __STATIC_INLINE uint32_t __get_LR(void)
AnnaBridge 156:ff21514d8981 111 {
AnnaBridge 156:ff21514d8981 112 return(__reglr);
AnnaBridge 156:ff21514d8981 113 }
AnnaBridge 156:ff21514d8981 114
AnnaBridge 156:ff21514d8981 115 /** \brief Set link register
AnnaBridge 156:ff21514d8981 116
AnnaBridge 156:ff21514d8981 117 This function sets the value of the link register
AnnaBridge 156:ff21514d8981 118
AnnaBridge 156:ff21514d8981 119 \param [in] lr LR value to set
AnnaBridge 156:ff21514d8981 120 */
AnnaBridge 156:ff21514d8981 121 __STATIC_INLINE void __set_LR(uint32_t lr)
AnnaBridge 156:ff21514d8981 122 {
AnnaBridge 156:ff21514d8981 123 __reglr = lr;
AnnaBridge 156:ff21514d8981 124 }
AnnaBridge 156:ff21514d8981 125
AnnaBridge 156:ff21514d8981 126 /** \brief Set Process Stack Pointer
AnnaBridge 156:ff21514d8981 127
AnnaBridge 156:ff21514d8981 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
AnnaBridge 156:ff21514d8981 129
AnnaBridge 156:ff21514d8981 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 156:ff21514d8981 131 */
AnnaBridge 156:ff21514d8981 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 156:ff21514d8981 133 {
AnnaBridge 156:ff21514d8981 134 ARM
AnnaBridge 156:ff21514d8981 135 PRESERVE8
AnnaBridge 156:ff21514d8981 136
AnnaBridge 156:ff21514d8981 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
AnnaBridge 156:ff21514d8981 138 MRS R1, CPSR
AnnaBridge 156:ff21514d8981 139 CPS #MODE_SYS ;no effect in USR mode
AnnaBridge 156:ff21514d8981 140 MOV SP, R0
AnnaBridge 156:ff21514d8981 141 MSR CPSR_c, R1 ;no effect in USR mode
AnnaBridge 156:ff21514d8981 142 ISB
AnnaBridge 156:ff21514d8981 143 BX LR
AnnaBridge 156:ff21514d8981 144
AnnaBridge 156:ff21514d8981 145 }
AnnaBridge 156:ff21514d8981 146
AnnaBridge 156:ff21514d8981 147 /** \brief Set User Mode
AnnaBridge 156:ff21514d8981 148
AnnaBridge 156:ff21514d8981 149 This function changes the processor state to User Mode
AnnaBridge 156:ff21514d8981 150 */
AnnaBridge 156:ff21514d8981 151 __STATIC_ASM void __set_CPS_USR(void)
AnnaBridge 156:ff21514d8981 152 {
AnnaBridge 156:ff21514d8981 153 ARM
AnnaBridge 156:ff21514d8981 154
AnnaBridge 156:ff21514d8981 155 CPS #MODE_USR
AnnaBridge 156:ff21514d8981 156 BX LR
AnnaBridge 156:ff21514d8981 157 }
AnnaBridge 156:ff21514d8981 158
AnnaBridge 156:ff21514d8981 159
AnnaBridge 156:ff21514d8981 160 /** \brief Enable FIQ
AnnaBridge 156:ff21514d8981 161
AnnaBridge 156:ff21514d8981 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 156:ff21514d8981 163 Can only be executed in Privileged modes.
AnnaBridge 156:ff21514d8981 164 */
AnnaBridge 156:ff21514d8981 165 #define __enable_fault_irq __enable_fiq
AnnaBridge 156:ff21514d8981 166
AnnaBridge 156:ff21514d8981 167
AnnaBridge 156:ff21514d8981 168 /** \brief Disable FIQ
AnnaBridge 156:ff21514d8981 169
AnnaBridge 156:ff21514d8981 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 156:ff21514d8981 171 Can only be executed in Privileged modes.
AnnaBridge 156:ff21514d8981 172 */
AnnaBridge 156:ff21514d8981 173 #define __disable_fault_irq __disable_fiq
AnnaBridge 156:ff21514d8981 174
AnnaBridge 156:ff21514d8981 175
AnnaBridge 156:ff21514d8981 176 /** \brief Get FPSCR
AnnaBridge 156:ff21514d8981 177
AnnaBridge 156:ff21514d8981 178 This function returns the current value of the Floating Point Status/Control register.
AnnaBridge 156:ff21514d8981 179
AnnaBridge 156:ff21514d8981 180 \return Floating Point Status/Control register value
AnnaBridge 156:ff21514d8981 181 */
AnnaBridge 156:ff21514d8981 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 156:ff21514d8981 183 {
AnnaBridge 156:ff21514d8981 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 156:ff21514d8981 185 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 156:ff21514d8981 186 return(__regfpscr);
AnnaBridge 156:ff21514d8981 187 #else
AnnaBridge 156:ff21514d8981 188 return(0);
AnnaBridge 156:ff21514d8981 189 #endif
AnnaBridge 156:ff21514d8981 190 }
AnnaBridge 156:ff21514d8981 191
AnnaBridge 156:ff21514d8981 192
AnnaBridge 156:ff21514d8981 193 /** \brief Set FPSCR
AnnaBridge 156:ff21514d8981 194
AnnaBridge 156:ff21514d8981 195 This function assigns the given value to the Floating Point Status/Control register.
AnnaBridge 156:ff21514d8981 196
AnnaBridge 156:ff21514d8981 197 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 156:ff21514d8981 198 */
AnnaBridge 156:ff21514d8981 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 156:ff21514d8981 200 {
AnnaBridge 156:ff21514d8981 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 156:ff21514d8981 202 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 156:ff21514d8981 203 __regfpscr = (fpscr);
AnnaBridge 156:ff21514d8981 204 #endif
AnnaBridge 156:ff21514d8981 205 }
AnnaBridge 156:ff21514d8981 206
AnnaBridge 156:ff21514d8981 207 /** \brief Get FPEXC
AnnaBridge 156:ff21514d8981 208
AnnaBridge 156:ff21514d8981 209 This function returns the current value of the Floating Point Exception Control register.
AnnaBridge 156:ff21514d8981 210
AnnaBridge 156:ff21514d8981 211 \return Floating Point Exception Control register value
AnnaBridge 156:ff21514d8981 212 */
AnnaBridge 156:ff21514d8981 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
AnnaBridge 156:ff21514d8981 214 {
AnnaBridge 156:ff21514d8981 215 #if (__FPU_PRESENT == 1)
AnnaBridge 156:ff21514d8981 216 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 156:ff21514d8981 217 return(__regfpexc);
AnnaBridge 156:ff21514d8981 218 #else
AnnaBridge 156:ff21514d8981 219 return(0);
AnnaBridge 156:ff21514d8981 220 #endif
AnnaBridge 156:ff21514d8981 221 }
AnnaBridge 156:ff21514d8981 222
AnnaBridge 156:ff21514d8981 223
AnnaBridge 156:ff21514d8981 224 /** \brief Set FPEXC
AnnaBridge 156:ff21514d8981 225
AnnaBridge 156:ff21514d8981 226 This function assigns the given value to the Floating Point Exception Control register.
AnnaBridge 156:ff21514d8981 227
AnnaBridge 156:ff21514d8981 228 \param [in] fpscr Floating Point Exception Control value to set
AnnaBridge 156:ff21514d8981 229 */
AnnaBridge 156:ff21514d8981 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 156:ff21514d8981 231 {
AnnaBridge 156:ff21514d8981 232 #if (__FPU_PRESENT == 1)
AnnaBridge 156:ff21514d8981 233 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 156:ff21514d8981 234 __regfpexc = (fpexc);
AnnaBridge 156:ff21514d8981 235 #endif
AnnaBridge 156:ff21514d8981 236 }
AnnaBridge 156:ff21514d8981 237
AnnaBridge 156:ff21514d8981 238 /** \brief Get CPACR
AnnaBridge 156:ff21514d8981 239
AnnaBridge 156:ff21514d8981 240 This function returns the current value of the Coprocessor Access Control register.
AnnaBridge 156:ff21514d8981 241
AnnaBridge 156:ff21514d8981 242 \return Coprocessor Access Control register value
AnnaBridge 156:ff21514d8981 243 */
AnnaBridge 156:ff21514d8981 244 __STATIC_INLINE uint32_t __get_CPACR(void)
AnnaBridge 156:ff21514d8981 245 {
AnnaBridge 156:ff21514d8981 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 156:ff21514d8981 247 return __regCPACR;
AnnaBridge 156:ff21514d8981 248 }
AnnaBridge 156:ff21514d8981 249
AnnaBridge 156:ff21514d8981 250 /** \brief Set CPACR
AnnaBridge 156:ff21514d8981 251
AnnaBridge 156:ff21514d8981 252 This function assigns the given value to the Coprocessor Access Control register.
AnnaBridge 156:ff21514d8981 253
AnnaBridge 156:ff21514d8981 254 \param [in] cpacr Coprocessor Acccess Control value to set
AnnaBridge 156:ff21514d8981 255 */
AnnaBridge 156:ff21514d8981 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
AnnaBridge 156:ff21514d8981 257 {
AnnaBridge 156:ff21514d8981 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 156:ff21514d8981 259 __regCPACR = cpacr;
AnnaBridge 156:ff21514d8981 260 __ISB();
AnnaBridge 156:ff21514d8981 261 }
AnnaBridge 156:ff21514d8981 262
AnnaBridge 156:ff21514d8981 263 /** \brief Get CBAR
AnnaBridge 156:ff21514d8981 264
AnnaBridge 156:ff21514d8981 265 This function returns the value of the Configuration Base Address register.
AnnaBridge 156:ff21514d8981 266
AnnaBridge 156:ff21514d8981 267 \return Configuration Base Address register value
AnnaBridge 156:ff21514d8981 268 */
AnnaBridge 156:ff21514d8981 269 __STATIC_INLINE uint32_t __get_CBAR() {
AnnaBridge 156:ff21514d8981 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
AnnaBridge 156:ff21514d8981 271 return(__regCBAR);
AnnaBridge 156:ff21514d8981 272 }
AnnaBridge 156:ff21514d8981 273
AnnaBridge 156:ff21514d8981 274 /** \brief Get TTBR0
AnnaBridge 156:ff21514d8981 275
AnnaBridge 156:ff21514d8981 276 This function returns the value of the Translation Table Base Register 0.
AnnaBridge 156:ff21514d8981 277
AnnaBridge 156:ff21514d8981 278 \return Translation Table Base Register 0 value
AnnaBridge 156:ff21514d8981 279 */
AnnaBridge 156:ff21514d8981 280 __STATIC_INLINE uint32_t __get_TTBR0() {
AnnaBridge 156:ff21514d8981 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 156:ff21514d8981 282 return(__regTTBR0);
AnnaBridge 156:ff21514d8981 283 }
AnnaBridge 156:ff21514d8981 284
AnnaBridge 156:ff21514d8981 285 /** \brief Set TTBR0
AnnaBridge 156:ff21514d8981 286
AnnaBridge 156:ff21514d8981 287 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 156:ff21514d8981 288
AnnaBridge 156:ff21514d8981 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 156:ff21514d8981 290 */
AnnaBridge 156:ff21514d8981 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 156:ff21514d8981 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 156:ff21514d8981 293 __regTTBR0 = ttbr0;
AnnaBridge 156:ff21514d8981 294 __ISB();
AnnaBridge 156:ff21514d8981 295 }
AnnaBridge 156:ff21514d8981 296
AnnaBridge 156:ff21514d8981 297 /** \brief Get DACR
AnnaBridge 156:ff21514d8981 298
AnnaBridge 156:ff21514d8981 299 This function returns the value of the Domain Access Control Register.
AnnaBridge 156:ff21514d8981 300
AnnaBridge 156:ff21514d8981 301 \return Domain Access Control Register value
AnnaBridge 156:ff21514d8981 302 */
AnnaBridge 156:ff21514d8981 303 __STATIC_INLINE uint32_t __get_DACR() {
AnnaBridge 156:ff21514d8981 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 156:ff21514d8981 305 return(__regDACR);
AnnaBridge 156:ff21514d8981 306 }
AnnaBridge 156:ff21514d8981 307
AnnaBridge 156:ff21514d8981 308 /** \brief Set DACR
AnnaBridge 156:ff21514d8981 309
AnnaBridge 156:ff21514d8981 310 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 156:ff21514d8981 311
AnnaBridge 156:ff21514d8981 312 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 156:ff21514d8981 313 */
AnnaBridge 156:ff21514d8981 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 156:ff21514d8981 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 156:ff21514d8981 316 __regDACR = dacr;
AnnaBridge 156:ff21514d8981 317 __ISB();
AnnaBridge 156:ff21514d8981 318 }
AnnaBridge 156:ff21514d8981 319
AnnaBridge 156:ff21514d8981 320 /******************************** Cache and BTAC enable ****************************************************/
AnnaBridge 156:ff21514d8981 321
AnnaBridge 156:ff21514d8981 322 /** \brief Set SCTLR
AnnaBridge 156:ff21514d8981 323
AnnaBridge 156:ff21514d8981 324 This function assigns the given value to the System Control Register.
AnnaBridge 156:ff21514d8981 325
AnnaBridge 156:ff21514d8981 326 \param [in] sctlr System Control Register value to set
AnnaBridge 156:ff21514d8981 327 */
AnnaBridge 156:ff21514d8981 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
AnnaBridge 156:ff21514d8981 329 {
AnnaBridge 156:ff21514d8981 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 156:ff21514d8981 331 __regSCTLR = sctlr;
AnnaBridge 156:ff21514d8981 332 }
AnnaBridge 156:ff21514d8981 333
AnnaBridge 156:ff21514d8981 334 /** \brief Get SCTLR
AnnaBridge 156:ff21514d8981 335
AnnaBridge 156:ff21514d8981 336 This function returns the value of the System Control Register.
AnnaBridge 156:ff21514d8981 337
AnnaBridge 156:ff21514d8981 338 \return System Control Register value
AnnaBridge 156:ff21514d8981 339 */
AnnaBridge 156:ff21514d8981 340 __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 156:ff21514d8981 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 156:ff21514d8981 342 return(__regSCTLR);
AnnaBridge 156:ff21514d8981 343 }
AnnaBridge 156:ff21514d8981 344
AnnaBridge 156:ff21514d8981 345 /** \brief Enable Caches
AnnaBridge 156:ff21514d8981 346
AnnaBridge 156:ff21514d8981 347 Enable Caches
AnnaBridge 156:ff21514d8981 348 */
AnnaBridge 156:ff21514d8981 349 __STATIC_INLINE void __enable_caches(void) {
AnnaBridge 156:ff21514d8981 350 // Set I bit 12 to enable I Cache
AnnaBridge 156:ff21514d8981 351 // Set C bit 2 to enable D Cache
AnnaBridge 156:ff21514d8981 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 156:ff21514d8981 353 }
AnnaBridge 156:ff21514d8981 354
AnnaBridge 156:ff21514d8981 355 /** \brief Disable Caches
AnnaBridge 156:ff21514d8981 356
AnnaBridge 156:ff21514d8981 357 Disable Caches
AnnaBridge 156:ff21514d8981 358 */
AnnaBridge 156:ff21514d8981 359 __STATIC_INLINE void __disable_caches(void) {
AnnaBridge 156:ff21514d8981 360 // Clear I bit 12 to disable I Cache
AnnaBridge 156:ff21514d8981 361 // Clear C bit 2 to disable D Cache
AnnaBridge 156:ff21514d8981 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
AnnaBridge 156:ff21514d8981 363 __ISB();
AnnaBridge 156:ff21514d8981 364 }
AnnaBridge 156:ff21514d8981 365
AnnaBridge 156:ff21514d8981 366 /** \brief Enable BTAC
AnnaBridge 156:ff21514d8981 367
AnnaBridge 156:ff21514d8981 368 Enable BTAC
AnnaBridge 156:ff21514d8981 369 */
AnnaBridge 156:ff21514d8981 370 __STATIC_INLINE void __enable_btac(void) {
AnnaBridge 156:ff21514d8981 371 // Set Z bit 11 to enable branch prediction
AnnaBridge 156:ff21514d8981 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 156:ff21514d8981 373 __ISB();
AnnaBridge 156:ff21514d8981 374 }
AnnaBridge 156:ff21514d8981 375
AnnaBridge 156:ff21514d8981 376 /** \brief Disable BTAC
AnnaBridge 156:ff21514d8981 377
AnnaBridge 156:ff21514d8981 378 Disable BTAC
AnnaBridge 156:ff21514d8981 379 */
AnnaBridge 156:ff21514d8981 380 __STATIC_INLINE void __disable_btac(void) {
AnnaBridge 156:ff21514d8981 381 // Clear Z bit 11 to disable branch prediction
AnnaBridge 156:ff21514d8981 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
AnnaBridge 156:ff21514d8981 383 }
AnnaBridge 156:ff21514d8981 384
AnnaBridge 156:ff21514d8981 385
AnnaBridge 156:ff21514d8981 386 /** \brief Enable MMU
AnnaBridge 156:ff21514d8981 387
AnnaBridge 156:ff21514d8981 388 Enable MMU
AnnaBridge 156:ff21514d8981 389 */
AnnaBridge 156:ff21514d8981 390 __STATIC_INLINE void __enable_mmu(void) {
AnnaBridge 156:ff21514d8981 391 // Set M bit 0 to enable the MMU
AnnaBridge 156:ff21514d8981 392 // Set AFE bit to enable simplified access permissions model
AnnaBridge 156:ff21514d8981 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 156:ff21514d8981 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 156:ff21514d8981 395 __ISB();
AnnaBridge 156:ff21514d8981 396 }
AnnaBridge 156:ff21514d8981 397
AnnaBridge 156:ff21514d8981 398 /** \brief Disable MMU
AnnaBridge 156:ff21514d8981 399
AnnaBridge 156:ff21514d8981 400 Disable MMU
AnnaBridge 156:ff21514d8981 401 */
AnnaBridge 156:ff21514d8981 402 __STATIC_INLINE void __disable_mmu(void) {
AnnaBridge 156:ff21514d8981 403 // Clear M bit 0 to disable the MMU
AnnaBridge 156:ff21514d8981 404 __set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge 156:ff21514d8981 405 __ISB();
AnnaBridge 156:ff21514d8981 406 }
AnnaBridge 156:ff21514d8981 407
AnnaBridge 156:ff21514d8981 408 /******************************** TLB maintenance operations ************************************************/
AnnaBridge 156:ff21514d8981 409 /** \brief Invalidate the whole tlb
AnnaBridge 156:ff21514d8981 410
AnnaBridge 156:ff21514d8981 411 TLBIALL. Invalidate the whole tlb
AnnaBridge 156:ff21514d8981 412 */
AnnaBridge 156:ff21514d8981 413
AnnaBridge 156:ff21514d8981 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
AnnaBridge 156:ff21514d8981 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
AnnaBridge 156:ff21514d8981 416 __TLBIALL = 0;
AnnaBridge 156:ff21514d8981 417 __DSB();
AnnaBridge 156:ff21514d8981 418 __ISB();
AnnaBridge 156:ff21514d8981 419 }
AnnaBridge 156:ff21514d8981 420
AnnaBridge 156:ff21514d8981 421 /******************************** BTB maintenance operations ************************************************/
AnnaBridge 156:ff21514d8981 422 /** \brief Invalidate entire branch predictor array
AnnaBridge 156:ff21514d8981 423
AnnaBridge 156:ff21514d8981 424 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 156:ff21514d8981 425 */
AnnaBridge 156:ff21514d8981 426
AnnaBridge 156:ff21514d8981 427 __STATIC_INLINE void __v7_inv_btac(void) {
AnnaBridge 156:ff21514d8981 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
AnnaBridge 156:ff21514d8981 429 __BPIALL = 0;
AnnaBridge 156:ff21514d8981 430 __DSB(); //ensure completion of the invalidation
AnnaBridge 156:ff21514d8981 431 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 156:ff21514d8981 432 }
AnnaBridge 156:ff21514d8981 433
AnnaBridge 156:ff21514d8981 434
AnnaBridge 156:ff21514d8981 435 /******************************** L1 cache operations ******************************************************/
AnnaBridge 156:ff21514d8981 436
AnnaBridge 156:ff21514d8981 437 /** \brief Invalidate the whole I$
AnnaBridge 156:ff21514d8981 438
AnnaBridge 156:ff21514d8981 439 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 156:ff21514d8981 440 */
AnnaBridge 156:ff21514d8981 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
AnnaBridge 156:ff21514d8981 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
AnnaBridge 156:ff21514d8981 443 __ICIALLU = 0;
AnnaBridge 156:ff21514d8981 444 __DSB(); //ensure completion of the invalidation
AnnaBridge 156:ff21514d8981 445 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 156:ff21514d8981 446 }
AnnaBridge 156:ff21514d8981 447
AnnaBridge 156:ff21514d8981 448 /** \brief Clean D$ by MVA
AnnaBridge 156:ff21514d8981 449
AnnaBridge 156:ff21514d8981 450 DCCMVAC. Data cache clean by MVA to PoC
AnnaBridge 156:ff21514d8981 451 */
AnnaBridge 156:ff21514d8981 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
AnnaBridge 156:ff21514d8981 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
AnnaBridge 156:ff21514d8981 454 __DCCMVAC = (uint32_t)va;
AnnaBridge 156:ff21514d8981 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 156:ff21514d8981 456 }
AnnaBridge 156:ff21514d8981 457
AnnaBridge 156:ff21514d8981 458 /** \brief Invalidate D$ by MVA
AnnaBridge 156:ff21514d8981 459
AnnaBridge 156:ff21514d8981 460 DCIMVAC. Data cache invalidate by MVA to PoC
AnnaBridge 156:ff21514d8981 461 */
AnnaBridge 156:ff21514d8981 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
AnnaBridge 156:ff21514d8981 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
AnnaBridge 156:ff21514d8981 464 __DCIMVAC = (uint32_t)va;
AnnaBridge 156:ff21514d8981 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 156:ff21514d8981 466 }
AnnaBridge 156:ff21514d8981 467
AnnaBridge 156:ff21514d8981 468 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 156:ff21514d8981 469
AnnaBridge 156:ff21514d8981 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 156:ff21514d8981 471 */
AnnaBridge 156:ff21514d8981 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
AnnaBridge 156:ff21514d8981 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
AnnaBridge 156:ff21514d8981 474 __DCCIMVAC = (uint32_t)va;
AnnaBridge 156:ff21514d8981 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 156:ff21514d8981 476 }
AnnaBridge 156:ff21514d8981 477
AnnaBridge 156:ff21514d8981 478 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 156:ff21514d8981 479
AnnaBridge 156:ff21514d8981 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
AnnaBridge 156:ff21514d8981 481 */
AnnaBridge 156:ff21514d8981 482 #pragma push
AnnaBridge 156:ff21514d8981 483 #pragma arm
AnnaBridge 156:ff21514d8981 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
AnnaBridge 156:ff21514d8981 485 ARM
AnnaBridge 156:ff21514d8981 486
AnnaBridge 156:ff21514d8981 487 PUSH {R4-R11}
AnnaBridge 156:ff21514d8981 488
AnnaBridge 156:ff21514d8981 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
AnnaBridge 156:ff21514d8981 490 ANDS R3, R6, #0x07000000 // Extract coherency level
AnnaBridge 156:ff21514d8981 491 MOV R3, R3, LSR #23 // Total cache levels << 1
AnnaBridge 156:ff21514d8981 492 BEQ Finished // If 0, no need to clean
AnnaBridge 156:ff21514d8981 493
AnnaBridge 156:ff21514d8981 494 MOV R10, #0 // R10 holds current cache level << 1
AnnaBridge 156:ff21514d8981 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
AnnaBridge 156:ff21514d8981 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
AnnaBridge 156:ff21514d8981 497 AND R1, R1, #7 // Isolate those lower 3 bits
AnnaBridge 156:ff21514d8981 498 CMP R1, #2
AnnaBridge 156:ff21514d8981 499 BLT Skip // No cache or only instruction cache at this level
AnnaBridge 156:ff21514d8981 500
AnnaBridge 156:ff21514d8981 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
AnnaBridge 156:ff21514d8981 502 ISB // ISB to sync the change to the CacheSizeID reg
AnnaBridge 156:ff21514d8981 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
AnnaBridge 156:ff21514d8981 504 AND R2, R1, #7 // Extract the line length field
AnnaBridge 156:ff21514d8981 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
AnnaBridge 156:ff21514d8981 506 LDR R4, =0x3FF
AnnaBridge 156:ff21514d8981 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
AnnaBridge 156:ff21514d8981 508 CLZ R5, R4 // R5 is the bit position of the way size increment
AnnaBridge 156:ff21514d8981 509 LDR R7, =0x7FFF
AnnaBridge 156:ff21514d8981 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
AnnaBridge 156:ff21514d8981 511
AnnaBridge 156:ff21514d8981 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
AnnaBridge 156:ff21514d8981 513
AnnaBridge 156:ff21514d8981 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
AnnaBridge 156:ff21514d8981 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
AnnaBridge 156:ff21514d8981 516 CMP R0, #0
AnnaBridge 156:ff21514d8981 517 BNE Dccsw
AnnaBridge 156:ff21514d8981 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
AnnaBridge 156:ff21514d8981 519 B cont
AnnaBridge 156:ff21514d8981 520 Dccsw CMP R0, #1
AnnaBridge 156:ff21514d8981 521 BNE Dccisw
AnnaBridge 156:ff21514d8981 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
AnnaBridge 156:ff21514d8981 523 B cont
AnnaBridge 156:ff21514d8981 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 156:ff21514d8981 525 cont SUBS R9, R9, #1 // Decrement the Way number
AnnaBridge 156:ff21514d8981 526 BGE Loop3
AnnaBridge 156:ff21514d8981 527 SUBS R7, R7, #1 // Decrement the Set number
AnnaBridge 156:ff21514d8981 528 BGE Loop2
AnnaBridge 156:ff21514d8981 529 Skip ADD R10, R10, #2 // Increment the cache number
AnnaBridge 156:ff21514d8981 530 CMP R3, R10
AnnaBridge 156:ff21514d8981 531 BGT Loop1
AnnaBridge 156:ff21514d8981 532
AnnaBridge 156:ff21514d8981 533 Finished
AnnaBridge 156:ff21514d8981 534 DSB
AnnaBridge 156:ff21514d8981 535 POP {R4-R11}
AnnaBridge 156:ff21514d8981 536 BX lr
AnnaBridge 156:ff21514d8981 537
AnnaBridge 156:ff21514d8981 538 }
AnnaBridge 156:ff21514d8981 539 #pragma pop
AnnaBridge 156:ff21514d8981 540
AnnaBridge 156:ff21514d8981 541
AnnaBridge 156:ff21514d8981 542 /** \brief Invalidate the whole D$
AnnaBridge 156:ff21514d8981 543
AnnaBridge 156:ff21514d8981 544 DCISW. Invalidate by Set/Way
AnnaBridge 156:ff21514d8981 545 */
AnnaBridge 156:ff21514d8981 546
AnnaBridge 156:ff21514d8981 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
AnnaBridge 156:ff21514d8981 548 __v7_all_cache(0);
AnnaBridge 156:ff21514d8981 549 }
AnnaBridge 156:ff21514d8981 550
AnnaBridge 156:ff21514d8981 551 /** \brief Clean the whole D$
AnnaBridge 156:ff21514d8981 552
AnnaBridge 156:ff21514d8981 553 DCCSW. Clean by Set/Way
AnnaBridge 156:ff21514d8981 554 */
AnnaBridge 156:ff21514d8981 555
AnnaBridge 156:ff21514d8981 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
AnnaBridge 156:ff21514d8981 557 __v7_all_cache(1);
AnnaBridge 156:ff21514d8981 558 }
AnnaBridge 156:ff21514d8981 559
AnnaBridge 156:ff21514d8981 560 /** \brief Clean and invalidate the whole D$
AnnaBridge 156:ff21514d8981 561
AnnaBridge 156:ff21514d8981 562 DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 156:ff21514d8981 563 */
AnnaBridge 156:ff21514d8981 564
AnnaBridge 156:ff21514d8981 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
AnnaBridge 156:ff21514d8981 566 __v7_all_cache(2);
AnnaBridge 156:ff21514d8981 567 }
AnnaBridge 156:ff21514d8981 568
AnnaBridge 156:ff21514d8981 569 #include "core_ca_mmu.h"
AnnaBridge 156:ff21514d8981 570
AnnaBridge 156:ff21514d8981 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
AnnaBridge 156:ff21514d8981 572
AnnaBridge 156:ff21514d8981 573 #define __inline inline
AnnaBridge 156:ff21514d8981 574
AnnaBridge 156:ff21514d8981 575 inline static uint32_t __disable_irq_iar() {
AnnaBridge 156:ff21514d8981 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
AnnaBridge 156:ff21514d8981 577 __disable_irq();
AnnaBridge 156:ff21514d8981 578 return irq_dis;
AnnaBridge 156:ff21514d8981 579 }
AnnaBridge 156:ff21514d8981 580
AnnaBridge 156:ff21514d8981 581 #define MODE_USR 0x10
AnnaBridge 156:ff21514d8981 582 #define MODE_FIQ 0x11
AnnaBridge 156:ff21514d8981 583 #define MODE_IRQ 0x12
AnnaBridge 156:ff21514d8981 584 #define MODE_SVC 0x13
AnnaBridge 156:ff21514d8981 585 #define MODE_MON 0x16
AnnaBridge 156:ff21514d8981 586 #define MODE_ABT 0x17
AnnaBridge 156:ff21514d8981 587 #define MODE_HYP 0x1A
AnnaBridge 156:ff21514d8981 588 #define MODE_UND 0x1B
AnnaBridge 156:ff21514d8981 589 #define MODE_SYS 0x1F
AnnaBridge 156:ff21514d8981 590
AnnaBridge 156:ff21514d8981 591 /** \brief Set Process Stack Pointer
AnnaBridge 156:ff21514d8981 592
AnnaBridge 156:ff21514d8981 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
AnnaBridge 156:ff21514d8981 594
AnnaBridge 156:ff21514d8981 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 156:ff21514d8981 596 */
AnnaBridge 156:ff21514d8981 597 // from rt_CMSIS.c
AnnaBridge 156:ff21514d8981 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
AnnaBridge 156:ff21514d8981 599 __asm(
AnnaBridge 156:ff21514d8981 600 " ARM\n"
AnnaBridge 156:ff21514d8981 601 // " PRESERVE8\n"
AnnaBridge 156:ff21514d8981 602
AnnaBridge 156:ff21514d8981 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
AnnaBridge 156:ff21514d8981 604 " MRS R1, CPSR \n"
AnnaBridge 156:ff21514d8981 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
AnnaBridge 156:ff21514d8981 606 " MOV SP, R0 \n"
AnnaBridge 156:ff21514d8981 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
AnnaBridge 156:ff21514d8981 608 " ISB \n"
AnnaBridge 156:ff21514d8981 609 " BX LR \n");
AnnaBridge 156:ff21514d8981 610 }
AnnaBridge 156:ff21514d8981 611
AnnaBridge 156:ff21514d8981 612 /** \brief Set User Mode
AnnaBridge 156:ff21514d8981 613
AnnaBridge 156:ff21514d8981 614 This function changes the processor state to User Mode
AnnaBridge 156:ff21514d8981 615 */
AnnaBridge 156:ff21514d8981 616 // from rt_CMSIS.c
AnnaBridge 156:ff21514d8981 617 __arm static inline void __set_CPS_USR(void) {
AnnaBridge 156:ff21514d8981 618 __asm(
AnnaBridge 156:ff21514d8981 619 " ARM \n"
AnnaBridge 156:ff21514d8981 620
AnnaBridge 156:ff21514d8981 621 " CPS #0x10 \n" // MODE_USR
AnnaBridge 156:ff21514d8981 622 " BX LR\n");
AnnaBridge 156:ff21514d8981 623 }
AnnaBridge 156:ff21514d8981 624
AnnaBridge 156:ff21514d8981 625 /** \brief Set TTBR0
AnnaBridge 156:ff21514d8981 626
AnnaBridge 156:ff21514d8981 627 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 156:ff21514d8981 628
AnnaBridge 156:ff21514d8981 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 156:ff21514d8981 630 */
AnnaBridge 156:ff21514d8981 631 // from mmu_Renesas_RZ_A1.c
AnnaBridge 156:ff21514d8981 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 156:ff21514d8981 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
AnnaBridge 156:ff21514d8981 634 __ISB();
AnnaBridge 156:ff21514d8981 635 }
AnnaBridge 156:ff21514d8981 636
AnnaBridge 156:ff21514d8981 637 /** \brief Set DACR
AnnaBridge 156:ff21514d8981 638
AnnaBridge 156:ff21514d8981 639 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 156:ff21514d8981 640
AnnaBridge 156:ff21514d8981 641 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 156:ff21514d8981 642 */
AnnaBridge 156:ff21514d8981 643 // from mmu_Renesas_RZ_A1.c
AnnaBridge 156:ff21514d8981 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 156:ff21514d8981 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
AnnaBridge 156:ff21514d8981 646 __ISB();
AnnaBridge 156:ff21514d8981 647 }
AnnaBridge 156:ff21514d8981 648
AnnaBridge 156:ff21514d8981 649
AnnaBridge 156:ff21514d8981 650 /******************************** Cache and BTAC enable ****************************************************/
AnnaBridge 156:ff21514d8981 651 /** \brief Set SCTLR
AnnaBridge 156:ff21514d8981 652
AnnaBridge 156:ff21514d8981 653 This function assigns the given value to the System Control Register.
AnnaBridge 156:ff21514d8981 654
AnnaBridge 156:ff21514d8981 655 \param [in] sctlr System Control Register value to set
AnnaBridge 156:ff21514d8981 656 */
AnnaBridge 156:ff21514d8981 657 // from __enable_mmu()
AnnaBridge 156:ff21514d8981 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
AnnaBridge 156:ff21514d8981 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
AnnaBridge 156:ff21514d8981 660 }
AnnaBridge 156:ff21514d8981 661
AnnaBridge 156:ff21514d8981 662 /** \brief Get SCTLR
AnnaBridge 156:ff21514d8981 663
AnnaBridge 156:ff21514d8981 664 This function returns the value of the System Control Register.
AnnaBridge 156:ff21514d8981 665
AnnaBridge 156:ff21514d8981 666 \return System Control Register value
AnnaBridge 156:ff21514d8981 667 */
AnnaBridge 156:ff21514d8981 668 // from __enable_mmu()
AnnaBridge 156:ff21514d8981 669 __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 156:ff21514d8981 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
AnnaBridge 156:ff21514d8981 671 return __regSCTLR;
AnnaBridge 156:ff21514d8981 672 }
AnnaBridge 156:ff21514d8981 673
AnnaBridge 156:ff21514d8981 674 /** \brief Enable Caches
AnnaBridge 156:ff21514d8981 675
AnnaBridge 156:ff21514d8981 676 Enable Caches
AnnaBridge 156:ff21514d8981 677 */
AnnaBridge 156:ff21514d8981 678 // from system_Renesas_RZ_A1.c
AnnaBridge 156:ff21514d8981 679 __STATIC_INLINE void __enable_caches(void) {
AnnaBridge 156:ff21514d8981 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 156:ff21514d8981 681 }
AnnaBridge 156:ff21514d8981 682
AnnaBridge 156:ff21514d8981 683 /** \brief Enable BTAC
AnnaBridge 156:ff21514d8981 684
AnnaBridge 156:ff21514d8981 685 Enable BTAC
AnnaBridge 156:ff21514d8981 686 */
AnnaBridge 156:ff21514d8981 687 // from system_Renesas_RZ_A1.c
AnnaBridge 156:ff21514d8981 688 __STATIC_INLINE void __enable_btac(void) {
AnnaBridge 156:ff21514d8981 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 156:ff21514d8981 690 __ISB();
AnnaBridge 156:ff21514d8981 691 }
AnnaBridge 156:ff21514d8981 692
AnnaBridge 156:ff21514d8981 693 /** \brief Enable MMU
AnnaBridge 156:ff21514d8981 694
AnnaBridge 156:ff21514d8981 695 Enable MMU
AnnaBridge 156:ff21514d8981 696 */
AnnaBridge 156:ff21514d8981 697 // from system_Renesas_RZ_A1.c
AnnaBridge 156:ff21514d8981 698 __STATIC_INLINE void __enable_mmu(void) {
AnnaBridge 156:ff21514d8981 699 // Set M bit 0 to enable the MMU
AnnaBridge 156:ff21514d8981 700 // Set AFE bit to enable simplified access permissions model
AnnaBridge 156:ff21514d8981 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 156:ff21514d8981 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 156:ff21514d8981 703 __ISB();
AnnaBridge 156:ff21514d8981 704 }
AnnaBridge 156:ff21514d8981 705
AnnaBridge 156:ff21514d8981 706 /******************************** TLB maintenance operations ************************************************/
AnnaBridge 156:ff21514d8981 707 /** \brief Invalidate the whole tlb
AnnaBridge 156:ff21514d8981 708
AnnaBridge 156:ff21514d8981 709 TLBIALL. Invalidate the whole tlb
AnnaBridge 156:ff21514d8981 710 */
AnnaBridge 156:ff21514d8981 711 // from system_Renesas_RZ_A1.c
AnnaBridge 156:ff21514d8981 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
AnnaBridge 156:ff21514d8981 713 uint32_t val = 0;
AnnaBridge 156:ff21514d8981 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
AnnaBridge 156:ff21514d8981 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
AnnaBridge 156:ff21514d8981 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
AnnaBridge 156:ff21514d8981 717 __DSB();
AnnaBridge 156:ff21514d8981 718 __ISB();
AnnaBridge 156:ff21514d8981 719 }
AnnaBridge 156:ff21514d8981 720
AnnaBridge 156:ff21514d8981 721 /******************************** BTB maintenance operations ************************************************/
AnnaBridge 156:ff21514d8981 722 /** \brief Invalidate entire branch predictor array
AnnaBridge 156:ff21514d8981 723
AnnaBridge 156:ff21514d8981 724 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 156:ff21514d8981 725 */
AnnaBridge 156:ff21514d8981 726 // from system_Renesas_RZ_A1.c
AnnaBridge 156:ff21514d8981 727 __STATIC_INLINE void __v7_inv_btac(void) {
AnnaBridge 156:ff21514d8981 728 uint32_t val = 0;
AnnaBridge 156:ff21514d8981 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
AnnaBridge 156:ff21514d8981 730 __DSB(); //ensure completion of the invalidation
AnnaBridge 156:ff21514d8981 731 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 156:ff21514d8981 732 }
AnnaBridge 156:ff21514d8981 733
AnnaBridge 156:ff21514d8981 734
AnnaBridge 156:ff21514d8981 735 /******************************** L1 cache operations ******************************************************/
AnnaBridge 156:ff21514d8981 736
AnnaBridge 156:ff21514d8981 737 /** \brief Invalidate the whole I$
AnnaBridge 156:ff21514d8981 738
AnnaBridge 156:ff21514d8981 739 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 156:ff21514d8981 740 */
AnnaBridge 156:ff21514d8981 741 // from system_Renesas_RZ_A1.c
AnnaBridge 156:ff21514d8981 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
AnnaBridge 156:ff21514d8981 743 uint32_t val = 0;
AnnaBridge 156:ff21514d8981 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
AnnaBridge 156:ff21514d8981 745 __DSB(); //ensure completion of the invalidation
AnnaBridge 156:ff21514d8981 746 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 156:ff21514d8981 747 }
AnnaBridge 156:ff21514d8981 748
AnnaBridge 156:ff21514d8981 749 // from __v7_inv_dcache_all()
AnnaBridge 156:ff21514d8981 750 __arm static inline void __v7_all_cache(uint32_t op) {
AnnaBridge 156:ff21514d8981 751 __asm(
AnnaBridge 156:ff21514d8981 752 " ARM \n"
AnnaBridge 156:ff21514d8981 753
AnnaBridge 156:ff21514d8981 754 " PUSH {R4-R11} \n"
AnnaBridge 156:ff21514d8981 755
AnnaBridge 156:ff21514d8981 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
AnnaBridge 156:ff21514d8981 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
AnnaBridge 156:ff21514d8981 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
AnnaBridge 156:ff21514d8981 759 " BEQ Finished\n" // If 0, no need to clean
AnnaBridge 156:ff21514d8981 760
AnnaBridge 156:ff21514d8981 761 " MOV R10, #0\n" // R10 holds current cache level << 1
AnnaBridge 156:ff21514d8981 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
AnnaBridge 156:ff21514d8981 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
AnnaBridge 156:ff21514d8981 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
AnnaBridge 156:ff21514d8981 765 " CMP R1, #2 \n"
AnnaBridge 156:ff21514d8981 766 " BLT Skip \n" // No cache or only instruction cache at this level
AnnaBridge 156:ff21514d8981 767
AnnaBridge 156:ff21514d8981 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
AnnaBridge 156:ff21514d8981 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
AnnaBridge 156:ff21514d8981 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
AnnaBridge 156:ff21514d8981 771 " AND R2, R1, #7 \n" // Extract the line length field
AnnaBridge 156:ff21514d8981 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
AnnaBridge 156:ff21514d8981 773 " movw R4, #0x3FF \n"
AnnaBridge 156:ff21514d8981 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
AnnaBridge 156:ff21514d8981 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
AnnaBridge 156:ff21514d8981 776 " movw R7, #0x7FFF \n"
AnnaBridge 156:ff21514d8981 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
AnnaBridge 156:ff21514d8981 778
AnnaBridge 156:ff21514d8981 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
AnnaBridge 156:ff21514d8981 780
AnnaBridge 156:ff21514d8981 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
AnnaBridge 156:ff21514d8981 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
AnnaBridge 156:ff21514d8981 783 " CMP R0, #0 \n"
AnnaBridge 156:ff21514d8981 784 " BNE Dccsw \n"
AnnaBridge 156:ff21514d8981 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
AnnaBridge 156:ff21514d8981 786 " B cont \n"
AnnaBridge 156:ff21514d8981 787 "Dccsw: CMP R0, #1 \n"
AnnaBridge 156:ff21514d8981 788 " BNE Dccisw \n"
AnnaBridge 156:ff21514d8981 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
AnnaBridge 156:ff21514d8981 790 " B cont \n"
AnnaBridge 156:ff21514d8981 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
AnnaBridge 156:ff21514d8981 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
AnnaBridge 156:ff21514d8981 793 " BGE Loop3 \n"
AnnaBridge 156:ff21514d8981 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
AnnaBridge 156:ff21514d8981 795 " BGE Loop2 \n"
AnnaBridge 156:ff21514d8981 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
AnnaBridge 156:ff21514d8981 797 " CMP R3, R10 \n"
AnnaBridge 156:ff21514d8981 798 " BGT Loop1 \n"
AnnaBridge 156:ff21514d8981 799
AnnaBridge 156:ff21514d8981 800 "Finished: \n"
AnnaBridge 156:ff21514d8981 801 " DSB \n"
AnnaBridge 156:ff21514d8981 802 " POP {R4-R11} \n"
AnnaBridge 156:ff21514d8981 803 " BX lr \n" );
AnnaBridge 156:ff21514d8981 804 }
AnnaBridge 156:ff21514d8981 805
AnnaBridge 156:ff21514d8981 806 /** \brief Invalidate the whole D$
AnnaBridge 156:ff21514d8981 807
AnnaBridge 156:ff21514d8981 808 DCISW. Invalidate by Set/Way
AnnaBridge 156:ff21514d8981 809 */
AnnaBridge 156:ff21514d8981 810 // from system_Renesas_RZ_A1.c
AnnaBridge 156:ff21514d8981 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
AnnaBridge 156:ff21514d8981 812 __v7_all_cache(0);
AnnaBridge 156:ff21514d8981 813 }
AnnaBridge 156:ff21514d8981 814 /** \brief Clean the whole D$
AnnaBridge 156:ff21514d8981 815
AnnaBridge 156:ff21514d8981 816 DCCSW. Clean by Set/Way
AnnaBridge 156:ff21514d8981 817 */
AnnaBridge 156:ff21514d8981 818
AnnaBridge 156:ff21514d8981 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
AnnaBridge 156:ff21514d8981 820 __v7_all_cache(1);
AnnaBridge 156:ff21514d8981 821 }
AnnaBridge 156:ff21514d8981 822
AnnaBridge 156:ff21514d8981 823 /** \brief Clean and invalidate the whole D$
AnnaBridge 156:ff21514d8981 824
AnnaBridge 156:ff21514d8981 825 DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 156:ff21514d8981 826 */
AnnaBridge 156:ff21514d8981 827
AnnaBridge 156:ff21514d8981 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
AnnaBridge 156:ff21514d8981 829 __v7_all_cache(2);
AnnaBridge 156:ff21514d8981 830 }
AnnaBridge 156:ff21514d8981 831 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 156:ff21514d8981 832
AnnaBridge 156:ff21514d8981 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 156:ff21514d8981 834 */
AnnaBridge 156:ff21514d8981 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
AnnaBridge 156:ff21514d8981 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
AnnaBridge 156:ff21514d8981 837 __DMB();
AnnaBridge 156:ff21514d8981 838 }
AnnaBridge 156:ff21514d8981 839
AnnaBridge 156:ff21514d8981 840 #include "core_ca_mmu.h"
AnnaBridge 156:ff21514d8981 841
AnnaBridge 156:ff21514d8981 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
AnnaBridge 156:ff21514d8981 843 /* GNU gcc specific functions */
AnnaBridge 156:ff21514d8981 844
AnnaBridge 156:ff21514d8981 845 #define MODE_USR 0x10
AnnaBridge 156:ff21514d8981 846 #define MODE_FIQ 0x11
AnnaBridge 156:ff21514d8981 847 #define MODE_IRQ 0x12
AnnaBridge 156:ff21514d8981 848 #define MODE_SVC 0x13
AnnaBridge 156:ff21514d8981 849 #define MODE_MON 0x16
AnnaBridge 156:ff21514d8981 850 #define MODE_ABT 0x17
AnnaBridge 156:ff21514d8981 851 #define MODE_HYP 0x1A
AnnaBridge 156:ff21514d8981 852 #define MODE_UND 0x1B
AnnaBridge 156:ff21514d8981 853 #define MODE_SYS 0x1F
AnnaBridge 156:ff21514d8981 854
AnnaBridge 156:ff21514d8981 855
AnnaBridge 156:ff21514d8981 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
AnnaBridge 156:ff21514d8981 857 {
AnnaBridge 156:ff21514d8981 858 __ASM volatile ("cpsie i");
AnnaBridge 156:ff21514d8981 859 }
AnnaBridge 156:ff21514d8981 860
AnnaBridge 156:ff21514d8981 861 /** \brief Disable IRQ Interrupts
AnnaBridge 156:ff21514d8981 862
AnnaBridge 156:ff21514d8981 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge 156:ff21514d8981 864 Can only be executed in Privileged modes.
AnnaBridge 156:ff21514d8981 865 */
AnnaBridge 156:ff21514d8981 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
AnnaBridge 156:ff21514d8981 867 {
AnnaBridge 156:ff21514d8981 868 uint32_t result;
AnnaBridge 156:ff21514d8981 869
AnnaBridge 156:ff21514d8981 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
AnnaBridge 156:ff21514d8981 871 __ASM volatile ("cpsid i");
AnnaBridge 156:ff21514d8981 872 return(result & 0x80);
AnnaBridge 156:ff21514d8981 873 }
AnnaBridge 156:ff21514d8981 874
AnnaBridge 156:ff21514d8981 875
AnnaBridge 156:ff21514d8981 876 /** \brief Get APSR Register
AnnaBridge 156:ff21514d8981 877
AnnaBridge 156:ff21514d8981 878 This function returns the content of the APSR Register.
AnnaBridge 156:ff21514d8981 879
AnnaBridge 156:ff21514d8981 880 \return APSR Register value
AnnaBridge 156:ff21514d8981 881 */
AnnaBridge 156:ff21514d8981 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge 156:ff21514d8981 883 {
AnnaBridge 156:ff21514d8981 884 #if 1
AnnaBridge 156:ff21514d8981 885 register uint32_t __regAPSR;
AnnaBridge 156:ff21514d8981 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
AnnaBridge 156:ff21514d8981 887 #else
AnnaBridge 156:ff21514d8981 888 register uint32_t __regAPSR __ASM("apsr");
AnnaBridge 156:ff21514d8981 889 #endif
AnnaBridge 156:ff21514d8981 890 return(__regAPSR);
AnnaBridge 156:ff21514d8981 891 }
AnnaBridge 156:ff21514d8981 892
AnnaBridge 156:ff21514d8981 893
AnnaBridge 156:ff21514d8981 894 /** \brief Get CPSR Register
AnnaBridge 156:ff21514d8981 895
AnnaBridge 156:ff21514d8981 896 This function returns the content of the CPSR Register.
AnnaBridge 156:ff21514d8981 897
AnnaBridge 156:ff21514d8981 898 \return CPSR Register value
AnnaBridge 156:ff21514d8981 899 */
AnnaBridge 156:ff21514d8981 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
AnnaBridge 156:ff21514d8981 901 {
AnnaBridge 156:ff21514d8981 902 #if 1
AnnaBridge 156:ff21514d8981 903 register uint32_t __regCPSR;
AnnaBridge 156:ff21514d8981 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
AnnaBridge 156:ff21514d8981 905 #else
AnnaBridge 156:ff21514d8981 906 register uint32_t __regCPSR __ASM("cpsr");
AnnaBridge 156:ff21514d8981 907 #endif
AnnaBridge 156:ff21514d8981 908 return(__regCPSR);
AnnaBridge 156:ff21514d8981 909 }
AnnaBridge 156:ff21514d8981 910
AnnaBridge 156:ff21514d8981 911 #if 0
AnnaBridge 156:ff21514d8981 912 /** \brief Set Stack Pointer
AnnaBridge 156:ff21514d8981 913
AnnaBridge 156:ff21514d8981 914 This function assigns the given value to the current stack pointer.
AnnaBridge 156:ff21514d8981 915
AnnaBridge 156:ff21514d8981 916 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 156:ff21514d8981 917 */
AnnaBridge 156:ff21514d8981 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
AnnaBridge 156:ff21514d8981 919 {
AnnaBridge 156:ff21514d8981 920 register uint32_t __regSP __ASM("sp");
AnnaBridge 156:ff21514d8981 921 __regSP = topOfStack;
AnnaBridge 156:ff21514d8981 922 }
AnnaBridge 156:ff21514d8981 923 #endif
AnnaBridge 156:ff21514d8981 924
AnnaBridge 156:ff21514d8981 925 /** \brief Get link register
AnnaBridge 156:ff21514d8981 926
AnnaBridge 156:ff21514d8981 927 This function returns the value of the link register
AnnaBridge 156:ff21514d8981 928
AnnaBridge 156:ff21514d8981 929 \return Value of link register
AnnaBridge 156:ff21514d8981 930 */
AnnaBridge 156:ff21514d8981 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
AnnaBridge 156:ff21514d8981 932 {
AnnaBridge 156:ff21514d8981 933 register uint32_t __reglr __ASM("lr");
AnnaBridge 156:ff21514d8981 934 return(__reglr);
AnnaBridge 156:ff21514d8981 935 }
AnnaBridge 156:ff21514d8981 936
AnnaBridge 156:ff21514d8981 937 #if 0
AnnaBridge 156:ff21514d8981 938 /** \brief Set link register
AnnaBridge 156:ff21514d8981 939
AnnaBridge 156:ff21514d8981 940 This function sets the value of the link register
AnnaBridge 156:ff21514d8981 941
AnnaBridge 156:ff21514d8981 942 \param [in] lr LR value to set
AnnaBridge 156:ff21514d8981 943 */
AnnaBridge 156:ff21514d8981 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
AnnaBridge 156:ff21514d8981 945 {
AnnaBridge 156:ff21514d8981 946 register uint32_t __reglr __ASM("lr");
AnnaBridge 156:ff21514d8981 947 __reglr = lr;
AnnaBridge 156:ff21514d8981 948 }
AnnaBridge 156:ff21514d8981 949 #endif
AnnaBridge 156:ff21514d8981 950
AnnaBridge 156:ff21514d8981 951 /** \brief Set Process Stack Pointer
AnnaBridge 156:ff21514d8981 952
AnnaBridge 156:ff21514d8981 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
AnnaBridge 156:ff21514d8981 954
AnnaBridge 156:ff21514d8981 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 156:ff21514d8981 956 */
AnnaBridge 156:ff21514d8981 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 156:ff21514d8981 958 {
AnnaBridge 156:ff21514d8981 959 __asm__ volatile (
AnnaBridge 156:ff21514d8981 960 ".ARM;"
AnnaBridge 156:ff21514d8981 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
AnnaBridge 156:ff21514d8981 962
AnnaBridge 156:ff21514d8981 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
AnnaBridge 156:ff21514d8981 964 "MRS R1, CPSR;"
AnnaBridge 156:ff21514d8981 965 "CPS %0;" /* ;no effect in USR mode */
AnnaBridge 156:ff21514d8981 966 "MOV SP, R0;"
AnnaBridge 156:ff21514d8981 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
AnnaBridge 156:ff21514d8981 968 "ISB;"
AnnaBridge 156:ff21514d8981 969 //"BX LR;"
AnnaBridge 156:ff21514d8981 970 :
AnnaBridge 156:ff21514d8981 971 : "i"(MODE_SYS)
AnnaBridge 156:ff21514d8981 972 : "r0", "r1");
AnnaBridge 156:ff21514d8981 973 return;
AnnaBridge 156:ff21514d8981 974 }
AnnaBridge 156:ff21514d8981 975
AnnaBridge 156:ff21514d8981 976 /** \brief Set User Mode
AnnaBridge 156:ff21514d8981 977
AnnaBridge 156:ff21514d8981 978 This function changes the processor state to User Mode
AnnaBridge 156:ff21514d8981 979 */
AnnaBridge 156:ff21514d8981 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
AnnaBridge 156:ff21514d8981 981 {
AnnaBridge 156:ff21514d8981 982 __asm__ volatile (
AnnaBridge 156:ff21514d8981 983 ".ARM;"
AnnaBridge 156:ff21514d8981 984
AnnaBridge 156:ff21514d8981 985 "CPS %0;"
AnnaBridge 156:ff21514d8981 986 //"BX LR;"
AnnaBridge 156:ff21514d8981 987 :
AnnaBridge 156:ff21514d8981 988 : "i"(MODE_USR)
AnnaBridge 156:ff21514d8981 989 : );
AnnaBridge 156:ff21514d8981 990 return;
AnnaBridge 156:ff21514d8981 991 }
AnnaBridge 156:ff21514d8981 992
AnnaBridge 156:ff21514d8981 993
AnnaBridge 156:ff21514d8981 994 /** \brief Enable FIQ
AnnaBridge 156:ff21514d8981 995
AnnaBridge 156:ff21514d8981 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 156:ff21514d8981 997 Can only be executed in Privileged modes.
AnnaBridge 156:ff21514d8981 998 */
AnnaBridge 156:ff21514d8981 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
AnnaBridge 156:ff21514d8981 1000
AnnaBridge 156:ff21514d8981 1001
AnnaBridge 156:ff21514d8981 1002 /** \brief Disable FIQ
AnnaBridge 156:ff21514d8981 1003
AnnaBridge 156:ff21514d8981 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 156:ff21514d8981 1005 Can only be executed in Privileged modes.
AnnaBridge 156:ff21514d8981 1006 */
AnnaBridge 156:ff21514d8981 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
AnnaBridge 156:ff21514d8981 1008
AnnaBridge 156:ff21514d8981 1009
AnnaBridge 156:ff21514d8981 1010 /** \brief Get FPSCR
AnnaBridge 156:ff21514d8981 1011
AnnaBridge 156:ff21514d8981 1012 This function returns the current value of the Floating Point Status/Control register.
AnnaBridge 156:ff21514d8981 1013
AnnaBridge 156:ff21514d8981 1014 \return Floating Point Status/Control register value
AnnaBridge 156:ff21514d8981 1015 */
AnnaBridge 156:ff21514d8981 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 156:ff21514d8981 1017 {
AnnaBridge 156:ff21514d8981 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 156:ff21514d8981 1019 #if 1
AnnaBridge 156:ff21514d8981 1020 uint32_t result;
AnnaBridge 156:ff21514d8981 1021
AnnaBridge 156:ff21514d8981 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
AnnaBridge 156:ff21514d8981 1023 return (result);
AnnaBridge 156:ff21514d8981 1024 #else
AnnaBridge 156:ff21514d8981 1025 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 156:ff21514d8981 1026 return(__regfpscr);
AnnaBridge 156:ff21514d8981 1027 #endif
AnnaBridge 156:ff21514d8981 1028 #else
AnnaBridge 156:ff21514d8981 1029 return(0);
AnnaBridge 156:ff21514d8981 1030 #endif
AnnaBridge 156:ff21514d8981 1031 }
AnnaBridge 156:ff21514d8981 1032
AnnaBridge 156:ff21514d8981 1033
AnnaBridge 156:ff21514d8981 1034 /** \brief Set FPSCR
AnnaBridge 156:ff21514d8981 1035
AnnaBridge 156:ff21514d8981 1036 This function assigns the given value to the Floating Point Status/Control register.
AnnaBridge 156:ff21514d8981 1037
AnnaBridge 156:ff21514d8981 1038 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 156:ff21514d8981 1039 */
AnnaBridge 156:ff21514d8981 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 156:ff21514d8981 1041 {
AnnaBridge 156:ff21514d8981 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 156:ff21514d8981 1043 #if 1
AnnaBridge 156:ff21514d8981 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
AnnaBridge 156:ff21514d8981 1045 #else
AnnaBridge 156:ff21514d8981 1046 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 156:ff21514d8981 1047 __regfpscr = (fpscr);
AnnaBridge 156:ff21514d8981 1048 #endif
AnnaBridge 156:ff21514d8981 1049 #endif
AnnaBridge 156:ff21514d8981 1050 }
AnnaBridge 156:ff21514d8981 1051
AnnaBridge 156:ff21514d8981 1052 /** \brief Get FPEXC
AnnaBridge 156:ff21514d8981 1053
AnnaBridge 156:ff21514d8981 1054 This function returns the current value of the Floating Point Exception Control register.
AnnaBridge 156:ff21514d8981 1055
AnnaBridge 156:ff21514d8981 1056 \return Floating Point Exception Control register value
AnnaBridge 156:ff21514d8981 1057 */
AnnaBridge 156:ff21514d8981 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
AnnaBridge 156:ff21514d8981 1059 {
AnnaBridge 156:ff21514d8981 1060 #if (__FPU_PRESENT == 1)
AnnaBridge 156:ff21514d8981 1061 #if 1
AnnaBridge 156:ff21514d8981 1062 uint32_t result;
AnnaBridge 156:ff21514d8981 1063
AnnaBridge 156:ff21514d8981 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
AnnaBridge 156:ff21514d8981 1065 return (result);
AnnaBridge 156:ff21514d8981 1066 #else
AnnaBridge 156:ff21514d8981 1067 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 156:ff21514d8981 1068 return(__regfpexc);
AnnaBridge 156:ff21514d8981 1069 #endif
AnnaBridge 156:ff21514d8981 1070 #else
AnnaBridge 156:ff21514d8981 1071 return(0);
AnnaBridge 156:ff21514d8981 1072 #endif
AnnaBridge 156:ff21514d8981 1073 }
AnnaBridge 156:ff21514d8981 1074
AnnaBridge 156:ff21514d8981 1075
AnnaBridge 156:ff21514d8981 1076 /** \brief Set FPEXC
AnnaBridge 156:ff21514d8981 1077
AnnaBridge 156:ff21514d8981 1078 This function assigns the given value to the Floating Point Exception Control register.
AnnaBridge 156:ff21514d8981 1079
AnnaBridge 156:ff21514d8981 1080 \param [in] fpscr Floating Point Exception Control value to set
AnnaBridge 156:ff21514d8981 1081 */
AnnaBridge 156:ff21514d8981 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 156:ff21514d8981 1083 {
AnnaBridge 156:ff21514d8981 1084 #if (__FPU_PRESENT == 1)
AnnaBridge 156:ff21514d8981 1085 #if 1
AnnaBridge 156:ff21514d8981 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
AnnaBridge 156:ff21514d8981 1087 #else
AnnaBridge 156:ff21514d8981 1088 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 156:ff21514d8981 1089 __regfpexc = (fpexc);
AnnaBridge 156:ff21514d8981 1090 #endif
AnnaBridge 156:ff21514d8981 1091 #endif
AnnaBridge 156:ff21514d8981 1092 }
AnnaBridge 156:ff21514d8981 1093
AnnaBridge 156:ff21514d8981 1094 /** \brief Get CPACR
AnnaBridge 156:ff21514d8981 1095
AnnaBridge 156:ff21514d8981 1096 This function returns the current value of the Coprocessor Access Control register.
AnnaBridge 156:ff21514d8981 1097
AnnaBridge 156:ff21514d8981 1098 \return Coprocessor Access Control register value
AnnaBridge 156:ff21514d8981 1099 */
AnnaBridge 156:ff21514d8981 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
AnnaBridge 156:ff21514d8981 1101 {
AnnaBridge 156:ff21514d8981 1102 #if 1
AnnaBridge 156:ff21514d8981 1103 register uint32_t __regCPACR;
AnnaBridge 156:ff21514d8981 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
AnnaBridge 156:ff21514d8981 1105 #else
AnnaBridge 156:ff21514d8981 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 156:ff21514d8981 1107 #endif
AnnaBridge 156:ff21514d8981 1108 return __regCPACR;
AnnaBridge 156:ff21514d8981 1109 }
AnnaBridge 156:ff21514d8981 1110
AnnaBridge 156:ff21514d8981 1111 /** \brief Set CPACR
AnnaBridge 156:ff21514d8981 1112
AnnaBridge 156:ff21514d8981 1113 This function assigns the given value to the Coprocessor Access Control register.
AnnaBridge 156:ff21514d8981 1114
AnnaBridge 156:ff21514d8981 1115 \param [in] cpacr Coprocessor Acccess Control value to set
AnnaBridge 156:ff21514d8981 1116 */
AnnaBridge 156:ff21514d8981 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
AnnaBridge 156:ff21514d8981 1118 {
AnnaBridge 156:ff21514d8981 1119 #if 1
AnnaBridge 156:ff21514d8981 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
AnnaBridge 156:ff21514d8981 1121 #else
AnnaBridge 156:ff21514d8981 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 156:ff21514d8981 1123 __regCPACR = cpacr;
AnnaBridge 156:ff21514d8981 1124 #endif
AnnaBridge 156:ff21514d8981 1125 __ISB();
AnnaBridge 156:ff21514d8981 1126 }
AnnaBridge 156:ff21514d8981 1127
AnnaBridge 156:ff21514d8981 1128 /** \brief Get CBAR
AnnaBridge 156:ff21514d8981 1129
AnnaBridge 156:ff21514d8981 1130 This function returns the value of the Configuration Base Address register.
AnnaBridge 156:ff21514d8981 1131
AnnaBridge 156:ff21514d8981 1132 \return Configuration Base Address register value
AnnaBridge 156:ff21514d8981 1133 */
AnnaBridge 156:ff21514d8981 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
AnnaBridge 156:ff21514d8981 1135 #if 1
AnnaBridge 156:ff21514d8981 1136 register uint32_t __regCBAR;
AnnaBridge 156:ff21514d8981 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
AnnaBridge 156:ff21514d8981 1138 #else
AnnaBridge 156:ff21514d8981 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
AnnaBridge 156:ff21514d8981 1140 #endif
AnnaBridge 156:ff21514d8981 1141 return(__regCBAR);
AnnaBridge 156:ff21514d8981 1142 }
AnnaBridge 156:ff21514d8981 1143
AnnaBridge 156:ff21514d8981 1144 /** \brief Get TTBR0
AnnaBridge 156:ff21514d8981 1145
AnnaBridge 156:ff21514d8981 1146 This function returns the value of the Translation Table Base Register 0.
AnnaBridge 156:ff21514d8981 1147
AnnaBridge 156:ff21514d8981 1148 \return Translation Table Base Register 0 value
AnnaBridge 156:ff21514d8981 1149 */
AnnaBridge 156:ff21514d8981 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
AnnaBridge 156:ff21514d8981 1151 #if 1
AnnaBridge 156:ff21514d8981 1152 register uint32_t __regTTBR0;
AnnaBridge 156:ff21514d8981 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
AnnaBridge 156:ff21514d8981 1154 #else
AnnaBridge 156:ff21514d8981 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 156:ff21514d8981 1156 #endif
AnnaBridge 156:ff21514d8981 1157 return(__regTTBR0);
AnnaBridge 156:ff21514d8981 1158 }
AnnaBridge 156:ff21514d8981 1159
AnnaBridge 156:ff21514d8981 1160 /** \brief Set TTBR0
AnnaBridge 156:ff21514d8981 1161
AnnaBridge 156:ff21514d8981 1162 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 156:ff21514d8981 1163
AnnaBridge 156:ff21514d8981 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 156:ff21514d8981 1165 */
AnnaBridge 156:ff21514d8981 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 156:ff21514d8981 1167 #if 1
AnnaBridge 156:ff21514d8981 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
AnnaBridge 156:ff21514d8981 1169 #else
AnnaBridge 156:ff21514d8981 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 156:ff21514d8981 1171 __regTTBR0 = ttbr0;
AnnaBridge 156:ff21514d8981 1172 #endif
AnnaBridge 156:ff21514d8981 1173 __ISB();
AnnaBridge 156:ff21514d8981 1174 }
AnnaBridge 156:ff21514d8981 1175
AnnaBridge 156:ff21514d8981 1176 /** \brief Get DACR
AnnaBridge 156:ff21514d8981 1177
AnnaBridge 156:ff21514d8981 1178 This function returns the value of the Domain Access Control Register.
AnnaBridge 156:ff21514d8981 1179
AnnaBridge 156:ff21514d8981 1180 \return Domain Access Control Register value
AnnaBridge 156:ff21514d8981 1181 */
AnnaBridge 156:ff21514d8981 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
AnnaBridge 156:ff21514d8981 1183 #if 1
AnnaBridge 156:ff21514d8981 1184 register uint32_t __regDACR;
AnnaBridge 156:ff21514d8981 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
AnnaBridge 156:ff21514d8981 1186 #else
AnnaBridge 156:ff21514d8981 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 156:ff21514d8981 1188 #endif
AnnaBridge 156:ff21514d8981 1189 return(__regDACR);
AnnaBridge 156:ff21514d8981 1190 }
AnnaBridge 156:ff21514d8981 1191
AnnaBridge 156:ff21514d8981 1192 /** \brief Set DACR
AnnaBridge 156:ff21514d8981 1193
AnnaBridge 156:ff21514d8981 1194 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 156:ff21514d8981 1195
AnnaBridge 156:ff21514d8981 1196 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 156:ff21514d8981 1197 */
AnnaBridge 156:ff21514d8981 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 156:ff21514d8981 1199 #if 1
AnnaBridge 156:ff21514d8981 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
AnnaBridge 156:ff21514d8981 1201 #else
AnnaBridge 156:ff21514d8981 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 156:ff21514d8981 1203 __regDACR = dacr;
AnnaBridge 156:ff21514d8981 1204 #endif
AnnaBridge 156:ff21514d8981 1205 __ISB();
AnnaBridge 156:ff21514d8981 1206 }
AnnaBridge 156:ff21514d8981 1207
AnnaBridge 156:ff21514d8981 1208 /******************************** Cache and BTAC enable ****************************************************/
AnnaBridge 156:ff21514d8981 1209
AnnaBridge 156:ff21514d8981 1210 /** \brief Set SCTLR
AnnaBridge 156:ff21514d8981 1211
AnnaBridge 156:ff21514d8981 1212 This function assigns the given value to the System Control Register.
AnnaBridge 156:ff21514d8981 1213
AnnaBridge 156:ff21514d8981 1214 \param [in] sctlr System Control Register value to set
AnnaBridge 156:ff21514d8981 1215 */
AnnaBridge 156:ff21514d8981 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
AnnaBridge 156:ff21514d8981 1217 {
AnnaBridge 156:ff21514d8981 1218 #if 1
AnnaBridge 156:ff21514d8981 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
AnnaBridge 156:ff21514d8981 1220 #else
AnnaBridge 156:ff21514d8981 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 156:ff21514d8981 1222 __regSCTLR = sctlr;
AnnaBridge 156:ff21514d8981 1223 #endif
AnnaBridge 156:ff21514d8981 1224 }
AnnaBridge 156:ff21514d8981 1225
AnnaBridge 156:ff21514d8981 1226 /** \brief Get SCTLR
AnnaBridge 156:ff21514d8981 1227
AnnaBridge 156:ff21514d8981 1228 This function returns the value of the System Control Register.
AnnaBridge 156:ff21514d8981 1229
AnnaBridge 156:ff21514d8981 1230 \return System Control Register value
AnnaBridge 156:ff21514d8981 1231 */
AnnaBridge 156:ff21514d8981 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 156:ff21514d8981 1233 #if 1
AnnaBridge 156:ff21514d8981 1234 register uint32_t __regSCTLR;
AnnaBridge 156:ff21514d8981 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
AnnaBridge 156:ff21514d8981 1236 #else
AnnaBridge 156:ff21514d8981 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 156:ff21514d8981 1238 #endif
AnnaBridge 156:ff21514d8981 1239 return(__regSCTLR);
AnnaBridge 156:ff21514d8981 1240 }
AnnaBridge 156:ff21514d8981 1241
AnnaBridge 156:ff21514d8981 1242 /** \brief Enable Caches
AnnaBridge 156:ff21514d8981 1243
AnnaBridge 156:ff21514d8981 1244 Enable Caches
AnnaBridge 156:ff21514d8981 1245 */
AnnaBridge 156:ff21514d8981 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
AnnaBridge 156:ff21514d8981 1247 // Set I bit 12 to enable I Cache
AnnaBridge 156:ff21514d8981 1248 // Set C bit 2 to enable D Cache
AnnaBridge 156:ff21514d8981 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 156:ff21514d8981 1250 }
AnnaBridge 156:ff21514d8981 1251
AnnaBridge 156:ff21514d8981 1252 /** \brief Disable Caches
AnnaBridge 156:ff21514d8981 1253
AnnaBridge 156:ff21514d8981 1254 Disable Caches
AnnaBridge 156:ff21514d8981 1255 */
AnnaBridge 156:ff21514d8981 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
AnnaBridge 156:ff21514d8981 1257 // Clear I bit 12 to disable I Cache
AnnaBridge 156:ff21514d8981 1258 // Clear C bit 2 to disable D Cache
AnnaBridge 156:ff21514d8981 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
AnnaBridge 156:ff21514d8981 1260 __ISB();
AnnaBridge 156:ff21514d8981 1261 }
AnnaBridge 156:ff21514d8981 1262
AnnaBridge 156:ff21514d8981 1263 /** \brief Enable BTAC
AnnaBridge 156:ff21514d8981 1264
AnnaBridge 156:ff21514d8981 1265 Enable BTAC
AnnaBridge 156:ff21514d8981 1266 */
AnnaBridge 156:ff21514d8981 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
AnnaBridge 156:ff21514d8981 1268 // Set Z bit 11 to enable branch prediction
AnnaBridge 156:ff21514d8981 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 156:ff21514d8981 1270 __ISB();
AnnaBridge 156:ff21514d8981 1271 }
AnnaBridge 156:ff21514d8981 1272
AnnaBridge 156:ff21514d8981 1273 /** \brief Disable BTAC
AnnaBridge 156:ff21514d8981 1274
AnnaBridge 156:ff21514d8981 1275 Disable BTAC
AnnaBridge 156:ff21514d8981 1276 */
AnnaBridge 156:ff21514d8981 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
AnnaBridge 156:ff21514d8981 1278 // Clear Z bit 11 to disable branch prediction
AnnaBridge 156:ff21514d8981 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
AnnaBridge 156:ff21514d8981 1280 }
AnnaBridge 156:ff21514d8981 1281
AnnaBridge 156:ff21514d8981 1282
AnnaBridge 156:ff21514d8981 1283 /** \brief Enable MMU
AnnaBridge 156:ff21514d8981 1284
AnnaBridge 156:ff21514d8981 1285 Enable MMU
AnnaBridge 156:ff21514d8981 1286 */
AnnaBridge 156:ff21514d8981 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
AnnaBridge 156:ff21514d8981 1288 // Set M bit 0 to enable the MMU
AnnaBridge 156:ff21514d8981 1289 // Set AFE bit to enable simplified access permissions model
AnnaBridge 156:ff21514d8981 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 156:ff21514d8981 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 156:ff21514d8981 1292 __ISB();
AnnaBridge 156:ff21514d8981 1293 }
AnnaBridge 156:ff21514d8981 1294
AnnaBridge 156:ff21514d8981 1295 /** \brief Disable MMU
AnnaBridge 156:ff21514d8981 1296
AnnaBridge 156:ff21514d8981 1297 Disable MMU
AnnaBridge 156:ff21514d8981 1298 */
AnnaBridge 156:ff21514d8981 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
AnnaBridge 156:ff21514d8981 1300 // Clear M bit 0 to disable the MMU
AnnaBridge 156:ff21514d8981 1301 __set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge 156:ff21514d8981 1302 __ISB();
AnnaBridge 156:ff21514d8981 1303 }
AnnaBridge 156:ff21514d8981 1304
AnnaBridge 156:ff21514d8981 1305 /******************************** TLB maintenance operations ************************************************/
AnnaBridge 156:ff21514d8981 1306 /** \brief Invalidate the whole tlb
AnnaBridge 156:ff21514d8981 1307
AnnaBridge 156:ff21514d8981 1308 TLBIALL. Invalidate the whole tlb
AnnaBridge 156:ff21514d8981 1309 */
AnnaBridge 156:ff21514d8981 1310
AnnaBridge 156:ff21514d8981 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
AnnaBridge 156:ff21514d8981 1312 #if 1
AnnaBridge 156:ff21514d8981 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
AnnaBridge 156:ff21514d8981 1314 #else
AnnaBridge 156:ff21514d8981 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
AnnaBridge 156:ff21514d8981 1316 __TLBIALL = 0;
AnnaBridge 156:ff21514d8981 1317 #endif
AnnaBridge 156:ff21514d8981 1318 __DSB();
AnnaBridge 156:ff21514d8981 1319 __ISB();
AnnaBridge 156:ff21514d8981 1320 }
AnnaBridge 156:ff21514d8981 1321
AnnaBridge 156:ff21514d8981 1322 /******************************** BTB maintenance operations ************************************************/
AnnaBridge 156:ff21514d8981 1323 /** \brief Invalidate entire branch predictor array
AnnaBridge 156:ff21514d8981 1324
AnnaBridge 156:ff21514d8981 1325 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 156:ff21514d8981 1326 */
AnnaBridge 156:ff21514d8981 1327
AnnaBridge 156:ff21514d8981 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
AnnaBridge 156:ff21514d8981 1329 #if 1
AnnaBridge 156:ff21514d8981 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
AnnaBridge 156:ff21514d8981 1331 #else
AnnaBridge 156:ff21514d8981 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
AnnaBridge 156:ff21514d8981 1333 __BPIALL = 0;
AnnaBridge 156:ff21514d8981 1334 #endif
AnnaBridge 156:ff21514d8981 1335 __DSB(); //ensure completion of the invalidation
AnnaBridge 156:ff21514d8981 1336 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 156:ff21514d8981 1337 }
AnnaBridge 156:ff21514d8981 1338
AnnaBridge 156:ff21514d8981 1339
AnnaBridge 156:ff21514d8981 1340 /******************************** L1 cache operations ******************************************************/
AnnaBridge 156:ff21514d8981 1341
AnnaBridge 156:ff21514d8981 1342 /** \brief Invalidate the whole I$
AnnaBridge 156:ff21514d8981 1343
AnnaBridge 156:ff21514d8981 1344 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 156:ff21514d8981 1345 */
AnnaBridge 156:ff21514d8981 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
AnnaBridge 156:ff21514d8981 1347 #if 1
AnnaBridge 156:ff21514d8981 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
AnnaBridge 156:ff21514d8981 1349 #else
AnnaBridge 156:ff21514d8981 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
AnnaBridge 156:ff21514d8981 1351 __ICIALLU = 0;
AnnaBridge 156:ff21514d8981 1352 #endif
AnnaBridge 156:ff21514d8981 1353 __DSB(); //ensure completion of the invalidation
AnnaBridge 156:ff21514d8981 1354 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 156:ff21514d8981 1355 }
AnnaBridge 156:ff21514d8981 1356
AnnaBridge 156:ff21514d8981 1357 /** \brief Clean D$ by MVA
AnnaBridge 156:ff21514d8981 1358
AnnaBridge 156:ff21514d8981 1359 DCCMVAC. Data cache clean by MVA to PoC
AnnaBridge 156:ff21514d8981 1360 */
AnnaBridge 156:ff21514d8981 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
AnnaBridge 156:ff21514d8981 1362 #if 1
AnnaBridge 156:ff21514d8981 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
AnnaBridge 156:ff21514d8981 1364 #else
AnnaBridge 156:ff21514d8981 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
AnnaBridge 156:ff21514d8981 1366 __DCCMVAC = (uint32_t)va;
AnnaBridge 156:ff21514d8981 1367 #endif
AnnaBridge 156:ff21514d8981 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 156:ff21514d8981 1369 }
AnnaBridge 156:ff21514d8981 1370
AnnaBridge 156:ff21514d8981 1371 /** \brief Invalidate D$ by MVA
AnnaBridge 156:ff21514d8981 1372
AnnaBridge 156:ff21514d8981 1373 DCIMVAC. Data cache invalidate by MVA to PoC
AnnaBridge 156:ff21514d8981 1374 */
AnnaBridge 156:ff21514d8981 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
AnnaBridge 156:ff21514d8981 1376 #if 1
AnnaBridge 156:ff21514d8981 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
AnnaBridge 156:ff21514d8981 1378 #else
AnnaBridge 156:ff21514d8981 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
AnnaBridge 156:ff21514d8981 1380 __DCIMVAC = (uint32_t)va;
AnnaBridge 156:ff21514d8981 1381 #endif
AnnaBridge 156:ff21514d8981 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 156:ff21514d8981 1383 }
AnnaBridge 156:ff21514d8981 1384
AnnaBridge 156:ff21514d8981 1385 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 156:ff21514d8981 1386
AnnaBridge 156:ff21514d8981 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 156:ff21514d8981 1388 */
AnnaBridge 156:ff21514d8981 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
AnnaBridge 156:ff21514d8981 1390 #if 1
AnnaBridge 156:ff21514d8981 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
AnnaBridge 156:ff21514d8981 1392 #else
AnnaBridge 156:ff21514d8981 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
AnnaBridge 156:ff21514d8981 1394 __DCCIMVAC = (uint32_t)va;
AnnaBridge 156:ff21514d8981 1395 #endif
AnnaBridge 156:ff21514d8981 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 156:ff21514d8981 1397 }
AnnaBridge 156:ff21514d8981 1398
AnnaBridge 156:ff21514d8981 1399 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 156:ff21514d8981 1400
AnnaBridge 156:ff21514d8981 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
AnnaBridge 156:ff21514d8981 1402 */
AnnaBridge 156:ff21514d8981 1403 extern void __v7_all_cache(uint32_t op);
AnnaBridge 156:ff21514d8981 1404
AnnaBridge 156:ff21514d8981 1405
AnnaBridge 156:ff21514d8981 1406 /** \brief Invalidate the whole D$
AnnaBridge 156:ff21514d8981 1407
AnnaBridge 156:ff21514d8981 1408 DCISW. Invalidate by Set/Way
AnnaBridge 156:ff21514d8981 1409 */
AnnaBridge 156:ff21514d8981 1410
AnnaBridge 156:ff21514d8981 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
AnnaBridge 156:ff21514d8981 1412 __v7_all_cache(0);
AnnaBridge 156:ff21514d8981 1413 }
AnnaBridge 156:ff21514d8981 1414
AnnaBridge 156:ff21514d8981 1415 /** \brief Clean the whole D$
AnnaBridge 156:ff21514d8981 1416
AnnaBridge 156:ff21514d8981 1417 DCCSW. Clean by Set/Way
AnnaBridge 156:ff21514d8981 1418 */
AnnaBridge 156:ff21514d8981 1419
AnnaBridge 156:ff21514d8981 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
AnnaBridge 156:ff21514d8981 1421 __v7_all_cache(1);
AnnaBridge 156:ff21514d8981 1422 }
AnnaBridge 156:ff21514d8981 1423
AnnaBridge 156:ff21514d8981 1424 /** \brief Clean and invalidate the whole D$
AnnaBridge 156:ff21514d8981 1425
AnnaBridge 156:ff21514d8981 1426 DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 156:ff21514d8981 1427 */
AnnaBridge 156:ff21514d8981 1428
AnnaBridge 156:ff21514d8981 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
AnnaBridge 156:ff21514d8981 1430 __v7_all_cache(2);
AnnaBridge 156:ff21514d8981 1431 }
AnnaBridge 156:ff21514d8981 1432
AnnaBridge 156:ff21514d8981 1433 #include "core_ca_mmu.h"
AnnaBridge 156:ff21514d8981 1434
AnnaBridge 156:ff21514d8981 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
AnnaBridge 156:ff21514d8981 1436
AnnaBridge 156:ff21514d8981 1437 #error TASKING Compiler support not implemented for Cortex-A
AnnaBridge 156:ff21514d8981 1438
AnnaBridge 156:ff21514d8981 1439 #endif
AnnaBridge 156:ff21514d8981 1440
AnnaBridge 156:ff21514d8981 1441 /*@} end of CMSIS_Core_RegAccFunctions */
AnnaBridge 156:ff21514d8981 1442
AnnaBridge 156:ff21514d8981 1443
AnnaBridge 156:ff21514d8981 1444 #endif /* __CORE_CAFUNC_H__ */