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TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.h@157:e7ca05fa8600, 2017-11-09 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 09 11:14:10 2017 +0000
- Revision:
- 157:e7ca05fa8600
- Child:
- 167:84c0a372a020
Release 155 of the mbed library.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 157:e7ca05fa8600 | 1 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 2 | ****************************************************************************** |
| AnnaBridge | 157:e7ca05fa8600 | 3 | * @file stm32l0xx_hal_spi.h |
| AnnaBridge | 157:e7ca05fa8600 | 4 | * @author MCD Application Team |
| AnnaBridge | 157:e7ca05fa8600 | 5 | * @version V1.7.0 |
| AnnaBridge | 157:e7ca05fa8600 | 6 | * @date 31-May-2016 |
| AnnaBridge | 157:e7ca05fa8600 | 7 | * @brief Header file of SPI HAL module. |
| AnnaBridge | 157:e7ca05fa8600 | 8 | ****************************************************************************** |
| AnnaBridge | 157:e7ca05fa8600 | 9 | * @attention |
| AnnaBridge | 157:e7ca05fa8600 | 10 | * |
| AnnaBridge | 157:e7ca05fa8600 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 157:e7ca05fa8600 | 12 | * |
| AnnaBridge | 157:e7ca05fa8600 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 157:e7ca05fa8600 | 14 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 157:e7ca05fa8600 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 157:e7ca05fa8600 | 16 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 157:e7ca05fa8600 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 157:e7ca05fa8600 | 18 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 157:e7ca05fa8600 | 19 | * and/or other materials provided with the distribution. |
| AnnaBridge | 157:e7ca05fa8600 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 157:e7ca05fa8600 | 21 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 157:e7ca05fa8600 | 22 | * without specific prior written permission. |
| AnnaBridge | 157:e7ca05fa8600 | 23 | * |
| AnnaBridge | 157:e7ca05fa8600 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 157:e7ca05fa8600 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 157:e7ca05fa8600 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 157:e7ca05fa8600 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 157:e7ca05fa8600 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 157:e7ca05fa8600 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 157:e7ca05fa8600 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 157:e7ca05fa8600 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 157:e7ca05fa8600 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 157:e7ca05fa8600 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 157:e7ca05fa8600 | 34 | * |
| AnnaBridge | 157:e7ca05fa8600 | 35 | ****************************************************************************** |
| AnnaBridge | 157:e7ca05fa8600 | 36 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 37 | |
| AnnaBridge | 157:e7ca05fa8600 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 39 | #ifndef __STM32L0xx_HAL_SPI_H |
| AnnaBridge | 157:e7ca05fa8600 | 40 | #define __STM32L0xx_HAL_SPI_H |
| AnnaBridge | 157:e7ca05fa8600 | 41 | |
| AnnaBridge | 157:e7ca05fa8600 | 42 | #ifdef __cplusplus |
| AnnaBridge | 157:e7ca05fa8600 | 43 | extern "C" { |
| AnnaBridge | 157:e7ca05fa8600 | 44 | #endif |
| AnnaBridge | 157:e7ca05fa8600 | 45 | |
| AnnaBridge | 157:e7ca05fa8600 | 46 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 47 | #include "stm32l0xx_hal_def.h" |
| AnnaBridge | 157:e7ca05fa8600 | 48 | |
| AnnaBridge | 157:e7ca05fa8600 | 49 | /** @addtogroup STM32L0xx_HAL_Driver |
| AnnaBridge | 157:e7ca05fa8600 | 50 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 51 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 52 | |
| AnnaBridge | 157:e7ca05fa8600 | 53 | /** @defgroup SPI SPI |
| AnnaBridge | 157:e7ca05fa8600 | 54 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 55 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 56 | |
| AnnaBridge | 157:e7ca05fa8600 | 57 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 58 | /** @defgroup SPI_Exported_Types SPI Exported Types |
| AnnaBridge | 157:e7ca05fa8600 | 59 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 60 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 61 | |
| AnnaBridge | 157:e7ca05fa8600 | 62 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 63 | * @brief SPI Configuration Structure definition |
| AnnaBridge | 157:e7ca05fa8600 | 64 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 65 | typedef struct |
| AnnaBridge | 157:e7ca05fa8600 | 66 | { |
| AnnaBridge | 157:e7ca05fa8600 | 67 | uint32_t Mode; /*!< Specifies the SPI operating mode. |
| AnnaBridge | 157:e7ca05fa8600 | 68 | This parameter can be a value of @ref SPI_mode */ |
| AnnaBridge | 157:e7ca05fa8600 | 69 | |
| AnnaBridge | 157:e7ca05fa8600 | 70 | uint32_t Direction; /*!< Specifies the SPI Directional mode state. |
| AnnaBridge | 157:e7ca05fa8600 | 71 | This parameter can be a value of @ref SPI_Direction_mode */ |
| AnnaBridge | 157:e7ca05fa8600 | 72 | |
| AnnaBridge | 157:e7ca05fa8600 | 73 | uint32_t DataSize; /*!< Specifies the SPI data size. |
| AnnaBridge | 157:e7ca05fa8600 | 74 | This parameter can be a value of @ref SPI_data_size */ |
| AnnaBridge | 157:e7ca05fa8600 | 75 | |
| AnnaBridge | 157:e7ca05fa8600 | 76 | uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. |
| AnnaBridge | 157:e7ca05fa8600 | 77 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
| AnnaBridge | 157:e7ca05fa8600 | 78 | |
| AnnaBridge | 157:e7ca05fa8600 | 79 | uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. |
| AnnaBridge | 157:e7ca05fa8600 | 80 | This parameter can be a value of @ref SPI_Clock_Phase */ |
| AnnaBridge | 157:e7ca05fa8600 | 81 | |
| AnnaBridge | 157:e7ca05fa8600 | 82 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by |
| AnnaBridge | 157:e7ca05fa8600 | 83 | hardware (NSS pin) or by software using the SSI bit. |
| AnnaBridge | 157:e7ca05fa8600 | 84 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
| AnnaBridge | 157:e7ca05fa8600 | 85 | |
| AnnaBridge | 157:e7ca05fa8600 | 86 | uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
| AnnaBridge | 157:e7ca05fa8600 | 87 | used to configure the transmit and receive SCK clock. |
| AnnaBridge | 157:e7ca05fa8600 | 88 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| AnnaBridge | 157:e7ca05fa8600 | 89 | @note The communication clock is derived from the master |
| AnnaBridge | 157:e7ca05fa8600 | 90 | clock. The slave clock does not need to be set */ |
| AnnaBridge | 157:e7ca05fa8600 | 91 | |
| AnnaBridge | 157:e7ca05fa8600 | 92 | uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
| AnnaBridge | 157:e7ca05fa8600 | 93 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
| AnnaBridge | 157:e7ca05fa8600 | 94 | |
| AnnaBridge | 157:e7ca05fa8600 | 95 | uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. |
| AnnaBridge | 157:e7ca05fa8600 | 96 | This parameter can be a value of @ref SPI_TI_mode */ |
| AnnaBridge | 157:e7ca05fa8600 | 97 | |
| AnnaBridge | 157:e7ca05fa8600 | 98 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
| AnnaBridge | 157:e7ca05fa8600 | 99 | This parameter can be a value of @ref SPI_CRC_Calculation */ |
| AnnaBridge | 157:e7ca05fa8600 | 100 | |
| AnnaBridge | 157:e7ca05fa8600 | 101 | uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. |
| AnnaBridge | 157:e7ca05fa8600 | 102 | This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ |
| AnnaBridge | 157:e7ca05fa8600 | 103 | |
| AnnaBridge | 157:e7ca05fa8600 | 104 | }SPI_InitTypeDef; |
| AnnaBridge | 157:e7ca05fa8600 | 105 | |
| AnnaBridge | 157:e7ca05fa8600 | 106 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 107 | * @brief HAL SPI State structure definition |
| AnnaBridge | 157:e7ca05fa8600 | 108 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 109 | typedef enum |
| AnnaBridge | 157:e7ca05fa8600 | 110 | { |
| AnnaBridge | 157:e7ca05fa8600 | 111 | HAL_SPI_STATE_RESET = 0x00U, /*!< SPI not yet initialized or disabled */ |
| AnnaBridge | 157:e7ca05fa8600 | 112 | HAL_SPI_STATE_READY = 0x01U, /*!< SPI initialized and ready for use */ |
| AnnaBridge | 157:e7ca05fa8600 | 113 | HAL_SPI_STATE_BUSY = 0x02U, /*!< SPI process is ongoing */ |
| AnnaBridge | 157:e7ca05fa8600 | 114 | HAL_SPI_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ |
| AnnaBridge | 157:e7ca05fa8600 | 115 | HAL_SPI_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ |
| AnnaBridge | 157:e7ca05fa8600 | 116 | HAL_SPI_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ |
| AnnaBridge | 157:e7ca05fa8600 | 117 | HAL_SPI_STATE_ERROR = 0x03U /*!< SPI error state */ |
| AnnaBridge | 157:e7ca05fa8600 | 118 | |
| AnnaBridge | 157:e7ca05fa8600 | 119 | }HAL_SPI_StateTypeDef; |
| AnnaBridge | 157:e7ca05fa8600 | 120 | |
| AnnaBridge | 157:e7ca05fa8600 | 121 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 122 | * @brief SPI handle Structure definition |
| AnnaBridge | 157:e7ca05fa8600 | 123 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 124 | typedef struct __SPI_HandleTypeDef |
| AnnaBridge | 157:e7ca05fa8600 | 125 | { |
| AnnaBridge | 157:e7ca05fa8600 | 126 | SPI_TypeDef *Instance; /*!< SPI registers base address */ |
| AnnaBridge | 157:e7ca05fa8600 | 127 | |
| AnnaBridge | 157:e7ca05fa8600 | 128 | SPI_InitTypeDef Init; /*!< SPI communication parameters */ |
| AnnaBridge | 157:e7ca05fa8600 | 129 | |
| AnnaBridge | 157:e7ca05fa8600 | 130 | uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ |
| AnnaBridge | 157:e7ca05fa8600 | 131 | |
| AnnaBridge | 157:e7ca05fa8600 | 132 | uint16_t TxXferSize; /*!< SPI Tx transfer size */ |
| AnnaBridge | 157:e7ca05fa8600 | 133 | |
| AnnaBridge | 157:e7ca05fa8600 | 134 | uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ |
| AnnaBridge | 157:e7ca05fa8600 | 135 | |
| AnnaBridge | 157:e7ca05fa8600 | 136 | uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ |
| AnnaBridge | 157:e7ca05fa8600 | 137 | |
| AnnaBridge | 157:e7ca05fa8600 | 138 | uint16_t RxXferSize; /*!< SPI Rx transfer size */ |
| AnnaBridge | 157:e7ca05fa8600 | 139 | |
| AnnaBridge | 157:e7ca05fa8600 | 140 | uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ |
| AnnaBridge | 157:e7ca05fa8600 | 141 | |
| AnnaBridge | 157:e7ca05fa8600 | 142 | DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */ |
| AnnaBridge | 157:e7ca05fa8600 | 143 | |
| AnnaBridge | 157:e7ca05fa8600 | 144 | DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */ |
| AnnaBridge | 157:e7ca05fa8600 | 145 | |
| AnnaBridge | 157:e7ca05fa8600 | 146 | void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */ |
| AnnaBridge | 157:e7ca05fa8600 | 147 | |
| AnnaBridge | 157:e7ca05fa8600 | 148 | void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */ |
| AnnaBridge | 157:e7ca05fa8600 | 149 | |
| AnnaBridge | 157:e7ca05fa8600 | 150 | HAL_LockTypeDef Lock; /*!< SPI locking object */ |
| AnnaBridge | 157:e7ca05fa8600 | 151 | |
| AnnaBridge | 157:e7ca05fa8600 | 152 | __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ |
| AnnaBridge | 157:e7ca05fa8600 | 153 | |
| AnnaBridge | 157:e7ca05fa8600 | 154 | __IO uint32_t ErrorCode; /*!< SPI Error code */ |
| AnnaBridge | 157:e7ca05fa8600 | 155 | |
| AnnaBridge | 157:e7ca05fa8600 | 156 | }SPI_HandleTypeDef; |
| AnnaBridge | 157:e7ca05fa8600 | 157 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 158 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 159 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 160 | |
| AnnaBridge | 157:e7ca05fa8600 | 161 | |
| AnnaBridge | 157:e7ca05fa8600 | 162 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 163 | |
| AnnaBridge | 157:e7ca05fa8600 | 164 | /** @defgroup SPI_Exported_Constants SPI Exported Constants |
| AnnaBridge | 157:e7ca05fa8600 | 165 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 166 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 167 | |
| AnnaBridge | 157:e7ca05fa8600 | 168 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 169 | * @defgroup SPI_ErrorCode SPI Error Code |
| AnnaBridge | 157:e7ca05fa8600 | 170 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 171 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 172 | #define HAL_SPI_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ |
| AnnaBridge | 157:e7ca05fa8600 | 173 | #define HAL_SPI_ERROR_MODF ((uint32_t)0x01U) /*!< MODF error */ |
| AnnaBridge | 157:e7ca05fa8600 | 174 | #define HAL_SPI_ERROR_CRC ((uint32_t)0x02U) /*!< CRC error */ |
| AnnaBridge | 157:e7ca05fa8600 | 175 | #define HAL_SPI_ERROR_OVR ((uint32_t)0x04U) /*!< OVR error */ |
| AnnaBridge | 157:e7ca05fa8600 | 176 | #define HAL_SPI_ERROR_FRE ((uint32_t)0x08U) /*!< FRE error */ |
| AnnaBridge | 157:e7ca05fa8600 | 177 | #define HAL_SPI_ERROR_DMA ((uint32_t)0x10U) /*!< DMA transfer error */ |
| AnnaBridge | 157:e7ca05fa8600 | 178 | #define HAL_SPI_ERROR_FLAG ((uint32_t)0x20U) /*!< Flag: RXNE,TXE, BSY */ |
| AnnaBridge | 157:e7ca05fa8600 | 179 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 180 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 181 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 182 | |
| AnnaBridge | 157:e7ca05fa8600 | 183 | /** @defgroup SPI_mode SPI mode |
| AnnaBridge | 157:e7ca05fa8600 | 184 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 185 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 186 | #define SPI_MODE_SLAVE ((uint32_t)0x00000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 187 | #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
| AnnaBridge | 157:e7ca05fa8600 | 188 | |
| AnnaBridge | 157:e7ca05fa8600 | 189 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 190 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 191 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 192 | |
| AnnaBridge | 157:e7ca05fa8600 | 193 | /** @defgroup SPI_Direction_mode SPI Direction mode |
| AnnaBridge | 157:e7ca05fa8600 | 194 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 195 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 196 | #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 197 | #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
| AnnaBridge | 157:e7ca05fa8600 | 198 | #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
| AnnaBridge | 157:e7ca05fa8600 | 199 | |
| AnnaBridge | 157:e7ca05fa8600 | 200 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 201 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 202 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 203 | |
| AnnaBridge | 157:e7ca05fa8600 | 204 | /** @defgroup SPI_data_size SPI data size |
| AnnaBridge | 157:e7ca05fa8600 | 205 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 206 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 207 | #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 208 | #define SPI_DATASIZE_16BIT SPI_CR1_DFF |
| AnnaBridge | 157:e7ca05fa8600 | 209 | |
| AnnaBridge | 157:e7ca05fa8600 | 210 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 211 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 212 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 213 | |
| AnnaBridge | 157:e7ca05fa8600 | 214 | /** @defgroup SPI_Clock_Polarity SPI Clock Polarity |
| AnnaBridge | 157:e7ca05fa8600 | 215 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 216 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 217 | #define SPI_POLARITY_LOW ((uint32_t)0x00000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 218 | #define SPI_POLARITY_HIGH SPI_CR1_CPOL |
| AnnaBridge | 157:e7ca05fa8600 | 219 | |
| AnnaBridge | 157:e7ca05fa8600 | 220 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 221 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 222 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 223 | |
| AnnaBridge | 157:e7ca05fa8600 | 224 | /** @defgroup SPI_Clock_Phase SPI Clock Phase |
| AnnaBridge | 157:e7ca05fa8600 | 225 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 226 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 227 | #define SPI_PHASE_1EDGE ((uint32_t)0x00000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 228 | #define SPI_PHASE_2EDGE SPI_CR1_CPHA |
| AnnaBridge | 157:e7ca05fa8600 | 229 | |
| AnnaBridge | 157:e7ca05fa8600 | 230 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 231 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 232 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 233 | |
| AnnaBridge | 157:e7ca05fa8600 | 234 | /** @defgroup SPI_Slave_Select_management SPI Slave Select management |
| AnnaBridge | 157:e7ca05fa8600 | 235 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 236 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 237 | #define SPI_NSS_SOFT SPI_CR1_SSM |
| AnnaBridge | 157:e7ca05fa8600 | 238 | #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 239 | #define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16U)) |
| AnnaBridge | 157:e7ca05fa8600 | 240 | |
| AnnaBridge | 157:e7ca05fa8600 | 241 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 242 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 243 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 244 | |
| AnnaBridge | 157:e7ca05fa8600 | 245 | /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler |
| AnnaBridge | 157:e7ca05fa8600 | 246 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 247 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 248 | #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 249 | #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) |
| AnnaBridge | 157:e7ca05fa8600 | 250 | #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) |
| AnnaBridge | 157:e7ca05fa8600 | 251 | #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) |
| AnnaBridge | 157:e7ca05fa8600 | 252 | #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) |
| AnnaBridge | 157:e7ca05fa8600 | 253 | #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) |
| AnnaBridge | 157:e7ca05fa8600 | 254 | #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) |
| AnnaBridge | 157:e7ca05fa8600 | 255 | #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) |
| AnnaBridge | 157:e7ca05fa8600 | 256 | |
| AnnaBridge | 157:e7ca05fa8600 | 257 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 258 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 259 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 260 | |
| AnnaBridge | 157:e7ca05fa8600 | 261 | /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission |
| AnnaBridge | 157:e7ca05fa8600 | 262 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 263 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 264 | #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 265 | #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
| AnnaBridge | 157:e7ca05fa8600 | 266 | |
| AnnaBridge | 157:e7ca05fa8600 | 267 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 268 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 269 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 270 | |
| AnnaBridge | 157:e7ca05fa8600 | 271 | /** @defgroup SPI_TI_mode SPI TI mode |
| AnnaBridge | 157:e7ca05fa8600 | 272 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 273 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 274 | #define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 275 | #define SPI_TIMODE_ENABLE SPI_CR2_FRF |
| AnnaBridge | 157:e7ca05fa8600 | 276 | |
| AnnaBridge | 157:e7ca05fa8600 | 277 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 278 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 279 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 280 | |
| AnnaBridge | 157:e7ca05fa8600 | 281 | /** @defgroup SPI_CRC_Calculation SPI CRC Calculation |
| AnnaBridge | 157:e7ca05fa8600 | 282 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 283 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 284 | #define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) |
| AnnaBridge | 157:e7ca05fa8600 | 285 | #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
| AnnaBridge | 157:e7ca05fa8600 | 286 | |
| AnnaBridge | 157:e7ca05fa8600 | 287 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 288 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 289 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 290 | |
| AnnaBridge | 157:e7ca05fa8600 | 291 | /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition |
| AnnaBridge | 157:e7ca05fa8600 | 292 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 293 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 294 | #define SPI_IT_TXE SPI_CR2_TXEIE |
| AnnaBridge | 157:e7ca05fa8600 | 295 | #define SPI_IT_RXNE SPI_CR2_RXNEIE |
| AnnaBridge | 157:e7ca05fa8600 | 296 | #define SPI_IT_ERR SPI_CR2_ERRIE |
| AnnaBridge | 157:e7ca05fa8600 | 297 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 298 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 299 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 300 | |
| AnnaBridge | 157:e7ca05fa8600 | 301 | /** @defgroup SPI_Flag_definition SPI Flag definition |
| AnnaBridge | 157:e7ca05fa8600 | 302 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 303 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 304 | #define SPI_FLAG_RXNE SPI_SR_RXNE |
| AnnaBridge | 157:e7ca05fa8600 | 305 | #define SPI_FLAG_TXE SPI_SR_TXE |
| AnnaBridge | 157:e7ca05fa8600 | 306 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR |
| AnnaBridge | 157:e7ca05fa8600 | 307 | #define SPI_FLAG_MODF SPI_SR_MODF |
| AnnaBridge | 157:e7ca05fa8600 | 308 | #define SPI_FLAG_OVR SPI_SR_OVR |
| AnnaBridge | 157:e7ca05fa8600 | 309 | #define SPI_FLAG_BSY SPI_SR_BSY |
| AnnaBridge | 157:e7ca05fa8600 | 310 | #define SPI_FLAG_FRE SPI_SR_FRE |
| AnnaBridge | 157:e7ca05fa8600 | 311 | |
| AnnaBridge | 157:e7ca05fa8600 | 312 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 313 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 314 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 315 | |
| AnnaBridge | 157:e7ca05fa8600 | 316 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 317 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 318 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 319 | |
| AnnaBridge | 157:e7ca05fa8600 | 320 | |
| AnnaBridge | 157:e7ca05fa8600 | 321 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 322 | /** @defgroup SPI_Exported_Macros SPI Exported Macros |
| AnnaBridge | 157:e7ca05fa8600 | 323 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 324 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 325 | |
| AnnaBridge | 157:e7ca05fa8600 | 326 | /** @brief Reset SPI handle state |
| AnnaBridge | 157:e7ca05fa8600 | 327 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 157:e7ca05fa8600 | 328 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 329 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 330 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 331 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
| AnnaBridge | 157:e7ca05fa8600 | 332 | |
| AnnaBridge | 157:e7ca05fa8600 | 333 | /** @brief Enable the specified SPI interrupts. |
| AnnaBridge | 157:e7ca05fa8600 | 334 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 157:e7ca05fa8600 | 335 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 336 | * @param __INTERRUPT__: specifies the interrupt source to enable. |
| AnnaBridge | 157:e7ca05fa8600 | 337 | * This parameter can be one of the following values: |
| AnnaBridge | 157:e7ca05fa8600 | 338 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 157:e7ca05fa8600 | 339 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 157:e7ca05fa8600 | 340 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 157:e7ca05fa8600 | 341 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 342 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 343 | #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
| AnnaBridge | 157:e7ca05fa8600 | 344 | |
| AnnaBridge | 157:e7ca05fa8600 | 345 | /** @brief Disable the specified SPI interrupts. |
| AnnaBridge | 157:e7ca05fa8600 | 346 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 157:e7ca05fa8600 | 347 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 348 | * @param __INTERRUPT__: specifies the interrupt source to disable. |
| AnnaBridge | 157:e7ca05fa8600 | 349 | * This parameter can be one of the following values: |
| AnnaBridge | 157:e7ca05fa8600 | 350 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 157:e7ca05fa8600 | 351 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 157:e7ca05fa8600 | 352 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 157:e7ca05fa8600 | 353 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 354 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 355 | #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
| AnnaBridge | 157:e7ca05fa8600 | 356 | |
| AnnaBridge | 157:e7ca05fa8600 | 357 | /** @brief Check if the specified SPI interrupt source is enabled or disabled. |
| AnnaBridge | 157:e7ca05fa8600 | 358 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 157:e7ca05fa8600 | 359 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 360 | * @param __INTERRUPT__: specifies the SPI interrupt source to check. |
| AnnaBridge | 157:e7ca05fa8600 | 361 | * This parameter can be one of the following values: |
| AnnaBridge | 157:e7ca05fa8600 | 362 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 157:e7ca05fa8600 | 363 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 157:e7ca05fa8600 | 364 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 157:e7ca05fa8600 | 365 | * @retval The new state of __IT__ (TRUE or FALSE). |
| AnnaBridge | 157:e7ca05fa8600 | 366 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 367 | #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| AnnaBridge | 157:e7ca05fa8600 | 368 | |
| AnnaBridge | 157:e7ca05fa8600 | 369 | /** @brief Check whether the specified SPI flag is set or not. |
| AnnaBridge | 157:e7ca05fa8600 | 370 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 157:e7ca05fa8600 | 371 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 372 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 157:e7ca05fa8600 | 373 | * This parameter can be one of the following values: |
| AnnaBridge | 157:e7ca05fa8600 | 374 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
| AnnaBridge | 157:e7ca05fa8600 | 375 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
| AnnaBridge | 157:e7ca05fa8600 | 376 | * @arg SPI_FLAG_CRCERR: CRC error flag |
| AnnaBridge | 157:e7ca05fa8600 | 377 | * @arg SPI_FLAG_MODF: Mode fault flag |
| AnnaBridge | 157:e7ca05fa8600 | 378 | * @arg SPI_FLAG_OVR: Overrun flag |
| AnnaBridge | 157:e7ca05fa8600 | 379 | * @arg SPI_FLAG_BSY: Busy flag |
| AnnaBridge | 157:e7ca05fa8600 | 380 | * @arg SPI_FLAG_FRE: Frame format error flag |
| AnnaBridge | 157:e7ca05fa8600 | 381 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 157:e7ca05fa8600 | 382 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 383 | #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 157:e7ca05fa8600 | 384 | |
| AnnaBridge | 157:e7ca05fa8600 | 385 | /** @brief Clear the SPI CRCERR pending flag. |
| AnnaBridge | 157:e7ca05fa8600 | 386 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 157:e7ca05fa8600 | 387 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 388 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 389 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 390 | #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) |
| AnnaBridge | 157:e7ca05fa8600 | 391 | |
| AnnaBridge | 157:e7ca05fa8600 | 392 | /** @brief Clear the SPI MODF pending flag. |
| AnnaBridge | 157:e7ca05fa8600 | 393 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 157:e7ca05fa8600 | 394 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 395 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 396 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 397 | #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
| AnnaBridge | 157:e7ca05fa8600 | 398 | do{ \ |
| AnnaBridge | 157:e7ca05fa8600 | 399 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 157:e7ca05fa8600 | 400 | tmpreg = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 157:e7ca05fa8600 | 401 | (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ |
| AnnaBridge | 157:e7ca05fa8600 | 402 | UNUSED(tmpreg); \ |
| AnnaBridge | 157:e7ca05fa8600 | 403 | } while(0) |
| AnnaBridge | 157:e7ca05fa8600 | 404 | |
| AnnaBridge | 157:e7ca05fa8600 | 405 | /** @brief Clear the SPI OVR pending flag. |
| AnnaBridge | 157:e7ca05fa8600 | 406 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 157:e7ca05fa8600 | 407 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 408 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 409 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 410 | #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
| AnnaBridge | 157:e7ca05fa8600 | 411 | do{ \ |
| AnnaBridge | 157:e7ca05fa8600 | 412 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 157:e7ca05fa8600 | 413 | tmpreg = (__HANDLE__)->Instance->DR; \ |
| AnnaBridge | 157:e7ca05fa8600 | 414 | tmpreg = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 157:e7ca05fa8600 | 415 | UNUSED(tmpreg); \ |
| AnnaBridge | 157:e7ca05fa8600 | 416 | } while(0) |
| AnnaBridge | 157:e7ca05fa8600 | 417 | |
| AnnaBridge | 157:e7ca05fa8600 | 418 | /** @brief Clear the SPI FRE pending flag. |
| AnnaBridge | 157:e7ca05fa8600 | 419 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 157:e7ca05fa8600 | 420 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 421 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 422 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 423 | #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ |
| AnnaBridge | 157:e7ca05fa8600 | 424 | do{ \ |
| AnnaBridge | 157:e7ca05fa8600 | 425 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 157:e7ca05fa8600 | 426 | tmpreg = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 157:e7ca05fa8600 | 427 | UNUSED(tmpreg); \ |
| AnnaBridge | 157:e7ca05fa8600 | 428 | } while(0) |
| AnnaBridge | 157:e7ca05fa8600 | 429 | |
| AnnaBridge | 157:e7ca05fa8600 | 430 | /** @brief Enables the SPI. |
| AnnaBridge | 157:e7ca05fa8600 | 431 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 157:e7ca05fa8600 | 432 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 433 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 434 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 435 | #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
| AnnaBridge | 157:e7ca05fa8600 | 436 | |
| AnnaBridge | 157:e7ca05fa8600 | 437 | /** @brief Disables the SPI. |
| AnnaBridge | 157:e7ca05fa8600 | 438 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 157:e7ca05fa8600 | 439 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 440 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 441 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 442 | #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
| AnnaBridge | 157:e7ca05fa8600 | 443 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 444 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 445 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 446 | |
| AnnaBridge | 157:e7ca05fa8600 | 447 | |
| AnnaBridge | 157:e7ca05fa8600 | 448 | /* Private macros -----------------------------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 449 | /** @defgroup SPI_Private_Macros SPI Private Macros |
| AnnaBridge | 157:e7ca05fa8600 | 450 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 451 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 452 | |
| AnnaBridge | 157:e7ca05fa8600 | 453 | /** @brief Checks if SPI Mode parameter is in allowed range. |
| AnnaBridge | 157:e7ca05fa8600 | 454 | * @param __MODE__: specifies the SPI Mode. |
| AnnaBridge | 157:e7ca05fa8600 | 455 | * This parameter can be a value of @ref SPI_mode |
| AnnaBridge | 157:e7ca05fa8600 | 456 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 457 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 458 | #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER)) |
| AnnaBridge | 157:e7ca05fa8600 | 459 | |
| AnnaBridge | 157:e7ca05fa8600 | 460 | /** @brief Checks if SPI Direction Mode parameter is in allowed range. |
| AnnaBridge | 157:e7ca05fa8600 | 461 | * @param __MODE__: specifies the SPI Direction Mode. |
| AnnaBridge | 157:e7ca05fa8600 | 462 | * This parameter can be a value of @ref SPI_Direction_mode |
| AnnaBridge | 157:e7ca05fa8600 | 463 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 464 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 465 | #define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 466 | ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 467 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
| AnnaBridge | 157:e7ca05fa8600 | 468 | |
| AnnaBridge | 157:e7ca05fa8600 | 469 | /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. |
| AnnaBridge | 157:e7ca05fa8600 | 470 | * @param __MODE__: specifies the SPI Direction Mode. |
| AnnaBridge | 157:e7ca05fa8600 | 471 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 472 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 473 | #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 474 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
| AnnaBridge | 157:e7ca05fa8600 | 475 | |
| AnnaBridge | 157:e7ca05fa8600 | 476 | /** @brief Checks if SPI Direction Mode parameter is 2 lines. |
| AnnaBridge | 157:e7ca05fa8600 | 477 | * @param __MODE__: specifies the SPI Direction Mode. |
| AnnaBridge | 157:e7ca05fa8600 | 478 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 479 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 480 | #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) |
| AnnaBridge | 157:e7ca05fa8600 | 481 | |
| AnnaBridge | 157:e7ca05fa8600 | 482 | /** @brief Checks if SPI Data Size parameter is in allowed range. |
| AnnaBridge | 157:e7ca05fa8600 | 483 | * @param __DATASIZE__: specifies the SPI Data Size. |
| AnnaBridge | 157:e7ca05fa8600 | 484 | * This parameter can be a value of @ref SPI_data_size |
| AnnaBridge | 157:e7ca05fa8600 | 485 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 486 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 487 | #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 488 | ((__DATASIZE__) == SPI_DATASIZE_8BIT)) |
| AnnaBridge | 157:e7ca05fa8600 | 489 | |
| AnnaBridge | 157:e7ca05fa8600 | 490 | /** @brief Checks if SPI Serial clock steady state parameter is in allowed range. |
| AnnaBridge | 157:e7ca05fa8600 | 491 | * @param __CPOL__: specifies the SPI serial clock steady state. |
| AnnaBridge | 157:e7ca05fa8600 | 492 | * This parameter can be a value of @ref SPI_Clock_Polarity |
| AnnaBridge | 157:e7ca05fa8600 | 493 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 494 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 495 | #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 496 | ((__CPOL__) == SPI_POLARITY_HIGH)) |
| AnnaBridge | 157:e7ca05fa8600 | 497 | |
| AnnaBridge | 157:e7ca05fa8600 | 498 | /** @brief Checks if SPI Clock Phase parameter is in allowed range. |
| AnnaBridge | 157:e7ca05fa8600 | 499 | * @param __CPHA__: specifies the SPI Clock Phase. |
| AnnaBridge | 157:e7ca05fa8600 | 500 | * This parameter can be a value of @ref SPI_Clock_Phase |
| AnnaBridge | 157:e7ca05fa8600 | 501 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 502 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 503 | #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 504 | ((__CPHA__) == SPI_PHASE_2EDGE)) |
| AnnaBridge | 157:e7ca05fa8600 | 505 | |
| AnnaBridge | 157:e7ca05fa8600 | 506 | /** @brief Checks if SPI Slave select parameter is in allowed range. |
| AnnaBridge | 157:e7ca05fa8600 | 507 | * @param __NSS__: specifies the SPI Slave Slelect management parameter. |
| AnnaBridge | 157:e7ca05fa8600 | 508 | * This parameter can be a value of @ref SPI_Slave_Select_management |
| AnnaBridge | 157:e7ca05fa8600 | 509 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 510 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 511 | #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 512 | ((__NSS__) == SPI_NSS_HARD_INPUT) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 513 | ((__NSS__) == SPI_NSS_HARD_OUTPUT)) |
| AnnaBridge | 157:e7ca05fa8600 | 514 | |
| AnnaBridge | 157:e7ca05fa8600 | 515 | /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. |
| AnnaBridge | 157:e7ca05fa8600 | 516 | * @param __PRESCALER__: specifies the SPI Baudrate prescaler. |
| AnnaBridge | 157:e7ca05fa8600 | 517 | * This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| AnnaBridge | 157:e7ca05fa8600 | 518 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 519 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 520 | #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 521 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 522 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 523 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 524 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 525 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 526 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 527 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) |
| AnnaBridge | 157:e7ca05fa8600 | 528 | |
| AnnaBridge | 157:e7ca05fa8600 | 529 | /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. |
| AnnaBridge | 157:e7ca05fa8600 | 530 | * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). |
| AnnaBridge | 157:e7ca05fa8600 | 531 | * This parameter can be a value of @ref SPI_MSB_LSB_transmission |
| AnnaBridge | 157:e7ca05fa8600 | 532 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 533 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 534 | #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 535 | ((__BIT__) == SPI_FIRSTBIT_LSB)) |
| AnnaBridge | 157:e7ca05fa8600 | 536 | |
| AnnaBridge | 157:e7ca05fa8600 | 537 | /** @brief Checks if SPI TI mode parameter is in allowed range. |
| AnnaBridge | 157:e7ca05fa8600 | 538 | * @param __MODE__: specifies the SPI TI mode. |
| AnnaBridge | 157:e7ca05fa8600 | 539 | * This parameter can be a value of @ref SPI_TI_mode |
| AnnaBridge | 157:e7ca05fa8600 | 540 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 541 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 542 | #define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 543 | ((__MODE__) == SPI_TIMODE_ENABLE)) |
| AnnaBridge | 157:e7ca05fa8600 | 544 | /** @brief Checks if SPI CRC calculation enabled state is in allowed range. |
| AnnaBridge | 157:e7ca05fa8600 | 545 | * @param __CALCULATION__: specifies the SPI CRC calculation enable state. |
| AnnaBridge | 157:e7ca05fa8600 | 546 | * This parameter can be a value of @ref SPI_CRC_Calculation |
| AnnaBridge | 157:e7ca05fa8600 | 547 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 548 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 549 | #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ |
| AnnaBridge | 157:e7ca05fa8600 | 550 | ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) |
| AnnaBridge | 157:e7ca05fa8600 | 551 | |
| AnnaBridge | 157:e7ca05fa8600 | 552 | /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. |
| AnnaBridge | 157:e7ca05fa8600 | 553 | * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation. |
| AnnaBridge | 157:e7ca05fa8600 | 554 | * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 |
| AnnaBridge | 157:e7ca05fa8600 | 555 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 556 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 557 | #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU)) |
| AnnaBridge | 157:e7ca05fa8600 | 558 | /** @brief Sets the SPI transmit-only mode. |
| AnnaBridge | 157:e7ca05fa8600 | 559 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 157:e7ca05fa8600 | 560 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 561 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 562 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 563 | #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
| AnnaBridge | 157:e7ca05fa8600 | 564 | |
| AnnaBridge | 157:e7ca05fa8600 | 565 | /** @brief Sets the SPI receive-only mode. |
| AnnaBridge | 157:e7ca05fa8600 | 566 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 157:e7ca05fa8600 | 567 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 568 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 569 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 570 | #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
| AnnaBridge | 157:e7ca05fa8600 | 571 | |
| AnnaBridge | 157:e7ca05fa8600 | 572 | /** @brief Resets the CRC calculation of the SPI. |
| AnnaBridge | 157:e7ca05fa8600 | 573 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 157:e7ca05fa8600 | 574 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 157:e7ca05fa8600 | 575 | * @retval None |
| AnnaBridge | 157:e7ca05fa8600 | 576 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 577 | #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ |
| AnnaBridge | 157:e7ca05fa8600 | 578 | SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) |
| AnnaBridge | 157:e7ca05fa8600 | 579 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 580 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 581 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 582 | |
| AnnaBridge | 157:e7ca05fa8600 | 583 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 584 | /** @defgroup SPI_Exported_Functions SPI Exported Functions |
| AnnaBridge | 157:e7ca05fa8600 | 585 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 586 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 587 | |
| AnnaBridge | 157:e7ca05fa8600 | 588 | /* Initialization/de-initialization functions **********************************/ |
| AnnaBridge | 157:e7ca05fa8600 | 589 | /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 157:e7ca05fa8600 | 590 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 591 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 592 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 593 | HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 594 | void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 595 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 596 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 597 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 598 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 599 | |
| AnnaBridge | 157:e7ca05fa8600 | 600 | /* I/O operation functions *****************************************************/ |
| AnnaBridge | 157:e7ca05fa8600 | 601 | /** @defgroup SPI_Exported_Functions_Group2 IO operation functions |
| AnnaBridge | 157:e7ca05fa8600 | 602 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 603 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 604 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 157:e7ca05fa8600 | 605 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 157:e7ca05fa8600 | 606 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 157:e7ca05fa8600 | 607 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 157:e7ca05fa8600 | 608 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 157:e7ca05fa8600 | 609 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
| AnnaBridge | 157:e7ca05fa8600 | 610 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 157:e7ca05fa8600 | 611 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 157:e7ca05fa8600 | 612 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
| AnnaBridge | 157:e7ca05fa8600 | 613 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 614 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 615 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 616 | |
| AnnaBridge | 157:e7ca05fa8600 | 617 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 618 | void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 619 | void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 620 | void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 621 | void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 622 | void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 623 | void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 624 | void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 625 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 626 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 627 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 628 | |
| AnnaBridge | 157:e7ca05fa8600 | 629 | |
| AnnaBridge | 157:e7ca05fa8600 | 630 | /* Peripheral State and Control functions **************************************/ |
| AnnaBridge | 157:e7ca05fa8600 | 631 | /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions |
| AnnaBridge | 157:e7ca05fa8600 | 632 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 633 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 634 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 635 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 157:e7ca05fa8600 | 636 | |
| AnnaBridge | 157:e7ca05fa8600 | 637 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 638 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 639 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 640 | |
| AnnaBridge | 157:e7ca05fa8600 | 641 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 642 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 643 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 644 | |
| AnnaBridge | 157:e7ca05fa8600 | 645 | /* Private group definition ------------------------------------------------------*/ |
| AnnaBridge | 157:e7ca05fa8600 | 646 | /** @defgroup SPI_Private_Macros SPI Private Macros |
| AnnaBridge | 157:e7ca05fa8600 | 647 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 648 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 649 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 650 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 651 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 652 | |
| AnnaBridge | 157:e7ca05fa8600 | 653 | /* Define the private group ***********************************/ |
| AnnaBridge | 157:e7ca05fa8600 | 654 | /**************************************************************/ |
| AnnaBridge | 157:e7ca05fa8600 | 655 | /** @defgroup SPI_Private SPI Private |
| AnnaBridge | 157:e7ca05fa8600 | 656 | * @{ |
| AnnaBridge | 157:e7ca05fa8600 | 657 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 658 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 659 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 660 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 661 | /**************************************************************/ |
| AnnaBridge | 157:e7ca05fa8600 | 662 | |
| AnnaBridge | 157:e7ca05fa8600 | 663 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 664 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 665 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 666 | |
| AnnaBridge | 157:e7ca05fa8600 | 667 | /** |
| AnnaBridge | 157:e7ca05fa8600 | 668 | * @} |
| AnnaBridge | 157:e7ca05fa8600 | 669 | */ |
| AnnaBridge | 157:e7ca05fa8600 | 670 | |
| AnnaBridge | 157:e7ca05fa8600 | 671 | #ifdef __cplusplus |
| AnnaBridge | 157:e7ca05fa8600 | 672 | } |
| AnnaBridge | 157:e7ca05fa8600 | 673 | #endif |
| AnnaBridge | 157:e7ca05fa8600 | 674 | |
| AnnaBridge | 157:e7ca05fa8600 | 675 | #endif /* __STM32L0xx_HAL_SPI_H */ |
| AnnaBridge | 157:e7ca05fa8600 | 676 | |
| AnnaBridge | 157:e7ca05fa8600 | 677 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 157:e7ca05fa8600 | 678 |
