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TARGET_NUCLEO_F091RC/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
134:ad3be0349dc5
Child:
160:5571c4ff569f
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 134:ad3be0349dc5 1 /**
<> 134:ad3be0349dc5 2 ******************************************************************************
<> 134:ad3be0349dc5 3 * @file stm32f0xx_ll_utils.h
<> 134:ad3be0349dc5 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.4.0
<> 134:ad3be0349dc5 6 * @date 27-May-2016
<> 134:ad3be0349dc5 7 * @brief Header file of UTILS LL module.
<> 134:ad3be0349dc5 8 @verbatim
<> 134:ad3be0349dc5 9 ==============================================================================
<> 134:ad3be0349dc5 10 ##### How to use this driver #####
<> 134:ad3be0349dc5 11 ==============================================================================
<> 134:ad3be0349dc5 12 [..]
<> 134:ad3be0349dc5 13 The LL UTILS driver contains a set of generic APIs that can be
<> 134:ad3be0349dc5 14 used by user:
<> 134:ad3be0349dc5 15 (+) Device electronic signature
<> 134:ad3be0349dc5 16 (+) Timing functions
<> 134:ad3be0349dc5 17 (+) PLL configuration functions
<> 134:ad3be0349dc5 18
<> 134:ad3be0349dc5 19 @endverbatim
<> 134:ad3be0349dc5 20 ******************************************************************************
<> 134:ad3be0349dc5 21 * @attention
<> 134:ad3be0349dc5 22 *
<> 134:ad3be0349dc5 23 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 134:ad3be0349dc5 24 *
<> 134:ad3be0349dc5 25 * Redistribution and use in source and binary forms, with or without modification,
<> 134:ad3be0349dc5 26 * are permitted provided that the following conditions are met:
<> 134:ad3be0349dc5 27 * 1. Redistributions of source code must retain the above copyright notice,
<> 134:ad3be0349dc5 28 * this list of conditions and the following disclaimer.
<> 134:ad3be0349dc5 29 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 134:ad3be0349dc5 30 * this list of conditions and the following disclaimer in the documentation
<> 134:ad3be0349dc5 31 * and/or other materials provided with the distribution.
<> 134:ad3be0349dc5 32 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 134:ad3be0349dc5 33 * may be used to endorse or promote products derived from this software
<> 134:ad3be0349dc5 34 * without specific prior written permission.
<> 134:ad3be0349dc5 35 *
<> 134:ad3be0349dc5 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 134:ad3be0349dc5 37 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 134:ad3be0349dc5 38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 134:ad3be0349dc5 39 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 134:ad3be0349dc5 40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 134:ad3be0349dc5 41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 134:ad3be0349dc5 42 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 134:ad3be0349dc5 43 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 134:ad3be0349dc5 44 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 134:ad3be0349dc5 45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 134:ad3be0349dc5 46 *
<> 134:ad3be0349dc5 47 ******************************************************************************
<> 134:ad3be0349dc5 48 */
<> 134:ad3be0349dc5 49
<> 134:ad3be0349dc5 50 /* Define to prevent recursive inclusion -------------------------------------*/
<> 134:ad3be0349dc5 51 #ifndef __STM32F0xx_LL_UTILS_H
<> 134:ad3be0349dc5 52 #define __STM32F0xx_LL_UTILS_H
<> 134:ad3be0349dc5 53
<> 134:ad3be0349dc5 54 #ifdef __cplusplus
<> 134:ad3be0349dc5 55 extern "C" {
<> 134:ad3be0349dc5 56 #endif
<> 134:ad3be0349dc5 57
<> 134:ad3be0349dc5 58 /* Includes ------------------------------------------------------------------*/
<> 134:ad3be0349dc5 59 #include "stm32f0xx.h"
<> 134:ad3be0349dc5 60
<> 134:ad3be0349dc5 61 /** @addtogroup STM32F0xx_LL_Driver
<> 134:ad3be0349dc5 62 * @{
<> 134:ad3be0349dc5 63 */
<> 134:ad3be0349dc5 64
<> 134:ad3be0349dc5 65 /** @defgroup UTILS_LL UTILS
<> 134:ad3be0349dc5 66 * @{
<> 134:ad3be0349dc5 67 */
<> 134:ad3be0349dc5 68
<> 134:ad3be0349dc5 69 /* Private types -------------------------------------------------------------*/
<> 134:ad3be0349dc5 70 /* Private variables ---------------------------------------------------------*/
<> 134:ad3be0349dc5 71
<> 134:ad3be0349dc5 72 /* Private constants ---------------------------------------------------------*/
<> 134:ad3be0349dc5 73 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
<> 134:ad3be0349dc5 74 * @{
<> 134:ad3be0349dc5 75 */
<> 134:ad3be0349dc5 76
<> 134:ad3be0349dc5 77 /* Max delay can be used in LL_mDelay */
<> 134:ad3be0349dc5 78 #define LL_MAX_DELAY (uint32_t)0xFFFFFFFFU
<> 134:ad3be0349dc5 79
<> 134:ad3be0349dc5 80 /**
<> 134:ad3be0349dc5 81 * @brief Unique device ID register base address
<> 134:ad3be0349dc5 82 */
<> 134:ad3be0349dc5 83 #define UID_BASE_ADDRESS UID_BASE
<> 134:ad3be0349dc5 84
<> 134:ad3be0349dc5 85 /**
<> 134:ad3be0349dc5 86 * @brief Flash size data register base address
<> 134:ad3be0349dc5 87 */
<> 134:ad3be0349dc5 88 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
<> 134:ad3be0349dc5 89
<> 134:ad3be0349dc5 90 /**
<> 134:ad3be0349dc5 91 * @}
<> 134:ad3be0349dc5 92 */
<> 134:ad3be0349dc5 93
<> 134:ad3be0349dc5 94 /* Private macros ------------------------------------------------------------*/
<> 134:ad3be0349dc5 95 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
<> 134:ad3be0349dc5 96 * @{
<> 134:ad3be0349dc5 97 */
<> 134:ad3be0349dc5 98 /**
<> 134:ad3be0349dc5 99 * @}
<> 134:ad3be0349dc5 100 */
<> 134:ad3be0349dc5 101 /* Exported types ------------------------------------------------------------*/
<> 134:ad3be0349dc5 102 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
<> 134:ad3be0349dc5 103 * @{
<> 134:ad3be0349dc5 104 */
<> 134:ad3be0349dc5 105 /**
<> 134:ad3be0349dc5 106 * @brief UTILS PLL structure definition
<> 134:ad3be0349dc5 107 */
<> 134:ad3be0349dc5 108 typedef struct
<> 134:ad3be0349dc5 109 {
<> 134:ad3be0349dc5 110 uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
<> 134:ad3be0349dc5 111 This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
<> 134:ad3be0349dc5 112
<> 134:ad3be0349dc5 113 This feature can be modified afterwards using unitary function
<> 134:ad3be0349dc5 114 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
<> 134:ad3be0349dc5 115
<> 134:ad3be0349dc5 116 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<> 134:ad3be0349dc5 117 uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock.
<> 134:ad3be0349dc5 118 This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
<> 134:ad3be0349dc5 119
<> 134:ad3be0349dc5 120 This feature can be modified afterwards using unitary function
<> 134:ad3be0349dc5 121 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
<> 134:ad3be0349dc5 122 #else
<> 134:ad3be0349dc5 123 uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
<> 134:ad3be0349dc5 124 This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
<> 134:ad3be0349dc5 125
<> 134:ad3be0349dc5 126 This feature can be modified afterwards using unitary function
<> 134:ad3be0349dc5 127 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
<> 134:ad3be0349dc5 128 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
<> 134:ad3be0349dc5 129 } LL_UTILS_PLLInitTypeDef;
<> 134:ad3be0349dc5 130
<> 134:ad3be0349dc5 131 /**
<> 134:ad3be0349dc5 132 * @brief UTILS System, AHB and APB buses clock configuration structure definition
<> 134:ad3be0349dc5 133 */
<> 134:ad3be0349dc5 134 typedef struct
<> 134:ad3be0349dc5 135 {
<> 134:ad3be0349dc5 136 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
<> 134:ad3be0349dc5 137 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
<> 134:ad3be0349dc5 138
<> 134:ad3be0349dc5 139 This feature can be modified afterwards using unitary function
<> 134:ad3be0349dc5 140 @ref LL_RCC_SetAHBPrescaler(). */
<> 134:ad3be0349dc5 141
<> 134:ad3be0349dc5 142 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
<> 134:ad3be0349dc5 143 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
<> 134:ad3be0349dc5 144
<> 134:ad3be0349dc5 145 This feature can be modified afterwards using unitary function
<> 134:ad3be0349dc5 146 @ref LL_RCC_SetAPB1Prescaler(). */
<> 134:ad3be0349dc5 147 } LL_UTILS_ClkInitTypeDef;
<> 134:ad3be0349dc5 148
<> 134:ad3be0349dc5 149 /**
<> 134:ad3be0349dc5 150 * @}
<> 134:ad3be0349dc5 151 */
<> 134:ad3be0349dc5 152
<> 134:ad3be0349dc5 153 /* Exported constants --------------------------------------------------------*/
<> 134:ad3be0349dc5 154 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
<> 134:ad3be0349dc5 155 * @{
<> 134:ad3be0349dc5 156 */
<> 134:ad3be0349dc5 157
<> 134:ad3be0349dc5 158 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
<> 134:ad3be0349dc5 159 * @{
<> 134:ad3be0349dc5 160 */
<> 134:ad3be0349dc5 161 #define LL_UTILS_HSEBYPASS_OFF (uint32_t)0x00000000U /*!< HSE Bypass is not enabled */
<> 134:ad3be0349dc5 162 #define LL_UTILS_HSEBYPASS_ON (uint32_t)0x00000001U /*!< HSE Bypass is enabled */
<> 134:ad3be0349dc5 163 /**
<> 134:ad3be0349dc5 164 * @}
<> 134:ad3be0349dc5 165 */
<> 134:ad3be0349dc5 166
<> 134:ad3be0349dc5 167 /**
<> 134:ad3be0349dc5 168 * @}
<> 134:ad3be0349dc5 169 */
<> 134:ad3be0349dc5 170
<> 134:ad3be0349dc5 171 /* Exported macro ------------------------------------------------------------*/
<> 134:ad3be0349dc5 172
<> 134:ad3be0349dc5 173 /* Exported functions --------------------------------------------------------*/
<> 134:ad3be0349dc5 174 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
<> 134:ad3be0349dc5 175 * @{
<> 134:ad3be0349dc5 176 */
<> 134:ad3be0349dc5 177
<> 134:ad3be0349dc5 178 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
<> 134:ad3be0349dc5 179 * @{
<> 134:ad3be0349dc5 180 */
<> 134:ad3be0349dc5 181
<> 134:ad3be0349dc5 182 /**
<> 134:ad3be0349dc5 183 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
<> 134:ad3be0349dc5 184 * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
<> 134:ad3be0349dc5 185 */
<> 134:ad3be0349dc5 186 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
<> 134:ad3be0349dc5 187 {
<> 134:ad3be0349dc5 188 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
<> 134:ad3be0349dc5 189 }
<> 134:ad3be0349dc5 190
<> 134:ad3be0349dc5 191 /**
<> 134:ad3be0349dc5 192 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
<> 134:ad3be0349dc5 193 * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
<> 134:ad3be0349dc5 194 */
<> 134:ad3be0349dc5 195 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
<> 134:ad3be0349dc5 196 {
<> 134:ad3be0349dc5 197 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
<> 134:ad3be0349dc5 198 }
<> 134:ad3be0349dc5 199
<> 134:ad3be0349dc5 200 /**
<> 134:ad3be0349dc5 201 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
<> 134:ad3be0349dc5 202 * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
<> 134:ad3be0349dc5 203 */
<> 134:ad3be0349dc5 204 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
<> 134:ad3be0349dc5 205 {
<> 134:ad3be0349dc5 206 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
<> 134:ad3be0349dc5 207 }
<> 134:ad3be0349dc5 208
<> 134:ad3be0349dc5 209 /**
<> 134:ad3be0349dc5 210 * @brief Get Flash memory size
<> 134:ad3be0349dc5 211 * @note This bitfield indicates the size of the device Flash memory expressed in
<> 134:ad3be0349dc5 212 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
<> 134:ad3be0349dc5 213 * @retval FLASH_SIZE[15:0]: Flash memory size
<> 134:ad3be0349dc5 214 */
<> 134:ad3be0349dc5 215 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
<> 134:ad3be0349dc5 216 {
<> 134:ad3be0349dc5 217 return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
<> 134:ad3be0349dc5 218 }
<> 134:ad3be0349dc5 219
<> 134:ad3be0349dc5 220 /**
<> 134:ad3be0349dc5 221 * @}
<> 134:ad3be0349dc5 222 */
<> 134:ad3be0349dc5 223
<> 134:ad3be0349dc5 224 /** @defgroup UTILS_LL_EF_DELAY DELAY
<> 134:ad3be0349dc5 225 * @{
<> 134:ad3be0349dc5 226 */
<> 134:ad3be0349dc5 227
<> 134:ad3be0349dc5 228 /**
<> 134:ad3be0349dc5 229 * @brief This function configures the Cortex-M SysTick source of the time base.
<> 134:ad3be0349dc5 230 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
<> 134:ad3be0349dc5 231 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
<> 134:ad3be0349dc5 232 * configuration by calling this function, for a delay use rather osDelay RTOS service.
<> 134:ad3be0349dc5 233 * @param Ticks Number of ticks
<> 134:ad3be0349dc5 234 * @retval None
<> 134:ad3be0349dc5 235 */
<> 134:ad3be0349dc5 236 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
<> 134:ad3be0349dc5 237 {
<> 134:ad3be0349dc5 238 /* Configure the SysTick to have interrupt in 1ms time base */
<> 134:ad3be0349dc5 239 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
<> 134:ad3be0349dc5 240 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 134:ad3be0349dc5 241 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 134:ad3be0349dc5 242 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
<> 134:ad3be0349dc5 243 }
<> 134:ad3be0349dc5 244
<> 134:ad3be0349dc5 245 void LL_Init1msTick(uint32_t HCLKFrequency);
<> 134:ad3be0349dc5 246 void LL_mDelay(uint32_t Delay);
<> 134:ad3be0349dc5 247
<> 134:ad3be0349dc5 248 /**
<> 134:ad3be0349dc5 249 * @}
<> 134:ad3be0349dc5 250 */
<> 134:ad3be0349dc5 251
<> 134:ad3be0349dc5 252 /** @defgroup UTILS_EF_SYSTEM SYSTEM
<> 134:ad3be0349dc5 253 * @{
<> 134:ad3be0349dc5 254 */
<> 134:ad3be0349dc5 255
<> 134:ad3be0349dc5 256 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
<> 134:ad3be0349dc5 257 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
<> 134:ad3be0349dc5 258 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<> 134:ad3be0349dc5 259 #if defined(RCC_CFGR_SW_HSI48)
<> 134:ad3be0349dc5 260 ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
<> 134:ad3be0349dc5 261 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<> 134:ad3be0349dc5 262 #endif /*RCC_CFGR_SW_HSI48*/
<> 134:ad3be0349dc5 263 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
<> 134:ad3be0349dc5 264 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<> 134:ad3be0349dc5 265
<> 134:ad3be0349dc5 266 /**
<> 134:ad3be0349dc5 267 * @}
<> 134:ad3be0349dc5 268 */
<> 134:ad3be0349dc5 269
<> 134:ad3be0349dc5 270 /**
<> 134:ad3be0349dc5 271 * @}
<> 134:ad3be0349dc5 272 */
<> 134:ad3be0349dc5 273
<> 134:ad3be0349dc5 274 /**
<> 134:ad3be0349dc5 275 * @}
<> 134:ad3be0349dc5 276 */
<> 134:ad3be0349dc5 277
<> 134:ad3be0349dc5 278 /**
<> 134:ad3be0349dc5 279 * @}
<> 134:ad3be0349dc5 280 */
<> 134:ad3be0349dc5 281
<> 134:ad3be0349dc5 282 #ifdef __cplusplus
<> 134:ad3be0349dc5 283 }
<> 134:ad3be0349dc5 284 #endif
<> 134:ad3be0349dc5 285
<> 134:ad3be0349dc5 286 #endif /* __STM32F0xx_LL_UTILS_H */
<> 134:ad3be0349dc5 287
<> 134:ad3be0349dc5 288 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/