mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F091RC/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_iwdg.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
134:ad3be0349dc5
Child:
160:5571c4ff569f
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 134:ad3be0349dc5 1 /**
<> 134:ad3be0349dc5 2 ******************************************************************************
<> 134:ad3be0349dc5 3 * @file stm32f0xx_ll_iwdg.h
<> 134:ad3be0349dc5 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.4.0
<> 134:ad3be0349dc5 6 * @date 27-May-2016
<> 134:ad3be0349dc5 7 * @brief Header file of IWDG LL module.
<> 134:ad3be0349dc5 8 ******************************************************************************
<> 134:ad3be0349dc5 9 * @attention
<> 134:ad3be0349dc5 10 *
<> 134:ad3be0349dc5 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 134:ad3be0349dc5 12 *
<> 134:ad3be0349dc5 13 * Redistribution and use in source and binary forms, with or without modification,
<> 134:ad3be0349dc5 14 * are permitted provided that the following conditions are met:
<> 134:ad3be0349dc5 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 134:ad3be0349dc5 16 * this list of conditions and the following disclaimer.
<> 134:ad3be0349dc5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 134:ad3be0349dc5 18 * this list of conditions and the following disclaimer in the documentation
<> 134:ad3be0349dc5 19 * and/or other materials provided with the distribution.
<> 134:ad3be0349dc5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 134:ad3be0349dc5 21 * may be used to endorse or promote products derived from this software
<> 134:ad3be0349dc5 22 * without specific prior written permission.
<> 134:ad3be0349dc5 23 *
<> 134:ad3be0349dc5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 134:ad3be0349dc5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 134:ad3be0349dc5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 134:ad3be0349dc5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 134:ad3be0349dc5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 134:ad3be0349dc5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 134:ad3be0349dc5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 134:ad3be0349dc5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 134:ad3be0349dc5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 134:ad3be0349dc5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 134:ad3be0349dc5 34 *
<> 134:ad3be0349dc5 35 ******************************************************************************
<> 134:ad3be0349dc5 36 */
<> 134:ad3be0349dc5 37
<> 134:ad3be0349dc5 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 134:ad3be0349dc5 39 #ifndef __STM32F0xx_LL_IWDG_H
<> 134:ad3be0349dc5 40 #define __STM32F0xx_LL_IWDG_H
<> 134:ad3be0349dc5 41
<> 134:ad3be0349dc5 42 #ifdef __cplusplus
<> 134:ad3be0349dc5 43 extern "C" {
<> 134:ad3be0349dc5 44 #endif
<> 134:ad3be0349dc5 45
<> 134:ad3be0349dc5 46 /* Includes ------------------------------------------------------------------*/
<> 134:ad3be0349dc5 47 #include "stm32f0xx.h"
<> 134:ad3be0349dc5 48
<> 134:ad3be0349dc5 49 /** @addtogroup STM32F0xx_LL_Driver
<> 134:ad3be0349dc5 50 * @{
<> 134:ad3be0349dc5 51 */
<> 134:ad3be0349dc5 52
<> 134:ad3be0349dc5 53 #if defined(IWDG)
<> 134:ad3be0349dc5 54
<> 134:ad3be0349dc5 55 /** @defgroup IWDG_LL IWDG
<> 134:ad3be0349dc5 56 * @{
<> 134:ad3be0349dc5 57 */
<> 134:ad3be0349dc5 58
<> 134:ad3be0349dc5 59 /* Private types -------------------------------------------------------------*/
<> 134:ad3be0349dc5 60 /* Private variables ---------------------------------------------------------*/
<> 134:ad3be0349dc5 61
<> 134:ad3be0349dc5 62 /* Private constants ---------------------------------------------------------*/
<> 134:ad3be0349dc5 63 /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
<> 134:ad3be0349dc5 64 * @{
<> 134:ad3be0349dc5 65 */
<> 134:ad3be0349dc5 66
<> 134:ad3be0349dc5 67 #define LL_IWDG_KEY_RELOAD ((uint32_t)0x0000AAAAU) /*!< IWDG Reload Counter Enable */
<> 134:ad3be0349dc5 68 #define LL_IWDG_KEY_ENABLE ((uint32_t)0x0000CCCCU) /*!< IWDG Peripheral Enable */
<> 134:ad3be0349dc5 69 #define LL_IWDG_KEY_WR_ACCESS_ENABLE ((uint32_t)0x00005555U) /*!< IWDG KR Write Access Enable */
<> 134:ad3be0349dc5 70 #define LL_IWDG_KEY_WR_ACCESS_DISABLE ((uint32_t)0x00000000U) /*!< IWDG KR Write Access Disable */
<> 134:ad3be0349dc5 71
<> 134:ad3be0349dc5 72 /**
<> 134:ad3be0349dc5 73 * @}
<> 134:ad3be0349dc5 74 */
<> 134:ad3be0349dc5 75
<> 134:ad3be0349dc5 76 /* Private macros ------------------------------------------------------------*/
<> 134:ad3be0349dc5 77
<> 134:ad3be0349dc5 78 /* Exported types ------------------------------------------------------------*/
<> 134:ad3be0349dc5 79 /* Exported constants --------------------------------------------------------*/
<> 134:ad3be0349dc5 80 /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
<> 134:ad3be0349dc5 81 * @{
<> 134:ad3be0349dc5 82 */
<> 134:ad3be0349dc5 83
<> 134:ad3be0349dc5 84 /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
<> 134:ad3be0349dc5 85 * @brief Flags defines which can be used with LL_IWDG_ReadReg function
<> 134:ad3be0349dc5 86 * @{
<> 134:ad3be0349dc5 87 */
<> 134:ad3be0349dc5 88 #define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
<> 134:ad3be0349dc5 89 #define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
<> 134:ad3be0349dc5 90 #define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
<> 134:ad3be0349dc5 91
<> 134:ad3be0349dc5 92 /**
<> 134:ad3be0349dc5 93 * @}
<> 134:ad3be0349dc5 94 */
<> 134:ad3be0349dc5 95
<> 134:ad3be0349dc5 96 /** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
<> 134:ad3be0349dc5 97 * @{
<> 134:ad3be0349dc5 98 */
<> 134:ad3be0349dc5 99 #define LL_IWDG_PRESCALER_4 ((uint32_t)0x00000000U) /*!< Divider by 4 */
<> 134:ad3be0349dc5 100 #define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
<> 134:ad3be0349dc5 101 #define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
<> 134:ad3be0349dc5 102 #define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
<> 134:ad3be0349dc5 103 #define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
<> 134:ad3be0349dc5 104 #define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
<> 134:ad3be0349dc5 105 #define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
<> 134:ad3be0349dc5 106 /**
<> 134:ad3be0349dc5 107 * @}
<> 134:ad3be0349dc5 108 */
<> 134:ad3be0349dc5 109
<> 134:ad3be0349dc5 110 /**
<> 134:ad3be0349dc5 111 * @}
<> 134:ad3be0349dc5 112 */
<> 134:ad3be0349dc5 113
<> 134:ad3be0349dc5 114 /* Exported macro ------------------------------------------------------------*/
<> 134:ad3be0349dc5 115 /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
<> 134:ad3be0349dc5 116 * @{
<> 134:ad3be0349dc5 117 */
<> 134:ad3be0349dc5 118
<> 134:ad3be0349dc5 119 /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
<> 134:ad3be0349dc5 120 * @{
<> 134:ad3be0349dc5 121 */
<> 134:ad3be0349dc5 122
<> 134:ad3be0349dc5 123 /**
<> 134:ad3be0349dc5 124 * @brief Write a value in IWDG register
<> 134:ad3be0349dc5 125 * @param __INSTANCE__ IWDG Instance
<> 134:ad3be0349dc5 126 * @param __REG__ Register to be written
<> 134:ad3be0349dc5 127 * @param __VALUE__ Value to be written in the register
<> 134:ad3be0349dc5 128 * @retval None
<> 134:ad3be0349dc5 129 */
<> 134:ad3be0349dc5 130 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 134:ad3be0349dc5 131
<> 134:ad3be0349dc5 132 /**
<> 134:ad3be0349dc5 133 * @brief Read a value in IWDG register
<> 134:ad3be0349dc5 134 * @param __INSTANCE__ IWDG Instance
<> 134:ad3be0349dc5 135 * @param __REG__ Register to be read
<> 134:ad3be0349dc5 136 * @retval Register value
<> 134:ad3be0349dc5 137 */
<> 134:ad3be0349dc5 138 #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 134:ad3be0349dc5 139 /**
<> 134:ad3be0349dc5 140 * @}
<> 134:ad3be0349dc5 141 */
<> 134:ad3be0349dc5 142
<> 134:ad3be0349dc5 143 /**
<> 134:ad3be0349dc5 144 * @}
<> 134:ad3be0349dc5 145 */
<> 134:ad3be0349dc5 146
<> 134:ad3be0349dc5 147
<> 134:ad3be0349dc5 148 /* Exported functions --------------------------------------------------------*/
<> 134:ad3be0349dc5 149 /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
<> 134:ad3be0349dc5 150 * @{
<> 134:ad3be0349dc5 151 */
<> 134:ad3be0349dc5 152 /** @defgroup IWDG_LL_EF_Configuration Configuration
<> 134:ad3be0349dc5 153 * @{
<> 134:ad3be0349dc5 154 */
<> 134:ad3be0349dc5 155
<> 134:ad3be0349dc5 156 /**
<> 134:ad3be0349dc5 157 * @brief Start the Independent Watchdog
<> 134:ad3be0349dc5 158 * @note Except if the hardware watchdog option is selected
<> 134:ad3be0349dc5 159 * @rmtoll KR KEY LL_IWDG_Enable
<> 134:ad3be0349dc5 160 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 161 * @retval None
<> 134:ad3be0349dc5 162 */
<> 134:ad3be0349dc5 163 __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
<> 134:ad3be0349dc5 164 {
<> 134:ad3be0349dc5 165 WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
<> 134:ad3be0349dc5 166 }
<> 134:ad3be0349dc5 167
<> 134:ad3be0349dc5 168 /**
<> 134:ad3be0349dc5 169 * @brief Reloads IWDG counter with value defined in the reload register
<> 134:ad3be0349dc5 170 * @rmtoll KR KEY LL_IWDG_ReloadCounter
<> 134:ad3be0349dc5 171 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 172 * @retval None
<> 134:ad3be0349dc5 173 */
<> 134:ad3be0349dc5 174 __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
<> 134:ad3be0349dc5 175 {
<> 134:ad3be0349dc5 176 WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
<> 134:ad3be0349dc5 177 }
<> 134:ad3be0349dc5 178
<> 134:ad3be0349dc5 179 /**
<> 134:ad3be0349dc5 180 * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
<> 134:ad3be0349dc5 181 * @rmtoll KR KEY LL_IWDG_EnableWriteAccess
<> 134:ad3be0349dc5 182 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 183 * @retval None
<> 134:ad3be0349dc5 184 */
<> 134:ad3be0349dc5 185 __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
<> 134:ad3be0349dc5 186 {
<> 134:ad3be0349dc5 187 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
<> 134:ad3be0349dc5 188 }
<> 134:ad3be0349dc5 189
<> 134:ad3be0349dc5 190 /**
<> 134:ad3be0349dc5 191 * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
<> 134:ad3be0349dc5 192 * @rmtoll KR KEY LL_IWDG_DisableWriteAccess
<> 134:ad3be0349dc5 193 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 194 * @retval None
<> 134:ad3be0349dc5 195 */
<> 134:ad3be0349dc5 196 __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
<> 134:ad3be0349dc5 197 {
<> 134:ad3be0349dc5 198 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
<> 134:ad3be0349dc5 199 }
<> 134:ad3be0349dc5 200
<> 134:ad3be0349dc5 201 /**
<> 134:ad3be0349dc5 202 * @brief Select the prescaler of the IWDG
<> 134:ad3be0349dc5 203 * @rmtoll PR PR LL_IWDG_SetPrescaler
<> 134:ad3be0349dc5 204 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 205 * @param Prescaler This parameter can be one of the following values:
<> 134:ad3be0349dc5 206 * @arg @ref LL_IWDG_PRESCALER_4
<> 134:ad3be0349dc5 207 * @arg @ref LL_IWDG_PRESCALER_8
<> 134:ad3be0349dc5 208 * @arg @ref LL_IWDG_PRESCALER_16
<> 134:ad3be0349dc5 209 * @arg @ref LL_IWDG_PRESCALER_32
<> 134:ad3be0349dc5 210 * @arg @ref LL_IWDG_PRESCALER_64
<> 134:ad3be0349dc5 211 * @arg @ref LL_IWDG_PRESCALER_128
<> 134:ad3be0349dc5 212 * @arg @ref LL_IWDG_PRESCALER_256
<> 134:ad3be0349dc5 213 * @retval None
<> 134:ad3be0349dc5 214 */
<> 134:ad3be0349dc5 215 __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
<> 134:ad3be0349dc5 216 {
<> 134:ad3be0349dc5 217 WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
<> 134:ad3be0349dc5 218 }
<> 134:ad3be0349dc5 219
<> 134:ad3be0349dc5 220 /**
<> 134:ad3be0349dc5 221 * @brief Get the selected prescaler of the IWDG
<> 134:ad3be0349dc5 222 * @rmtoll PR PR LL_IWDG_GetPrescaler
<> 134:ad3be0349dc5 223 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 224 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 225 * @arg @ref LL_IWDG_PRESCALER_4
<> 134:ad3be0349dc5 226 * @arg @ref LL_IWDG_PRESCALER_8
<> 134:ad3be0349dc5 227 * @arg @ref LL_IWDG_PRESCALER_16
<> 134:ad3be0349dc5 228 * @arg @ref LL_IWDG_PRESCALER_32
<> 134:ad3be0349dc5 229 * @arg @ref LL_IWDG_PRESCALER_64
<> 134:ad3be0349dc5 230 * @arg @ref LL_IWDG_PRESCALER_128
<> 134:ad3be0349dc5 231 * @arg @ref LL_IWDG_PRESCALER_256
<> 134:ad3be0349dc5 232 */
<> 134:ad3be0349dc5 233 __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
<> 134:ad3be0349dc5 234 {
<> 134:ad3be0349dc5 235 return (uint32_t)(READ_REG(IWDGx->PR));
<> 134:ad3be0349dc5 236 }
<> 134:ad3be0349dc5 237
<> 134:ad3be0349dc5 238 /**
<> 134:ad3be0349dc5 239 * @brief Specify the IWDG down-counter reload value
<> 134:ad3be0349dc5 240 * @rmtoll RLR RL LL_IWDG_SetReloadCounter
<> 134:ad3be0349dc5 241 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 242 * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
<> 134:ad3be0349dc5 243 * @retval None
<> 134:ad3be0349dc5 244 */
<> 134:ad3be0349dc5 245 __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
<> 134:ad3be0349dc5 246 {
<> 134:ad3be0349dc5 247 WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
<> 134:ad3be0349dc5 248 }
<> 134:ad3be0349dc5 249
<> 134:ad3be0349dc5 250 /**
<> 134:ad3be0349dc5 251 * @brief Get the specified IWDG down-counter reload value
<> 134:ad3be0349dc5 252 * @rmtoll RLR RL LL_IWDG_GetReloadCounter
<> 134:ad3be0349dc5 253 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 254 * @retval Value between Min_Data=0 and Max_Data=0x0FFF
<> 134:ad3be0349dc5 255 */
<> 134:ad3be0349dc5 256 __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
<> 134:ad3be0349dc5 257 {
<> 134:ad3be0349dc5 258 return (uint32_t)(READ_REG(IWDGx->RLR));
<> 134:ad3be0349dc5 259 }
<> 134:ad3be0349dc5 260
<> 134:ad3be0349dc5 261 /**
<> 134:ad3be0349dc5 262 * @brief Specify high limit of the window value to be compared to the down-counter.
<> 134:ad3be0349dc5 263 * @rmtoll WINR WIN LL_IWDG_SetWindow
<> 134:ad3be0349dc5 264 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 265 * @param Window Value between Min_Data=0 and Max_Data=0x0FFF
<> 134:ad3be0349dc5 266 * @retval None
<> 134:ad3be0349dc5 267 */
<> 134:ad3be0349dc5 268 __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
<> 134:ad3be0349dc5 269 {
<> 134:ad3be0349dc5 270 WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
<> 134:ad3be0349dc5 271 }
<> 134:ad3be0349dc5 272
<> 134:ad3be0349dc5 273 /**
<> 134:ad3be0349dc5 274 * @brief Get the high limit of the window value specified.
<> 134:ad3be0349dc5 275 * @rmtoll WINR WIN LL_IWDG_GetWindow
<> 134:ad3be0349dc5 276 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 277 * @retval Value between Min_Data=0 and Max_Data=0x0FFF
<> 134:ad3be0349dc5 278 */
<> 134:ad3be0349dc5 279 __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
<> 134:ad3be0349dc5 280 {
<> 134:ad3be0349dc5 281 return (uint32_t)(READ_REG(IWDGx->WINR));
<> 134:ad3be0349dc5 282 }
<> 134:ad3be0349dc5 283
<> 134:ad3be0349dc5 284 /**
<> 134:ad3be0349dc5 285 * @}
<> 134:ad3be0349dc5 286 */
<> 134:ad3be0349dc5 287
<> 134:ad3be0349dc5 288 /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
<> 134:ad3be0349dc5 289 * @{
<> 134:ad3be0349dc5 290 */
<> 134:ad3be0349dc5 291
<> 134:ad3be0349dc5 292 /**
<> 134:ad3be0349dc5 293 * @brief Check if flag Prescaler Value Update is set or not
<> 134:ad3be0349dc5 294 * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
<> 134:ad3be0349dc5 295 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 296 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 297 */
<> 134:ad3be0349dc5 298 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
<> 134:ad3be0349dc5 299 {
<> 134:ad3be0349dc5 300 return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
<> 134:ad3be0349dc5 301 }
<> 134:ad3be0349dc5 302
<> 134:ad3be0349dc5 303 /**
<> 134:ad3be0349dc5 304 * @brief Check if flag Reload Value Update is set or not
<> 134:ad3be0349dc5 305 * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
<> 134:ad3be0349dc5 306 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 307 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 308 */
<> 134:ad3be0349dc5 309 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
<> 134:ad3be0349dc5 310 {
<> 134:ad3be0349dc5 311 return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
<> 134:ad3be0349dc5 312 }
<> 134:ad3be0349dc5 313
<> 134:ad3be0349dc5 314 /**
<> 134:ad3be0349dc5 315 * @brief Check if flag Window Value Update is set or not
<> 134:ad3be0349dc5 316 * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
<> 134:ad3be0349dc5 317 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 318 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 319 */
<> 134:ad3be0349dc5 320 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
<> 134:ad3be0349dc5 321 {
<> 134:ad3be0349dc5 322 return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
<> 134:ad3be0349dc5 323 }
<> 134:ad3be0349dc5 324
<> 134:ad3be0349dc5 325 /**
<> 134:ad3be0349dc5 326 * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
<> 134:ad3be0349dc5 327 * @rmtoll SR PVU LL_IWDG_IsReady\n
<> 134:ad3be0349dc5 328 * SR WVU LL_IWDG_IsReady\n
<> 134:ad3be0349dc5 329 * SR RVU LL_IWDG_IsReady
<> 134:ad3be0349dc5 330 * @param IWDGx IWDG Instance
<> 134:ad3be0349dc5 331 * @retval State of bits (1 or 0).
<> 134:ad3be0349dc5 332 */
<> 134:ad3be0349dc5 333 __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
<> 134:ad3be0349dc5 334 {
<> 134:ad3be0349dc5 335 return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
<> 134:ad3be0349dc5 336 }
<> 134:ad3be0349dc5 337
<> 134:ad3be0349dc5 338 /**
<> 134:ad3be0349dc5 339 * @}
<> 134:ad3be0349dc5 340 */
<> 134:ad3be0349dc5 341
<> 134:ad3be0349dc5 342
<> 134:ad3be0349dc5 343 /**
<> 134:ad3be0349dc5 344 * @}
<> 134:ad3be0349dc5 345 */
<> 134:ad3be0349dc5 346
<> 134:ad3be0349dc5 347 /**
<> 134:ad3be0349dc5 348 * @}
<> 134:ad3be0349dc5 349 */
<> 134:ad3be0349dc5 350
<> 134:ad3be0349dc5 351 #endif /* IWDG) */
<> 134:ad3be0349dc5 352
<> 134:ad3be0349dc5 353 /**
<> 134:ad3be0349dc5 354 * @}
<> 134:ad3be0349dc5 355 */
<> 134:ad3be0349dc5 356
<> 134:ad3be0349dc5 357 #ifdef __cplusplus
<> 134:ad3be0349dc5 358 }
<> 134:ad3be0349dc5 359 #endif
<> 134:ad3be0349dc5 360
<> 134:ad3be0349dc5 361 #endif /* __STM32F0xx_LL_IWDG_H */
<> 134:ad3be0349dc5 362
<> 134:ad3be0349dc5 363 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/