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TARGET_NUCLEO_F091RC/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 09 11:14:10 2017 +0000
Revision:: 157:e7ca05fa8600
Parent:: 134:ad3be0349dc5
Child:: 160:5571c4ff569f

Release 155 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	134:ad3be0349dc5	1	/**
<>	134:ad3be0349dc5	2	******************************************************************************
<>	134:ad3be0349dc5	3	* @file stm32f0xx_ll_dac.h
<>	134:ad3be0349dc5	4	* @author MCD Application Team
<>	134:ad3be0349dc5	5	* @version V1.4.0
<>	134:ad3be0349dc5	6	* @date 27-May-2016
<>	134:ad3be0349dc5	7	* @brief Header file of DAC LL module.
<>	134:ad3be0349dc5	8	******************************************************************************
<>	134:ad3be0349dc5	9	* @attention
<>	134:ad3be0349dc5	10	*
<>	134:ad3be0349dc5	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	134:ad3be0349dc5	12	*
<>	134:ad3be0349dc5	13	* Redistribution and use in source and binary forms, with or without modification,
<>	134:ad3be0349dc5	14	* are permitted provided that the following conditions are met:
<>	134:ad3be0349dc5	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	134:ad3be0349dc5	16	* this list of conditions and the following disclaimer.
<>	134:ad3be0349dc5	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	134:ad3be0349dc5	18	* this list of conditions and the following disclaimer in the documentation
<>	134:ad3be0349dc5	19	* and/or other materials provided with the distribution.
<>	134:ad3be0349dc5	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	134:ad3be0349dc5	21	* may be used to endorse or promote products derived from this software
<>	134:ad3be0349dc5	22	* without specific prior written permission.
<>	134:ad3be0349dc5	23	*
<>	134:ad3be0349dc5	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	134:ad3be0349dc5	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	134:ad3be0349dc5	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	134:ad3be0349dc5	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	134:ad3be0349dc5	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	134:ad3be0349dc5	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	134:ad3be0349dc5	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	134:ad3be0349dc5	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	134:ad3be0349dc5	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	134:ad3be0349dc5	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	134:ad3be0349dc5	34	*
<>	134:ad3be0349dc5	35	******************************************************************************
<>	134:ad3be0349dc5	36	*/
<>	134:ad3be0349dc5	37
<>	134:ad3be0349dc5	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	134:ad3be0349dc5	39	#ifndef __STM32F0xx_LL_DAC_H
<>	134:ad3be0349dc5	40	#define __STM32F0xx_LL_DAC_H
<>	134:ad3be0349dc5	41
<>	134:ad3be0349dc5	42	#ifdef __cplusplus
<>	134:ad3be0349dc5	43	extern "C" {
<>	134:ad3be0349dc5	44	#endif
<>	134:ad3be0349dc5	45
<>	134:ad3be0349dc5	46	/* Includes ------------------------------------------------------------------*/
<>	134:ad3be0349dc5	47	#include "stm32f0xx.h"
<>	134:ad3be0349dc5	48
<>	134:ad3be0349dc5	49	/** @addtogroup STM32F0xx_LL_Driver
<>	134:ad3be0349dc5	50	* @{
<>	134:ad3be0349dc5	51	*/
<>	134:ad3be0349dc5	52
<>	134:ad3be0349dc5	53	#if defined (DAC1)
<>	134:ad3be0349dc5	54
<>	134:ad3be0349dc5	55	/** @defgroup DAC_LL DAC
<>	134:ad3be0349dc5	56	* @{
<>	134:ad3be0349dc5	57	*/
<>	134:ad3be0349dc5	58
<>	134:ad3be0349dc5	59	/* Private types -------------------------------------------------------------*/
<>	134:ad3be0349dc5	60	/* Private variables ---------------------------------------------------------*/
<>	134:ad3be0349dc5	61
<>	134:ad3be0349dc5	62	/* Private constants ---------------------------------------------------------*/
<>	134:ad3be0349dc5	63	/** @defgroup DAC_LL_Private_Constants DAC Private Constants
<>	134:ad3be0349dc5	64	* @{
<>	134:ad3be0349dc5	65	*/
<>	134:ad3be0349dc5	66
<>	134:ad3be0349dc5	67	/* Internal masks for DAC channels definition */
<>	134:ad3be0349dc5	68	/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
<>	134:ad3be0349dc5	69	/* - channel bits position into register CR */
<>	134:ad3be0349dc5	70	/* - channel bits position into register SWTRIG */
<>	134:ad3be0349dc5	71	/* - channel register offset of data holding register DHRx */
<>	134:ad3be0349dc5	72	/* - channel register offset of data output register DORx */
<>	134:ad3be0349dc5	73	#define DAC_CR_CH1_BITOFFSET ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
<>	134:ad3be0349dc5	74	#define DAC_CR_CH2_BITOFFSET ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
<>	134:ad3be0349dc5	75	#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET \| DAC_CR_CH2_BITOFFSET)
<>	134:ad3be0349dc5	76
<>	134:ad3be0349dc5	77	#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
<>	134:ad3be0349dc5	78	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	79	#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
<>	134:ad3be0349dc5	80	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 \| DAC_SWTR_CH2)
<>	134:ad3be0349dc5	81	#else
<>	134:ad3be0349dc5	82	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
<>	134:ad3be0349dc5	83	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	84
<>	134:ad3be0349dc5	85	#define DAC_REG_DHR12R1_REGOFFSET ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */
<>	134:ad3be0349dc5	86	#define DAC_REG_DHR12L1_REGOFFSET ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
<>	134:ad3be0349dc5	87	#define DAC_REG_DHR8R1_REGOFFSET ((uint32_t)0x02000000U) /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
<>	134:ad3be0349dc5	88	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	89	#define DAC_REG_DHR12R2_REGOFFSET ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
<>	134:ad3be0349dc5	90	#define DAC_REG_DHR12L2_REGOFFSET ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
<>	134:ad3be0349dc5	91	#define DAC_REG_DHR8R2_REGOFFSET ((uint32_t)0x05000000U) /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
<>	134:ad3be0349dc5	92	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	93	#define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U)
<>	134:ad3be0349dc5	94	#define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U)
<>	134:ad3be0349dc5	95	#define DAC_REG_DHR8RX_REGOFFSET_MASK ((uint32_t)0x0F000000U)
<>	134:ad3be0349dc5	96	#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK \| DAC_REG_DHR12LX_REGOFFSET_MASK \| DAC_REG_DHR8RX_REGOFFSET_MASK)
<>	134:ad3be0349dc5	97
<>	134:ad3be0349dc5	98	#define DAC_REG_DOR1_REGOFFSET ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */
<>	134:ad3be0349dc5	99	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	100	#define DAC_REG_DOR2_REGOFFSET ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
<>	134:ad3be0349dc5	101	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DOR2_REGOFFSET)
<>	134:ad3be0349dc5	102	#else
<>	134:ad3be0349dc5	103	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
<>	134:ad3be0349dc5	104	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	105
<>	134:ad3be0349dc5	106	#define DAC_REG_REGOFFSET_MASK_POSBIT0 ((uint32_t)0x0000000FU) /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */
<>	134:ad3be0349dc5	107
<>	134:ad3be0349dc5	108	#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS ((uint32_t)16U) /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
<>	134:ad3be0349dc5	109	#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS ((uint32_t)20U) /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
<>	134:ad3be0349dc5	110	#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS ((uint32_t)24U) /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
<>	134:ad3be0349dc5	111	#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS ((uint32_t)28U) /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
<>	134:ad3be0349dc5	112
<>	134:ad3be0349dc5	113	/* DAC registers bits positions */
<>	134:ad3be0349dc5	114	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	115	#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
<>	134:ad3be0349dc5	116	#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
<>	134:ad3be0349dc5	117	#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
<>	134:ad3be0349dc5	118	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	119
<>	134:ad3be0349dc5	120	/* Miscellaneous data */
<>	134:ad3be0349dc5	121	#define DAC_DIGITAL_SCALE_12BITS ((uint32_t)4095U) /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
<>	134:ad3be0349dc5	122
<>	134:ad3be0349dc5	123	/**
<>	134:ad3be0349dc5	124	* @}
<>	134:ad3be0349dc5	125	*/
<>	134:ad3be0349dc5	126
<>	134:ad3be0349dc5	127
<>	134:ad3be0349dc5	128	/* Private macros ------------------------------------------------------------*/
<>	134:ad3be0349dc5	129	/** @defgroup DAC_LL_Private_Macros DAC Private Macros
<>	134:ad3be0349dc5	130	* @{
<>	134:ad3be0349dc5	131	*/
<>	134:ad3be0349dc5	132
<>	134:ad3be0349dc5	133	/**
<>	134:ad3be0349dc5	134	* @brief Driver macro reserved for internal use: set a pointer to
<>	134:ad3be0349dc5	135	* a register from a register basis from which an offset
<>	134:ad3be0349dc5	136	* is applied.
<>	134:ad3be0349dc5	137	* @param __REG__ Register basis from which the offset is applied.
<>	134:ad3be0349dc5	138	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
<>	134:ad3be0349dc5	139	* @retval Pointer to register address
<>	134:ad3be0349dc5	140	*/
<>	134:ad3be0349dc5	141	#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
<>	134:ad3be0349dc5	142	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
<>	134:ad3be0349dc5	143
<>	134:ad3be0349dc5	144	/**
<>	134:ad3be0349dc5	145	* @}
<>	134:ad3be0349dc5	146	*/
<>	134:ad3be0349dc5	147
<>	134:ad3be0349dc5	148
<>	134:ad3be0349dc5	149	/* Exported types ------------------------------------------------------------*/
<>	134:ad3be0349dc5	150	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	151	/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
<>	134:ad3be0349dc5	152	* @{
<>	134:ad3be0349dc5	153	*/
<>	134:ad3be0349dc5	154
<>	134:ad3be0349dc5	155	/**
<>	134:ad3be0349dc5	156	* @brief Structure definition of some features of DAC instance.
<>	134:ad3be0349dc5	157	*/
<>	134:ad3be0349dc5	158	typedef struct
<>	134:ad3be0349dc5	159	{
<>	134:ad3be0349dc5	160	uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
<>	134:ad3be0349dc5	161	This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
<>	134:ad3be0349dc5	162
<>	134:ad3be0349dc5	163	This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
<>	134:ad3be0349dc5	164
<>	134:ad3be0349dc5	165	#if defined(DAC_CR_WAVE1)
<>	134:ad3be0349dc5	166	uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
<>	134:ad3be0349dc5	167	This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
<>	134:ad3be0349dc5	168
<>	134:ad3be0349dc5	169	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
<>	134:ad3be0349dc5	170
<>	134:ad3be0349dc5	171	uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
<>	134:ad3be0349dc5	172	If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
<>	134:ad3be0349dc5	173	If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
<>	134:ad3be0349dc5	174	@note If waveform automatic generation mode is disabled, this parameter is discarded.
<>	134:ad3be0349dc5	175
<>	134:ad3be0349dc5	176	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
<>	134:ad3be0349dc5	177	#endif
<>	134:ad3be0349dc5	178
<>	134:ad3be0349dc5	179	uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
<>	134:ad3be0349dc5	180	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
<>	134:ad3be0349dc5	181
<>	134:ad3be0349dc5	182	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
<>	134:ad3be0349dc5	183
<>	134:ad3be0349dc5	184	} LL_DAC_InitTypeDef;
<>	134:ad3be0349dc5	185
<>	134:ad3be0349dc5	186	/**
<>	134:ad3be0349dc5	187	* @}
<>	134:ad3be0349dc5	188	*/
<>	134:ad3be0349dc5	189	#endif /* USE_FULL_LL_DRIVER */
<>	134:ad3be0349dc5	190
<>	134:ad3be0349dc5	191	/* Exported constants --------------------------------------------------------*/
<>	134:ad3be0349dc5	192	/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
<>	134:ad3be0349dc5	193	* @{
<>	134:ad3be0349dc5	194	*/
<>	134:ad3be0349dc5	195
<>	134:ad3be0349dc5	196	/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
<>	134:ad3be0349dc5	197	* @brief Flags defines which can be used with LL_DAC_ReadReg function
<>	134:ad3be0349dc5	198	* @{
<>	134:ad3be0349dc5	199	*/
<>	134:ad3be0349dc5	200	/* DAC channel 1 flags */
<>	134:ad3be0349dc5	201	#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /!< DAC channel 1 flag DMA underrun /
<>	134:ad3be0349dc5	202
<>	134:ad3be0349dc5	203	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	204	/* DAC channel 2 flags */
<>	134:ad3be0349dc5	205	#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /!< DAC channel 2 flag DMA underrun /
<>	134:ad3be0349dc5	206	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	207	/**
<>	134:ad3be0349dc5	208	* @}
<>	134:ad3be0349dc5	209	*/
<>	134:ad3be0349dc5	210
<>	134:ad3be0349dc5	211	/** @defgroup DAC_LL_EC_IT DAC interruptions
<>	134:ad3be0349dc5	212	* @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
<>	134:ad3be0349dc5	213	* @{
<>	134:ad3be0349dc5	214	*/
<>	134:ad3be0349dc5	215	#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /!< DAC channel 1 interruption DMA underrun /
<>	134:ad3be0349dc5	216	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	217	#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /!< DAC channel 2 interruption DMA underrun /
<>	134:ad3be0349dc5	218	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	219	/**
<>	134:ad3be0349dc5	220	* @}
<>	134:ad3be0349dc5	221	*/
<>	134:ad3be0349dc5	222
<>	134:ad3be0349dc5	223	/** @defgroup DAC_LL_EC_CHANNEL DAC channels
<>	134:ad3be0349dc5	224	* @{
<>	134:ad3be0349dc5	225	*/
<>	134:ad3be0349dc5	226	#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DHR12R1_REGOFFSET \| DAC_REG_DHR12L1_REGOFFSET \| DAC_REG_DHR8R1_REGOFFSET \| DAC_CR_CH1_BITOFFSET \| DAC_SWTR_CH1) /!< DAC channel 1 /
<>	134:ad3be0349dc5	227	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	228	#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET \| DAC_REG_DHR12R2_REGOFFSET \| DAC_REG_DHR12L2_REGOFFSET \| DAC_REG_DHR8R2_REGOFFSET \| DAC_CR_CH2_BITOFFSET \| DAC_SWTR_CH2) /!< DAC channel 2 /
<>	134:ad3be0349dc5	229	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	230	/**
<>	134:ad3be0349dc5	231	* @}
<>	134:ad3be0349dc5	232	*/
<>	134:ad3be0349dc5	233
<>	134:ad3be0349dc5	234	/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
<>	134:ad3be0349dc5	235	* @{
<>	134:ad3be0349dc5	236	*/
<>	134:ad3be0349dc5	237	#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger internal (SW start) /
<>	134:ad3be0349dc5	238	#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /!< DAC channel conversion trigger from external IP: TIM2 TRGO. /
<>	134:ad3be0349dc5	239	#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM3 TRGO. /
<>	134:ad3be0349dc5	240	#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM4 TRGO. /
<>	134:ad3be0349dc5	241	#define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /!< DAC channel conversion trigger from external IP: TIM6 TRGO. /
<>	134:ad3be0349dc5	242	#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: TIM7 TRGO. /
<>	134:ad3be0349dc5	243	#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM15 TRGO. /
<>	134:ad3be0349dc5	244	#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: external interrupt line 9. /
<>	134:ad3be0349dc5	245	/**
<>	134:ad3be0349dc5	246	* @}
<>	134:ad3be0349dc5	247	*/
<>	134:ad3be0349dc5	248
<>	134:ad3be0349dc5	249	/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
<>	134:ad3be0349dc5	250	* @{
<>	134:ad3be0349dc5	251	*/
<>	134:ad3be0349dc5	252	#define LL_DAC_WAVE_AUTO_GENERATION_NONE ((uint32_t)0x00000000U) /!< DAC channel wave auto generation mode disabled. /
<>	134:ad3be0349dc5	253	#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /!< DAC channel wave auto generation mode enabled, set generated noise waveform. /
<>	134:ad3be0349dc5	254	#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /!< DAC channel wave auto generation mode enabled, set generated triangle waveform. /
<>	134:ad3be0349dc5	255	/**
<>	134:ad3be0349dc5	256	* @}
<>	134:ad3be0349dc5	257	*/
<>	134:ad3be0349dc5	258
<>	134:ad3be0349dc5	259	/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
<>	134:ad3be0349dc5	260	* @{
<>	134:ad3be0349dc5	261	*/
<>	134:ad3be0349dc5	262	#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 ((uint32_t)0x00000000U) /!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel /
<>	134:ad3be0349dc5	263	#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel /
<>	134:ad3be0349dc5	264	#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel /
<>	134:ad3be0349dc5	265	#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel /
<>	134:ad3be0349dc5	266	#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel /
<>	134:ad3be0349dc5	267	#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel /
<>	134:ad3be0349dc5	268	#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel /
<>	134:ad3be0349dc5	269	#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel /
<>	134:ad3be0349dc5	270	#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel /
<>	134:ad3be0349dc5	271	#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel /
<>	134:ad3be0349dc5	272	#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel /
<>	134:ad3be0349dc5	273	#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel /
<>	134:ad3be0349dc5	274	/**
<>	134:ad3be0349dc5	275	* @}
<>	134:ad3be0349dc5	276	*/
<>	134:ad3be0349dc5	277
<>	134:ad3be0349dc5	278	/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
<>	134:ad3be0349dc5	279	* @{
<>	134:ad3be0349dc5	280	*/
<>	134:ad3be0349dc5	281	#define LL_DAC_TRIANGLE_AMPLITUDE_1 ((uint32_t)0x00000000U) /!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel /
<>	134:ad3be0349dc5	282	#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel /
<>	134:ad3be0349dc5	283	#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel /
<>	134:ad3be0349dc5	284	#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel /
<>	134:ad3be0349dc5	285	#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel /
<>	134:ad3be0349dc5	286	#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel /
<>	134:ad3be0349dc5	287	#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel /
<>	134:ad3be0349dc5	288	#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel /
<>	134:ad3be0349dc5	289	#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel /
<>	134:ad3be0349dc5	290	#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel /
<>	134:ad3be0349dc5	291	#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel /
<>	134:ad3be0349dc5	292	#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel /
<>	134:ad3be0349dc5	293	/**
<>	134:ad3be0349dc5	294	* @}
<>	134:ad3be0349dc5	295	*/
<>	134:ad3be0349dc5	296
<>	134:ad3be0349dc5	297	/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
<>	134:ad3be0349dc5	298	* @{
<>	134:ad3be0349dc5	299	*/
<>	134:ad3be0349dc5	300	#define LL_DAC_OUTPUT_BUFFER_ENABLE ((uint32_t)0x00000000U) /!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption /
<>	134:ad3be0349dc5	301	#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption /
<>	134:ad3be0349dc5	302	/**
<>	134:ad3be0349dc5	303	* @}
<>	134:ad3be0349dc5	304	*/
<>	134:ad3be0349dc5	305
<>	134:ad3be0349dc5	306
<>	134:ad3be0349dc5	307	/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
<>	134:ad3be0349dc5	308	* @{
<>	134:ad3be0349dc5	309	*/
<>	134:ad3be0349dc5	310	#define LL_DAC_RESOLUTION_12B ((uint32_t)0x00000000U) /!< DAC channel resolution 12 bits /
<>	134:ad3be0349dc5	311	#define LL_DAC_RESOLUTION_8B ((uint32_t)0x00000002U) /!< DAC channel resolution 8 bits /
<>	134:ad3be0349dc5	312	/**
<>	134:ad3be0349dc5	313	* @}
<>	134:ad3be0349dc5	314	*/
<>	134:ad3be0349dc5	315
<>	134:ad3be0349dc5	316	/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
<>	134:ad3be0349dc5	317	* @{
<>	134:ad3be0349dc5	318	*/
<>	134:ad3be0349dc5	319	/* List of DAC registers intended to be used (most commonly) with */
<>	134:ad3be0349dc5	320	/* DMA transfer. */
<>	134:ad3be0349dc5	321	/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
<>	134:ad3be0349dc5	322	#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 12 bits right aligned /
<>	134:ad3be0349dc5	323	#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 12 bits left aligned /
<>	134:ad3be0349dc5	324	#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 8 bits right aligned /
<>	134:ad3be0349dc5	325	/**
<>	134:ad3be0349dc5	326	* @}
<>	134:ad3be0349dc5	327	*/
<>	134:ad3be0349dc5	328
<>	134:ad3be0349dc5	329	/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
<>	134:ad3be0349dc5	330	* @note Only DAC IP HW delays are defined in DAC LL driver driver,
<>	134:ad3be0349dc5	331	* not timeout values.
<>	134:ad3be0349dc5	332	* For details on delays values, refer to descriptions in source code
<>	134:ad3be0349dc5	333	* above each literal definition.
<>	134:ad3be0349dc5	334	* @{
<>	134:ad3be0349dc5	335	*/
<>	134:ad3be0349dc5	336
<>	134:ad3be0349dc5	337	/* Delay for DAC channel voltage settling time from DAC channel startup */
<>	134:ad3be0349dc5	338	/* (transition from disable to enable). */
<>	134:ad3be0349dc5	339	/* Note: DAC channel startup time depends on board application environment: */
<>	134:ad3be0349dc5	340	/* impedance connected to DAC channel output. */
<>	134:ad3be0349dc5	341	/* The delay below is specified under conditions: */
<>	134:ad3be0349dc5	342	/* - voltage maximum transition (lowest to highest value) */
<>	134:ad3be0349dc5	343	/* - until voltage reaches final value +-1LSB */
<>	134:ad3be0349dc5	344	/* - DAC channel output buffer enabled */
<>	134:ad3be0349dc5	345	/* - load impedance of 5kOhm (min), 50pF (max) */
<>	134:ad3be0349dc5	346	/* Literal set to maximum value (refer to device datasheet, */
<>	134:ad3be0349dc5	347	/* parameter "tWAKEUP"). */
<>	134:ad3be0349dc5	348	/* Unit: us */
<>	134:ad3be0349dc5	349	#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 15U) /!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) /
<>	134:ad3be0349dc5	350
<>	134:ad3be0349dc5	351	/* Delay for DAC channel voltage settling time. */
<>	134:ad3be0349dc5	352	/* Note: DAC channel startup time depends on board application environment: */
<>	134:ad3be0349dc5	353	/* impedance connected to DAC channel output. */
<>	134:ad3be0349dc5	354	/* The delay below is specified under conditions: */
<>	134:ad3be0349dc5	355	/* - voltage maximum transition (lowest to highest value) */
<>	134:ad3be0349dc5	356	/* - until voltage reaches final value +-1LSB */
<>	134:ad3be0349dc5	357	/* - DAC channel output buffer enabled */
<>	134:ad3be0349dc5	358	/* - load impedance of 5kOhm min, 50pF max */
<>	134:ad3be0349dc5	359	/* Literal set to maximum value (refer to device datasheet, */
<>	134:ad3be0349dc5	360	/* parameter "tSETTLING"). */
<>	134:ad3be0349dc5	361	/* Unit: us */
<>	134:ad3be0349dc5	362	#define LL_DAC_DELAY_VOLTAGE_SETTLING_US ((uint32_t) 12U) /!< Delay for DAC channel voltage settling time /
<>	134:ad3be0349dc5	363	/**
<>	134:ad3be0349dc5	364	* @}
<>	134:ad3be0349dc5	365	*/
<>	134:ad3be0349dc5	366
<>	134:ad3be0349dc5	367	/**
<>	134:ad3be0349dc5	368	* @}
<>	134:ad3be0349dc5	369	*/
<>	134:ad3be0349dc5	370
<>	134:ad3be0349dc5	371	/* Exported macro ------------------------------------------------------------*/
<>	134:ad3be0349dc5	372	/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
<>	134:ad3be0349dc5	373	* @{
<>	134:ad3be0349dc5	374	*/
<>	134:ad3be0349dc5	375
<>	134:ad3be0349dc5	376	/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
<>	134:ad3be0349dc5	377	* @{
<>	134:ad3be0349dc5	378	*/
<>	134:ad3be0349dc5	379
<>	134:ad3be0349dc5	380	/**
<>	134:ad3be0349dc5	381	* @brief Write a value in DAC register
<>	134:ad3be0349dc5	382	* @param __INSTANCE__ DAC Instance
<>	134:ad3be0349dc5	383	* @param __REG__ Register to be written
<>	134:ad3be0349dc5	384	* @param __VALUE__ Value to be written in the register
<>	134:ad3be0349dc5	385	* @retval None
<>	134:ad3be0349dc5	386	*/
<>	134:ad3be0349dc5	387	#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	134:ad3be0349dc5	388
<>	134:ad3be0349dc5	389	/**
<>	134:ad3be0349dc5	390	* @brief Read a value in DAC register
<>	134:ad3be0349dc5	391	* @param __INSTANCE__ DAC Instance
<>	134:ad3be0349dc5	392	* @param __REG__ Register to be read
<>	134:ad3be0349dc5	393	* @retval Register value
<>	134:ad3be0349dc5	394	*/
<>	134:ad3be0349dc5	395	#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	134:ad3be0349dc5	396
<>	134:ad3be0349dc5	397	/**
<>	134:ad3be0349dc5	398	* @}
<>	134:ad3be0349dc5	399	*/
<>	134:ad3be0349dc5	400
<>	134:ad3be0349dc5	401	/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
<>	134:ad3be0349dc5	402	* @{
<>	134:ad3be0349dc5	403	*/
<>	134:ad3be0349dc5	404
<>	134:ad3be0349dc5	405	/**
<>	134:ad3be0349dc5	406	* @brief Helper macro to get DAC channel number in decimal format
<>	134:ad3be0349dc5	407	* from literals LL_DAC_CHANNEL_x.
<>	134:ad3be0349dc5	408	* Example:
<>	134:ad3be0349dc5	409	* __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
<>	134:ad3be0349dc5	410	* will return decimal number "1".
<>	134:ad3be0349dc5	411	* @note The input can be a value from functions where a channel
<>	134:ad3be0349dc5	412	* number is returned.
<>	134:ad3be0349dc5	413	* @param __CHANNEL__ This parameter can be one of the following values:
<>	134:ad3be0349dc5	414	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	415	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	416	*
<>	134:ad3be0349dc5	417	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	418	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	419	* @retval 1...2 (value "2" depending on DAC channel 2 availability)
<>	134:ad3be0349dc5	420	*/
<>	134:ad3be0349dc5	421	#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
<>	134:ad3be0349dc5	422	((__CHANNEL__) & DAC_SWTR_CHX_MASK)
<>	134:ad3be0349dc5	423
<>	134:ad3be0349dc5	424	/**
<>	134:ad3be0349dc5	425	* @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
<>	134:ad3be0349dc5	426	* from number in decimal format.
<>	134:ad3be0349dc5	427	* Example:
<>	134:ad3be0349dc5	428	* __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
<>	134:ad3be0349dc5	429	* will return a data equivalent to "LL_DAC_CHANNEL_1".
<>	134:ad3be0349dc5	430	* @note If the input parameter does not correspond to a DAC channel,
<>	134:ad3be0349dc5	431	* this macro returns value '0'.
<>	134:ad3be0349dc5	432	* @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
<>	134:ad3be0349dc5	433	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	434	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	435	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	436	*
<>	134:ad3be0349dc5	437	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	438	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	439	*/
<>	134:ad3be0349dc5	440	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	441	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<>	134:ad3be0349dc5	442	(((__DECIMAL_NB__) == 1U) \
<>	134:ad3be0349dc5	443	? ( \
<>	134:ad3be0349dc5	444	LL_DAC_CHANNEL_1 \
<>	134:ad3be0349dc5	445	) \
<>	134:ad3be0349dc5	446	: \
<>	134:ad3be0349dc5	447	(((__DECIMAL_NB__) == 2U) \
<>	134:ad3be0349dc5	448	? ( \
<>	134:ad3be0349dc5	449	LL_DAC_CHANNEL_2 \
<>	134:ad3be0349dc5	450	) \
<>	134:ad3be0349dc5	451	: \
<>	134:ad3be0349dc5	452	( \
<>	134:ad3be0349dc5	453	0 \
<>	134:ad3be0349dc5	454	) \
<>	134:ad3be0349dc5	455	) \
<>	134:ad3be0349dc5	456	)
<>	134:ad3be0349dc5	457	#else
<>	134:ad3be0349dc5	458	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<>	134:ad3be0349dc5	459	(((__DECIMAL_NB__) == 1U) \
<>	134:ad3be0349dc5	460	? ( \
<>	134:ad3be0349dc5	461	LL_DAC_CHANNEL_1 \
<>	134:ad3be0349dc5	462	) \
<>	134:ad3be0349dc5	463	: \
<>	134:ad3be0349dc5	464	( \
<>	134:ad3be0349dc5	465	0 \
<>	134:ad3be0349dc5	466	) \
<>	134:ad3be0349dc5	467	)
<>	134:ad3be0349dc5	468	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	469
<>	134:ad3be0349dc5	470	/**
<>	134:ad3be0349dc5	471	* @brief Helper macro to define the DAC conversion data full-scale digital
<>	134:ad3be0349dc5	472	* value corresponding to the selected DAC resolution.
<>	134:ad3be0349dc5	473	* @note DAC conversion data full-scale corresponds to voltage range
<>	134:ad3be0349dc5	474	* determined by analog voltage references Vref+ and Vref-
<>	134:ad3be0349dc5	475	* (refer to reference manual).
<>	134:ad3be0349dc5	476	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
<>	134:ad3be0349dc5	477	* @arg @ref LL_DAC_RESOLUTION_12B
<>	134:ad3be0349dc5	478	* @arg @ref LL_DAC_RESOLUTION_8B
<>	134:ad3be0349dc5	479	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	134:ad3be0349dc5	480	*/
<>	134:ad3be0349dc5	481	#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
<>	134:ad3be0349dc5	482	(((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U))
<>	134:ad3be0349dc5	483
<>	134:ad3be0349dc5	484	/**
<>	134:ad3be0349dc5	485	* @brief Helper macro to calculate the DAC conversion data (unit: digital
<>	134:ad3be0349dc5	486	* value) corresponding to a voltage (unit: mVolt).
<>	134:ad3be0349dc5	487	* @note This helper macro is intended to provide input data in voltage
<>	134:ad3be0349dc5	488	* rather than digital value,
<>	134:ad3be0349dc5	489	* to be used with LL DAC functions such as
<>	134:ad3be0349dc5	490	* @ref LL_DAC_ConvertData12RightAligned().
<>	134:ad3be0349dc5	491	* @note Analog reference voltage (Vref+) must be either known from
<>	134:ad3be0349dc5	492	* user board environment or can be calculated using ADC measurement
<>	134:ad3be0349dc5	493	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	134:ad3be0349dc5	494	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<>	134:ad3be0349dc5	495	* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
<>	134:ad3be0349dc5	496	* (unit: mVolt).
<>	134:ad3be0349dc5	497	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
<>	134:ad3be0349dc5	498	* @arg @ref LL_DAC_RESOLUTION_12B
<>	134:ad3be0349dc5	499	* @arg @ref LL_DAC_RESOLUTION_8B
<>	134:ad3be0349dc5	500	* @retval DAC conversion data (unit: digital value)
<>	134:ad3be0349dc5	501	*/
<>	134:ad3be0349dc5	502	#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
<>	134:ad3be0349dc5	503	__DAC_VOLTAGE__,\
<>	134:ad3be0349dc5	504	__DAC_RESOLUTION__) \
<>	134:ad3be0349dc5	505	((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
<>	134:ad3be0349dc5	506	/ (__VREFANALOG_VOLTAGE__) \
<>	134:ad3be0349dc5	507	)
<>	134:ad3be0349dc5	508
<>	134:ad3be0349dc5	509	/**
<>	134:ad3be0349dc5	510	* @}
<>	134:ad3be0349dc5	511	*/
<>	134:ad3be0349dc5	512
<>	134:ad3be0349dc5	513	/**
<>	134:ad3be0349dc5	514	* @}
<>	134:ad3be0349dc5	515	*/
<>	134:ad3be0349dc5	516
<>	134:ad3be0349dc5	517
<>	134:ad3be0349dc5	518	/* Exported functions --------------------------------------------------------*/
<>	134:ad3be0349dc5	519	/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
<>	134:ad3be0349dc5	520	* @{
<>	134:ad3be0349dc5	521	*/
<>	134:ad3be0349dc5	522	/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
<>	134:ad3be0349dc5	523	* @{
<>	134:ad3be0349dc5	524	*/
<>	134:ad3be0349dc5	525
<>	134:ad3be0349dc5	526	/**
<>	134:ad3be0349dc5	527	* @brief Set the conversion trigger source for the selected DAC channel.
<>	134:ad3be0349dc5	528	* @note For conversion trigger source to be effective, DAC trigger
<>	134:ad3be0349dc5	529	* must be enabled using function @ref LL_DAC_EnableTrigger().
<>	134:ad3be0349dc5	530	* @note To set conversion trigger source, DAC channel must be disabled.
<>	134:ad3be0349dc5	531	* Otherwise, the setting is discarded.
<>	134:ad3be0349dc5	532	* @note Availability of parameters of trigger sources from timer
<>	134:ad3be0349dc5	533	* depends on timers availability on the selected device.
<>	134:ad3be0349dc5	534	* @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
<>	134:ad3be0349dc5	535	* CR TSEL2 LL_DAC_SetTriggerSource
<>	134:ad3be0349dc5	536	* @param DACx DAC instance
<>	134:ad3be0349dc5	537	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	538	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	539	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	540	*
<>	134:ad3be0349dc5	541	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	542	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	543	* @param TriggerSource This parameter can be one of the following values:
<>	134:ad3be0349dc5	544	* @arg @ref LL_DAC_TRIG_SOFTWARE
<>	134:ad3be0349dc5	545	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
<>	134:ad3be0349dc5	546	* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
<>	134:ad3be0349dc5	547	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
<>	134:ad3be0349dc5	548	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
<>	134:ad3be0349dc5	549	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
<>	134:ad3be0349dc5	550	* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
<>	134:ad3be0349dc5	551	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
<>	134:ad3be0349dc5	552	* @retval None
<>	134:ad3be0349dc5	553	*/
<>	134:ad3be0349dc5	554	__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
<>	134:ad3be0349dc5	555	{
<>	134:ad3be0349dc5	556	MODIFY_REG(DACx->CR,
<>	134:ad3be0349dc5	557	DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	134:ad3be0349dc5	558	TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	134:ad3be0349dc5	559	}
<>	134:ad3be0349dc5	560
<>	134:ad3be0349dc5	561	/**
<>	134:ad3be0349dc5	562	* @brief Get the conversion trigger source for the selected DAC channel.
<>	134:ad3be0349dc5	563	* @note For conversion trigger source to be effective, DAC trigger
<>	134:ad3be0349dc5	564	* must be enabled using function @ref LL_DAC_EnableTrigger().
<>	134:ad3be0349dc5	565	* @note Availability of parameters of trigger sources from timer
<>	134:ad3be0349dc5	566	* depends on timers availability on the selected device.
<>	134:ad3be0349dc5	567	* @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
<>	134:ad3be0349dc5	568	* CR TSEL2 LL_DAC_GetTriggerSource
<>	134:ad3be0349dc5	569	* @param DACx DAC instance
<>	134:ad3be0349dc5	570	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	571	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	572	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	573	*
<>	134:ad3be0349dc5	574	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	575	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	576	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	577	* @arg @ref LL_DAC_TRIG_SOFTWARE
<>	134:ad3be0349dc5	578	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
<>	134:ad3be0349dc5	579	* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
<>	134:ad3be0349dc5	580	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
<>	134:ad3be0349dc5	581	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
<>	134:ad3be0349dc5	582	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
<>	134:ad3be0349dc5	583	* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
<>	134:ad3be0349dc5	584	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
<>	134:ad3be0349dc5	585	*/
<>	134:ad3be0349dc5	586	__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	587	{
<>	134:ad3be0349dc5	588	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	134:ad3be0349dc5	589	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	134:ad3be0349dc5	590	);
<>	134:ad3be0349dc5	591	}
<>	134:ad3be0349dc5	592
<>	134:ad3be0349dc5	593	#if defined(DAC_CR_WAVE1)
<>	134:ad3be0349dc5	594	/**
<>	134:ad3be0349dc5	595	* @brief Set the waveform automatic generation mode
<>	134:ad3be0349dc5	596	* for the selected DAC channel.
<>	134:ad3be0349dc5	597	* @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
<>	134:ad3be0349dc5	598	* CR WAVE2 LL_DAC_SetWaveAutoGeneration
<>	134:ad3be0349dc5	599	* @param DACx DAC instance
<>	134:ad3be0349dc5	600	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	601	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	602	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	603	*
<>	134:ad3be0349dc5	604	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	605	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	606	* @param WaveAutoGeneration This parameter can be one of the following values:
<>	134:ad3be0349dc5	607	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
<>	134:ad3be0349dc5	608	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
<>	134:ad3be0349dc5	609	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
<>	134:ad3be0349dc5	610	* @retval None
<>	134:ad3be0349dc5	611	*/
<>	134:ad3be0349dc5	612	__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
<>	134:ad3be0349dc5	613	{
<>	134:ad3be0349dc5	614	MODIFY_REG(DACx->CR,
<>	134:ad3be0349dc5	615	DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	134:ad3be0349dc5	616	WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	134:ad3be0349dc5	617	}
<>	134:ad3be0349dc5	618
<>	134:ad3be0349dc5	619	/**
<>	134:ad3be0349dc5	620	* @brief Get the waveform automatic generation mode
<>	134:ad3be0349dc5	621	* for the selected DAC channel.
<>	134:ad3be0349dc5	622	* @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
<>	134:ad3be0349dc5	623	* CR WAVE2 LL_DAC_GetWaveAutoGeneration
<>	134:ad3be0349dc5	624	* @param DACx DAC instance
<>	134:ad3be0349dc5	625	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	626	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	627	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	628	*
<>	134:ad3be0349dc5	629	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	630	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	631	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	632	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
<>	134:ad3be0349dc5	633	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
<>	134:ad3be0349dc5	634	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
<>	134:ad3be0349dc5	635	*/
<>	134:ad3be0349dc5	636	__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	637	{
<>	134:ad3be0349dc5	638	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	134:ad3be0349dc5	639	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	134:ad3be0349dc5	640	);
<>	134:ad3be0349dc5	641	}
<>	134:ad3be0349dc5	642
<>	134:ad3be0349dc5	643	/**
<>	134:ad3be0349dc5	644	* @brief Set the noise waveform generation for the selected DAC channel:
<>	134:ad3be0349dc5	645	* Noise mode and parameters LFSR (linear feedback shift register).
<>	134:ad3be0349dc5	646	* @note For wave generation to be effective, DAC channel
<>	134:ad3be0349dc5	647	* wave generation mode must be enabled using
<>	134:ad3be0349dc5	648	* function @ref LL_DAC_SetWaveAutoGeneration().
<>	134:ad3be0349dc5	649	* @note This setting can be set when the selected DAC channel is disabled
<>	134:ad3be0349dc5	650	* (otherwise, the setting operation is ignored).
<>	134:ad3be0349dc5	651	* @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
<>	134:ad3be0349dc5	652	* CR MAMP2 LL_DAC_SetWaveNoiseLFSR
<>	134:ad3be0349dc5	653	* @param DACx DAC instance
<>	134:ad3be0349dc5	654	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	655	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	656	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	657	*
<>	134:ad3be0349dc5	658	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	659	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	660	* @param NoiseLFSRMask This parameter can be one of the following values:
<>	134:ad3be0349dc5	661	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
<>	134:ad3be0349dc5	662	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
<>	134:ad3be0349dc5	663	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
<>	134:ad3be0349dc5	664	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
<>	134:ad3be0349dc5	665	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
<>	134:ad3be0349dc5	666	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
<>	134:ad3be0349dc5	667	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
<>	134:ad3be0349dc5	668	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
<>	134:ad3be0349dc5	669	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
<>	134:ad3be0349dc5	670	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
<>	134:ad3be0349dc5	671	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
<>	134:ad3be0349dc5	672	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
<>	134:ad3be0349dc5	673	* @retval None
<>	134:ad3be0349dc5	674	*/
<>	134:ad3be0349dc5	675	__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
<>	134:ad3be0349dc5	676	{
<>	134:ad3be0349dc5	677	MODIFY_REG(DACx->CR,
<>	134:ad3be0349dc5	678	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	134:ad3be0349dc5	679	NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	134:ad3be0349dc5	680	}
<>	134:ad3be0349dc5	681
<>	134:ad3be0349dc5	682	/**
<>	134:ad3be0349dc5	683	* @brief Set the noise waveform generation for the selected DAC channel:
<>	134:ad3be0349dc5	684	* Noise mode and parameters LFSR (linear feedback shift register).
<>	134:ad3be0349dc5	685	* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
<>	134:ad3be0349dc5	686	* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
<>	134:ad3be0349dc5	687	* @param DACx DAC instance
<>	134:ad3be0349dc5	688	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	689	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	690	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	691	*
<>	134:ad3be0349dc5	692	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	693	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	694	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	695	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
<>	134:ad3be0349dc5	696	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
<>	134:ad3be0349dc5	697	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
<>	134:ad3be0349dc5	698	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
<>	134:ad3be0349dc5	699	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
<>	134:ad3be0349dc5	700	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
<>	134:ad3be0349dc5	701	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
<>	134:ad3be0349dc5	702	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
<>	134:ad3be0349dc5	703	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
<>	134:ad3be0349dc5	704	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
<>	134:ad3be0349dc5	705	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
<>	134:ad3be0349dc5	706	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
<>	134:ad3be0349dc5	707	*/
<>	134:ad3be0349dc5	708	__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	709	{
<>	134:ad3be0349dc5	710	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	134:ad3be0349dc5	711	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	134:ad3be0349dc5	712	);
<>	134:ad3be0349dc5	713	}
<>	134:ad3be0349dc5	714
<>	134:ad3be0349dc5	715	/**
<>	134:ad3be0349dc5	716	* @brief Set the triangle waveform generation for the selected DAC channel:
<>	134:ad3be0349dc5	717	* triangle mode and amplitude.
<>	134:ad3be0349dc5	718	* @note For wave generation to be effective, DAC channel
<>	134:ad3be0349dc5	719	* wave generation mode must be enabled using
<>	134:ad3be0349dc5	720	* function @ref LL_DAC_SetWaveAutoGeneration().
<>	134:ad3be0349dc5	721	* @note This setting can be set when the selected DAC channel is disabled
<>	134:ad3be0349dc5	722	* (otherwise, the setting operation is ignored).
<>	134:ad3be0349dc5	723	* @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
<>	134:ad3be0349dc5	724	* CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
<>	134:ad3be0349dc5	725	* @param DACx DAC instance
<>	134:ad3be0349dc5	726	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	727	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	728	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	729	*
<>	134:ad3be0349dc5	730	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	731	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	732	* @param TriangleAmplitude This parameter can be one of the following values:
<>	134:ad3be0349dc5	733	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
<>	134:ad3be0349dc5	734	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
<>	134:ad3be0349dc5	735	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
<>	134:ad3be0349dc5	736	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
<>	134:ad3be0349dc5	737	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
<>	134:ad3be0349dc5	738	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
<>	134:ad3be0349dc5	739	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
<>	134:ad3be0349dc5	740	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
<>	134:ad3be0349dc5	741	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
<>	134:ad3be0349dc5	742	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
<>	134:ad3be0349dc5	743	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
<>	134:ad3be0349dc5	744	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
<>	134:ad3be0349dc5	745	* @retval None
<>	134:ad3be0349dc5	746	*/
<>	134:ad3be0349dc5	747	__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
<>	134:ad3be0349dc5	748	{
<>	134:ad3be0349dc5	749	MODIFY_REG(DACx->CR,
<>	134:ad3be0349dc5	750	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	134:ad3be0349dc5	751	TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	134:ad3be0349dc5	752	}
<>	134:ad3be0349dc5	753
<>	134:ad3be0349dc5	754	/**
<>	134:ad3be0349dc5	755	* @brief Set the triangle waveform generation for the selected DAC channel:
<>	134:ad3be0349dc5	756	* triangle mode and amplitude.
<>	134:ad3be0349dc5	757	* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
<>	134:ad3be0349dc5	758	* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
<>	134:ad3be0349dc5	759	* @param DACx DAC instance
<>	134:ad3be0349dc5	760	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	761	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	762	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	763	*
<>	134:ad3be0349dc5	764	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	765	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	766	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	767	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
<>	134:ad3be0349dc5	768	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
<>	134:ad3be0349dc5	769	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
<>	134:ad3be0349dc5	770	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
<>	134:ad3be0349dc5	771	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
<>	134:ad3be0349dc5	772	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
<>	134:ad3be0349dc5	773	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
<>	134:ad3be0349dc5	774	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
<>	134:ad3be0349dc5	775	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
<>	134:ad3be0349dc5	776	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
<>	134:ad3be0349dc5	777	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
<>	134:ad3be0349dc5	778	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
<>	134:ad3be0349dc5	779	*/
<>	134:ad3be0349dc5	780	__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	781	{
<>	134:ad3be0349dc5	782	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	134:ad3be0349dc5	783	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	134:ad3be0349dc5	784	);
<>	134:ad3be0349dc5	785	}
<>	134:ad3be0349dc5	786	#endif
<>	134:ad3be0349dc5	787
<>	134:ad3be0349dc5	788	/**
<>	134:ad3be0349dc5	789	* @brief Set the output buffer for the selected DAC channel.
<>	134:ad3be0349dc5	790	* @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
<>	134:ad3be0349dc5	791	* CR BOFF2 LL_DAC_SetOutputBuffer
<>	134:ad3be0349dc5	792	* @param DACx DAC instance
<>	134:ad3be0349dc5	793	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	794	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	795	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	796	*
<>	134:ad3be0349dc5	797	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	798	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	799	* @param OutputBuffer This parameter can be one of the following values:
<>	134:ad3be0349dc5	800	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
<>	134:ad3be0349dc5	801	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
<>	134:ad3be0349dc5	802	* @retval None
<>	134:ad3be0349dc5	803	*/
<>	134:ad3be0349dc5	804	__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
<>	134:ad3be0349dc5	805	{
<>	134:ad3be0349dc5	806	MODIFY_REG(DACx->CR,
<>	134:ad3be0349dc5	807	DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	134:ad3be0349dc5	808	OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	134:ad3be0349dc5	809	}
<>	134:ad3be0349dc5	810
<>	134:ad3be0349dc5	811	/**
<>	134:ad3be0349dc5	812	* @brief Get the output buffer state for the selected DAC channel.
<>	134:ad3be0349dc5	813	* @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
<>	134:ad3be0349dc5	814	* CR BOFF2 LL_DAC_GetOutputBuffer
<>	134:ad3be0349dc5	815	* @param DACx DAC instance
<>	134:ad3be0349dc5	816	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	817	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	818	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	819	*
<>	134:ad3be0349dc5	820	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	821	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	822	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	823	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
<>	134:ad3be0349dc5	824	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
<>	134:ad3be0349dc5	825	*/
<>	134:ad3be0349dc5	826	__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	827	{
<>	134:ad3be0349dc5	828	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	134:ad3be0349dc5	829	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	134:ad3be0349dc5	830	);
<>	134:ad3be0349dc5	831	}
<>	134:ad3be0349dc5	832
<>	134:ad3be0349dc5	833	/**
<>	134:ad3be0349dc5	834	* @}
<>	134:ad3be0349dc5	835	*/
<>	134:ad3be0349dc5	836
<>	134:ad3be0349dc5	837	/** @defgroup DAC_LL_EF_DMA_Management DMA Management
<>	134:ad3be0349dc5	838	* @{
<>	134:ad3be0349dc5	839	*/
<>	134:ad3be0349dc5	840
<>	134:ad3be0349dc5	841	/**
<>	134:ad3be0349dc5	842	* @brief Enable DAC DMA transfer request of the selected channel.
<>	134:ad3be0349dc5	843	* @note To configure DMA source address (peripheral address),
<>	134:ad3be0349dc5	844	* use function @ref LL_DAC_DMA_GetRegAddr().
<>	134:ad3be0349dc5	845	* @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
<>	134:ad3be0349dc5	846	* CR DMAEN2 LL_DAC_EnableDMAReq
<>	134:ad3be0349dc5	847	* @param DACx DAC instance
<>	134:ad3be0349dc5	848	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	849	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	850	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	851	*
<>	134:ad3be0349dc5	852	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	853	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	854	* @retval None
<>	134:ad3be0349dc5	855	*/
<>	134:ad3be0349dc5	856	__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	857	{
<>	134:ad3be0349dc5	858	SET_BIT(DACx->CR,
<>	134:ad3be0349dc5	859	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	134:ad3be0349dc5	860	}
<>	134:ad3be0349dc5	861
<>	134:ad3be0349dc5	862	/**
<>	134:ad3be0349dc5	863	* @brief Disable DAC DMA transfer request of the selected channel.
<>	134:ad3be0349dc5	864	* @note To configure DMA source address (peripheral address),
<>	134:ad3be0349dc5	865	* use function @ref LL_DAC_DMA_GetRegAddr().
<>	134:ad3be0349dc5	866	* @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
<>	134:ad3be0349dc5	867	* CR DMAEN2 LL_DAC_DisableDMAReq
<>	134:ad3be0349dc5	868	* @param DACx DAC instance
<>	134:ad3be0349dc5	869	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	870	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	871	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	872	*
<>	134:ad3be0349dc5	873	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	874	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	875	* @retval None
<>	134:ad3be0349dc5	876	*/
<>	134:ad3be0349dc5	877	__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	878	{
<>	134:ad3be0349dc5	879	CLEAR_BIT(DACx->CR,
<>	134:ad3be0349dc5	880	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	134:ad3be0349dc5	881	}
<>	134:ad3be0349dc5	882
<>	134:ad3be0349dc5	883	/**
<>	134:ad3be0349dc5	884	* @brief Get DAC DMA transfer request state of the selected channel.
<>	134:ad3be0349dc5	885	* (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
<>	134:ad3be0349dc5	886	* @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
<>	134:ad3be0349dc5	887	* CR DMAEN2 LL_DAC_IsDMAReqEnabled
<>	134:ad3be0349dc5	888	* @param DACx DAC instance
<>	134:ad3be0349dc5	889	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	890	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	891	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	892	*
<>	134:ad3be0349dc5	893	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	894	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	895	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	896	*/
<>	134:ad3be0349dc5	897	__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	898	{
<>	134:ad3be0349dc5	899	return (READ_BIT(DACx->CR,
<>	134:ad3be0349dc5	900	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	134:ad3be0349dc5	901	== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<>	134:ad3be0349dc5	902	}
<>	134:ad3be0349dc5	903
<>	134:ad3be0349dc5	904	/**
<>	134:ad3be0349dc5	905	* @brief Function to help to configure DMA transfer to DAC: retrieve the
<>	134:ad3be0349dc5	906	* DAC register address from DAC instance and a list of DAC registers
<>	134:ad3be0349dc5	907	* intended to be used (most commonly) with DMA transfer.
<>	134:ad3be0349dc5	908	* @note These DAC registers are data holding registers:
<>	134:ad3be0349dc5	909	* when DAC conversion is requested, DAC generates a DMA transfer
<>	134:ad3be0349dc5	910	* request to have data available in DAC data holding registers.
<>	134:ad3be0349dc5	911	* @note This macro is intended to be used with LL DMA driver, refer to
<>	134:ad3be0349dc5	912	* function "LL_DMA_ConfigAddresses()".
<>	134:ad3be0349dc5	913	* Example:
<>	134:ad3be0349dc5	914	* LL_DMA_ConfigAddresses(DMA1,
<>	134:ad3be0349dc5	915	* LL_DMA_CHANNEL_1,
<>	134:ad3be0349dc5	916	* (uint32_t)&< array or variable >,
<>	134:ad3be0349dc5	917	* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
<>	134:ad3be0349dc5	918	* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
<>	134:ad3be0349dc5	919	* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<>	134:ad3be0349dc5	920	* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<>	134:ad3be0349dc5	921	* DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<>	134:ad3be0349dc5	922	* DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
<>	134:ad3be0349dc5	923	* DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
<>	134:ad3be0349dc5	924	* DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
<>	134:ad3be0349dc5	925	* @param DACx DAC instance
<>	134:ad3be0349dc5	926	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	927	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	928	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	929	*
<>	134:ad3be0349dc5	930	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	931	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	932	* @param Register This parameter can be one of the following values:
<>	134:ad3be0349dc5	933	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
<>	134:ad3be0349dc5	934	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
<>	134:ad3be0349dc5	935	* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
<>	134:ad3be0349dc5	936	* @retval DAC register address
<>	134:ad3be0349dc5	937	*/
<>	134:ad3be0349dc5	938	__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
<>	134:ad3be0349dc5	939	{
<>	134:ad3be0349dc5	940	/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
<>	134:ad3be0349dc5	941	/* DAC channel selected. */
<>	134:ad3be0349dc5	942	return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REGOFFSET_MASK_POSBIT0))));
<>	134:ad3be0349dc5	943	}
<>	134:ad3be0349dc5	944	/**
<>	134:ad3be0349dc5	945	* @}
<>	134:ad3be0349dc5	946	*/
<>	134:ad3be0349dc5	947
<>	134:ad3be0349dc5	948	/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
<>	134:ad3be0349dc5	949	* @{
<>	134:ad3be0349dc5	950	*/
<>	134:ad3be0349dc5	951
<>	134:ad3be0349dc5	952	/**
<>	134:ad3be0349dc5	953	* @brief Enable DAC selected channel.
<>	134:ad3be0349dc5	954	* @rmtoll CR EN1 LL_DAC_Enable\n
<>	134:ad3be0349dc5	955	* CR EN2 LL_DAC_Enable
<>	134:ad3be0349dc5	956	* @note After enable from off state, DAC channel requires a delay
<>	134:ad3be0349dc5	957	* for output voltage to reach accuracy +/- 1 LSB.
<>	134:ad3be0349dc5	958	* Refer to device datasheet, parameter "tWAKEUP".
<>	134:ad3be0349dc5	959	* @param DACx DAC instance
<>	134:ad3be0349dc5	960	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	961	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	962	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	963	*
<>	134:ad3be0349dc5	964	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	965	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	966	* @retval None
<>	134:ad3be0349dc5	967	*/
<>	134:ad3be0349dc5	968	__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	969	{
<>	134:ad3be0349dc5	970	SET_BIT(DACx->CR,
<>	134:ad3be0349dc5	971	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	134:ad3be0349dc5	972	}
<>	134:ad3be0349dc5	973
<>	134:ad3be0349dc5	974	/**
<>	134:ad3be0349dc5	975	* @brief Disable DAC selected channel.
<>	134:ad3be0349dc5	976	* @rmtoll CR EN1 LL_DAC_Disable\n
<>	134:ad3be0349dc5	977	* CR EN2 LL_DAC_Disable
<>	134:ad3be0349dc5	978	* @param DACx DAC instance
<>	134:ad3be0349dc5	979	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	980	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	981	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	982	*
<>	134:ad3be0349dc5	983	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	984	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	985	* @retval None
<>	134:ad3be0349dc5	986	*/
<>	134:ad3be0349dc5	987	__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	988	{
<>	134:ad3be0349dc5	989	CLEAR_BIT(DACx->CR,
<>	134:ad3be0349dc5	990	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	134:ad3be0349dc5	991	}
<>	134:ad3be0349dc5	992
<>	134:ad3be0349dc5	993	/**
<>	134:ad3be0349dc5	994	* @brief Get DAC enable state of the selected channel.
<>	134:ad3be0349dc5	995	* (0: DAC channel is disabled, 1: DAC channel is enabled)
<>	134:ad3be0349dc5	996	* @rmtoll CR EN1 LL_DAC_IsEnabled\n
<>	134:ad3be0349dc5	997	* CR EN2 LL_DAC_IsEnabled
<>	134:ad3be0349dc5	998	* @param DACx DAC instance
<>	134:ad3be0349dc5	999	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1000	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	1001	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	1002	*
<>	134:ad3be0349dc5	1003	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	1004	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	1005	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1006	*/
<>	134:ad3be0349dc5	1007	__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	1008	{
<>	134:ad3be0349dc5	1009	return (READ_BIT(DACx->CR,
<>	134:ad3be0349dc5	1010	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	134:ad3be0349dc5	1011	== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<>	134:ad3be0349dc5	1012	}
<>	134:ad3be0349dc5	1013
<>	134:ad3be0349dc5	1014	/**
<>	134:ad3be0349dc5	1015	* @brief Enable DAC trigger of the selected channel.
<>	134:ad3be0349dc5	1016	* @note - If DAC trigger is disabled, DAC conversion is performed
<>	134:ad3be0349dc5	1017	* automatically once the data holding register is updated,
<>	134:ad3be0349dc5	1018	* using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
<>	134:ad3be0349dc5	1019	* @ref LL_DAC_ConvertData12RightAligned(), ...
<>	134:ad3be0349dc5	1020	* - If DAC trigger is enabled, DAC conversion is performed
<>	134:ad3be0349dc5	1021	* only when a hardware of software trigger event is occurring.
<>	134:ad3be0349dc5	1022	* Select trigger source using
<>	134:ad3be0349dc5	1023	* function @ref LL_DAC_SetTriggerSource().
<>	134:ad3be0349dc5	1024	* @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
<>	134:ad3be0349dc5	1025	* CR TEN2 LL_DAC_EnableTrigger
<>	134:ad3be0349dc5	1026	* @param DACx DAC instance
<>	134:ad3be0349dc5	1027	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1028	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	1029	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	1030	*
<>	134:ad3be0349dc5	1031	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	1032	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	1033	* @retval None
<>	134:ad3be0349dc5	1034	*/
<>	134:ad3be0349dc5	1035	__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	1036	{
<>	134:ad3be0349dc5	1037	SET_BIT(DACx->CR,
<>	134:ad3be0349dc5	1038	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	134:ad3be0349dc5	1039	}
<>	134:ad3be0349dc5	1040
<>	134:ad3be0349dc5	1041	/**
<>	134:ad3be0349dc5	1042	* @brief Disable DAC trigger of the selected channel.
<>	134:ad3be0349dc5	1043	* @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
<>	134:ad3be0349dc5	1044	* CR TEN2 LL_DAC_DisableTrigger
<>	134:ad3be0349dc5	1045	* @param DACx DAC instance
<>	134:ad3be0349dc5	1046	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1047	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	1048	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	1049	*
<>	134:ad3be0349dc5	1050	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	1051	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	1052	* @retval None
<>	134:ad3be0349dc5	1053	*/
<>	134:ad3be0349dc5	1054	__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	1055	{
<>	134:ad3be0349dc5	1056	CLEAR_BIT(DACx->CR,
<>	134:ad3be0349dc5	1057	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	134:ad3be0349dc5	1058	}
<>	134:ad3be0349dc5	1059
<>	134:ad3be0349dc5	1060	/**
<>	134:ad3be0349dc5	1061	* @brief Get DAC trigger state of the selected channel.
<>	134:ad3be0349dc5	1062	* (0: DAC trigger is disabled, 1: DAC trigger is enabled)
<>	134:ad3be0349dc5	1063	* @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
<>	134:ad3be0349dc5	1064	* CR TEN2 LL_DAC_IsTriggerEnabled
<>	134:ad3be0349dc5	1065	* @param DACx DAC instance
<>	134:ad3be0349dc5	1066	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1067	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	1068	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	1069	*
<>	134:ad3be0349dc5	1070	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	1071	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	1072	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1073	*/
<>	134:ad3be0349dc5	1074	__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	1075	{
<>	134:ad3be0349dc5	1076	return (READ_BIT(DACx->CR,
<>	134:ad3be0349dc5	1077	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	134:ad3be0349dc5	1078	== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<>	134:ad3be0349dc5	1079	}
<>	134:ad3be0349dc5	1080
<>	134:ad3be0349dc5	1081	/**
<>	134:ad3be0349dc5	1082	* @brief Trig DAC conversion by software for the selected DAC channel.
<>	134:ad3be0349dc5	1083	* @note Preliminarily, DAC trigger must be set to software trigger
<>	134:ad3be0349dc5	1084	* using function @ref LL_DAC_SetTriggerSource()
<>	134:ad3be0349dc5	1085	* with parameter "LL_DAC_TRIGGER_SOFTWARE".
<>	134:ad3be0349dc5	1086	* and DAC trigger must be enabled using
<>	134:ad3be0349dc5	1087	* function @ref LL_DAC_EnableTrigger().
<>	134:ad3be0349dc5	1088	* @note For devices featuring DAC with 2 channels: this function
<>	134:ad3be0349dc5	1089	* can perform a SW start of both DAC channels simultaneously.
<>	134:ad3be0349dc5	1090	* Two channels can be selected as parameter.
<>	134:ad3be0349dc5	1091	* Example: (LL_DAC_CHANNEL_1 \| LL_DAC_CHANNEL_2)
<>	134:ad3be0349dc5	1092	* @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
<>	134:ad3be0349dc5	1093	* SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
<>	134:ad3be0349dc5	1094	* @param DACx DAC instance
<>	134:ad3be0349dc5	1095	* @param DAC_Channel This parameter can a combination of the following values:
<>	134:ad3be0349dc5	1096	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	1097	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	1098	*
<>	134:ad3be0349dc5	1099	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	1100	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	1101	* @retval None
<>	134:ad3be0349dc5	1102	*/
<>	134:ad3be0349dc5	1103	__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	1104	{
<>	134:ad3be0349dc5	1105	SET_BIT(DACx->SWTRIGR,
<>	134:ad3be0349dc5	1106	(DAC_Channel & DAC_SWTR_CHX_MASK));
<>	134:ad3be0349dc5	1107	}
<>	134:ad3be0349dc5	1108
<>	134:ad3be0349dc5	1109	/**
<>	134:ad3be0349dc5	1110	* @brief Set the data to be loaded in the data holding register
<>	134:ad3be0349dc5	1111	* in format 12 bits left alignment (LSB aligned on bit 0),
<>	134:ad3be0349dc5	1112	* for the selected DAC channel.
<>	134:ad3be0349dc5	1113	* @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
<>	134:ad3be0349dc5	1114	* DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
<>	134:ad3be0349dc5	1115	* @param DACx DAC instance
<>	134:ad3be0349dc5	1116	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1117	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	1118	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	1119	*
<>	134:ad3be0349dc5	1120	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	1121	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	1122	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
<>	134:ad3be0349dc5	1123	* @retval None
<>	134:ad3be0349dc5	1124	*/
<>	134:ad3be0349dc5	1125	__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<>	134:ad3be0349dc5	1126	{
<>	134:ad3be0349dc5	1127	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
<>	134:ad3be0349dc5	1128
<>	134:ad3be0349dc5	1129	MODIFY_REG(*preg,
<>	134:ad3be0349dc5	1130	DAC_DHR12R1_DACC1DHR,
<>	134:ad3be0349dc5	1131	Data);
<>	134:ad3be0349dc5	1132	}
<>	134:ad3be0349dc5	1133
<>	134:ad3be0349dc5	1134	/**
<>	134:ad3be0349dc5	1135	* @brief Set the data to be loaded in the data holding register
<>	134:ad3be0349dc5	1136	* in format 12 bits left alignment (MSB aligned on bit 15),
<>	134:ad3be0349dc5	1137	* for the selected DAC channel.
<>	134:ad3be0349dc5	1138	* @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
<>	134:ad3be0349dc5	1139	* DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
<>	134:ad3be0349dc5	1140	* @param DACx DAC instance
<>	134:ad3be0349dc5	1141	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1142	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	1143	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	1144	*
<>	134:ad3be0349dc5	1145	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	1146	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	1147	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
<>	134:ad3be0349dc5	1148	* @retval None
<>	134:ad3be0349dc5	1149	*/
<>	134:ad3be0349dc5	1150	__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<>	134:ad3be0349dc5	1151	{
<>	134:ad3be0349dc5	1152	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
<>	134:ad3be0349dc5	1153
<>	134:ad3be0349dc5	1154	MODIFY_REG(*preg,
<>	134:ad3be0349dc5	1155	DAC_DHR12L1_DACC1DHR,
<>	134:ad3be0349dc5	1156	Data);
<>	134:ad3be0349dc5	1157	}
<>	134:ad3be0349dc5	1158
<>	134:ad3be0349dc5	1159	/**
<>	134:ad3be0349dc5	1160	* @brief Set the data to be loaded in the data holding register
<>	134:ad3be0349dc5	1161	* in format 8 bits left alignment (LSB aligned on bit 0),
<>	134:ad3be0349dc5	1162	* for the selected DAC channel.
<>	134:ad3be0349dc5	1163	* @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
<>	134:ad3be0349dc5	1164	* DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
<>	134:ad3be0349dc5	1165	* @param DACx DAC instance
<>	134:ad3be0349dc5	1166	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1167	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	1168	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	1169	*
<>	134:ad3be0349dc5	1170	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	1171	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	1172	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
<>	134:ad3be0349dc5	1173	* @retval None
<>	134:ad3be0349dc5	1174	*/
<>	134:ad3be0349dc5	1175	__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<>	134:ad3be0349dc5	1176	{
<>	134:ad3be0349dc5	1177	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
<>	134:ad3be0349dc5	1178
<>	134:ad3be0349dc5	1179	MODIFY_REG(*preg,
<>	134:ad3be0349dc5	1180	DAC_DHR8R1_DACC1DHR,
<>	134:ad3be0349dc5	1181	Data);
<>	134:ad3be0349dc5	1182	}
<>	134:ad3be0349dc5	1183
<>	134:ad3be0349dc5	1184	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	1185	/**
<>	134:ad3be0349dc5	1186	* @brief Set the data to be loaded in the data holding register
<>	134:ad3be0349dc5	1187	* in format 12 bits left alignment (LSB aligned on bit 0),
<>	134:ad3be0349dc5	1188	* for both DAC channels.
<>	134:ad3be0349dc5	1189	* @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
<>	134:ad3be0349dc5	1190	* DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
<>	134:ad3be0349dc5	1191	* @param DACx DAC instance
<>	134:ad3be0349dc5	1192	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
<>	134:ad3be0349dc5	1193	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
<>	134:ad3be0349dc5	1194	* @retval None
<>	134:ad3be0349dc5	1195	*/
<>	134:ad3be0349dc5	1196	__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<>	134:ad3be0349dc5	1197	{
<>	134:ad3be0349dc5	1198	MODIFY_REG(DACx->DHR12RD,
<>	134:ad3be0349dc5	1199	(DAC_DHR12RD_DACC2DHR \| DAC_DHR12RD_DACC1DHR),
<>	134:ad3be0349dc5	1200	((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
<>	134:ad3be0349dc5	1201	}
<>	134:ad3be0349dc5	1202
<>	134:ad3be0349dc5	1203	/**
<>	134:ad3be0349dc5	1204	* @brief Set the data to be loaded in the data holding register
<>	134:ad3be0349dc5	1205	* in format 12 bits left alignment (MSB aligned on bit 15),
<>	134:ad3be0349dc5	1206	* for both DAC channels.
<>	134:ad3be0349dc5	1207	* @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
<>	134:ad3be0349dc5	1208	* DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
<>	134:ad3be0349dc5	1209	* @param DACx DAC instance
<>	134:ad3be0349dc5	1210	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
<>	134:ad3be0349dc5	1211	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
<>	134:ad3be0349dc5	1212	* @retval None
<>	134:ad3be0349dc5	1213	*/
<>	134:ad3be0349dc5	1214	__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<>	134:ad3be0349dc5	1215	{
<>	134:ad3be0349dc5	1216	/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
<>	134:ad3be0349dc5	1217	/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
<>	134:ad3be0349dc5	1218	/* the 4 LSB must be taken into account for the shift value. */
<>	134:ad3be0349dc5	1219	MODIFY_REG(DACx->DHR12LD,
<>	134:ad3be0349dc5	1220	(DAC_DHR12LD_DACC2DHR \| DAC_DHR12LD_DACC1DHR),
<>	134:ad3be0349dc5	1221	((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) \| DataChannel1));
<>	134:ad3be0349dc5	1222	}
<>	134:ad3be0349dc5	1223
<>	134:ad3be0349dc5	1224	/**
<>	134:ad3be0349dc5	1225	* @brief Set the data to be loaded in the data holding register
<>	134:ad3be0349dc5	1226	* in format 8 bits left alignment (LSB aligned on bit 0),
<>	134:ad3be0349dc5	1227	* for both DAC channels.
<>	134:ad3be0349dc5	1228	* @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
<>	134:ad3be0349dc5	1229	* DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
<>	134:ad3be0349dc5	1230	* @param DACx DAC instance
<>	134:ad3be0349dc5	1231	* @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
<>	134:ad3be0349dc5	1232	* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
<>	134:ad3be0349dc5	1233	* @retval None
<>	134:ad3be0349dc5	1234	*/
<>	134:ad3be0349dc5	1235	__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<>	134:ad3be0349dc5	1236	{
<>	134:ad3be0349dc5	1237	MODIFY_REG(DACx->DHR8RD,
<>	134:ad3be0349dc5	1238	(DAC_DHR8RD_DACC2DHR \| DAC_DHR8RD_DACC1DHR),
<>	134:ad3be0349dc5	1239	((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
<>	134:ad3be0349dc5	1240	}
<>	134:ad3be0349dc5	1241
<>	134:ad3be0349dc5	1242	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	1243	/**
<>	134:ad3be0349dc5	1244	* @brief Retrieve output data currently generated for the selected DAC channel.
<>	134:ad3be0349dc5	1245	* @note Whatever alignment and resolution settings
<>	134:ad3be0349dc5	1246	* (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
<>	134:ad3be0349dc5	1247	* @ref LL_DAC_ConvertData12RightAligned(), ...),
<>	134:ad3be0349dc5	1248	* output data format is 12 bits right aligned (LSB aligned on bit 0).
<>	134:ad3be0349dc5	1249	* @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
<>	134:ad3be0349dc5	1250	* DOR2 DACC2DOR LL_DAC_RetrieveOutputData
<>	134:ad3be0349dc5	1251	* @param DACx DAC instance
<>	134:ad3be0349dc5	1252	* @param DAC_Channel This parameter can be one of the following values:
<>	134:ad3be0349dc5	1253	* @arg @ref LL_DAC_CHANNEL_1
<>	134:ad3be0349dc5	1254	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	134:ad3be0349dc5	1255	*
<>	134:ad3be0349dc5	1256	* (1) On this STM32 serie, parameter not available on all devices.
<>	134:ad3be0349dc5	1257	* Refer to device datasheet for channels availability.
<>	134:ad3be0349dc5	1258	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	134:ad3be0349dc5	1259	*/
<>	134:ad3be0349dc5	1260	__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	134:ad3be0349dc5	1261	{
<>	134:ad3be0349dc5	1262	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
<>	134:ad3be0349dc5	1263
<>	134:ad3be0349dc5	1264	return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
<>	134:ad3be0349dc5	1265	}
<>	134:ad3be0349dc5	1266
<>	134:ad3be0349dc5	1267	/**
<>	134:ad3be0349dc5	1268	* @}
<>	134:ad3be0349dc5	1269	*/
<>	134:ad3be0349dc5	1270
<>	134:ad3be0349dc5	1271	/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
<>	134:ad3be0349dc5	1272	* @{
<>	134:ad3be0349dc5	1273	*/
<>	134:ad3be0349dc5	1274	/**
<>	134:ad3be0349dc5	1275	* @brief Get DAC underrun flag for DAC channel 1
<>	134:ad3be0349dc5	1276	* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
<>	134:ad3be0349dc5	1277	* @param DACx DAC instance
<>	134:ad3be0349dc5	1278	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1279	*/
<>	134:ad3be0349dc5	1280	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
<>	134:ad3be0349dc5	1281	{
<>	134:ad3be0349dc5	1282	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
<>	134:ad3be0349dc5	1283	}
<>	134:ad3be0349dc5	1284
<>	134:ad3be0349dc5	1285	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	1286	/**
<>	134:ad3be0349dc5	1287	* @brief Get DAC underrun flag for DAC channel 2
<>	134:ad3be0349dc5	1288	* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
<>	134:ad3be0349dc5	1289	* @param DACx DAC instance
<>	134:ad3be0349dc5	1290	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1291	*/
<>	134:ad3be0349dc5	1292	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
<>	134:ad3be0349dc5	1293	{
<>	134:ad3be0349dc5	1294	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
<>	134:ad3be0349dc5	1295	}
<>	134:ad3be0349dc5	1296	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	1297
<>	134:ad3be0349dc5	1298	/**
<>	134:ad3be0349dc5	1299	* @brief Clear DAC underrun flag for DAC channel 1
<>	134:ad3be0349dc5	1300	* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
<>	134:ad3be0349dc5	1301	* @param DACx DAC instance
<>	134:ad3be0349dc5	1302	* @retval None
<>	134:ad3be0349dc5	1303	*/
<>	134:ad3be0349dc5	1304	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
<>	134:ad3be0349dc5	1305	{
<>	134:ad3be0349dc5	1306	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
<>	134:ad3be0349dc5	1307	}
<>	134:ad3be0349dc5	1308
<>	134:ad3be0349dc5	1309	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	1310	/**
<>	134:ad3be0349dc5	1311	* @brief Clear DAC underrun flag for DAC channel 2
<>	134:ad3be0349dc5	1312	* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
<>	134:ad3be0349dc5	1313	* @param DACx DAC instance
<>	134:ad3be0349dc5	1314	* @retval None
<>	134:ad3be0349dc5	1315	*/
<>	134:ad3be0349dc5	1316	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
<>	134:ad3be0349dc5	1317	{
<>	134:ad3be0349dc5	1318	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
<>	134:ad3be0349dc5	1319	}
<>	134:ad3be0349dc5	1320	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	1321
<>	134:ad3be0349dc5	1322	/**
<>	134:ad3be0349dc5	1323	* @}
<>	134:ad3be0349dc5	1324	*/
<>	134:ad3be0349dc5	1325
<>	134:ad3be0349dc5	1326	/** @defgroup DAC_LL_EF_IT_Management IT management
<>	134:ad3be0349dc5	1327	* @{
<>	134:ad3be0349dc5	1328	*/
<>	134:ad3be0349dc5	1329
<>	134:ad3be0349dc5	1330	/**
<>	134:ad3be0349dc5	1331	* @brief Enable DMA underrun interrupt for DAC channel 1
<>	134:ad3be0349dc5	1332	* @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
<>	134:ad3be0349dc5	1333	* @param DACx DAC instance
<>	134:ad3be0349dc5	1334	* @retval None
<>	134:ad3be0349dc5	1335	*/
<>	134:ad3be0349dc5	1336	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
<>	134:ad3be0349dc5	1337	{
<>	134:ad3be0349dc5	1338	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
<>	134:ad3be0349dc5	1339	}
<>	134:ad3be0349dc5	1340
<>	134:ad3be0349dc5	1341	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	1342	/**
<>	134:ad3be0349dc5	1343	* @brief Enable DMA underrun interrupt for DAC channel 2
<>	134:ad3be0349dc5	1344	* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
<>	134:ad3be0349dc5	1345	* @param DACx DAC instance
<>	134:ad3be0349dc5	1346	* @retval None
<>	134:ad3be0349dc5	1347	*/
<>	134:ad3be0349dc5	1348	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
<>	134:ad3be0349dc5	1349	{
<>	134:ad3be0349dc5	1350	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
<>	134:ad3be0349dc5	1351	}
<>	134:ad3be0349dc5	1352	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	1353
<>	134:ad3be0349dc5	1354	/**
<>	134:ad3be0349dc5	1355	* @brief Disable DMA underrun interrupt for DAC channel 1
<>	134:ad3be0349dc5	1356	* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
<>	134:ad3be0349dc5	1357	* @param DACx DAC instance
<>	134:ad3be0349dc5	1358	* @retval None
<>	134:ad3be0349dc5	1359	*/
<>	134:ad3be0349dc5	1360	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
<>	134:ad3be0349dc5	1361	{
<>	134:ad3be0349dc5	1362	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
<>	134:ad3be0349dc5	1363	}
<>	134:ad3be0349dc5	1364
<>	134:ad3be0349dc5	1365	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	1366	/**
<>	134:ad3be0349dc5	1367	* @brief Disable DMA underrun interrupt for DAC channel 2
<>	134:ad3be0349dc5	1368	* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
<>	134:ad3be0349dc5	1369	* @param DACx DAC instance
<>	134:ad3be0349dc5	1370	* @retval None
<>	134:ad3be0349dc5	1371	*/
<>	134:ad3be0349dc5	1372	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
<>	134:ad3be0349dc5	1373	{
<>	134:ad3be0349dc5	1374	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
<>	134:ad3be0349dc5	1375	}
<>	134:ad3be0349dc5	1376	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	1377
<>	134:ad3be0349dc5	1378	/**
<>	134:ad3be0349dc5	1379	* @brief Get DMA underrun interrupt for DAC channel 1
<>	134:ad3be0349dc5	1380	* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
<>	134:ad3be0349dc5	1381	* @param DACx DAC instance
<>	134:ad3be0349dc5	1382	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1383	*/
<>	134:ad3be0349dc5	1384	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
<>	134:ad3be0349dc5	1385	{
<>	134:ad3be0349dc5	1386	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
<>	134:ad3be0349dc5	1387	}
<>	134:ad3be0349dc5	1388
<>	134:ad3be0349dc5	1389	#if defined(DAC_CHANNEL2_SUPPORT)
<>	134:ad3be0349dc5	1390	/**
<>	134:ad3be0349dc5	1391	* @brief Get DMA underrun interrupt for DAC channel 2
<>	134:ad3be0349dc5	1392	* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
<>	134:ad3be0349dc5	1393	* @param DACx DAC instance
<>	134:ad3be0349dc5	1394	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1395	*/
<>	134:ad3be0349dc5	1396	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
<>	134:ad3be0349dc5	1397	{
<>	134:ad3be0349dc5	1398	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
<>	134:ad3be0349dc5	1399	}
<>	134:ad3be0349dc5	1400	#endif /* DAC_CHANNEL2_SUPPORT */
<>	134:ad3be0349dc5	1401
<>	134:ad3be0349dc5	1402	/**
<>	134:ad3be0349dc5	1403	* @}
<>	134:ad3be0349dc5	1404	*/
<>	134:ad3be0349dc5	1405
<>	134:ad3be0349dc5	1406	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	1407	/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
<>	134:ad3be0349dc5	1408	* @{
<>	134:ad3be0349dc5	1409	*/
<>	134:ad3be0349dc5	1410
<>	134:ad3be0349dc5	1411	ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
<>	134:ad3be0349dc5	1412	ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
<>	134:ad3be0349dc5	1413	void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
<>	134:ad3be0349dc5	1414
<>	134:ad3be0349dc5	1415	/**
<>	134:ad3be0349dc5	1416	* @}
<>	134:ad3be0349dc5	1417	*/
<>	134:ad3be0349dc5	1418	#endif /* USE_FULL_LL_DRIVER */
<>	134:ad3be0349dc5	1419
<>	134:ad3be0349dc5	1420	/**
<>	134:ad3be0349dc5	1421	* @}
<>	134:ad3be0349dc5	1422	*/
<>	134:ad3be0349dc5	1423
<>	134:ad3be0349dc5	1424	/**
<>	134:ad3be0349dc5	1425	* @}
<>	134:ad3be0349dc5	1426	*/
<>	134:ad3be0349dc5	1427
<>	134:ad3be0349dc5	1428	#endif /* DAC1 */
<>	134:ad3be0349dc5	1429
<>	134:ad3be0349dc5	1430	/**
<>	134:ad3be0349dc5	1431	* @}
<>	134:ad3be0349dc5	1432	*/
<>	134:ad3be0349dc5	1433
<>	134:ad3be0349dc5	1434	#ifdef __cplusplus
<>	134:ad3be0349dc5	1435	}
<>	134:ad3be0349dc5	1436	#endif
<>	134:ad3be0349dc5	1437
<>	134:ad3be0349dc5	1438	#endif /* __STM32F0xx_LL_DAC_H */
<>	134:ad3be0349dc5	1439
<>	134:ad3be0349dc5	1440	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/