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TARGET_NUCLEO_F091RC/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_cortex.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
134:ad3be0349dc5
Child:
160:5571c4ff569f
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 134:ad3be0349dc5 1 /**
<> 134:ad3be0349dc5 2 ******************************************************************************
<> 134:ad3be0349dc5 3 * @file stm32f0xx_ll_cortex.h
<> 134:ad3be0349dc5 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.4.0
<> 134:ad3be0349dc5 6 * @date 27-May-2016
<> 134:ad3be0349dc5 7 * @brief Header file of CORTEX LL module.
<> 134:ad3be0349dc5 8 @verbatim
<> 134:ad3be0349dc5 9 ==============================================================================
<> 134:ad3be0349dc5 10 ##### How to use this driver #####
<> 134:ad3be0349dc5 11 ==============================================================================
<> 134:ad3be0349dc5 12 [..]
<> 134:ad3be0349dc5 13 The LL CORTEX driver contains a set of generic APIs that can be
<> 134:ad3be0349dc5 14 used by user:
<> 134:ad3be0349dc5 15 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
<> 134:ad3be0349dc5 16 functions
<> 134:ad3be0349dc5 17 (+) Low power mode configuration (SCB register of Cortex-MCU)
<> 134:ad3be0349dc5 18 (+) API to access to MCU info (CPUID register)
<> 134:ad3be0349dc5 19
<> 134:ad3be0349dc5 20 @endverbatim
<> 134:ad3be0349dc5 21 ******************************************************************************
<> 134:ad3be0349dc5 22 * @attention
<> 134:ad3be0349dc5 23 *
<> 134:ad3be0349dc5 24 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 134:ad3be0349dc5 25 *
<> 134:ad3be0349dc5 26 * Redistribution and use in source and binary forms, with or without modification,
<> 134:ad3be0349dc5 27 * are permitted provided that the following conditions are met:
<> 134:ad3be0349dc5 28 * 1. Redistributions of source code must retain the above copyright notice,
<> 134:ad3be0349dc5 29 * this list of conditions and the following disclaimer.
<> 134:ad3be0349dc5 30 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 134:ad3be0349dc5 31 * this list of conditions and the following disclaimer in the documentation
<> 134:ad3be0349dc5 32 * and/or other materials provided with the distribution.
<> 134:ad3be0349dc5 33 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 134:ad3be0349dc5 34 * may be used to endorse or promote products derived from this software
<> 134:ad3be0349dc5 35 * without specific prior written permission.
<> 134:ad3be0349dc5 36 *
<> 134:ad3be0349dc5 37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 134:ad3be0349dc5 38 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 134:ad3be0349dc5 39 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 134:ad3be0349dc5 40 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 134:ad3be0349dc5 41 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 134:ad3be0349dc5 42 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 134:ad3be0349dc5 43 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 134:ad3be0349dc5 44 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 134:ad3be0349dc5 45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 134:ad3be0349dc5 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 134:ad3be0349dc5 47 *
<> 134:ad3be0349dc5 48 ******************************************************************************
<> 134:ad3be0349dc5 49 */
<> 134:ad3be0349dc5 50
<> 134:ad3be0349dc5 51 /* Define to prevent recursive inclusion -------------------------------------*/
<> 134:ad3be0349dc5 52 #ifndef __STM32F0xx_LL_CORTEX_H
<> 134:ad3be0349dc5 53 #define __STM32F0xx_LL_CORTEX_H
<> 134:ad3be0349dc5 54
<> 134:ad3be0349dc5 55 #ifdef __cplusplus
<> 134:ad3be0349dc5 56 extern "C" {
<> 134:ad3be0349dc5 57 #endif
<> 134:ad3be0349dc5 58
<> 134:ad3be0349dc5 59 /* Includes ------------------------------------------------------------------*/
<> 134:ad3be0349dc5 60 #include "stm32f0xx.h"
<> 134:ad3be0349dc5 61
<> 134:ad3be0349dc5 62 /** @addtogroup STM32F0xx_LL_Driver
<> 134:ad3be0349dc5 63 * @{
<> 134:ad3be0349dc5 64 */
<> 134:ad3be0349dc5 65
<> 134:ad3be0349dc5 66 /** @defgroup CORTEX_LL CORTEX
<> 134:ad3be0349dc5 67 * @{
<> 134:ad3be0349dc5 68 */
<> 134:ad3be0349dc5 69
<> 134:ad3be0349dc5 70 /* Private types -------------------------------------------------------------*/
<> 134:ad3be0349dc5 71 /* Private variables ---------------------------------------------------------*/
<> 134:ad3be0349dc5 72
<> 134:ad3be0349dc5 73 /* Private constants ---------------------------------------------------------*/
<> 134:ad3be0349dc5 74
<> 134:ad3be0349dc5 75 /* Private macros ------------------------------------------------------------*/
<> 134:ad3be0349dc5 76
<> 134:ad3be0349dc5 77 /* Exported types ------------------------------------------------------------*/
<> 134:ad3be0349dc5 78 /* Exported constants --------------------------------------------------------*/
<> 134:ad3be0349dc5 79 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
<> 134:ad3be0349dc5 80 * @{
<> 134:ad3be0349dc5 81 */
<> 134:ad3be0349dc5 82
<> 134:ad3be0349dc5 83 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
<> 134:ad3be0349dc5 84 * @{
<> 134:ad3be0349dc5 85 */
<> 134:ad3be0349dc5 86 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/
<> 134:ad3be0349dc5 87 #define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
<> 134:ad3be0349dc5 88 /**
<> 134:ad3be0349dc5 89 * @}
<> 134:ad3be0349dc5 90 */
<> 134:ad3be0349dc5 91
<> 134:ad3be0349dc5 92 /**
<> 134:ad3be0349dc5 93 * @}
<> 134:ad3be0349dc5 94 */
<> 134:ad3be0349dc5 95
<> 134:ad3be0349dc5 96 /* Exported macro ------------------------------------------------------------*/
<> 134:ad3be0349dc5 97
<> 134:ad3be0349dc5 98 /* Exported functions --------------------------------------------------------*/
<> 134:ad3be0349dc5 99 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
<> 134:ad3be0349dc5 100 * @{
<> 134:ad3be0349dc5 101 */
<> 134:ad3be0349dc5 102
<> 134:ad3be0349dc5 103 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
<> 134:ad3be0349dc5 104 * @{
<> 134:ad3be0349dc5 105 */
<> 134:ad3be0349dc5 106
<> 134:ad3be0349dc5 107 /**
<> 134:ad3be0349dc5 108 * @brief This function checks if the Systick counter flag is active or not.
<> 134:ad3be0349dc5 109 * @note It can be used in timeout function on application side.
<> 134:ad3be0349dc5 110 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
<> 134:ad3be0349dc5 111 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 112 */
<> 134:ad3be0349dc5 113 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
<> 134:ad3be0349dc5 114 {
<> 134:ad3be0349dc5 115 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
<> 134:ad3be0349dc5 116 }
<> 134:ad3be0349dc5 117
<> 134:ad3be0349dc5 118 /**
<> 134:ad3be0349dc5 119 * @brief Configures the SysTick clock source
<> 134:ad3be0349dc5 120 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
<> 134:ad3be0349dc5 121 * @param Source This parameter can be one of the following values:
<> 134:ad3be0349dc5 122 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
<> 134:ad3be0349dc5 123 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
<> 134:ad3be0349dc5 124 * @retval None
<> 134:ad3be0349dc5 125 */
<> 134:ad3be0349dc5 126 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
<> 134:ad3be0349dc5 127 {
<> 134:ad3be0349dc5 128 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
<> 134:ad3be0349dc5 129 {
<> 134:ad3be0349dc5 130 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 134:ad3be0349dc5 131 }
<> 134:ad3be0349dc5 132 else
<> 134:ad3be0349dc5 133 {
<> 134:ad3be0349dc5 134 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 134:ad3be0349dc5 135 }
<> 134:ad3be0349dc5 136 }
<> 134:ad3be0349dc5 137
<> 134:ad3be0349dc5 138 /**
<> 134:ad3be0349dc5 139 * @brief Get the SysTick clock source
<> 134:ad3be0349dc5 140 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
<> 134:ad3be0349dc5 141 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 142 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
<> 134:ad3be0349dc5 143 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
<> 134:ad3be0349dc5 144 */
<> 134:ad3be0349dc5 145 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
<> 134:ad3be0349dc5 146 {
<> 134:ad3be0349dc5 147 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 134:ad3be0349dc5 148 }
<> 134:ad3be0349dc5 149
<> 134:ad3be0349dc5 150 /**
<> 134:ad3be0349dc5 151 * @brief Enable SysTick exception request
<> 134:ad3be0349dc5 152 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
<> 134:ad3be0349dc5 153 * @retval None
<> 134:ad3be0349dc5 154 */
<> 134:ad3be0349dc5 155 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
<> 134:ad3be0349dc5 156 {
<> 134:ad3be0349dc5 157 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
<> 134:ad3be0349dc5 158 }
<> 134:ad3be0349dc5 159
<> 134:ad3be0349dc5 160 /**
<> 134:ad3be0349dc5 161 * @brief Disable SysTick exception request
<> 134:ad3be0349dc5 162 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
<> 134:ad3be0349dc5 163 * @retval None
<> 134:ad3be0349dc5 164 */
<> 134:ad3be0349dc5 165 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
<> 134:ad3be0349dc5 166 {
<> 134:ad3be0349dc5 167 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
<> 134:ad3be0349dc5 168 }
<> 134:ad3be0349dc5 169
<> 134:ad3be0349dc5 170 /**
<> 134:ad3be0349dc5 171 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
<> 134:ad3be0349dc5 172 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
<> 134:ad3be0349dc5 173 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 174 */
<> 134:ad3be0349dc5 175 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
<> 134:ad3be0349dc5 176 {
<> 134:ad3be0349dc5 177 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
<> 134:ad3be0349dc5 178 }
<> 134:ad3be0349dc5 179
<> 134:ad3be0349dc5 180 /**
<> 134:ad3be0349dc5 181 * @}
<> 134:ad3be0349dc5 182 */
<> 134:ad3be0349dc5 183
<> 134:ad3be0349dc5 184 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
<> 134:ad3be0349dc5 185 * @{
<> 134:ad3be0349dc5 186 */
<> 134:ad3be0349dc5 187
<> 134:ad3be0349dc5 188 /**
<> 134:ad3be0349dc5 189 * @brief Processor uses sleep as its low power mode
<> 134:ad3be0349dc5 190 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
<> 134:ad3be0349dc5 191 * @retval None
<> 134:ad3be0349dc5 192 */
<> 134:ad3be0349dc5 193 __STATIC_INLINE void LL_LPM_EnableSleep(void)
<> 134:ad3be0349dc5 194 {
<> 134:ad3be0349dc5 195 /* Clear SLEEPDEEP bit of Cortex System Control Register */
<> 134:ad3be0349dc5 196 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 134:ad3be0349dc5 197 }
<> 134:ad3be0349dc5 198
<> 134:ad3be0349dc5 199 /**
<> 134:ad3be0349dc5 200 * @brief Processor uses deep sleep as its low power mode
<> 134:ad3be0349dc5 201 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
<> 134:ad3be0349dc5 202 * @retval None
<> 134:ad3be0349dc5 203 */
<> 134:ad3be0349dc5 204 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
<> 134:ad3be0349dc5 205 {
<> 134:ad3be0349dc5 206 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 134:ad3be0349dc5 207 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 134:ad3be0349dc5 208 }
<> 134:ad3be0349dc5 209
<> 134:ad3be0349dc5 210 /**
<> 134:ad3be0349dc5 211 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
<> 134:ad3be0349dc5 212 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
<> 134:ad3be0349dc5 213 * empty main application.
<> 134:ad3be0349dc5 214 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
<> 134:ad3be0349dc5 215 * @retval None
<> 134:ad3be0349dc5 216 */
<> 134:ad3be0349dc5 217 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
<> 134:ad3be0349dc5 218 {
<> 134:ad3be0349dc5 219 /* Set SLEEPONEXIT bit of Cortex System Control Register */
<> 134:ad3be0349dc5 220 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 134:ad3be0349dc5 221 }
<> 134:ad3be0349dc5 222
<> 134:ad3be0349dc5 223 /**
<> 134:ad3be0349dc5 224 * @brief Do not sleep when returning to Thread mode.
<> 134:ad3be0349dc5 225 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
<> 134:ad3be0349dc5 226 * @retval None
<> 134:ad3be0349dc5 227 */
<> 134:ad3be0349dc5 228 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
<> 134:ad3be0349dc5 229 {
<> 134:ad3be0349dc5 230 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
<> 134:ad3be0349dc5 231 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 134:ad3be0349dc5 232 }
<> 134:ad3be0349dc5 233
<> 134:ad3be0349dc5 234 /**
<> 134:ad3be0349dc5 235 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
<> 134:ad3be0349dc5 236 * processor.
<> 134:ad3be0349dc5 237 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
<> 134:ad3be0349dc5 238 * @retval None
<> 134:ad3be0349dc5 239 */
<> 134:ad3be0349dc5 240 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
<> 134:ad3be0349dc5 241 {
<> 134:ad3be0349dc5 242 /* Set SEVEONPEND bit of Cortex System Control Register */
<> 134:ad3be0349dc5 243 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 134:ad3be0349dc5 244 }
<> 134:ad3be0349dc5 245
<> 134:ad3be0349dc5 246 /**
<> 134:ad3be0349dc5 247 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
<> 134:ad3be0349dc5 248 * excluded
<> 134:ad3be0349dc5 249 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
<> 134:ad3be0349dc5 250 * @retval None
<> 134:ad3be0349dc5 251 */
<> 134:ad3be0349dc5 252 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
<> 134:ad3be0349dc5 253 {
<> 134:ad3be0349dc5 254 /* Clear SEVEONPEND bit of Cortex System Control Register */
<> 134:ad3be0349dc5 255 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 134:ad3be0349dc5 256 }
<> 134:ad3be0349dc5 257
<> 134:ad3be0349dc5 258 /**
<> 134:ad3be0349dc5 259 * @}
<> 134:ad3be0349dc5 260 */
<> 134:ad3be0349dc5 261
<> 134:ad3be0349dc5 262 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
<> 134:ad3be0349dc5 263 * @{
<> 134:ad3be0349dc5 264 */
<> 134:ad3be0349dc5 265
<> 134:ad3be0349dc5 266 /**
<> 134:ad3be0349dc5 267 * @brief Get Implementer code
<> 134:ad3be0349dc5 268 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
<> 134:ad3be0349dc5 269 * @retval Value should be equal to 0x41 for ARM
<> 134:ad3be0349dc5 270 */
<> 134:ad3be0349dc5 271 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
<> 134:ad3be0349dc5 272 {
<> 134:ad3be0349dc5 273 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
<> 134:ad3be0349dc5 274 }
<> 134:ad3be0349dc5 275
<> 134:ad3be0349dc5 276 /**
<> 134:ad3be0349dc5 277 * @brief Get Variant number (The r value in the rnpn product revision identifier)
<> 134:ad3be0349dc5 278 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
<> 134:ad3be0349dc5 279 * @retval Value between 0 and 255 (0x0: revision 0)
<> 134:ad3be0349dc5 280 */
<> 134:ad3be0349dc5 281 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
<> 134:ad3be0349dc5 282 {
<> 134:ad3be0349dc5 283 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
<> 134:ad3be0349dc5 284 }
<> 134:ad3be0349dc5 285
<> 134:ad3be0349dc5 286 /**
<> 134:ad3be0349dc5 287 * @brief Get Architecture number
<> 134:ad3be0349dc5 288 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
<> 134:ad3be0349dc5 289 * @retval Value should be equal to 0xC for Cortex-M0 devices
<> 134:ad3be0349dc5 290 */
<> 134:ad3be0349dc5 291 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
<> 134:ad3be0349dc5 292 {
<> 134:ad3be0349dc5 293 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
<> 134:ad3be0349dc5 294 }
<> 134:ad3be0349dc5 295
<> 134:ad3be0349dc5 296 /**
<> 134:ad3be0349dc5 297 * @brief Get Part number
<> 134:ad3be0349dc5 298 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
<> 134:ad3be0349dc5 299 * @retval Value should be equal to 0xC20 for Cortex-M0
<> 134:ad3be0349dc5 300 */
<> 134:ad3be0349dc5 301 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
<> 134:ad3be0349dc5 302 {
<> 134:ad3be0349dc5 303 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
<> 134:ad3be0349dc5 304 }
<> 134:ad3be0349dc5 305
<> 134:ad3be0349dc5 306 /**
<> 134:ad3be0349dc5 307 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
<> 134:ad3be0349dc5 308 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
<> 134:ad3be0349dc5 309 * @retval Value between 0 and 255 (0x1: patch 1)
<> 134:ad3be0349dc5 310 */
<> 134:ad3be0349dc5 311 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
<> 134:ad3be0349dc5 312 {
<> 134:ad3be0349dc5 313 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
<> 134:ad3be0349dc5 314 }
<> 134:ad3be0349dc5 315
<> 134:ad3be0349dc5 316 /**
<> 134:ad3be0349dc5 317 * @}
<> 134:ad3be0349dc5 318 */
<> 134:ad3be0349dc5 319
<> 134:ad3be0349dc5 320 /**
<> 134:ad3be0349dc5 321 * @}
<> 134:ad3be0349dc5 322 */
<> 134:ad3be0349dc5 323
<> 134:ad3be0349dc5 324 /**
<> 134:ad3be0349dc5 325 * @}
<> 134:ad3be0349dc5 326 */
<> 134:ad3be0349dc5 327
<> 134:ad3be0349dc5 328 /**
<> 134:ad3be0349dc5 329 * @}
<> 134:ad3be0349dc5 330 */
<> 134:ad3be0349dc5 331
<> 134:ad3be0349dc5 332 #ifdef __cplusplus
<> 134:ad3be0349dc5 333 }
<> 134:ad3be0349dc5 334 #endif
<> 134:ad3be0349dc5 335
<> 134:ad3be0349dc5 336 #endif /* __STM32F0xx_LL_CORTEX_H */
<> 134:ad3be0349dc5 337
<> 134:ad3be0349dc5 338 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/