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TARGET_NUCLEO_F091RC/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
156:ff21514d8981
Child:
160:5571c4ff569f
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32f0xx_hal.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @version V1.5.0
AnnaBridge 156:ff21514d8981 6 * @date 04-November-2016
AnnaBridge 156:ff21514d8981 7 * @brief This file contains all the functions prototypes for the HAL
AnnaBridge 156:ff21514d8981 8 * module driver.
AnnaBridge 156:ff21514d8981 9 ******************************************************************************
AnnaBridge 156:ff21514d8981 10 * @attention
AnnaBridge 156:ff21514d8981 11 *
AnnaBridge 156:ff21514d8981 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 13 *
AnnaBridge 156:ff21514d8981 14 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 15 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 16 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 17 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 20 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 22 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 23 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 24 *
AnnaBridge 156:ff21514d8981 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 35 *
AnnaBridge 156:ff21514d8981 36 ******************************************************************************
AnnaBridge 156:ff21514d8981 37 */
AnnaBridge 156:ff21514d8981 38
AnnaBridge 156:ff21514d8981 39 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 40 #ifndef __STM32F0xx_HAL_H
AnnaBridge 156:ff21514d8981 41 #define __STM32F0xx_HAL_H
AnnaBridge 156:ff21514d8981 42
AnnaBridge 156:ff21514d8981 43 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 44 extern "C" {
AnnaBridge 156:ff21514d8981 45 #endif
AnnaBridge 156:ff21514d8981 46
AnnaBridge 156:ff21514d8981 47 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 48 #include "stm32f0xx_hal_conf.h"
AnnaBridge 156:ff21514d8981 49
AnnaBridge 156:ff21514d8981 50 /** @addtogroup STM32F0xx_HAL_Driver
AnnaBridge 156:ff21514d8981 51 * @{
AnnaBridge 156:ff21514d8981 52 */
AnnaBridge 156:ff21514d8981 53
AnnaBridge 156:ff21514d8981 54 /** @addtogroup HAL
AnnaBridge 156:ff21514d8981 55 * @{
AnnaBridge 156:ff21514d8981 56 */
AnnaBridge 156:ff21514d8981 57
AnnaBridge 156:ff21514d8981 58 /* Private macros ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 59 /** @addtogroup HAL_Private_Macros
AnnaBridge 156:ff21514d8981 60 * @{
AnnaBridge 156:ff21514d8981 61 */
AnnaBridge 156:ff21514d8981 62 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
AnnaBridge 156:ff21514d8981 63 defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
AnnaBridge 156:ff21514d8981 64 defined(STM32F070xB) || defined(STM32F030x6)
AnnaBridge 156:ff21514d8981 65 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
AnnaBridge 156:ff21514d8981 66 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
AnnaBridge 156:ff21514d8981 67 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
AnnaBridge 156:ff21514d8981 68 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
AnnaBridge 156:ff21514d8981 69 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
AnnaBridge 156:ff21514d8981 70 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
AnnaBridge 156:ff21514d8981 71 #else
AnnaBridge 156:ff21514d8981 72 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
AnnaBridge 156:ff21514d8981 73 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
AnnaBridge 156:ff21514d8981 74 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
AnnaBridge 156:ff21514d8981 75 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
AnnaBridge 156:ff21514d8981 76 #endif
AnnaBridge 156:ff21514d8981 77 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
AnnaBridge 156:ff21514d8981 78 #define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
AnnaBridge 156:ff21514d8981 79 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
AnnaBridge 156:ff21514d8981 80 #if defined(STM32F091xC) || defined(STM32F098xx)
AnnaBridge 156:ff21514d8981 81 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
AnnaBridge 156:ff21514d8981 82 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
AnnaBridge 156:ff21514d8981 83 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
AnnaBridge 156:ff21514d8981 84 #endif /* STM32F091xC || STM32F098xx */
AnnaBridge 156:ff21514d8981 85 /**
AnnaBridge 156:ff21514d8981 86 * @}
AnnaBridge 156:ff21514d8981 87 */
AnnaBridge 156:ff21514d8981 88
AnnaBridge 156:ff21514d8981 89 /* Exported types ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 90 /* Exported constants --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 91 /** @defgroup HAL_Exported_Constants HAL Exported Constants
AnnaBridge 156:ff21514d8981 92 * @{
AnnaBridge 156:ff21514d8981 93 */
AnnaBridge 156:ff21514d8981 94
AnnaBridge 156:ff21514d8981 95 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
AnnaBridge 156:ff21514d8981 96 /** @defgroup HAL_Pin_remapping HAL Pin remapping
AnnaBridge 156:ff21514d8981 97 * @{
AnnaBridge 156:ff21514d8981 98 */
AnnaBridge 156:ff21514d8981 99 #define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins).
AnnaBridge 156:ff21514d8981 100 0: No remap (pin pair PA9/10 mapped on the pins)
AnnaBridge 156:ff21514d8981 101 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */
AnnaBridge 156:ff21514d8981 102
AnnaBridge 156:ff21514d8981 103 /**
AnnaBridge 156:ff21514d8981 104 * @}
AnnaBridge 156:ff21514d8981 105 */
AnnaBridge 156:ff21514d8981 106 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
AnnaBridge 156:ff21514d8981 107
AnnaBridge 156:ff21514d8981 108 #if defined(STM32F091xC) || defined(STM32F098xx)
AnnaBridge 156:ff21514d8981 109 /** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection
AnnaBridge 156:ff21514d8981 110 * @note Applicable on STM32F09x
AnnaBridge 156:ff21514d8981 111 * @{
AnnaBridge 156:ff21514d8981 112 */
AnnaBridge 156:ff21514d8981 113 #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */
AnnaBridge 156:ff21514d8981 114 #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */
AnnaBridge 156:ff21514d8981 115 #define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */
AnnaBridge 156:ff21514d8981 116
AnnaBridge 156:ff21514d8981 117 /**
AnnaBridge 156:ff21514d8981 118 * @}
AnnaBridge 156:ff21514d8981 119 */
AnnaBridge 156:ff21514d8981 120 #endif /* STM32F091xC || STM32F098xx */
AnnaBridge 156:ff21514d8981 121
AnnaBridge 156:ff21514d8981 122
AnnaBridge 156:ff21514d8981 123 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
AnnaBridge 156:ff21514d8981 124 * @{
AnnaBridge 156:ff21514d8981 125 */
AnnaBridge 156:ff21514d8981 126
AnnaBridge 156:ff21514d8981 127 /** @brief Fast-mode Plus driving capability on a specific GPIO
AnnaBridge 156:ff21514d8981 128 */
AnnaBridge 156:ff21514d8981 129 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
AnnaBridge 156:ff21514d8981 130 defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
AnnaBridge 156:ff21514d8981 131 defined(STM32F070xB) || defined(STM32F030x6)
AnnaBridge 156:ff21514d8981 132 #define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */
AnnaBridge 156:ff21514d8981 133 #define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */
AnnaBridge 156:ff21514d8981 134 #endif
AnnaBridge 156:ff21514d8981 135 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */
AnnaBridge 156:ff21514d8981 136 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */
AnnaBridge 156:ff21514d8981 137 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */
AnnaBridge 156:ff21514d8981 138 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */
AnnaBridge 156:ff21514d8981 139
AnnaBridge 156:ff21514d8981 140 /**
AnnaBridge 156:ff21514d8981 141 * @}
AnnaBridge 156:ff21514d8981 142 */
AnnaBridge 156:ff21514d8981 143
AnnaBridge 156:ff21514d8981 144
AnnaBridge 156:ff21514d8981 145 #if defined(STM32F091xC) || defined (STM32F098xx)
AnnaBridge 156:ff21514d8981 146 /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
AnnaBridge 156:ff21514d8981 147 * @brief ISR Wrapper
AnnaBridge 156:ff21514d8981 148 * @note applicable on STM32F09x
AnnaBridge 156:ff21514d8981 149 * @{
AnnaBridge 156:ff21514d8981 150 */
AnnaBridge 156:ff21514d8981 151 #define HAL_SYSCFG_ITLINE0 ( 0x00000000U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 152 #define HAL_SYSCFG_ITLINE1 ( 0x00000001U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 153 #define HAL_SYSCFG_ITLINE2 ( 0x00000002U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 154 #define HAL_SYSCFG_ITLINE3 ( 0x00000003U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 155 #define HAL_SYSCFG_ITLINE4 ( 0x00000004U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 156 #define HAL_SYSCFG_ITLINE5 ( 0x00000005U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 157 #define HAL_SYSCFG_ITLINE6 ( 0x00000006U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 158 #define HAL_SYSCFG_ITLINE7 ( 0x00000007U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 159 #define HAL_SYSCFG_ITLINE8 ( 0x00000008U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 160 #define HAL_SYSCFG_ITLINE9 ( 0x00000009U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 161 #define HAL_SYSCFG_ITLINE10 ( 0x0000000AU) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 162 #define HAL_SYSCFG_ITLINE11 ( 0x0000000BU) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 163 #define HAL_SYSCFG_ITLINE12 ( 0x0000000CU) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 164 #define HAL_SYSCFG_ITLINE13 ( 0x0000000DU) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 165 #define HAL_SYSCFG_ITLINE14 ( 0x0000000EU) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 166 #define HAL_SYSCFG_ITLINE15 ( 0x0000000FU) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 167 #define HAL_SYSCFG_ITLINE16 ( 0x00000010U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 168 #define HAL_SYSCFG_ITLINE17 ( 0x00000011U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 169 #define HAL_SYSCFG_ITLINE18 ( 0x00000012U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 170 #define HAL_SYSCFG_ITLINE19 ( 0x00000013U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 171 #define HAL_SYSCFG_ITLINE20 ( 0x00000014U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 172 #define HAL_SYSCFG_ITLINE21 ( 0x00000015U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 173 #define HAL_SYSCFG_ITLINE22 ( 0x00000016U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 174 #define HAL_SYSCFG_ITLINE23 ( 0x00000017U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 175 #define HAL_SYSCFG_ITLINE24 ( 0x00000018U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 176 #define HAL_SYSCFG_ITLINE25 ( 0x00000019U) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 177 #define HAL_SYSCFG_ITLINE26 ( 0x0000001AU) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 178 #define HAL_SYSCFG_ITLINE27 ( 0x0000001BU) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 179 #define HAL_SYSCFG_ITLINE28 ( 0x0000001CU) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 180 #define HAL_SYSCFG_ITLINE29 ( 0x0000001DU) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 181 #define HAL_SYSCFG_ITLINE30 ( 0x0000001EU) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 182 #define HAL_SYSCFG_ITLINE31 ( 0x0000001FU) /*!< Internal define for macro handling */
AnnaBridge 156:ff21514d8981 183
AnnaBridge 156:ff21514d8981 184 #define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */
AnnaBridge 156:ff21514d8981 185 #if defined(STM32F091xC)
AnnaBridge 156:ff21514d8981 186 #define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */
AnnaBridge 156:ff21514d8981 187 #endif
AnnaBridge 156:ff21514d8981 188 #define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */
AnnaBridge 156:ff21514d8981 189 #define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */
AnnaBridge 156:ff21514d8981 190 #define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */
AnnaBridge 156:ff21514d8981 191 #define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */
AnnaBridge 156:ff21514d8981 192 #define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */
AnnaBridge 156:ff21514d8981 193 #define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */
AnnaBridge 156:ff21514d8981 194 #define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */
AnnaBridge 156:ff21514d8981 195 #define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */
AnnaBridge 156:ff21514d8981 196 #define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */
AnnaBridge 156:ff21514d8981 197 #define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */
AnnaBridge 156:ff21514d8981 198 #define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */
AnnaBridge 156:ff21514d8981 199 #define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */
AnnaBridge 156:ff21514d8981 200 #define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */
AnnaBridge 156:ff21514d8981 201 #define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */
AnnaBridge 156:ff21514d8981 202 #define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */
AnnaBridge 156:ff21514d8981 203 #define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */
AnnaBridge 156:ff21514d8981 204 #define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */
AnnaBridge 156:ff21514d8981 205 #define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */
AnnaBridge 156:ff21514d8981 206 #define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */
AnnaBridge 156:ff21514d8981 207 #define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */
AnnaBridge 156:ff21514d8981 208 #define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */
AnnaBridge 156:ff21514d8981 209 #define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */
AnnaBridge 156:ff21514d8981 210 #define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */
AnnaBridge 156:ff21514d8981 211 #define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */
AnnaBridge 156:ff21514d8981 212 #define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */
AnnaBridge 156:ff21514d8981 213 #define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */
AnnaBridge 156:ff21514d8981 214 #define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */
AnnaBridge 156:ff21514d8981 215 #define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */
AnnaBridge 156:ff21514d8981 216 #define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */
AnnaBridge 156:ff21514d8981 217 #define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */
AnnaBridge 156:ff21514d8981 218 #define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */
AnnaBridge 156:ff21514d8981 219 #define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */
AnnaBridge 156:ff21514d8981 220 #define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */
AnnaBridge 156:ff21514d8981 221 #define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */
AnnaBridge 156:ff21514d8981 222 #define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */
AnnaBridge 156:ff21514d8981 223 #define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */
AnnaBridge 156:ff21514d8981 224 #define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */
AnnaBridge 156:ff21514d8981 225 #define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */
AnnaBridge 156:ff21514d8981 226 #define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */
AnnaBridge 156:ff21514d8981 227 #define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */
AnnaBridge 156:ff21514d8981 228 #define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */
AnnaBridge 156:ff21514d8981 229 #define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */
AnnaBridge 156:ff21514d8981 230 #define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */
AnnaBridge 156:ff21514d8981 231 #define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */
AnnaBridge 156:ff21514d8981 232 #define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */
AnnaBridge 156:ff21514d8981 233 #define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */
AnnaBridge 156:ff21514d8981 234 #define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */
AnnaBridge 156:ff21514d8981 235 #define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */
AnnaBridge 156:ff21514d8981 236 #define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */
AnnaBridge 156:ff21514d8981 237 #define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */
AnnaBridge 156:ff21514d8981 238 #define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */
AnnaBridge 156:ff21514d8981 239 #define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */
AnnaBridge 156:ff21514d8981 240 #define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */
AnnaBridge 156:ff21514d8981 241 #define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */
AnnaBridge 156:ff21514d8981 242 #define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */
AnnaBridge 156:ff21514d8981 243 #define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */
AnnaBridge 156:ff21514d8981 244 #define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */
AnnaBridge 156:ff21514d8981 245 #define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */
AnnaBridge 156:ff21514d8981 246 #define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */
AnnaBridge 156:ff21514d8981 247 #define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */
AnnaBridge 156:ff21514d8981 248 #define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */
AnnaBridge 156:ff21514d8981 249 #define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */
AnnaBridge 156:ff21514d8981 250 #define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */
AnnaBridge 156:ff21514d8981 251 #define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */
AnnaBridge 156:ff21514d8981 252 #define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */
AnnaBridge 156:ff21514d8981 253 #define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */
AnnaBridge 156:ff21514d8981 254 #define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */
AnnaBridge 156:ff21514d8981 255 #define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */
AnnaBridge 156:ff21514d8981 256 /**
AnnaBridge 156:ff21514d8981 257 * @}
AnnaBridge 156:ff21514d8981 258 */
AnnaBridge 156:ff21514d8981 259 #endif /* STM32F091xC || STM32F098xx */
AnnaBridge 156:ff21514d8981 260
AnnaBridge 156:ff21514d8981 261 /**
AnnaBridge 156:ff21514d8981 262 * @}
AnnaBridge 156:ff21514d8981 263 */
AnnaBridge 156:ff21514d8981 264
AnnaBridge 156:ff21514d8981 265 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 266 /** @defgroup HAL_Exported_Macros HAL Exported Macros
AnnaBridge 156:ff21514d8981 267 * @{
AnnaBridge 156:ff21514d8981 268 */
AnnaBridge 156:ff21514d8981 269
AnnaBridge 156:ff21514d8981 270 /** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals
AnnaBridge 156:ff21514d8981 271 * @brief Freeze/Unfreeze Peripherals in Debug mode
AnnaBridge 156:ff21514d8981 272 * @{
AnnaBridge 156:ff21514d8981 273 */
AnnaBridge 156:ff21514d8981 274
AnnaBridge 156:ff21514d8981 275 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
AnnaBridge 156:ff21514d8981 276 #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
AnnaBridge 156:ff21514d8981 277 #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
AnnaBridge 156:ff21514d8981 278 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
AnnaBridge 156:ff21514d8981 279
AnnaBridge 156:ff21514d8981 280 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
AnnaBridge 156:ff21514d8981 281 #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
AnnaBridge 156:ff21514d8981 282 #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
AnnaBridge 156:ff21514d8981 283 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
AnnaBridge 156:ff21514d8981 284
AnnaBridge 156:ff21514d8981 285 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
AnnaBridge 156:ff21514d8981 286 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
AnnaBridge 156:ff21514d8981 287 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
AnnaBridge 156:ff21514d8981 288 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
AnnaBridge 156:ff21514d8981 289
AnnaBridge 156:ff21514d8981 290 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
AnnaBridge 156:ff21514d8981 291 #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
AnnaBridge 156:ff21514d8981 292 #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
AnnaBridge 156:ff21514d8981 293 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
AnnaBridge 156:ff21514d8981 294
AnnaBridge 156:ff21514d8981 295 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
AnnaBridge 156:ff21514d8981 296 #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
AnnaBridge 156:ff21514d8981 297 #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
AnnaBridge 156:ff21514d8981 298 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
AnnaBridge 156:ff21514d8981 299
AnnaBridge 156:ff21514d8981 300 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
AnnaBridge 156:ff21514d8981 301 #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
AnnaBridge 156:ff21514d8981 302 #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
AnnaBridge 156:ff21514d8981 303 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
AnnaBridge 156:ff21514d8981 304
AnnaBridge 156:ff21514d8981 305 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
AnnaBridge 156:ff21514d8981 306 #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
AnnaBridge 156:ff21514d8981 307 #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
AnnaBridge 156:ff21514d8981 308 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
AnnaBridge 156:ff21514d8981 309
AnnaBridge 156:ff21514d8981 310 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
AnnaBridge 156:ff21514d8981 311 #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
AnnaBridge 156:ff21514d8981 312 #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
AnnaBridge 156:ff21514d8981 313 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
AnnaBridge 156:ff21514d8981 314
AnnaBridge 156:ff21514d8981 315 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
AnnaBridge 156:ff21514d8981 316 #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
AnnaBridge 156:ff21514d8981 317 #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
AnnaBridge 156:ff21514d8981 318 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
AnnaBridge 156:ff21514d8981 319
AnnaBridge 156:ff21514d8981 320 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
AnnaBridge 156:ff21514d8981 321 #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
AnnaBridge 156:ff21514d8981 322 #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
AnnaBridge 156:ff21514d8981 323 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
AnnaBridge 156:ff21514d8981 324
AnnaBridge 156:ff21514d8981 325 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
AnnaBridge 156:ff21514d8981 326 #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
AnnaBridge 156:ff21514d8981 327 #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
AnnaBridge 156:ff21514d8981 328 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
AnnaBridge 156:ff21514d8981 329
AnnaBridge 156:ff21514d8981 330 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
AnnaBridge 156:ff21514d8981 331 #define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
AnnaBridge 156:ff21514d8981 332 #define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
AnnaBridge 156:ff21514d8981 333 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
AnnaBridge 156:ff21514d8981 334
AnnaBridge 156:ff21514d8981 335 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
AnnaBridge 156:ff21514d8981 336 #define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
AnnaBridge 156:ff21514d8981 337 #define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
AnnaBridge 156:ff21514d8981 338 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
AnnaBridge 156:ff21514d8981 339
AnnaBridge 156:ff21514d8981 340 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
AnnaBridge 156:ff21514d8981 341 #define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
AnnaBridge 156:ff21514d8981 342 #define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
AnnaBridge 156:ff21514d8981 343 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
AnnaBridge 156:ff21514d8981 344
AnnaBridge 156:ff21514d8981 345 /**
AnnaBridge 156:ff21514d8981 346 * @}
AnnaBridge 156:ff21514d8981 347 */
AnnaBridge 156:ff21514d8981 348
AnnaBridge 156:ff21514d8981 349 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
AnnaBridge 156:ff21514d8981 350 * @{
AnnaBridge 156:ff21514d8981 351 */
AnnaBridge 156:ff21514d8981 352 #if defined(SYSCFG_CFGR1_MEM_MODE)
AnnaBridge 156:ff21514d8981 353 /** @brief Main Flash memory mapped at 0x00000000
AnnaBridge 156:ff21514d8981 354 */
AnnaBridge 156:ff21514d8981 355 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
AnnaBridge 156:ff21514d8981 356 #endif /* SYSCFG_CFGR1_MEM_MODE */
AnnaBridge 156:ff21514d8981 357
AnnaBridge 156:ff21514d8981 358 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
AnnaBridge 156:ff21514d8981 359 /** @brief System Flash memory mapped at 0x00000000
AnnaBridge 156:ff21514d8981 360 */
AnnaBridge 156:ff21514d8981 361 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
AnnaBridge 156:ff21514d8981 362 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
AnnaBridge 156:ff21514d8981 363 }while(0)
AnnaBridge 156:ff21514d8981 364 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
AnnaBridge 156:ff21514d8981 365
AnnaBridge 156:ff21514d8981 366 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
AnnaBridge 156:ff21514d8981 367 /** @brief Embedded SRAM mapped at 0x00000000
AnnaBridge 156:ff21514d8981 368 */
AnnaBridge 156:ff21514d8981 369 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
AnnaBridge 156:ff21514d8981 370 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
AnnaBridge 156:ff21514d8981 371 }while(0)
AnnaBridge 156:ff21514d8981 372 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
AnnaBridge 156:ff21514d8981 373 /**
AnnaBridge 156:ff21514d8981 374 * @}
AnnaBridge 156:ff21514d8981 375 */
AnnaBridge 156:ff21514d8981 376
AnnaBridge 156:ff21514d8981 377
AnnaBridge 156:ff21514d8981 378 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
AnnaBridge 156:ff21514d8981 379 /** @defgroup HAL_Pin_remap HAL Pin remap
AnnaBridge 156:ff21514d8981 380 * @brief Pin remapping enable/disable macros
AnnaBridge 156:ff21514d8981 381 * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping
AnnaBridge 156:ff21514d8981 382 * @{
AnnaBridge 156:ff21514d8981 383 */
AnnaBridge 156:ff21514d8981 384 #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
AnnaBridge 156:ff21514d8981 385 SYSCFG->CFGR1 |= (__PIN_REMAP__); \
AnnaBridge 156:ff21514d8981 386 }while(0)
AnnaBridge 156:ff21514d8981 387 #define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
AnnaBridge 156:ff21514d8981 388 SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \
AnnaBridge 156:ff21514d8981 389 }while(0)
AnnaBridge 156:ff21514d8981 390 /**
AnnaBridge 156:ff21514d8981 391 * @}
AnnaBridge 156:ff21514d8981 392 */
AnnaBridge 156:ff21514d8981 393 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
AnnaBridge 156:ff21514d8981 394
AnnaBridge 156:ff21514d8981 395 /** @brief Fast-mode Plus driving capability enable/disable macros
AnnaBridge 156:ff21514d8981 396 * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
AnnaBridge 156:ff21514d8981 397 * That you can find above these macros.
AnnaBridge 156:ff21514d8981 398 */
AnnaBridge 156:ff21514d8981 399 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
AnnaBridge 156:ff21514d8981 400 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
AnnaBridge 156:ff21514d8981 401 }while(0)
AnnaBridge 156:ff21514d8981 402
AnnaBridge 156:ff21514d8981 403 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
AnnaBridge 156:ff21514d8981 404 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
AnnaBridge 156:ff21514d8981 405 }while(0)
AnnaBridge 156:ff21514d8981 406 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
AnnaBridge 156:ff21514d8981 407 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
AnnaBridge 156:ff21514d8981 408 * @{
AnnaBridge 156:ff21514d8981 409 */
AnnaBridge 156:ff21514d8981 410 /** @brief SYSCFG Break Lockup lock
AnnaBridge 156:ff21514d8981 411 * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
AnnaBridge 156:ff21514d8981 412 * @note The selected configuration is locked and can be unlocked by system reset
AnnaBridge 156:ff21514d8981 413 */
AnnaBridge 156:ff21514d8981 414 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
AnnaBridge 156:ff21514d8981 415 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
AnnaBridge 156:ff21514d8981 416 }while(0)
AnnaBridge 156:ff21514d8981 417 /**
AnnaBridge 156:ff21514d8981 418 * @}
AnnaBridge 156:ff21514d8981 419 */
AnnaBridge 156:ff21514d8981 420 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
AnnaBridge 156:ff21514d8981 421
AnnaBridge 156:ff21514d8981 422 #if defined(SYSCFG_CFGR2_PVD_LOCK)
AnnaBridge 156:ff21514d8981 423 /** @defgroup PVD_Lock_Enable PVD Lock
AnnaBridge 156:ff21514d8981 424 * @{
AnnaBridge 156:ff21514d8981 425 */
AnnaBridge 156:ff21514d8981 426 /** @brief SYSCFG Break PVD lock
AnnaBridge 156:ff21514d8981 427 * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
AnnaBridge 156:ff21514d8981 428 * @note The selected configuration is locked and can be unlocked by system reset
AnnaBridge 156:ff21514d8981 429 */
AnnaBridge 156:ff21514d8981 430 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
AnnaBridge 156:ff21514d8981 431 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
AnnaBridge 156:ff21514d8981 432 }while(0)
AnnaBridge 156:ff21514d8981 433 /**
AnnaBridge 156:ff21514d8981 434 * @}
AnnaBridge 156:ff21514d8981 435 */
AnnaBridge 156:ff21514d8981 436 #endif /* SYSCFG_CFGR2_PVD_LOCK */
AnnaBridge 156:ff21514d8981 437
AnnaBridge 156:ff21514d8981 438 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
AnnaBridge 156:ff21514d8981 439 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
AnnaBridge 156:ff21514d8981 440 * @{
AnnaBridge 156:ff21514d8981 441 */
AnnaBridge 156:ff21514d8981 442 /** @brief SYSCFG Break SRAM PARITY lock
AnnaBridge 156:ff21514d8981 443 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
AnnaBridge 156:ff21514d8981 444 * @note The selected configuration is locked and can be unlocked by system reset
AnnaBridge 156:ff21514d8981 445 */
AnnaBridge 156:ff21514d8981 446 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
AnnaBridge 156:ff21514d8981 447 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
AnnaBridge 156:ff21514d8981 448 }while(0)
AnnaBridge 156:ff21514d8981 449 /**
AnnaBridge 156:ff21514d8981 450 * @}
AnnaBridge 156:ff21514d8981 451 */
AnnaBridge 156:ff21514d8981 452 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
AnnaBridge 156:ff21514d8981 453
AnnaBridge 156:ff21514d8981 454 #if defined(SYSCFG_CFGR2_SRAM_PEF)
AnnaBridge 156:ff21514d8981 455 /** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM
AnnaBridge 156:ff21514d8981 456 * @brief Parity check on RAM disable macro
AnnaBridge 156:ff21514d8981 457 * @note Disabling the parity check on RAM locks the configuration bit.
AnnaBridge 156:ff21514d8981 458 * To re-enable the parity check on RAM perform a system reset.
AnnaBridge 156:ff21514d8981 459 * @{
AnnaBridge 156:ff21514d8981 460 */
AnnaBridge 156:ff21514d8981 461 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
AnnaBridge 156:ff21514d8981 462 /**
AnnaBridge 156:ff21514d8981 463 * @}
AnnaBridge 156:ff21514d8981 464 */
AnnaBridge 156:ff21514d8981 465 #endif /* SYSCFG_CFGR2_SRAM_PEF */
AnnaBridge 156:ff21514d8981 466
AnnaBridge 156:ff21514d8981 467
AnnaBridge 156:ff21514d8981 468 #if defined(STM32F091xC) || defined (STM32F098xx)
AnnaBridge 156:ff21514d8981 469 /** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check
AnnaBridge 156:ff21514d8981 470 * @brief ISR wrapper check
AnnaBridge 156:ff21514d8981 471 * @note This feature is applicable on STM32F09x
AnnaBridge 156:ff21514d8981 472 * @note Allow to determine interrupt source per line.
AnnaBridge 156:ff21514d8981 473 * @{
AnnaBridge 156:ff21514d8981 474 */
AnnaBridge 156:ff21514d8981 475 #define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
AnnaBridge 156:ff21514d8981 476 /**
AnnaBridge 156:ff21514d8981 477 * @}
AnnaBridge 156:ff21514d8981 478 */
AnnaBridge 156:ff21514d8981 479 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
AnnaBridge 156:ff21514d8981 480
AnnaBridge 156:ff21514d8981 481 #if defined(STM32F091xC) || defined (STM32F098xx)
AnnaBridge 156:ff21514d8981 482 /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
AnnaBridge 156:ff21514d8981 483 * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
AnnaBridge 156:ff21514d8981 484 * @note This feature is applicable on STM32F09x
AnnaBridge 156:ff21514d8981 485 * @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL
AnnaBridge 156:ff21514d8981 486 * @{
AnnaBridge 156:ff21514d8981 487 */
AnnaBridge 156:ff21514d8981 488 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
AnnaBridge 156:ff21514d8981 489 SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \
AnnaBridge 156:ff21514d8981 490 SYSCFG->CFGR1 |= (__SOURCE__); \
AnnaBridge 156:ff21514d8981 491 }while(0)
AnnaBridge 156:ff21514d8981 492
AnnaBridge 156:ff21514d8981 493 #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0)
AnnaBridge 156:ff21514d8981 494 /**
AnnaBridge 156:ff21514d8981 495 * @}
AnnaBridge 156:ff21514d8981 496 */
AnnaBridge 156:ff21514d8981 497 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
AnnaBridge 156:ff21514d8981 498
AnnaBridge 156:ff21514d8981 499 /**
AnnaBridge 156:ff21514d8981 500 * @}
AnnaBridge 156:ff21514d8981 501 */
AnnaBridge 156:ff21514d8981 502
AnnaBridge 156:ff21514d8981 503 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 504
AnnaBridge 156:ff21514d8981 505 /** @addtogroup HAL_Exported_Functions
AnnaBridge 156:ff21514d8981 506 * @{
AnnaBridge 156:ff21514d8981 507 */
AnnaBridge 156:ff21514d8981 508
AnnaBridge 156:ff21514d8981 509 /** @addtogroup HAL_Exported_Functions_Group1
AnnaBridge 156:ff21514d8981 510 * @{
AnnaBridge 156:ff21514d8981 511 */
AnnaBridge 156:ff21514d8981 512 /* Initialization and de-initialization functions ******************************/
AnnaBridge 156:ff21514d8981 513 HAL_StatusTypeDef HAL_Init(void);
AnnaBridge 156:ff21514d8981 514 HAL_StatusTypeDef HAL_DeInit(void);
AnnaBridge 156:ff21514d8981 515 void HAL_MspInit(void);
AnnaBridge 156:ff21514d8981 516 void HAL_MspDeInit(void);
AnnaBridge 156:ff21514d8981 517 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
AnnaBridge 156:ff21514d8981 518 /**
AnnaBridge 156:ff21514d8981 519 * @}
AnnaBridge 156:ff21514d8981 520 */
AnnaBridge 156:ff21514d8981 521
AnnaBridge 156:ff21514d8981 522 /** @addtogroup HAL_Exported_Functions_Group2
AnnaBridge 156:ff21514d8981 523 * @{
AnnaBridge 156:ff21514d8981 524 */
AnnaBridge 156:ff21514d8981 525
AnnaBridge 156:ff21514d8981 526 /* Peripheral Control functions ************************************************/
AnnaBridge 156:ff21514d8981 527 void HAL_IncTick(void);
AnnaBridge 156:ff21514d8981 528 void HAL_Delay(__IO uint32_t Delay);
AnnaBridge 156:ff21514d8981 529 uint32_t HAL_GetTick(void);
AnnaBridge 156:ff21514d8981 530 void HAL_SuspendTick(void);
AnnaBridge 156:ff21514d8981 531 void HAL_ResumeTick(void);
AnnaBridge 156:ff21514d8981 532 uint32_t HAL_GetHalVersion(void);
AnnaBridge 156:ff21514d8981 533 uint32_t HAL_GetREVID(void);
AnnaBridge 156:ff21514d8981 534 uint32_t HAL_GetDEVID(void);
AnnaBridge 156:ff21514d8981 535 void HAL_DBGMCU_EnableDBGStopMode(void);
AnnaBridge 156:ff21514d8981 536 void HAL_DBGMCU_DisableDBGStopMode(void);
AnnaBridge 156:ff21514d8981 537 void HAL_DBGMCU_EnableDBGStandbyMode(void);
AnnaBridge 156:ff21514d8981 538 void HAL_DBGMCU_DisableDBGStandbyMode(void);
AnnaBridge 156:ff21514d8981 539 /**
AnnaBridge 156:ff21514d8981 540 * @}
AnnaBridge 156:ff21514d8981 541 */
AnnaBridge 156:ff21514d8981 542
AnnaBridge 156:ff21514d8981 543 /**
AnnaBridge 156:ff21514d8981 544 * @}
AnnaBridge 156:ff21514d8981 545 */
AnnaBridge 156:ff21514d8981 546
AnnaBridge 156:ff21514d8981 547 /**
AnnaBridge 156:ff21514d8981 548 * @}
AnnaBridge 156:ff21514d8981 549 */
AnnaBridge 156:ff21514d8981 550
AnnaBridge 156:ff21514d8981 551 /**
AnnaBridge 156:ff21514d8981 552 * @}
AnnaBridge 156:ff21514d8981 553 */
AnnaBridge 156:ff21514d8981 554
AnnaBridge 156:ff21514d8981 555 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 556 }
AnnaBridge 156:ff21514d8981 557 #endif
AnnaBridge 156:ff21514d8981 558
AnnaBridge 156:ff21514d8981 559 #endif /* __STM32F0xx_HAL_H */
AnnaBridge 156:ff21514d8981 560
AnnaBridge 156:ff21514d8981 561 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/