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TARGET_NUCLEO_F091RC/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
156:ff21514d8981
Child:
160:5571c4ff569f
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32_hal_legacy.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @version V1.5.0
AnnaBridge 156:ff21514d8981 6 * @date 04-November-2016
AnnaBridge 156:ff21514d8981 7 * @brief This file contains aliases definition for the STM32Cube HAL constants
AnnaBridge 156:ff21514d8981 8 * macros and functions maintained for legacy purpose.
AnnaBridge 156:ff21514d8981 9 ******************************************************************************
AnnaBridge 156:ff21514d8981 10 * @attention
AnnaBridge 156:ff21514d8981 11 *
AnnaBridge 156:ff21514d8981 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 13 *
AnnaBridge 156:ff21514d8981 14 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 15 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 16 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 17 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 20 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 22 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 23 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 24 *
AnnaBridge 156:ff21514d8981 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 35 *
AnnaBridge 156:ff21514d8981 36 ******************************************************************************
AnnaBridge 156:ff21514d8981 37 */
AnnaBridge 156:ff21514d8981 38
AnnaBridge 156:ff21514d8981 39 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 40 #ifndef __STM32_HAL_LEGACY
AnnaBridge 156:ff21514d8981 41 #define __STM32_HAL_LEGACY
AnnaBridge 156:ff21514d8981 42
AnnaBridge 156:ff21514d8981 43 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 44 extern "C" {
AnnaBridge 156:ff21514d8981 45 #endif
AnnaBridge 156:ff21514d8981 46
AnnaBridge 156:ff21514d8981 47 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 48 /* Exported types ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 49 /* Exported constants --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 50
AnnaBridge 156:ff21514d8981 51 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 52 * @{
AnnaBridge 156:ff21514d8981 53 */
AnnaBridge 156:ff21514d8981 54 #define AES_FLAG_RDERR CRYP_FLAG_RDERR
AnnaBridge 156:ff21514d8981 55 #define AES_FLAG_WRERR CRYP_FLAG_WRERR
AnnaBridge 156:ff21514d8981 56 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
AnnaBridge 156:ff21514d8981 57 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
AnnaBridge 156:ff21514d8981 58 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
AnnaBridge 156:ff21514d8981 59
AnnaBridge 156:ff21514d8981 60 /**
AnnaBridge 156:ff21514d8981 61 * @}
AnnaBridge 156:ff21514d8981 62 */
AnnaBridge 156:ff21514d8981 63
AnnaBridge 156:ff21514d8981 64 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 65 * @{
AnnaBridge 156:ff21514d8981 66 */
AnnaBridge 156:ff21514d8981 67 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
AnnaBridge 156:ff21514d8981 68 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
AnnaBridge 156:ff21514d8981 69 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
AnnaBridge 156:ff21514d8981 70 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
AnnaBridge 156:ff21514d8981 71 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
AnnaBridge 156:ff21514d8981 72 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
AnnaBridge 156:ff21514d8981 73 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
AnnaBridge 156:ff21514d8981 74 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
AnnaBridge 156:ff21514d8981 75 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
AnnaBridge 156:ff21514d8981 76 #define REGULAR_GROUP ADC_REGULAR_GROUP
AnnaBridge 156:ff21514d8981 77 #define INJECTED_GROUP ADC_INJECTED_GROUP
AnnaBridge 156:ff21514d8981 78 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
AnnaBridge 156:ff21514d8981 79 #define AWD_EVENT ADC_AWD_EVENT
AnnaBridge 156:ff21514d8981 80 #define AWD1_EVENT ADC_AWD1_EVENT
AnnaBridge 156:ff21514d8981 81 #define AWD2_EVENT ADC_AWD2_EVENT
AnnaBridge 156:ff21514d8981 82 #define AWD3_EVENT ADC_AWD3_EVENT
AnnaBridge 156:ff21514d8981 83 #define OVR_EVENT ADC_OVR_EVENT
AnnaBridge 156:ff21514d8981 84 #define JQOVF_EVENT ADC_JQOVF_EVENT
AnnaBridge 156:ff21514d8981 85 #define ALL_CHANNELS ADC_ALL_CHANNELS
AnnaBridge 156:ff21514d8981 86 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
AnnaBridge 156:ff21514d8981 87 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
AnnaBridge 156:ff21514d8981 88 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
AnnaBridge 156:ff21514d8981 89 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
AnnaBridge 156:ff21514d8981 90 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
AnnaBridge 156:ff21514d8981 91 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
AnnaBridge 156:ff21514d8981 92 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
AnnaBridge 156:ff21514d8981 93 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
AnnaBridge 156:ff21514d8981 94 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
AnnaBridge 156:ff21514d8981 95 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
AnnaBridge 156:ff21514d8981 96 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
AnnaBridge 156:ff21514d8981 97 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
AnnaBridge 156:ff21514d8981 98 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
AnnaBridge 156:ff21514d8981 99 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
AnnaBridge 156:ff21514d8981 100 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
AnnaBridge 156:ff21514d8981 101 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
AnnaBridge 156:ff21514d8981 102 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
AnnaBridge 156:ff21514d8981 103 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
AnnaBridge 156:ff21514d8981 104 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
AnnaBridge 156:ff21514d8981 105 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
AnnaBridge 156:ff21514d8981 106 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
AnnaBridge 156:ff21514d8981 107
AnnaBridge 156:ff21514d8981 108 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
AnnaBridge 156:ff21514d8981 109 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
AnnaBridge 156:ff21514d8981 110 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
AnnaBridge 156:ff21514d8981 111 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
AnnaBridge 156:ff21514d8981 112 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
AnnaBridge 156:ff21514d8981 113 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
AnnaBridge 156:ff21514d8981 114 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
AnnaBridge 156:ff21514d8981 115 /**
AnnaBridge 156:ff21514d8981 116 * @}
AnnaBridge 156:ff21514d8981 117 */
AnnaBridge 156:ff21514d8981 118
AnnaBridge 156:ff21514d8981 119 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 120 * @{
AnnaBridge 156:ff21514d8981 121 */
AnnaBridge 156:ff21514d8981 122
AnnaBridge 156:ff21514d8981 123 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
AnnaBridge 156:ff21514d8981 124
AnnaBridge 156:ff21514d8981 125 /**
AnnaBridge 156:ff21514d8981 126 * @}
AnnaBridge 156:ff21514d8981 127 */
AnnaBridge 156:ff21514d8981 128
AnnaBridge 156:ff21514d8981 129 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 130 * @{
AnnaBridge 156:ff21514d8981 131 */
AnnaBridge 156:ff21514d8981 132 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
AnnaBridge 156:ff21514d8981 133 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
AnnaBridge 156:ff21514d8981 134 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
AnnaBridge 156:ff21514d8981 135 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
AnnaBridge 156:ff21514d8981 136 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
AnnaBridge 156:ff21514d8981 137 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
AnnaBridge 156:ff21514d8981 138 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
AnnaBridge 156:ff21514d8981 139 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
AnnaBridge 156:ff21514d8981 140 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
AnnaBridge 156:ff21514d8981 141 #define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
AnnaBridge 156:ff21514d8981 142 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
AnnaBridge 156:ff21514d8981 143 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 156:ff21514d8981 144 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
AnnaBridge 156:ff21514d8981 145 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
AnnaBridge 156:ff21514d8981 146 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 156:ff21514d8981 147
AnnaBridge 156:ff21514d8981 148 #if defined(STM32L0) || defined(STM32L4)
AnnaBridge 156:ff21514d8981 149 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
AnnaBridge 156:ff21514d8981 150
AnnaBridge 156:ff21514d8981 151 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
AnnaBridge 156:ff21514d8981 152 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
AnnaBridge 156:ff21514d8981 153 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
AnnaBridge 156:ff21514d8981 154 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
AnnaBridge 156:ff21514d8981 155 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
AnnaBridge 156:ff21514d8981 156 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
AnnaBridge 156:ff21514d8981 157
AnnaBridge 156:ff21514d8981 158 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
AnnaBridge 156:ff21514d8981 159 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
AnnaBridge 156:ff21514d8981 160 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
AnnaBridge 156:ff21514d8981 161 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
AnnaBridge 156:ff21514d8981 162 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
AnnaBridge 156:ff21514d8981 163 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
AnnaBridge 156:ff21514d8981 164 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
AnnaBridge 156:ff21514d8981 165 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
AnnaBridge 156:ff21514d8981 166 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
AnnaBridge 156:ff21514d8981 167 #if defined(STM32L0)
AnnaBridge 156:ff21514d8981 168 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
AnnaBridge 156:ff21514d8981 169 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
AnnaBridge 156:ff21514d8981 170 /* to the second dedicated IO (only for COMP2). */
AnnaBridge 156:ff21514d8981 171 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
AnnaBridge 156:ff21514d8981 172 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
AnnaBridge 156:ff21514d8981 173 #else
AnnaBridge 156:ff21514d8981 174 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
AnnaBridge 156:ff21514d8981 175 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
AnnaBridge 156:ff21514d8981 176 #endif
AnnaBridge 156:ff21514d8981 177 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
AnnaBridge 156:ff21514d8981 178 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
AnnaBridge 156:ff21514d8981 179
AnnaBridge 156:ff21514d8981 180 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
AnnaBridge 156:ff21514d8981 181 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
AnnaBridge 156:ff21514d8981 182
AnnaBridge 156:ff21514d8981 183 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
AnnaBridge 156:ff21514d8981 184 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
AnnaBridge 156:ff21514d8981 185 #if defined(COMP_CSR_LOCK)
AnnaBridge 156:ff21514d8981 186 #define COMP_FLAG_LOCK COMP_CSR_LOCK
AnnaBridge 156:ff21514d8981 187 #elif defined(COMP_CSR_COMP1LOCK)
AnnaBridge 156:ff21514d8981 188 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
AnnaBridge 156:ff21514d8981 189 #elif defined(COMP_CSR_COMPxLOCK)
AnnaBridge 156:ff21514d8981 190 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
AnnaBridge 156:ff21514d8981 191 #endif
AnnaBridge 156:ff21514d8981 192
AnnaBridge 156:ff21514d8981 193 #if defined(STM32L4)
AnnaBridge 156:ff21514d8981 194 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
AnnaBridge 156:ff21514d8981 195 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
AnnaBridge 156:ff21514d8981 196 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
AnnaBridge 156:ff21514d8981 197 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
AnnaBridge 156:ff21514d8981 198 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
AnnaBridge 156:ff21514d8981 199 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
AnnaBridge 156:ff21514d8981 200 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
AnnaBridge 156:ff21514d8981 201 #endif
AnnaBridge 156:ff21514d8981 202
AnnaBridge 156:ff21514d8981 203 #if defined(STM32L0)
AnnaBridge 156:ff21514d8981 204 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
AnnaBridge 156:ff21514d8981 205 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
AnnaBridge 156:ff21514d8981 206 #else
AnnaBridge 156:ff21514d8981 207 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
AnnaBridge 156:ff21514d8981 208 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
AnnaBridge 156:ff21514d8981 209 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
AnnaBridge 156:ff21514d8981 210 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
AnnaBridge 156:ff21514d8981 211 #endif
AnnaBridge 156:ff21514d8981 212
AnnaBridge 156:ff21514d8981 213 #endif
AnnaBridge 156:ff21514d8981 214 /**
AnnaBridge 156:ff21514d8981 215 * @}
AnnaBridge 156:ff21514d8981 216 */
AnnaBridge 156:ff21514d8981 217
AnnaBridge 156:ff21514d8981 218 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 219 * @{
AnnaBridge 156:ff21514d8981 220 */
AnnaBridge 156:ff21514d8981 221 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
AnnaBridge 156:ff21514d8981 222 /**
AnnaBridge 156:ff21514d8981 223 * @}
AnnaBridge 156:ff21514d8981 224 */
AnnaBridge 156:ff21514d8981 225
AnnaBridge 156:ff21514d8981 226 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 227 * @{
AnnaBridge 156:ff21514d8981 228 */
AnnaBridge 156:ff21514d8981 229
AnnaBridge 156:ff21514d8981 230 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
AnnaBridge 156:ff21514d8981 231 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
AnnaBridge 156:ff21514d8981 232
AnnaBridge 156:ff21514d8981 233 /**
AnnaBridge 156:ff21514d8981 234 * @}
AnnaBridge 156:ff21514d8981 235 */
AnnaBridge 156:ff21514d8981 236
AnnaBridge 156:ff21514d8981 237 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 238 * @{
AnnaBridge 156:ff21514d8981 239 */
AnnaBridge 156:ff21514d8981 240
AnnaBridge 156:ff21514d8981 241 #define DAC1_CHANNEL_1 DAC_CHANNEL_1
AnnaBridge 156:ff21514d8981 242 #define DAC1_CHANNEL_2 DAC_CHANNEL_2
AnnaBridge 156:ff21514d8981 243 #define DAC2_CHANNEL_1 DAC_CHANNEL_1
AnnaBridge 156:ff21514d8981 244 #define DAC_WAVE_NONE ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 245 #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
AnnaBridge 156:ff21514d8981 246 #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
AnnaBridge 156:ff21514d8981 247 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
AnnaBridge 156:ff21514d8981 248 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
AnnaBridge 156:ff21514d8981 249 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
AnnaBridge 156:ff21514d8981 250
AnnaBridge 156:ff21514d8981 251 /**
AnnaBridge 156:ff21514d8981 252 * @}
AnnaBridge 156:ff21514d8981 253 */
AnnaBridge 156:ff21514d8981 254
AnnaBridge 156:ff21514d8981 255 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 256 * @{
AnnaBridge 156:ff21514d8981 257 */
AnnaBridge 156:ff21514d8981 258 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
AnnaBridge 156:ff21514d8981 259 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
AnnaBridge 156:ff21514d8981 260 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
AnnaBridge 156:ff21514d8981 261 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
AnnaBridge 156:ff21514d8981 262 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
AnnaBridge 156:ff21514d8981 263 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
AnnaBridge 156:ff21514d8981 264 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
AnnaBridge 156:ff21514d8981 265 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
AnnaBridge 156:ff21514d8981 266 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
AnnaBridge 156:ff21514d8981 267 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
AnnaBridge 156:ff21514d8981 268 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
AnnaBridge 156:ff21514d8981 269 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
AnnaBridge 156:ff21514d8981 270 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
AnnaBridge 156:ff21514d8981 271 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
AnnaBridge 156:ff21514d8981 272 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
AnnaBridge 156:ff21514d8981 273
AnnaBridge 156:ff21514d8981 274 #define IS_HAL_REMAPDMA IS_DMA_REMAP
AnnaBridge 156:ff21514d8981 275 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
AnnaBridge 156:ff21514d8981 276 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
AnnaBridge 156:ff21514d8981 277
AnnaBridge 156:ff21514d8981 278
AnnaBridge 156:ff21514d8981 279
AnnaBridge 156:ff21514d8981 280 /**
AnnaBridge 156:ff21514d8981 281 * @}
AnnaBridge 156:ff21514d8981 282 */
AnnaBridge 156:ff21514d8981 283
AnnaBridge 156:ff21514d8981 284 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 285 * @{
AnnaBridge 156:ff21514d8981 286 */
AnnaBridge 156:ff21514d8981 287
AnnaBridge 156:ff21514d8981 288 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
AnnaBridge 156:ff21514d8981 289 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
AnnaBridge 156:ff21514d8981 290 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
AnnaBridge 156:ff21514d8981 291 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
AnnaBridge 156:ff21514d8981 292 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
AnnaBridge 156:ff21514d8981 293 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
AnnaBridge 156:ff21514d8981 294 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
AnnaBridge 156:ff21514d8981 295 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
AnnaBridge 156:ff21514d8981 296 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
AnnaBridge 156:ff21514d8981 297 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
AnnaBridge 156:ff21514d8981 298 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
AnnaBridge 156:ff21514d8981 299 #define OBEX_PCROP OPTIONBYTE_PCROP
AnnaBridge 156:ff21514d8981 300 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
AnnaBridge 156:ff21514d8981 301 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
AnnaBridge 156:ff21514d8981 302 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
AnnaBridge 156:ff21514d8981 303 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
AnnaBridge 156:ff21514d8981 304 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
AnnaBridge 156:ff21514d8981 305 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
AnnaBridge 156:ff21514d8981 306 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
AnnaBridge 156:ff21514d8981 307 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
AnnaBridge 156:ff21514d8981 308 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
AnnaBridge 156:ff21514d8981 309 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
AnnaBridge 156:ff21514d8981 310 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
AnnaBridge 156:ff21514d8981 311 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
AnnaBridge 156:ff21514d8981 312 #define PAGESIZE FLASH_PAGE_SIZE
AnnaBridge 156:ff21514d8981 313 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
AnnaBridge 156:ff21514d8981 314 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
AnnaBridge 156:ff21514d8981 315 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
AnnaBridge 156:ff21514d8981 316 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
AnnaBridge 156:ff21514d8981 317 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
AnnaBridge 156:ff21514d8981 318 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
AnnaBridge 156:ff21514d8981 319 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
AnnaBridge 156:ff21514d8981 320 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
AnnaBridge 156:ff21514d8981 321 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
AnnaBridge 156:ff21514d8981 322 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
AnnaBridge 156:ff21514d8981 323 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
AnnaBridge 156:ff21514d8981 324 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
AnnaBridge 156:ff21514d8981 325 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
AnnaBridge 156:ff21514d8981 326 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
AnnaBridge 156:ff21514d8981 327 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
AnnaBridge 156:ff21514d8981 328 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
AnnaBridge 156:ff21514d8981 329 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
AnnaBridge 156:ff21514d8981 330 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
AnnaBridge 156:ff21514d8981 331 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
AnnaBridge 156:ff21514d8981 332 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
AnnaBridge 156:ff21514d8981 333 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
AnnaBridge 156:ff21514d8981 334 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
AnnaBridge 156:ff21514d8981 335 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
AnnaBridge 156:ff21514d8981 336 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
AnnaBridge 156:ff21514d8981 337 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
AnnaBridge 156:ff21514d8981 338 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
AnnaBridge 156:ff21514d8981 339 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
AnnaBridge 156:ff21514d8981 340 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
AnnaBridge 156:ff21514d8981 341 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
AnnaBridge 156:ff21514d8981 342 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
AnnaBridge 156:ff21514d8981 343 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
AnnaBridge 156:ff21514d8981 344 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
AnnaBridge 156:ff21514d8981 345 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
AnnaBridge 156:ff21514d8981 346 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
AnnaBridge 156:ff21514d8981 347 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
AnnaBridge 156:ff21514d8981 348 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
AnnaBridge 156:ff21514d8981 349 #define OB_WDG_SW OB_IWDG_SW
AnnaBridge 156:ff21514d8981 350 #define OB_WDG_HW OB_IWDG_HW
AnnaBridge 156:ff21514d8981 351 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
AnnaBridge 156:ff21514d8981 352 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
AnnaBridge 156:ff21514d8981 353 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
AnnaBridge 156:ff21514d8981 354 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
AnnaBridge 156:ff21514d8981 355 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
AnnaBridge 156:ff21514d8981 356 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
AnnaBridge 156:ff21514d8981 357 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
AnnaBridge 156:ff21514d8981 358 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
AnnaBridge 156:ff21514d8981 359
AnnaBridge 156:ff21514d8981 360 /**
AnnaBridge 156:ff21514d8981 361 * @}
AnnaBridge 156:ff21514d8981 362 */
AnnaBridge 156:ff21514d8981 363
AnnaBridge 156:ff21514d8981 364 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 365 * @{
AnnaBridge 156:ff21514d8981 366 */
AnnaBridge 156:ff21514d8981 367
AnnaBridge 156:ff21514d8981 368 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
AnnaBridge 156:ff21514d8981 369 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
AnnaBridge 156:ff21514d8981 370 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
AnnaBridge 156:ff21514d8981 371 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
AnnaBridge 156:ff21514d8981 372 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
AnnaBridge 156:ff21514d8981 373 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
AnnaBridge 156:ff21514d8981 374 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
AnnaBridge 156:ff21514d8981 375 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
AnnaBridge 156:ff21514d8981 376 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
AnnaBridge 156:ff21514d8981 377 /**
AnnaBridge 156:ff21514d8981 378 * @}
AnnaBridge 156:ff21514d8981 379 */
AnnaBridge 156:ff21514d8981 380
AnnaBridge 156:ff21514d8981 381
AnnaBridge 156:ff21514d8981 382 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
AnnaBridge 156:ff21514d8981 383 * @{
AnnaBridge 156:ff21514d8981 384 */
AnnaBridge 156:ff21514d8981 385 #if defined(STM32L4) || defined(STM32F7)
AnnaBridge 156:ff21514d8981 386 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
AnnaBridge 156:ff21514d8981 387 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
AnnaBridge 156:ff21514d8981 388 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
AnnaBridge 156:ff21514d8981 389 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
AnnaBridge 156:ff21514d8981 390 #else
AnnaBridge 156:ff21514d8981 391 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
AnnaBridge 156:ff21514d8981 392 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
AnnaBridge 156:ff21514d8981 393 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
AnnaBridge 156:ff21514d8981 394 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
AnnaBridge 156:ff21514d8981 395 #endif
AnnaBridge 156:ff21514d8981 396 /**
AnnaBridge 156:ff21514d8981 397 * @}
AnnaBridge 156:ff21514d8981 398 */
AnnaBridge 156:ff21514d8981 399
AnnaBridge 156:ff21514d8981 400 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 401 * @{
AnnaBridge 156:ff21514d8981 402 */
AnnaBridge 156:ff21514d8981 403
AnnaBridge 156:ff21514d8981 404 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
AnnaBridge 156:ff21514d8981 405 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
AnnaBridge 156:ff21514d8981 406 /**
AnnaBridge 156:ff21514d8981 407 * @}
AnnaBridge 156:ff21514d8981 408 */
AnnaBridge 156:ff21514d8981 409
AnnaBridge 156:ff21514d8981 410 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 411 * @{
AnnaBridge 156:ff21514d8981 412 */
AnnaBridge 156:ff21514d8981 413 #define GET_GPIO_SOURCE GPIO_GET_INDEX
AnnaBridge 156:ff21514d8981 414 #define GET_GPIO_INDEX GPIO_GET_INDEX
AnnaBridge 156:ff21514d8981 415
AnnaBridge 156:ff21514d8981 416 #if defined(STM32F4)
AnnaBridge 156:ff21514d8981 417 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO
AnnaBridge 156:ff21514d8981 418 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
AnnaBridge 156:ff21514d8981 419 #endif
AnnaBridge 156:ff21514d8981 420
AnnaBridge 156:ff21514d8981 421 #if defined(STM32F7)
AnnaBridge 156:ff21514d8981 422 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
AnnaBridge 156:ff21514d8981 423 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
AnnaBridge 156:ff21514d8981 424 #endif
AnnaBridge 156:ff21514d8981 425
AnnaBridge 156:ff21514d8981 426 #if defined(STM32L4)
AnnaBridge 156:ff21514d8981 427 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
AnnaBridge 156:ff21514d8981 428 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
AnnaBridge 156:ff21514d8981 429 #endif
AnnaBridge 156:ff21514d8981 430
AnnaBridge 156:ff21514d8981 431 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
AnnaBridge 156:ff21514d8981 432 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
AnnaBridge 156:ff21514d8981 433 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
AnnaBridge 156:ff21514d8981 434
AnnaBridge 156:ff21514d8981 435 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
AnnaBridge 156:ff21514d8981 436 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
AnnaBridge 156:ff21514d8981 437 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
AnnaBridge 156:ff21514d8981 438 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
AnnaBridge 156:ff21514d8981 439 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
AnnaBridge 156:ff21514d8981 440 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
AnnaBridge 156:ff21514d8981 441
AnnaBridge 156:ff21514d8981 442 #if defined(STM32L1)
AnnaBridge 156:ff21514d8981 443 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
AnnaBridge 156:ff21514d8981 444 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
AnnaBridge 156:ff21514d8981 445 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
AnnaBridge 156:ff21514d8981 446 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
AnnaBridge 156:ff21514d8981 447 #endif /* STM32L1 */
AnnaBridge 156:ff21514d8981 448
AnnaBridge 156:ff21514d8981 449 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
AnnaBridge 156:ff21514d8981 450 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
AnnaBridge 156:ff21514d8981 451 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
AnnaBridge 156:ff21514d8981 452 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
AnnaBridge 156:ff21514d8981 453 #endif /* STM32F0 || STM32F3 || STM32F1 */
AnnaBridge 156:ff21514d8981 454
AnnaBridge 156:ff21514d8981 455 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
AnnaBridge 156:ff21514d8981 456 /**
AnnaBridge 156:ff21514d8981 457 * @}
AnnaBridge 156:ff21514d8981 458 */
AnnaBridge 156:ff21514d8981 459
AnnaBridge 156:ff21514d8981 460 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 461 * @{
AnnaBridge 156:ff21514d8981 462 */
AnnaBridge 156:ff21514d8981 463 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
AnnaBridge 156:ff21514d8981 464 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
AnnaBridge 156:ff21514d8981 465 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
AnnaBridge 156:ff21514d8981 466 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
AnnaBridge 156:ff21514d8981 467 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
AnnaBridge 156:ff21514d8981 468 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
AnnaBridge 156:ff21514d8981 469 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
AnnaBridge 156:ff21514d8981 470 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
AnnaBridge 156:ff21514d8981 471 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
AnnaBridge 156:ff21514d8981 472
AnnaBridge 156:ff21514d8981 473 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
AnnaBridge 156:ff21514d8981 474 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
AnnaBridge 156:ff21514d8981 475 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
AnnaBridge 156:ff21514d8981 476 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
AnnaBridge 156:ff21514d8981 477 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
AnnaBridge 156:ff21514d8981 478 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
AnnaBridge 156:ff21514d8981 479 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
AnnaBridge 156:ff21514d8981 480 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
AnnaBridge 156:ff21514d8981 481 /**
AnnaBridge 156:ff21514d8981 482 * @}
AnnaBridge 156:ff21514d8981 483 */
AnnaBridge 156:ff21514d8981 484
AnnaBridge 156:ff21514d8981 485 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 486 * @{
AnnaBridge 156:ff21514d8981 487 */
AnnaBridge 156:ff21514d8981 488 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
AnnaBridge 156:ff21514d8981 489 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
AnnaBridge 156:ff21514d8981 490 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
AnnaBridge 156:ff21514d8981 491 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
AnnaBridge 156:ff21514d8981 492 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
AnnaBridge 156:ff21514d8981 493 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
AnnaBridge 156:ff21514d8981 494 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
AnnaBridge 156:ff21514d8981 495 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
AnnaBridge 156:ff21514d8981 496 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
AnnaBridge 156:ff21514d8981 497 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
AnnaBridge 156:ff21514d8981 498 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
AnnaBridge 156:ff21514d8981 499 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
AnnaBridge 156:ff21514d8981 500 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
AnnaBridge 156:ff21514d8981 501 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
AnnaBridge 156:ff21514d8981 502 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
AnnaBridge 156:ff21514d8981 503 #endif
AnnaBridge 156:ff21514d8981 504 /**
AnnaBridge 156:ff21514d8981 505 * @}
AnnaBridge 156:ff21514d8981 506 */
AnnaBridge 156:ff21514d8981 507
AnnaBridge 156:ff21514d8981 508 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 509 * @{
AnnaBridge 156:ff21514d8981 510 */
AnnaBridge 156:ff21514d8981 511 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
AnnaBridge 156:ff21514d8981 512 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
AnnaBridge 156:ff21514d8981 513
AnnaBridge 156:ff21514d8981 514 /**
AnnaBridge 156:ff21514d8981 515 * @}
AnnaBridge 156:ff21514d8981 516 */
AnnaBridge 156:ff21514d8981 517
AnnaBridge 156:ff21514d8981 518 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 519 * @{
AnnaBridge 156:ff21514d8981 520 */
AnnaBridge 156:ff21514d8981 521 #define KR_KEY_RELOAD IWDG_KEY_RELOAD
AnnaBridge 156:ff21514d8981 522 #define KR_KEY_ENABLE IWDG_KEY_ENABLE
AnnaBridge 156:ff21514d8981 523 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
AnnaBridge 156:ff21514d8981 524 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
AnnaBridge 156:ff21514d8981 525 /**
AnnaBridge 156:ff21514d8981 526 * @}
AnnaBridge 156:ff21514d8981 527 */
AnnaBridge 156:ff21514d8981 528
AnnaBridge 156:ff21514d8981 529 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 530 * @{
AnnaBridge 156:ff21514d8981 531 */
AnnaBridge 156:ff21514d8981 532
AnnaBridge 156:ff21514d8981 533 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
AnnaBridge 156:ff21514d8981 534 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
AnnaBridge 156:ff21514d8981 535 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
AnnaBridge 156:ff21514d8981 536 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
AnnaBridge 156:ff21514d8981 537
AnnaBridge 156:ff21514d8981 538 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
AnnaBridge 156:ff21514d8981 539 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
AnnaBridge 156:ff21514d8981 540 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
AnnaBridge 156:ff21514d8981 541
AnnaBridge 156:ff21514d8981 542 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
AnnaBridge 156:ff21514d8981 543 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
AnnaBridge 156:ff21514d8981 544 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
AnnaBridge 156:ff21514d8981 545 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
AnnaBridge 156:ff21514d8981 546
AnnaBridge 156:ff21514d8981 547 /* The following 3 definition have also been present in a temporary version of lptim.h */
AnnaBridge 156:ff21514d8981 548 /* They need to be renamed also to the right name, just in case */
AnnaBridge 156:ff21514d8981 549 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
AnnaBridge 156:ff21514d8981 550 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
AnnaBridge 156:ff21514d8981 551 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
AnnaBridge 156:ff21514d8981 552
AnnaBridge 156:ff21514d8981 553 /**
AnnaBridge 156:ff21514d8981 554 * @}
AnnaBridge 156:ff21514d8981 555 */
AnnaBridge 156:ff21514d8981 556
AnnaBridge 156:ff21514d8981 557 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 558 * @{
AnnaBridge 156:ff21514d8981 559 */
AnnaBridge 156:ff21514d8981 560 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
AnnaBridge 156:ff21514d8981 561 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
AnnaBridge 156:ff21514d8981 562 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
AnnaBridge 156:ff21514d8981 563 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
AnnaBridge 156:ff21514d8981 564
AnnaBridge 156:ff21514d8981 565 #define NAND_AddressTypedef NAND_AddressTypeDef
AnnaBridge 156:ff21514d8981 566
AnnaBridge 156:ff21514d8981 567 #define __ARRAY_ADDRESS ARRAY_ADDRESS
AnnaBridge 156:ff21514d8981 568 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
AnnaBridge 156:ff21514d8981 569 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
AnnaBridge 156:ff21514d8981 570 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
AnnaBridge 156:ff21514d8981 571 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
AnnaBridge 156:ff21514d8981 572 /**
AnnaBridge 156:ff21514d8981 573 * @}
AnnaBridge 156:ff21514d8981 574 */
AnnaBridge 156:ff21514d8981 575
AnnaBridge 156:ff21514d8981 576 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 577 * @{
AnnaBridge 156:ff21514d8981 578 */
AnnaBridge 156:ff21514d8981 579 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
AnnaBridge 156:ff21514d8981 580 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
AnnaBridge 156:ff21514d8981 581 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
AnnaBridge 156:ff21514d8981 582 #define NOR_ERROR HAL_NOR_STATUS_ERROR
AnnaBridge 156:ff21514d8981 583 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
AnnaBridge 156:ff21514d8981 584
AnnaBridge 156:ff21514d8981 585 #define __NOR_WRITE NOR_WRITE
AnnaBridge 156:ff21514d8981 586 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
AnnaBridge 156:ff21514d8981 587 /**
AnnaBridge 156:ff21514d8981 588 * @}
AnnaBridge 156:ff21514d8981 589 */
AnnaBridge 156:ff21514d8981 590
AnnaBridge 156:ff21514d8981 591 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 592 * @{
AnnaBridge 156:ff21514d8981 593 */
AnnaBridge 156:ff21514d8981 594
AnnaBridge 156:ff21514d8981 595 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
AnnaBridge 156:ff21514d8981 596 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
AnnaBridge 156:ff21514d8981 597 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
AnnaBridge 156:ff21514d8981 598 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
AnnaBridge 156:ff21514d8981 599
AnnaBridge 156:ff21514d8981 600 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
AnnaBridge 156:ff21514d8981 601 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
AnnaBridge 156:ff21514d8981 602 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
AnnaBridge 156:ff21514d8981 603 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
AnnaBridge 156:ff21514d8981 604
AnnaBridge 156:ff21514d8981 605 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
AnnaBridge 156:ff21514d8981 606 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
AnnaBridge 156:ff21514d8981 607
AnnaBridge 156:ff21514d8981 608 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
AnnaBridge 156:ff21514d8981 609 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
AnnaBridge 156:ff21514d8981 610
AnnaBridge 156:ff21514d8981 611 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
AnnaBridge 156:ff21514d8981 612 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
AnnaBridge 156:ff21514d8981 613
AnnaBridge 156:ff21514d8981 614 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
AnnaBridge 156:ff21514d8981 615
AnnaBridge 156:ff21514d8981 616 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
AnnaBridge 156:ff21514d8981 617 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
AnnaBridge 156:ff21514d8981 618 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
AnnaBridge 156:ff21514d8981 619
AnnaBridge 156:ff21514d8981 620 /**
AnnaBridge 156:ff21514d8981 621 * @}
AnnaBridge 156:ff21514d8981 622 */
AnnaBridge 156:ff21514d8981 623
AnnaBridge 156:ff21514d8981 624 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 625 * @{
AnnaBridge 156:ff21514d8981 626 */
AnnaBridge 156:ff21514d8981 627 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
AnnaBridge 156:ff21514d8981 628 #if defined(STM32F7)
AnnaBridge 156:ff21514d8981 629 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
AnnaBridge 156:ff21514d8981 630 #endif
AnnaBridge 156:ff21514d8981 631 /**
AnnaBridge 156:ff21514d8981 632 * @}
AnnaBridge 156:ff21514d8981 633 */
AnnaBridge 156:ff21514d8981 634
AnnaBridge 156:ff21514d8981 635 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 636 * @{
AnnaBridge 156:ff21514d8981 637 */
AnnaBridge 156:ff21514d8981 638
AnnaBridge 156:ff21514d8981 639 /* Compact Flash-ATA registers description */
AnnaBridge 156:ff21514d8981 640 #define CF_DATA ATA_DATA
AnnaBridge 156:ff21514d8981 641 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
AnnaBridge 156:ff21514d8981 642 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
AnnaBridge 156:ff21514d8981 643 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
AnnaBridge 156:ff21514d8981 644 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
AnnaBridge 156:ff21514d8981 645 #define CF_CARD_HEAD ATA_CARD_HEAD
AnnaBridge 156:ff21514d8981 646 #define CF_STATUS_CMD ATA_STATUS_CMD
AnnaBridge 156:ff21514d8981 647 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
AnnaBridge 156:ff21514d8981 648 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
AnnaBridge 156:ff21514d8981 649
AnnaBridge 156:ff21514d8981 650 /* Compact Flash-ATA commands */
AnnaBridge 156:ff21514d8981 651 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
AnnaBridge 156:ff21514d8981 652 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
AnnaBridge 156:ff21514d8981 653 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
AnnaBridge 156:ff21514d8981 654 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
AnnaBridge 156:ff21514d8981 655
AnnaBridge 156:ff21514d8981 656 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
AnnaBridge 156:ff21514d8981 657 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
AnnaBridge 156:ff21514d8981 658 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
AnnaBridge 156:ff21514d8981 659 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
AnnaBridge 156:ff21514d8981 660 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
AnnaBridge 156:ff21514d8981 661 /**
AnnaBridge 156:ff21514d8981 662 * @}
AnnaBridge 156:ff21514d8981 663 */
AnnaBridge 156:ff21514d8981 664
AnnaBridge 156:ff21514d8981 665 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 666 * @{
AnnaBridge 156:ff21514d8981 667 */
AnnaBridge 156:ff21514d8981 668
AnnaBridge 156:ff21514d8981 669 #define FORMAT_BIN RTC_FORMAT_BIN
AnnaBridge 156:ff21514d8981 670 #define FORMAT_BCD RTC_FORMAT_BCD
AnnaBridge 156:ff21514d8981 671
AnnaBridge 156:ff21514d8981 672 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
AnnaBridge 156:ff21514d8981 673 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
AnnaBridge 156:ff21514d8981 674 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
AnnaBridge 156:ff21514d8981 675 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
AnnaBridge 156:ff21514d8981 676 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
AnnaBridge 156:ff21514d8981 677
AnnaBridge 156:ff21514d8981 678 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
AnnaBridge 156:ff21514d8981 679 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
AnnaBridge 156:ff21514d8981 680 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
AnnaBridge 156:ff21514d8981 681 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
AnnaBridge 156:ff21514d8981 682 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
AnnaBridge 156:ff21514d8981 683 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
AnnaBridge 156:ff21514d8981 684 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
AnnaBridge 156:ff21514d8981 685 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
AnnaBridge 156:ff21514d8981 686
AnnaBridge 156:ff21514d8981 687 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
AnnaBridge 156:ff21514d8981 688 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
AnnaBridge 156:ff21514d8981 689 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
AnnaBridge 156:ff21514d8981 690 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
AnnaBridge 156:ff21514d8981 691
AnnaBridge 156:ff21514d8981 692 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
AnnaBridge 156:ff21514d8981 693 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
AnnaBridge 156:ff21514d8981 694 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
AnnaBridge 156:ff21514d8981 695
AnnaBridge 156:ff21514d8981 696 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
AnnaBridge 156:ff21514d8981 697 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
AnnaBridge 156:ff21514d8981 698 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
AnnaBridge 156:ff21514d8981 699
AnnaBridge 156:ff21514d8981 700 /**
AnnaBridge 156:ff21514d8981 701 * @}
AnnaBridge 156:ff21514d8981 702 */
AnnaBridge 156:ff21514d8981 703
AnnaBridge 156:ff21514d8981 704
AnnaBridge 156:ff21514d8981 705 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 706 * @{
AnnaBridge 156:ff21514d8981 707 */
AnnaBridge 156:ff21514d8981 708 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
AnnaBridge 156:ff21514d8981 709 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
AnnaBridge 156:ff21514d8981 710
AnnaBridge 156:ff21514d8981 711 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
AnnaBridge 156:ff21514d8981 712 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
AnnaBridge 156:ff21514d8981 713 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
AnnaBridge 156:ff21514d8981 714 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
AnnaBridge 156:ff21514d8981 715
AnnaBridge 156:ff21514d8981 716 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
AnnaBridge 156:ff21514d8981 717 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
AnnaBridge 156:ff21514d8981 718
AnnaBridge 156:ff21514d8981 719 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
AnnaBridge 156:ff21514d8981 720 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
AnnaBridge 156:ff21514d8981 721 /**
AnnaBridge 156:ff21514d8981 722 * @}
AnnaBridge 156:ff21514d8981 723 */
AnnaBridge 156:ff21514d8981 724
AnnaBridge 156:ff21514d8981 725
AnnaBridge 156:ff21514d8981 726 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 727 * @{
AnnaBridge 156:ff21514d8981 728 */
AnnaBridge 156:ff21514d8981 729 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
AnnaBridge 156:ff21514d8981 730 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
AnnaBridge 156:ff21514d8981 731 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
AnnaBridge 156:ff21514d8981 732 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
AnnaBridge 156:ff21514d8981 733 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
AnnaBridge 156:ff21514d8981 734 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
AnnaBridge 156:ff21514d8981 735 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
AnnaBridge 156:ff21514d8981 736 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
AnnaBridge 156:ff21514d8981 737 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
AnnaBridge 156:ff21514d8981 738 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
AnnaBridge 156:ff21514d8981 739 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
AnnaBridge 156:ff21514d8981 740 /**
AnnaBridge 156:ff21514d8981 741 * @}
AnnaBridge 156:ff21514d8981 742 */
AnnaBridge 156:ff21514d8981 743
AnnaBridge 156:ff21514d8981 744 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 745 * @{
AnnaBridge 156:ff21514d8981 746 */
AnnaBridge 156:ff21514d8981 747 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
AnnaBridge 156:ff21514d8981 748 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
AnnaBridge 156:ff21514d8981 749
AnnaBridge 156:ff21514d8981 750 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
AnnaBridge 156:ff21514d8981 751 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
AnnaBridge 156:ff21514d8981 752
AnnaBridge 156:ff21514d8981 753 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
AnnaBridge 156:ff21514d8981 754 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
AnnaBridge 156:ff21514d8981 755
AnnaBridge 156:ff21514d8981 756 /**
AnnaBridge 156:ff21514d8981 757 * @}
AnnaBridge 156:ff21514d8981 758 */
AnnaBridge 156:ff21514d8981 759
AnnaBridge 156:ff21514d8981 760 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 761 * @{
AnnaBridge 156:ff21514d8981 762 */
AnnaBridge 156:ff21514d8981 763 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
AnnaBridge 156:ff21514d8981 764 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
AnnaBridge 156:ff21514d8981 765
AnnaBridge 156:ff21514d8981 766 #define TIM_DMABase_CR1 TIM_DMABASE_CR1
AnnaBridge 156:ff21514d8981 767 #define TIM_DMABase_CR2 TIM_DMABASE_CR2
AnnaBridge 156:ff21514d8981 768 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
AnnaBridge 156:ff21514d8981 769 #define TIM_DMABase_DIER TIM_DMABASE_DIER
AnnaBridge 156:ff21514d8981 770 #define TIM_DMABase_SR TIM_DMABASE_SR
AnnaBridge 156:ff21514d8981 771 #define TIM_DMABase_EGR TIM_DMABASE_EGR
AnnaBridge 156:ff21514d8981 772 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
AnnaBridge 156:ff21514d8981 773 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
AnnaBridge 156:ff21514d8981 774 #define TIM_DMABase_CCER TIM_DMABASE_CCER
AnnaBridge 156:ff21514d8981 775 #define TIM_DMABase_CNT TIM_DMABASE_CNT
AnnaBridge 156:ff21514d8981 776 #define TIM_DMABase_PSC TIM_DMABASE_PSC
AnnaBridge 156:ff21514d8981 777 #define TIM_DMABase_ARR TIM_DMABASE_ARR
AnnaBridge 156:ff21514d8981 778 #define TIM_DMABase_RCR TIM_DMABASE_RCR
AnnaBridge 156:ff21514d8981 779 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
AnnaBridge 156:ff21514d8981 780 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
AnnaBridge 156:ff21514d8981 781 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
AnnaBridge 156:ff21514d8981 782 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
AnnaBridge 156:ff21514d8981 783 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
AnnaBridge 156:ff21514d8981 784 #define TIM_DMABase_DCR TIM_DMABASE_DCR
AnnaBridge 156:ff21514d8981 785 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
AnnaBridge 156:ff21514d8981 786 #define TIM_DMABase_OR1 TIM_DMABASE_OR1
AnnaBridge 156:ff21514d8981 787 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
AnnaBridge 156:ff21514d8981 788 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
AnnaBridge 156:ff21514d8981 789 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
AnnaBridge 156:ff21514d8981 790 #define TIM_DMABase_OR2 TIM_DMABASE_OR2
AnnaBridge 156:ff21514d8981 791 #define TIM_DMABase_OR3 TIM_DMABASE_OR3
AnnaBridge 156:ff21514d8981 792 #define TIM_DMABase_OR TIM_DMABASE_OR
AnnaBridge 156:ff21514d8981 793
AnnaBridge 156:ff21514d8981 794 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
AnnaBridge 156:ff21514d8981 795 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
AnnaBridge 156:ff21514d8981 796 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
AnnaBridge 156:ff21514d8981 797 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
AnnaBridge 156:ff21514d8981 798 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
AnnaBridge 156:ff21514d8981 799 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
AnnaBridge 156:ff21514d8981 800 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
AnnaBridge 156:ff21514d8981 801 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
AnnaBridge 156:ff21514d8981 802 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
AnnaBridge 156:ff21514d8981 803
AnnaBridge 156:ff21514d8981 804 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
AnnaBridge 156:ff21514d8981 805 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
AnnaBridge 156:ff21514d8981 806 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
AnnaBridge 156:ff21514d8981 807 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
AnnaBridge 156:ff21514d8981 808 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
AnnaBridge 156:ff21514d8981 809 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
AnnaBridge 156:ff21514d8981 810 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
AnnaBridge 156:ff21514d8981 811 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
AnnaBridge 156:ff21514d8981 812 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
AnnaBridge 156:ff21514d8981 813 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
AnnaBridge 156:ff21514d8981 814 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
AnnaBridge 156:ff21514d8981 815 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
AnnaBridge 156:ff21514d8981 816 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
AnnaBridge 156:ff21514d8981 817 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
AnnaBridge 156:ff21514d8981 818 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
AnnaBridge 156:ff21514d8981 819 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
AnnaBridge 156:ff21514d8981 820 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
AnnaBridge 156:ff21514d8981 821 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
AnnaBridge 156:ff21514d8981 822
AnnaBridge 156:ff21514d8981 823 /**
AnnaBridge 156:ff21514d8981 824 * @}
AnnaBridge 156:ff21514d8981 825 */
AnnaBridge 156:ff21514d8981 826
AnnaBridge 156:ff21514d8981 827 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 828 * @{
AnnaBridge 156:ff21514d8981 829 */
AnnaBridge 156:ff21514d8981 830 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
AnnaBridge 156:ff21514d8981 831 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
AnnaBridge 156:ff21514d8981 832 /**
AnnaBridge 156:ff21514d8981 833 * @}
AnnaBridge 156:ff21514d8981 834 */
AnnaBridge 156:ff21514d8981 835
AnnaBridge 156:ff21514d8981 836 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 837 * @{
AnnaBridge 156:ff21514d8981 838 */
AnnaBridge 156:ff21514d8981 839 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
AnnaBridge 156:ff21514d8981 840 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
AnnaBridge 156:ff21514d8981 841 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
AnnaBridge 156:ff21514d8981 842 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
AnnaBridge 156:ff21514d8981 843
AnnaBridge 156:ff21514d8981 844 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
AnnaBridge 156:ff21514d8981 845 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
AnnaBridge 156:ff21514d8981 846
AnnaBridge 156:ff21514d8981 847 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
AnnaBridge 156:ff21514d8981 848 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
AnnaBridge 156:ff21514d8981 849 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
AnnaBridge 156:ff21514d8981 850 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
AnnaBridge 156:ff21514d8981 851
AnnaBridge 156:ff21514d8981 852 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
AnnaBridge 156:ff21514d8981 853 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
AnnaBridge 156:ff21514d8981 854 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
AnnaBridge 156:ff21514d8981 855 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
AnnaBridge 156:ff21514d8981 856
AnnaBridge 156:ff21514d8981 857 #define __DIV_LPUART UART_DIV_LPUART
AnnaBridge 156:ff21514d8981 858
AnnaBridge 156:ff21514d8981 859 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
AnnaBridge 156:ff21514d8981 860 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
AnnaBridge 156:ff21514d8981 861
AnnaBridge 156:ff21514d8981 862 /**
AnnaBridge 156:ff21514d8981 863 * @}
AnnaBridge 156:ff21514d8981 864 */
AnnaBridge 156:ff21514d8981 865
AnnaBridge 156:ff21514d8981 866
AnnaBridge 156:ff21514d8981 867 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 868 * @{
AnnaBridge 156:ff21514d8981 869 */
AnnaBridge 156:ff21514d8981 870
AnnaBridge 156:ff21514d8981 871 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
AnnaBridge 156:ff21514d8981 872 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
AnnaBridge 156:ff21514d8981 873
AnnaBridge 156:ff21514d8981 874 #define USARTNACK_ENABLED USART_NACK_ENABLE
AnnaBridge 156:ff21514d8981 875 #define USARTNACK_DISABLED USART_NACK_DISABLE
AnnaBridge 156:ff21514d8981 876 /**
AnnaBridge 156:ff21514d8981 877 * @}
AnnaBridge 156:ff21514d8981 878 */
AnnaBridge 156:ff21514d8981 879
AnnaBridge 156:ff21514d8981 880 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 881 * @{
AnnaBridge 156:ff21514d8981 882 */
AnnaBridge 156:ff21514d8981 883 #define CFR_BASE WWDG_CFR_BASE
AnnaBridge 156:ff21514d8981 884
AnnaBridge 156:ff21514d8981 885 /**
AnnaBridge 156:ff21514d8981 886 * @}
AnnaBridge 156:ff21514d8981 887 */
AnnaBridge 156:ff21514d8981 888
AnnaBridge 156:ff21514d8981 889 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 890 * @{
AnnaBridge 156:ff21514d8981 891 */
AnnaBridge 156:ff21514d8981 892 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
AnnaBridge 156:ff21514d8981 893 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
AnnaBridge 156:ff21514d8981 894 #define CAN_IT_RQCP0 CAN_IT_TME
AnnaBridge 156:ff21514d8981 895 #define CAN_IT_RQCP1 CAN_IT_TME
AnnaBridge 156:ff21514d8981 896 #define CAN_IT_RQCP2 CAN_IT_TME
AnnaBridge 156:ff21514d8981 897 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
AnnaBridge 156:ff21514d8981 898 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
AnnaBridge 156:ff21514d8981 899 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
AnnaBridge 156:ff21514d8981 900 #define CAN_TXSTATUS_OK ((uint8_t)0x01U)
AnnaBridge 156:ff21514d8981 901 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
AnnaBridge 156:ff21514d8981 902
AnnaBridge 156:ff21514d8981 903 /**
AnnaBridge 156:ff21514d8981 904 * @}
AnnaBridge 156:ff21514d8981 905 */
AnnaBridge 156:ff21514d8981 906
AnnaBridge 156:ff21514d8981 907 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 908 * @{
AnnaBridge 156:ff21514d8981 909 */
AnnaBridge 156:ff21514d8981 910
AnnaBridge 156:ff21514d8981 911 #define VLAN_TAG ETH_VLAN_TAG
AnnaBridge 156:ff21514d8981 912 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
AnnaBridge 156:ff21514d8981 913 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
AnnaBridge 156:ff21514d8981 914 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
AnnaBridge 156:ff21514d8981 915 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
AnnaBridge 156:ff21514d8981 916 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
AnnaBridge 156:ff21514d8981 917 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
AnnaBridge 156:ff21514d8981 918 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
AnnaBridge 156:ff21514d8981 919
AnnaBridge 156:ff21514d8981 920 #define ETH_MMCCR ((uint32_t)0x00000100U)
AnnaBridge 156:ff21514d8981 921 #define ETH_MMCRIR ((uint32_t)0x00000104U)
AnnaBridge 156:ff21514d8981 922 #define ETH_MMCTIR ((uint32_t)0x00000108U)
AnnaBridge 156:ff21514d8981 923 #define ETH_MMCRIMR ((uint32_t)0x0000010CU)
AnnaBridge 156:ff21514d8981 924 #define ETH_MMCTIMR ((uint32_t)0x00000110U)
AnnaBridge 156:ff21514d8981 925 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
AnnaBridge 156:ff21514d8981 926 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
AnnaBridge 156:ff21514d8981 927 #define ETH_MMCTGFCR ((uint32_t)0x00000168U)
AnnaBridge 156:ff21514d8981 928 #define ETH_MMCRFCECR ((uint32_t)0x00000194U)
AnnaBridge 156:ff21514d8981 929 #define ETH_MMCRFAECR ((uint32_t)0x00000198U)
AnnaBridge 156:ff21514d8981 930 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
AnnaBridge 156:ff21514d8981 931
AnnaBridge 156:ff21514d8981 932 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
AnnaBridge 156:ff21514d8981 933 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
AnnaBridge 156:ff21514d8981 934 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
AnnaBridge 156:ff21514d8981 935 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
AnnaBridge 156:ff21514d8981 936 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
AnnaBridge 156:ff21514d8981 937 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
AnnaBridge 156:ff21514d8981 938 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
AnnaBridge 156:ff21514d8981 939 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
AnnaBridge 156:ff21514d8981 940 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
AnnaBridge 156:ff21514d8981 941 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
AnnaBridge 156:ff21514d8981 942 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
AnnaBridge 156:ff21514d8981 943 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
AnnaBridge 156:ff21514d8981 944 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
AnnaBridge 156:ff21514d8981 945 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
AnnaBridge 156:ff21514d8981 946 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
AnnaBridge 156:ff21514d8981 947 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
AnnaBridge 156:ff21514d8981 948 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
AnnaBridge 156:ff21514d8981 949 #if defined(STM32F1)
AnnaBridge 156:ff21514d8981 950 #else
AnnaBridge 156:ff21514d8981 951 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
AnnaBridge 156:ff21514d8981 952 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
AnnaBridge 156:ff21514d8981 953 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
AnnaBridge 156:ff21514d8981 954 #endif
AnnaBridge 156:ff21514d8981 955 #define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
AnnaBridge 156:ff21514d8981 956 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
AnnaBridge 156:ff21514d8981 957 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
AnnaBridge 156:ff21514d8981 958 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
AnnaBridge 156:ff21514d8981 959 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
AnnaBridge 156:ff21514d8981 960 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
AnnaBridge 156:ff21514d8981 961 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
AnnaBridge 156:ff21514d8981 962
AnnaBridge 156:ff21514d8981 963 /**
AnnaBridge 156:ff21514d8981 964 * @}
AnnaBridge 156:ff21514d8981 965 */
AnnaBridge 156:ff21514d8981 966
AnnaBridge 156:ff21514d8981 967 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 968 * @{
AnnaBridge 156:ff21514d8981 969 */
AnnaBridge 156:ff21514d8981 970 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
AnnaBridge 156:ff21514d8981 971 #define DCMI_IT_OVF DCMI_IT_OVR
AnnaBridge 156:ff21514d8981 972 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
AnnaBridge 156:ff21514d8981 973 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
AnnaBridge 156:ff21514d8981 974
AnnaBridge 156:ff21514d8981 975 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
AnnaBridge 156:ff21514d8981 976 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
AnnaBridge 156:ff21514d8981 977 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
AnnaBridge 156:ff21514d8981 978
AnnaBridge 156:ff21514d8981 979 /**
AnnaBridge 156:ff21514d8981 980 * @}
AnnaBridge 156:ff21514d8981 981 */
AnnaBridge 156:ff21514d8981 982
AnnaBridge 156:ff21514d8981 983 #if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
AnnaBridge 156:ff21514d8981 984 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
AnnaBridge 156:ff21514d8981 985 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 986 * @{
AnnaBridge 156:ff21514d8981 987 */
AnnaBridge 156:ff21514d8981 988 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
AnnaBridge 156:ff21514d8981 989 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
AnnaBridge 156:ff21514d8981 990 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
AnnaBridge 156:ff21514d8981 991 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
AnnaBridge 156:ff21514d8981 992 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
AnnaBridge 156:ff21514d8981 993
AnnaBridge 156:ff21514d8981 994 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888
AnnaBridge 156:ff21514d8981 995 #define CM_RGB888 DMA2D_INPUT_RGB888
AnnaBridge 156:ff21514d8981 996 #define CM_RGB565 DMA2D_INPUT_RGB565
AnnaBridge 156:ff21514d8981 997 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555
AnnaBridge 156:ff21514d8981 998 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444
AnnaBridge 156:ff21514d8981 999 #define CM_L8 DMA2D_INPUT_L8
AnnaBridge 156:ff21514d8981 1000 #define CM_AL44 DMA2D_INPUT_AL44
AnnaBridge 156:ff21514d8981 1001 #define CM_AL88 DMA2D_INPUT_AL88
AnnaBridge 156:ff21514d8981 1002 #define CM_L4 DMA2D_INPUT_L4
AnnaBridge 156:ff21514d8981 1003 #define CM_A8 DMA2D_INPUT_A8
AnnaBridge 156:ff21514d8981 1004 #define CM_A4 DMA2D_INPUT_A4
AnnaBridge 156:ff21514d8981 1005 /**
AnnaBridge 156:ff21514d8981 1006 * @}
AnnaBridge 156:ff21514d8981 1007 */
AnnaBridge 156:ff21514d8981 1008 #endif /* STM32L4xx || STM32F7*/
AnnaBridge 156:ff21514d8981 1009
AnnaBridge 156:ff21514d8981 1010 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1011 * @{
AnnaBridge 156:ff21514d8981 1012 */
AnnaBridge 156:ff21514d8981 1013
AnnaBridge 156:ff21514d8981 1014 /**
AnnaBridge 156:ff21514d8981 1015 * @}
AnnaBridge 156:ff21514d8981 1016 */
AnnaBridge 156:ff21514d8981 1017
AnnaBridge 156:ff21514d8981 1018 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1019
AnnaBridge 156:ff21514d8981 1020 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1021 * @{
AnnaBridge 156:ff21514d8981 1022 */
AnnaBridge 156:ff21514d8981 1023 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
AnnaBridge 156:ff21514d8981 1024 /**
AnnaBridge 156:ff21514d8981 1025 * @}
AnnaBridge 156:ff21514d8981 1026 */
AnnaBridge 156:ff21514d8981 1027
AnnaBridge 156:ff21514d8981 1028 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1029 * @{
AnnaBridge 156:ff21514d8981 1030 */
AnnaBridge 156:ff21514d8981 1031 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
AnnaBridge 156:ff21514d8981 1032 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
AnnaBridge 156:ff21514d8981 1033 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
AnnaBridge 156:ff21514d8981 1034 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
AnnaBridge 156:ff21514d8981 1035 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
AnnaBridge 156:ff21514d8981 1036 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
AnnaBridge 156:ff21514d8981 1037
AnnaBridge 156:ff21514d8981 1038 /*HASH Algorithm Selection*/
AnnaBridge 156:ff21514d8981 1039
AnnaBridge 156:ff21514d8981 1040 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
AnnaBridge 156:ff21514d8981 1041 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
AnnaBridge 156:ff21514d8981 1042 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
AnnaBridge 156:ff21514d8981 1043 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
AnnaBridge 156:ff21514d8981 1044
AnnaBridge 156:ff21514d8981 1045 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
AnnaBridge 156:ff21514d8981 1046 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
AnnaBridge 156:ff21514d8981 1047
AnnaBridge 156:ff21514d8981 1048 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
AnnaBridge 156:ff21514d8981 1049 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
AnnaBridge 156:ff21514d8981 1050 /**
AnnaBridge 156:ff21514d8981 1051 * @}
AnnaBridge 156:ff21514d8981 1052 */
AnnaBridge 156:ff21514d8981 1053
AnnaBridge 156:ff21514d8981 1054 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1055 * @{
AnnaBridge 156:ff21514d8981 1056 */
AnnaBridge 156:ff21514d8981 1057 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
AnnaBridge 156:ff21514d8981 1058 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
AnnaBridge 156:ff21514d8981 1059 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
AnnaBridge 156:ff21514d8981 1060 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
AnnaBridge 156:ff21514d8981 1061 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
AnnaBridge 156:ff21514d8981 1062 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
AnnaBridge 156:ff21514d8981 1063 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
AnnaBridge 156:ff21514d8981 1064 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
AnnaBridge 156:ff21514d8981 1065 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
AnnaBridge 156:ff21514d8981 1066 #if defined(STM32L0)
AnnaBridge 156:ff21514d8981 1067 #else
AnnaBridge 156:ff21514d8981 1068 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
AnnaBridge 156:ff21514d8981 1069 #endif
AnnaBridge 156:ff21514d8981 1070 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
AnnaBridge 156:ff21514d8981 1071 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
AnnaBridge 156:ff21514d8981 1072 /**
AnnaBridge 156:ff21514d8981 1073 * @}
AnnaBridge 156:ff21514d8981 1074 */
AnnaBridge 156:ff21514d8981 1075
AnnaBridge 156:ff21514d8981 1076 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1077 * @{
AnnaBridge 156:ff21514d8981 1078 */
AnnaBridge 156:ff21514d8981 1079 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
AnnaBridge 156:ff21514d8981 1080 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
AnnaBridge 156:ff21514d8981 1081 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
AnnaBridge 156:ff21514d8981 1082 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
AnnaBridge 156:ff21514d8981 1083 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
AnnaBridge 156:ff21514d8981 1084 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
AnnaBridge 156:ff21514d8981 1085 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
AnnaBridge 156:ff21514d8981 1086
AnnaBridge 156:ff21514d8981 1087 /**
AnnaBridge 156:ff21514d8981 1088 * @}
AnnaBridge 156:ff21514d8981 1089 */
AnnaBridge 156:ff21514d8981 1090
AnnaBridge 156:ff21514d8981 1091 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1092 * @{
AnnaBridge 156:ff21514d8981 1093 */
AnnaBridge 156:ff21514d8981 1094 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
AnnaBridge 156:ff21514d8981 1095 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
AnnaBridge 156:ff21514d8981 1096 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
AnnaBridge 156:ff21514d8981 1097 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
AnnaBridge 156:ff21514d8981 1098
AnnaBridge 156:ff21514d8981 1099 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
AnnaBridge 156:ff21514d8981 1100 /**
AnnaBridge 156:ff21514d8981 1101 * @}
AnnaBridge 156:ff21514d8981 1102 */
AnnaBridge 156:ff21514d8981 1103
AnnaBridge 156:ff21514d8981 1104 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1105 * @{
AnnaBridge 156:ff21514d8981 1106 */
AnnaBridge 156:ff21514d8981 1107 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
AnnaBridge 156:ff21514d8981 1108 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
AnnaBridge 156:ff21514d8981 1109 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
AnnaBridge 156:ff21514d8981 1110 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
AnnaBridge 156:ff21514d8981 1111 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
AnnaBridge 156:ff21514d8981 1112 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
AnnaBridge 156:ff21514d8981 1113 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
AnnaBridge 156:ff21514d8981 1114 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
AnnaBridge 156:ff21514d8981 1115 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
AnnaBridge 156:ff21514d8981 1116 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
AnnaBridge 156:ff21514d8981 1117 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
AnnaBridge 156:ff21514d8981 1118 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
AnnaBridge 156:ff21514d8981 1119 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
AnnaBridge 156:ff21514d8981 1120 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
AnnaBridge 156:ff21514d8981 1121 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
AnnaBridge 156:ff21514d8981 1122 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
AnnaBridge 156:ff21514d8981 1123
AnnaBridge 156:ff21514d8981 1124 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
AnnaBridge 156:ff21514d8981 1125 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
AnnaBridge 156:ff21514d8981 1126 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
AnnaBridge 156:ff21514d8981 1127 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
AnnaBridge 156:ff21514d8981 1128 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
AnnaBridge 156:ff21514d8981 1129 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
AnnaBridge 156:ff21514d8981 1130 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
AnnaBridge 156:ff21514d8981 1131
AnnaBridge 156:ff21514d8981 1132 #define CR_OFFSET_BB PWR_CR_OFFSET_BB
AnnaBridge 156:ff21514d8981 1133 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
AnnaBridge 156:ff21514d8981 1134
AnnaBridge 156:ff21514d8981 1135 #define DBP_BitNumber DBP_BIT_NUMBER
AnnaBridge 156:ff21514d8981 1136 #define PVDE_BitNumber PVDE_BIT_NUMBER
AnnaBridge 156:ff21514d8981 1137 #define PMODE_BitNumber PMODE_BIT_NUMBER
AnnaBridge 156:ff21514d8981 1138 #define EWUP_BitNumber EWUP_BIT_NUMBER
AnnaBridge 156:ff21514d8981 1139 #define FPDS_BitNumber FPDS_BIT_NUMBER
AnnaBridge 156:ff21514d8981 1140 #define ODEN_BitNumber ODEN_BIT_NUMBER
AnnaBridge 156:ff21514d8981 1141 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
AnnaBridge 156:ff21514d8981 1142 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
AnnaBridge 156:ff21514d8981 1143 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
AnnaBridge 156:ff21514d8981 1144 #define BRE_BitNumber BRE_BIT_NUMBER
AnnaBridge 156:ff21514d8981 1145
AnnaBridge 156:ff21514d8981 1146 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
AnnaBridge 156:ff21514d8981 1147
AnnaBridge 156:ff21514d8981 1148 /**
AnnaBridge 156:ff21514d8981 1149 * @}
AnnaBridge 156:ff21514d8981 1150 */
AnnaBridge 156:ff21514d8981 1151
AnnaBridge 156:ff21514d8981 1152 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1153 * @{
AnnaBridge 156:ff21514d8981 1154 */
AnnaBridge 156:ff21514d8981 1155 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
AnnaBridge 156:ff21514d8981 1156 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
AnnaBridge 156:ff21514d8981 1157 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
AnnaBridge 156:ff21514d8981 1158 /**
AnnaBridge 156:ff21514d8981 1159 * @}
AnnaBridge 156:ff21514d8981 1160 */
AnnaBridge 156:ff21514d8981 1161
AnnaBridge 156:ff21514d8981 1162 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1163 * @{
AnnaBridge 156:ff21514d8981 1164 */
AnnaBridge 156:ff21514d8981 1165 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
AnnaBridge 156:ff21514d8981 1166 /**
AnnaBridge 156:ff21514d8981 1167 * @}
AnnaBridge 156:ff21514d8981 1168 */
AnnaBridge 156:ff21514d8981 1169
AnnaBridge 156:ff21514d8981 1170 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1171 * @{
AnnaBridge 156:ff21514d8981 1172 */
AnnaBridge 156:ff21514d8981 1173 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
AnnaBridge 156:ff21514d8981 1174 #define HAL_TIM_DMAError TIM_DMAError
AnnaBridge 156:ff21514d8981 1175 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
AnnaBridge 156:ff21514d8981 1176 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
AnnaBridge 156:ff21514d8981 1177 /**
AnnaBridge 156:ff21514d8981 1178 * @}
AnnaBridge 156:ff21514d8981 1179 */
AnnaBridge 156:ff21514d8981 1180
AnnaBridge 156:ff21514d8981 1181 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1182 * @{
AnnaBridge 156:ff21514d8981 1183 */
AnnaBridge 156:ff21514d8981 1184 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
AnnaBridge 156:ff21514d8981 1185 /**
AnnaBridge 156:ff21514d8981 1186 * @}
AnnaBridge 156:ff21514d8981 1187 */
AnnaBridge 156:ff21514d8981 1188
AnnaBridge 156:ff21514d8981 1189 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1190 * @{
AnnaBridge 156:ff21514d8981 1191 */
AnnaBridge 156:ff21514d8981 1192 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
AnnaBridge 156:ff21514d8981 1193 /**
AnnaBridge 156:ff21514d8981 1194 * @}
AnnaBridge 156:ff21514d8981 1195 */
AnnaBridge 156:ff21514d8981 1196
AnnaBridge 156:ff21514d8981 1197
AnnaBridge 156:ff21514d8981 1198 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1199 * @{
AnnaBridge 156:ff21514d8981 1200 */
AnnaBridge 156:ff21514d8981 1201
AnnaBridge 156:ff21514d8981 1202 /**
AnnaBridge 156:ff21514d8981 1203 * @}
AnnaBridge 156:ff21514d8981 1204 */
AnnaBridge 156:ff21514d8981 1205
AnnaBridge 156:ff21514d8981 1206 /* Exported macros ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1207
AnnaBridge 156:ff21514d8981 1208 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1209 * @{
AnnaBridge 156:ff21514d8981 1210 */
AnnaBridge 156:ff21514d8981 1211 #define AES_IT_CC CRYP_IT_CC
AnnaBridge 156:ff21514d8981 1212 #define AES_IT_ERR CRYP_IT_ERR
AnnaBridge 156:ff21514d8981 1213 #define AES_FLAG_CCF CRYP_FLAG_CCF
AnnaBridge 156:ff21514d8981 1214 /**
AnnaBridge 156:ff21514d8981 1215 * @}
AnnaBridge 156:ff21514d8981 1216 */
AnnaBridge 156:ff21514d8981 1217
AnnaBridge 156:ff21514d8981 1218 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1219 * @{
AnnaBridge 156:ff21514d8981 1220 */
AnnaBridge 156:ff21514d8981 1221 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
AnnaBridge 156:ff21514d8981 1222 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
AnnaBridge 156:ff21514d8981 1223 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
AnnaBridge 156:ff21514d8981 1224 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
AnnaBridge 156:ff21514d8981 1225 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
AnnaBridge 156:ff21514d8981 1226 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
AnnaBridge 156:ff21514d8981 1227 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
AnnaBridge 156:ff21514d8981 1228 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
AnnaBridge 156:ff21514d8981 1229 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
AnnaBridge 156:ff21514d8981 1230 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
AnnaBridge 156:ff21514d8981 1231 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
AnnaBridge 156:ff21514d8981 1232 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
AnnaBridge 156:ff21514d8981 1233 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
AnnaBridge 156:ff21514d8981 1234
AnnaBridge 156:ff21514d8981 1235 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
AnnaBridge 156:ff21514d8981 1236 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
AnnaBridge 156:ff21514d8981 1237 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
AnnaBridge 156:ff21514d8981 1238 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
AnnaBridge 156:ff21514d8981 1239 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
AnnaBridge 156:ff21514d8981 1240
AnnaBridge 156:ff21514d8981 1241 /**
AnnaBridge 156:ff21514d8981 1242 * @}
AnnaBridge 156:ff21514d8981 1243 */
AnnaBridge 156:ff21514d8981 1244
AnnaBridge 156:ff21514d8981 1245
AnnaBridge 156:ff21514d8981 1246 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1247 * @{
AnnaBridge 156:ff21514d8981 1248 */
AnnaBridge 156:ff21514d8981 1249 #define __ADC_ENABLE __HAL_ADC_ENABLE
AnnaBridge 156:ff21514d8981 1250 #define __ADC_DISABLE __HAL_ADC_DISABLE
AnnaBridge 156:ff21514d8981 1251 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
AnnaBridge 156:ff21514d8981 1252 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
AnnaBridge 156:ff21514d8981 1253 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
AnnaBridge 156:ff21514d8981 1254 #define __ADC_IS_ENABLED ADC_IS_ENABLE
AnnaBridge 156:ff21514d8981 1255 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
AnnaBridge 156:ff21514d8981 1256 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
AnnaBridge 156:ff21514d8981 1257 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
AnnaBridge 156:ff21514d8981 1258 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
AnnaBridge 156:ff21514d8981 1259 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
AnnaBridge 156:ff21514d8981 1260 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
AnnaBridge 156:ff21514d8981 1261 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
AnnaBridge 156:ff21514d8981 1262
AnnaBridge 156:ff21514d8981 1263 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
AnnaBridge 156:ff21514d8981 1264 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
AnnaBridge 156:ff21514d8981 1265 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
AnnaBridge 156:ff21514d8981 1266 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
AnnaBridge 156:ff21514d8981 1267 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
AnnaBridge 156:ff21514d8981 1268 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
AnnaBridge 156:ff21514d8981 1269 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
AnnaBridge 156:ff21514d8981 1270 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
AnnaBridge 156:ff21514d8981 1271 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
AnnaBridge 156:ff21514d8981 1272 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
AnnaBridge 156:ff21514d8981 1273 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
AnnaBridge 156:ff21514d8981 1274 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
AnnaBridge 156:ff21514d8981 1275 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
AnnaBridge 156:ff21514d8981 1276 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
AnnaBridge 156:ff21514d8981 1277 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
AnnaBridge 156:ff21514d8981 1278 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
AnnaBridge 156:ff21514d8981 1279 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
AnnaBridge 156:ff21514d8981 1280 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
AnnaBridge 156:ff21514d8981 1281 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
AnnaBridge 156:ff21514d8981 1282 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
AnnaBridge 156:ff21514d8981 1283
AnnaBridge 156:ff21514d8981 1284 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
AnnaBridge 156:ff21514d8981 1285 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
AnnaBridge 156:ff21514d8981 1286 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
AnnaBridge 156:ff21514d8981 1287 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
AnnaBridge 156:ff21514d8981 1288 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
AnnaBridge 156:ff21514d8981 1289 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
AnnaBridge 156:ff21514d8981 1290 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
AnnaBridge 156:ff21514d8981 1291 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
AnnaBridge 156:ff21514d8981 1292 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
AnnaBridge 156:ff21514d8981 1293 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
AnnaBridge 156:ff21514d8981 1294
AnnaBridge 156:ff21514d8981 1295 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
AnnaBridge 156:ff21514d8981 1296 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
AnnaBridge 156:ff21514d8981 1297 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
AnnaBridge 156:ff21514d8981 1298 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
AnnaBridge 156:ff21514d8981 1299 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
AnnaBridge 156:ff21514d8981 1300 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
AnnaBridge 156:ff21514d8981 1301 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
AnnaBridge 156:ff21514d8981 1302 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
AnnaBridge 156:ff21514d8981 1303
AnnaBridge 156:ff21514d8981 1304 #define __HAL_ADC_SQR1 ADC_SQR1
AnnaBridge 156:ff21514d8981 1305 #define __HAL_ADC_SMPR1 ADC_SMPR1
AnnaBridge 156:ff21514d8981 1306 #define __HAL_ADC_SMPR2 ADC_SMPR2
AnnaBridge 156:ff21514d8981 1307 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
AnnaBridge 156:ff21514d8981 1308 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
AnnaBridge 156:ff21514d8981 1309 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
AnnaBridge 156:ff21514d8981 1310 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
AnnaBridge 156:ff21514d8981 1311 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
AnnaBridge 156:ff21514d8981 1312 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
AnnaBridge 156:ff21514d8981 1313 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
AnnaBridge 156:ff21514d8981 1314 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
AnnaBridge 156:ff21514d8981 1315 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
AnnaBridge 156:ff21514d8981 1316 #define __HAL_ADC_JSQR ADC_JSQR
AnnaBridge 156:ff21514d8981 1317
AnnaBridge 156:ff21514d8981 1318 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
AnnaBridge 156:ff21514d8981 1319 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
AnnaBridge 156:ff21514d8981 1320 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
AnnaBridge 156:ff21514d8981 1321 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
AnnaBridge 156:ff21514d8981 1322 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
AnnaBridge 156:ff21514d8981 1323 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
AnnaBridge 156:ff21514d8981 1324 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
AnnaBridge 156:ff21514d8981 1325 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
AnnaBridge 156:ff21514d8981 1326
AnnaBridge 156:ff21514d8981 1327 /**
AnnaBridge 156:ff21514d8981 1328 * @}
AnnaBridge 156:ff21514d8981 1329 */
AnnaBridge 156:ff21514d8981 1330
AnnaBridge 156:ff21514d8981 1331 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1332 * @{
AnnaBridge 156:ff21514d8981 1333 */
AnnaBridge 156:ff21514d8981 1334 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
AnnaBridge 156:ff21514d8981 1335 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
AnnaBridge 156:ff21514d8981 1336 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
AnnaBridge 156:ff21514d8981 1337 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
AnnaBridge 156:ff21514d8981 1338
AnnaBridge 156:ff21514d8981 1339 /**
AnnaBridge 156:ff21514d8981 1340 * @}
AnnaBridge 156:ff21514d8981 1341 */
AnnaBridge 156:ff21514d8981 1342
AnnaBridge 156:ff21514d8981 1343 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1344 * @{
AnnaBridge 156:ff21514d8981 1345 */
AnnaBridge 156:ff21514d8981 1346 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
AnnaBridge 156:ff21514d8981 1347 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
AnnaBridge 156:ff21514d8981 1348 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
AnnaBridge 156:ff21514d8981 1349 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
AnnaBridge 156:ff21514d8981 1350 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
AnnaBridge 156:ff21514d8981 1351 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
AnnaBridge 156:ff21514d8981 1352 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
AnnaBridge 156:ff21514d8981 1353 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
AnnaBridge 156:ff21514d8981 1354 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
AnnaBridge 156:ff21514d8981 1355 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
AnnaBridge 156:ff21514d8981 1356 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
AnnaBridge 156:ff21514d8981 1357 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
AnnaBridge 156:ff21514d8981 1358 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
AnnaBridge 156:ff21514d8981 1359 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
AnnaBridge 156:ff21514d8981 1360 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
AnnaBridge 156:ff21514d8981 1361 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
AnnaBridge 156:ff21514d8981 1362
AnnaBridge 156:ff21514d8981 1363 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
AnnaBridge 156:ff21514d8981 1364 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
AnnaBridge 156:ff21514d8981 1365 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
AnnaBridge 156:ff21514d8981 1366 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
AnnaBridge 156:ff21514d8981 1367 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
AnnaBridge 156:ff21514d8981 1368 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
AnnaBridge 156:ff21514d8981 1369 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
AnnaBridge 156:ff21514d8981 1370 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
AnnaBridge 156:ff21514d8981 1371 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
AnnaBridge 156:ff21514d8981 1372 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
AnnaBridge 156:ff21514d8981 1373 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
AnnaBridge 156:ff21514d8981 1374 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
AnnaBridge 156:ff21514d8981 1375 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
AnnaBridge 156:ff21514d8981 1376 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
AnnaBridge 156:ff21514d8981 1377
AnnaBridge 156:ff21514d8981 1378
AnnaBridge 156:ff21514d8981 1379 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
AnnaBridge 156:ff21514d8981 1380 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
AnnaBridge 156:ff21514d8981 1381 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
AnnaBridge 156:ff21514d8981 1382 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
AnnaBridge 156:ff21514d8981 1383 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
AnnaBridge 156:ff21514d8981 1384 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
AnnaBridge 156:ff21514d8981 1385 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
AnnaBridge 156:ff21514d8981 1386 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
AnnaBridge 156:ff21514d8981 1387 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
AnnaBridge 156:ff21514d8981 1388 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
AnnaBridge 156:ff21514d8981 1389 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
AnnaBridge 156:ff21514d8981 1390 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
AnnaBridge 156:ff21514d8981 1391 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
AnnaBridge 156:ff21514d8981 1392 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
AnnaBridge 156:ff21514d8981 1393 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
AnnaBridge 156:ff21514d8981 1394 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
AnnaBridge 156:ff21514d8981 1395 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
AnnaBridge 156:ff21514d8981 1396 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
AnnaBridge 156:ff21514d8981 1397 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
AnnaBridge 156:ff21514d8981 1398 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
AnnaBridge 156:ff21514d8981 1399 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
AnnaBridge 156:ff21514d8981 1400 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
AnnaBridge 156:ff21514d8981 1401 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
AnnaBridge 156:ff21514d8981 1402 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
AnnaBridge 156:ff21514d8981 1403
AnnaBridge 156:ff21514d8981 1404 /**
AnnaBridge 156:ff21514d8981 1405 * @}
AnnaBridge 156:ff21514d8981 1406 */
AnnaBridge 156:ff21514d8981 1407
AnnaBridge 156:ff21514d8981 1408 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1409 * @{
AnnaBridge 156:ff21514d8981 1410 */
AnnaBridge 156:ff21514d8981 1411 #if defined(STM32F3)
AnnaBridge 156:ff21514d8981 1412 #define COMP_START __HAL_COMP_ENABLE
AnnaBridge 156:ff21514d8981 1413 #define COMP_STOP __HAL_COMP_DISABLE
AnnaBridge 156:ff21514d8981 1414 #define COMP_LOCK __HAL_COMP_LOCK
AnnaBridge 156:ff21514d8981 1415
AnnaBridge 156:ff21514d8981 1416 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
AnnaBridge 156:ff21514d8981 1417 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1418 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1419 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
AnnaBridge 156:ff21514d8981 1420 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1421 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1422 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
AnnaBridge 156:ff21514d8981 1423 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1424 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1425 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge 156:ff21514d8981 1426 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1427 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1428 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge 156:ff21514d8981 1429 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1430 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1431 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
AnnaBridge 156:ff21514d8981 1432 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1433 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1434 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
AnnaBridge 156:ff21514d8981 1435 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1436 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1437 __HAL_COMP_COMP6_EXTI_GET_FLAG())
AnnaBridge 156:ff21514d8981 1438 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1439 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1440 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
AnnaBridge 156:ff21514d8981 1441 # endif
AnnaBridge 156:ff21514d8981 1442 # if defined(STM32F302xE) || defined(STM32F302xC)
AnnaBridge 156:ff21514d8981 1443 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1444 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1445 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1446 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
AnnaBridge 156:ff21514d8981 1447 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1448 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1449 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1450 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
AnnaBridge 156:ff21514d8981 1451 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1452 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1453 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1454 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge 156:ff21514d8981 1455 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1456 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1457 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1458 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge 156:ff21514d8981 1459 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1460 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1461 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1462 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
AnnaBridge 156:ff21514d8981 1463 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1464 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1465 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1466 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
AnnaBridge 156:ff21514d8981 1467 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1468 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1469 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1470 __HAL_COMP_COMP6_EXTI_GET_FLAG())
AnnaBridge 156:ff21514d8981 1471 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1472 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1473 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1474 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
AnnaBridge 156:ff21514d8981 1475 # endif
AnnaBridge 156:ff21514d8981 1476 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 156:ff21514d8981 1477 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1478 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1479 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1480 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1481 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1482 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1483 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
AnnaBridge 156:ff21514d8981 1484 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1485 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1486 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1487 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1488 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1489 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1490 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
AnnaBridge 156:ff21514d8981 1491 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1492 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1493 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1494 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1495 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1496 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1497 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge 156:ff21514d8981 1498 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1499 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1500 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1501 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1502 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1503 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1504 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge 156:ff21514d8981 1505 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1506 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1507 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1508 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1509 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1510 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1511 __HAL_COMP_COMP7_EXTI_ENABLE_IT())
AnnaBridge 156:ff21514d8981 1512 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1513 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1514 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1515 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1516 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1517 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1518 __HAL_COMP_COMP7_EXTI_DISABLE_IT())
AnnaBridge 156:ff21514d8981 1519 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1520 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1521 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1522 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1523 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1524 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1525 __HAL_COMP_COMP7_EXTI_GET_FLAG())
AnnaBridge 156:ff21514d8981 1526 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1527 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1528 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1529 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1530 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1531 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1532 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
AnnaBridge 156:ff21514d8981 1533 # endif
AnnaBridge 156:ff21514d8981 1534 # if defined(STM32F373xC) ||defined(STM32F378xx)
AnnaBridge 156:ff21514d8981 1535 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1536 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
AnnaBridge 156:ff21514d8981 1537 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1538 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
AnnaBridge 156:ff21514d8981 1539 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1540 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge 156:ff21514d8981 1541 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1542 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge 156:ff21514d8981 1543 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1544 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
AnnaBridge 156:ff21514d8981 1545 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1546 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
AnnaBridge 156:ff21514d8981 1547 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1548 __HAL_COMP_COMP2_EXTI_GET_FLAG())
AnnaBridge 156:ff21514d8981 1549 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1550 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
AnnaBridge 156:ff21514d8981 1551 # endif
AnnaBridge 156:ff21514d8981 1552 #else
AnnaBridge 156:ff21514d8981 1553 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1554 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
AnnaBridge 156:ff21514d8981 1555 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge 156:ff21514d8981 1556 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
AnnaBridge 156:ff21514d8981 1557 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1558 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge 156:ff21514d8981 1559 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge 156:ff21514d8981 1560 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge 156:ff21514d8981 1561 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 1562 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
AnnaBridge 156:ff21514d8981 1563 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 1564 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
AnnaBridge 156:ff21514d8981 1565 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 1566 __HAL_COMP_COMP2_EXTI_GET_FLAG())
AnnaBridge 156:ff21514d8981 1567 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 1568 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
AnnaBridge 156:ff21514d8981 1569 #endif
AnnaBridge 156:ff21514d8981 1570
AnnaBridge 156:ff21514d8981 1571 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
AnnaBridge 156:ff21514d8981 1572
AnnaBridge 156:ff21514d8981 1573 #if defined(STM32L0) || defined(STM32L4)
AnnaBridge 156:ff21514d8981 1574 /* Note: On these STM32 families, the only argument of this macro */
AnnaBridge 156:ff21514d8981 1575 /* is COMP_FLAG_LOCK. */
AnnaBridge 156:ff21514d8981 1576 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
AnnaBridge 156:ff21514d8981 1577 /* argument. */
AnnaBridge 156:ff21514d8981 1578 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
AnnaBridge 156:ff21514d8981 1579 #endif
AnnaBridge 156:ff21514d8981 1580 /**
AnnaBridge 156:ff21514d8981 1581 * @}
AnnaBridge 156:ff21514d8981 1582 */
AnnaBridge 156:ff21514d8981 1583
AnnaBridge 156:ff21514d8981 1584 #if defined(STM32L0) || defined(STM32L4)
AnnaBridge 156:ff21514d8981 1585 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1586 * @{
AnnaBridge 156:ff21514d8981 1587 */
AnnaBridge 156:ff21514d8981 1588 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
AnnaBridge 156:ff21514d8981 1589 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
AnnaBridge 156:ff21514d8981 1590 /**
AnnaBridge 156:ff21514d8981 1591 * @}
AnnaBridge 156:ff21514d8981 1592 */
AnnaBridge 156:ff21514d8981 1593 #endif
AnnaBridge 156:ff21514d8981 1594
AnnaBridge 156:ff21514d8981 1595 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1596 * @{
AnnaBridge 156:ff21514d8981 1597 */
AnnaBridge 156:ff21514d8981 1598
AnnaBridge 156:ff21514d8981 1599 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
AnnaBridge 156:ff21514d8981 1600 ((WAVE) == DAC_WAVE_NOISE)|| \
AnnaBridge 156:ff21514d8981 1601 ((WAVE) == DAC_WAVE_TRIANGLE))
AnnaBridge 156:ff21514d8981 1602
AnnaBridge 156:ff21514d8981 1603 /**
AnnaBridge 156:ff21514d8981 1604 * @}
AnnaBridge 156:ff21514d8981 1605 */
AnnaBridge 156:ff21514d8981 1606
AnnaBridge 156:ff21514d8981 1607 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1608 * @{
AnnaBridge 156:ff21514d8981 1609 */
AnnaBridge 156:ff21514d8981 1610
AnnaBridge 156:ff21514d8981 1611 #define IS_WRPAREA IS_OB_WRPAREA
AnnaBridge 156:ff21514d8981 1612 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
AnnaBridge 156:ff21514d8981 1613 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
AnnaBridge 156:ff21514d8981 1614 #define IS_TYPEERASE IS_FLASH_TYPEERASE
AnnaBridge 156:ff21514d8981 1615 #define IS_NBSECTORS IS_FLASH_NBSECTORS
AnnaBridge 156:ff21514d8981 1616 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
AnnaBridge 156:ff21514d8981 1617
AnnaBridge 156:ff21514d8981 1618 /**
AnnaBridge 156:ff21514d8981 1619 * @}
AnnaBridge 156:ff21514d8981 1620 */
AnnaBridge 156:ff21514d8981 1621
AnnaBridge 156:ff21514d8981 1622 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1623 * @{
AnnaBridge 156:ff21514d8981 1624 */
AnnaBridge 156:ff21514d8981 1625
AnnaBridge 156:ff21514d8981 1626 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
AnnaBridge 156:ff21514d8981 1627 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
AnnaBridge 156:ff21514d8981 1628 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
AnnaBridge 156:ff21514d8981 1629 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
AnnaBridge 156:ff21514d8981 1630 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
AnnaBridge 156:ff21514d8981 1631 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
AnnaBridge 156:ff21514d8981 1632 #define __HAL_I2C_SPEED I2C_SPEED
AnnaBridge 156:ff21514d8981 1633 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
AnnaBridge 156:ff21514d8981 1634 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
AnnaBridge 156:ff21514d8981 1635 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
AnnaBridge 156:ff21514d8981 1636 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
AnnaBridge 156:ff21514d8981 1637 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
AnnaBridge 156:ff21514d8981 1638 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
AnnaBridge 156:ff21514d8981 1639 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
AnnaBridge 156:ff21514d8981 1640 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
AnnaBridge 156:ff21514d8981 1641 /**
AnnaBridge 156:ff21514d8981 1642 * @}
AnnaBridge 156:ff21514d8981 1643 */
AnnaBridge 156:ff21514d8981 1644
AnnaBridge 156:ff21514d8981 1645 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1646 * @{
AnnaBridge 156:ff21514d8981 1647 */
AnnaBridge 156:ff21514d8981 1648
AnnaBridge 156:ff21514d8981 1649 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
AnnaBridge 156:ff21514d8981 1650 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
AnnaBridge 156:ff21514d8981 1651
AnnaBridge 156:ff21514d8981 1652 /**
AnnaBridge 156:ff21514d8981 1653 * @}
AnnaBridge 156:ff21514d8981 1654 */
AnnaBridge 156:ff21514d8981 1655
AnnaBridge 156:ff21514d8981 1656 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1657 * @{
AnnaBridge 156:ff21514d8981 1658 */
AnnaBridge 156:ff21514d8981 1659
AnnaBridge 156:ff21514d8981 1660 #define __IRDA_DISABLE __HAL_IRDA_DISABLE
AnnaBridge 156:ff21514d8981 1661 #define __IRDA_ENABLE __HAL_IRDA_ENABLE
AnnaBridge 156:ff21514d8981 1662
AnnaBridge 156:ff21514d8981 1663 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
AnnaBridge 156:ff21514d8981 1664 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
AnnaBridge 156:ff21514d8981 1665 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
AnnaBridge 156:ff21514d8981 1666 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
AnnaBridge 156:ff21514d8981 1667
AnnaBridge 156:ff21514d8981 1668 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
AnnaBridge 156:ff21514d8981 1669
AnnaBridge 156:ff21514d8981 1670
AnnaBridge 156:ff21514d8981 1671 /**
AnnaBridge 156:ff21514d8981 1672 * @}
AnnaBridge 156:ff21514d8981 1673 */
AnnaBridge 156:ff21514d8981 1674
AnnaBridge 156:ff21514d8981 1675
AnnaBridge 156:ff21514d8981 1676 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1677 * @{
AnnaBridge 156:ff21514d8981 1678 */
AnnaBridge 156:ff21514d8981 1679 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
AnnaBridge 156:ff21514d8981 1680 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
AnnaBridge 156:ff21514d8981 1681 /**
AnnaBridge 156:ff21514d8981 1682 * @}
AnnaBridge 156:ff21514d8981 1683 */
AnnaBridge 156:ff21514d8981 1684
AnnaBridge 156:ff21514d8981 1685
AnnaBridge 156:ff21514d8981 1686 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1687 * @{
AnnaBridge 156:ff21514d8981 1688 */
AnnaBridge 156:ff21514d8981 1689
AnnaBridge 156:ff21514d8981 1690 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
AnnaBridge 156:ff21514d8981 1691 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
AnnaBridge 156:ff21514d8981 1692 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
AnnaBridge 156:ff21514d8981 1693
AnnaBridge 156:ff21514d8981 1694 /**
AnnaBridge 156:ff21514d8981 1695 * @}
AnnaBridge 156:ff21514d8981 1696 */
AnnaBridge 156:ff21514d8981 1697
AnnaBridge 156:ff21514d8981 1698
AnnaBridge 156:ff21514d8981 1699 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1700 * @{
AnnaBridge 156:ff21514d8981 1701 */
AnnaBridge 156:ff21514d8981 1702 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
AnnaBridge 156:ff21514d8981 1703 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
AnnaBridge 156:ff21514d8981 1704 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
AnnaBridge 156:ff21514d8981 1705 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
AnnaBridge 156:ff21514d8981 1706 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
AnnaBridge 156:ff21514d8981 1707 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
AnnaBridge 156:ff21514d8981 1708 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
AnnaBridge 156:ff21514d8981 1709 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
AnnaBridge 156:ff21514d8981 1710 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
AnnaBridge 156:ff21514d8981 1711 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
AnnaBridge 156:ff21514d8981 1712 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
AnnaBridge 156:ff21514d8981 1713 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
AnnaBridge 156:ff21514d8981 1714 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
AnnaBridge 156:ff21514d8981 1715
AnnaBridge 156:ff21514d8981 1716 /**
AnnaBridge 156:ff21514d8981 1717 * @}
AnnaBridge 156:ff21514d8981 1718 */
AnnaBridge 156:ff21514d8981 1719
AnnaBridge 156:ff21514d8981 1720
AnnaBridge 156:ff21514d8981 1721 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1722 * @{
AnnaBridge 156:ff21514d8981 1723 */
AnnaBridge 156:ff21514d8981 1724 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
AnnaBridge 156:ff21514d8981 1725 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
AnnaBridge 156:ff21514d8981 1726 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
AnnaBridge 156:ff21514d8981 1727 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 156:ff21514d8981 1728 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
AnnaBridge 156:ff21514d8981 1729 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
AnnaBridge 156:ff21514d8981 1730 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
AnnaBridge 156:ff21514d8981 1731 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
AnnaBridge 156:ff21514d8981 1732 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
AnnaBridge 156:ff21514d8981 1733 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
AnnaBridge 156:ff21514d8981 1734 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
AnnaBridge 156:ff21514d8981 1735 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
AnnaBridge 156:ff21514d8981 1736 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
AnnaBridge 156:ff21514d8981 1737 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
AnnaBridge 156:ff21514d8981 1738 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
AnnaBridge 156:ff21514d8981 1739 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
AnnaBridge 156:ff21514d8981 1740 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
AnnaBridge 156:ff21514d8981 1741 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
AnnaBridge 156:ff21514d8981 1742 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
AnnaBridge 156:ff21514d8981 1743 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
AnnaBridge 156:ff21514d8981 1744 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 156:ff21514d8981 1745 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
AnnaBridge 156:ff21514d8981 1746 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
AnnaBridge 156:ff21514d8981 1747 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 156:ff21514d8981 1748 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
AnnaBridge 156:ff21514d8981 1749 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
AnnaBridge 156:ff21514d8981 1750 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
AnnaBridge 156:ff21514d8981 1751 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
AnnaBridge 156:ff21514d8981 1752 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
AnnaBridge 156:ff21514d8981 1753 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
AnnaBridge 156:ff21514d8981 1754 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
AnnaBridge 156:ff21514d8981 1755 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
AnnaBridge 156:ff21514d8981 1756 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 156:ff21514d8981 1757 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
AnnaBridge 156:ff21514d8981 1758 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
AnnaBridge 156:ff21514d8981 1759
AnnaBridge 156:ff21514d8981 1760 #if defined (STM32F4)
AnnaBridge 156:ff21514d8981 1761 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
AnnaBridge 156:ff21514d8981 1762 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
AnnaBridge 156:ff21514d8981 1763 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
AnnaBridge 156:ff21514d8981 1764 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
AnnaBridge 156:ff21514d8981 1765 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
AnnaBridge 156:ff21514d8981 1766 #else
AnnaBridge 156:ff21514d8981 1767 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
AnnaBridge 156:ff21514d8981 1768 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
AnnaBridge 156:ff21514d8981 1769 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
AnnaBridge 156:ff21514d8981 1770 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
AnnaBridge 156:ff21514d8981 1771 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
AnnaBridge 156:ff21514d8981 1772 #endif /* STM32F4 */
AnnaBridge 156:ff21514d8981 1773 /**
AnnaBridge 156:ff21514d8981 1774 * @}
AnnaBridge 156:ff21514d8981 1775 */
AnnaBridge 156:ff21514d8981 1776
AnnaBridge 156:ff21514d8981 1777
AnnaBridge 156:ff21514d8981 1778 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
AnnaBridge 156:ff21514d8981 1779 * @{
AnnaBridge 156:ff21514d8981 1780 */
AnnaBridge 156:ff21514d8981 1781
AnnaBridge 156:ff21514d8981 1782 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
AnnaBridge 156:ff21514d8981 1783 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
AnnaBridge 156:ff21514d8981 1784
AnnaBridge 156:ff21514d8981 1785 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
AnnaBridge 156:ff21514d8981 1786 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
AnnaBridge 156:ff21514d8981 1787
AnnaBridge 156:ff21514d8981 1788 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1789 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1790 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1791 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1792 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
AnnaBridge 156:ff21514d8981 1793 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1794 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1795 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1796 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
AnnaBridge 156:ff21514d8981 1797 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1798 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1799 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1800 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1801 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1802 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
AnnaBridge 156:ff21514d8981 1803 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1804 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1805 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1806 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
AnnaBridge 156:ff21514d8981 1807 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1808 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1809 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1810 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1811 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1812 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
AnnaBridge 156:ff21514d8981 1813 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1814 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1815 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1816 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1817 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1818 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
AnnaBridge 156:ff21514d8981 1819 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1820 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1821 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1822 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
AnnaBridge 156:ff21514d8981 1823 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1824 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
AnnaBridge 156:ff21514d8981 1825 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1826 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
AnnaBridge 156:ff21514d8981 1827 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1828 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
AnnaBridge 156:ff21514d8981 1829 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1830 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
AnnaBridge 156:ff21514d8981 1831 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1832 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
AnnaBridge 156:ff21514d8981 1833 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1834 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
AnnaBridge 156:ff21514d8981 1835 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1836 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1837 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1838 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
AnnaBridge 156:ff21514d8981 1839 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1840 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1841 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1842 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1843 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1844 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
AnnaBridge 156:ff21514d8981 1845 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1846 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1847 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1848 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
AnnaBridge 156:ff21514d8981 1849 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1850 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1851 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1852 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
AnnaBridge 156:ff21514d8981 1853 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1854 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1855 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1856 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1857 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1858 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
AnnaBridge 156:ff21514d8981 1859 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1860 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1861 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1862 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
AnnaBridge 156:ff21514d8981 1863 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1864 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1865 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1866 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1867 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1868 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
AnnaBridge 156:ff21514d8981 1869 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1870 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1871 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1872 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
AnnaBridge 156:ff21514d8981 1873 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1874 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1875 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1876 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1877 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1878 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
AnnaBridge 156:ff21514d8981 1879 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1880 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1881 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1882 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
AnnaBridge 156:ff21514d8981 1883 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1884 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1885 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1886 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1887 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1888 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
AnnaBridge 156:ff21514d8981 1889 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1890 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1891 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1892 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1893 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1894 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
AnnaBridge 156:ff21514d8981 1895 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1896 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1897 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1898 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1899 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1900 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
AnnaBridge 156:ff21514d8981 1901 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1902 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1903 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1904 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
AnnaBridge 156:ff21514d8981 1905 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1906 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1907 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1908 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1909 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1910 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1911 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1912 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1913 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1914 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1915 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1916 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
AnnaBridge 156:ff21514d8981 1917 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1918 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1919 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1920 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
AnnaBridge 156:ff21514d8981 1921 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1922 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1923 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1924 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1925 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1926 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1927 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1928 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
AnnaBridge 156:ff21514d8981 1929 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1930 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1931 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1932 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1933 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1934 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1935 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1936 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
AnnaBridge 156:ff21514d8981 1937 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1938 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1939 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1940 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1941 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1942 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
AnnaBridge 156:ff21514d8981 1943 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1944 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1945 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1946 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1947 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1948 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
AnnaBridge 156:ff21514d8981 1949 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1950 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1951 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1952 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1953 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1954 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
AnnaBridge 156:ff21514d8981 1955 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1956 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1957 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1958 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1959 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1960 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
AnnaBridge 156:ff21514d8981 1961 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1962 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1963 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1964 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1965 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1966 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
AnnaBridge 156:ff21514d8981 1967 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1968 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1969 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1970 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1971 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1972 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
AnnaBridge 156:ff21514d8981 1973 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1974 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1975 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1976 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1977 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1978 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
AnnaBridge 156:ff21514d8981 1979 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1980 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1981 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1982 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1983 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1984 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
AnnaBridge 156:ff21514d8981 1985 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1986 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1987 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1988 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1989 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1990 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
AnnaBridge 156:ff21514d8981 1991 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1992 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1993 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
AnnaBridge 156:ff21514d8981 1994 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 1995 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 1996 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
AnnaBridge 156:ff21514d8981 1997 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
AnnaBridge 156:ff21514d8981 1998 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
AnnaBridge 156:ff21514d8981 1999 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2000 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2001 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2002 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
AnnaBridge 156:ff21514d8981 2003 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2004 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2005 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2006 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2007 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2008 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
AnnaBridge 156:ff21514d8981 2009 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2010 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2011 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2012 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2013 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2014 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
AnnaBridge 156:ff21514d8981 2015 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2016 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2017 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2018 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2019 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2020 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
AnnaBridge 156:ff21514d8981 2021 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2022 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2023 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2024 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2025 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2026 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
AnnaBridge 156:ff21514d8981 2027 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2028 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2029 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2030 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2031 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2032 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
AnnaBridge 156:ff21514d8981 2033 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2034 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2035 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2036 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2037 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2038 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
AnnaBridge 156:ff21514d8981 2039 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2040 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2041 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2042 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2043 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2044 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
AnnaBridge 156:ff21514d8981 2045 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2046 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2047 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2048 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2049 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2050 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
AnnaBridge 156:ff21514d8981 2051 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2052 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2053 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2054 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2055 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2056 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
AnnaBridge 156:ff21514d8981 2057 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2058 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2059 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2060 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2061 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2062 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
AnnaBridge 156:ff21514d8981 2063 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2064 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2065 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2066 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2067 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2068 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2069 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2070 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
AnnaBridge 156:ff21514d8981 2071 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2072 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2073 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2074 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2075 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2076 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
AnnaBridge 156:ff21514d8981 2077 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2078 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2079 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2080 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2081 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2082 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
AnnaBridge 156:ff21514d8981 2083 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2084 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2085 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2086 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2087 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2088 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
AnnaBridge 156:ff21514d8981 2089 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2090 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2091 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2092 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2093 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2094 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2095 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2096 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2097 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2098 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2099 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2100 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
AnnaBridge 156:ff21514d8981 2101 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2102 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2103 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2104 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2105 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2106 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
AnnaBridge 156:ff21514d8981 2107 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2108 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2109 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2110 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2111 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2112 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
AnnaBridge 156:ff21514d8981 2113 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2114 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2115 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2116 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
AnnaBridge 156:ff21514d8981 2117 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2118 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2119 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2120 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
AnnaBridge 156:ff21514d8981 2121 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2122 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2123 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2124 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
AnnaBridge 156:ff21514d8981 2125 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2126 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2127 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2128 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
AnnaBridge 156:ff21514d8981 2129 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2130 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2131 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2132 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
AnnaBridge 156:ff21514d8981 2133 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2134 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2135 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2136 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2137 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2138 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
AnnaBridge 156:ff21514d8981 2139 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2140 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2141 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2142 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2143 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2144 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
AnnaBridge 156:ff21514d8981 2145 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2146 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2147 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2148 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2149 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2150 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
AnnaBridge 156:ff21514d8981 2151 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2152 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2153 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2154 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2155 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2156 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
AnnaBridge 156:ff21514d8981 2157 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2158 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2159 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2160 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2161 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2162 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
AnnaBridge 156:ff21514d8981 2163 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2164 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2165 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2166 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2167 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2168 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
AnnaBridge 156:ff21514d8981 2169 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2170 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2171 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2172 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2173 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2174 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
AnnaBridge 156:ff21514d8981 2175 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2176 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2177 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2178 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2179 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2180 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
AnnaBridge 156:ff21514d8981 2181 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2182 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2183 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2184 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2185 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2186 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
AnnaBridge 156:ff21514d8981 2187 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2188 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2189 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2190 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2191 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2192 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
AnnaBridge 156:ff21514d8981 2193 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2194 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2195 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2196 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
AnnaBridge 156:ff21514d8981 2197 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2198 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2199 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2200 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2201 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2202 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
AnnaBridge 156:ff21514d8981 2203 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2204 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2205 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2206 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2207 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2208 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
AnnaBridge 156:ff21514d8981 2209 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2210 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2211 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2212 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2213 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2214 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
AnnaBridge 156:ff21514d8981 2215 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2216 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2217 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2218 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2219 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2220 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
AnnaBridge 156:ff21514d8981 2221 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2222 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2223 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2224 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2225 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2226 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
AnnaBridge 156:ff21514d8981 2227 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2228 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2229 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2230 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2231 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2232 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
AnnaBridge 156:ff21514d8981 2233 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2234 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2235 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2236 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2237 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2238 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
AnnaBridge 156:ff21514d8981 2239 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2240 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2241 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2242 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2243 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2244 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
AnnaBridge 156:ff21514d8981 2245 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2246 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2247 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2248 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
AnnaBridge 156:ff21514d8981 2249 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2250 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2251 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2252 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
AnnaBridge 156:ff21514d8981 2253 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2254 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2255 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2256 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
AnnaBridge 156:ff21514d8981 2257 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2258 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2259 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2260 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2261 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2262 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2263 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2264 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2265 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2266 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
AnnaBridge 156:ff21514d8981 2267 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2268 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2269 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2270 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
AnnaBridge 156:ff21514d8981 2271 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2272 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2273 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2274 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2275 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2276 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
AnnaBridge 156:ff21514d8981 2277 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2278 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2279 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2280 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2281 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2282 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2283 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2284 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
AnnaBridge 156:ff21514d8981 2285 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2286 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
AnnaBridge 156:ff21514d8981 2287 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
AnnaBridge 156:ff21514d8981 2288
AnnaBridge 156:ff21514d8981 2289 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
AnnaBridge 156:ff21514d8981 2290 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2291 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2292 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2293 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2294 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2295 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2296 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2297 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2298 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2299 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2300 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2301 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2302 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2303 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2304 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2305 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2306 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2307 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2308 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
AnnaBridge 156:ff21514d8981 2309 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2310 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2311 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2312 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2313 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2314 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2315 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
AnnaBridge 156:ff21514d8981 2316 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2317 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2318 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2319 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2320 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2321 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
AnnaBridge 156:ff21514d8981 2322 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2323 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2324 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2325 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2326 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2327 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
AnnaBridge 156:ff21514d8981 2328 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2329 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2330 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2331 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2332 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2333 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2334 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2335 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2336 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2337 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2338 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2339 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2340 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2341 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2342 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2343 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2344 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2345 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2346 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2347 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2348 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2349 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2350 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
AnnaBridge 156:ff21514d8981 2351 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2352 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2353 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2354 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2355 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2356 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
AnnaBridge 156:ff21514d8981 2357 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2358 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2359 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2360 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2361 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2362 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
AnnaBridge 156:ff21514d8981 2363 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2364 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2365 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2366 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2367 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2368 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
AnnaBridge 156:ff21514d8981 2369 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2370 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2371 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2372 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2373 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2374 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2375 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2376 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2377 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2378 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2379 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2380 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2381 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
AnnaBridge 156:ff21514d8981 2382 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2383 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2384 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2385 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2386 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2387 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2388 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
AnnaBridge 156:ff21514d8981 2389 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2390 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2391 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2392 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2393 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
AnnaBridge 156:ff21514d8981 2394 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2395 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2396 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2397 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2398 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2399 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
AnnaBridge 156:ff21514d8981 2400 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2401 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2402 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2403 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2404 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2405 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
AnnaBridge 156:ff21514d8981 2406 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
AnnaBridge 156:ff21514d8981 2407 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
AnnaBridge 156:ff21514d8981 2408 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2409 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2410 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2411 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
AnnaBridge 156:ff21514d8981 2412 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
AnnaBridge 156:ff21514d8981 2413 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
AnnaBridge 156:ff21514d8981 2414 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2415 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2416 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2417 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2418 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2419 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2420 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2421 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2422 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2423 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
AnnaBridge 156:ff21514d8981 2424 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2425 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2426 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2427 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
AnnaBridge 156:ff21514d8981 2428 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2429 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2430 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2431 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2432 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2433 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
AnnaBridge 156:ff21514d8981 2434 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2435 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2436 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2437
AnnaBridge 156:ff21514d8981 2438 /* alias define maintained for legacy */
AnnaBridge 156:ff21514d8981 2439 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
AnnaBridge 156:ff21514d8981 2440 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2441
AnnaBridge 156:ff21514d8981 2442 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2443 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2444 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2445 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2446 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2447 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2448 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2449 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2450 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2451 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2452 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2453 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2454 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2455 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2456 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2457 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2458 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2459 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2460 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2461 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2462 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2463 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2464
AnnaBridge 156:ff21514d8981 2465 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
AnnaBridge 156:ff21514d8981 2466 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2467 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
AnnaBridge 156:ff21514d8981 2468 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2469 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
AnnaBridge 156:ff21514d8981 2470 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2471 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
AnnaBridge 156:ff21514d8981 2472 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2473 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
AnnaBridge 156:ff21514d8981 2474 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2475 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
AnnaBridge 156:ff21514d8981 2476 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2477 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
AnnaBridge 156:ff21514d8981 2478 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2479 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
AnnaBridge 156:ff21514d8981 2480 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2481 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
AnnaBridge 156:ff21514d8981 2482 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
AnnaBridge 156:ff21514d8981 2483 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
AnnaBridge 156:ff21514d8981 2484 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2485 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2486 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2487
AnnaBridge 156:ff21514d8981 2488 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2489 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2490 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2491 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2492 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2493 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2494 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2495 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2496 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2497 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2498 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2499 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2500 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2501 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2502 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2503 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2504 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2505 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2506 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2507 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2508 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2509 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2510 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2511 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2512 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2513 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2514 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2515 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2516 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2517 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2518 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2519 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2520 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2521 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2522 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2523 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2524 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2525 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2526 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2527 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2528 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2529 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2530 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2531 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2532 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2533 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2534 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2535 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2536 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2537 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2538 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2539 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2540 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2541 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2542 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2543 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2544 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2545 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2546 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2547 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2548 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2549 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2550 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2551 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2552 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2553 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2554 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2555 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2556 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2557 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2558 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2559 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2560 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2561 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2562 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2563 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2564 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2565 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2566 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2567 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2568 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2569 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2570 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2571 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2572 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2573 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2574 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2575 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2576 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2577 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2578 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2579 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2580 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2581 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2582 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2583 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2584 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2585 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2586 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2587 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2588 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2589 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2590 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2591 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2592 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2593 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2594 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2595 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2596 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2597 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2598 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2599 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2600 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2601 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2602 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2603 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2604
AnnaBridge 156:ff21514d8981 2605 #if defined(STM32F4)
AnnaBridge 156:ff21514d8981 2606 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
AnnaBridge 156:ff21514d8981 2607 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2608 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2609 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2610 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2611 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2612 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2613 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2614 #define Sdmmc1ClockSelection SdioClockSelection
AnnaBridge 156:ff21514d8981 2615 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
AnnaBridge 156:ff21514d8981 2616 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
AnnaBridge 156:ff21514d8981 2617 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
AnnaBridge 156:ff21514d8981 2618 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
AnnaBridge 156:ff21514d8981 2619 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
AnnaBridge 156:ff21514d8981 2620 #endif
AnnaBridge 156:ff21514d8981 2621
AnnaBridge 156:ff21514d8981 2622 #if defined(STM32F7) || defined(STM32L4)
AnnaBridge 156:ff21514d8981 2623 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
AnnaBridge 156:ff21514d8981 2624 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2625 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2626 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2627 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2628 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2629 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2630 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2631 #define SdioClockSelection Sdmmc1ClockSelection
AnnaBridge 156:ff21514d8981 2632 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
AnnaBridge 156:ff21514d8981 2633 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
AnnaBridge 156:ff21514d8981 2634 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
AnnaBridge 156:ff21514d8981 2635 #endif
AnnaBridge 156:ff21514d8981 2636
AnnaBridge 156:ff21514d8981 2637 #if defined(STM32F7)
AnnaBridge 156:ff21514d8981 2638 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
AnnaBridge 156:ff21514d8981 2639 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
AnnaBridge 156:ff21514d8981 2640 #endif
AnnaBridge 156:ff21514d8981 2641
AnnaBridge 156:ff21514d8981 2642 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
AnnaBridge 156:ff21514d8981 2643 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
AnnaBridge 156:ff21514d8981 2644
AnnaBridge 156:ff21514d8981 2645 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
AnnaBridge 156:ff21514d8981 2646
AnnaBridge 156:ff21514d8981 2647 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
AnnaBridge 156:ff21514d8981 2648 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
AnnaBridge 156:ff21514d8981 2649 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
AnnaBridge 156:ff21514d8981 2650 #define IS_RCC_HCLK_DIV IS_RCC_PCLK
AnnaBridge 156:ff21514d8981 2651 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
AnnaBridge 156:ff21514d8981 2652
AnnaBridge 156:ff21514d8981 2653 #define RCC_IT_HSI14 RCC_IT_HSI14RDY
AnnaBridge 156:ff21514d8981 2654
AnnaBridge 156:ff21514d8981 2655 #define RCC_IT_CSSLSE RCC_IT_LSECSS
AnnaBridge 156:ff21514d8981 2656 #define RCC_IT_CSSHSE RCC_IT_CSS
AnnaBridge 156:ff21514d8981 2657
AnnaBridge 156:ff21514d8981 2658 #define RCC_PLLMUL_3 RCC_PLL_MUL3
AnnaBridge 156:ff21514d8981 2659 #define RCC_PLLMUL_4 RCC_PLL_MUL4
AnnaBridge 156:ff21514d8981 2660 #define RCC_PLLMUL_6 RCC_PLL_MUL6
AnnaBridge 156:ff21514d8981 2661 #define RCC_PLLMUL_8 RCC_PLL_MUL8
AnnaBridge 156:ff21514d8981 2662 #define RCC_PLLMUL_12 RCC_PLL_MUL12
AnnaBridge 156:ff21514d8981 2663 #define RCC_PLLMUL_16 RCC_PLL_MUL16
AnnaBridge 156:ff21514d8981 2664 #define RCC_PLLMUL_24 RCC_PLL_MUL24
AnnaBridge 156:ff21514d8981 2665 #define RCC_PLLMUL_32 RCC_PLL_MUL32
AnnaBridge 156:ff21514d8981 2666 #define RCC_PLLMUL_48 RCC_PLL_MUL48
AnnaBridge 156:ff21514d8981 2667
AnnaBridge 156:ff21514d8981 2668 #define RCC_PLLDIV_2 RCC_PLL_DIV2
AnnaBridge 156:ff21514d8981 2669 #define RCC_PLLDIV_3 RCC_PLL_DIV3
AnnaBridge 156:ff21514d8981 2670 #define RCC_PLLDIV_4 RCC_PLL_DIV4
AnnaBridge 156:ff21514d8981 2671
AnnaBridge 156:ff21514d8981 2672 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
AnnaBridge 156:ff21514d8981 2673 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
AnnaBridge 156:ff21514d8981 2674 #define RCC_MCO_NODIV RCC_MCODIV_1
AnnaBridge 156:ff21514d8981 2675 #define RCC_MCO_DIV1 RCC_MCODIV_1
AnnaBridge 156:ff21514d8981 2676 #define RCC_MCO_DIV2 RCC_MCODIV_2
AnnaBridge 156:ff21514d8981 2677 #define RCC_MCO_DIV4 RCC_MCODIV_4
AnnaBridge 156:ff21514d8981 2678 #define RCC_MCO_DIV8 RCC_MCODIV_8
AnnaBridge 156:ff21514d8981 2679 #define RCC_MCO_DIV16 RCC_MCODIV_16
AnnaBridge 156:ff21514d8981 2680 #define RCC_MCO_DIV32 RCC_MCODIV_32
AnnaBridge 156:ff21514d8981 2681 #define RCC_MCO_DIV64 RCC_MCODIV_64
AnnaBridge 156:ff21514d8981 2682 #define RCC_MCO_DIV128 RCC_MCODIV_128
AnnaBridge 156:ff21514d8981 2683 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
AnnaBridge 156:ff21514d8981 2684 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
AnnaBridge 156:ff21514d8981 2685 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
AnnaBridge 156:ff21514d8981 2686 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
AnnaBridge 156:ff21514d8981 2687 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
AnnaBridge 156:ff21514d8981 2688 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
AnnaBridge 156:ff21514d8981 2689 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
AnnaBridge 156:ff21514d8981 2690 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
AnnaBridge 156:ff21514d8981 2691 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
AnnaBridge 156:ff21514d8981 2692 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
AnnaBridge 156:ff21514d8981 2693 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
AnnaBridge 156:ff21514d8981 2694
AnnaBridge 156:ff21514d8981 2695 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
AnnaBridge 156:ff21514d8981 2696
AnnaBridge 156:ff21514d8981 2697 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
AnnaBridge 156:ff21514d8981 2698 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
AnnaBridge 156:ff21514d8981 2699 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
AnnaBridge 156:ff21514d8981 2700 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
AnnaBridge 156:ff21514d8981 2701 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
AnnaBridge 156:ff21514d8981 2702 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
AnnaBridge 156:ff21514d8981 2703 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
AnnaBridge 156:ff21514d8981 2704 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
AnnaBridge 156:ff21514d8981 2705
AnnaBridge 156:ff21514d8981 2706 #define HSION_BitNumber RCC_HSION_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2707 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2708 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2709 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2710 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2711 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2712 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2713 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2714 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2715 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2716 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2717 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2718 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2719 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2720 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2721 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2722 #define LSION_BitNumber RCC_LSION_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2723 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2724 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2725 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2726 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2727 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2728 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2729 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2730 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2731 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
AnnaBridge 156:ff21514d8981 2732 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
AnnaBridge 156:ff21514d8981 2733 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
AnnaBridge 156:ff21514d8981 2734 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
AnnaBridge 156:ff21514d8981 2735 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
AnnaBridge 156:ff21514d8981 2736 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
AnnaBridge 156:ff21514d8981 2737 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
AnnaBridge 156:ff21514d8981 2738
AnnaBridge 156:ff21514d8981 2739 #define CR_HSION_BB RCC_CR_HSION_BB
AnnaBridge 156:ff21514d8981 2740 #define CR_CSSON_BB RCC_CR_CSSON_BB
AnnaBridge 156:ff21514d8981 2741 #define CR_PLLON_BB RCC_CR_PLLON_BB
AnnaBridge 156:ff21514d8981 2742 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
AnnaBridge 156:ff21514d8981 2743 #define CR_MSION_BB RCC_CR_MSION_BB
AnnaBridge 156:ff21514d8981 2744 #define CSR_LSION_BB RCC_CSR_LSION_BB
AnnaBridge 156:ff21514d8981 2745 #define CSR_LSEON_BB RCC_CSR_LSEON_BB
AnnaBridge 156:ff21514d8981 2746 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
AnnaBridge 156:ff21514d8981 2747 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
AnnaBridge 156:ff21514d8981 2748 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
AnnaBridge 156:ff21514d8981 2749 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
AnnaBridge 156:ff21514d8981 2750 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
AnnaBridge 156:ff21514d8981 2751 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
AnnaBridge 156:ff21514d8981 2752 #define CR_HSEON_BB RCC_CR_HSEON_BB
AnnaBridge 156:ff21514d8981 2753 #define CSR_RMVF_BB RCC_CSR_RMVF_BB
AnnaBridge 156:ff21514d8981 2754 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
AnnaBridge 156:ff21514d8981 2755 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
AnnaBridge 156:ff21514d8981 2756
AnnaBridge 156:ff21514d8981 2757 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
AnnaBridge 156:ff21514d8981 2758 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
AnnaBridge 156:ff21514d8981 2759 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
AnnaBridge 156:ff21514d8981 2760 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
AnnaBridge 156:ff21514d8981 2761 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
AnnaBridge 156:ff21514d8981 2762
AnnaBridge 156:ff21514d8981 2763 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
AnnaBridge 156:ff21514d8981 2764
AnnaBridge 156:ff21514d8981 2765 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
AnnaBridge 156:ff21514d8981 2766 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
AnnaBridge 156:ff21514d8981 2767
AnnaBridge 156:ff21514d8981 2768 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
AnnaBridge 156:ff21514d8981 2769 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
AnnaBridge 156:ff21514d8981 2770 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
AnnaBridge 156:ff21514d8981 2771 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
AnnaBridge 156:ff21514d8981 2772 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
AnnaBridge 156:ff21514d8981 2773 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
AnnaBridge 156:ff21514d8981 2774
AnnaBridge 156:ff21514d8981 2775 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
AnnaBridge 156:ff21514d8981 2776 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
AnnaBridge 156:ff21514d8981 2777 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
AnnaBridge 156:ff21514d8981 2778 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
AnnaBridge 156:ff21514d8981 2779 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
AnnaBridge 156:ff21514d8981 2780 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
AnnaBridge 156:ff21514d8981 2781 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
AnnaBridge 156:ff21514d8981 2782 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
AnnaBridge 156:ff21514d8981 2783 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
AnnaBridge 156:ff21514d8981 2784 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
AnnaBridge 156:ff21514d8981 2785 #define DfsdmClockSelection Dfsdm1ClockSelection
AnnaBridge 156:ff21514d8981 2786 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
AnnaBridge 156:ff21514d8981 2787 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
AnnaBridge 156:ff21514d8981 2788 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
AnnaBridge 156:ff21514d8981 2789 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
AnnaBridge 156:ff21514d8981 2790 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
AnnaBridge 156:ff21514d8981 2791
AnnaBridge 156:ff21514d8981 2792 /**
AnnaBridge 156:ff21514d8981 2793 * @}
AnnaBridge 156:ff21514d8981 2794 */
AnnaBridge 156:ff21514d8981 2795
AnnaBridge 156:ff21514d8981 2796 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 2797 * @{
AnnaBridge 156:ff21514d8981 2798 */
AnnaBridge 156:ff21514d8981 2799 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
AnnaBridge 156:ff21514d8981 2800
AnnaBridge 156:ff21514d8981 2801 /**
AnnaBridge 156:ff21514d8981 2802 * @}
AnnaBridge 156:ff21514d8981 2803 */
AnnaBridge 156:ff21514d8981 2804
AnnaBridge 156:ff21514d8981 2805 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 2806 * @{
AnnaBridge 156:ff21514d8981 2807 */
AnnaBridge 156:ff21514d8981 2808
AnnaBridge 156:ff21514d8981 2809 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
AnnaBridge 156:ff21514d8981 2810 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
AnnaBridge 156:ff21514d8981 2811 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
AnnaBridge 156:ff21514d8981 2812
AnnaBridge 156:ff21514d8981 2813 #if defined (STM32F1)
AnnaBridge 156:ff21514d8981 2814 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
AnnaBridge 156:ff21514d8981 2815
AnnaBridge 156:ff21514d8981 2816 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
AnnaBridge 156:ff21514d8981 2817
AnnaBridge 156:ff21514d8981 2818 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
AnnaBridge 156:ff21514d8981 2819
AnnaBridge 156:ff21514d8981 2820 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
AnnaBridge 156:ff21514d8981 2821
AnnaBridge 156:ff21514d8981 2822 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
AnnaBridge 156:ff21514d8981 2823 #else
AnnaBridge 156:ff21514d8981 2824 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 2825 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
AnnaBridge 156:ff21514d8981 2826 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
AnnaBridge 156:ff21514d8981 2827 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 2828 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
AnnaBridge 156:ff21514d8981 2829 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
AnnaBridge 156:ff21514d8981 2830 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 2831 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
AnnaBridge 156:ff21514d8981 2832 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
AnnaBridge 156:ff21514d8981 2833 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 2834 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
AnnaBridge 156:ff21514d8981 2835 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
AnnaBridge 156:ff21514d8981 2836 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
AnnaBridge 156:ff21514d8981 2837 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
AnnaBridge 156:ff21514d8981 2838 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
AnnaBridge 156:ff21514d8981 2839 #endif /* STM32F1 */
AnnaBridge 156:ff21514d8981 2840
AnnaBridge 156:ff21514d8981 2841 #define IS_ALARM IS_RTC_ALARM
AnnaBridge 156:ff21514d8981 2842 #define IS_ALARM_MASK IS_RTC_ALARM_MASK
AnnaBridge 156:ff21514d8981 2843 #define IS_TAMPER IS_RTC_TAMPER
AnnaBridge 156:ff21514d8981 2844 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
AnnaBridge 156:ff21514d8981 2845 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
AnnaBridge 156:ff21514d8981 2846 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
AnnaBridge 156:ff21514d8981 2847 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
AnnaBridge 156:ff21514d8981 2848 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
AnnaBridge 156:ff21514d8981 2849 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
AnnaBridge 156:ff21514d8981 2850 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
AnnaBridge 156:ff21514d8981 2851 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
AnnaBridge 156:ff21514d8981 2852 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
AnnaBridge 156:ff21514d8981 2853 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
AnnaBridge 156:ff21514d8981 2854 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
AnnaBridge 156:ff21514d8981 2855
AnnaBridge 156:ff21514d8981 2856 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
AnnaBridge 156:ff21514d8981 2857 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
AnnaBridge 156:ff21514d8981 2858
AnnaBridge 156:ff21514d8981 2859 /**
AnnaBridge 156:ff21514d8981 2860 * @}
AnnaBridge 156:ff21514d8981 2861 */
AnnaBridge 156:ff21514d8981 2862
AnnaBridge 156:ff21514d8981 2863 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 2864 * @{
AnnaBridge 156:ff21514d8981 2865 */
AnnaBridge 156:ff21514d8981 2866
AnnaBridge 156:ff21514d8981 2867 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
AnnaBridge 156:ff21514d8981 2868 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
AnnaBridge 156:ff21514d8981 2869
AnnaBridge 156:ff21514d8981 2870 #if defined(STM32F4)
AnnaBridge 156:ff21514d8981 2871 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
AnnaBridge 156:ff21514d8981 2872 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
AnnaBridge 156:ff21514d8981 2873 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
AnnaBridge 156:ff21514d8981 2874 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
AnnaBridge 156:ff21514d8981 2875 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
AnnaBridge 156:ff21514d8981 2876 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
AnnaBridge 156:ff21514d8981 2877 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
AnnaBridge 156:ff21514d8981 2878 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
AnnaBridge 156:ff21514d8981 2879 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
AnnaBridge 156:ff21514d8981 2880 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
AnnaBridge 156:ff21514d8981 2881 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
AnnaBridge 156:ff21514d8981 2882 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
AnnaBridge 156:ff21514d8981 2883 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
AnnaBridge 156:ff21514d8981 2884 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
AnnaBridge 156:ff21514d8981 2885 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
AnnaBridge 156:ff21514d8981 2886 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
AnnaBridge 156:ff21514d8981 2887 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
AnnaBridge 156:ff21514d8981 2888 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
AnnaBridge 156:ff21514d8981 2889 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
AnnaBridge 156:ff21514d8981 2890 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
AnnaBridge 156:ff21514d8981 2891 /* alias CMSIS */
AnnaBridge 156:ff21514d8981 2892 #define SDMMC1_IRQn SDIO_IRQn
AnnaBridge 156:ff21514d8981 2893 #define SDMMC1_IRQHandler SDIO_IRQHandler
AnnaBridge 156:ff21514d8981 2894 #endif
AnnaBridge 156:ff21514d8981 2895
AnnaBridge 156:ff21514d8981 2896 #if defined(STM32F7) || defined(STM32L4)
AnnaBridge 156:ff21514d8981 2897 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED
AnnaBridge 156:ff21514d8981 2898 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
AnnaBridge 156:ff21514d8981 2899 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
AnnaBridge 156:ff21514d8981 2900 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
AnnaBridge 156:ff21514d8981 2901 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
AnnaBridge 156:ff21514d8981 2902 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
AnnaBridge 156:ff21514d8981 2903 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
AnnaBridge 156:ff21514d8981 2904 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
AnnaBridge 156:ff21514d8981 2905 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
AnnaBridge 156:ff21514d8981 2906 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
AnnaBridge 156:ff21514d8981 2907 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
AnnaBridge 156:ff21514d8981 2908 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
AnnaBridge 156:ff21514d8981 2909 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
AnnaBridge 156:ff21514d8981 2910 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
AnnaBridge 156:ff21514d8981 2911 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
AnnaBridge 156:ff21514d8981 2912 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
AnnaBridge 156:ff21514d8981 2913 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
AnnaBridge 156:ff21514d8981 2914 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
AnnaBridge 156:ff21514d8981 2915 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
AnnaBridge 156:ff21514d8981 2916 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
AnnaBridge 156:ff21514d8981 2917 /* alias CMSIS for compatibilities */
AnnaBridge 156:ff21514d8981 2918 #define SDIO_IRQn SDMMC1_IRQn
AnnaBridge 156:ff21514d8981 2919 #define SDIO_IRQHandler SDMMC1_IRQHandler
AnnaBridge 156:ff21514d8981 2920 #endif
AnnaBridge 156:ff21514d8981 2921 /**
AnnaBridge 156:ff21514d8981 2922 * @}
AnnaBridge 156:ff21514d8981 2923 */
AnnaBridge 156:ff21514d8981 2924
AnnaBridge 156:ff21514d8981 2925 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 2926 * @{
AnnaBridge 156:ff21514d8981 2927 */
AnnaBridge 156:ff21514d8981 2928
AnnaBridge 156:ff21514d8981 2929 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
AnnaBridge 156:ff21514d8981 2930 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
AnnaBridge 156:ff21514d8981 2931 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
AnnaBridge 156:ff21514d8981 2932 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
AnnaBridge 156:ff21514d8981 2933 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
AnnaBridge 156:ff21514d8981 2934 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
AnnaBridge 156:ff21514d8981 2935
AnnaBridge 156:ff21514d8981 2936 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
AnnaBridge 156:ff21514d8981 2937 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
AnnaBridge 156:ff21514d8981 2938
AnnaBridge 156:ff21514d8981 2939 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
AnnaBridge 156:ff21514d8981 2940
AnnaBridge 156:ff21514d8981 2941 /**
AnnaBridge 156:ff21514d8981 2942 * @}
AnnaBridge 156:ff21514d8981 2943 */
AnnaBridge 156:ff21514d8981 2944
AnnaBridge 156:ff21514d8981 2945 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 2946 * @{
AnnaBridge 156:ff21514d8981 2947 */
AnnaBridge 156:ff21514d8981 2948 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
AnnaBridge 156:ff21514d8981 2949 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
AnnaBridge 156:ff21514d8981 2950 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
AnnaBridge 156:ff21514d8981 2951 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
AnnaBridge 156:ff21514d8981 2952 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
AnnaBridge 156:ff21514d8981 2953 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
AnnaBridge 156:ff21514d8981 2954 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
AnnaBridge 156:ff21514d8981 2955 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
AnnaBridge 156:ff21514d8981 2956 /**
AnnaBridge 156:ff21514d8981 2957 * @}
AnnaBridge 156:ff21514d8981 2958 */
AnnaBridge 156:ff21514d8981 2959
AnnaBridge 156:ff21514d8981 2960 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 2961 * @{
AnnaBridge 156:ff21514d8981 2962 */
AnnaBridge 156:ff21514d8981 2963
AnnaBridge 156:ff21514d8981 2964 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
AnnaBridge 156:ff21514d8981 2965 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
AnnaBridge 156:ff21514d8981 2966 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
AnnaBridge 156:ff21514d8981 2967
AnnaBridge 156:ff21514d8981 2968 /**
AnnaBridge 156:ff21514d8981 2969 * @}
AnnaBridge 156:ff21514d8981 2970 */
AnnaBridge 156:ff21514d8981 2971
AnnaBridge 156:ff21514d8981 2972 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 2973 * @{
AnnaBridge 156:ff21514d8981 2974 */
AnnaBridge 156:ff21514d8981 2975
AnnaBridge 156:ff21514d8981 2976 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
AnnaBridge 156:ff21514d8981 2977 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
AnnaBridge 156:ff21514d8981 2978 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
AnnaBridge 156:ff21514d8981 2979 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
AnnaBridge 156:ff21514d8981 2980
AnnaBridge 156:ff21514d8981 2981 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
AnnaBridge 156:ff21514d8981 2982
AnnaBridge 156:ff21514d8981 2983 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
AnnaBridge 156:ff21514d8981 2984 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
AnnaBridge 156:ff21514d8981 2985
AnnaBridge 156:ff21514d8981 2986 /**
AnnaBridge 156:ff21514d8981 2987 * @}
AnnaBridge 156:ff21514d8981 2988 */
AnnaBridge 156:ff21514d8981 2989
AnnaBridge 156:ff21514d8981 2990
AnnaBridge 156:ff21514d8981 2991 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 2992 * @{
AnnaBridge 156:ff21514d8981 2993 */
AnnaBridge 156:ff21514d8981 2994
AnnaBridge 156:ff21514d8981 2995 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
AnnaBridge 156:ff21514d8981 2996 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
AnnaBridge 156:ff21514d8981 2997 #define __USART_ENABLE __HAL_USART_ENABLE
AnnaBridge 156:ff21514d8981 2998 #define __USART_DISABLE __HAL_USART_DISABLE
AnnaBridge 156:ff21514d8981 2999
AnnaBridge 156:ff21514d8981 3000 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
AnnaBridge 156:ff21514d8981 3001 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
AnnaBridge 156:ff21514d8981 3002
AnnaBridge 156:ff21514d8981 3003 /**
AnnaBridge 156:ff21514d8981 3004 * @}
AnnaBridge 156:ff21514d8981 3005 */
AnnaBridge 156:ff21514d8981 3006
AnnaBridge 156:ff21514d8981 3007 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 3008 * @{
AnnaBridge 156:ff21514d8981 3009 */
AnnaBridge 156:ff21514d8981 3010 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
AnnaBridge 156:ff21514d8981 3011
AnnaBridge 156:ff21514d8981 3012 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
AnnaBridge 156:ff21514d8981 3013 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
AnnaBridge 156:ff21514d8981 3014 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
AnnaBridge 156:ff21514d8981 3015 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
AnnaBridge 156:ff21514d8981 3016
AnnaBridge 156:ff21514d8981 3017 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
AnnaBridge 156:ff21514d8981 3018 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
AnnaBridge 156:ff21514d8981 3019 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
AnnaBridge 156:ff21514d8981 3020 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
AnnaBridge 156:ff21514d8981 3021
AnnaBridge 156:ff21514d8981 3022 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
AnnaBridge 156:ff21514d8981 3023 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
AnnaBridge 156:ff21514d8981 3024 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
AnnaBridge 156:ff21514d8981 3025 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge 156:ff21514d8981 3026 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
AnnaBridge 156:ff21514d8981 3027 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 156:ff21514d8981 3028 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
AnnaBridge 156:ff21514d8981 3029
AnnaBridge 156:ff21514d8981 3030 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
AnnaBridge 156:ff21514d8981 3031 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
AnnaBridge 156:ff21514d8981 3032 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
AnnaBridge 156:ff21514d8981 3033 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge 156:ff21514d8981 3034 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
AnnaBridge 156:ff21514d8981 3035 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 156:ff21514d8981 3036 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
AnnaBridge 156:ff21514d8981 3037 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
AnnaBridge 156:ff21514d8981 3038
AnnaBridge 156:ff21514d8981 3039 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
AnnaBridge 156:ff21514d8981 3040 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
AnnaBridge 156:ff21514d8981 3041 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
AnnaBridge 156:ff21514d8981 3042 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge 156:ff21514d8981 3043 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
AnnaBridge 156:ff21514d8981 3044 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
AnnaBridge 156:ff21514d8981 3045 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
AnnaBridge 156:ff21514d8981 3046 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
AnnaBridge 156:ff21514d8981 3047
AnnaBridge 156:ff21514d8981 3048 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
AnnaBridge 156:ff21514d8981 3049 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
AnnaBridge 156:ff21514d8981 3050
AnnaBridge 156:ff21514d8981 3051 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
AnnaBridge 156:ff21514d8981 3052 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
AnnaBridge 156:ff21514d8981 3053 /**
AnnaBridge 156:ff21514d8981 3054 * @}
AnnaBridge 156:ff21514d8981 3055 */
AnnaBridge 156:ff21514d8981 3056
AnnaBridge 156:ff21514d8981 3057 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 3058 * @{
AnnaBridge 156:ff21514d8981 3059 */
AnnaBridge 156:ff21514d8981 3060 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
AnnaBridge 156:ff21514d8981 3061 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
AnnaBridge 156:ff21514d8981 3062
AnnaBridge 156:ff21514d8981 3063 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
AnnaBridge 156:ff21514d8981 3064 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
AnnaBridge 156:ff21514d8981 3065
AnnaBridge 156:ff21514d8981 3066 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
AnnaBridge 156:ff21514d8981 3067
AnnaBridge 156:ff21514d8981 3068 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
AnnaBridge 156:ff21514d8981 3069 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
AnnaBridge 156:ff21514d8981 3070 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
AnnaBridge 156:ff21514d8981 3071 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
AnnaBridge 156:ff21514d8981 3072 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
AnnaBridge 156:ff21514d8981 3073 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
AnnaBridge 156:ff21514d8981 3074 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
AnnaBridge 156:ff21514d8981 3075 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
AnnaBridge 156:ff21514d8981 3076 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
AnnaBridge 156:ff21514d8981 3077 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
AnnaBridge 156:ff21514d8981 3078 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
AnnaBridge 156:ff21514d8981 3079 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
AnnaBridge 156:ff21514d8981 3080
AnnaBridge 156:ff21514d8981 3081 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
AnnaBridge 156:ff21514d8981 3082 /**
AnnaBridge 156:ff21514d8981 3083 * @}
AnnaBridge 156:ff21514d8981 3084 */
AnnaBridge 156:ff21514d8981 3085
AnnaBridge 156:ff21514d8981 3086 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 3087 * @{
AnnaBridge 156:ff21514d8981 3088 */
AnnaBridge 156:ff21514d8981 3089
AnnaBridge 156:ff21514d8981 3090 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
AnnaBridge 156:ff21514d8981 3091 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
AnnaBridge 156:ff21514d8981 3092 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
AnnaBridge 156:ff21514d8981 3093 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge 156:ff21514d8981 3094 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
AnnaBridge 156:ff21514d8981 3095 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
AnnaBridge 156:ff21514d8981 3096 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
AnnaBridge 156:ff21514d8981 3097
AnnaBridge 156:ff21514d8981 3098 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
AnnaBridge 156:ff21514d8981 3099 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
AnnaBridge 156:ff21514d8981 3100 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
AnnaBridge 156:ff21514d8981 3101 /**
AnnaBridge 156:ff21514d8981 3102 * @}
AnnaBridge 156:ff21514d8981 3103 */
AnnaBridge 156:ff21514d8981 3104
AnnaBridge 156:ff21514d8981 3105 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 3106 * @{
AnnaBridge 156:ff21514d8981 3107 */
AnnaBridge 156:ff21514d8981 3108 #define __HAL_LTDC_LAYER LTDC_LAYER
AnnaBridge 156:ff21514d8981 3109 /**
AnnaBridge 156:ff21514d8981 3110 * @}
AnnaBridge 156:ff21514d8981 3111 */
AnnaBridge 156:ff21514d8981 3112
AnnaBridge 156:ff21514d8981 3113 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 3114 * @{
AnnaBridge 156:ff21514d8981 3115 */
AnnaBridge 156:ff21514d8981 3116 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
AnnaBridge 156:ff21514d8981 3117 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
AnnaBridge 156:ff21514d8981 3118 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
AnnaBridge 156:ff21514d8981 3119 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
AnnaBridge 156:ff21514d8981 3120 #define SAI_STREOMODE SAI_STEREOMODE
AnnaBridge 156:ff21514d8981 3121 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
AnnaBridge 156:ff21514d8981 3122 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
AnnaBridge 156:ff21514d8981 3123 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
AnnaBridge 156:ff21514d8981 3124 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
AnnaBridge 156:ff21514d8981 3125 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
AnnaBridge 156:ff21514d8981 3126 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
AnnaBridge 156:ff21514d8981 3127 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
AnnaBridge 156:ff21514d8981 3128 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
AnnaBridge 156:ff21514d8981 3129 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
AnnaBridge 156:ff21514d8981 3130 /**
AnnaBridge 156:ff21514d8981 3131 * @}
AnnaBridge 156:ff21514d8981 3132 */
AnnaBridge 156:ff21514d8981 3133
AnnaBridge 156:ff21514d8981 3134
AnnaBridge 156:ff21514d8981 3135 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
AnnaBridge 156:ff21514d8981 3136 * @{
AnnaBridge 156:ff21514d8981 3137 */
AnnaBridge 156:ff21514d8981 3138
AnnaBridge 156:ff21514d8981 3139 /**
AnnaBridge 156:ff21514d8981 3140 * @}
AnnaBridge 156:ff21514d8981 3141 */
AnnaBridge 156:ff21514d8981 3142
AnnaBridge 156:ff21514d8981 3143 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 3144 }
AnnaBridge 156:ff21514d8981 3145 #endif
AnnaBridge 156:ff21514d8981 3146
AnnaBridge 156:ff21514d8981 3147 #endif /* ___STM32_HAL_LEGACY */
AnnaBridge 156:ff21514d8981 3148
AnnaBridge 156:ff21514d8981 3149 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
AnnaBridge 156:ff21514d8981 3150