mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_LPC546XX/core_ca.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
153:b484a57bc302 
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 153:b484a57bc302 1 /**************************************************************************//**
AnnaBridge 153:b484a57bc302 2 * @file core_ca.h
AnnaBridge 153:b484a57bc302 3 * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
AnnaBridge 153:b484a57bc302 4 * @version V1.00
AnnaBridge 153:b484a57bc302 5 * @date 22. Feb 2017
AnnaBridge 153:b484a57bc302 6 ******************************************************************************/
AnnaBridge 153:b484a57bc302 7 /*
AnnaBridge 153:b484a57bc302 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 153:b484a57bc302 9 *
AnnaBridge 153:b484a57bc302 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 153:b484a57bc302 11 *
AnnaBridge 153:b484a57bc302 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 153:b484a57bc302 13 * not use this file except in compliance with the License.
AnnaBridge 153:b484a57bc302 14 * You may obtain a copy of the License at
AnnaBridge 153:b484a57bc302 15 *
AnnaBridge 153:b484a57bc302 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 153:b484a57bc302 17 *
AnnaBridge 153:b484a57bc302 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 153:b484a57bc302 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 153:b484a57bc302 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 153:b484a57bc302 21 * See the License for the specific language governing permissions and
AnnaBridge 153:b484a57bc302 22 * limitations under the License.
AnnaBridge 153:b484a57bc302 23 */
AnnaBridge 153:b484a57bc302 24
AnnaBridge 153:b484a57bc302 25 #if defined ( __ICCARM__ )
AnnaBridge 153:b484a57bc302 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 153:b484a57bc302 27 #endif
AnnaBridge 153:b484a57bc302 28
AnnaBridge 153:b484a57bc302 29 #ifdef __cplusplus
AnnaBridge 153:b484a57bc302 30 extern "C" {
AnnaBridge 153:b484a57bc302 31 #endif
AnnaBridge 153:b484a57bc302 32
AnnaBridge 153:b484a57bc302 33 #ifndef __CORE_CA_H_GENERIC
AnnaBridge 153:b484a57bc302 34 #define __CORE_CA_H_GENERIC
AnnaBridge 153:b484a57bc302 35
AnnaBridge 153:b484a57bc302 36
AnnaBridge 153:b484a57bc302 37 /*******************************************************************************
AnnaBridge 153:b484a57bc302 38 * CMSIS definitions
AnnaBridge 153:b484a57bc302 39 ******************************************************************************/
AnnaBridge 153:b484a57bc302 40
AnnaBridge 153:b484a57bc302 41 /* CMSIS CA definitions */
AnnaBridge 153:b484a57bc302 42 #define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS HAL main version */
AnnaBridge 153:b484a57bc302 43 #define __CA_CMSIS_VERSION_SUB (0U) /*!< \brief [15:0] CMSIS HAL sub version */
AnnaBridge 153:b484a57bc302 44 #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 153:b484a57bc302 45 __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS HAL version number */
AnnaBridge 153:b484a57bc302 46
AnnaBridge 153:b484a57bc302 47 #if defined ( __CC_ARM )
AnnaBridge 153:b484a57bc302 48 #if defined __TARGET_FPU_VFP
AnnaBridge 153:b484a57bc302 49 #if (__FPU_PRESENT == 1)
AnnaBridge 153:b484a57bc302 50 #define __FPU_USED 1U
AnnaBridge 153:b484a57bc302 51 #else
AnnaBridge 153:b484a57bc302 52 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 153:b484a57bc302 53 #define __FPU_USED 0U
AnnaBridge 153:b484a57bc302 54 #endif
AnnaBridge 153:b484a57bc302 55 #else
AnnaBridge 153:b484a57bc302 56 #define __FPU_USED 0U
AnnaBridge 153:b484a57bc302 57 #endif
AnnaBridge 153:b484a57bc302 58
AnnaBridge 153:b484a57bc302 59 #elif defined ( __ICCARM__ )
AnnaBridge 153:b484a57bc302 60 #if defined __ARMVFP__
AnnaBridge 153:b484a57bc302 61 #if (__FPU_PRESENT == 1)
AnnaBridge 153:b484a57bc302 62 #define __FPU_USED 1U
AnnaBridge 153:b484a57bc302 63 #else
AnnaBridge 153:b484a57bc302 64 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 153:b484a57bc302 65 #define __FPU_USED 0U
AnnaBridge 153:b484a57bc302 66 #endif
AnnaBridge 153:b484a57bc302 67 #else
AnnaBridge 153:b484a57bc302 68 #define __FPU_USED 0U
AnnaBridge 153:b484a57bc302 69 #endif
AnnaBridge 153:b484a57bc302 70
AnnaBridge 153:b484a57bc302 71 #elif defined ( __TMS470__ )
AnnaBridge 153:b484a57bc302 72 #if defined __TI_VFP_SUPPORT__
AnnaBridge 153:b484a57bc302 73 #if (__FPU_PRESENT == 1)
AnnaBridge 153:b484a57bc302 74 #define __FPU_USED 1U
AnnaBridge 153:b484a57bc302 75 #else
AnnaBridge 153:b484a57bc302 76 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 153:b484a57bc302 77 #define __FPU_USED 0U
AnnaBridge 153:b484a57bc302 78 #endif
AnnaBridge 153:b484a57bc302 79 #else
AnnaBridge 153:b484a57bc302 80 #define __FPU_USED 0U
AnnaBridge 153:b484a57bc302 81 #endif
AnnaBridge 153:b484a57bc302 82
AnnaBridge 153:b484a57bc302 83 #elif defined ( __GNUC__ )
AnnaBridge 153:b484a57bc302 84 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 153:b484a57bc302 85 #if (__FPU_PRESENT == 1)
AnnaBridge 153:b484a57bc302 86 #define __FPU_USED 1U
AnnaBridge 153:b484a57bc302 87 #else
AnnaBridge 153:b484a57bc302 88 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 153:b484a57bc302 89 #define __FPU_USED 0U
AnnaBridge 153:b484a57bc302 90 #endif
AnnaBridge 153:b484a57bc302 91 #else
AnnaBridge 153:b484a57bc302 92 #define __FPU_USED 0U
AnnaBridge 153:b484a57bc302 93 #endif
AnnaBridge 153:b484a57bc302 94
AnnaBridge 153:b484a57bc302 95 #elif defined ( __TASKING__ )
AnnaBridge 153:b484a57bc302 96 #if defined __FPU_VFP__
AnnaBridge 153:b484a57bc302 97 #if (__FPU_PRESENT == 1)
AnnaBridge 153:b484a57bc302 98 #define __FPU_USED 1U
AnnaBridge 153:b484a57bc302 99 #else
AnnaBridge 153:b484a57bc302 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 153:b484a57bc302 101 #define __FPU_USED 0U
AnnaBridge 153:b484a57bc302 102 #endif
AnnaBridge 153:b484a57bc302 103 #else
AnnaBridge 153:b484a57bc302 104 #define __FPU_USED 0U
AnnaBridge 153:b484a57bc302 105 #endif
AnnaBridge 153:b484a57bc302 106 #endif
AnnaBridge 153:b484a57bc302 107
AnnaBridge 153:b484a57bc302 108 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 153:b484a57bc302 109
AnnaBridge 153:b484a57bc302 110 #ifdef __cplusplus
AnnaBridge 153:b484a57bc302 111 }
AnnaBridge 153:b484a57bc302 112 #endif
AnnaBridge 153:b484a57bc302 113
AnnaBridge 153:b484a57bc302 114 #endif /* __CORE_CA_H_GENERIC */
AnnaBridge 153:b484a57bc302 115
AnnaBridge 153:b484a57bc302 116 #ifndef __CMSIS_GENERIC
AnnaBridge 153:b484a57bc302 117
AnnaBridge 153:b484a57bc302 118 #ifndef __CORE_CA_H_DEPENDANT
AnnaBridge 153:b484a57bc302 119 #define __CORE_CA_H_DEPENDANT
AnnaBridge 153:b484a57bc302 120
AnnaBridge 153:b484a57bc302 121 #ifdef __cplusplus
AnnaBridge 153:b484a57bc302 122 extern "C" {
AnnaBridge 153:b484a57bc302 123 #endif
AnnaBridge 153:b484a57bc302 124
AnnaBridge 153:b484a57bc302 125 /* check device defines and use defaults */
AnnaBridge 153:b484a57bc302 126 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 153:b484a57bc302 127 #ifndef __CA_REV
AnnaBridge 153:b484a57bc302 128 #define __CA_REV 0x0000U
AnnaBridge 153:b484a57bc302 129 #warning "__CA_REV not defined in device header file; using default!"
AnnaBridge 153:b484a57bc302 130 #endif
AnnaBridge 153:b484a57bc302 131
AnnaBridge 153:b484a57bc302 132 #ifndef __FPU_PRESENT
AnnaBridge 153:b484a57bc302 133 #define __FPU_PRESENT 0U
AnnaBridge 153:b484a57bc302 134 #warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge 153:b484a57bc302 135 #endif
AnnaBridge 153:b484a57bc302 136
AnnaBridge 153:b484a57bc302 137 #ifndef __MPU_PRESENT
AnnaBridge 153:b484a57bc302 138 #define __MPU_PRESENT 0U
AnnaBridge 153:b484a57bc302 139 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 153:b484a57bc302 140 #endif
AnnaBridge 153:b484a57bc302 141
AnnaBridge 153:b484a57bc302 142 #ifndef __GIC_PRESENT
AnnaBridge 153:b484a57bc302 143 #define __GIC_PRESENT 1U
AnnaBridge 153:b484a57bc302 144 #warning "__GIC_PRESENT not defined in device header file; using default!"
AnnaBridge 153:b484a57bc302 145 #endif
AnnaBridge 153:b484a57bc302 146
AnnaBridge 153:b484a57bc302 147 #ifndef __TIM_PRESENT
AnnaBridge 153:b484a57bc302 148 #define __TIM_PRESENT 1U
AnnaBridge 153:b484a57bc302 149 #warning "__TIM_PRESENT not defined in device header file; using default!"
AnnaBridge 153:b484a57bc302 150 #endif
AnnaBridge 153:b484a57bc302 151
AnnaBridge 153:b484a57bc302 152 #ifndef __L2C_PRESENT
AnnaBridge 153:b484a57bc302 153 #define __L2C_PRESENT 0U
AnnaBridge 153:b484a57bc302 154 #warning "__L2C_PRESENT not defined in device header file; using default!"
AnnaBridge 153:b484a57bc302 155 #endif
AnnaBridge 153:b484a57bc302 156 #endif
AnnaBridge 153:b484a57bc302 157
AnnaBridge 153:b484a57bc302 158 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 153:b484a57bc302 159 #ifdef __cplusplus
AnnaBridge 153:b484a57bc302 160 #define __I volatile /*!< \brief Defines 'read only' permissions */
AnnaBridge 153:b484a57bc302 161 #else
AnnaBridge 153:b484a57bc302 162 #define __I volatile const /*!< \brief Defines 'read only' permissions */
AnnaBridge 153:b484a57bc302 163 #endif
AnnaBridge 153:b484a57bc302 164 #define __O volatile /*!< \brief Defines 'write only' permissions */
AnnaBridge 153:b484a57bc302 165 #define __IO volatile /*!< \brief Defines 'read / write' permissions */
AnnaBridge 153:b484a57bc302 166
AnnaBridge 153:b484a57bc302 167 /* following defines should be used for structure members */
AnnaBridge 153:b484a57bc302 168 #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */
AnnaBridge 153:b484a57bc302 169 #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */
AnnaBridge 153:b484a57bc302 170 #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */
AnnaBridge 153:b484a57bc302 171
AnnaBridge 153:b484a57bc302 172
AnnaBridge 153:b484a57bc302 173 /*******************************************************************************
AnnaBridge 153:b484a57bc302 174 * Register Abstraction
AnnaBridge 153:b484a57bc302 175 Core Register contain:
AnnaBridge 153:b484a57bc302 176 - CPSR
AnnaBridge 153:b484a57bc302 177 - CP15 Registers
AnnaBridge 153:b484a57bc302 178 - L2C-310 Cache Controller
AnnaBridge 153:b484a57bc302 179 - Generic Interrupt Controller Distributor
AnnaBridge 153:b484a57bc302 180 - Generic Interrupt Controller Interface
AnnaBridge 153:b484a57bc302 181 ******************************************************************************/
AnnaBridge 153:b484a57bc302 182
AnnaBridge 153:b484a57bc302 183 /* Core Register CPSR */
AnnaBridge 153:b484a57bc302 184 typedef union
AnnaBridge 153:b484a57bc302 185 {
AnnaBridge 153:b484a57bc302 186 struct
AnnaBridge 153:b484a57bc302 187 {
AnnaBridge 153:b484a57bc302 188 uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */
AnnaBridge 153:b484a57bc302 189 uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */
AnnaBridge 153:b484a57bc302 190 uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */
AnnaBridge 153:b484a57bc302 191 uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */
AnnaBridge 153:b484a57bc302 192 uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */
AnnaBridge 153:b484a57bc302 193 uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */
AnnaBridge 153:b484a57bc302 194 uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */
AnnaBridge 153:b484a57bc302 195 uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */
AnnaBridge 153:b484a57bc302 196 uint32_t _reserved0:4; /*!< \brief bit: 20..23 Reserved */
AnnaBridge 153:b484a57bc302 197 uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */
AnnaBridge 153:b484a57bc302 198 uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */
AnnaBridge 153:b484a57bc302 199 uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */
AnnaBridge 153:b484a57bc302 200 uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */
AnnaBridge 153:b484a57bc302 201 uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */
AnnaBridge 153:b484a57bc302 202 uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */
AnnaBridge 153:b484a57bc302 203 uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */
AnnaBridge 153:b484a57bc302 204 } b; /*!< \brief Structure used for bit access */
AnnaBridge 153:b484a57bc302 205 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 153:b484a57bc302 206 } CPSR_Type;
AnnaBridge 153:b484a57bc302 207
AnnaBridge 153:b484a57bc302 208 /* CPSR Register Definitions */
AnnaBridge 153:b484a57bc302 209 #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */
AnnaBridge 153:b484a57bc302 210 #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */
AnnaBridge 153:b484a57bc302 211
AnnaBridge 153:b484a57bc302 212 #define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */
AnnaBridge 153:b484a57bc302 213 #define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */
AnnaBridge 153:b484a57bc302 214
AnnaBridge 153:b484a57bc302 215 #define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */
AnnaBridge 153:b484a57bc302 216 #define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */
AnnaBridge 153:b484a57bc302 217
AnnaBridge 153:b484a57bc302 218 #define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */
AnnaBridge 153:b484a57bc302 219 #define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */
AnnaBridge 153:b484a57bc302 220
AnnaBridge 153:b484a57bc302 221 #define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */
AnnaBridge 153:b484a57bc302 222 #define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */
AnnaBridge 153:b484a57bc302 223
AnnaBridge 153:b484a57bc302 224 #define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */
AnnaBridge 153:b484a57bc302 225 #define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */
AnnaBridge 153:b484a57bc302 226
AnnaBridge 153:b484a57bc302 227 #define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */
AnnaBridge 153:b484a57bc302 228 #define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */
AnnaBridge 153:b484a57bc302 229
AnnaBridge 153:b484a57bc302 230 #define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */
AnnaBridge 153:b484a57bc302 231 #define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */
AnnaBridge 153:b484a57bc302 232
AnnaBridge 153:b484a57bc302 233 #define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */
AnnaBridge 153:b484a57bc302 234 #define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */
AnnaBridge 153:b484a57bc302 235
AnnaBridge 153:b484a57bc302 236 #define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */
AnnaBridge 153:b484a57bc302 237 #define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */
AnnaBridge 153:b484a57bc302 238
AnnaBridge 153:b484a57bc302 239 #define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */
AnnaBridge 153:b484a57bc302 240 #define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */
AnnaBridge 153:b484a57bc302 241
AnnaBridge 153:b484a57bc302 242 #define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */
AnnaBridge 153:b484a57bc302 243 #define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */
AnnaBridge 153:b484a57bc302 244
AnnaBridge 153:b484a57bc302 245 #define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */
AnnaBridge 153:b484a57bc302 246 #define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */
AnnaBridge 153:b484a57bc302 247
AnnaBridge 153:b484a57bc302 248 #define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */
AnnaBridge 153:b484a57bc302 249 #define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */
AnnaBridge 153:b484a57bc302 250
AnnaBridge 153:b484a57bc302 251 #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */
AnnaBridge 153:b484a57bc302 252 #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */
AnnaBridge 153:b484a57bc302 253
AnnaBridge 153:b484a57bc302 254 /* CP15 Register SCTLR */
AnnaBridge 153:b484a57bc302 255 typedef union
AnnaBridge 153:b484a57bc302 256 {
AnnaBridge 153:b484a57bc302 257 struct
AnnaBridge 153:b484a57bc302 258 {
AnnaBridge 153:b484a57bc302 259 uint32_t M:1; /*!< \brief bit: 0 MMU enable */
AnnaBridge 153:b484a57bc302 260 uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
AnnaBridge 153:b484a57bc302 261 uint32_t C:1; /*!< \brief bit: 2 Cache enable */
AnnaBridge 153:b484a57bc302 262 uint32_t _reserved0:2; /*!< \brief bit: 3.. 4 Reserved */
AnnaBridge 153:b484a57bc302 263 uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */
AnnaBridge 153:b484a57bc302 264 uint32_t _reserved1:1; /*!< \brief bit: 6 Reserved */
AnnaBridge 153:b484a57bc302 265 uint32_t B:1; /*!< \brief bit: 7 Endianness model */
AnnaBridge 153:b484a57bc302 266 uint32_t _reserved2:2; /*!< \brief bit: 8.. 9 Reserved */
AnnaBridge 153:b484a57bc302 267 uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */
AnnaBridge 153:b484a57bc302 268 uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */
AnnaBridge 153:b484a57bc302 269 uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
AnnaBridge 153:b484a57bc302 270 uint32_t V:1; /*!< \brief bit: 13 Vectors bit */
AnnaBridge 153:b484a57bc302 271 uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */
AnnaBridge 153:b484a57bc302 272 uint32_t _reserved3:2; /*!< \brief bit:15..16 Reserved */
AnnaBridge 153:b484a57bc302 273 uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */
AnnaBridge 153:b484a57bc302 274 uint32_t _reserved4:1; /*!< \brief bit: 18 Reserved */
AnnaBridge 153:b484a57bc302 275 uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */
AnnaBridge 153:b484a57bc302 276 uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */
AnnaBridge 153:b484a57bc302 277 uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
AnnaBridge 153:b484a57bc302 278 uint32_t U:1; /*!< \brief bit: 22 Alignment model */
AnnaBridge 153:b484a57bc302 279 uint32_t _reserved5:1; /*!< \brief bit: 23 Reserved */
AnnaBridge 153:b484a57bc302 280 uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */
AnnaBridge 153:b484a57bc302 281 uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
AnnaBridge 153:b484a57bc302 282 uint32_t _reserved6:1; /*!< \brief bit: 26 Reserved */
AnnaBridge 153:b484a57bc302 283 uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */
AnnaBridge 153:b484a57bc302 284 uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */
AnnaBridge 153:b484a57bc302 285 uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */
AnnaBridge 153:b484a57bc302 286 uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
AnnaBridge 153:b484a57bc302 287 uint32_t _reserved7:1; /*!< \brief bit: 31 Reserved */
AnnaBridge 153:b484a57bc302 288 } b; /*!< \brief Structure used for bit access */
AnnaBridge 153:b484a57bc302 289 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 153:b484a57bc302 290 } SCTLR_Type;
AnnaBridge 153:b484a57bc302 291
AnnaBridge 153:b484a57bc302 292 #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */
AnnaBridge 153:b484a57bc302 293 #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */
AnnaBridge 153:b484a57bc302 294
AnnaBridge 153:b484a57bc302 295 #define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */
AnnaBridge 153:b484a57bc302 296 #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */
AnnaBridge 153:b484a57bc302 297
AnnaBridge 153:b484a57bc302 298 #define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */
AnnaBridge 153:b484a57bc302 299 #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */
AnnaBridge 153:b484a57bc302 300
AnnaBridge 153:b484a57bc302 301 #define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */
AnnaBridge 153:b484a57bc302 302 #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */
AnnaBridge 153:b484a57bc302 303
AnnaBridge 153:b484a57bc302 304 #define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */
AnnaBridge 153:b484a57bc302 305 #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */
AnnaBridge 153:b484a57bc302 306
AnnaBridge 153:b484a57bc302 307 #define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */
AnnaBridge 153:b484a57bc302 308 #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */
AnnaBridge 153:b484a57bc302 309
AnnaBridge 153:b484a57bc302 310 #define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */
AnnaBridge 153:b484a57bc302 311 #define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */
AnnaBridge 153:b484a57bc302 312
AnnaBridge 153:b484a57bc302 313 #define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */
AnnaBridge 153:b484a57bc302 314 #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */
AnnaBridge 153:b484a57bc302 315
AnnaBridge 153:b484a57bc302 316 #define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */
AnnaBridge 153:b484a57bc302 317 #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */
AnnaBridge 153:b484a57bc302 318
AnnaBridge 153:b484a57bc302 319 #define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */
AnnaBridge 153:b484a57bc302 320 #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */
AnnaBridge 153:b484a57bc302 321
AnnaBridge 153:b484a57bc302 322 #define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */
AnnaBridge 153:b484a57bc302 323 #define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */
AnnaBridge 153:b484a57bc302 324
AnnaBridge 153:b484a57bc302 325 #define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */
AnnaBridge 153:b484a57bc302 326 #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */
AnnaBridge 153:b484a57bc302 327
AnnaBridge 153:b484a57bc302 328 #define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */
AnnaBridge 153:b484a57bc302 329 #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */
AnnaBridge 153:b484a57bc302 330
AnnaBridge 153:b484a57bc302 331 #define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */
AnnaBridge 153:b484a57bc302 332 #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */
AnnaBridge 153:b484a57bc302 333
AnnaBridge 153:b484a57bc302 334 #define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */
AnnaBridge 153:b484a57bc302 335 #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */
AnnaBridge 153:b484a57bc302 336
AnnaBridge 153:b484a57bc302 337 #define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */
AnnaBridge 153:b484a57bc302 338 #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */
AnnaBridge 153:b484a57bc302 339
AnnaBridge 153:b484a57bc302 340 #define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */
AnnaBridge 153:b484a57bc302 341 #define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */
AnnaBridge 153:b484a57bc302 342
AnnaBridge 153:b484a57bc302 343 #define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */
AnnaBridge 153:b484a57bc302 344 #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */
AnnaBridge 153:b484a57bc302 345
AnnaBridge 153:b484a57bc302 346 #define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */
AnnaBridge 153:b484a57bc302 347 #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */
AnnaBridge 153:b484a57bc302 348
AnnaBridge 153:b484a57bc302 349 #define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */
AnnaBridge 153:b484a57bc302 350 #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */
AnnaBridge 153:b484a57bc302 351
AnnaBridge 153:b484a57bc302 352 #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */
AnnaBridge 153:b484a57bc302 353 #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */
AnnaBridge 153:b484a57bc302 354
AnnaBridge 153:b484a57bc302 355 /* CP15 Register CPACR */
AnnaBridge 153:b484a57bc302 356 typedef union
AnnaBridge 153:b484a57bc302 357 {
AnnaBridge 153:b484a57bc302 358 struct
AnnaBridge 153:b484a57bc302 359 {
AnnaBridge 153:b484a57bc302 360 uint32_t _reserved0:20; /*!< \brief bit: 0..19 Reserved */
AnnaBridge 153:b484a57bc302 361 uint32_t cp10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */
AnnaBridge 153:b484a57bc302 362 uint32_t cp11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */
AnnaBridge 153:b484a57bc302 363 uint32_t _reserved1:6; /*!< \brief bit:24..29 Reserved */
AnnaBridge 153:b484a57bc302 364 uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */
AnnaBridge 153:b484a57bc302 365 uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */
AnnaBridge 153:b484a57bc302 366 } b; /*!< \brief Structure used for bit access */
AnnaBridge 153:b484a57bc302 367 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 153:b484a57bc302 368 } CPACR_Type;
AnnaBridge 153:b484a57bc302 369
AnnaBridge 153:b484a57bc302 370 #define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */
AnnaBridge 153:b484a57bc302 371 #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */
AnnaBridge 153:b484a57bc302 372
AnnaBridge 153:b484a57bc302 373 #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */
AnnaBridge 153:b484a57bc302 374 #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
AnnaBridge 153:b484a57bc302 375
AnnaBridge 153:b484a57bc302 376 #define CPACR_cp11_Pos 22U /*!< \brief CPACR: cp11 Position */
AnnaBridge 153:b484a57bc302 377 #define CPACR_cp11_Msk (3UL << CPACR_cp11_Pos) /*!< \brief CPACR: cp11 Mask */
AnnaBridge 153:b484a57bc302 378
AnnaBridge 153:b484a57bc302 379 #define CPACR_cp10_Pos 20U /*!< \brief CPACR: cp10 Position */
AnnaBridge 153:b484a57bc302 380 #define CPACR_cp10_Msk (3UL << CPACR_cp10_Pos) /*!< \brief CPACR: cp10 Mask */
AnnaBridge 153:b484a57bc302 381
AnnaBridge 153:b484a57bc302 382 /* CP15 Register DFSR */
AnnaBridge 153:b484a57bc302 383 typedef union
AnnaBridge 153:b484a57bc302 384 {
AnnaBridge 153:b484a57bc302 385 struct
AnnaBridge 153:b484a57bc302 386 {
AnnaBridge 153:b484a57bc302 387 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
AnnaBridge 153:b484a57bc302 388 uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */
AnnaBridge 153:b484a57bc302 389 uint32_t _reserved0:2; /*!< \brief bit: 8.. 9 Reserved */
AnnaBridge 153:b484a57bc302 390 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
AnnaBridge 153:b484a57bc302 391 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
AnnaBridge 153:b484a57bc302 392 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
AnnaBridge 153:b484a57bc302 393 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
AnnaBridge 153:b484a57bc302 394 uint32_t _reserved1:18; /*!< \brief bit:14..31 Reserved */
AnnaBridge 153:b484a57bc302 395 } b; /*!< \brief Structure used for bit access */
AnnaBridge 153:b484a57bc302 396 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 153:b484a57bc302 397 } DFSR_Type;
AnnaBridge 153:b484a57bc302 398
AnnaBridge 153:b484a57bc302 399 #define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */
AnnaBridge 153:b484a57bc302 400 #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */
AnnaBridge 153:b484a57bc302 401
AnnaBridge 153:b484a57bc302 402 #define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */
AnnaBridge 153:b484a57bc302 403 #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */
AnnaBridge 153:b484a57bc302 404
AnnaBridge 153:b484a57bc302 405 #define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */
AnnaBridge 153:b484a57bc302 406 #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */
AnnaBridge 153:b484a57bc302 407
AnnaBridge 153:b484a57bc302 408 #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */
AnnaBridge 153:b484a57bc302 409 #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */
AnnaBridge 153:b484a57bc302 410
AnnaBridge 153:b484a57bc302 411 #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */
AnnaBridge 153:b484a57bc302 412 #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */
AnnaBridge 153:b484a57bc302 413
AnnaBridge 153:b484a57bc302 414 #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */
AnnaBridge 153:b484a57bc302 415 #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */
AnnaBridge 153:b484a57bc302 416
AnnaBridge 153:b484a57bc302 417 /* CP15 Register IFSR */
AnnaBridge 153:b484a57bc302 418 typedef union
AnnaBridge 153:b484a57bc302 419 {
AnnaBridge 153:b484a57bc302 420 struct
AnnaBridge 153:b484a57bc302 421 {
AnnaBridge 153:b484a57bc302 422 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
AnnaBridge 153:b484a57bc302 423 uint32_t _reserved0:6; /*!< \brief bit: 4.. 9 Reserved */
AnnaBridge 153:b484a57bc302 424 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
AnnaBridge 153:b484a57bc302 425 uint32_t _reserved1:1; /*!< \brief bit: 11 Reserved */
AnnaBridge 153:b484a57bc302 426 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
AnnaBridge 153:b484a57bc302 427 uint32_t _reserved2:19; /*!< \brief bit:13..31 Reserved */
AnnaBridge 153:b484a57bc302 428 } b; /*!< \brief Structure used for bit access */
AnnaBridge 153:b484a57bc302 429 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 153:b484a57bc302 430 } IFSR_Type;
AnnaBridge 153:b484a57bc302 431
AnnaBridge 153:b484a57bc302 432 #define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */
AnnaBridge 153:b484a57bc302 433 #define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */
AnnaBridge 153:b484a57bc302 434
AnnaBridge 153:b484a57bc302 435 #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */
AnnaBridge 153:b484a57bc302 436 #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */
AnnaBridge 153:b484a57bc302 437
AnnaBridge 153:b484a57bc302 438 #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */
AnnaBridge 153:b484a57bc302 439 #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */
AnnaBridge 153:b484a57bc302 440
AnnaBridge 153:b484a57bc302 441 /* CP15 Register ISR */
AnnaBridge 153:b484a57bc302 442 typedef union
AnnaBridge 153:b484a57bc302 443 {
AnnaBridge 153:b484a57bc302 444 struct
AnnaBridge 153:b484a57bc302 445 {
AnnaBridge 153:b484a57bc302 446 uint32_t _reserved0:6; /*!< \brief bit: 0.. 5 Reserved */
AnnaBridge 153:b484a57bc302 447 uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */
AnnaBridge 153:b484a57bc302 448 uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */
AnnaBridge 153:b484a57bc302 449 uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */
AnnaBridge 153:b484a57bc302 450 uint32_t _reserved1:23; /*!< \brief bit:14..31 Reserved */
AnnaBridge 153:b484a57bc302 451 } b; /*!< \brief Structure used for bit access */
AnnaBridge 153:b484a57bc302 452 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 153:b484a57bc302 453 } ISR_Type;
AnnaBridge 153:b484a57bc302 454
AnnaBridge 153:b484a57bc302 455 #define ISR_A_Pos 13U /*!< \brief ISR: A Position */
AnnaBridge 153:b484a57bc302 456 #define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */
AnnaBridge 153:b484a57bc302 457
AnnaBridge 153:b484a57bc302 458 #define ISR_I_Pos 12U /*!< \brief ISR: I Position */
AnnaBridge 153:b484a57bc302 459 #define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */
AnnaBridge 153:b484a57bc302 460
AnnaBridge 153:b484a57bc302 461 #define ISR_F_Pos 11U /*!< \brief ISR: F Position */
AnnaBridge 153:b484a57bc302 462 #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */
AnnaBridge 153:b484a57bc302 463
AnnaBridge 153:b484a57bc302 464
AnnaBridge 153:b484a57bc302 465 /**
AnnaBridge 153:b484a57bc302 466 \brief Union type to access the L2C_310 Cache Controller.
AnnaBridge 153:b484a57bc302 467 */
AnnaBridge 153:b484a57bc302 468 #if (__L2C_PRESENT == 1U)
AnnaBridge 153:b484a57bc302 469 typedef struct
AnnaBridge 153:b484a57bc302 470 {
AnnaBridge 153:b484a57bc302 471 __I uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 Cache ID Register */
AnnaBridge 153:b484a57bc302 472 __I uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 Cache Type Register */
AnnaBridge 153:b484a57bc302 473 uint32_t RESERVED0[0x3e];
AnnaBridge 153:b484a57bc302 474 __IO uint32_t CONTROL; /*!< \brief Offset: 0x0100 Control Register */
AnnaBridge 153:b484a57bc302 475 __IO uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 Auxiliary Control */
AnnaBridge 153:b484a57bc302 476 uint32_t RESERVED1[0x3e];
AnnaBridge 153:b484a57bc302 477 __IO uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 Event Counter Control */
AnnaBridge 153:b484a57bc302 478 __IO uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 Event Counter 1 Configuration */
AnnaBridge 153:b484a57bc302 479 __IO uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 Event Counter 1 Configuration */
AnnaBridge 153:b484a57bc302 480 uint32_t RESERVED2[0x2];
AnnaBridge 153:b484a57bc302 481 __IO uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 Interrupt Mask */
AnnaBridge 153:b484a57bc302 482 __I uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 Masked Interrupt Status */
AnnaBridge 153:b484a57bc302 483 __I uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c Raw Interrupt Status */
AnnaBridge 153:b484a57bc302 484 __O uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 Interrupt Clear */
AnnaBridge 153:b484a57bc302 485 uint32_t RESERVED3[0x143];
AnnaBridge 153:b484a57bc302 486 __IO uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 Cache Sync */
AnnaBridge 153:b484a57bc302 487 uint32_t RESERVED4[0xf];
AnnaBridge 153:b484a57bc302 488 __IO uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 Invalidate Line By PA */
AnnaBridge 153:b484a57bc302 489 uint32_t RESERVED6[2];
AnnaBridge 153:b484a57bc302 490 __IO uint32_t INV_WAY; /*!< \brief Offset: 0x077c Invalidate by Way */
AnnaBridge 153:b484a57bc302 491 uint32_t RESERVED5[0xc];
AnnaBridge 153:b484a57bc302 492 __IO uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 Clean Line by PA */
AnnaBridge 153:b484a57bc302 493 uint32_t RESERVED7[1];
AnnaBridge 153:b484a57bc302 494 __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 Clean Line by Index/Way */
AnnaBridge 153:b484a57bc302 495 __IO uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc Clean by Way */
AnnaBridge 153:b484a57bc302 496 uint32_t RESERVED8[0xc];
AnnaBridge 153:b484a57bc302 497 __IO uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 Clean and Invalidate Line by PA */
AnnaBridge 153:b484a57bc302 498 uint32_t RESERVED9[1];
AnnaBridge 153:b484a57bc302 499 __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 Clean and Invalidate Line by Index/Way */
AnnaBridge 153:b484a57bc302 500 __IO uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc Clean and Invalidate by Way */
AnnaBridge 153:b484a57bc302 501 uint32_t RESERVED10[0x40];
AnnaBridge 153:b484a57bc302 502 __IO uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 Data Lockdown 0 by Way */
AnnaBridge 153:b484a57bc302 503 __IO uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 Instruction Lockdown 0 by Way */
AnnaBridge 153:b484a57bc302 504 __IO uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 Data Lockdown 1 by Way */
AnnaBridge 153:b484a57bc302 505 __IO uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c Instruction Lockdown 1 by Way */
AnnaBridge 153:b484a57bc302 506 __IO uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 Data Lockdown 2 by Way */
AnnaBridge 153:b484a57bc302 507 __IO uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 Instruction Lockdown 2 by Way */
AnnaBridge 153:b484a57bc302 508 __IO uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 Data Lockdown 3 by Way */
AnnaBridge 153:b484a57bc302 509 __IO uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c Instruction Lockdown 3 by Way */
AnnaBridge 153:b484a57bc302 510 __IO uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 Data Lockdown 4 by Way */
AnnaBridge 153:b484a57bc302 511 __IO uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 Instruction Lockdown 4 by Way */
AnnaBridge 153:b484a57bc302 512 __IO uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 Data Lockdown 5 by Way */
AnnaBridge 153:b484a57bc302 513 __IO uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c Instruction Lockdown 5 by Way */
AnnaBridge 153:b484a57bc302 514 __IO uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 Data Lockdown 5 by Way */
AnnaBridge 153:b484a57bc302 515 __IO uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 Instruction Lockdown 5 by Way */
AnnaBridge 153:b484a57bc302 516 __IO uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 Data Lockdown 6 by Way */
AnnaBridge 153:b484a57bc302 517 __IO uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c Instruction Lockdown 6 by Way */
AnnaBridge 153:b484a57bc302 518 uint32_t RESERVED11[0x4];
AnnaBridge 153:b484a57bc302 519 __IO uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 Lockdown by Line Enable */
AnnaBridge 153:b484a57bc302 520 __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 Unlock All Lines by Way */
AnnaBridge 153:b484a57bc302 521 uint32_t RESERVED12[0xaa];
AnnaBridge 153:b484a57bc302 522 __IO uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 Address Filtering Start */
AnnaBridge 153:b484a57bc302 523 __IO uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 Address Filtering End */
AnnaBridge 153:b484a57bc302 524 uint32_t RESERVED13[0xce];
AnnaBridge 153:b484a57bc302 525 __IO uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 Debug Control Register */
AnnaBridge 153:b484a57bc302 526 } L2C_310_TypeDef;
AnnaBridge 153:b484a57bc302 527
AnnaBridge 153:b484a57bc302 528 #define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 Declaration */
AnnaBridge 153:b484a57bc302 529 #endif
AnnaBridge 153:b484a57bc302 530
AnnaBridge 153:b484a57bc302 531 #if (__GIC_PRESENT == 1U)
AnnaBridge 153:b484a57bc302 532 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
AnnaBridge 153:b484a57bc302 533 */
AnnaBridge 153:b484a57bc302 534 typedef struct
AnnaBridge 153:b484a57bc302 535 {
AnnaBridge 153:b484a57bc302 536 __IO uint32_t ICDDCR;
AnnaBridge 153:b484a57bc302 537 __I uint32_t ICDICTR;
AnnaBridge 153:b484a57bc302 538 __I uint32_t ICDIIDR;
AnnaBridge 153:b484a57bc302 539 uint32_t RESERVED0[29];
AnnaBridge 153:b484a57bc302 540 __IO uint32_t ICDISR[32];
AnnaBridge 153:b484a57bc302 541 __IO uint32_t ICDISER[32];
AnnaBridge 153:b484a57bc302 542 __IO uint32_t ICDICER[32];
AnnaBridge 153:b484a57bc302 543 __IO uint32_t ICDISPR[32];
AnnaBridge 153:b484a57bc302 544 __IO uint32_t ICDICPR[32];
AnnaBridge 153:b484a57bc302 545 __I uint32_t ICDABR[32];
AnnaBridge 153:b484a57bc302 546 uint32_t RESERVED1[32];
AnnaBridge 153:b484a57bc302 547 __IO uint32_t ICDIPR[256];
AnnaBridge 153:b484a57bc302 548 __IO uint32_t ICDIPTR[256];
AnnaBridge 153:b484a57bc302 549 __IO uint32_t ICDICFR[64];
AnnaBridge 153:b484a57bc302 550 uint32_t RESERVED2[128];
AnnaBridge 153:b484a57bc302 551 __IO uint32_t ICDSGIR;
AnnaBridge 153:b484a57bc302 552 } GICDistributor_Type;
AnnaBridge 153:b484a57bc302 553
AnnaBridge 153:b484a57bc302 554 #define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
AnnaBridge 153:b484a57bc302 555
AnnaBridge 153:b484a57bc302 556 /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
AnnaBridge 153:b484a57bc302 557 */
AnnaBridge 153:b484a57bc302 558 typedef struct
AnnaBridge 153:b484a57bc302 559 {
AnnaBridge 153:b484a57bc302 560 __IO uint32_t ICCICR; //!< \brief +0x000 - RW - CPU Interface Control Register
AnnaBridge 153:b484a57bc302 561 __IO uint32_t ICCPMR; //!< \brief +0x004 - RW - Interrupt Priority Mask Register
AnnaBridge 153:b484a57bc302 562 __IO uint32_t ICCBPR; //!< \brief +0x008 - RW - Binary Point Register
AnnaBridge 153:b484a57bc302 563 __I uint32_t ICCIAR; //!< \brief +0x00C - RO - Interrupt Acknowledge Register
AnnaBridge 153:b484a57bc302 564 __IO uint32_t ICCEOIR; //!< \brief +0x010 - WO - End of Interrupt Register
AnnaBridge 153:b484a57bc302 565 __I uint32_t ICCRPR; //!< \brief +0x014 - RO - Running Priority Register
AnnaBridge 153:b484a57bc302 566 __I uint32_t ICCHPIR; //!< \brief +0x018 - RO - Highest Pending Interrupt Register
AnnaBridge 153:b484a57bc302 567 __IO uint32_t ICCABPR; //!< \brief +0x01C - RW - Aliased Binary Point Register
AnnaBridge 153:b484a57bc302 568 uint32_t RESERVED[55];
AnnaBridge 153:b484a57bc302 569 __I uint32_t ICCIIDR; //!< \brief +0x0FC - RO - CPU Interface Identification Register
AnnaBridge 153:b484a57bc302 570 } GICInterface_Type;
AnnaBridge 153:b484a57bc302 571
AnnaBridge 153:b484a57bc302 572 #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */
AnnaBridge 153:b484a57bc302 573 #endif
AnnaBridge 153:b484a57bc302 574
AnnaBridge 153:b484a57bc302 575 #if (__TIM_PRESENT == 1U)
AnnaBridge 153:b484a57bc302 576 #if ((__CORTEX_A == 5U)||(__CORTEX_A == 9U))
AnnaBridge 153:b484a57bc302 577 /** \brief Structure type to access the Private Timer
AnnaBridge 153:b484a57bc302 578 */
AnnaBridge 153:b484a57bc302 579 typedef struct
AnnaBridge 153:b484a57bc302 580 {
AnnaBridge 153:b484a57bc302 581 __IO uint32_t LOAD; //!< \brief +0x000 - RW - Private Timer Load Register
AnnaBridge 153:b484a57bc302 582 __IO uint32_t COUNTER; //!< \brief +0x004 - RW - Private Timer Counter Register
AnnaBridge 153:b484a57bc302 583 __IO uint32_t CONTROL; //!< \brief +0x008 - RW - Private Timer Control Register
AnnaBridge 153:b484a57bc302 584 __IO uint32_t ISR; //!< \brief +0x00C - RO - Private Timer Interrupt Status Register
AnnaBridge 153:b484a57bc302 585 uint32_t RESERVED[8];
AnnaBridge 153:b484a57bc302 586 __IO uint32_t WLOAD; //!< \brief +0x020 - RW - Watchdog Load Register
AnnaBridge 153:b484a57bc302 587 __IO uint32_t WCOUNTER; //!< \brief +0x024 - RW - Watchdog Counter Register
AnnaBridge 153:b484a57bc302 588 __IO uint32_t WCONTROL; //!< \brief +0x028 - RW - Watchdog Control Register
AnnaBridge 153:b484a57bc302 589 __IO uint32_t WISR; //!< \brief +0x02C - RW - Watchdog Interrupt Status Register
AnnaBridge 153:b484a57bc302 590 __IO uint32_t WRESET; //!< \brief +0x030 - RW - Watchdog Reset Status Register
AnnaBridge 153:b484a57bc302 591 __I uint32_t WDISABLE; //!< \brief +0x0FC - RO - Watchdog Disable Register
AnnaBridge 153:b484a57bc302 592 } Timer_Type;
AnnaBridge 153:b484a57bc302 593 #define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer configuration struct */
AnnaBridge 153:b484a57bc302 594 #endif
AnnaBridge 153:b484a57bc302 595 #endif
AnnaBridge 153:b484a57bc302 596
AnnaBridge 153:b484a57bc302 597 /*******************************************************************************
AnnaBridge 153:b484a57bc302 598 * Hardware Abstraction Layer
AnnaBridge 153:b484a57bc302 599 Core Function Interface contains:
AnnaBridge 153:b484a57bc302 600 - L1 Cache Functions
AnnaBridge 153:b484a57bc302 601 - L2C-310 Cache Controller Functions
AnnaBridge 153:b484a57bc302 602 - PL1 Timer Functions
AnnaBridge 153:b484a57bc302 603 - GIC Functions
AnnaBridge 153:b484a57bc302 604 - MMU Functions
AnnaBridge 153:b484a57bc302 605 ******************************************************************************/
AnnaBridge 153:b484a57bc302 606
AnnaBridge 153:b484a57bc302 607 /* ########################## L1 Cache functions ################################# */
AnnaBridge 153:b484a57bc302 608
AnnaBridge 153:b484a57bc302 609 /** \brief Enable Caches
AnnaBridge 153:b484a57bc302 610
AnnaBridge 153:b484a57bc302 611 Enable Caches
AnnaBridge 153:b484a57bc302 612 */
AnnaBridge 153:b484a57bc302 613 __STATIC_INLINE void L1C_EnableCaches(void) {
AnnaBridge 153:b484a57bc302 614 // Set I bit 12 to enable I Cache
AnnaBridge 153:b484a57bc302 615 // Set C bit 2 to enable D Cache
AnnaBridge 153:b484a57bc302 616 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 153:b484a57bc302 617 }
AnnaBridge 153:b484a57bc302 618
AnnaBridge 153:b484a57bc302 619 /** \brief Disable Caches
AnnaBridge 153:b484a57bc302 620
AnnaBridge 153:b484a57bc302 621 Disable Caches
AnnaBridge 153:b484a57bc302 622 */
AnnaBridge 153:b484a57bc302 623 __STATIC_INLINE void L1C_DisableCaches(void) {
AnnaBridge 153:b484a57bc302 624 // Clear I bit 12 to disable I Cache
AnnaBridge 153:b484a57bc302 625 // Clear C bit 2 to disable D Cache
AnnaBridge 153:b484a57bc302 626 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
AnnaBridge 153:b484a57bc302 627 __ISB();
AnnaBridge 153:b484a57bc302 628 }
AnnaBridge 153:b484a57bc302 629
AnnaBridge 153:b484a57bc302 630 /** \brief Enable BTAC
AnnaBridge 153:b484a57bc302 631
AnnaBridge 153:b484a57bc302 632 Enable BTAC
AnnaBridge 153:b484a57bc302 633 */
AnnaBridge 153:b484a57bc302 634 __STATIC_INLINE void L1C_EnableBTAC(void) {
AnnaBridge 153:b484a57bc302 635 // Set Z bit 11 to enable branch prediction
AnnaBridge 153:b484a57bc302 636 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 153:b484a57bc302 637 __ISB();
AnnaBridge 153:b484a57bc302 638 }
AnnaBridge 153:b484a57bc302 639
AnnaBridge 153:b484a57bc302 640 /** \brief Disable BTAC
AnnaBridge 153:b484a57bc302 641
AnnaBridge 153:b484a57bc302 642 Disable BTAC
AnnaBridge 153:b484a57bc302 643 */
AnnaBridge 153:b484a57bc302 644 __STATIC_INLINE void L1C_DisableBTAC(void) {
AnnaBridge 153:b484a57bc302 645 // Clear Z bit 11 to disable branch prediction
AnnaBridge 153:b484a57bc302 646 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
AnnaBridge 153:b484a57bc302 647 }
AnnaBridge 153:b484a57bc302 648
AnnaBridge 153:b484a57bc302 649 /** \brief Invalidate entire branch predictor array
AnnaBridge 153:b484a57bc302 650
AnnaBridge 153:b484a57bc302 651 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 153:b484a57bc302 652 */
AnnaBridge 153:b484a57bc302 653
AnnaBridge 153:b484a57bc302 654 __STATIC_INLINE void L1C_InvalidateBTAC(void) {
AnnaBridge 153:b484a57bc302 655 __set_BPIALL(0);
AnnaBridge 153:b484a57bc302 656 __DSB(); //ensure completion of the invalidation
AnnaBridge 153:b484a57bc302 657 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 153:b484a57bc302 658 }
AnnaBridge 153:b484a57bc302 659
AnnaBridge 153:b484a57bc302 660 /** \brief Invalidate the whole I$
AnnaBridge 153:b484a57bc302 661
AnnaBridge 153:b484a57bc302 662 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 153:b484a57bc302 663 */
AnnaBridge 153:b484a57bc302 664 __STATIC_INLINE void L1C_InvalidateICacheAll(void) {
AnnaBridge 153:b484a57bc302 665 __set_ICIALLU(0);
AnnaBridge 153:b484a57bc302 666 __DSB(); //ensure completion of the invalidation
AnnaBridge 153:b484a57bc302 667 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 153:b484a57bc302 668 }
AnnaBridge 153:b484a57bc302 669
AnnaBridge 153:b484a57bc302 670 /** \brief Clean D$ by MVA
AnnaBridge 153:b484a57bc302 671
AnnaBridge 153:b484a57bc302 672 DCCMVAC. Data cache clean by MVA to PoC
AnnaBridge 153:b484a57bc302 673 */
AnnaBridge 153:b484a57bc302 674 __STATIC_INLINE void L1C_CleanDCacheMVA(void *va) {
AnnaBridge 153:b484a57bc302 675 __set_DCCMVAC((uint32_t)va);
AnnaBridge 153:b484a57bc302 676 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 153:b484a57bc302 677 }
AnnaBridge 153:b484a57bc302 678
AnnaBridge 153:b484a57bc302 679 /** \brief Invalidate D$ by MVA
AnnaBridge 153:b484a57bc302 680
AnnaBridge 153:b484a57bc302 681 DCIMVAC. Data cache invalidate by MVA to PoC
AnnaBridge 153:b484a57bc302 682 */
AnnaBridge 153:b484a57bc302 683 __STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) {
AnnaBridge 153:b484a57bc302 684 __set_DCIMVAC((uint32_t)va);
AnnaBridge 153:b484a57bc302 685 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 153:b484a57bc302 686 }
AnnaBridge 153:b484a57bc302 687
AnnaBridge 153:b484a57bc302 688 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 153:b484a57bc302 689
AnnaBridge 153:b484a57bc302 690 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 153:b484a57bc302 691 */
AnnaBridge 153:b484a57bc302 692 __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
AnnaBridge 153:b484a57bc302 693 __set_DCCIMVAC((uint32_t)va);
AnnaBridge 153:b484a57bc302 694 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 153:b484a57bc302 695 }
AnnaBridge 153:b484a57bc302 696
AnnaBridge 153:b484a57bc302 697 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 153:b484a57bc302 698
AnnaBridge 153:b484a57bc302 699 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
AnnaBridge 153:b484a57bc302 700 */
AnnaBridge 153:b484a57bc302 701 __STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) {
AnnaBridge 153:b484a57bc302 702 __L1C_CleanInvalidateCache(op); // compiler specific call
AnnaBridge 153:b484a57bc302 703 }
AnnaBridge 153:b484a57bc302 704
AnnaBridge 153:b484a57bc302 705
AnnaBridge 153:b484a57bc302 706 /** \brief Invalidate the whole D$
AnnaBridge 153:b484a57bc302 707
AnnaBridge 153:b484a57bc302 708 DCISW. Invalidate by Set/Way
AnnaBridge 153:b484a57bc302 709 */
AnnaBridge 153:b484a57bc302 710
AnnaBridge 153:b484a57bc302 711 __STATIC_INLINE void L1C_InvalidateDCacheAll(void) {
AnnaBridge 153:b484a57bc302 712 L1C_CleanInvalidateCache(0);
AnnaBridge 153:b484a57bc302 713 }
AnnaBridge 153:b484a57bc302 714
AnnaBridge 153:b484a57bc302 715 /** \brief Clean the whole D$
AnnaBridge 153:b484a57bc302 716
AnnaBridge 153:b484a57bc302 717 DCCSW. Clean by Set/Way
AnnaBridge 153:b484a57bc302 718 */
AnnaBridge 153:b484a57bc302 719
AnnaBridge 153:b484a57bc302 720 __STATIC_INLINE void L1C_CleanDCacheAll(void) {
AnnaBridge 153:b484a57bc302 721 L1C_CleanInvalidateCache(1);
AnnaBridge 153:b484a57bc302 722 }
AnnaBridge 153:b484a57bc302 723
AnnaBridge 153:b484a57bc302 724 /** \brief Clean and invalidate the whole D$
AnnaBridge 153:b484a57bc302 725
AnnaBridge 153:b484a57bc302 726 DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 153:b484a57bc302 727 */
AnnaBridge 153:b484a57bc302 728
AnnaBridge 153:b484a57bc302 729 __STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) {
AnnaBridge 153:b484a57bc302 730 L1C_CleanInvalidateCache(2);
AnnaBridge 153:b484a57bc302 731 }
AnnaBridge 153:b484a57bc302 732
AnnaBridge 153:b484a57bc302 733
AnnaBridge 153:b484a57bc302 734 /* ########################## L2 Cache functions ################################# */
AnnaBridge 153:b484a57bc302 735 #if (__L2C_PRESENT == 1U)
AnnaBridge 153:b484a57bc302 736 //Cache Sync operation
AnnaBridge 153:b484a57bc302 737 __STATIC_INLINE void L2C_Sync(void)
AnnaBridge 153:b484a57bc302 738 {
AnnaBridge 153:b484a57bc302 739 L2C_310->CACHE_SYNC = 0x0;
AnnaBridge 153:b484a57bc302 740 }
AnnaBridge 153:b484a57bc302 741
AnnaBridge 153:b484a57bc302 742 //return Cache controller cache ID
AnnaBridge 153:b484a57bc302 743 __STATIC_INLINE int L2C_GetID (void)
AnnaBridge 153:b484a57bc302 744 {
AnnaBridge 153:b484a57bc302 745 return L2C_310->CACHE_ID;
AnnaBridge 153:b484a57bc302 746 }
AnnaBridge 153:b484a57bc302 747
AnnaBridge 153:b484a57bc302 748 //return Cache controller cache Type
AnnaBridge 153:b484a57bc302 749 __STATIC_INLINE int L2C_GetType (void)
AnnaBridge 153:b484a57bc302 750 {
AnnaBridge 153:b484a57bc302 751 return L2C_310->CACHE_TYPE;
AnnaBridge 153:b484a57bc302 752 }
AnnaBridge 153:b484a57bc302 753
AnnaBridge 153:b484a57bc302 754 //Invalidate all cache by way
AnnaBridge 153:b484a57bc302 755 __STATIC_INLINE void L2C_InvAllByWay (void)
AnnaBridge 153:b484a57bc302 756 {
AnnaBridge 153:b484a57bc302 757 unsigned int assoc;
AnnaBridge 153:b484a57bc302 758
AnnaBridge 153:b484a57bc302 759 if (L2C_310->AUX_CNT & (1<<16))
AnnaBridge 153:b484a57bc302 760 assoc = 16;
AnnaBridge 153:b484a57bc302 761 else
AnnaBridge 153:b484a57bc302 762 assoc = 8;
AnnaBridge 153:b484a57bc302 763
AnnaBridge 153:b484a57bc302 764 L2C_310->INV_WAY = (1 << assoc) - 1;
AnnaBridge 153:b484a57bc302 765 while(L2C_310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
AnnaBridge 153:b484a57bc302 766
AnnaBridge 153:b484a57bc302 767 L2C_Sync();
AnnaBridge 153:b484a57bc302 768 }
AnnaBridge 153:b484a57bc302 769
AnnaBridge 153:b484a57bc302 770 //Clean and Invalidate all cache by way
AnnaBridge 153:b484a57bc302 771 __STATIC_INLINE void L2C_CleanInvAllByWay (void)
AnnaBridge 153:b484a57bc302 772 {
AnnaBridge 153:b484a57bc302 773 unsigned int assoc;
AnnaBridge 153:b484a57bc302 774
AnnaBridge 153:b484a57bc302 775 if (L2C_310->AUX_CNT & (1<<16))
AnnaBridge 153:b484a57bc302 776 assoc = 16;
AnnaBridge 153:b484a57bc302 777 else
AnnaBridge 153:b484a57bc302 778 assoc = 8;
AnnaBridge 153:b484a57bc302 779
AnnaBridge 153:b484a57bc302 780 L2C_310->CLEAN_INV_WAY = (1 << assoc) - 1;
AnnaBridge 153:b484a57bc302 781 while(L2C_310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
AnnaBridge 153:b484a57bc302 782
AnnaBridge 153:b484a57bc302 783 L2C_Sync();
AnnaBridge 153:b484a57bc302 784 }
AnnaBridge 153:b484a57bc302 785
AnnaBridge 153:b484a57bc302 786 //Enable Cache
AnnaBridge 153:b484a57bc302 787 __STATIC_INLINE void L2C_Enable(void)
AnnaBridge 153:b484a57bc302 788 {
AnnaBridge 153:b484a57bc302 789 L2C_310->CONTROL = 0;
AnnaBridge 153:b484a57bc302 790 L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
AnnaBridge 153:b484a57bc302 791 L2C_310->DEBUG_CONTROL = 0;
AnnaBridge 153:b484a57bc302 792 L2C_310->DATA_LOCK_0_WAY = 0;
AnnaBridge 153:b484a57bc302 793 L2C_310->CACHE_SYNC = 0;
AnnaBridge 153:b484a57bc302 794 L2C_310->CONTROL = 0x01;
AnnaBridge 153:b484a57bc302 795 L2C_Sync();
AnnaBridge 153:b484a57bc302 796 }
AnnaBridge 153:b484a57bc302 797 //Disable Cache
AnnaBridge 153:b484a57bc302 798 __STATIC_INLINE void L2C_Disable(void)
AnnaBridge 153:b484a57bc302 799 {
AnnaBridge 153:b484a57bc302 800 L2C_310->CONTROL = 0x00;
AnnaBridge 153:b484a57bc302 801 L2C_Sync();
AnnaBridge 153:b484a57bc302 802 }
AnnaBridge 153:b484a57bc302 803
AnnaBridge 153:b484a57bc302 804 //Invalidate cache by physical address
AnnaBridge 153:b484a57bc302 805 __STATIC_INLINE void L2C_InvPa (void *pa)
AnnaBridge 153:b484a57bc302 806 {
AnnaBridge 153:b484a57bc302 807 L2C_310->INV_LINE_PA = (unsigned int)pa;
AnnaBridge 153:b484a57bc302 808 L2C_Sync();
AnnaBridge 153:b484a57bc302 809 }
AnnaBridge 153:b484a57bc302 810
AnnaBridge 153:b484a57bc302 811 //Clean cache by physical address
AnnaBridge 153:b484a57bc302 812 __STATIC_INLINE void L2C_CleanPa (void *pa)
AnnaBridge 153:b484a57bc302 813 {
AnnaBridge 153:b484a57bc302 814 L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
AnnaBridge 153:b484a57bc302 815 L2C_Sync();
AnnaBridge 153:b484a57bc302 816 }
AnnaBridge 153:b484a57bc302 817
AnnaBridge 153:b484a57bc302 818 //Clean and invalidate cache by physical address
AnnaBridge 153:b484a57bc302 819 __STATIC_INLINE void L2C_CleanInvPa (void *pa)
AnnaBridge 153:b484a57bc302 820 {
AnnaBridge 153:b484a57bc302 821 L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
AnnaBridge 153:b484a57bc302 822 L2C_Sync();
AnnaBridge 153:b484a57bc302 823 }
AnnaBridge 153:b484a57bc302 824 #endif
AnnaBridge 153:b484a57bc302 825
AnnaBridge 153:b484a57bc302 826 /* ########################## GIC functions ###################################### */
AnnaBridge 153:b484a57bc302 827 #if (__GIC_PRESENT == 1U)
AnnaBridge 153:b484a57bc302 828
AnnaBridge 153:b484a57bc302 829 __STATIC_INLINE void GIC_EnableDistributor(void)
AnnaBridge 153:b484a57bc302 830 {
AnnaBridge 153:b484a57bc302 831 GICDistributor->ICDDCR |= 1; //enable distributor
AnnaBridge 153:b484a57bc302 832 }
AnnaBridge 153:b484a57bc302 833
AnnaBridge 153:b484a57bc302 834 __STATIC_INLINE void GIC_DisableDistributor(void)
AnnaBridge 153:b484a57bc302 835 {
AnnaBridge 153:b484a57bc302 836 GICDistributor->ICDDCR &=~1; //disable distributor
AnnaBridge 153:b484a57bc302 837 }
AnnaBridge 153:b484a57bc302 838
AnnaBridge 153:b484a57bc302 839 __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
AnnaBridge 153:b484a57bc302 840 {
AnnaBridge 153:b484a57bc302 841 return (uint32_t)(GICDistributor->ICDICTR);
AnnaBridge 153:b484a57bc302 842 }
AnnaBridge 153:b484a57bc302 843
AnnaBridge 153:b484a57bc302 844 __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
AnnaBridge 153:b484a57bc302 845 {
AnnaBridge 153:b484a57bc302 846 return (uint32_t)(GICDistributor->ICDIIDR);
AnnaBridge 153:b484a57bc302 847 }
AnnaBridge 153:b484a57bc302 848
AnnaBridge 153:b484a57bc302 849 __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
AnnaBridge 153:b484a57bc302 850 {
AnnaBridge 153:b484a57bc302 851 char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
AnnaBridge 153:b484a57bc302 852 field += IRQn % 4;
AnnaBridge 153:b484a57bc302 853 *field = (char)cpu_target & 0xf;
AnnaBridge 153:b484a57bc302 854 }
AnnaBridge 153:b484a57bc302 855
AnnaBridge 153:b484a57bc302 856 __STATIC_INLINE void GIC_SetICDICFR (const uint32_t *ICDICFRn)
AnnaBridge 153:b484a57bc302 857 {
AnnaBridge 153:b484a57bc302 858 uint32_t i, num_irq;
AnnaBridge 153:b484a57bc302 859
AnnaBridge 153:b484a57bc302 860 //Get the maximum number of interrupts that the GIC supports
AnnaBridge 153:b484a57bc302 861 num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
AnnaBridge 153:b484a57bc302 862
AnnaBridge 153:b484a57bc302 863 for (i = 0; i < (num_irq/16); i++)
AnnaBridge 153:b484a57bc302 864 {
AnnaBridge 153:b484a57bc302 865 GICDistributor->ICDISPR[i] = *ICDICFRn++;
AnnaBridge 153:b484a57bc302 866 }
AnnaBridge 153:b484a57bc302 867 }
AnnaBridge 153:b484a57bc302 868
AnnaBridge 153:b484a57bc302 869 __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 870 {
AnnaBridge 153:b484a57bc302 871 char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
AnnaBridge 153:b484a57bc302 872 field += IRQn % 4;
AnnaBridge 153:b484a57bc302 873 return ((uint32_t)*field & 0xf);
AnnaBridge 153:b484a57bc302 874 }
AnnaBridge 153:b484a57bc302 875
AnnaBridge 153:b484a57bc302 876 __STATIC_INLINE void GIC_EnableInterface(void)
AnnaBridge 153:b484a57bc302 877 {
AnnaBridge 153:b484a57bc302 878 GICInterface->ICCICR |= 1; //enable interface
AnnaBridge 153:b484a57bc302 879 }
AnnaBridge 153:b484a57bc302 880
AnnaBridge 153:b484a57bc302 881 __STATIC_INLINE void GIC_DisableInterface(void)
AnnaBridge 153:b484a57bc302 882 {
AnnaBridge 153:b484a57bc302 883 GICInterface->ICCICR &=~1; //disable distributor
AnnaBridge 153:b484a57bc302 884 }
AnnaBridge 153:b484a57bc302 885
AnnaBridge 153:b484a57bc302 886 __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
AnnaBridge 153:b484a57bc302 887 {
AnnaBridge 153:b484a57bc302 888 return (IRQn_Type)(GICInterface->ICCIAR);
AnnaBridge 153:b484a57bc302 889 }
AnnaBridge 153:b484a57bc302 890
AnnaBridge 153:b484a57bc302 891 __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 892 {
AnnaBridge 153:b484a57bc302 893 GICInterface->ICCEOIR = IRQn;
AnnaBridge 153:b484a57bc302 894 }
AnnaBridge 153:b484a57bc302 895
AnnaBridge 153:b484a57bc302 896 __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 897 {
AnnaBridge 153:b484a57bc302 898 GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge 153:b484a57bc302 899 }
AnnaBridge 153:b484a57bc302 900
AnnaBridge 153:b484a57bc302 901 __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 902 {
AnnaBridge 153:b484a57bc302 903 GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge 153:b484a57bc302 904 }
AnnaBridge 153:b484a57bc302 905
AnnaBridge 153:b484a57bc302 906 __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 907 {
AnnaBridge 153:b484a57bc302 908 GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge 153:b484a57bc302 909 }
AnnaBridge 153:b484a57bc302 910
AnnaBridge 153:b484a57bc302 911 __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 912 {
AnnaBridge 153:b484a57bc302 913 GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge 153:b484a57bc302 914 }
AnnaBridge 153:b484a57bc302 915
AnnaBridge 153:b484a57bc302 916 __STATIC_INLINE void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
AnnaBridge 153:b484a57bc302 917 {
AnnaBridge 153:b484a57bc302 918 // Word-size read/writes must be used to access this register
AnnaBridge 153:b484a57bc302 919 volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]);
AnnaBridge 153:b484a57bc302 920 unsigned bit_shift = (IRQn % 16)<<1;
AnnaBridge 153:b484a57bc302 921 unsigned int save_word;
AnnaBridge 153:b484a57bc302 922
AnnaBridge 153:b484a57bc302 923 save_word = *field;
AnnaBridge 153:b484a57bc302 924 save_word &= (~(3 << bit_shift));
AnnaBridge 153:b484a57bc302 925
AnnaBridge 153:b484a57bc302 926 *field = (save_word | (((edge_level<<1) | model) << bit_shift));
AnnaBridge 153:b484a57bc302 927 }
AnnaBridge 153:b484a57bc302 928
AnnaBridge 153:b484a57bc302 929 __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 153:b484a57bc302 930 {
AnnaBridge 153:b484a57bc302 931 char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
AnnaBridge 153:b484a57bc302 932 field += IRQn % 4;
AnnaBridge 153:b484a57bc302 933 *field = (char)priority;
AnnaBridge 153:b484a57bc302 934 }
AnnaBridge 153:b484a57bc302 935
AnnaBridge 153:b484a57bc302 936 __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 937 {
AnnaBridge 153:b484a57bc302 938 char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
AnnaBridge 153:b484a57bc302 939 field += IRQn % 4;
AnnaBridge 153:b484a57bc302 940 return (uint32_t)*field;
AnnaBridge 153:b484a57bc302 941 }
AnnaBridge 153:b484a57bc302 942
AnnaBridge 153:b484a57bc302 943 __STATIC_INLINE void GIC_InterfacePriorityMask(uint32_t priority)
AnnaBridge 153:b484a57bc302 944 {
AnnaBridge 153:b484a57bc302 945 GICInterface->ICCPMR = priority & 0xff; //set priority mask
AnnaBridge 153:b484a57bc302 946 }
AnnaBridge 153:b484a57bc302 947
AnnaBridge 153:b484a57bc302 948 __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
AnnaBridge 153:b484a57bc302 949 {
AnnaBridge 153:b484a57bc302 950 GICInterface->ICCBPR = binary_point & 0x07; //set binary point
AnnaBridge 153:b484a57bc302 951 }
AnnaBridge 153:b484a57bc302 952
AnnaBridge 153:b484a57bc302 953 __STATIC_INLINE uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
AnnaBridge 153:b484a57bc302 954 {
AnnaBridge 153:b484a57bc302 955 return (uint32_t)GICInterface->ICCBPR;
AnnaBridge 153:b484a57bc302 956 }
AnnaBridge 153:b484a57bc302 957
AnnaBridge 153:b484a57bc302 958 __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
AnnaBridge 153:b484a57bc302 959 {
AnnaBridge 153:b484a57bc302 960 uint32_t pending, active;
AnnaBridge 153:b484a57bc302 961
AnnaBridge 153:b484a57bc302 962 active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
AnnaBridge 153:b484a57bc302 963 pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
AnnaBridge 153:b484a57bc302 964
AnnaBridge 153:b484a57bc302 965 return ((active<<1) | pending);
AnnaBridge 153:b484a57bc302 966 }
AnnaBridge 153:b484a57bc302 967
AnnaBridge 153:b484a57bc302 968 __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
AnnaBridge 153:b484a57bc302 969 {
AnnaBridge 153:b484a57bc302 970 GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
AnnaBridge 153:b484a57bc302 971 }
AnnaBridge 153:b484a57bc302 972
AnnaBridge 153:b484a57bc302 973 __STATIC_INLINE void GIC_DistInit(void)
AnnaBridge 153:b484a57bc302 974 {
AnnaBridge 153:b484a57bc302 975 IRQn_Type i;
AnnaBridge 153:b484a57bc302 976 uint32_t num_irq = 0;
AnnaBridge 153:b484a57bc302 977 uint32_t priority_field;
AnnaBridge 153:b484a57bc302 978
AnnaBridge 153:b484a57bc302 979 //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
AnnaBridge 153:b484a57bc302 980 //configuring all of the interrupts as Secure.
AnnaBridge 153:b484a57bc302 981
AnnaBridge 153:b484a57bc302 982 //Disable interrupt forwarding
AnnaBridge 153:b484a57bc302 983 GIC_DisableDistributor();
AnnaBridge 153:b484a57bc302 984 //Get the maximum number of interrupts that the GIC supports
AnnaBridge 153:b484a57bc302 985 num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
AnnaBridge 153:b484a57bc302 986
AnnaBridge 153:b484a57bc302 987 /* Priority level is implementation defined.
AnnaBridge 153:b484a57bc302 988 To determine the number of priority bits implemented write 0xFF to an ICDIPR
AnnaBridge 153:b484a57bc302 989 priority field and read back the value stored.*/
AnnaBridge 153:b484a57bc302 990 GIC_SetPriority((IRQn_Type)0, 0xff);
AnnaBridge 153:b484a57bc302 991 priority_field = GIC_GetPriority((IRQn_Type)0);
AnnaBridge 153:b484a57bc302 992
AnnaBridge 153:b484a57bc302 993 for (i = (IRQn_Type)32; i < num_irq; i++)
AnnaBridge 153:b484a57bc302 994 {
AnnaBridge 153:b484a57bc302 995 //Disable the SPI interrupt
AnnaBridge 153:b484a57bc302 996 GIC_DisableIRQ(i);
AnnaBridge 153:b484a57bc302 997 //Set level-sensitive and 1-N model
AnnaBridge 153:b484a57bc302 998 GIC_SetLevelModel(i, 0, 1);
AnnaBridge 153:b484a57bc302 999 //Set priority
AnnaBridge 153:b484a57bc302 1000 GIC_SetPriority(i, priority_field/2);
AnnaBridge 153:b484a57bc302 1001 //Set target list to CPU0
AnnaBridge 153:b484a57bc302 1002 GIC_SetTarget(i, 1);
AnnaBridge 153:b484a57bc302 1003 }
AnnaBridge 153:b484a57bc302 1004 //Enable distributor
AnnaBridge 153:b484a57bc302 1005 GIC_EnableDistributor();
AnnaBridge 153:b484a57bc302 1006 }
AnnaBridge 153:b484a57bc302 1007
AnnaBridge 153:b484a57bc302 1008 __STATIC_INLINE void GIC_CPUInterfaceInit(void)
AnnaBridge 153:b484a57bc302 1009 {
AnnaBridge 153:b484a57bc302 1010 IRQn_Type i;
AnnaBridge 153:b484a57bc302 1011 uint32_t priority_field;
AnnaBridge 153:b484a57bc302 1012
AnnaBridge 153:b484a57bc302 1013 //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
AnnaBridge 153:b484a57bc302 1014 //configuring all of the interrupts as Secure.
AnnaBridge 153:b484a57bc302 1015
AnnaBridge 153:b484a57bc302 1016 //Disable interrupt forwarding
AnnaBridge 153:b484a57bc302 1017 GIC_DisableInterface();
AnnaBridge 153:b484a57bc302 1018
AnnaBridge 153:b484a57bc302 1019 /* Priority level is implementation defined.
AnnaBridge 153:b484a57bc302 1020 To determine the number of priority bits implemented write 0xFF to an ICDIPR
AnnaBridge 153:b484a57bc302 1021 priority field and read back the value stored.*/
AnnaBridge 153:b484a57bc302 1022 GIC_SetPriority((IRQn_Type)0, 0xff);
AnnaBridge 153:b484a57bc302 1023 priority_field = GIC_GetPriority((IRQn_Type)0);
AnnaBridge 153:b484a57bc302 1024
AnnaBridge 153:b484a57bc302 1025 //SGI and PPI
AnnaBridge 153:b484a57bc302 1026 for (i = (IRQn_Type)0; i < 32; i++)
AnnaBridge 153:b484a57bc302 1027 {
AnnaBridge 153:b484a57bc302 1028 //Set level-sensitive and 1-N model for PPI
AnnaBridge 153:b484a57bc302 1029 if(i > 15)
AnnaBridge 153:b484a57bc302 1030 GIC_SetLevelModel(i, 0, 1);
AnnaBridge 153:b484a57bc302 1031 //Disable SGI and PPI interrupts
AnnaBridge 153:b484a57bc302 1032 GIC_DisableIRQ(i);
AnnaBridge 153:b484a57bc302 1033 //Set priority
AnnaBridge 153:b484a57bc302 1034 GIC_SetPriority(i, priority_field/2);
AnnaBridge 153:b484a57bc302 1035 }
AnnaBridge 153:b484a57bc302 1036 //Enable interface
AnnaBridge 153:b484a57bc302 1037 GIC_EnableInterface();
AnnaBridge 153:b484a57bc302 1038 //Set binary point to 0
AnnaBridge 153:b484a57bc302 1039 GIC_SetBinaryPoint(0);
AnnaBridge 153:b484a57bc302 1040 //Set priority mask
AnnaBridge 153:b484a57bc302 1041 GIC_InterfacePriorityMask(0xff);
AnnaBridge 153:b484a57bc302 1042 }
AnnaBridge 153:b484a57bc302 1043
AnnaBridge 153:b484a57bc302 1044 __STATIC_INLINE void GIC_Enable(void)
AnnaBridge 153:b484a57bc302 1045 {
AnnaBridge 153:b484a57bc302 1046 GIC_DistInit();
AnnaBridge 153:b484a57bc302 1047 GIC_CPUInterfaceInit(); //per CPU
AnnaBridge 153:b484a57bc302 1048 }
AnnaBridge 153:b484a57bc302 1049 #endif
AnnaBridge 153:b484a57bc302 1050
AnnaBridge 153:b484a57bc302 1051 /* ########################## Generic Timer functions ############################ */
AnnaBridge 153:b484a57bc302 1052 #if (__TIM_PRESENT == 1U)
AnnaBridge 153:b484a57bc302 1053
AnnaBridge 153:b484a57bc302 1054 /* PL1 Physical Timer */
AnnaBridge 153:b484a57bc302 1055 #if (__CORTEX_A == 7U)
AnnaBridge 153:b484a57bc302 1056 __STATIC_INLINE void PL1_SetLoadValue(uint32_t value) {
AnnaBridge 153:b484a57bc302 1057 __set_CNTP_TVAL(value);
AnnaBridge 153:b484a57bc302 1058 __ISB();
AnnaBridge 153:b484a57bc302 1059 }
AnnaBridge 153:b484a57bc302 1060
AnnaBridge 153:b484a57bc302 1061 __STATIC_INLINE uint32_t PL1_GetCurrentValue() {
AnnaBridge 153:b484a57bc302 1062 return(__get_CNTP_TVAL());
AnnaBridge 153:b484a57bc302 1063 }
AnnaBridge 153:b484a57bc302 1064
AnnaBridge 153:b484a57bc302 1065 __STATIC_INLINE void PL1_SetControl(uint32_t value) {
AnnaBridge 153:b484a57bc302 1066 __set_CNTP_CTL(value);
AnnaBridge 153:b484a57bc302 1067 __ISB();
AnnaBridge 153:b484a57bc302 1068 }
AnnaBridge 153:b484a57bc302 1069
AnnaBridge 153:b484a57bc302 1070 /* Private Timer */
AnnaBridge 153:b484a57bc302 1071 #elif ((__CORTEX_A == 5U)||(__CORTEX_A == 9U))
AnnaBridge 153:b484a57bc302 1072 __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
AnnaBridge 153:b484a57bc302 1073 PTIM->LOAD = value;
AnnaBridge 153:b484a57bc302 1074 }
AnnaBridge 153:b484a57bc302 1075
AnnaBridge 153:b484a57bc302 1076 __STATIC_INLINE uint32_t PTIM_GetLoadValue() {
AnnaBridge 153:b484a57bc302 1077 return(PTIM->LOAD);
AnnaBridge 153:b484a57bc302 1078 }
AnnaBridge 153:b484a57bc302 1079
AnnaBridge 153:b484a57bc302 1080 __STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
AnnaBridge 153:b484a57bc302 1081 return(PTIM->COUNTER);
AnnaBridge 153:b484a57bc302 1082 }
AnnaBridge 153:b484a57bc302 1083
AnnaBridge 153:b484a57bc302 1084 __STATIC_INLINE void PTIM_SetControl(uint32_t value) {
AnnaBridge 153:b484a57bc302 1085 PTIM->CONTROL = value;
AnnaBridge 153:b484a57bc302 1086 }
AnnaBridge 153:b484a57bc302 1087
AnnaBridge 153:b484a57bc302 1088 __STATIC_INLINE uint32_t PTIM_GetControl(void) {
AnnaBridge 153:b484a57bc302 1089 return(PTIM->CONTROL);
AnnaBridge 153:b484a57bc302 1090 }
AnnaBridge 153:b484a57bc302 1091
AnnaBridge 153:b484a57bc302 1092 __STATIC_INLINE void PTIM_ClearEventFlag(void) {
AnnaBridge 153:b484a57bc302 1093 PTIM->ISR = 1;
AnnaBridge 153:b484a57bc302 1094 }
AnnaBridge 153:b484a57bc302 1095 #endif
AnnaBridge 153:b484a57bc302 1096 #endif
AnnaBridge 153:b484a57bc302 1097
AnnaBridge 153:b484a57bc302 1098 /* ########################## MMU functions ###################################### */
AnnaBridge 153:b484a57bc302 1099
AnnaBridge 153:b484a57bc302 1100 #define SECTION_DESCRIPTOR (0x2)
AnnaBridge 153:b484a57bc302 1101 #define SECTION_MASK (0xFFFFFFFC)
AnnaBridge 153:b484a57bc302 1102
AnnaBridge 153:b484a57bc302 1103 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 153:b484a57bc302 1104 #define SECTION_B_SHIFT (2)
AnnaBridge 153:b484a57bc302 1105 #define SECTION_C_SHIFT (3)
AnnaBridge 153:b484a57bc302 1106 #define SECTION_TEX0_SHIFT (12)
AnnaBridge 153:b484a57bc302 1107 #define SECTION_TEX1_SHIFT (13)
AnnaBridge 153:b484a57bc302 1108 #define SECTION_TEX2_SHIFT (14)
AnnaBridge 153:b484a57bc302 1109
AnnaBridge 153:b484a57bc302 1110 #define SECTION_XN_MASK (0xFFFFFFEF)
AnnaBridge 153:b484a57bc302 1111 #define SECTION_XN_SHIFT (4)
AnnaBridge 153:b484a57bc302 1112
AnnaBridge 153:b484a57bc302 1113 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge 153:b484a57bc302 1114 #define SECTION_DOMAIN_SHIFT (5)
AnnaBridge 153:b484a57bc302 1115
AnnaBridge 153:b484a57bc302 1116 #define SECTION_P_MASK (0xFFFFFDFF)
AnnaBridge 153:b484a57bc302 1117 #define SECTION_P_SHIFT (9)
AnnaBridge 153:b484a57bc302 1118
AnnaBridge 153:b484a57bc302 1119 #define SECTION_AP_MASK (0xFFFF73FF)
AnnaBridge 153:b484a57bc302 1120 #define SECTION_AP_SHIFT (10)
AnnaBridge 153:b484a57bc302 1121 #define SECTION_AP2_SHIFT (15)
AnnaBridge 153:b484a57bc302 1122
AnnaBridge 153:b484a57bc302 1123 #define SECTION_S_MASK (0xFFFEFFFF)
AnnaBridge 153:b484a57bc302 1124 #define SECTION_S_SHIFT (16)
AnnaBridge 153:b484a57bc302 1125
AnnaBridge 153:b484a57bc302 1126 #define SECTION_NG_MASK (0xFFFDFFFF)
AnnaBridge 153:b484a57bc302 1127 #define SECTION_NG_SHIFT (17)
AnnaBridge 153:b484a57bc302 1128
AnnaBridge 153:b484a57bc302 1129 #define SECTION_NS_MASK (0xFFF7FFFF)
AnnaBridge 153:b484a57bc302 1130 #define SECTION_NS_SHIFT (19)
AnnaBridge 153:b484a57bc302 1131
AnnaBridge 153:b484a57bc302 1132 #define PAGE_L1_DESCRIPTOR (0x1)
AnnaBridge 153:b484a57bc302 1133 #define PAGE_L1_MASK (0xFFFFFFFC)
AnnaBridge 153:b484a57bc302 1134
AnnaBridge 153:b484a57bc302 1135 #define PAGE_L2_4K_DESC (0x2)
AnnaBridge 153:b484a57bc302 1136 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
AnnaBridge 153:b484a57bc302 1137
AnnaBridge 153:b484a57bc302 1138 #define PAGE_L2_64K_DESC (0x1)
AnnaBridge 153:b484a57bc302 1139 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
AnnaBridge 153:b484a57bc302 1140
AnnaBridge 153:b484a57bc302 1141 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
AnnaBridge 153:b484a57bc302 1142 #define PAGE_4K_B_SHIFT (2)
AnnaBridge 153:b484a57bc302 1143 #define PAGE_4K_C_SHIFT (3)
AnnaBridge 153:b484a57bc302 1144 #define PAGE_4K_TEX0_SHIFT (6)
AnnaBridge 153:b484a57bc302 1145 #define PAGE_4K_TEX1_SHIFT (7)
AnnaBridge 153:b484a57bc302 1146 #define PAGE_4K_TEX2_SHIFT (8)
AnnaBridge 153:b484a57bc302 1147
AnnaBridge 153:b484a57bc302 1148 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 153:b484a57bc302 1149 #define PAGE_64K_B_SHIFT (2)
AnnaBridge 153:b484a57bc302 1150 #define PAGE_64K_C_SHIFT (3)
AnnaBridge 153:b484a57bc302 1151 #define PAGE_64K_TEX0_SHIFT (12)
AnnaBridge 153:b484a57bc302 1152 #define PAGE_64K_TEX1_SHIFT (13)
AnnaBridge 153:b484a57bc302 1153 #define PAGE_64K_TEX2_SHIFT (14)
AnnaBridge 153:b484a57bc302 1154
AnnaBridge 153:b484a57bc302 1155 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 153:b484a57bc302 1156 #define PAGE_B_SHIFT (2)
AnnaBridge 153:b484a57bc302 1157 #define PAGE_C_SHIFT (3)
AnnaBridge 153:b484a57bc302 1158 #define PAGE_TEX_SHIFT (12)
AnnaBridge 153:b484a57bc302 1159
AnnaBridge 153:b484a57bc302 1160 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
AnnaBridge 153:b484a57bc302 1161 #define PAGE_XN_4K_SHIFT (0)
AnnaBridge 153:b484a57bc302 1162 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
AnnaBridge 153:b484a57bc302 1163 #define PAGE_XN_64K_SHIFT (15)
AnnaBridge 153:b484a57bc302 1164
AnnaBridge 153:b484a57bc302 1165 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge 153:b484a57bc302 1166 #define PAGE_DOMAIN_SHIFT (5)
AnnaBridge 153:b484a57bc302 1167
AnnaBridge 153:b484a57bc302 1168 #define PAGE_P_MASK (0xFFFFFDFF)
AnnaBridge 153:b484a57bc302 1169 #define PAGE_P_SHIFT (9)
AnnaBridge 153:b484a57bc302 1170
AnnaBridge 153:b484a57bc302 1171 #define PAGE_AP_MASK (0xFFFFFDCF)
AnnaBridge 153:b484a57bc302 1172 #define PAGE_AP_SHIFT (4)
AnnaBridge 153:b484a57bc302 1173 #define PAGE_AP2_SHIFT (9)
AnnaBridge 153:b484a57bc302 1174
AnnaBridge 153:b484a57bc302 1175 #define PAGE_S_MASK (0xFFFFFBFF)
AnnaBridge 153:b484a57bc302 1176 #define PAGE_S_SHIFT (10)
AnnaBridge 153:b484a57bc302 1177
AnnaBridge 153:b484a57bc302 1178 #define PAGE_NG_MASK (0xFFFFF7FF)
AnnaBridge 153:b484a57bc302 1179 #define PAGE_NG_SHIFT (11)
AnnaBridge 153:b484a57bc302 1180
AnnaBridge 153:b484a57bc302 1181 #define PAGE_NS_MASK (0xFFFFFFF7)
AnnaBridge 153:b484a57bc302 1182 #define PAGE_NS_SHIFT (3)
AnnaBridge 153:b484a57bc302 1183
AnnaBridge 153:b484a57bc302 1184 #define OFFSET_1M (0x00100000)
AnnaBridge 153:b484a57bc302 1185 #define OFFSET_64K (0x00010000)
AnnaBridge 153:b484a57bc302 1186 #define OFFSET_4K (0x00001000)
AnnaBridge 153:b484a57bc302 1187
AnnaBridge 153:b484a57bc302 1188 #define DESCRIPTOR_FAULT (0x00000000)
AnnaBridge 153:b484a57bc302 1189
AnnaBridge 153:b484a57bc302 1190 /* Attributes enumerations */
AnnaBridge 153:b484a57bc302 1191
AnnaBridge 153:b484a57bc302 1192 /* Region size attributes */
AnnaBridge 153:b484a57bc302 1193 typedef enum
AnnaBridge 153:b484a57bc302 1194 {
AnnaBridge 153:b484a57bc302 1195 SECTION,
AnnaBridge 153:b484a57bc302 1196 PAGE_4k,
AnnaBridge 153:b484a57bc302 1197 PAGE_64k,
AnnaBridge 153:b484a57bc302 1198 } mmu_region_size_Type;
AnnaBridge 153:b484a57bc302 1199
AnnaBridge 153:b484a57bc302 1200 /* Region type attributes */
AnnaBridge 153:b484a57bc302 1201 typedef enum
AnnaBridge 153:b484a57bc302 1202 {
AnnaBridge 153:b484a57bc302 1203 NORMAL,
AnnaBridge 153:b484a57bc302 1204 DEVICE,
AnnaBridge 153:b484a57bc302 1205 SHARED_DEVICE,
AnnaBridge 153:b484a57bc302 1206 NON_SHARED_DEVICE,
AnnaBridge 153:b484a57bc302 1207 STRONGLY_ORDERED
AnnaBridge 153:b484a57bc302 1208 } mmu_memory_Type;
AnnaBridge 153:b484a57bc302 1209
AnnaBridge 153:b484a57bc302 1210 /* Region cacheability attributes */
AnnaBridge 153:b484a57bc302 1211 typedef enum
AnnaBridge 153:b484a57bc302 1212 {
AnnaBridge 153:b484a57bc302 1213 NON_CACHEABLE,
AnnaBridge 153:b484a57bc302 1214 WB_WA,
AnnaBridge 153:b484a57bc302 1215 WT,
AnnaBridge 153:b484a57bc302 1216 WB_NO_WA,
AnnaBridge 153:b484a57bc302 1217 } mmu_cacheability_Type;
AnnaBridge 153:b484a57bc302 1218
AnnaBridge 153:b484a57bc302 1219 /* Region parity check attributes */
AnnaBridge 153:b484a57bc302 1220 typedef enum
AnnaBridge 153:b484a57bc302 1221 {
AnnaBridge 153:b484a57bc302 1222 ECC_DISABLED,
AnnaBridge 153:b484a57bc302 1223 ECC_ENABLED,
AnnaBridge 153:b484a57bc302 1224 } mmu_ecc_check_Type;
AnnaBridge 153:b484a57bc302 1225
AnnaBridge 153:b484a57bc302 1226 /* Region execution attributes */
AnnaBridge 153:b484a57bc302 1227 typedef enum
AnnaBridge 153:b484a57bc302 1228 {
AnnaBridge 153:b484a57bc302 1229 EXECUTE,
AnnaBridge 153:b484a57bc302 1230 NON_EXECUTE,
AnnaBridge 153:b484a57bc302 1231 } mmu_execute_Type;
AnnaBridge 153:b484a57bc302 1232
AnnaBridge 153:b484a57bc302 1233 /* Region global attributes */
AnnaBridge 153:b484a57bc302 1234 typedef enum
AnnaBridge 153:b484a57bc302 1235 {
AnnaBridge 153:b484a57bc302 1236 GLOBAL,
AnnaBridge 153:b484a57bc302 1237 NON_GLOBAL,
AnnaBridge 153:b484a57bc302 1238 } mmu_global_Type;
AnnaBridge 153:b484a57bc302 1239
AnnaBridge 153:b484a57bc302 1240 /* Region shareability attributes */
AnnaBridge 153:b484a57bc302 1241 typedef enum
AnnaBridge 153:b484a57bc302 1242 {
AnnaBridge 153:b484a57bc302 1243 NON_SHARED,
AnnaBridge 153:b484a57bc302 1244 SHARED,
AnnaBridge 153:b484a57bc302 1245 } mmu_shared_Type;
AnnaBridge 153:b484a57bc302 1246
AnnaBridge 153:b484a57bc302 1247 /* Region security attributes */
AnnaBridge 153:b484a57bc302 1248 typedef enum
AnnaBridge 153:b484a57bc302 1249 {
AnnaBridge 153:b484a57bc302 1250 SECURE,
AnnaBridge 153:b484a57bc302 1251 NON_SECURE,
AnnaBridge 153:b484a57bc302 1252 } mmu_secure_Type;
AnnaBridge 153:b484a57bc302 1253
AnnaBridge 153:b484a57bc302 1254 /* Region access attributes */
AnnaBridge 153:b484a57bc302 1255 typedef enum
AnnaBridge 153:b484a57bc302 1256 {
AnnaBridge 153:b484a57bc302 1257 NO_ACCESS,
AnnaBridge 153:b484a57bc302 1258 RW,
AnnaBridge 153:b484a57bc302 1259 READ,
AnnaBridge 153:b484a57bc302 1260 } mmu_access_Type;
AnnaBridge 153:b484a57bc302 1261
AnnaBridge 153:b484a57bc302 1262 /* Memory Region definition */
AnnaBridge 153:b484a57bc302 1263 typedef struct RegionStruct {
AnnaBridge 153:b484a57bc302 1264 mmu_region_size_Type rg_t;
AnnaBridge 153:b484a57bc302 1265 mmu_memory_Type mem_t;
AnnaBridge 153:b484a57bc302 1266 uint8_t domain;
AnnaBridge 153:b484a57bc302 1267 mmu_cacheability_Type inner_norm_t;
AnnaBridge 153:b484a57bc302 1268 mmu_cacheability_Type outer_norm_t;
AnnaBridge 153:b484a57bc302 1269 mmu_ecc_check_Type e_t;
AnnaBridge 153:b484a57bc302 1270 mmu_execute_Type xn_t;
AnnaBridge 153:b484a57bc302 1271 mmu_global_Type g_t;
AnnaBridge 153:b484a57bc302 1272 mmu_secure_Type sec_t;
AnnaBridge 153:b484a57bc302 1273 mmu_access_Type priv_t;
AnnaBridge 153:b484a57bc302 1274 mmu_access_Type user_t;
AnnaBridge 153:b484a57bc302 1275 mmu_shared_Type sh_t;
AnnaBridge 153:b484a57bc302 1276
AnnaBridge 153:b484a57bc302 1277 } mmu_region_attributes_Type;
AnnaBridge 153:b484a57bc302 1278
AnnaBridge 153:b484a57bc302 1279 //Following macros define the descriptors and attributes
AnnaBridge 153:b484a57bc302 1280 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
AnnaBridge 153:b484a57bc302 1281 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 153:b484a57bc302 1282 region.domain = 0x0; \
AnnaBridge 153:b484a57bc302 1283 region.e_t = ECC_DISABLED; \
AnnaBridge 153:b484a57bc302 1284 region.g_t = GLOBAL; \
AnnaBridge 153:b484a57bc302 1285 region.inner_norm_t = WB_WA; \
AnnaBridge 153:b484a57bc302 1286 region.outer_norm_t = WB_WA; \
AnnaBridge 153:b484a57bc302 1287 region.mem_t = NORMAL; \
AnnaBridge 153:b484a57bc302 1288 region.sec_t = SECURE; \
AnnaBridge 153:b484a57bc302 1289 region.xn_t = EXECUTE; \
AnnaBridge 153:b484a57bc302 1290 region.priv_t = RW; \
AnnaBridge 153:b484a57bc302 1291 region.user_t = RW; \
AnnaBridge 153:b484a57bc302 1292 region.sh_t = NON_SHARED; \
AnnaBridge 153:b484a57bc302 1293 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 153:b484a57bc302 1294
AnnaBridge 153:b484a57bc302 1295 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
AnnaBridge 153:b484a57bc302 1296 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 153:b484a57bc302 1297 region.domain = 0x0; \
AnnaBridge 153:b484a57bc302 1298 region.e_t = ECC_DISABLED; \
AnnaBridge 153:b484a57bc302 1299 region.g_t = GLOBAL; \
AnnaBridge 153:b484a57bc302 1300 region.inner_norm_t = WB_WA; \
AnnaBridge 153:b484a57bc302 1301 region.outer_norm_t = WB_WA; \
AnnaBridge 153:b484a57bc302 1302 region.mem_t = NORMAL; \
AnnaBridge 153:b484a57bc302 1303 region.sec_t = SECURE; \
AnnaBridge 153:b484a57bc302 1304 region.xn_t = EXECUTE; \
AnnaBridge 153:b484a57bc302 1305 region.priv_t = READ; \
AnnaBridge 153:b484a57bc302 1306 region.user_t = READ; \
AnnaBridge 153:b484a57bc302 1307 region.sh_t = NON_SHARED; \
AnnaBridge 153:b484a57bc302 1308 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 153:b484a57bc302 1309
AnnaBridge 153:b484a57bc302 1310 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
AnnaBridge 153:b484a57bc302 1311 #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 153:b484a57bc302 1312 region.domain = 0x0; \
AnnaBridge 153:b484a57bc302 1313 region.e_t = ECC_DISABLED; \
AnnaBridge 153:b484a57bc302 1314 region.g_t = GLOBAL; \
AnnaBridge 153:b484a57bc302 1315 region.inner_norm_t = WB_WA; \
AnnaBridge 153:b484a57bc302 1316 region.outer_norm_t = WB_WA; \
AnnaBridge 153:b484a57bc302 1317 region.mem_t = NORMAL; \
AnnaBridge 153:b484a57bc302 1318 region.sec_t = SECURE; \
AnnaBridge 153:b484a57bc302 1319 region.xn_t = NON_EXECUTE; \
AnnaBridge 153:b484a57bc302 1320 region.priv_t = READ; \
AnnaBridge 153:b484a57bc302 1321 region.user_t = READ; \
AnnaBridge 153:b484a57bc302 1322 region.sh_t = NON_SHARED; \
AnnaBridge 153:b484a57bc302 1323 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 153:b484a57bc302 1324
AnnaBridge 153:b484a57bc302 1325 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
AnnaBridge 153:b484a57bc302 1326 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 153:b484a57bc302 1327 region.domain = 0x0; \
AnnaBridge 153:b484a57bc302 1328 region.e_t = ECC_DISABLED; \
AnnaBridge 153:b484a57bc302 1329 region.g_t = GLOBAL; \
AnnaBridge 153:b484a57bc302 1330 region.inner_norm_t = WB_WA; \
AnnaBridge 153:b484a57bc302 1331 region.outer_norm_t = WB_WA; \
AnnaBridge 153:b484a57bc302 1332 region.mem_t = NORMAL; \
AnnaBridge 153:b484a57bc302 1333 region.sec_t = SECURE; \
AnnaBridge 153:b484a57bc302 1334 region.xn_t = NON_EXECUTE; \
AnnaBridge 153:b484a57bc302 1335 region.priv_t = RW; \
AnnaBridge 153:b484a57bc302 1336 region.user_t = RW; \
AnnaBridge 153:b484a57bc302 1337 region.sh_t = NON_SHARED; \
AnnaBridge 153:b484a57bc302 1338 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 153:b484a57bc302 1339 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
AnnaBridge 153:b484a57bc302 1340 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 153:b484a57bc302 1341 region.domain = 0x0; \
AnnaBridge 153:b484a57bc302 1342 region.e_t = ECC_DISABLED; \
AnnaBridge 153:b484a57bc302 1343 region.g_t = GLOBAL; \
AnnaBridge 153:b484a57bc302 1344 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 153:b484a57bc302 1345 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 153:b484a57bc302 1346 region.mem_t = STRONGLY_ORDERED; \
AnnaBridge 153:b484a57bc302 1347 region.sec_t = SECURE; \
AnnaBridge 153:b484a57bc302 1348 region.xn_t = NON_EXECUTE; \
AnnaBridge 153:b484a57bc302 1349 region.priv_t = RW; \
AnnaBridge 153:b484a57bc302 1350 region.user_t = RW; \
AnnaBridge 153:b484a57bc302 1351 region.sh_t = NON_SHARED; \
AnnaBridge 153:b484a57bc302 1352 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 153:b484a57bc302 1353
AnnaBridge 153:b484a57bc302 1354 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
AnnaBridge 153:b484a57bc302 1355 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 153:b484a57bc302 1356 region.domain = 0x0; \
AnnaBridge 153:b484a57bc302 1357 region.e_t = ECC_DISABLED; \
AnnaBridge 153:b484a57bc302 1358 region.g_t = GLOBAL; \
AnnaBridge 153:b484a57bc302 1359 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 153:b484a57bc302 1360 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 153:b484a57bc302 1361 region.mem_t = STRONGLY_ORDERED; \
AnnaBridge 153:b484a57bc302 1362 region.sec_t = SECURE; \
AnnaBridge 153:b484a57bc302 1363 region.xn_t = NON_EXECUTE; \
AnnaBridge 153:b484a57bc302 1364 region.priv_t = READ; \
AnnaBridge 153:b484a57bc302 1365 region.user_t = READ; \
AnnaBridge 153:b484a57bc302 1366 region.sh_t = NON_SHARED; \
AnnaBridge 153:b484a57bc302 1367 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 153:b484a57bc302 1368
AnnaBridge 153:b484a57bc302 1369 //Sect_Device_RW. Sect_Device_RO, but writeable
AnnaBridge 153:b484a57bc302 1370 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 153:b484a57bc302 1371 region.domain = 0x0; \
AnnaBridge 153:b484a57bc302 1372 region.e_t = ECC_DISABLED; \
AnnaBridge 153:b484a57bc302 1373 region.g_t = GLOBAL; \
AnnaBridge 153:b484a57bc302 1374 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 153:b484a57bc302 1375 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 153:b484a57bc302 1376 region.mem_t = STRONGLY_ORDERED; \
AnnaBridge 153:b484a57bc302 1377 region.sec_t = SECURE; \
AnnaBridge 153:b484a57bc302 1378 region.xn_t = NON_EXECUTE; \
AnnaBridge 153:b484a57bc302 1379 region.priv_t = RW; \
AnnaBridge 153:b484a57bc302 1380 region.user_t = RW; \
AnnaBridge 153:b484a57bc302 1381 region.sh_t = NON_SHARED; \
AnnaBridge 153:b484a57bc302 1382 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 153:b484a57bc302 1383 //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
AnnaBridge 153:b484a57bc302 1384 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
AnnaBridge 153:b484a57bc302 1385 region.domain = 0x0; \
AnnaBridge 153:b484a57bc302 1386 region.e_t = ECC_DISABLED; \
AnnaBridge 153:b484a57bc302 1387 region.g_t = GLOBAL; \
AnnaBridge 153:b484a57bc302 1388 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 153:b484a57bc302 1389 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 153:b484a57bc302 1390 region.mem_t = SHARED_DEVICE; \
AnnaBridge 153:b484a57bc302 1391 region.sec_t = SECURE; \
AnnaBridge 153:b484a57bc302 1392 region.xn_t = NON_EXECUTE; \
AnnaBridge 153:b484a57bc302 1393 region.priv_t = RW; \
AnnaBridge 153:b484a57bc302 1394 region.user_t = RW; \
AnnaBridge 153:b484a57bc302 1395 region.sh_t = NON_SHARED; \
AnnaBridge 153:b484a57bc302 1396 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
AnnaBridge 153:b484a57bc302 1397
AnnaBridge 153:b484a57bc302 1398 //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
AnnaBridge 153:b484a57bc302 1399 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
AnnaBridge 153:b484a57bc302 1400 region.domain = 0x0; \
AnnaBridge 153:b484a57bc302 1401 region.e_t = ECC_DISABLED; \
AnnaBridge 153:b484a57bc302 1402 region.g_t = GLOBAL; \
AnnaBridge 153:b484a57bc302 1403 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 153:b484a57bc302 1404 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 153:b484a57bc302 1405 region.mem_t = SHARED_DEVICE; \
AnnaBridge 153:b484a57bc302 1406 region.sec_t = SECURE; \
AnnaBridge 153:b484a57bc302 1407 region.xn_t = NON_EXECUTE; \
AnnaBridge 153:b484a57bc302 1408 region.priv_t = RW; \
AnnaBridge 153:b484a57bc302 1409 region.user_t = RW; \
AnnaBridge 153:b484a57bc302 1410 region.sh_t = NON_SHARED; \
AnnaBridge 153:b484a57bc302 1411 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
AnnaBridge 153:b484a57bc302 1412
AnnaBridge 153:b484a57bc302 1413 /** \brief Set section execution-never attribute
AnnaBridge 153:b484a57bc302 1414
AnnaBridge 153:b484a57bc302 1415 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 153:b484a57bc302 1416 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge 153:b484a57bc302 1417
AnnaBridge 153:b484a57bc302 1418 \return 0
AnnaBridge 153:b484a57bc302 1419 */
AnnaBridge 153:b484a57bc302 1420 __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
AnnaBridge 153:b484a57bc302 1421 {
AnnaBridge 153:b484a57bc302 1422 *descriptor_l1 &= SECTION_XN_MASK;
AnnaBridge 153:b484a57bc302 1423 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
AnnaBridge 153:b484a57bc302 1424 return 0;
AnnaBridge 153:b484a57bc302 1425 }
AnnaBridge 153:b484a57bc302 1426
AnnaBridge 153:b484a57bc302 1427 /** \brief Set section domain
AnnaBridge 153:b484a57bc302 1428
AnnaBridge 153:b484a57bc302 1429 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 153:b484a57bc302 1430 \param [in] domain Section domain
AnnaBridge 153:b484a57bc302 1431
AnnaBridge 153:b484a57bc302 1432 \return 0
AnnaBridge 153:b484a57bc302 1433 */
AnnaBridge 153:b484a57bc302 1434 __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge 153:b484a57bc302 1435 {
AnnaBridge 153:b484a57bc302 1436 *descriptor_l1 &= SECTION_DOMAIN_MASK;
AnnaBridge 153:b484a57bc302 1437 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
AnnaBridge 153:b484a57bc302 1438 return 0;
AnnaBridge 153:b484a57bc302 1439 }
AnnaBridge 153:b484a57bc302 1440
AnnaBridge 153:b484a57bc302 1441 /** \brief Set section parity check
AnnaBridge 153:b484a57bc302 1442
AnnaBridge 153:b484a57bc302 1443 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 153:b484a57bc302 1444 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge 153:b484a57bc302 1445
AnnaBridge 153:b484a57bc302 1446 \return 0
AnnaBridge 153:b484a57bc302 1447 */
AnnaBridge 153:b484a57bc302 1448 __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge 153:b484a57bc302 1449 {
AnnaBridge 153:b484a57bc302 1450 *descriptor_l1 &= SECTION_P_MASK;
AnnaBridge 153:b484a57bc302 1451 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge 153:b484a57bc302 1452 return 0;
AnnaBridge 153:b484a57bc302 1453 }
AnnaBridge 153:b484a57bc302 1454
AnnaBridge 153:b484a57bc302 1455 /** \brief Set section access privileges
AnnaBridge 153:b484a57bc302 1456
AnnaBridge 153:b484a57bc302 1457 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 153:b484a57bc302 1458 \param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge 153:b484a57bc302 1459 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge 153:b484a57bc302 1460 \param [in] afe Access flag enable
AnnaBridge 153:b484a57bc302 1461
AnnaBridge 153:b484a57bc302 1462 \return 0
AnnaBridge 153:b484a57bc302 1463 */
AnnaBridge 153:b484a57bc302 1464 __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge 153:b484a57bc302 1465 {
AnnaBridge 153:b484a57bc302 1466 uint32_t ap = 0;
AnnaBridge 153:b484a57bc302 1467
AnnaBridge 153:b484a57bc302 1468 if (afe == 0) { //full access
AnnaBridge 153:b484a57bc302 1469 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge 153:b484a57bc302 1470 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 153:b484a57bc302 1471 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge 153:b484a57bc302 1472 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 153:b484a57bc302 1473 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 153:b484a57bc302 1474 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 153:b484a57bc302 1475 }
AnnaBridge 153:b484a57bc302 1476
AnnaBridge 153:b484a57bc302 1477 else { //Simplified access
AnnaBridge 153:b484a57bc302 1478 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 153:b484a57bc302 1479 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 153:b484a57bc302 1480 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 153:b484a57bc302 1481 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 153:b484a57bc302 1482 }
AnnaBridge 153:b484a57bc302 1483
AnnaBridge 153:b484a57bc302 1484 *descriptor_l1 &= SECTION_AP_MASK;
AnnaBridge 153:b484a57bc302 1485 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
AnnaBridge 153:b484a57bc302 1486 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
AnnaBridge 153:b484a57bc302 1487
AnnaBridge 153:b484a57bc302 1488 return 0;
AnnaBridge 153:b484a57bc302 1489 }
AnnaBridge 153:b484a57bc302 1490
AnnaBridge 153:b484a57bc302 1491 /** \brief Set section shareability
AnnaBridge 153:b484a57bc302 1492
AnnaBridge 153:b484a57bc302 1493 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 153:b484a57bc302 1494 \param [in] s_bit Section shareability: NON_SHARED, SHARED
AnnaBridge 153:b484a57bc302 1495
AnnaBridge 153:b484a57bc302 1496 \return 0
AnnaBridge 153:b484a57bc302 1497 */
AnnaBridge 153:b484a57bc302 1498 __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
AnnaBridge 153:b484a57bc302 1499 {
AnnaBridge 153:b484a57bc302 1500 *descriptor_l1 &= SECTION_S_MASK;
AnnaBridge 153:b484a57bc302 1501 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
AnnaBridge 153:b484a57bc302 1502 return 0;
AnnaBridge 153:b484a57bc302 1503 }
AnnaBridge 153:b484a57bc302 1504
AnnaBridge 153:b484a57bc302 1505 /** \brief Set section Global attribute
AnnaBridge 153:b484a57bc302 1506
AnnaBridge 153:b484a57bc302 1507 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 153:b484a57bc302 1508 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
AnnaBridge 153:b484a57bc302 1509
AnnaBridge 153:b484a57bc302 1510 \return 0
AnnaBridge 153:b484a57bc302 1511 */
AnnaBridge 153:b484a57bc302 1512 __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
AnnaBridge 153:b484a57bc302 1513 {
AnnaBridge 153:b484a57bc302 1514 *descriptor_l1 &= SECTION_NG_MASK;
AnnaBridge 153:b484a57bc302 1515 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
AnnaBridge 153:b484a57bc302 1516 return 0;
AnnaBridge 153:b484a57bc302 1517 }
AnnaBridge 153:b484a57bc302 1518
AnnaBridge 153:b484a57bc302 1519 /** \brief Set section Security attribute
AnnaBridge 153:b484a57bc302 1520
AnnaBridge 153:b484a57bc302 1521 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 153:b484a57bc302 1522 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
AnnaBridge 153:b484a57bc302 1523
AnnaBridge 153:b484a57bc302 1524 \return 0
AnnaBridge 153:b484a57bc302 1525 */
AnnaBridge 153:b484a57bc302 1526 __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge 153:b484a57bc302 1527 {
AnnaBridge 153:b484a57bc302 1528 *descriptor_l1 &= SECTION_NS_MASK;
AnnaBridge 153:b484a57bc302 1529 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
AnnaBridge 153:b484a57bc302 1530 return 0;
AnnaBridge 153:b484a57bc302 1531 }
AnnaBridge 153:b484a57bc302 1532
AnnaBridge 153:b484a57bc302 1533 /* Page 4k or 64k */
AnnaBridge 153:b484a57bc302 1534 /** \brief Set 4k/64k page execution-never attribute
AnnaBridge 153:b484a57bc302 1535
AnnaBridge 153:b484a57bc302 1536 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 153:b484a57bc302 1537 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge 153:b484a57bc302 1538 \param [in] page Page size: PAGE_4k, PAGE_64k,
AnnaBridge 153:b484a57bc302 1539
AnnaBridge 153:b484a57bc302 1540 \return 0
AnnaBridge 153:b484a57bc302 1541 */
AnnaBridge 153:b484a57bc302 1542 __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
AnnaBridge 153:b484a57bc302 1543 {
AnnaBridge 153:b484a57bc302 1544 if (page == PAGE_4k)
AnnaBridge 153:b484a57bc302 1545 {
AnnaBridge 153:b484a57bc302 1546 *descriptor_l2 &= PAGE_XN_4K_MASK;
AnnaBridge 153:b484a57bc302 1547 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
AnnaBridge 153:b484a57bc302 1548 }
AnnaBridge 153:b484a57bc302 1549 else
AnnaBridge 153:b484a57bc302 1550 {
AnnaBridge 153:b484a57bc302 1551 *descriptor_l2 &= PAGE_XN_64K_MASK;
AnnaBridge 153:b484a57bc302 1552 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
AnnaBridge 153:b484a57bc302 1553 }
AnnaBridge 153:b484a57bc302 1554 return 0;
AnnaBridge 153:b484a57bc302 1555 }
AnnaBridge 153:b484a57bc302 1556
AnnaBridge 153:b484a57bc302 1557 /** \brief Set 4k/64k page domain
AnnaBridge 153:b484a57bc302 1558
AnnaBridge 153:b484a57bc302 1559 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 153:b484a57bc302 1560 \param [in] domain Page domain
AnnaBridge 153:b484a57bc302 1561
AnnaBridge 153:b484a57bc302 1562 \return 0
AnnaBridge 153:b484a57bc302 1563 */
AnnaBridge 153:b484a57bc302 1564 __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge 153:b484a57bc302 1565 {
AnnaBridge 153:b484a57bc302 1566 *descriptor_l1 &= PAGE_DOMAIN_MASK;
AnnaBridge 153:b484a57bc302 1567 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
AnnaBridge 153:b484a57bc302 1568 return 0;
AnnaBridge 153:b484a57bc302 1569 }
AnnaBridge 153:b484a57bc302 1570
AnnaBridge 153:b484a57bc302 1571 /** \brief Set 4k/64k page parity check
AnnaBridge 153:b484a57bc302 1572
AnnaBridge 153:b484a57bc302 1573 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 153:b484a57bc302 1574 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge 153:b484a57bc302 1575
AnnaBridge 153:b484a57bc302 1576 \return 0
AnnaBridge 153:b484a57bc302 1577 */
AnnaBridge 153:b484a57bc302 1578 __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge 153:b484a57bc302 1579 {
AnnaBridge 153:b484a57bc302 1580 *descriptor_l1 &= SECTION_P_MASK;
AnnaBridge 153:b484a57bc302 1581 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge 153:b484a57bc302 1582 return 0;
AnnaBridge 153:b484a57bc302 1583 }
AnnaBridge 153:b484a57bc302 1584
AnnaBridge 153:b484a57bc302 1585 /** \brief Set 4k/64k page access privileges
AnnaBridge 153:b484a57bc302 1586
AnnaBridge 153:b484a57bc302 1587 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 153:b484a57bc302 1588 \param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge 153:b484a57bc302 1589 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge 153:b484a57bc302 1590 \param [in] afe Access flag enable
AnnaBridge 153:b484a57bc302 1591
AnnaBridge 153:b484a57bc302 1592 \return 0
AnnaBridge 153:b484a57bc302 1593 */
AnnaBridge 153:b484a57bc302 1594 __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge 153:b484a57bc302 1595 {
AnnaBridge 153:b484a57bc302 1596 uint32_t ap = 0;
AnnaBridge 153:b484a57bc302 1597
AnnaBridge 153:b484a57bc302 1598 if (afe == 0) { //full access
AnnaBridge 153:b484a57bc302 1599 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge 153:b484a57bc302 1600 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 153:b484a57bc302 1601 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge 153:b484a57bc302 1602 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 153:b484a57bc302 1603 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 153:b484a57bc302 1604 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
AnnaBridge 153:b484a57bc302 1605 }
AnnaBridge 153:b484a57bc302 1606
AnnaBridge 153:b484a57bc302 1607 else { //Simplified access
AnnaBridge 153:b484a57bc302 1608 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 153:b484a57bc302 1609 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 153:b484a57bc302 1610 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 153:b484a57bc302 1611 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 153:b484a57bc302 1612 }
AnnaBridge 153:b484a57bc302 1613
AnnaBridge 153:b484a57bc302 1614 *descriptor_l2 &= PAGE_AP_MASK;
AnnaBridge 153:b484a57bc302 1615 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
AnnaBridge 153:b484a57bc302 1616 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
AnnaBridge 153:b484a57bc302 1617
AnnaBridge 153:b484a57bc302 1618 return 0;
AnnaBridge 153:b484a57bc302 1619 }
AnnaBridge 153:b484a57bc302 1620
AnnaBridge 153:b484a57bc302 1621 /** \brief Set 4k/64k page shareability
AnnaBridge 153:b484a57bc302 1622
AnnaBridge 153:b484a57bc302 1623 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 153:b484a57bc302 1624 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
AnnaBridge 153:b484a57bc302 1625
AnnaBridge 153:b484a57bc302 1626 \return 0
AnnaBridge 153:b484a57bc302 1627 */
AnnaBridge 153:b484a57bc302 1628 __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
AnnaBridge 153:b484a57bc302 1629 {
AnnaBridge 153:b484a57bc302 1630 *descriptor_l2 &= PAGE_S_MASK;
AnnaBridge 153:b484a57bc302 1631 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
AnnaBridge 153:b484a57bc302 1632 return 0;
AnnaBridge 153:b484a57bc302 1633 }
AnnaBridge 153:b484a57bc302 1634
AnnaBridge 153:b484a57bc302 1635 /** \brief Set 4k/64k page Global attribute
AnnaBridge 153:b484a57bc302 1636
AnnaBridge 153:b484a57bc302 1637 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 153:b484a57bc302 1638 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
AnnaBridge 153:b484a57bc302 1639
AnnaBridge 153:b484a57bc302 1640 \return 0
AnnaBridge 153:b484a57bc302 1641 */
AnnaBridge 153:b484a57bc302 1642 __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
AnnaBridge 153:b484a57bc302 1643 {
AnnaBridge 153:b484a57bc302 1644 *descriptor_l2 &= PAGE_NG_MASK;
AnnaBridge 153:b484a57bc302 1645 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
AnnaBridge 153:b484a57bc302 1646 return 0;
AnnaBridge 153:b484a57bc302 1647 }
AnnaBridge 153:b484a57bc302 1648
AnnaBridge 153:b484a57bc302 1649 /** \brief Set 4k/64k page Security attribute
AnnaBridge 153:b484a57bc302 1650
AnnaBridge 153:b484a57bc302 1651 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 153:b484a57bc302 1652 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
AnnaBridge 153:b484a57bc302 1653
AnnaBridge 153:b484a57bc302 1654 \return 0
AnnaBridge 153:b484a57bc302 1655 */
AnnaBridge 153:b484a57bc302 1656 __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge 153:b484a57bc302 1657 {
AnnaBridge 153:b484a57bc302 1658 *descriptor_l1 &= PAGE_NS_MASK;
AnnaBridge 153:b484a57bc302 1659 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
AnnaBridge 153:b484a57bc302 1660 return 0;
AnnaBridge 153:b484a57bc302 1661 }
AnnaBridge 153:b484a57bc302 1662
AnnaBridge 153:b484a57bc302 1663 /** \brief Set Section memory attributes
AnnaBridge 153:b484a57bc302 1664
AnnaBridge 153:b484a57bc302 1665 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 153:b484a57bc302 1666 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge 153:b484a57bc302 1667 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 153:b484a57bc302 1668 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 153:b484a57bc302 1669
AnnaBridge 153:b484a57bc302 1670 \return 0
AnnaBridge 153:b484a57bc302 1671 */
AnnaBridge 153:b484a57bc302 1672 __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
AnnaBridge 153:b484a57bc302 1673 {
AnnaBridge 153:b484a57bc302 1674 *descriptor_l1 &= SECTION_TEXCB_MASK;
AnnaBridge 153:b484a57bc302 1675
AnnaBridge 153:b484a57bc302 1676 if (STRONGLY_ORDERED == mem)
AnnaBridge 153:b484a57bc302 1677 {
AnnaBridge 153:b484a57bc302 1678 return 0;
AnnaBridge 153:b484a57bc302 1679 }
AnnaBridge 153:b484a57bc302 1680 else if (SHARED_DEVICE == mem)
AnnaBridge 153:b484a57bc302 1681 {
AnnaBridge 153:b484a57bc302 1682 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
AnnaBridge 153:b484a57bc302 1683 }
AnnaBridge 153:b484a57bc302 1684 else if (NON_SHARED_DEVICE == mem)
AnnaBridge 153:b484a57bc302 1685 {
AnnaBridge 153:b484a57bc302 1686 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
AnnaBridge 153:b484a57bc302 1687 }
AnnaBridge 153:b484a57bc302 1688 else if (NORMAL == mem)
AnnaBridge 153:b484a57bc302 1689 {
AnnaBridge 153:b484a57bc302 1690 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
AnnaBridge 153:b484a57bc302 1691 switch(inner)
AnnaBridge 153:b484a57bc302 1692 {
AnnaBridge 153:b484a57bc302 1693 case NON_CACHEABLE:
AnnaBridge 153:b484a57bc302 1694 break;
AnnaBridge 153:b484a57bc302 1695 case WB_WA:
AnnaBridge 153:b484a57bc302 1696 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
AnnaBridge 153:b484a57bc302 1697 break;
AnnaBridge 153:b484a57bc302 1698 case WT:
AnnaBridge 153:b484a57bc302 1699 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
AnnaBridge 153:b484a57bc302 1700 break;
AnnaBridge 153:b484a57bc302 1701 case WB_NO_WA:
AnnaBridge 153:b484a57bc302 1702 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
AnnaBridge 153:b484a57bc302 1703 break;
AnnaBridge 153:b484a57bc302 1704 }
AnnaBridge 153:b484a57bc302 1705 switch(outer)
AnnaBridge 153:b484a57bc302 1706 {
AnnaBridge 153:b484a57bc302 1707 case NON_CACHEABLE:
AnnaBridge 153:b484a57bc302 1708 break;
AnnaBridge 153:b484a57bc302 1709 case WB_WA:
AnnaBridge 153:b484a57bc302 1710 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
AnnaBridge 153:b484a57bc302 1711 break;
AnnaBridge 153:b484a57bc302 1712 case WT:
AnnaBridge 153:b484a57bc302 1713 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
AnnaBridge 153:b484a57bc302 1714 break;
AnnaBridge 153:b484a57bc302 1715 case WB_NO_WA:
AnnaBridge 153:b484a57bc302 1716 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
AnnaBridge 153:b484a57bc302 1717 break;
AnnaBridge 153:b484a57bc302 1718 }
AnnaBridge 153:b484a57bc302 1719 }
AnnaBridge 153:b484a57bc302 1720 return 0;
AnnaBridge 153:b484a57bc302 1721 }
AnnaBridge 153:b484a57bc302 1722
AnnaBridge 153:b484a57bc302 1723 /** \brief Set 4k/64k page memory attributes
AnnaBridge 153:b484a57bc302 1724
AnnaBridge 153:b484a57bc302 1725 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 153:b484a57bc302 1726 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge 153:b484a57bc302 1727 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 153:b484a57bc302 1728 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 153:b484a57bc302 1729 \param [in] page Page size
AnnaBridge 153:b484a57bc302 1730
AnnaBridge 153:b484a57bc302 1731 \return 0
AnnaBridge 153:b484a57bc302 1732 */
AnnaBridge 153:b484a57bc302 1733 __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
AnnaBridge 153:b484a57bc302 1734 {
AnnaBridge 153:b484a57bc302 1735 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
AnnaBridge 153:b484a57bc302 1736
AnnaBridge 153:b484a57bc302 1737 if (page == PAGE_64k)
AnnaBridge 153:b484a57bc302 1738 {
AnnaBridge 153:b484a57bc302 1739 //same as section
AnnaBridge 153:b484a57bc302 1740 MMU_MemorySection(descriptor_l2, mem, outer, inner);
AnnaBridge 153:b484a57bc302 1741 }
AnnaBridge 153:b484a57bc302 1742 else
AnnaBridge 153:b484a57bc302 1743 {
AnnaBridge 153:b484a57bc302 1744 if (STRONGLY_ORDERED == mem)
AnnaBridge 153:b484a57bc302 1745 {
AnnaBridge 153:b484a57bc302 1746 return 0;
AnnaBridge 153:b484a57bc302 1747 }
AnnaBridge 153:b484a57bc302 1748 else if (SHARED_DEVICE == mem)
AnnaBridge 153:b484a57bc302 1749 {
AnnaBridge 153:b484a57bc302 1750 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
AnnaBridge 153:b484a57bc302 1751 }
AnnaBridge 153:b484a57bc302 1752 else if (NON_SHARED_DEVICE == mem)
AnnaBridge 153:b484a57bc302 1753 {
AnnaBridge 153:b484a57bc302 1754 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
AnnaBridge 153:b484a57bc302 1755 }
AnnaBridge 153:b484a57bc302 1756 else if (NORMAL == mem)
AnnaBridge 153:b484a57bc302 1757 {
AnnaBridge 153:b484a57bc302 1758 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
AnnaBridge 153:b484a57bc302 1759 switch(inner)
AnnaBridge 153:b484a57bc302 1760 {
AnnaBridge 153:b484a57bc302 1761 case NON_CACHEABLE:
AnnaBridge 153:b484a57bc302 1762 break;
AnnaBridge 153:b484a57bc302 1763 case WB_WA:
AnnaBridge 153:b484a57bc302 1764 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
AnnaBridge 153:b484a57bc302 1765 break;
AnnaBridge 153:b484a57bc302 1766 case WT:
AnnaBridge 153:b484a57bc302 1767 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
AnnaBridge 153:b484a57bc302 1768 break;
AnnaBridge 153:b484a57bc302 1769 case WB_NO_WA:
AnnaBridge 153:b484a57bc302 1770 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
AnnaBridge 153:b484a57bc302 1771 break;
AnnaBridge 153:b484a57bc302 1772 }
AnnaBridge 153:b484a57bc302 1773 switch(outer)
AnnaBridge 153:b484a57bc302 1774 {
AnnaBridge 153:b484a57bc302 1775 case NON_CACHEABLE:
AnnaBridge 153:b484a57bc302 1776 break;
AnnaBridge 153:b484a57bc302 1777 case WB_WA:
AnnaBridge 153:b484a57bc302 1778 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge 153:b484a57bc302 1779 break;
AnnaBridge 153:b484a57bc302 1780 case WT:
AnnaBridge 153:b484a57bc302 1781 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
AnnaBridge 153:b484a57bc302 1782 break;
AnnaBridge 153:b484a57bc302 1783 case WB_NO_WA:
AnnaBridge 153:b484a57bc302 1784 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge 153:b484a57bc302 1785 break;
AnnaBridge 153:b484a57bc302 1786 }
AnnaBridge 153:b484a57bc302 1787 }
AnnaBridge 153:b484a57bc302 1788 }
AnnaBridge 153:b484a57bc302 1789
AnnaBridge 153:b484a57bc302 1790 return 0;
AnnaBridge 153:b484a57bc302 1791 }
AnnaBridge 153:b484a57bc302 1792
AnnaBridge 153:b484a57bc302 1793 /** \brief Create a L1 section descriptor
AnnaBridge 153:b484a57bc302 1794
AnnaBridge 153:b484a57bc302 1795 \param [out] descriptor L1 descriptor
AnnaBridge 153:b484a57bc302 1796 \param [in] reg Section attributes
AnnaBridge 153:b484a57bc302 1797
AnnaBridge 153:b484a57bc302 1798 \return 0
AnnaBridge 153:b484a57bc302 1799 */
AnnaBridge 153:b484a57bc302 1800 __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
AnnaBridge 153:b484a57bc302 1801 {
AnnaBridge 153:b484a57bc302 1802 *descriptor = 0;
AnnaBridge 153:b484a57bc302 1803
AnnaBridge 153:b484a57bc302 1804 MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
AnnaBridge 153:b484a57bc302 1805 MMU_XNSection(descriptor,reg.xn_t);
AnnaBridge 153:b484a57bc302 1806 MMU_DomainSection(descriptor, reg.domain);
AnnaBridge 153:b484a57bc302 1807 MMU_PSection(descriptor, reg.e_t);
AnnaBridge 153:b484a57bc302 1808 MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
AnnaBridge 153:b484a57bc302 1809 MMU_SharedSection(descriptor,reg.sh_t);
AnnaBridge 153:b484a57bc302 1810 MMU_GlobalSection(descriptor,reg.g_t);
AnnaBridge 153:b484a57bc302 1811 MMU_SecureSection(descriptor,reg.sec_t);
AnnaBridge 153:b484a57bc302 1812 *descriptor &= SECTION_MASK;
AnnaBridge 153:b484a57bc302 1813 *descriptor |= SECTION_DESCRIPTOR;
AnnaBridge 153:b484a57bc302 1814
AnnaBridge 153:b484a57bc302 1815 return 0;
AnnaBridge 153:b484a57bc302 1816 }
AnnaBridge 153:b484a57bc302 1817
AnnaBridge 153:b484a57bc302 1818
AnnaBridge 153:b484a57bc302 1819 /** \brief Create a L1 and L2 4k/64k page descriptor
AnnaBridge 153:b484a57bc302 1820
AnnaBridge 153:b484a57bc302 1821 \param [out] descriptor L1 descriptor
AnnaBridge 153:b484a57bc302 1822 \param [out] descriptor2 L2 descriptor
AnnaBridge 153:b484a57bc302 1823 \param [in] reg 4k/64k page attributes
AnnaBridge 153:b484a57bc302 1824
AnnaBridge 153:b484a57bc302 1825 \return 0
AnnaBridge 153:b484a57bc302 1826 */
AnnaBridge 153:b484a57bc302 1827 __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
AnnaBridge 153:b484a57bc302 1828 {
AnnaBridge 153:b484a57bc302 1829 *descriptor = 0;
AnnaBridge 153:b484a57bc302 1830 *descriptor2 = 0;
AnnaBridge 153:b484a57bc302 1831
AnnaBridge 153:b484a57bc302 1832 switch (reg.rg_t)
AnnaBridge 153:b484a57bc302 1833 {
AnnaBridge 153:b484a57bc302 1834 case PAGE_4k:
AnnaBridge 153:b484a57bc302 1835 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
AnnaBridge 153:b484a57bc302 1836 MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
AnnaBridge 153:b484a57bc302 1837 MMU_DomainPage(descriptor, reg.domain);
AnnaBridge 153:b484a57bc302 1838 MMU_PPage(descriptor, reg.e_t);
AnnaBridge 153:b484a57bc302 1839 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge 153:b484a57bc302 1840 MMU_SharedPage(descriptor2,reg.sh_t);
AnnaBridge 153:b484a57bc302 1841 MMU_GlobalPage(descriptor2,reg.g_t);
AnnaBridge 153:b484a57bc302 1842 MMU_SecurePage(descriptor,reg.sec_t);
AnnaBridge 153:b484a57bc302 1843 *descriptor &= PAGE_L1_MASK;
AnnaBridge 153:b484a57bc302 1844 *descriptor |= PAGE_L1_DESCRIPTOR;
AnnaBridge 153:b484a57bc302 1845 *descriptor2 &= PAGE_L2_4K_MASK;
AnnaBridge 153:b484a57bc302 1846 *descriptor2 |= PAGE_L2_4K_DESC;
AnnaBridge 153:b484a57bc302 1847 break;
AnnaBridge 153:b484a57bc302 1848
AnnaBridge 153:b484a57bc302 1849 case PAGE_64k:
AnnaBridge 153:b484a57bc302 1850 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
AnnaBridge 153:b484a57bc302 1851 MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
AnnaBridge 153:b484a57bc302 1852 MMU_DomainPage(descriptor, reg.domain);
AnnaBridge 153:b484a57bc302 1853 MMU_PPage(descriptor, reg.e_t);
AnnaBridge 153:b484a57bc302 1854 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge 153:b484a57bc302 1855 MMU_SharedPage(descriptor2,reg.sh_t);
AnnaBridge 153:b484a57bc302 1856 MMU_GlobalPage(descriptor2,reg.g_t);
AnnaBridge 153:b484a57bc302 1857 MMU_SecurePage(descriptor,reg.sec_t);
AnnaBridge 153:b484a57bc302 1858 *descriptor &= PAGE_L1_MASK;
AnnaBridge 153:b484a57bc302 1859 *descriptor |= PAGE_L1_DESCRIPTOR;
AnnaBridge 153:b484a57bc302 1860 *descriptor2 &= PAGE_L2_64K_MASK;
AnnaBridge 153:b484a57bc302 1861 *descriptor2 |= PAGE_L2_64K_DESC;
AnnaBridge 153:b484a57bc302 1862 break;
AnnaBridge 153:b484a57bc302 1863
AnnaBridge 153:b484a57bc302 1864 case SECTION:
AnnaBridge 153:b484a57bc302 1865 //error
AnnaBridge 153:b484a57bc302 1866 break;
AnnaBridge 153:b484a57bc302 1867 }
AnnaBridge 153:b484a57bc302 1868
AnnaBridge 153:b484a57bc302 1869 return 0;
AnnaBridge 153:b484a57bc302 1870 }
AnnaBridge 153:b484a57bc302 1871
AnnaBridge 153:b484a57bc302 1872 /** \brief Create a 1MB Section
AnnaBridge 153:b484a57bc302 1873
AnnaBridge 153:b484a57bc302 1874 \param [in] ttb Translation table base address
AnnaBridge 153:b484a57bc302 1875 \param [in] base_address Section base address
AnnaBridge 153:b484a57bc302 1876 \param [in] count Number of sections to create
AnnaBridge 153:b484a57bc302 1877 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 153:b484a57bc302 1878
AnnaBridge 153:b484a57bc302 1879 */
AnnaBridge 153:b484a57bc302 1880 __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
AnnaBridge 153:b484a57bc302 1881 {
AnnaBridge 153:b484a57bc302 1882 uint32_t offset;
AnnaBridge 153:b484a57bc302 1883 uint32_t entry;
AnnaBridge 153:b484a57bc302 1884 uint32_t i;
AnnaBridge 153:b484a57bc302 1885
AnnaBridge 153:b484a57bc302 1886 offset = base_address >> 20;
AnnaBridge 153:b484a57bc302 1887 entry = (base_address & 0xFFF00000) | descriptor_l1;
AnnaBridge 153:b484a57bc302 1888
AnnaBridge 153:b484a57bc302 1889 //4 bytes aligned
AnnaBridge 153:b484a57bc302 1890 ttb = ttb + offset;
AnnaBridge 153:b484a57bc302 1891
AnnaBridge 153:b484a57bc302 1892 for (i = 0; i < count; i++ )
AnnaBridge 153:b484a57bc302 1893 {
AnnaBridge 153:b484a57bc302 1894 //4 bytes aligned
AnnaBridge 153:b484a57bc302 1895 *ttb++ = entry;
AnnaBridge 153:b484a57bc302 1896 entry += OFFSET_1M;
AnnaBridge 153:b484a57bc302 1897 }
AnnaBridge 153:b484a57bc302 1898 }
AnnaBridge 153:b484a57bc302 1899
AnnaBridge 153:b484a57bc302 1900 /** \brief Create a 4k page entry
AnnaBridge 153:b484a57bc302 1901
AnnaBridge 153:b484a57bc302 1902 \param [in] ttb L1 table base address
AnnaBridge 153:b484a57bc302 1903 \param [in] base_address 4k base address
AnnaBridge 153:b484a57bc302 1904 \param [in] count Number of 4k pages to create
AnnaBridge 153:b484a57bc302 1905 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 153:b484a57bc302 1906 \param [in] ttb_l2 L2 table base address
AnnaBridge 153:b484a57bc302 1907 \param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge 153:b484a57bc302 1908
AnnaBridge 153:b484a57bc302 1909 */
AnnaBridge 153:b484a57bc302 1910 __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
AnnaBridge 153:b484a57bc302 1911 {
AnnaBridge 153:b484a57bc302 1912
AnnaBridge 153:b484a57bc302 1913 uint32_t offset, offset2;
AnnaBridge 153:b484a57bc302 1914 uint32_t entry, entry2;
AnnaBridge 153:b484a57bc302 1915 uint32_t i;
AnnaBridge 153:b484a57bc302 1916
AnnaBridge 153:b484a57bc302 1917 offset = base_address >> 20;
AnnaBridge 153:b484a57bc302 1918 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
AnnaBridge 153:b484a57bc302 1919
AnnaBridge 153:b484a57bc302 1920 //4 bytes aligned
AnnaBridge 153:b484a57bc302 1921 ttb += offset;
AnnaBridge 153:b484a57bc302 1922 //create l1_entry
AnnaBridge 153:b484a57bc302 1923 *ttb = entry;
AnnaBridge 153:b484a57bc302 1924
AnnaBridge 153:b484a57bc302 1925 offset2 = (base_address & 0xff000) >> 12;
AnnaBridge 153:b484a57bc302 1926 ttb_l2 += offset2;
AnnaBridge 153:b484a57bc302 1927 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
AnnaBridge 153:b484a57bc302 1928 for (i = 0; i < count; i++ )
AnnaBridge 153:b484a57bc302 1929 {
AnnaBridge 153:b484a57bc302 1930 //4 bytes aligned
AnnaBridge 153:b484a57bc302 1931 *ttb_l2++ = entry2;
AnnaBridge 153:b484a57bc302 1932 entry2 += OFFSET_4K;
AnnaBridge 153:b484a57bc302 1933 }
AnnaBridge 153:b484a57bc302 1934 }
AnnaBridge 153:b484a57bc302 1935
AnnaBridge 153:b484a57bc302 1936 /** \brief Create a 64k page entry
AnnaBridge 153:b484a57bc302 1937
AnnaBridge 153:b484a57bc302 1938 \param [in] ttb L1 table base address
AnnaBridge 153:b484a57bc302 1939 \param [in] base_address 64k base address
AnnaBridge 153:b484a57bc302 1940 \param [in] count Number of 64k pages to create
AnnaBridge 153:b484a57bc302 1941 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 153:b484a57bc302 1942 \param [in] ttb_l2 L2 table base address
AnnaBridge 153:b484a57bc302 1943 \param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge 153:b484a57bc302 1944
AnnaBridge 153:b484a57bc302 1945 */
AnnaBridge 153:b484a57bc302 1946 __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
AnnaBridge 153:b484a57bc302 1947 {
AnnaBridge 153:b484a57bc302 1948 uint32_t offset, offset2;
AnnaBridge 153:b484a57bc302 1949 uint32_t entry, entry2;
AnnaBridge 153:b484a57bc302 1950 uint32_t i,j;
AnnaBridge 153:b484a57bc302 1951
AnnaBridge 153:b484a57bc302 1952
AnnaBridge 153:b484a57bc302 1953 offset = base_address >> 20;
AnnaBridge 153:b484a57bc302 1954 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
AnnaBridge 153:b484a57bc302 1955
AnnaBridge 153:b484a57bc302 1956 //4 bytes aligned
AnnaBridge 153:b484a57bc302 1957 ttb += offset;
AnnaBridge 153:b484a57bc302 1958 //create l1_entry
AnnaBridge 153:b484a57bc302 1959 *ttb = entry;
AnnaBridge 153:b484a57bc302 1960
AnnaBridge 153:b484a57bc302 1961 offset2 = (base_address & 0xff000) >> 12;
AnnaBridge 153:b484a57bc302 1962 ttb_l2 += offset2;
AnnaBridge 153:b484a57bc302 1963 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
AnnaBridge 153:b484a57bc302 1964 for (i = 0; i < count; i++ )
AnnaBridge 153:b484a57bc302 1965 {
AnnaBridge 153:b484a57bc302 1966 //create 16 entries
AnnaBridge 153:b484a57bc302 1967 for (j = 0; j < 16; j++)
AnnaBridge 153:b484a57bc302 1968 {
AnnaBridge 153:b484a57bc302 1969 //4 bytes aligned
AnnaBridge 153:b484a57bc302 1970 *ttb_l2++ = entry2;
AnnaBridge 153:b484a57bc302 1971 }
AnnaBridge 153:b484a57bc302 1972 entry2 += OFFSET_64K;
AnnaBridge 153:b484a57bc302 1973 }
AnnaBridge 153:b484a57bc302 1974 }
AnnaBridge 153:b484a57bc302 1975
AnnaBridge 153:b484a57bc302 1976 /** \brief Enable MMU
AnnaBridge 153:b484a57bc302 1977
AnnaBridge 153:b484a57bc302 1978 Enable MMU
AnnaBridge 153:b484a57bc302 1979 */
AnnaBridge 153:b484a57bc302 1980 __STATIC_INLINE void MMU_Enable(void) {
AnnaBridge 153:b484a57bc302 1981 // Set M bit 0 to enable the MMU
AnnaBridge 153:b484a57bc302 1982 // Set AFE bit to enable simplified access permissions model
AnnaBridge 153:b484a57bc302 1983 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 153:b484a57bc302 1984 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 153:b484a57bc302 1985 __ISB();
AnnaBridge 153:b484a57bc302 1986 }
AnnaBridge 153:b484a57bc302 1987
AnnaBridge 153:b484a57bc302 1988 /** \brief Disable MMU
AnnaBridge 153:b484a57bc302 1989
AnnaBridge 153:b484a57bc302 1990 Disable MMU
AnnaBridge 153:b484a57bc302 1991 */
AnnaBridge 153:b484a57bc302 1992 __STATIC_INLINE void MMU_Disable(void) {
AnnaBridge 153:b484a57bc302 1993 // Clear M bit 0 to disable the MMU
AnnaBridge 153:b484a57bc302 1994 __set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge 153:b484a57bc302 1995 __ISB();
AnnaBridge 153:b484a57bc302 1996 }
AnnaBridge 153:b484a57bc302 1997
AnnaBridge 153:b484a57bc302 1998 /** \brief Invalidate entire unified TLB
AnnaBridge 153:b484a57bc302 1999
AnnaBridge 153:b484a57bc302 2000 TLBIALL. Invalidate entire unified TLB
AnnaBridge 153:b484a57bc302 2001 */
AnnaBridge 153:b484a57bc302 2002
AnnaBridge 153:b484a57bc302 2003 __STATIC_INLINE void MMU_InvalidateTLB(void) {
AnnaBridge 153:b484a57bc302 2004 __set_TLBIALL(0);
AnnaBridge 153:b484a57bc302 2005 __DSB(); //ensure completion of the invalidation
AnnaBridge 153:b484a57bc302 2006 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 153:b484a57bc302 2007 }
AnnaBridge 153:b484a57bc302 2008
AnnaBridge 153:b484a57bc302 2009
AnnaBridge 153:b484a57bc302 2010 #ifdef __cplusplus
AnnaBridge 153:b484a57bc302 2011 }
AnnaBridge 153:b484a57bc302 2012 #endif
AnnaBridge 153:b484a57bc302 2013
AnnaBridge 153:b484a57bc302 2014 #endif /* __CORE_CA_H_DEPENDANT */
AnnaBridge 153:b484a57bc302 2015
AnnaBridge 153:b484a57bc302 2016 #endif /* __CMSIS_GENERIC */