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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_LPC1769/core_cm23.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Child:
160:5571c4ff569f
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**************************************************************************//**
AnnaBridge 157:e7ca05fa8600 2 * @file core_cm23.h
AnnaBridge 157:e7ca05fa8600 3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
AnnaBridge 157:e7ca05fa8600 4 * @version V5.0.2
AnnaBridge 157:e7ca05fa8600 5 * @date 13. February 2017
AnnaBridge 157:e7ca05fa8600 6 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 7 /*
AnnaBridge 157:e7ca05fa8600 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 157:e7ca05fa8600 9 *
AnnaBridge 157:e7ca05fa8600 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 157:e7ca05fa8600 11 *
AnnaBridge 157:e7ca05fa8600 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 157:e7ca05fa8600 13 * not use this file except in compliance with the License.
AnnaBridge 157:e7ca05fa8600 14 * You may obtain a copy of the License at
AnnaBridge 157:e7ca05fa8600 15 *
AnnaBridge 157:e7ca05fa8600 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 157:e7ca05fa8600 17 *
AnnaBridge 157:e7ca05fa8600 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 157:e7ca05fa8600 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 157:e7ca05fa8600 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 157:e7ca05fa8600 21 * See the License for the specific language governing permissions and
AnnaBridge 157:e7ca05fa8600 22 * limitations under the License.
AnnaBridge 157:e7ca05fa8600 23 */
AnnaBridge 157:e7ca05fa8600 24
AnnaBridge 157:e7ca05fa8600 25 #if defined ( __ICCARM__ )
AnnaBridge 157:e7ca05fa8600 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 157:e7ca05fa8600 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 157:e7ca05fa8600 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 157:e7ca05fa8600 29 #endif
AnnaBridge 157:e7ca05fa8600 30
AnnaBridge 157:e7ca05fa8600 31 #ifndef __CORE_CM23_H_GENERIC
AnnaBridge 157:e7ca05fa8600 32 #define __CORE_CM23_H_GENERIC
AnnaBridge 157:e7ca05fa8600 33
AnnaBridge 157:e7ca05fa8600 34 #include <stdint.h>
AnnaBridge 157:e7ca05fa8600 35
AnnaBridge 157:e7ca05fa8600 36 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 37 extern "C" {
AnnaBridge 157:e7ca05fa8600 38 #endif
AnnaBridge 157:e7ca05fa8600 39
AnnaBridge 157:e7ca05fa8600 40 /**
AnnaBridge 157:e7ca05fa8600 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 157:e7ca05fa8600 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 157:e7ca05fa8600 43
AnnaBridge 157:e7ca05fa8600 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 157:e7ca05fa8600 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 157:e7ca05fa8600 46
AnnaBridge 157:e7ca05fa8600 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 157:e7ca05fa8600 48 Unions are used for effective representation of core registers.
AnnaBridge 157:e7ca05fa8600 49
AnnaBridge 157:e7ca05fa8600 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 157:e7ca05fa8600 51 Function-like macros are used to allow more efficient code.
AnnaBridge 157:e7ca05fa8600 52 */
AnnaBridge 157:e7ca05fa8600 53
AnnaBridge 157:e7ca05fa8600 54
AnnaBridge 157:e7ca05fa8600 55 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 56 * CMSIS definitions
AnnaBridge 157:e7ca05fa8600 57 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 58 /**
AnnaBridge 157:e7ca05fa8600 59 \ingroup Cortex_M23
AnnaBridge 157:e7ca05fa8600 60 @{
AnnaBridge 157:e7ca05fa8600 61 */
AnnaBridge 157:e7ca05fa8600 62
AnnaBridge 157:e7ca05fa8600 63 /* CMSIS cmGrebe definitions */
AnnaBridge 157:e7ca05fa8600 64 #define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 157:e7ca05fa8600 65 #define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 157:e7ca05fa8600 66 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 157:e7ca05fa8600 67 __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 157:e7ca05fa8600 68
AnnaBridge 157:e7ca05fa8600 69 #define __CORTEX_M (23U) /*!< Cortex-M Core */
AnnaBridge 157:e7ca05fa8600 70
AnnaBridge 157:e7ca05fa8600 71 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 157:e7ca05fa8600 72 This core does not support an FPU at all
AnnaBridge 157:e7ca05fa8600 73 */
AnnaBridge 157:e7ca05fa8600 74 #define __FPU_USED 0U
AnnaBridge 157:e7ca05fa8600 75
AnnaBridge 157:e7ca05fa8600 76 #if defined ( __CC_ARM )
AnnaBridge 157:e7ca05fa8600 77 #if defined __TARGET_FPU_VFP
AnnaBridge 157:e7ca05fa8600 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 79 #endif
AnnaBridge 157:e7ca05fa8600 80
AnnaBridge 157:e7ca05fa8600 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 157:e7ca05fa8600 82 #if defined __ARM_PCS_VFP
AnnaBridge 157:e7ca05fa8600 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 84 #endif
AnnaBridge 157:e7ca05fa8600 85
AnnaBridge 157:e7ca05fa8600 86 #elif defined ( __GNUC__ )
AnnaBridge 157:e7ca05fa8600 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 157:e7ca05fa8600 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 89 #endif
AnnaBridge 157:e7ca05fa8600 90
AnnaBridge 157:e7ca05fa8600 91 #elif defined ( __ICCARM__ )
AnnaBridge 157:e7ca05fa8600 92 #if defined __ARMVFP__
AnnaBridge 157:e7ca05fa8600 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 94 #endif
AnnaBridge 157:e7ca05fa8600 95
AnnaBridge 157:e7ca05fa8600 96 #elif defined ( __TI_ARM__ )
AnnaBridge 157:e7ca05fa8600 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 157:e7ca05fa8600 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 99 #endif
AnnaBridge 157:e7ca05fa8600 100
AnnaBridge 157:e7ca05fa8600 101 #elif defined ( __TASKING__ )
AnnaBridge 157:e7ca05fa8600 102 #if defined __FPU_VFP__
AnnaBridge 157:e7ca05fa8600 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 104 #endif
AnnaBridge 157:e7ca05fa8600 105
AnnaBridge 157:e7ca05fa8600 106 #elif defined ( __CSMC__ )
AnnaBridge 157:e7ca05fa8600 107 #if ( __CSMC__ & 0x400U)
AnnaBridge 157:e7ca05fa8600 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 157:e7ca05fa8600 109 #endif
AnnaBridge 157:e7ca05fa8600 110
AnnaBridge 157:e7ca05fa8600 111 #endif
AnnaBridge 157:e7ca05fa8600 112
AnnaBridge 157:e7ca05fa8600 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 157:e7ca05fa8600 114
AnnaBridge 157:e7ca05fa8600 115
AnnaBridge 157:e7ca05fa8600 116 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 117 }
AnnaBridge 157:e7ca05fa8600 118 #endif
AnnaBridge 157:e7ca05fa8600 119
AnnaBridge 157:e7ca05fa8600 120 #endif /* __CORE_CM23_H_GENERIC */
AnnaBridge 157:e7ca05fa8600 121
AnnaBridge 157:e7ca05fa8600 122 #ifndef __CMSIS_GENERIC
AnnaBridge 157:e7ca05fa8600 123
AnnaBridge 157:e7ca05fa8600 124 #ifndef __CORE_CM23_H_DEPENDANT
AnnaBridge 157:e7ca05fa8600 125 #define __CORE_CM23_H_DEPENDANT
AnnaBridge 157:e7ca05fa8600 126
AnnaBridge 157:e7ca05fa8600 127 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 128 extern "C" {
AnnaBridge 157:e7ca05fa8600 129 #endif
AnnaBridge 157:e7ca05fa8600 130
AnnaBridge 157:e7ca05fa8600 131 /* check device defines and use defaults */
AnnaBridge 157:e7ca05fa8600 132 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 157:e7ca05fa8600 133 #ifndef __CM23_REV
AnnaBridge 157:e7ca05fa8600 134 #define __CM23_REV 0x0000U
AnnaBridge 157:e7ca05fa8600 135 #warning "__CM23_REV not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 136 #endif
AnnaBridge 157:e7ca05fa8600 137
AnnaBridge 157:e7ca05fa8600 138 #ifndef __FPU_PRESENT
AnnaBridge 157:e7ca05fa8600 139 #define __FPU_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 140 #warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 141 #endif
AnnaBridge 157:e7ca05fa8600 142
AnnaBridge 157:e7ca05fa8600 143 #ifndef __MPU_PRESENT
AnnaBridge 157:e7ca05fa8600 144 #define __MPU_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 145 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 146 #endif
AnnaBridge 157:e7ca05fa8600 147
AnnaBridge 157:e7ca05fa8600 148 #ifndef __SAUREGION_PRESENT
AnnaBridge 157:e7ca05fa8600 149 #define __SAUREGION_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 150 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 151 #endif
AnnaBridge 157:e7ca05fa8600 152
AnnaBridge 157:e7ca05fa8600 153 #ifndef __VTOR_PRESENT
AnnaBridge 157:e7ca05fa8600 154 #define __VTOR_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 155 #warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 156 #endif
AnnaBridge 157:e7ca05fa8600 157
AnnaBridge 157:e7ca05fa8600 158 #ifndef __NVIC_PRIO_BITS
AnnaBridge 157:e7ca05fa8600 159 #define __NVIC_PRIO_BITS 2U
AnnaBridge 157:e7ca05fa8600 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 161 #endif
AnnaBridge 157:e7ca05fa8600 162
AnnaBridge 157:e7ca05fa8600 163 #ifndef __Vendor_SysTickConfig
AnnaBridge 157:e7ca05fa8600 164 #define __Vendor_SysTickConfig 0U
AnnaBridge 157:e7ca05fa8600 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 166 #endif
AnnaBridge 157:e7ca05fa8600 167
AnnaBridge 157:e7ca05fa8600 168 #ifndef __ETM_PRESENT
AnnaBridge 157:e7ca05fa8600 169 #define __ETM_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 170 #warning "__ETM_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 171 #endif
AnnaBridge 157:e7ca05fa8600 172
AnnaBridge 157:e7ca05fa8600 173 #ifndef __MTB_PRESENT
AnnaBridge 157:e7ca05fa8600 174 #define __MTB_PRESENT 0U
AnnaBridge 157:e7ca05fa8600 175 #warning "__MTB_PRESENT not defined in device header file; using default!"
AnnaBridge 157:e7ca05fa8600 176 #endif
AnnaBridge 157:e7ca05fa8600 177
AnnaBridge 157:e7ca05fa8600 178 #endif
AnnaBridge 157:e7ca05fa8600 179
AnnaBridge 157:e7ca05fa8600 180 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 157:e7ca05fa8600 181 /**
AnnaBridge 157:e7ca05fa8600 182 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 157:e7ca05fa8600 183
AnnaBridge 157:e7ca05fa8600 184 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 157:e7ca05fa8600 185 \li to specify the access to peripheral variables.
AnnaBridge 157:e7ca05fa8600 186 \li for automatic generation of peripheral register debug information.
AnnaBridge 157:e7ca05fa8600 187 */
AnnaBridge 157:e7ca05fa8600 188 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 189 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 157:e7ca05fa8600 190 #else
AnnaBridge 157:e7ca05fa8600 191 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 157:e7ca05fa8600 192 #endif
AnnaBridge 157:e7ca05fa8600 193 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 157:e7ca05fa8600 194 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 157:e7ca05fa8600 195
AnnaBridge 157:e7ca05fa8600 196 /* following defines should be used for structure members */
AnnaBridge 157:e7ca05fa8600 197 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 157:e7ca05fa8600 198 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 157:e7ca05fa8600 199 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 157:e7ca05fa8600 200
AnnaBridge 157:e7ca05fa8600 201 /*@} end of group Cortex_M23 */
AnnaBridge 157:e7ca05fa8600 202
AnnaBridge 157:e7ca05fa8600 203
AnnaBridge 157:e7ca05fa8600 204
AnnaBridge 157:e7ca05fa8600 205 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 206 * Register Abstraction
AnnaBridge 157:e7ca05fa8600 207 Core Register contain:
AnnaBridge 157:e7ca05fa8600 208 - Core Register
AnnaBridge 157:e7ca05fa8600 209 - Core NVIC Register
AnnaBridge 157:e7ca05fa8600 210 - Core SCB Register
AnnaBridge 157:e7ca05fa8600 211 - Core SysTick Register
AnnaBridge 157:e7ca05fa8600 212 - Core Debug Register
AnnaBridge 157:e7ca05fa8600 213 - Core MPU Register
AnnaBridge 157:e7ca05fa8600 214 - Core SAU Register
AnnaBridge 157:e7ca05fa8600 215 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 216 /**
AnnaBridge 157:e7ca05fa8600 217 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 157:e7ca05fa8600 218 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 157:e7ca05fa8600 219 */
AnnaBridge 157:e7ca05fa8600 220
AnnaBridge 157:e7ca05fa8600 221 /**
AnnaBridge 157:e7ca05fa8600 222 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 223 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 157:e7ca05fa8600 224 \brief Core Register type definitions.
AnnaBridge 157:e7ca05fa8600 225 @{
AnnaBridge 157:e7ca05fa8600 226 */
AnnaBridge 157:e7ca05fa8600 227
AnnaBridge 157:e7ca05fa8600 228 /**
AnnaBridge 157:e7ca05fa8600 229 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 157:e7ca05fa8600 230 */
AnnaBridge 157:e7ca05fa8600 231 typedef union
AnnaBridge 157:e7ca05fa8600 232 {
AnnaBridge 157:e7ca05fa8600 233 struct
AnnaBridge 157:e7ca05fa8600 234 {
AnnaBridge 157:e7ca05fa8600 235 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 157:e7ca05fa8600 236 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 157:e7ca05fa8600 237 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 157:e7ca05fa8600 238 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 157:e7ca05fa8600 239 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 157:e7ca05fa8600 240 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 241 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 242 } APSR_Type;
AnnaBridge 157:e7ca05fa8600 243
AnnaBridge 157:e7ca05fa8600 244 /* APSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 245 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 157:e7ca05fa8600 246 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 157:e7ca05fa8600 247
AnnaBridge 157:e7ca05fa8600 248 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 157:e7ca05fa8600 249 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 157:e7ca05fa8600 250
AnnaBridge 157:e7ca05fa8600 251 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 157:e7ca05fa8600 252 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 157:e7ca05fa8600 253
AnnaBridge 157:e7ca05fa8600 254 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 157:e7ca05fa8600 255 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 157:e7ca05fa8600 256
AnnaBridge 157:e7ca05fa8600 257
AnnaBridge 157:e7ca05fa8600 258 /**
AnnaBridge 157:e7ca05fa8600 259 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 157:e7ca05fa8600 260 */
AnnaBridge 157:e7ca05fa8600 261 typedef union
AnnaBridge 157:e7ca05fa8600 262 {
AnnaBridge 157:e7ca05fa8600 263 struct
AnnaBridge 157:e7ca05fa8600 264 {
AnnaBridge 157:e7ca05fa8600 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 157:e7ca05fa8600 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 157:e7ca05fa8600 267 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 268 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 269 } IPSR_Type;
AnnaBridge 157:e7ca05fa8600 270
AnnaBridge 157:e7ca05fa8600 271 /* IPSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 272 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 157:e7ca05fa8600 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 157:e7ca05fa8600 274
AnnaBridge 157:e7ca05fa8600 275
AnnaBridge 157:e7ca05fa8600 276 /**
AnnaBridge 157:e7ca05fa8600 277 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 157:e7ca05fa8600 278 */
AnnaBridge 157:e7ca05fa8600 279 typedef union
AnnaBridge 157:e7ca05fa8600 280 {
AnnaBridge 157:e7ca05fa8600 281 struct
AnnaBridge 157:e7ca05fa8600 282 {
AnnaBridge 157:e7ca05fa8600 283 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 157:e7ca05fa8600 284 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 157:e7ca05fa8600 285 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 157:e7ca05fa8600 286 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 157:e7ca05fa8600 287 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 157:e7ca05fa8600 288 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 157:e7ca05fa8600 289 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 157:e7ca05fa8600 290 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 157:e7ca05fa8600 291 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 292 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 293 } xPSR_Type;
AnnaBridge 157:e7ca05fa8600 294
AnnaBridge 157:e7ca05fa8600 295 /* xPSR Register Definitions */
AnnaBridge 157:e7ca05fa8600 296 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 157:e7ca05fa8600 297 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 157:e7ca05fa8600 298
AnnaBridge 157:e7ca05fa8600 299 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 157:e7ca05fa8600 300 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 157:e7ca05fa8600 301
AnnaBridge 157:e7ca05fa8600 302 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 157:e7ca05fa8600 303 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 157:e7ca05fa8600 304
AnnaBridge 157:e7ca05fa8600 305 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 157:e7ca05fa8600 306 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 157:e7ca05fa8600 307
AnnaBridge 157:e7ca05fa8600 308 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 157:e7ca05fa8600 309 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 157:e7ca05fa8600 310
AnnaBridge 157:e7ca05fa8600 311 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 157:e7ca05fa8600 312 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 157:e7ca05fa8600 313
AnnaBridge 157:e7ca05fa8600 314
AnnaBridge 157:e7ca05fa8600 315 /**
AnnaBridge 157:e7ca05fa8600 316 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 157:e7ca05fa8600 317 */
AnnaBridge 157:e7ca05fa8600 318 typedef union
AnnaBridge 157:e7ca05fa8600 319 {
AnnaBridge 157:e7ca05fa8600 320 struct
AnnaBridge 157:e7ca05fa8600 321 {
AnnaBridge 157:e7ca05fa8600 322 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 157:e7ca05fa8600 323 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
AnnaBridge 157:e7ca05fa8600 324 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 157:e7ca05fa8600 325 } b; /*!< Structure used for bit access */
AnnaBridge 157:e7ca05fa8600 326 uint32_t w; /*!< Type used for word access */
AnnaBridge 157:e7ca05fa8600 327 } CONTROL_Type;
AnnaBridge 157:e7ca05fa8600 328
AnnaBridge 157:e7ca05fa8600 329 /* CONTROL Register Definitions */
AnnaBridge 157:e7ca05fa8600 330 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 157:e7ca05fa8600 331 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 157:e7ca05fa8600 332
AnnaBridge 157:e7ca05fa8600 333 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 157:e7ca05fa8600 334 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 157:e7ca05fa8600 335
AnnaBridge 157:e7ca05fa8600 336 /*@} end of group CMSIS_CORE */
AnnaBridge 157:e7ca05fa8600 337
AnnaBridge 157:e7ca05fa8600 338
AnnaBridge 157:e7ca05fa8600 339 /**
AnnaBridge 157:e7ca05fa8600 340 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 157:e7ca05fa8600 342 \brief Type definitions for the NVIC Registers
AnnaBridge 157:e7ca05fa8600 343 @{
AnnaBridge 157:e7ca05fa8600 344 */
AnnaBridge 157:e7ca05fa8600 345
AnnaBridge 157:e7ca05fa8600 346 /**
AnnaBridge 157:e7ca05fa8600 347 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 157:e7ca05fa8600 348 */
AnnaBridge 157:e7ca05fa8600 349 typedef struct
AnnaBridge 157:e7ca05fa8600 350 {
AnnaBridge 157:e7ca05fa8600 351 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 157:e7ca05fa8600 352 uint32_t RESERVED0[16U];
AnnaBridge 157:e7ca05fa8600 353 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 157:e7ca05fa8600 354 uint32_t RSERVED1[16U];
AnnaBridge 157:e7ca05fa8600 355 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 157:e7ca05fa8600 356 uint32_t RESERVED2[16U];
AnnaBridge 157:e7ca05fa8600 357 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 157:e7ca05fa8600 358 uint32_t RESERVED3[16U];
AnnaBridge 157:e7ca05fa8600 359 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 157:e7ca05fa8600 360 uint32_t RESERVED4[16U];
AnnaBridge 157:e7ca05fa8600 361 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
AnnaBridge 157:e7ca05fa8600 362 uint32_t RESERVED5[16U];
AnnaBridge 157:e7ca05fa8600 363 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 157:e7ca05fa8600 364 } NVIC_Type;
AnnaBridge 157:e7ca05fa8600 365
AnnaBridge 157:e7ca05fa8600 366 /*@} end of group CMSIS_NVIC */
AnnaBridge 157:e7ca05fa8600 367
AnnaBridge 157:e7ca05fa8600 368
AnnaBridge 157:e7ca05fa8600 369 /**
AnnaBridge 157:e7ca05fa8600 370 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 371 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 157:e7ca05fa8600 372 \brief Type definitions for the System Control Block Registers
AnnaBridge 157:e7ca05fa8600 373 @{
AnnaBridge 157:e7ca05fa8600 374 */
AnnaBridge 157:e7ca05fa8600 375
AnnaBridge 157:e7ca05fa8600 376 /**
AnnaBridge 157:e7ca05fa8600 377 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 157:e7ca05fa8600 378 */
AnnaBridge 157:e7ca05fa8600 379 typedef struct
AnnaBridge 157:e7ca05fa8600 380 {
AnnaBridge 157:e7ca05fa8600 381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 157:e7ca05fa8600 382 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 157:e7ca05fa8600 383 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 384 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 157:e7ca05fa8600 385 #else
AnnaBridge 157:e7ca05fa8600 386 uint32_t RESERVED0;
AnnaBridge 157:e7ca05fa8600 387 #endif
AnnaBridge 157:e7ca05fa8600 388 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 157:e7ca05fa8600 389 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 157:e7ca05fa8600 390 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 157:e7ca05fa8600 391 uint32_t RESERVED1;
AnnaBridge 157:e7ca05fa8600 392 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 157:e7ca05fa8600 393 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 157:e7ca05fa8600 394 } SCB_Type;
AnnaBridge 157:e7ca05fa8600 395
AnnaBridge 157:e7ca05fa8600 396 /* SCB CPUID Register Definitions */
AnnaBridge 157:e7ca05fa8600 397 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 157:e7ca05fa8600 398 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 157:e7ca05fa8600 399
AnnaBridge 157:e7ca05fa8600 400 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 157:e7ca05fa8600 401 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 157:e7ca05fa8600 402
AnnaBridge 157:e7ca05fa8600 403 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 157:e7ca05fa8600 404 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 157:e7ca05fa8600 405
AnnaBridge 157:e7ca05fa8600 406 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 157:e7ca05fa8600 407 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 157:e7ca05fa8600 408
AnnaBridge 157:e7ca05fa8600 409 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 157:e7ca05fa8600 410 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 157:e7ca05fa8600 411
AnnaBridge 157:e7ca05fa8600 412 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 157:e7ca05fa8600 413 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
AnnaBridge 157:e7ca05fa8600 414 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
AnnaBridge 157:e7ca05fa8600 415
AnnaBridge 157:e7ca05fa8600 416 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
AnnaBridge 157:e7ca05fa8600 417 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
AnnaBridge 157:e7ca05fa8600 418
AnnaBridge 157:e7ca05fa8600 419 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 157:e7ca05fa8600 420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 157:e7ca05fa8600 421
AnnaBridge 157:e7ca05fa8600 422 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 157:e7ca05fa8600 423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 157:e7ca05fa8600 424
AnnaBridge 157:e7ca05fa8600 425 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 157:e7ca05fa8600 426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 157:e7ca05fa8600 427
AnnaBridge 157:e7ca05fa8600 428 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 157:e7ca05fa8600 429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 157:e7ca05fa8600 430
AnnaBridge 157:e7ca05fa8600 431 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
AnnaBridge 157:e7ca05fa8600 432 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
AnnaBridge 157:e7ca05fa8600 433
AnnaBridge 157:e7ca05fa8600 434 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 157:e7ca05fa8600 435 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 157:e7ca05fa8600 436
AnnaBridge 157:e7ca05fa8600 437 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 157:e7ca05fa8600 438 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 157:e7ca05fa8600 439
AnnaBridge 157:e7ca05fa8600 440 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 157:e7ca05fa8600 441 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 157:e7ca05fa8600 442
AnnaBridge 157:e7ca05fa8600 443 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 157:e7ca05fa8600 444 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 157:e7ca05fa8600 445
AnnaBridge 157:e7ca05fa8600 446 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 157:e7ca05fa8600 447 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 157:e7ca05fa8600 448
AnnaBridge 157:e7ca05fa8600 449 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 450 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 157:e7ca05fa8600 451 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 157:e7ca05fa8600 452 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 157:e7ca05fa8600 453 #endif
AnnaBridge 157:e7ca05fa8600 454
AnnaBridge 157:e7ca05fa8600 455 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 456 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 157:e7ca05fa8600 457 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 157:e7ca05fa8600 458
AnnaBridge 157:e7ca05fa8600 459 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 157:e7ca05fa8600 460 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 157:e7ca05fa8600 461
AnnaBridge 157:e7ca05fa8600 462 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 157:e7ca05fa8600 463 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 157:e7ca05fa8600 464
AnnaBridge 157:e7ca05fa8600 465 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
AnnaBridge 157:e7ca05fa8600 466 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
AnnaBridge 157:e7ca05fa8600 467
AnnaBridge 157:e7ca05fa8600 468 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
AnnaBridge 157:e7ca05fa8600 469 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
AnnaBridge 157:e7ca05fa8600 470
AnnaBridge 157:e7ca05fa8600 471 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
AnnaBridge 157:e7ca05fa8600 472 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
AnnaBridge 157:e7ca05fa8600 473
AnnaBridge 157:e7ca05fa8600 474 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 157:e7ca05fa8600 475 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 157:e7ca05fa8600 476
AnnaBridge 157:e7ca05fa8600 477 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 157:e7ca05fa8600 478 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 157:e7ca05fa8600 479
AnnaBridge 157:e7ca05fa8600 480 /* SCB System Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 481 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 157:e7ca05fa8600 482 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 157:e7ca05fa8600 483
AnnaBridge 157:e7ca05fa8600 484 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
AnnaBridge 157:e7ca05fa8600 485 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
AnnaBridge 157:e7ca05fa8600 486
AnnaBridge 157:e7ca05fa8600 487 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 157:e7ca05fa8600 488 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 157:e7ca05fa8600 489
AnnaBridge 157:e7ca05fa8600 490 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 157:e7ca05fa8600 491 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 157:e7ca05fa8600 492
AnnaBridge 157:e7ca05fa8600 493 /* SCB Configuration Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 494 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
AnnaBridge 157:e7ca05fa8600 495 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
AnnaBridge 157:e7ca05fa8600 496
AnnaBridge 157:e7ca05fa8600 497 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
AnnaBridge 157:e7ca05fa8600 498 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
AnnaBridge 157:e7ca05fa8600 499
AnnaBridge 157:e7ca05fa8600 500 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
AnnaBridge 157:e7ca05fa8600 501 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
AnnaBridge 157:e7ca05fa8600 502
AnnaBridge 157:e7ca05fa8600 503 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
AnnaBridge 157:e7ca05fa8600 504 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
AnnaBridge 157:e7ca05fa8600 505
AnnaBridge 157:e7ca05fa8600 506 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 157:e7ca05fa8600 507 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 157:e7ca05fa8600 508
AnnaBridge 157:e7ca05fa8600 509 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 157:e7ca05fa8600 510 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 157:e7ca05fa8600 511
AnnaBridge 157:e7ca05fa8600 512 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 157:e7ca05fa8600 513 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 157:e7ca05fa8600 514
AnnaBridge 157:e7ca05fa8600 515 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 157:e7ca05fa8600 516 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 157:e7ca05fa8600 517
AnnaBridge 157:e7ca05fa8600 518 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 157:e7ca05fa8600 519 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
AnnaBridge 157:e7ca05fa8600 520 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
AnnaBridge 157:e7ca05fa8600 521
AnnaBridge 157:e7ca05fa8600 522 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 157:e7ca05fa8600 523 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 157:e7ca05fa8600 524
AnnaBridge 157:e7ca05fa8600 525 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 157:e7ca05fa8600 526 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 157:e7ca05fa8600 527
AnnaBridge 157:e7ca05fa8600 528 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 157:e7ca05fa8600 529 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 157:e7ca05fa8600 530
AnnaBridge 157:e7ca05fa8600 531 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 157:e7ca05fa8600 532 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 157:e7ca05fa8600 533
AnnaBridge 157:e7ca05fa8600 534 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
AnnaBridge 157:e7ca05fa8600 535 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
AnnaBridge 157:e7ca05fa8600 536
AnnaBridge 157:e7ca05fa8600 537 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
AnnaBridge 157:e7ca05fa8600 538 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
AnnaBridge 157:e7ca05fa8600 539
AnnaBridge 157:e7ca05fa8600 540 /*@} end of group CMSIS_SCB */
AnnaBridge 157:e7ca05fa8600 541
AnnaBridge 157:e7ca05fa8600 542
AnnaBridge 157:e7ca05fa8600 543 /**
AnnaBridge 157:e7ca05fa8600 544 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 545 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 157:e7ca05fa8600 546 \brief Type definitions for the System Timer Registers.
AnnaBridge 157:e7ca05fa8600 547 @{
AnnaBridge 157:e7ca05fa8600 548 */
AnnaBridge 157:e7ca05fa8600 549
AnnaBridge 157:e7ca05fa8600 550 /**
AnnaBridge 157:e7ca05fa8600 551 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 157:e7ca05fa8600 552 */
AnnaBridge 157:e7ca05fa8600 553 typedef struct
AnnaBridge 157:e7ca05fa8600 554 {
AnnaBridge 157:e7ca05fa8600 555 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 157:e7ca05fa8600 556 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 157:e7ca05fa8600 557 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 157:e7ca05fa8600 558 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 157:e7ca05fa8600 559 } SysTick_Type;
AnnaBridge 157:e7ca05fa8600 560
AnnaBridge 157:e7ca05fa8600 561 /* SysTick Control / Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 562 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 157:e7ca05fa8600 563 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 157:e7ca05fa8600 564
AnnaBridge 157:e7ca05fa8600 565 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 157:e7ca05fa8600 566 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 157:e7ca05fa8600 567
AnnaBridge 157:e7ca05fa8600 568 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 157:e7ca05fa8600 569 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 157:e7ca05fa8600 570
AnnaBridge 157:e7ca05fa8600 571 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 157:e7ca05fa8600 572 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 157:e7ca05fa8600 573
AnnaBridge 157:e7ca05fa8600 574 /* SysTick Reload Register Definitions */
AnnaBridge 157:e7ca05fa8600 575 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 157:e7ca05fa8600 576 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 157:e7ca05fa8600 577
AnnaBridge 157:e7ca05fa8600 578 /* SysTick Current Register Definitions */
AnnaBridge 157:e7ca05fa8600 579 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 157:e7ca05fa8600 580 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 157:e7ca05fa8600 581
AnnaBridge 157:e7ca05fa8600 582 /* SysTick Calibration Register Definitions */
AnnaBridge 157:e7ca05fa8600 583 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 157:e7ca05fa8600 584 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 157:e7ca05fa8600 585
AnnaBridge 157:e7ca05fa8600 586 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 157:e7ca05fa8600 587 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 157:e7ca05fa8600 588
AnnaBridge 157:e7ca05fa8600 589 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 157:e7ca05fa8600 590 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 157:e7ca05fa8600 591
AnnaBridge 157:e7ca05fa8600 592 /*@} end of group CMSIS_SysTick */
AnnaBridge 157:e7ca05fa8600 593
AnnaBridge 157:e7ca05fa8600 594
AnnaBridge 157:e7ca05fa8600 595 /**
AnnaBridge 157:e7ca05fa8600 596 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 597 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 157:e7ca05fa8600 598 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 157:e7ca05fa8600 599 @{
AnnaBridge 157:e7ca05fa8600 600 */
AnnaBridge 157:e7ca05fa8600 601
AnnaBridge 157:e7ca05fa8600 602 /**
AnnaBridge 157:e7ca05fa8600 603 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 157:e7ca05fa8600 604 */
AnnaBridge 157:e7ca05fa8600 605 typedef struct
AnnaBridge 157:e7ca05fa8600 606 {
AnnaBridge 157:e7ca05fa8600 607 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 157:e7ca05fa8600 608 uint32_t RESERVED0[6U];
AnnaBridge 157:e7ca05fa8600 609 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 157:e7ca05fa8600 610 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 157:e7ca05fa8600 611 uint32_t RESERVED1[1U];
AnnaBridge 157:e7ca05fa8600 612 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 157:e7ca05fa8600 613 uint32_t RESERVED2[1U];
AnnaBridge 157:e7ca05fa8600 614 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 157:e7ca05fa8600 615 uint32_t RESERVED3[1U];
AnnaBridge 157:e7ca05fa8600 616 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 157:e7ca05fa8600 617 uint32_t RESERVED4[1U];
AnnaBridge 157:e7ca05fa8600 618 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 157:e7ca05fa8600 619 uint32_t RESERVED5[1U];
AnnaBridge 157:e7ca05fa8600 620 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 157:e7ca05fa8600 621 uint32_t RESERVED6[1U];
AnnaBridge 157:e7ca05fa8600 622 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 157:e7ca05fa8600 623 uint32_t RESERVED7[1U];
AnnaBridge 157:e7ca05fa8600 624 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 157:e7ca05fa8600 625 uint32_t RESERVED8[1U];
AnnaBridge 157:e7ca05fa8600 626 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
AnnaBridge 157:e7ca05fa8600 627 uint32_t RESERVED9[1U];
AnnaBridge 157:e7ca05fa8600 628 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
AnnaBridge 157:e7ca05fa8600 629 uint32_t RESERVED10[1U];
AnnaBridge 157:e7ca05fa8600 630 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
AnnaBridge 157:e7ca05fa8600 631 uint32_t RESERVED11[1U];
AnnaBridge 157:e7ca05fa8600 632 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
AnnaBridge 157:e7ca05fa8600 633 uint32_t RESERVED12[1U];
AnnaBridge 157:e7ca05fa8600 634 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
AnnaBridge 157:e7ca05fa8600 635 uint32_t RESERVED13[1U];
AnnaBridge 157:e7ca05fa8600 636 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
AnnaBridge 157:e7ca05fa8600 637 uint32_t RESERVED14[1U];
AnnaBridge 157:e7ca05fa8600 638 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
AnnaBridge 157:e7ca05fa8600 639 uint32_t RESERVED15[1U];
AnnaBridge 157:e7ca05fa8600 640 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
AnnaBridge 157:e7ca05fa8600 641 uint32_t RESERVED16[1U];
AnnaBridge 157:e7ca05fa8600 642 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
AnnaBridge 157:e7ca05fa8600 643 uint32_t RESERVED17[1U];
AnnaBridge 157:e7ca05fa8600 644 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
AnnaBridge 157:e7ca05fa8600 645 uint32_t RESERVED18[1U];
AnnaBridge 157:e7ca05fa8600 646 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
AnnaBridge 157:e7ca05fa8600 647 uint32_t RESERVED19[1U];
AnnaBridge 157:e7ca05fa8600 648 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
AnnaBridge 157:e7ca05fa8600 649 uint32_t RESERVED20[1U];
AnnaBridge 157:e7ca05fa8600 650 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
AnnaBridge 157:e7ca05fa8600 651 uint32_t RESERVED21[1U];
AnnaBridge 157:e7ca05fa8600 652 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
AnnaBridge 157:e7ca05fa8600 653 uint32_t RESERVED22[1U];
AnnaBridge 157:e7ca05fa8600 654 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
AnnaBridge 157:e7ca05fa8600 655 uint32_t RESERVED23[1U];
AnnaBridge 157:e7ca05fa8600 656 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
AnnaBridge 157:e7ca05fa8600 657 uint32_t RESERVED24[1U];
AnnaBridge 157:e7ca05fa8600 658 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
AnnaBridge 157:e7ca05fa8600 659 uint32_t RESERVED25[1U];
AnnaBridge 157:e7ca05fa8600 660 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
AnnaBridge 157:e7ca05fa8600 661 uint32_t RESERVED26[1U];
AnnaBridge 157:e7ca05fa8600 662 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
AnnaBridge 157:e7ca05fa8600 663 uint32_t RESERVED27[1U];
AnnaBridge 157:e7ca05fa8600 664 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
AnnaBridge 157:e7ca05fa8600 665 uint32_t RESERVED28[1U];
AnnaBridge 157:e7ca05fa8600 666 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
AnnaBridge 157:e7ca05fa8600 667 uint32_t RESERVED29[1U];
AnnaBridge 157:e7ca05fa8600 668 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
AnnaBridge 157:e7ca05fa8600 669 uint32_t RESERVED30[1U];
AnnaBridge 157:e7ca05fa8600 670 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
AnnaBridge 157:e7ca05fa8600 671 uint32_t RESERVED31[1U];
AnnaBridge 157:e7ca05fa8600 672 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
AnnaBridge 157:e7ca05fa8600 673 } DWT_Type;
AnnaBridge 157:e7ca05fa8600 674
AnnaBridge 157:e7ca05fa8600 675 /* DWT Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 676 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 157:e7ca05fa8600 677 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 157:e7ca05fa8600 678
AnnaBridge 157:e7ca05fa8600 679 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 157:e7ca05fa8600 680 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 157:e7ca05fa8600 681
AnnaBridge 157:e7ca05fa8600 682 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 157:e7ca05fa8600 683 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 157:e7ca05fa8600 684
AnnaBridge 157:e7ca05fa8600 685 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 157:e7ca05fa8600 686 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 157:e7ca05fa8600 687
AnnaBridge 157:e7ca05fa8600 688 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 157:e7ca05fa8600 689 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 157:e7ca05fa8600 690
AnnaBridge 157:e7ca05fa8600 691 /* DWT Comparator Function Register Definitions */
AnnaBridge 157:e7ca05fa8600 692 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
AnnaBridge 157:e7ca05fa8600 693 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
AnnaBridge 157:e7ca05fa8600 694
AnnaBridge 157:e7ca05fa8600 695 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 157:e7ca05fa8600 696 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 157:e7ca05fa8600 697
AnnaBridge 157:e7ca05fa8600 698 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 157:e7ca05fa8600 699 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 157:e7ca05fa8600 700
AnnaBridge 157:e7ca05fa8600 701 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
AnnaBridge 157:e7ca05fa8600 702 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
AnnaBridge 157:e7ca05fa8600 703
AnnaBridge 157:e7ca05fa8600 704 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
AnnaBridge 157:e7ca05fa8600 705 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
AnnaBridge 157:e7ca05fa8600 706
AnnaBridge 157:e7ca05fa8600 707 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 157:e7ca05fa8600 708
AnnaBridge 157:e7ca05fa8600 709
AnnaBridge 157:e7ca05fa8600 710 /**
AnnaBridge 157:e7ca05fa8600 711 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 712 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 157:e7ca05fa8600 713 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 157:e7ca05fa8600 714 @{
AnnaBridge 157:e7ca05fa8600 715 */
AnnaBridge 157:e7ca05fa8600 716
AnnaBridge 157:e7ca05fa8600 717 /**
AnnaBridge 157:e7ca05fa8600 718 \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 157:e7ca05fa8600 719 */
AnnaBridge 157:e7ca05fa8600 720 typedef struct
AnnaBridge 157:e7ca05fa8600 721 {
AnnaBridge 157:e7ca05fa8600 722 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 157:e7ca05fa8600 723 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 157:e7ca05fa8600 724 uint32_t RESERVED0[2U];
AnnaBridge 157:e7ca05fa8600 725 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 157:e7ca05fa8600 726 uint32_t RESERVED1[55U];
AnnaBridge 157:e7ca05fa8600 727 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 157:e7ca05fa8600 728 uint32_t RESERVED2[131U];
AnnaBridge 157:e7ca05fa8600 729 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 157:e7ca05fa8600 730 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 157:e7ca05fa8600 731 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 157:e7ca05fa8600 732 uint32_t RESERVED3[759U];
AnnaBridge 157:e7ca05fa8600 733 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 157:e7ca05fa8600 734 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 157:e7ca05fa8600 735 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 157:e7ca05fa8600 736 uint32_t RESERVED4[1U];
AnnaBridge 157:e7ca05fa8600 737 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 157:e7ca05fa8600 738 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 157:e7ca05fa8600 739 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 157:e7ca05fa8600 740 uint32_t RESERVED5[39U];
AnnaBridge 157:e7ca05fa8600 741 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 157:e7ca05fa8600 742 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 157:e7ca05fa8600 743 uint32_t RESERVED7[8U];
AnnaBridge 157:e7ca05fa8600 744 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 157:e7ca05fa8600 745 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
AnnaBridge 157:e7ca05fa8600 746 } TPI_Type;
AnnaBridge 157:e7ca05fa8600 747
AnnaBridge 157:e7ca05fa8600 748 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 157:e7ca05fa8600 749 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
AnnaBridge 157:e7ca05fa8600 750 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
AnnaBridge 157:e7ca05fa8600 751
AnnaBridge 157:e7ca05fa8600 752 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 157:e7ca05fa8600 753 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
AnnaBridge 157:e7ca05fa8600 754 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 157:e7ca05fa8600 755
AnnaBridge 157:e7ca05fa8600 756 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 757 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 157:e7ca05fa8600 758 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 157:e7ca05fa8600 759
AnnaBridge 157:e7ca05fa8600 760 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
AnnaBridge 157:e7ca05fa8600 761 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 157:e7ca05fa8600 762
AnnaBridge 157:e7ca05fa8600 763 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
AnnaBridge 157:e7ca05fa8600 764 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 157:e7ca05fa8600 765
AnnaBridge 157:e7ca05fa8600 766 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
AnnaBridge 157:e7ca05fa8600 767 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 157:e7ca05fa8600 768
AnnaBridge 157:e7ca05fa8600 769 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 770 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
AnnaBridge 157:e7ca05fa8600 771 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 157:e7ca05fa8600 772
AnnaBridge 157:e7ca05fa8600 773 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
AnnaBridge 157:e7ca05fa8600 774 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 157:e7ca05fa8600 775
AnnaBridge 157:e7ca05fa8600 776 /* TPI TRIGGER Register Definitions */
AnnaBridge 157:e7ca05fa8600 777 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
AnnaBridge 157:e7ca05fa8600 778 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
AnnaBridge 157:e7ca05fa8600 779
AnnaBridge 157:e7ca05fa8600 780 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 157:e7ca05fa8600 781 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
AnnaBridge 157:e7ca05fa8600 782 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
AnnaBridge 157:e7ca05fa8600 783
AnnaBridge 157:e7ca05fa8600 784 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
AnnaBridge 157:e7ca05fa8600 785 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
AnnaBridge 157:e7ca05fa8600 786
AnnaBridge 157:e7ca05fa8600 787 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
AnnaBridge 157:e7ca05fa8600 788 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
AnnaBridge 157:e7ca05fa8600 789
AnnaBridge 157:e7ca05fa8600 790 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
AnnaBridge 157:e7ca05fa8600 791 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
AnnaBridge 157:e7ca05fa8600 792
AnnaBridge 157:e7ca05fa8600 793 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
AnnaBridge 157:e7ca05fa8600 794 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
AnnaBridge 157:e7ca05fa8600 795
AnnaBridge 157:e7ca05fa8600 796 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
AnnaBridge 157:e7ca05fa8600 797 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
AnnaBridge 157:e7ca05fa8600 798
AnnaBridge 157:e7ca05fa8600 799 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
AnnaBridge 157:e7ca05fa8600 800 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
AnnaBridge 157:e7ca05fa8600 801
AnnaBridge 157:e7ca05fa8600 802 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 157:e7ca05fa8600 803 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
AnnaBridge 157:e7ca05fa8600 804 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
AnnaBridge 157:e7ca05fa8600 805
AnnaBridge 157:e7ca05fa8600 806 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 157:e7ca05fa8600 807 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
AnnaBridge 157:e7ca05fa8600 808 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
AnnaBridge 157:e7ca05fa8600 809
AnnaBridge 157:e7ca05fa8600 810 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
AnnaBridge 157:e7ca05fa8600 811 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
AnnaBridge 157:e7ca05fa8600 812
AnnaBridge 157:e7ca05fa8600 813 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
AnnaBridge 157:e7ca05fa8600 814 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
AnnaBridge 157:e7ca05fa8600 815
AnnaBridge 157:e7ca05fa8600 816 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
AnnaBridge 157:e7ca05fa8600 817 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
AnnaBridge 157:e7ca05fa8600 818
AnnaBridge 157:e7ca05fa8600 819 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
AnnaBridge 157:e7ca05fa8600 820 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
AnnaBridge 157:e7ca05fa8600 821
AnnaBridge 157:e7ca05fa8600 822 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
AnnaBridge 157:e7ca05fa8600 823 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
AnnaBridge 157:e7ca05fa8600 824
AnnaBridge 157:e7ca05fa8600 825 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
AnnaBridge 157:e7ca05fa8600 826 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
AnnaBridge 157:e7ca05fa8600 827
AnnaBridge 157:e7ca05fa8600 828 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 157:e7ca05fa8600 829 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
AnnaBridge 157:e7ca05fa8600 830 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
AnnaBridge 157:e7ca05fa8600 831
AnnaBridge 157:e7ca05fa8600 832 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 833 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
AnnaBridge 157:e7ca05fa8600 834 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
AnnaBridge 157:e7ca05fa8600 835
AnnaBridge 157:e7ca05fa8600 836 /* TPI DEVID Register Definitions */
AnnaBridge 157:e7ca05fa8600 837 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 157:e7ca05fa8600 838 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 157:e7ca05fa8600 839
AnnaBridge 157:e7ca05fa8600 840 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 157:e7ca05fa8600 841 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 157:e7ca05fa8600 842
AnnaBridge 157:e7ca05fa8600 843 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 157:e7ca05fa8600 844 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 157:e7ca05fa8600 845
AnnaBridge 157:e7ca05fa8600 846 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
AnnaBridge 157:e7ca05fa8600 847 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
AnnaBridge 157:e7ca05fa8600 848
AnnaBridge 157:e7ca05fa8600 849 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
AnnaBridge 157:e7ca05fa8600 850 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
AnnaBridge 157:e7ca05fa8600 851
AnnaBridge 157:e7ca05fa8600 852 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 157:e7ca05fa8600 853 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
AnnaBridge 157:e7ca05fa8600 854
AnnaBridge 157:e7ca05fa8600 855 /* TPI DEVTYPE Register Definitions */
AnnaBridge 157:e7ca05fa8600 856 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 157:e7ca05fa8600 857 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 157:e7ca05fa8600 858
AnnaBridge 157:e7ca05fa8600 859 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 157:e7ca05fa8600 860 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 157:e7ca05fa8600 861
AnnaBridge 157:e7ca05fa8600 862 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 157:e7ca05fa8600 863
AnnaBridge 157:e7ca05fa8600 864
AnnaBridge 157:e7ca05fa8600 865 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 866 /**
AnnaBridge 157:e7ca05fa8600 867 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 868 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 157:e7ca05fa8600 869 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 157:e7ca05fa8600 870 @{
AnnaBridge 157:e7ca05fa8600 871 */
AnnaBridge 157:e7ca05fa8600 872
AnnaBridge 157:e7ca05fa8600 873 /**
AnnaBridge 157:e7ca05fa8600 874 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 157:e7ca05fa8600 875 */
AnnaBridge 157:e7ca05fa8600 876 typedef struct
AnnaBridge 157:e7ca05fa8600 877 {
AnnaBridge 157:e7ca05fa8600 878 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 157:e7ca05fa8600 879 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 157:e7ca05fa8600 880 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
AnnaBridge 157:e7ca05fa8600 881 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 157:e7ca05fa8600 882 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
AnnaBridge 157:e7ca05fa8600 883 uint32_t RESERVED0[7U];
AnnaBridge 157:e7ca05fa8600 884 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
AnnaBridge 157:e7ca05fa8600 885 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
AnnaBridge 157:e7ca05fa8600 886 } MPU_Type;
AnnaBridge 157:e7ca05fa8600 887
AnnaBridge 157:e7ca05fa8600 888 /* MPU Type Register Definitions */
AnnaBridge 157:e7ca05fa8600 889 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 157:e7ca05fa8600 890 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 157:e7ca05fa8600 891
AnnaBridge 157:e7ca05fa8600 892 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 157:e7ca05fa8600 893 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 157:e7ca05fa8600 894
AnnaBridge 157:e7ca05fa8600 895 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 157:e7ca05fa8600 896 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 157:e7ca05fa8600 897
AnnaBridge 157:e7ca05fa8600 898 /* MPU Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 899 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 157:e7ca05fa8600 900 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 157:e7ca05fa8600 901
AnnaBridge 157:e7ca05fa8600 902 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 157:e7ca05fa8600 903 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 157:e7ca05fa8600 904
AnnaBridge 157:e7ca05fa8600 905 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 157:e7ca05fa8600 906 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 157:e7ca05fa8600 907
AnnaBridge 157:e7ca05fa8600 908 /* MPU Region Number Register Definitions */
AnnaBridge 157:e7ca05fa8600 909 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 157:e7ca05fa8600 910 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 157:e7ca05fa8600 911
AnnaBridge 157:e7ca05fa8600 912 /* MPU Region Base Address Register Definitions */
AnnaBridge 157:e7ca05fa8600 913 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
AnnaBridge 157:e7ca05fa8600 914 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
AnnaBridge 157:e7ca05fa8600 915
AnnaBridge 157:e7ca05fa8600 916 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
AnnaBridge 157:e7ca05fa8600 917 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
AnnaBridge 157:e7ca05fa8600 918
AnnaBridge 157:e7ca05fa8600 919 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
AnnaBridge 157:e7ca05fa8600 920 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
AnnaBridge 157:e7ca05fa8600 921
AnnaBridge 157:e7ca05fa8600 922 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
AnnaBridge 157:e7ca05fa8600 923 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
AnnaBridge 157:e7ca05fa8600 924
AnnaBridge 157:e7ca05fa8600 925 /* MPU Region Limit Address Register Definitions */
AnnaBridge 157:e7ca05fa8600 926 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
AnnaBridge 157:e7ca05fa8600 927 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
AnnaBridge 157:e7ca05fa8600 928
AnnaBridge 157:e7ca05fa8600 929 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
AnnaBridge 157:e7ca05fa8600 930 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
AnnaBridge 157:e7ca05fa8600 931
AnnaBridge 157:e7ca05fa8600 932 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
AnnaBridge 157:e7ca05fa8600 933 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
AnnaBridge 157:e7ca05fa8600 934
AnnaBridge 157:e7ca05fa8600 935 /* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge 157:e7ca05fa8600 936 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
AnnaBridge 157:e7ca05fa8600 937 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
AnnaBridge 157:e7ca05fa8600 938
AnnaBridge 157:e7ca05fa8600 939 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
AnnaBridge 157:e7ca05fa8600 940 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
AnnaBridge 157:e7ca05fa8600 941
AnnaBridge 157:e7ca05fa8600 942 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
AnnaBridge 157:e7ca05fa8600 943 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
AnnaBridge 157:e7ca05fa8600 944
AnnaBridge 157:e7ca05fa8600 945 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
AnnaBridge 157:e7ca05fa8600 946 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
AnnaBridge 157:e7ca05fa8600 947
AnnaBridge 157:e7ca05fa8600 948 /* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge 157:e7ca05fa8600 949 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
AnnaBridge 157:e7ca05fa8600 950 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
AnnaBridge 157:e7ca05fa8600 951
AnnaBridge 157:e7ca05fa8600 952 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
AnnaBridge 157:e7ca05fa8600 953 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
AnnaBridge 157:e7ca05fa8600 954
AnnaBridge 157:e7ca05fa8600 955 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
AnnaBridge 157:e7ca05fa8600 956 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
AnnaBridge 157:e7ca05fa8600 957
AnnaBridge 157:e7ca05fa8600 958 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
AnnaBridge 157:e7ca05fa8600 959 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
AnnaBridge 157:e7ca05fa8600 960
AnnaBridge 157:e7ca05fa8600 961 /*@} end of group CMSIS_MPU */
AnnaBridge 157:e7ca05fa8600 962 #endif
AnnaBridge 157:e7ca05fa8600 963
AnnaBridge 157:e7ca05fa8600 964
AnnaBridge 157:e7ca05fa8600 965 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 157:e7ca05fa8600 966 /**
AnnaBridge 157:e7ca05fa8600 967 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 968 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge 157:e7ca05fa8600 969 \brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge 157:e7ca05fa8600 970 @{
AnnaBridge 157:e7ca05fa8600 971 */
AnnaBridge 157:e7ca05fa8600 972
AnnaBridge 157:e7ca05fa8600 973 /**
AnnaBridge 157:e7ca05fa8600 974 \brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge 157:e7ca05fa8600 975 */
AnnaBridge 157:e7ca05fa8600 976 typedef struct
AnnaBridge 157:e7ca05fa8600 977 {
AnnaBridge 157:e7ca05fa8600 978 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
AnnaBridge 157:e7ca05fa8600 979 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
AnnaBridge 157:e7ca05fa8600 980 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 981 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
AnnaBridge 157:e7ca05fa8600 982 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
AnnaBridge 157:e7ca05fa8600 983 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
AnnaBridge 157:e7ca05fa8600 984 #endif
AnnaBridge 157:e7ca05fa8600 985 } SAU_Type;
AnnaBridge 157:e7ca05fa8600 986
AnnaBridge 157:e7ca05fa8600 987 /* SAU Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 988 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
AnnaBridge 157:e7ca05fa8600 989 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
AnnaBridge 157:e7ca05fa8600 990
AnnaBridge 157:e7ca05fa8600 991 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
AnnaBridge 157:e7ca05fa8600 992 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
AnnaBridge 157:e7ca05fa8600 993
AnnaBridge 157:e7ca05fa8600 994 /* SAU Type Register Definitions */
AnnaBridge 157:e7ca05fa8600 995 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
AnnaBridge 157:e7ca05fa8600 996 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
AnnaBridge 157:e7ca05fa8600 997
AnnaBridge 157:e7ca05fa8600 998 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 999 /* SAU Region Number Register Definitions */
AnnaBridge 157:e7ca05fa8600 1000 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
AnnaBridge 157:e7ca05fa8600 1001 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
AnnaBridge 157:e7ca05fa8600 1002
AnnaBridge 157:e7ca05fa8600 1003 /* SAU Region Base Address Register Definitions */
AnnaBridge 157:e7ca05fa8600 1004 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
AnnaBridge 157:e7ca05fa8600 1005 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
AnnaBridge 157:e7ca05fa8600 1006
AnnaBridge 157:e7ca05fa8600 1007 /* SAU Region Limit Address Register Definitions */
AnnaBridge 157:e7ca05fa8600 1008 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
AnnaBridge 157:e7ca05fa8600 1009 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
AnnaBridge 157:e7ca05fa8600 1010
AnnaBridge 157:e7ca05fa8600 1011 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
AnnaBridge 157:e7ca05fa8600 1012 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
AnnaBridge 157:e7ca05fa8600 1013
AnnaBridge 157:e7ca05fa8600 1014 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
AnnaBridge 157:e7ca05fa8600 1015 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
AnnaBridge 157:e7ca05fa8600 1016
AnnaBridge 157:e7ca05fa8600 1017 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge 157:e7ca05fa8600 1018
AnnaBridge 157:e7ca05fa8600 1019 /*@} end of group CMSIS_SAU */
AnnaBridge 157:e7ca05fa8600 1020 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 157:e7ca05fa8600 1021
AnnaBridge 157:e7ca05fa8600 1022
AnnaBridge 157:e7ca05fa8600 1023 /**
AnnaBridge 157:e7ca05fa8600 1024 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 1025 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 157:e7ca05fa8600 1026 \brief Type definitions for the Core Debug Registers
AnnaBridge 157:e7ca05fa8600 1027 @{
AnnaBridge 157:e7ca05fa8600 1028 */
AnnaBridge 157:e7ca05fa8600 1029
AnnaBridge 157:e7ca05fa8600 1030 /**
AnnaBridge 157:e7ca05fa8600 1031 \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 157:e7ca05fa8600 1032 */
AnnaBridge 157:e7ca05fa8600 1033 typedef struct
AnnaBridge 157:e7ca05fa8600 1034 {
AnnaBridge 157:e7ca05fa8600 1035 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 157:e7ca05fa8600 1036 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 157:e7ca05fa8600 1037 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 157:e7ca05fa8600 1038 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 157:e7ca05fa8600 1039 uint32_t RESERVED4[1U];
AnnaBridge 157:e7ca05fa8600 1040 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
AnnaBridge 157:e7ca05fa8600 1041 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
AnnaBridge 157:e7ca05fa8600 1042 } CoreDebug_Type;
AnnaBridge 157:e7ca05fa8600 1043
AnnaBridge 157:e7ca05fa8600 1044 /* Debug Halting Control and Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 1045 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 157:e7ca05fa8600 1046 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 157:e7ca05fa8600 1047
AnnaBridge 157:e7ca05fa8600 1048 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
AnnaBridge 157:e7ca05fa8600 1049 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
AnnaBridge 157:e7ca05fa8600 1050
AnnaBridge 157:e7ca05fa8600 1051 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 157:e7ca05fa8600 1052 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 157:e7ca05fa8600 1053
AnnaBridge 157:e7ca05fa8600 1054 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 157:e7ca05fa8600 1055 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 157:e7ca05fa8600 1056
AnnaBridge 157:e7ca05fa8600 1057 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 157:e7ca05fa8600 1058 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 157:e7ca05fa8600 1059
AnnaBridge 157:e7ca05fa8600 1060 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 157:e7ca05fa8600 1061 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 157:e7ca05fa8600 1062
AnnaBridge 157:e7ca05fa8600 1063 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 157:e7ca05fa8600 1064 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 157:e7ca05fa8600 1065
AnnaBridge 157:e7ca05fa8600 1066 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 157:e7ca05fa8600 1067 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 157:e7ca05fa8600 1068
AnnaBridge 157:e7ca05fa8600 1069 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 157:e7ca05fa8600 1070 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 157:e7ca05fa8600 1071
AnnaBridge 157:e7ca05fa8600 1072 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 157:e7ca05fa8600 1073 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 157:e7ca05fa8600 1074
AnnaBridge 157:e7ca05fa8600 1075 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 157:e7ca05fa8600 1076 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 157:e7ca05fa8600 1077
AnnaBridge 157:e7ca05fa8600 1078 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 157:e7ca05fa8600 1079 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 157:e7ca05fa8600 1080
AnnaBridge 157:e7ca05fa8600 1081 /* Debug Core Register Selector Register Definitions */
AnnaBridge 157:e7ca05fa8600 1082 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 157:e7ca05fa8600 1083 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 157:e7ca05fa8600 1084
AnnaBridge 157:e7ca05fa8600 1085 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 157:e7ca05fa8600 1086 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 157:e7ca05fa8600 1087
AnnaBridge 157:e7ca05fa8600 1088 /* Debug Exception and Monitor Control Register */
AnnaBridge 157:e7ca05fa8600 1089 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
AnnaBridge 157:e7ca05fa8600 1090 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
AnnaBridge 157:e7ca05fa8600 1091
AnnaBridge 157:e7ca05fa8600 1092 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 157:e7ca05fa8600 1093 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 157:e7ca05fa8600 1094
AnnaBridge 157:e7ca05fa8600 1095 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 157:e7ca05fa8600 1096 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 157:e7ca05fa8600 1097
AnnaBridge 157:e7ca05fa8600 1098 /* Debug Authentication Control Register Definitions */
AnnaBridge 157:e7ca05fa8600 1099 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
AnnaBridge 157:e7ca05fa8600 1100 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
AnnaBridge 157:e7ca05fa8600 1101
AnnaBridge 157:e7ca05fa8600 1102 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
AnnaBridge 157:e7ca05fa8600 1103 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
AnnaBridge 157:e7ca05fa8600 1104
AnnaBridge 157:e7ca05fa8600 1105 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
AnnaBridge 157:e7ca05fa8600 1106 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
AnnaBridge 157:e7ca05fa8600 1107
AnnaBridge 157:e7ca05fa8600 1108 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
AnnaBridge 157:e7ca05fa8600 1109 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
AnnaBridge 157:e7ca05fa8600 1110
AnnaBridge 157:e7ca05fa8600 1111 /* Debug Security Control and Status Register Definitions */
AnnaBridge 157:e7ca05fa8600 1112 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
AnnaBridge 157:e7ca05fa8600 1113 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
AnnaBridge 157:e7ca05fa8600 1114
AnnaBridge 157:e7ca05fa8600 1115 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
AnnaBridge 157:e7ca05fa8600 1116 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
AnnaBridge 157:e7ca05fa8600 1117
AnnaBridge 157:e7ca05fa8600 1118 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
AnnaBridge 157:e7ca05fa8600 1119 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
AnnaBridge 157:e7ca05fa8600 1120
AnnaBridge 157:e7ca05fa8600 1121 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 157:e7ca05fa8600 1122
AnnaBridge 157:e7ca05fa8600 1123
AnnaBridge 157:e7ca05fa8600 1124 /**
AnnaBridge 157:e7ca05fa8600 1125 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 1126 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 157:e7ca05fa8600 1127 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 157:e7ca05fa8600 1128 @{
AnnaBridge 157:e7ca05fa8600 1129 */
AnnaBridge 157:e7ca05fa8600 1130
AnnaBridge 157:e7ca05fa8600 1131 /**
AnnaBridge 157:e7ca05fa8600 1132 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 157:e7ca05fa8600 1133 \param[in] field Name of the register bit field.
AnnaBridge 157:e7ca05fa8600 1134 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 157:e7ca05fa8600 1135 \return Masked and shifted value.
AnnaBridge 157:e7ca05fa8600 1136 */
AnnaBridge 157:e7ca05fa8600 1137 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 157:e7ca05fa8600 1138
AnnaBridge 157:e7ca05fa8600 1139 /**
AnnaBridge 157:e7ca05fa8600 1140 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 157:e7ca05fa8600 1141 \param[in] field Name of the register bit field.
AnnaBridge 157:e7ca05fa8600 1142 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 157:e7ca05fa8600 1143 \return Masked and shifted bit field value.
AnnaBridge 157:e7ca05fa8600 1144 */
AnnaBridge 157:e7ca05fa8600 1145 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 157:e7ca05fa8600 1146
AnnaBridge 157:e7ca05fa8600 1147 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 157:e7ca05fa8600 1148
AnnaBridge 157:e7ca05fa8600 1149
AnnaBridge 157:e7ca05fa8600 1150 /**
AnnaBridge 157:e7ca05fa8600 1151 \ingroup CMSIS_core_register
AnnaBridge 157:e7ca05fa8600 1152 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 157:e7ca05fa8600 1153 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 157:e7ca05fa8600 1154 @{
AnnaBridge 157:e7ca05fa8600 1155 */
AnnaBridge 157:e7ca05fa8600 1156
AnnaBridge 157:e7ca05fa8600 1157 /* Memory mapping of Core Hardware */
AnnaBridge 157:e7ca05fa8600 1158 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 157:e7ca05fa8600 1159 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 157:e7ca05fa8600 1160 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 157:e7ca05fa8600 1161 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 157:e7ca05fa8600 1162 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 157:e7ca05fa8600 1163 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 157:e7ca05fa8600 1164 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 157:e7ca05fa8600 1165
AnnaBridge 157:e7ca05fa8600 1166
AnnaBridge 157:e7ca05fa8600 1167 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 157:e7ca05fa8600 1168 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 157:e7ca05fa8600 1169 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 157:e7ca05fa8600 1170 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 157:e7ca05fa8600 1171 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 157:e7ca05fa8600 1172 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
AnnaBridge 157:e7ca05fa8600 1173
AnnaBridge 157:e7ca05fa8600 1174 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 1175 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 157:e7ca05fa8600 1176 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 157:e7ca05fa8600 1177 #endif
AnnaBridge 157:e7ca05fa8600 1178
AnnaBridge 157:e7ca05fa8600 1179 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 157:e7ca05fa8600 1180 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
AnnaBridge 157:e7ca05fa8600 1181 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
AnnaBridge 157:e7ca05fa8600 1182 #endif
AnnaBridge 157:e7ca05fa8600 1183
AnnaBridge 157:e7ca05fa8600 1184 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 157:e7ca05fa8600 1185 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
AnnaBridge 157:e7ca05fa8600 1186 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
AnnaBridge 157:e7ca05fa8600 1187 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
AnnaBridge 157:e7ca05fa8600 1188 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
AnnaBridge 157:e7ca05fa8600 1189 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
AnnaBridge 157:e7ca05fa8600 1190
AnnaBridge 157:e7ca05fa8600 1191 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
AnnaBridge 157:e7ca05fa8600 1192 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
AnnaBridge 157:e7ca05fa8600 1193 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
AnnaBridge 157:e7ca05fa8600 1194 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
AnnaBridge 157:e7ca05fa8600 1195
AnnaBridge 157:e7ca05fa8600 1196 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 1197 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
AnnaBridge 157:e7ca05fa8600 1198 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
AnnaBridge 157:e7ca05fa8600 1199 #endif
AnnaBridge 157:e7ca05fa8600 1200
AnnaBridge 157:e7ca05fa8600 1201 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 157:e7ca05fa8600 1202 /*@} */
AnnaBridge 157:e7ca05fa8600 1203
AnnaBridge 157:e7ca05fa8600 1204
AnnaBridge 157:e7ca05fa8600 1205
AnnaBridge 157:e7ca05fa8600 1206 /*******************************************************************************
AnnaBridge 157:e7ca05fa8600 1207 * Hardware Abstraction Layer
AnnaBridge 157:e7ca05fa8600 1208 Core Function Interface contains:
AnnaBridge 157:e7ca05fa8600 1209 - Core NVIC Functions
AnnaBridge 157:e7ca05fa8600 1210 - Core SysTick Functions
AnnaBridge 157:e7ca05fa8600 1211 - Core Register Access Functions
AnnaBridge 157:e7ca05fa8600 1212 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 1213 /**
AnnaBridge 157:e7ca05fa8600 1214 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 157:e7ca05fa8600 1215 */
AnnaBridge 157:e7ca05fa8600 1216
AnnaBridge 157:e7ca05fa8600 1217
AnnaBridge 157:e7ca05fa8600 1218
AnnaBridge 157:e7ca05fa8600 1219 /* ########################## NVIC functions #################################### */
AnnaBridge 157:e7ca05fa8600 1220 /**
AnnaBridge 157:e7ca05fa8600 1221 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 1222 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 157:e7ca05fa8600 1223 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 157:e7ca05fa8600 1224 @{
AnnaBridge 157:e7ca05fa8600 1225 */
AnnaBridge 157:e7ca05fa8600 1226
AnnaBridge 157:e7ca05fa8600 1227 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 157:e7ca05fa8600 1228 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 1229 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 157:e7ca05fa8600 1230 #endif
AnnaBridge 157:e7ca05fa8600 1231 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 1232 #else
AnnaBridge 157:e7ca05fa8600 1233 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
AnnaBridge 157:e7ca05fa8600 1234 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
AnnaBridge 157:e7ca05fa8600 1235 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 157:e7ca05fa8600 1236 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 157:e7ca05fa8600 1237 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 157:e7ca05fa8600 1238 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 157:e7ca05fa8600 1239 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 157:e7ca05fa8600 1240 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 157:e7ca05fa8600 1241 #define NVIC_GetActive __NVIC_GetActive
AnnaBridge 157:e7ca05fa8600 1242 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 157:e7ca05fa8600 1243 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 157:e7ca05fa8600 1244 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 157:e7ca05fa8600 1245 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 157:e7ca05fa8600 1246
AnnaBridge 157:e7ca05fa8600 1247 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 157:e7ca05fa8600 1248 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 1249 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 157:e7ca05fa8600 1250 #endif
AnnaBridge 157:e7ca05fa8600 1251 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 157:e7ca05fa8600 1252 #else
AnnaBridge 157:e7ca05fa8600 1253 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 157:e7ca05fa8600 1254 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 157:e7ca05fa8600 1255 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 157:e7ca05fa8600 1256
AnnaBridge 157:e7ca05fa8600 1257 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 157:e7ca05fa8600 1258
AnnaBridge 157:e7ca05fa8600 1259
AnnaBridge 157:e7ca05fa8600 1260 /* Interrupt Priorities are WORD accessible only under ARMv6M */
AnnaBridge 157:e7ca05fa8600 1261 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 157:e7ca05fa8600 1262 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 157:e7ca05fa8600 1263 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 157:e7ca05fa8600 1264 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 157:e7ca05fa8600 1265
AnnaBridge 157:e7ca05fa8600 1266
AnnaBridge 157:e7ca05fa8600 1267 /**
AnnaBridge 157:e7ca05fa8600 1268 \brief Enable Interrupt
AnnaBridge 157:e7ca05fa8600 1269 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 1270 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1271 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1272 */
AnnaBridge 157:e7ca05fa8600 1273 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1274 {
AnnaBridge 157:e7ca05fa8600 1275 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1276 {
AnnaBridge 157:e7ca05fa8600 1277 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 1278 }
AnnaBridge 157:e7ca05fa8600 1279 }
AnnaBridge 157:e7ca05fa8600 1280
AnnaBridge 157:e7ca05fa8600 1281
AnnaBridge 157:e7ca05fa8600 1282 /**
AnnaBridge 157:e7ca05fa8600 1283 \brief Get Interrupt Enable status
AnnaBridge 157:e7ca05fa8600 1284 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 1285 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1286 \return 0 Interrupt is not enabled.
AnnaBridge 157:e7ca05fa8600 1287 \return 1 Interrupt is enabled.
AnnaBridge 157:e7ca05fa8600 1288 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1289 */
AnnaBridge 157:e7ca05fa8600 1290 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1291 {
AnnaBridge 157:e7ca05fa8600 1292 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1293 {
AnnaBridge 157:e7ca05fa8600 1294 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 1295 }
AnnaBridge 157:e7ca05fa8600 1296 else
AnnaBridge 157:e7ca05fa8600 1297 {
AnnaBridge 157:e7ca05fa8600 1298 return(0U);
AnnaBridge 157:e7ca05fa8600 1299 }
AnnaBridge 157:e7ca05fa8600 1300 }
AnnaBridge 157:e7ca05fa8600 1301
AnnaBridge 157:e7ca05fa8600 1302
AnnaBridge 157:e7ca05fa8600 1303 /**
AnnaBridge 157:e7ca05fa8600 1304 \brief Disable Interrupt
AnnaBridge 157:e7ca05fa8600 1305 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 157:e7ca05fa8600 1306 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1307 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1308 */
AnnaBridge 157:e7ca05fa8600 1309 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1310 {
AnnaBridge 157:e7ca05fa8600 1311 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1312 {
AnnaBridge 157:e7ca05fa8600 1313 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 1314 __DSB();
AnnaBridge 157:e7ca05fa8600 1315 __ISB();
AnnaBridge 157:e7ca05fa8600 1316 }
AnnaBridge 157:e7ca05fa8600 1317 }
AnnaBridge 157:e7ca05fa8600 1318
AnnaBridge 157:e7ca05fa8600 1319
AnnaBridge 157:e7ca05fa8600 1320 /**
AnnaBridge 157:e7ca05fa8600 1321 \brief Get Pending Interrupt
AnnaBridge 157:e7ca05fa8600 1322 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 157:e7ca05fa8600 1323 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1324 \return 0 Interrupt status is not pending.
AnnaBridge 157:e7ca05fa8600 1325 \return 1 Interrupt status is pending.
AnnaBridge 157:e7ca05fa8600 1326 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1327 */
AnnaBridge 157:e7ca05fa8600 1328 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1329 {
AnnaBridge 157:e7ca05fa8600 1330 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1331 {
AnnaBridge 157:e7ca05fa8600 1332 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 1333 }
AnnaBridge 157:e7ca05fa8600 1334 else
AnnaBridge 157:e7ca05fa8600 1335 {
AnnaBridge 157:e7ca05fa8600 1336 return(0U);
AnnaBridge 157:e7ca05fa8600 1337 }
AnnaBridge 157:e7ca05fa8600 1338 }
AnnaBridge 157:e7ca05fa8600 1339
AnnaBridge 157:e7ca05fa8600 1340
AnnaBridge 157:e7ca05fa8600 1341 /**
AnnaBridge 157:e7ca05fa8600 1342 \brief Set Pending Interrupt
AnnaBridge 157:e7ca05fa8600 1343 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 157:e7ca05fa8600 1344 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1345 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1346 */
AnnaBridge 157:e7ca05fa8600 1347 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1348 {
AnnaBridge 157:e7ca05fa8600 1349 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1350 {
AnnaBridge 157:e7ca05fa8600 1351 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 1352 }
AnnaBridge 157:e7ca05fa8600 1353 }
AnnaBridge 157:e7ca05fa8600 1354
AnnaBridge 157:e7ca05fa8600 1355
AnnaBridge 157:e7ca05fa8600 1356 /**
AnnaBridge 157:e7ca05fa8600 1357 \brief Clear Pending Interrupt
AnnaBridge 157:e7ca05fa8600 1358 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 157:e7ca05fa8600 1359 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1360 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1361 */
AnnaBridge 157:e7ca05fa8600 1362 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1363 {
AnnaBridge 157:e7ca05fa8600 1364 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1365 {
AnnaBridge 157:e7ca05fa8600 1366 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 1367 }
AnnaBridge 157:e7ca05fa8600 1368 }
AnnaBridge 157:e7ca05fa8600 1369
AnnaBridge 157:e7ca05fa8600 1370
AnnaBridge 157:e7ca05fa8600 1371 /**
AnnaBridge 157:e7ca05fa8600 1372 \brief Get Active Interrupt
AnnaBridge 157:e7ca05fa8600 1373 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge 157:e7ca05fa8600 1374 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1375 \return 0 Interrupt status is not active.
AnnaBridge 157:e7ca05fa8600 1376 \return 1 Interrupt status is active.
AnnaBridge 157:e7ca05fa8600 1377 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1378 */
AnnaBridge 157:e7ca05fa8600 1379 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1380 {
AnnaBridge 157:e7ca05fa8600 1381 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1382 {
AnnaBridge 157:e7ca05fa8600 1383 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 1384 }
AnnaBridge 157:e7ca05fa8600 1385 else
AnnaBridge 157:e7ca05fa8600 1386 {
AnnaBridge 157:e7ca05fa8600 1387 return(0U);
AnnaBridge 157:e7ca05fa8600 1388 }
AnnaBridge 157:e7ca05fa8600 1389 }
AnnaBridge 157:e7ca05fa8600 1390
AnnaBridge 157:e7ca05fa8600 1391
AnnaBridge 157:e7ca05fa8600 1392 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 157:e7ca05fa8600 1393 /**
AnnaBridge 157:e7ca05fa8600 1394 \brief Get Interrupt Target State
AnnaBridge 157:e7ca05fa8600 1395 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 157:e7ca05fa8600 1396 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1397 \return 0 if interrupt is assigned to Secure
AnnaBridge 157:e7ca05fa8600 1398 \return 1 if interrupt is assigned to Non Secure
AnnaBridge 157:e7ca05fa8600 1399 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1400 */
AnnaBridge 157:e7ca05fa8600 1401 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1402 {
AnnaBridge 157:e7ca05fa8600 1403 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1404 {
AnnaBridge 157:e7ca05fa8600 1405 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 1406 }
AnnaBridge 157:e7ca05fa8600 1407 else
AnnaBridge 157:e7ca05fa8600 1408 {
AnnaBridge 157:e7ca05fa8600 1409 return(0U);
AnnaBridge 157:e7ca05fa8600 1410 }
AnnaBridge 157:e7ca05fa8600 1411 }
AnnaBridge 157:e7ca05fa8600 1412
AnnaBridge 157:e7ca05fa8600 1413
AnnaBridge 157:e7ca05fa8600 1414 /**
AnnaBridge 157:e7ca05fa8600 1415 \brief Set Interrupt Target State
AnnaBridge 157:e7ca05fa8600 1416 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 157:e7ca05fa8600 1417 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1418 \return 0 if interrupt is assigned to Secure
AnnaBridge 157:e7ca05fa8600 1419 1 if interrupt is assigned to Non Secure
AnnaBridge 157:e7ca05fa8600 1420 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1421 */
AnnaBridge 157:e7ca05fa8600 1422 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1423 {
AnnaBridge 157:e7ca05fa8600 1424 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1425 {
AnnaBridge 157:e7ca05fa8600 1426 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
AnnaBridge 157:e7ca05fa8600 1427 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 1428 }
AnnaBridge 157:e7ca05fa8600 1429 else
AnnaBridge 157:e7ca05fa8600 1430 {
AnnaBridge 157:e7ca05fa8600 1431 return(0U);
AnnaBridge 157:e7ca05fa8600 1432 }
AnnaBridge 157:e7ca05fa8600 1433 }
AnnaBridge 157:e7ca05fa8600 1434
AnnaBridge 157:e7ca05fa8600 1435
AnnaBridge 157:e7ca05fa8600 1436 /**
AnnaBridge 157:e7ca05fa8600 1437 \brief Clear Interrupt Target State
AnnaBridge 157:e7ca05fa8600 1438 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 157:e7ca05fa8600 1439 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1440 \return 0 if interrupt is assigned to Secure
AnnaBridge 157:e7ca05fa8600 1441 1 if interrupt is assigned to Non Secure
AnnaBridge 157:e7ca05fa8600 1442 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1443 */
AnnaBridge 157:e7ca05fa8600 1444 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1445 {
AnnaBridge 157:e7ca05fa8600 1446 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1447 {
AnnaBridge 157:e7ca05fa8600 1448 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
AnnaBridge 157:e7ca05fa8600 1449 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 1450 }
AnnaBridge 157:e7ca05fa8600 1451 else
AnnaBridge 157:e7ca05fa8600 1452 {
AnnaBridge 157:e7ca05fa8600 1453 return(0U);
AnnaBridge 157:e7ca05fa8600 1454 }
AnnaBridge 157:e7ca05fa8600 1455 }
AnnaBridge 157:e7ca05fa8600 1456 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 157:e7ca05fa8600 1457
AnnaBridge 157:e7ca05fa8600 1458
AnnaBridge 157:e7ca05fa8600 1459 /**
AnnaBridge 157:e7ca05fa8600 1460 \brief Set Interrupt Priority
AnnaBridge 157:e7ca05fa8600 1461 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 157:e7ca05fa8600 1462 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 1463 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 1464 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 1465 \param [in] priority Priority to set.
AnnaBridge 157:e7ca05fa8600 1466 \note The priority cannot be set for every processor exception.
AnnaBridge 157:e7ca05fa8600 1467 */
AnnaBridge 157:e7ca05fa8600 1468 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 157:e7ca05fa8600 1469 {
AnnaBridge 157:e7ca05fa8600 1470 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1471 {
AnnaBridge 157:e7ca05fa8600 1472 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 157:e7ca05fa8600 1473 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 157:e7ca05fa8600 1474 }
AnnaBridge 157:e7ca05fa8600 1475 else
AnnaBridge 157:e7ca05fa8600 1476 {
AnnaBridge 157:e7ca05fa8600 1477 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 157:e7ca05fa8600 1478 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 157:e7ca05fa8600 1479 }
AnnaBridge 157:e7ca05fa8600 1480 }
AnnaBridge 157:e7ca05fa8600 1481
AnnaBridge 157:e7ca05fa8600 1482
AnnaBridge 157:e7ca05fa8600 1483 /**
AnnaBridge 157:e7ca05fa8600 1484 \brief Get Interrupt Priority
AnnaBridge 157:e7ca05fa8600 1485 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 157:e7ca05fa8600 1486 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 1487 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 1488 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 1489 \return Interrupt Priority.
AnnaBridge 157:e7ca05fa8600 1490 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 157:e7ca05fa8600 1491 */
AnnaBridge 157:e7ca05fa8600 1492 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1493 {
AnnaBridge 157:e7ca05fa8600 1494
AnnaBridge 157:e7ca05fa8600 1495 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1496 {
AnnaBridge 157:e7ca05fa8600 1497 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 157:e7ca05fa8600 1498 }
AnnaBridge 157:e7ca05fa8600 1499 else
AnnaBridge 157:e7ca05fa8600 1500 {
AnnaBridge 157:e7ca05fa8600 1501 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 157:e7ca05fa8600 1502 }
AnnaBridge 157:e7ca05fa8600 1503 }
AnnaBridge 157:e7ca05fa8600 1504
AnnaBridge 157:e7ca05fa8600 1505
AnnaBridge 157:e7ca05fa8600 1506 /**
AnnaBridge 157:e7ca05fa8600 1507 \brief Set Interrupt Vector
AnnaBridge 157:e7ca05fa8600 1508 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 157:e7ca05fa8600 1509 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 1510 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 1511 VTOR must been relocated to SRAM before.
AnnaBridge 157:e7ca05fa8600 1512 If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge 157:e7ca05fa8600 1513 \param [in] IRQn Interrupt number
AnnaBridge 157:e7ca05fa8600 1514 \param [in] vector Address of interrupt handler function
AnnaBridge 157:e7ca05fa8600 1515 */
AnnaBridge 157:e7ca05fa8600 1516 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 157:e7ca05fa8600 1517 {
AnnaBridge 157:e7ca05fa8600 1518 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 1519 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 157:e7ca05fa8600 1520 #else
AnnaBridge 157:e7ca05fa8600 1521 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 157:e7ca05fa8600 1522 #endif
AnnaBridge 157:e7ca05fa8600 1523 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 157:e7ca05fa8600 1524 }
AnnaBridge 157:e7ca05fa8600 1525
AnnaBridge 157:e7ca05fa8600 1526
AnnaBridge 157:e7ca05fa8600 1527 /**
AnnaBridge 157:e7ca05fa8600 1528 \brief Get Interrupt Vector
AnnaBridge 157:e7ca05fa8600 1529 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 157:e7ca05fa8600 1530 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 1531 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 1532 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 1533 \return Address of interrupt handler function
AnnaBridge 157:e7ca05fa8600 1534 */
AnnaBridge 157:e7ca05fa8600 1535 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1536 {
AnnaBridge 157:e7ca05fa8600 1537 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 157:e7ca05fa8600 1538 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 157:e7ca05fa8600 1539 #else
AnnaBridge 157:e7ca05fa8600 1540 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 157:e7ca05fa8600 1541 #endif
AnnaBridge 157:e7ca05fa8600 1542 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 157:e7ca05fa8600 1543 }
AnnaBridge 157:e7ca05fa8600 1544
AnnaBridge 157:e7ca05fa8600 1545
AnnaBridge 157:e7ca05fa8600 1546 /**
AnnaBridge 157:e7ca05fa8600 1547 \brief System Reset
AnnaBridge 157:e7ca05fa8600 1548 \details Initiates a system reset request to reset the MCU.
AnnaBridge 157:e7ca05fa8600 1549 */
AnnaBridge 157:e7ca05fa8600 1550 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 157:e7ca05fa8600 1551 {
AnnaBridge 157:e7ca05fa8600 1552 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 157:e7ca05fa8600 1553 buffered write are completed before reset */
AnnaBridge 157:e7ca05fa8600 1554 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 157:e7ca05fa8600 1555 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 157:e7ca05fa8600 1556 __DSB(); /* Ensure completion of memory access */
AnnaBridge 157:e7ca05fa8600 1557
AnnaBridge 157:e7ca05fa8600 1558 for(;;) /* wait until reset */
AnnaBridge 157:e7ca05fa8600 1559 {
AnnaBridge 157:e7ca05fa8600 1560 __NOP();
AnnaBridge 157:e7ca05fa8600 1561 }
AnnaBridge 157:e7ca05fa8600 1562 }
AnnaBridge 157:e7ca05fa8600 1563
AnnaBridge 157:e7ca05fa8600 1564 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 157:e7ca05fa8600 1565 /**
AnnaBridge 157:e7ca05fa8600 1566 \brief Enable Interrupt (non-secure)
AnnaBridge 157:e7ca05fa8600 1567 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 157:e7ca05fa8600 1568 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1569 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1570 */
AnnaBridge 157:e7ca05fa8600 1571 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1572 {
AnnaBridge 157:e7ca05fa8600 1573 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1574 {
AnnaBridge 157:e7ca05fa8600 1575 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 1576 }
AnnaBridge 157:e7ca05fa8600 1577 }
AnnaBridge 157:e7ca05fa8600 1578
AnnaBridge 157:e7ca05fa8600 1579
AnnaBridge 157:e7ca05fa8600 1580 /**
AnnaBridge 157:e7ca05fa8600 1581 \brief Get Interrupt Enable status (non-secure)
AnnaBridge 157:e7ca05fa8600 1582 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 157:e7ca05fa8600 1583 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1584 \return 0 Interrupt is not enabled.
AnnaBridge 157:e7ca05fa8600 1585 \return 1 Interrupt is enabled.
AnnaBridge 157:e7ca05fa8600 1586 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1587 */
AnnaBridge 157:e7ca05fa8600 1588 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1589 {
AnnaBridge 157:e7ca05fa8600 1590 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1591 {
AnnaBridge 157:e7ca05fa8600 1592 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 1593 }
AnnaBridge 157:e7ca05fa8600 1594 else
AnnaBridge 157:e7ca05fa8600 1595 {
AnnaBridge 157:e7ca05fa8600 1596 return(0U);
AnnaBridge 157:e7ca05fa8600 1597 }
AnnaBridge 157:e7ca05fa8600 1598 }
AnnaBridge 157:e7ca05fa8600 1599
AnnaBridge 157:e7ca05fa8600 1600
AnnaBridge 157:e7ca05fa8600 1601 /**
AnnaBridge 157:e7ca05fa8600 1602 \brief Disable Interrupt (non-secure)
AnnaBridge 157:e7ca05fa8600 1603 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 157:e7ca05fa8600 1604 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1605 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1606 */
AnnaBridge 157:e7ca05fa8600 1607 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1608 {
AnnaBridge 157:e7ca05fa8600 1609 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1610 {
AnnaBridge 157:e7ca05fa8600 1611 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 1612 }
AnnaBridge 157:e7ca05fa8600 1613 }
AnnaBridge 157:e7ca05fa8600 1614
AnnaBridge 157:e7ca05fa8600 1615
AnnaBridge 157:e7ca05fa8600 1616 /**
AnnaBridge 157:e7ca05fa8600 1617 \brief Get Pending Interrupt (non-secure)
AnnaBridge 157:e7ca05fa8600 1618 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge 157:e7ca05fa8600 1619 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1620 \return 0 Interrupt status is not pending.
AnnaBridge 157:e7ca05fa8600 1621 \return 1 Interrupt status is pending.
AnnaBridge 157:e7ca05fa8600 1622 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1623 */
AnnaBridge 157:e7ca05fa8600 1624 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1625 {
AnnaBridge 157:e7ca05fa8600 1626 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1627 {
AnnaBridge 157:e7ca05fa8600 1628 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 1629 }
AnnaBridge 157:e7ca05fa8600 1630 }
AnnaBridge 157:e7ca05fa8600 1631
AnnaBridge 157:e7ca05fa8600 1632
AnnaBridge 157:e7ca05fa8600 1633 /**
AnnaBridge 157:e7ca05fa8600 1634 \brief Set Pending Interrupt (non-secure)
AnnaBridge 157:e7ca05fa8600 1635 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge 157:e7ca05fa8600 1636 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1637 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1638 */
AnnaBridge 157:e7ca05fa8600 1639 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1640 {
AnnaBridge 157:e7ca05fa8600 1641 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1642 {
AnnaBridge 157:e7ca05fa8600 1643 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 1644 }
AnnaBridge 157:e7ca05fa8600 1645 }
AnnaBridge 157:e7ca05fa8600 1646
AnnaBridge 157:e7ca05fa8600 1647
AnnaBridge 157:e7ca05fa8600 1648 /**
AnnaBridge 157:e7ca05fa8600 1649 \brief Clear Pending Interrupt (non-secure)
AnnaBridge 157:e7ca05fa8600 1650 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge 157:e7ca05fa8600 1651 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1652 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1653 */
AnnaBridge 157:e7ca05fa8600 1654 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1655 {
AnnaBridge 157:e7ca05fa8600 1656 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1657 {
AnnaBridge 157:e7ca05fa8600 1658 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 157:e7ca05fa8600 1659 }
AnnaBridge 157:e7ca05fa8600 1660 }
AnnaBridge 157:e7ca05fa8600 1661
AnnaBridge 157:e7ca05fa8600 1662
AnnaBridge 157:e7ca05fa8600 1663 /**
AnnaBridge 157:e7ca05fa8600 1664 \brief Get Active Interrupt (non-secure)
AnnaBridge 157:e7ca05fa8600 1665 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge 157:e7ca05fa8600 1666 \param [in] IRQn Device specific interrupt number.
AnnaBridge 157:e7ca05fa8600 1667 \return 0 Interrupt status is not active.
AnnaBridge 157:e7ca05fa8600 1668 \return 1 Interrupt status is active.
AnnaBridge 157:e7ca05fa8600 1669 \note IRQn must not be negative.
AnnaBridge 157:e7ca05fa8600 1670 */
AnnaBridge 157:e7ca05fa8600 1671 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1672 {
AnnaBridge 157:e7ca05fa8600 1673 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1674 {
AnnaBridge 157:e7ca05fa8600 1675 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 157:e7ca05fa8600 1676 }
AnnaBridge 157:e7ca05fa8600 1677 else
AnnaBridge 157:e7ca05fa8600 1678 {
AnnaBridge 157:e7ca05fa8600 1679 return(0U);
AnnaBridge 157:e7ca05fa8600 1680 }
AnnaBridge 157:e7ca05fa8600 1681 }
AnnaBridge 157:e7ca05fa8600 1682
AnnaBridge 157:e7ca05fa8600 1683
AnnaBridge 157:e7ca05fa8600 1684 /**
AnnaBridge 157:e7ca05fa8600 1685 \brief Set Interrupt Priority (non-secure)
AnnaBridge 157:e7ca05fa8600 1686 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge 157:e7ca05fa8600 1687 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 1688 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 1689 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 1690 \param [in] priority Priority to set.
AnnaBridge 157:e7ca05fa8600 1691 \note The priority cannot be set for every non-secure processor exception.
AnnaBridge 157:e7ca05fa8600 1692 */
AnnaBridge 157:e7ca05fa8600 1693 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 157:e7ca05fa8600 1694 {
AnnaBridge 157:e7ca05fa8600 1695 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1696 {
AnnaBridge 157:e7ca05fa8600 1697 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 157:e7ca05fa8600 1698 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 157:e7ca05fa8600 1699 }
AnnaBridge 157:e7ca05fa8600 1700 else
AnnaBridge 157:e7ca05fa8600 1701 {
AnnaBridge 157:e7ca05fa8600 1702 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 157:e7ca05fa8600 1703 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 157:e7ca05fa8600 1704 }
AnnaBridge 157:e7ca05fa8600 1705 }
AnnaBridge 157:e7ca05fa8600 1706
AnnaBridge 157:e7ca05fa8600 1707
AnnaBridge 157:e7ca05fa8600 1708 /**
AnnaBridge 157:e7ca05fa8600 1709 \brief Get Interrupt Priority (non-secure)
AnnaBridge 157:e7ca05fa8600 1710 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge 157:e7ca05fa8600 1711 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 157:e7ca05fa8600 1712 or negative to specify a processor exception.
AnnaBridge 157:e7ca05fa8600 1713 \param [in] IRQn Interrupt number.
AnnaBridge 157:e7ca05fa8600 1714 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 157:e7ca05fa8600 1715 */
AnnaBridge 157:e7ca05fa8600 1716 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge 157:e7ca05fa8600 1717 {
AnnaBridge 157:e7ca05fa8600 1718
AnnaBridge 157:e7ca05fa8600 1719 if ((int32_t)(IRQn) >= 0)
AnnaBridge 157:e7ca05fa8600 1720 {
AnnaBridge 157:e7ca05fa8600 1721 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 157:e7ca05fa8600 1722 }
AnnaBridge 157:e7ca05fa8600 1723 else
AnnaBridge 157:e7ca05fa8600 1724 {
AnnaBridge 157:e7ca05fa8600 1725 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 157:e7ca05fa8600 1726 }
AnnaBridge 157:e7ca05fa8600 1727 }
AnnaBridge 157:e7ca05fa8600 1728 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 157:e7ca05fa8600 1729
AnnaBridge 157:e7ca05fa8600 1730 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 157:e7ca05fa8600 1731
AnnaBridge 157:e7ca05fa8600 1732
AnnaBridge 157:e7ca05fa8600 1733 /* ########################## FPU functions #################################### */
AnnaBridge 157:e7ca05fa8600 1734 /**
AnnaBridge 157:e7ca05fa8600 1735 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 1736 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 157:e7ca05fa8600 1737 \brief Function that provides FPU type.
AnnaBridge 157:e7ca05fa8600 1738 @{
AnnaBridge 157:e7ca05fa8600 1739 */
AnnaBridge 157:e7ca05fa8600 1740
AnnaBridge 157:e7ca05fa8600 1741 /**
AnnaBridge 157:e7ca05fa8600 1742 \brief get FPU type
AnnaBridge 157:e7ca05fa8600 1743 \details returns the FPU type
AnnaBridge 157:e7ca05fa8600 1744 \returns
AnnaBridge 157:e7ca05fa8600 1745 - \b 0: No FPU
AnnaBridge 157:e7ca05fa8600 1746 - \b 1: Single precision FPU
AnnaBridge 157:e7ca05fa8600 1747 - \b 2: Double + Single precision FPU
AnnaBridge 157:e7ca05fa8600 1748 */
AnnaBridge 157:e7ca05fa8600 1749 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 157:e7ca05fa8600 1750 {
AnnaBridge 157:e7ca05fa8600 1751 return 0U; /* No FPU */
AnnaBridge 157:e7ca05fa8600 1752 }
AnnaBridge 157:e7ca05fa8600 1753
AnnaBridge 157:e7ca05fa8600 1754
AnnaBridge 157:e7ca05fa8600 1755 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 157:e7ca05fa8600 1756
AnnaBridge 157:e7ca05fa8600 1757
AnnaBridge 157:e7ca05fa8600 1758
AnnaBridge 157:e7ca05fa8600 1759 /* ########################## SAU functions #################################### */
AnnaBridge 157:e7ca05fa8600 1760 /**
AnnaBridge 157:e7ca05fa8600 1761 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 1762 \defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge 157:e7ca05fa8600 1763 \brief Functions that configure the SAU.
AnnaBridge 157:e7ca05fa8600 1764 @{
AnnaBridge 157:e7ca05fa8600 1765 */
AnnaBridge 157:e7ca05fa8600 1766
AnnaBridge 157:e7ca05fa8600 1767 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 157:e7ca05fa8600 1768
AnnaBridge 157:e7ca05fa8600 1769 /**
AnnaBridge 157:e7ca05fa8600 1770 \brief Enable SAU
AnnaBridge 157:e7ca05fa8600 1771 \details Enables the Security Attribution Unit (SAU).
AnnaBridge 157:e7ca05fa8600 1772 */
AnnaBridge 157:e7ca05fa8600 1773 __STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge 157:e7ca05fa8600 1774 {
AnnaBridge 157:e7ca05fa8600 1775 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
AnnaBridge 157:e7ca05fa8600 1776 }
AnnaBridge 157:e7ca05fa8600 1777
AnnaBridge 157:e7ca05fa8600 1778
AnnaBridge 157:e7ca05fa8600 1779
AnnaBridge 157:e7ca05fa8600 1780 /**
AnnaBridge 157:e7ca05fa8600 1781 \brief Disable SAU
AnnaBridge 157:e7ca05fa8600 1782 \details Disables the Security Attribution Unit (SAU).
AnnaBridge 157:e7ca05fa8600 1783 */
AnnaBridge 157:e7ca05fa8600 1784 __STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge 157:e7ca05fa8600 1785 {
AnnaBridge 157:e7ca05fa8600 1786 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge 157:e7ca05fa8600 1787 }
AnnaBridge 157:e7ca05fa8600 1788
AnnaBridge 157:e7ca05fa8600 1789 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 157:e7ca05fa8600 1790
AnnaBridge 157:e7ca05fa8600 1791 /*@} end of CMSIS_Core_SAUFunctions */
AnnaBridge 157:e7ca05fa8600 1792
AnnaBridge 157:e7ca05fa8600 1793
AnnaBridge 157:e7ca05fa8600 1794
AnnaBridge 157:e7ca05fa8600 1795
AnnaBridge 157:e7ca05fa8600 1796 /* ################################## SysTick function ############################################ */
AnnaBridge 157:e7ca05fa8600 1797 /**
AnnaBridge 157:e7ca05fa8600 1798 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 1799 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 157:e7ca05fa8600 1800 \brief Functions that configure the System.
AnnaBridge 157:e7ca05fa8600 1801 @{
AnnaBridge 157:e7ca05fa8600 1802 */
AnnaBridge 157:e7ca05fa8600 1803
AnnaBridge 157:e7ca05fa8600 1804 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 157:e7ca05fa8600 1805
AnnaBridge 157:e7ca05fa8600 1806 /**
AnnaBridge 157:e7ca05fa8600 1807 \brief System Tick Configuration
AnnaBridge 157:e7ca05fa8600 1808 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 157:e7ca05fa8600 1809 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 157:e7ca05fa8600 1810 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 157:e7ca05fa8600 1811 \return 0 Function succeeded.
AnnaBridge 157:e7ca05fa8600 1812 \return 1 Function failed.
AnnaBridge 157:e7ca05fa8600 1813 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 157:e7ca05fa8600 1814 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 157:e7ca05fa8600 1815 must contain a vendor-specific implementation of this function.
AnnaBridge 157:e7ca05fa8600 1816 */
AnnaBridge 157:e7ca05fa8600 1817 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 157:e7ca05fa8600 1818 {
AnnaBridge 157:e7ca05fa8600 1819 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 157:e7ca05fa8600 1820 {
AnnaBridge 157:e7ca05fa8600 1821 return (1UL); /* Reload value impossible */
AnnaBridge 157:e7ca05fa8600 1822 }
AnnaBridge 157:e7ca05fa8600 1823
AnnaBridge 157:e7ca05fa8600 1824 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 157:e7ca05fa8600 1825 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 157:e7ca05fa8600 1826 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 157:e7ca05fa8600 1827 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 157:e7ca05fa8600 1828 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 157:e7ca05fa8600 1829 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 157:e7ca05fa8600 1830 return (0UL); /* Function successful */
AnnaBridge 157:e7ca05fa8600 1831 }
AnnaBridge 157:e7ca05fa8600 1832
AnnaBridge 157:e7ca05fa8600 1833 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 157:e7ca05fa8600 1834 /**
AnnaBridge 157:e7ca05fa8600 1835 \brief System Tick Configuration (non-secure)
AnnaBridge 157:e7ca05fa8600 1836 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge 157:e7ca05fa8600 1837 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 157:e7ca05fa8600 1838 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 157:e7ca05fa8600 1839 \return 0 Function succeeded.
AnnaBridge 157:e7ca05fa8600 1840 \return 1 Function failed.
AnnaBridge 157:e7ca05fa8600 1841 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 157:e7ca05fa8600 1842 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 157:e7ca05fa8600 1843 must contain a vendor-specific implementation of this function.
AnnaBridge 157:e7ca05fa8600 1844
AnnaBridge 157:e7ca05fa8600 1845 */
AnnaBridge 157:e7ca05fa8600 1846 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge 157:e7ca05fa8600 1847 {
AnnaBridge 157:e7ca05fa8600 1848 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 157:e7ca05fa8600 1849 {
AnnaBridge 157:e7ca05fa8600 1850 return (1UL); /* Reload value impossible */
AnnaBridge 157:e7ca05fa8600 1851 }
AnnaBridge 157:e7ca05fa8600 1852
AnnaBridge 157:e7ca05fa8600 1853 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 157:e7ca05fa8600 1854 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 157:e7ca05fa8600 1855 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 157:e7ca05fa8600 1856 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 157:e7ca05fa8600 1857 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 157:e7ca05fa8600 1858 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 157:e7ca05fa8600 1859 return (0UL); /* Function successful */
AnnaBridge 157:e7ca05fa8600 1860 }
AnnaBridge 157:e7ca05fa8600 1861 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 157:e7ca05fa8600 1862
AnnaBridge 157:e7ca05fa8600 1863 #endif
AnnaBridge 157:e7ca05fa8600 1864
AnnaBridge 157:e7ca05fa8600 1865 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 157:e7ca05fa8600 1866
AnnaBridge 157:e7ca05fa8600 1867
AnnaBridge 157:e7ca05fa8600 1868
AnnaBridge 157:e7ca05fa8600 1869
AnnaBridge 157:e7ca05fa8600 1870 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 1871 }
AnnaBridge 157:e7ca05fa8600 1872 #endif
AnnaBridge 157:e7ca05fa8600 1873
AnnaBridge 157:e7ca05fa8600 1874 #endif /* __CORE_CM23_H_DEPENDANT */
AnnaBridge 157:e7ca05fa8600 1875
AnnaBridge 157:e7ca05fa8600 1876 #endif /* __CMSIS_GENERIC */