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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_LPC1769/cmsis_armclang.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Child:
160:5571c4ff569f
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**************************************************************************//**
AnnaBridge 157:e7ca05fa8600 2 * @file cmsis_armclang.h
AnnaBridge 157:e7ca05fa8600 3 * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
AnnaBridge 157:e7ca05fa8600 4 * @version V5.0.3
AnnaBridge 157:e7ca05fa8600 5 * @date 27. March 2017
AnnaBridge 157:e7ca05fa8600 6 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 7 /*
AnnaBridge 157:e7ca05fa8600 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 157:e7ca05fa8600 9 *
AnnaBridge 157:e7ca05fa8600 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 157:e7ca05fa8600 11 *
AnnaBridge 157:e7ca05fa8600 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 157:e7ca05fa8600 13 * not use this file except in compliance with the License.
AnnaBridge 157:e7ca05fa8600 14 * You may obtain a copy of the License at
AnnaBridge 157:e7ca05fa8600 15 *
AnnaBridge 157:e7ca05fa8600 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 157:e7ca05fa8600 17 *
AnnaBridge 157:e7ca05fa8600 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 157:e7ca05fa8600 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 157:e7ca05fa8600 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 157:e7ca05fa8600 21 * See the License for the specific language governing permissions and
AnnaBridge 157:e7ca05fa8600 22 * limitations under the License.
AnnaBridge 157:e7ca05fa8600 23 */
AnnaBridge 157:e7ca05fa8600 24
AnnaBridge 157:e7ca05fa8600 25 //lint -esym(9058, IRQn) disable MISRA 2012 Rule 2.4 for IRQn
AnnaBridge 157:e7ca05fa8600 26
AnnaBridge 157:e7ca05fa8600 27 #ifndef __CMSIS_ARMCLANG_H
AnnaBridge 157:e7ca05fa8600 28 #define __CMSIS_ARMCLANG_H
AnnaBridge 157:e7ca05fa8600 29
AnnaBridge 157:e7ca05fa8600 30 #ifndef __ARM_COMPAT_H
AnnaBridge 157:e7ca05fa8600 31 #include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
AnnaBridge 157:e7ca05fa8600 32 #endif
AnnaBridge 157:e7ca05fa8600 33
AnnaBridge 157:e7ca05fa8600 34 /* CMSIS compiler specific defines */
AnnaBridge 157:e7ca05fa8600 35 #ifndef __ASM
AnnaBridge 157:e7ca05fa8600 36 #define __ASM __asm
AnnaBridge 157:e7ca05fa8600 37 #endif
AnnaBridge 157:e7ca05fa8600 38 #ifndef __INLINE
AnnaBridge 157:e7ca05fa8600 39 #define __INLINE __inline
AnnaBridge 157:e7ca05fa8600 40 #endif
AnnaBridge 157:e7ca05fa8600 41 #ifndef __STATIC_INLINE
AnnaBridge 157:e7ca05fa8600 42 #define __STATIC_INLINE static __inline
AnnaBridge 157:e7ca05fa8600 43 #endif
AnnaBridge 157:e7ca05fa8600 44 #ifndef __NO_RETURN
AnnaBridge 157:e7ca05fa8600 45 #define __NO_RETURN __attribute__((noreturn))
AnnaBridge 157:e7ca05fa8600 46 #endif
AnnaBridge 157:e7ca05fa8600 47 #ifndef __USED
AnnaBridge 157:e7ca05fa8600 48 #define __USED __attribute__((used))
AnnaBridge 157:e7ca05fa8600 49 #endif
AnnaBridge 157:e7ca05fa8600 50 #ifndef __WEAK
AnnaBridge 157:e7ca05fa8600 51 #define __WEAK __attribute__((weak))
AnnaBridge 157:e7ca05fa8600 52 #endif
AnnaBridge 157:e7ca05fa8600 53 #ifndef __PACKED
AnnaBridge 157:e7ca05fa8600 54 #define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge 157:e7ca05fa8600 55 #endif
AnnaBridge 157:e7ca05fa8600 56 #ifndef __PACKED_STRUCT
AnnaBridge 157:e7ca05fa8600 57 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge 157:e7ca05fa8600 58 #endif
AnnaBridge 157:e7ca05fa8600 59 #ifndef __UNALIGNED_UINT32 /* deprecated */
AnnaBridge 157:e7ca05fa8600 60 #pragma clang diagnostic push
AnnaBridge 157:e7ca05fa8600 61 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 157:e7ca05fa8600 62 //lint -esym(9058, T_UINT32) disable MISRA 2012 Rule 2.4 for T_UINT32
AnnaBridge 157:e7ca05fa8600 63 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
AnnaBridge 157:e7ca05fa8600 64 #pragma clang diagnostic pop
AnnaBridge 157:e7ca05fa8600 65 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
AnnaBridge 157:e7ca05fa8600 66 #endif
AnnaBridge 157:e7ca05fa8600 67 #ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge 157:e7ca05fa8600 68 #pragma clang diagnostic push
AnnaBridge 157:e7ca05fa8600 69 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 157:e7ca05fa8600 70 //lint -esym(9058, T_UINT16_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE
AnnaBridge 157:e7ca05fa8600 71 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge 157:e7ca05fa8600 72 #pragma clang diagnostic pop
AnnaBridge 157:e7ca05fa8600 73 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 157:e7ca05fa8600 74 #endif
AnnaBridge 157:e7ca05fa8600 75 #ifndef __UNALIGNED_UINT16_READ
AnnaBridge 157:e7ca05fa8600 76 #pragma clang diagnostic push
AnnaBridge 157:e7ca05fa8600 77 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 157:e7ca05fa8600 78 //lint -esym(9058, T_UINT16_READ) disable MISRA 2012 Rule 2.4 for T_UINT16_READ
AnnaBridge 157:e7ca05fa8600 79 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge 157:e7ca05fa8600 80 #pragma clang diagnostic pop
AnnaBridge 157:e7ca05fa8600 81 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
AnnaBridge 157:e7ca05fa8600 82 #endif
AnnaBridge 157:e7ca05fa8600 83 #ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge 157:e7ca05fa8600 84 #pragma clang diagnostic push
AnnaBridge 157:e7ca05fa8600 85 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 157:e7ca05fa8600 86 //lint -esym(9058, T_UINT32_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE
AnnaBridge 157:e7ca05fa8600 87 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge 157:e7ca05fa8600 88 #pragma clang diagnostic pop
AnnaBridge 157:e7ca05fa8600 89 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 157:e7ca05fa8600 90 #endif
AnnaBridge 157:e7ca05fa8600 91 #ifndef __UNALIGNED_UINT32_READ
AnnaBridge 157:e7ca05fa8600 92 #pragma clang diagnostic push
AnnaBridge 157:e7ca05fa8600 93 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 157:e7ca05fa8600 94 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge 157:e7ca05fa8600 95 #pragma clang diagnostic pop
AnnaBridge 157:e7ca05fa8600 96 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
AnnaBridge 157:e7ca05fa8600 97 #endif
AnnaBridge 157:e7ca05fa8600 98 #ifndef __ALIGNED
AnnaBridge 157:e7ca05fa8600 99 #define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge 157:e7ca05fa8600 100 #endif
AnnaBridge 157:e7ca05fa8600 101
AnnaBridge 157:e7ca05fa8600 102
AnnaBridge 157:e7ca05fa8600 103 /* ########################### Core Function Access ########################### */
AnnaBridge 157:e7ca05fa8600 104 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 105 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge 157:e7ca05fa8600 106 @{
AnnaBridge 157:e7ca05fa8600 107 */
AnnaBridge 157:e7ca05fa8600 108
AnnaBridge 157:e7ca05fa8600 109 /**
AnnaBridge 157:e7ca05fa8600 110 \brief Enable IRQ Interrupts
AnnaBridge 157:e7ca05fa8600 111 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge 157:e7ca05fa8600 112 Can only be executed in Privileged modes.
AnnaBridge 157:e7ca05fa8600 113 */
AnnaBridge 157:e7ca05fa8600 114 /* intrinsic void __enable_irq(); see arm_compat.h */
AnnaBridge 157:e7ca05fa8600 115
AnnaBridge 157:e7ca05fa8600 116
AnnaBridge 157:e7ca05fa8600 117 /**
AnnaBridge 157:e7ca05fa8600 118 \brief Disable IRQ Interrupts
AnnaBridge 157:e7ca05fa8600 119 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge 157:e7ca05fa8600 120 Can only be executed in Privileged modes.
AnnaBridge 157:e7ca05fa8600 121 */
AnnaBridge 157:e7ca05fa8600 122 /* intrinsic void __disable_irq(); see arm_compat.h */
AnnaBridge 157:e7ca05fa8600 123
AnnaBridge 157:e7ca05fa8600 124
AnnaBridge 157:e7ca05fa8600 125 /**
AnnaBridge 157:e7ca05fa8600 126 \brief Get Control Register
AnnaBridge 157:e7ca05fa8600 127 \details Returns the content of the Control Register.
AnnaBridge 157:e7ca05fa8600 128 \return Control Register value
AnnaBridge 157:e7ca05fa8600 129 */
AnnaBridge 157:e7ca05fa8600 130 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
AnnaBridge 157:e7ca05fa8600 131 {
AnnaBridge 157:e7ca05fa8600 132 uint32_t result;
AnnaBridge 157:e7ca05fa8600 133
AnnaBridge 157:e7ca05fa8600 134 __ASM volatile ("MRS %0, control" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 135 return(result);
AnnaBridge 157:e7ca05fa8600 136 }
AnnaBridge 157:e7ca05fa8600 137
AnnaBridge 157:e7ca05fa8600 138
AnnaBridge 157:e7ca05fa8600 139 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 140 /**
AnnaBridge 157:e7ca05fa8600 141 \brief Get Control Register (non-secure)
AnnaBridge 157:e7ca05fa8600 142 \details Returns the content of the non-secure Control Register when in secure mode.
AnnaBridge 157:e7ca05fa8600 143 \return non-secure Control Register value
AnnaBridge 157:e7ca05fa8600 144 */
AnnaBridge 157:e7ca05fa8600 145 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
AnnaBridge 157:e7ca05fa8600 146 {
AnnaBridge 157:e7ca05fa8600 147 uint32_t result;
AnnaBridge 157:e7ca05fa8600 148
AnnaBridge 157:e7ca05fa8600 149 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 150 return(result);
AnnaBridge 157:e7ca05fa8600 151 }
AnnaBridge 157:e7ca05fa8600 152 #endif
AnnaBridge 157:e7ca05fa8600 153
AnnaBridge 157:e7ca05fa8600 154
AnnaBridge 157:e7ca05fa8600 155 /**
AnnaBridge 157:e7ca05fa8600 156 \brief Set Control Register
AnnaBridge 157:e7ca05fa8600 157 \details Writes the given value to the Control Register.
AnnaBridge 157:e7ca05fa8600 158 \param [in] control Control Register value to set
AnnaBridge 157:e7ca05fa8600 159 */
AnnaBridge 157:e7ca05fa8600 160 __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
AnnaBridge 157:e7ca05fa8600 161 {
AnnaBridge 157:e7ca05fa8600 162 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
AnnaBridge 157:e7ca05fa8600 163 }
AnnaBridge 157:e7ca05fa8600 164
AnnaBridge 157:e7ca05fa8600 165
AnnaBridge 157:e7ca05fa8600 166 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 167 /**
AnnaBridge 157:e7ca05fa8600 168 \brief Set Control Register (non-secure)
AnnaBridge 157:e7ca05fa8600 169 \details Writes the given value to the non-secure Control Register when in secure state.
AnnaBridge 157:e7ca05fa8600 170 \param [in] control Control Register value to set
AnnaBridge 157:e7ca05fa8600 171 */
AnnaBridge 157:e7ca05fa8600 172 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
AnnaBridge 157:e7ca05fa8600 173 {
AnnaBridge 157:e7ca05fa8600 174 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
AnnaBridge 157:e7ca05fa8600 175 }
AnnaBridge 157:e7ca05fa8600 176 #endif
AnnaBridge 157:e7ca05fa8600 177
AnnaBridge 157:e7ca05fa8600 178
AnnaBridge 157:e7ca05fa8600 179 /**
AnnaBridge 157:e7ca05fa8600 180 \brief Get IPSR Register
AnnaBridge 157:e7ca05fa8600 181 \details Returns the content of the IPSR Register.
AnnaBridge 157:e7ca05fa8600 182 \return IPSR Register value
AnnaBridge 157:e7ca05fa8600 183 */
AnnaBridge 157:e7ca05fa8600 184 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
AnnaBridge 157:e7ca05fa8600 185 {
AnnaBridge 157:e7ca05fa8600 186 uint32_t result;
AnnaBridge 157:e7ca05fa8600 187
AnnaBridge 157:e7ca05fa8600 188 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 189 return(result);
AnnaBridge 157:e7ca05fa8600 190 }
AnnaBridge 157:e7ca05fa8600 191
AnnaBridge 157:e7ca05fa8600 192
AnnaBridge 157:e7ca05fa8600 193 /**
AnnaBridge 157:e7ca05fa8600 194 \brief Get APSR Register
AnnaBridge 157:e7ca05fa8600 195 \details Returns the content of the APSR Register.
AnnaBridge 157:e7ca05fa8600 196 \return APSR Register value
AnnaBridge 157:e7ca05fa8600 197 */
AnnaBridge 157:e7ca05fa8600 198 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge 157:e7ca05fa8600 199 {
AnnaBridge 157:e7ca05fa8600 200 uint32_t result;
AnnaBridge 157:e7ca05fa8600 201
AnnaBridge 157:e7ca05fa8600 202 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 203 return(result);
AnnaBridge 157:e7ca05fa8600 204 }
AnnaBridge 157:e7ca05fa8600 205
AnnaBridge 157:e7ca05fa8600 206
AnnaBridge 157:e7ca05fa8600 207 /**
AnnaBridge 157:e7ca05fa8600 208 \brief Get xPSR Register
AnnaBridge 157:e7ca05fa8600 209 \details Returns the content of the xPSR Register.
AnnaBridge 157:e7ca05fa8600 210 \return xPSR Register value
AnnaBridge 157:e7ca05fa8600 211 */
AnnaBridge 157:e7ca05fa8600 212 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
AnnaBridge 157:e7ca05fa8600 213 {
AnnaBridge 157:e7ca05fa8600 214 uint32_t result;
AnnaBridge 157:e7ca05fa8600 215
AnnaBridge 157:e7ca05fa8600 216 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 217 return(result);
AnnaBridge 157:e7ca05fa8600 218 }
AnnaBridge 157:e7ca05fa8600 219
AnnaBridge 157:e7ca05fa8600 220
AnnaBridge 157:e7ca05fa8600 221 /**
AnnaBridge 157:e7ca05fa8600 222 \brief Get Process Stack Pointer
AnnaBridge 157:e7ca05fa8600 223 \details Returns the current value of the Process Stack Pointer (PSP).
AnnaBridge 157:e7ca05fa8600 224 \return PSP Register value
AnnaBridge 157:e7ca05fa8600 225 */
AnnaBridge 157:e7ca05fa8600 226 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
AnnaBridge 157:e7ca05fa8600 227 {
AnnaBridge 157:e7ca05fa8600 228 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 229
AnnaBridge 157:e7ca05fa8600 230 __ASM volatile ("MRS %0, psp" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 231 return(result);
AnnaBridge 157:e7ca05fa8600 232 }
AnnaBridge 157:e7ca05fa8600 233
AnnaBridge 157:e7ca05fa8600 234
AnnaBridge 157:e7ca05fa8600 235 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 236 /**
AnnaBridge 157:e7ca05fa8600 237 \brief Get Process Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 238 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge 157:e7ca05fa8600 239 \return PSP Register value
AnnaBridge 157:e7ca05fa8600 240 */
AnnaBridge 157:e7ca05fa8600 241 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
AnnaBridge 157:e7ca05fa8600 242 {
AnnaBridge 157:e7ca05fa8600 243 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 244
AnnaBridge 157:e7ca05fa8600 245 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 246 return(result);
AnnaBridge 157:e7ca05fa8600 247 }
AnnaBridge 157:e7ca05fa8600 248 #endif
AnnaBridge 157:e7ca05fa8600 249
AnnaBridge 157:e7ca05fa8600 250
AnnaBridge 157:e7ca05fa8600 251 /**
AnnaBridge 157:e7ca05fa8600 252 \brief Set Process Stack Pointer
AnnaBridge 157:e7ca05fa8600 253 \details Assigns the given value to the Process Stack Pointer (PSP).
AnnaBridge 157:e7ca05fa8600 254 \param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge 157:e7ca05fa8600 255 */
AnnaBridge 157:e7ca05fa8600 256 __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 157:e7ca05fa8600 257 {
AnnaBridge 157:e7ca05fa8600 258 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
AnnaBridge 157:e7ca05fa8600 259 }
AnnaBridge 157:e7ca05fa8600 260
AnnaBridge 157:e7ca05fa8600 261
AnnaBridge 157:e7ca05fa8600 262 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 263 /**
AnnaBridge 157:e7ca05fa8600 264 \brief Set Process Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 265 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge 157:e7ca05fa8600 266 \param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge 157:e7ca05fa8600 267 */
AnnaBridge 157:e7ca05fa8600 268 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
AnnaBridge 157:e7ca05fa8600 269 {
AnnaBridge 157:e7ca05fa8600 270 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
AnnaBridge 157:e7ca05fa8600 271 }
AnnaBridge 157:e7ca05fa8600 272 #endif
AnnaBridge 157:e7ca05fa8600 273
AnnaBridge 157:e7ca05fa8600 274
AnnaBridge 157:e7ca05fa8600 275 /**
AnnaBridge 157:e7ca05fa8600 276 \brief Get Main Stack Pointer
AnnaBridge 157:e7ca05fa8600 277 \details Returns the current value of the Main Stack Pointer (MSP).
AnnaBridge 157:e7ca05fa8600 278 \return MSP Register value
AnnaBridge 157:e7ca05fa8600 279 */
AnnaBridge 157:e7ca05fa8600 280 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
AnnaBridge 157:e7ca05fa8600 281 {
AnnaBridge 157:e7ca05fa8600 282 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 283
AnnaBridge 157:e7ca05fa8600 284 __ASM volatile ("MRS %0, msp" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 285 return(result);
AnnaBridge 157:e7ca05fa8600 286 }
AnnaBridge 157:e7ca05fa8600 287
AnnaBridge 157:e7ca05fa8600 288
AnnaBridge 157:e7ca05fa8600 289 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 290 /**
AnnaBridge 157:e7ca05fa8600 291 \brief Get Main Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 292 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge 157:e7ca05fa8600 293 \return MSP Register value
AnnaBridge 157:e7ca05fa8600 294 */
AnnaBridge 157:e7ca05fa8600 295 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
AnnaBridge 157:e7ca05fa8600 296 {
AnnaBridge 157:e7ca05fa8600 297 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 298
AnnaBridge 157:e7ca05fa8600 299 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 300 return(result);
AnnaBridge 157:e7ca05fa8600 301 }
AnnaBridge 157:e7ca05fa8600 302 #endif
AnnaBridge 157:e7ca05fa8600 303
AnnaBridge 157:e7ca05fa8600 304
AnnaBridge 157:e7ca05fa8600 305 /**
AnnaBridge 157:e7ca05fa8600 306 \brief Set Main Stack Pointer
AnnaBridge 157:e7ca05fa8600 307 \details Assigns the given value to the Main Stack Pointer (MSP).
AnnaBridge 157:e7ca05fa8600 308 \param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge 157:e7ca05fa8600 309 */
AnnaBridge 157:e7ca05fa8600 310 __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
AnnaBridge 157:e7ca05fa8600 311 {
AnnaBridge 157:e7ca05fa8600 312 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
AnnaBridge 157:e7ca05fa8600 313 }
AnnaBridge 157:e7ca05fa8600 314
AnnaBridge 157:e7ca05fa8600 315
AnnaBridge 157:e7ca05fa8600 316 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 317 /**
AnnaBridge 157:e7ca05fa8600 318 \brief Set Main Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 319 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge 157:e7ca05fa8600 320 \param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge 157:e7ca05fa8600 321 */
AnnaBridge 157:e7ca05fa8600 322 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
AnnaBridge 157:e7ca05fa8600 323 {
AnnaBridge 157:e7ca05fa8600 324 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
AnnaBridge 157:e7ca05fa8600 325 }
AnnaBridge 157:e7ca05fa8600 326 #endif
AnnaBridge 157:e7ca05fa8600 327
AnnaBridge 157:e7ca05fa8600 328
AnnaBridge 157:e7ca05fa8600 329 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 330 /**
AnnaBridge 157:e7ca05fa8600 331 \brief Get Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 332 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge 157:e7ca05fa8600 333 \return SP Register value
AnnaBridge 157:e7ca05fa8600 334 */
AnnaBridge 157:e7ca05fa8600 335 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
AnnaBridge 157:e7ca05fa8600 336 {
AnnaBridge 157:e7ca05fa8600 337 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 338
AnnaBridge 157:e7ca05fa8600 339 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 340 return(result);
AnnaBridge 157:e7ca05fa8600 341 }
AnnaBridge 157:e7ca05fa8600 342
AnnaBridge 157:e7ca05fa8600 343
AnnaBridge 157:e7ca05fa8600 344 /**
AnnaBridge 157:e7ca05fa8600 345 \brief Set Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 346 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge 157:e7ca05fa8600 347 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 157:e7ca05fa8600 348 */
AnnaBridge 157:e7ca05fa8600 349 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
AnnaBridge 157:e7ca05fa8600 350 {
AnnaBridge 157:e7ca05fa8600 351 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
AnnaBridge 157:e7ca05fa8600 352 }
AnnaBridge 157:e7ca05fa8600 353 #endif
AnnaBridge 157:e7ca05fa8600 354
AnnaBridge 157:e7ca05fa8600 355
AnnaBridge 157:e7ca05fa8600 356 /**
AnnaBridge 157:e7ca05fa8600 357 \brief Get Priority Mask
AnnaBridge 157:e7ca05fa8600 358 \details Returns the current state of the priority mask bit from the Priority Mask Register.
AnnaBridge 157:e7ca05fa8600 359 \return Priority Mask value
AnnaBridge 157:e7ca05fa8600 360 */
AnnaBridge 157:e7ca05fa8600 361 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
AnnaBridge 157:e7ca05fa8600 362 {
AnnaBridge 157:e7ca05fa8600 363 uint32_t result;
AnnaBridge 157:e7ca05fa8600 364
AnnaBridge 157:e7ca05fa8600 365 __ASM volatile ("MRS %0, primask" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 366 return(result);
AnnaBridge 157:e7ca05fa8600 367 }
AnnaBridge 157:e7ca05fa8600 368
AnnaBridge 157:e7ca05fa8600 369
AnnaBridge 157:e7ca05fa8600 370 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 371 /**
AnnaBridge 157:e7ca05fa8600 372 \brief Get Priority Mask (non-secure)
AnnaBridge 157:e7ca05fa8600 373 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
AnnaBridge 157:e7ca05fa8600 374 \return Priority Mask value
AnnaBridge 157:e7ca05fa8600 375 */
AnnaBridge 157:e7ca05fa8600 376 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
AnnaBridge 157:e7ca05fa8600 377 {
AnnaBridge 157:e7ca05fa8600 378 uint32_t result;
AnnaBridge 157:e7ca05fa8600 379
AnnaBridge 157:e7ca05fa8600 380 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 381 return(result);
AnnaBridge 157:e7ca05fa8600 382 }
AnnaBridge 157:e7ca05fa8600 383 #endif
AnnaBridge 157:e7ca05fa8600 384
AnnaBridge 157:e7ca05fa8600 385
AnnaBridge 157:e7ca05fa8600 386 /**
AnnaBridge 157:e7ca05fa8600 387 \brief Set Priority Mask
AnnaBridge 157:e7ca05fa8600 388 \details Assigns the given value to the Priority Mask Register.
AnnaBridge 157:e7ca05fa8600 389 \param [in] priMask Priority Mask
AnnaBridge 157:e7ca05fa8600 390 */
AnnaBridge 157:e7ca05fa8600 391 __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
AnnaBridge 157:e7ca05fa8600 392 {
AnnaBridge 157:e7ca05fa8600 393 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
AnnaBridge 157:e7ca05fa8600 394 }
AnnaBridge 157:e7ca05fa8600 395
AnnaBridge 157:e7ca05fa8600 396
AnnaBridge 157:e7ca05fa8600 397 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 398 /**
AnnaBridge 157:e7ca05fa8600 399 \brief Set Priority Mask (non-secure)
AnnaBridge 157:e7ca05fa8600 400 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
AnnaBridge 157:e7ca05fa8600 401 \param [in] priMask Priority Mask
AnnaBridge 157:e7ca05fa8600 402 */
AnnaBridge 157:e7ca05fa8600 403 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
AnnaBridge 157:e7ca05fa8600 404 {
AnnaBridge 157:e7ca05fa8600 405 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
AnnaBridge 157:e7ca05fa8600 406 }
AnnaBridge 157:e7ca05fa8600 407 #endif
AnnaBridge 157:e7ca05fa8600 408
AnnaBridge 157:e7ca05fa8600 409
AnnaBridge 157:e7ca05fa8600 410 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 411 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 412 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 413 /**
AnnaBridge 157:e7ca05fa8600 414 \brief Enable FIQ
AnnaBridge 157:e7ca05fa8600 415 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 157:e7ca05fa8600 416 Can only be executed in Privileged modes.
AnnaBridge 157:e7ca05fa8600 417 */
AnnaBridge 157:e7ca05fa8600 418 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
AnnaBridge 157:e7ca05fa8600 419
AnnaBridge 157:e7ca05fa8600 420
AnnaBridge 157:e7ca05fa8600 421 /**
AnnaBridge 157:e7ca05fa8600 422 \brief Disable FIQ
AnnaBridge 157:e7ca05fa8600 423 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 157:e7ca05fa8600 424 Can only be executed in Privileged modes.
AnnaBridge 157:e7ca05fa8600 425 */
AnnaBridge 157:e7ca05fa8600 426 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
AnnaBridge 157:e7ca05fa8600 427
AnnaBridge 157:e7ca05fa8600 428
AnnaBridge 157:e7ca05fa8600 429 /**
AnnaBridge 157:e7ca05fa8600 430 \brief Get Base Priority
AnnaBridge 157:e7ca05fa8600 431 \details Returns the current value of the Base Priority register.
AnnaBridge 157:e7ca05fa8600 432 \return Base Priority register value
AnnaBridge 157:e7ca05fa8600 433 */
AnnaBridge 157:e7ca05fa8600 434 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
AnnaBridge 157:e7ca05fa8600 435 {
AnnaBridge 157:e7ca05fa8600 436 uint32_t result;
AnnaBridge 157:e7ca05fa8600 437
AnnaBridge 157:e7ca05fa8600 438 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 439 return(result);
AnnaBridge 157:e7ca05fa8600 440 }
AnnaBridge 157:e7ca05fa8600 441
AnnaBridge 157:e7ca05fa8600 442
AnnaBridge 157:e7ca05fa8600 443 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 444 /**
AnnaBridge 157:e7ca05fa8600 445 \brief Get Base Priority (non-secure)
AnnaBridge 157:e7ca05fa8600 446 \details Returns the current value of the non-secure Base Priority register when in secure state.
AnnaBridge 157:e7ca05fa8600 447 \return Base Priority register value
AnnaBridge 157:e7ca05fa8600 448 */
AnnaBridge 157:e7ca05fa8600 449 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
AnnaBridge 157:e7ca05fa8600 450 {
AnnaBridge 157:e7ca05fa8600 451 uint32_t result;
AnnaBridge 157:e7ca05fa8600 452
AnnaBridge 157:e7ca05fa8600 453 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 454 return(result);
AnnaBridge 157:e7ca05fa8600 455 }
AnnaBridge 157:e7ca05fa8600 456 #endif
AnnaBridge 157:e7ca05fa8600 457
AnnaBridge 157:e7ca05fa8600 458
AnnaBridge 157:e7ca05fa8600 459 /**
AnnaBridge 157:e7ca05fa8600 460 \brief Set Base Priority
AnnaBridge 157:e7ca05fa8600 461 \details Assigns the given value to the Base Priority register.
AnnaBridge 157:e7ca05fa8600 462 \param [in] basePri Base Priority value to set
AnnaBridge 157:e7ca05fa8600 463 */
AnnaBridge 157:e7ca05fa8600 464 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
AnnaBridge 157:e7ca05fa8600 465 {
AnnaBridge 157:e7ca05fa8600 466 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
AnnaBridge 157:e7ca05fa8600 467 }
AnnaBridge 157:e7ca05fa8600 468
AnnaBridge 157:e7ca05fa8600 469
AnnaBridge 157:e7ca05fa8600 470 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 471 /**
AnnaBridge 157:e7ca05fa8600 472 \brief Set Base Priority (non-secure)
AnnaBridge 157:e7ca05fa8600 473 \details Assigns the given value to the non-secure Base Priority register when in secure state.
AnnaBridge 157:e7ca05fa8600 474 \param [in] basePri Base Priority value to set
AnnaBridge 157:e7ca05fa8600 475 */
AnnaBridge 157:e7ca05fa8600 476 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
AnnaBridge 157:e7ca05fa8600 477 {
AnnaBridge 157:e7ca05fa8600 478 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
AnnaBridge 157:e7ca05fa8600 479 }
AnnaBridge 157:e7ca05fa8600 480 #endif
AnnaBridge 157:e7ca05fa8600 481
AnnaBridge 157:e7ca05fa8600 482
AnnaBridge 157:e7ca05fa8600 483 /**
AnnaBridge 157:e7ca05fa8600 484 \brief Set Base Priority with condition
AnnaBridge 157:e7ca05fa8600 485 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
AnnaBridge 157:e7ca05fa8600 486 or the new value increases the BASEPRI priority level.
AnnaBridge 157:e7ca05fa8600 487 \param [in] basePri Base Priority value to set
AnnaBridge 157:e7ca05fa8600 488 */
AnnaBridge 157:e7ca05fa8600 489 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
AnnaBridge 157:e7ca05fa8600 490 {
AnnaBridge 157:e7ca05fa8600 491 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
AnnaBridge 157:e7ca05fa8600 492 }
AnnaBridge 157:e7ca05fa8600 493
AnnaBridge 157:e7ca05fa8600 494
AnnaBridge 157:e7ca05fa8600 495 /**
AnnaBridge 157:e7ca05fa8600 496 \brief Get Fault Mask
AnnaBridge 157:e7ca05fa8600 497 \details Returns the current value of the Fault Mask register.
AnnaBridge 157:e7ca05fa8600 498 \return Fault Mask register value
AnnaBridge 157:e7ca05fa8600 499 */
AnnaBridge 157:e7ca05fa8600 500 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
AnnaBridge 157:e7ca05fa8600 501 {
AnnaBridge 157:e7ca05fa8600 502 uint32_t result;
AnnaBridge 157:e7ca05fa8600 503
AnnaBridge 157:e7ca05fa8600 504 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 505 return(result);
AnnaBridge 157:e7ca05fa8600 506 }
AnnaBridge 157:e7ca05fa8600 507
AnnaBridge 157:e7ca05fa8600 508
AnnaBridge 157:e7ca05fa8600 509 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 510 /**
AnnaBridge 157:e7ca05fa8600 511 \brief Get Fault Mask (non-secure)
AnnaBridge 157:e7ca05fa8600 512 \details Returns the current value of the non-secure Fault Mask register when in secure state.
AnnaBridge 157:e7ca05fa8600 513 \return Fault Mask register value
AnnaBridge 157:e7ca05fa8600 514 */
AnnaBridge 157:e7ca05fa8600 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
AnnaBridge 157:e7ca05fa8600 516 {
AnnaBridge 157:e7ca05fa8600 517 uint32_t result;
AnnaBridge 157:e7ca05fa8600 518
AnnaBridge 157:e7ca05fa8600 519 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 520 return(result);
AnnaBridge 157:e7ca05fa8600 521 }
AnnaBridge 157:e7ca05fa8600 522 #endif
AnnaBridge 157:e7ca05fa8600 523
AnnaBridge 157:e7ca05fa8600 524
AnnaBridge 157:e7ca05fa8600 525 /**
AnnaBridge 157:e7ca05fa8600 526 \brief Set Fault Mask
AnnaBridge 157:e7ca05fa8600 527 \details Assigns the given value to the Fault Mask register.
AnnaBridge 157:e7ca05fa8600 528 \param [in] faultMask Fault Mask value to set
AnnaBridge 157:e7ca05fa8600 529 */
AnnaBridge 157:e7ca05fa8600 530 __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
AnnaBridge 157:e7ca05fa8600 531 {
AnnaBridge 157:e7ca05fa8600 532 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
AnnaBridge 157:e7ca05fa8600 533 }
AnnaBridge 157:e7ca05fa8600 534
AnnaBridge 157:e7ca05fa8600 535
AnnaBridge 157:e7ca05fa8600 536 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 537 /**
AnnaBridge 157:e7ca05fa8600 538 \brief Set Fault Mask (non-secure)
AnnaBridge 157:e7ca05fa8600 539 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
AnnaBridge 157:e7ca05fa8600 540 \param [in] faultMask Fault Mask value to set
AnnaBridge 157:e7ca05fa8600 541 */
AnnaBridge 157:e7ca05fa8600 542 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
AnnaBridge 157:e7ca05fa8600 543 {
AnnaBridge 157:e7ca05fa8600 544 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
AnnaBridge 157:e7ca05fa8600 545 }
AnnaBridge 157:e7ca05fa8600 546 #endif
AnnaBridge 157:e7ca05fa8600 547
AnnaBridge 157:e7ca05fa8600 548 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 549 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 550 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 157:e7ca05fa8600 551
AnnaBridge 157:e7ca05fa8600 552
AnnaBridge 157:e7ca05fa8600 553 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 554 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 157:e7ca05fa8600 555
AnnaBridge 157:e7ca05fa8600 556 /**
AnnaBridge 157:e7ca05fa8600 557 \brief Get Process Stack Pointer Limit
AnnaBridge 157:e7ca05fa8600 558 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
AnnaBridge 157:e7ca05fa8600 559 \return PSPLIM Register value
AnnaBridge 157:e7ca05fa8600 560 */
AnnaBridge 157:e7ca05fa8600 561 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
AnnaBridge 157:e7ca05fa8600 562 {
AnnaBridge 157:e7ca05fa8600 563 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 564
AnnaBridge 157:e7ca05fa8600 565 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 566 return(result);
AnnaBridge 157:e7ca05fa8600 567 }
AnnaBridge 157:e7ca05fa8600 568
AnnaBridge 157:e7ca05fa8600 569
AnnaBridge 157:e7ca05fa8600 570 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 157:e7ca05fa8600 571 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 572 /**
AnnaBridge 157:e7ca05fa8600 573 \brief Get Process Stack Pointer Limit (non-secure)
AnnaBridge 157:e7ca05fa8600 574 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge 157:e7ca05fa8600 575 \return PSPLIM Register value
AnnaBridge 157:e7ca05fa8600 576 */
AnnaBridge 157:e7ca05fa8600 577 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
AnnaBridge 157:e7ca05fa8600 578 {
AnnaBridge 157:e7ca05fa8600 579 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 580
AnnaBridge 157:e7ca05fa8600 581 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 582 return(result);
AnnaBridge 157:e7ca05fa8600 583 }
AnnaBridge 157:e7ca05fa8600 584 #endif
AnnaBridge 157:e7ca05fa8600 585
AnnaBridge 157:e7ca05fa8600 586
AnnaBridge 157:e7ca05fa8600 587 /**
AnnaBridge 157:e7ca05fa8600 588 \brief Set Process Stack Pointer Limit
AnnaBridge 157:e7ca05fa8600 589 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
AnnaBridge 157:e7ca05fa8600 590 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge 157:e7ca05fa8600 591 */
AnnaBridge 157:e7ca05fa8600 592 __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
AnnaBridge 157:e7ca05fa8600 593 {
AnnaBridge 157:e7ca05fa8600 594 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
AnnaBridge 157:e7ca05fa8600 595 }
AnnaBridge 157:e7ca05fa8600 596
AnnaBridge 157:e7ca05fa8600 597
AnnaBridge 157:e7ca05fa8600 598 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 157:e7ca05fa8600 599 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 600 /**
AnnaBridge 157:e7ca05fa8600 601 \brief Set Process Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 602 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge 157:e7ca05fa8600 603 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge 157:e7ca05fa8600 604 */
AnnaBridge 157:e7ca05fa8600 605 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
AnnaBridge 157:e7ca05fa8600 606 {
AnnaBridge 157:e7ca05fa8600 607 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
AnnaBridge 157:e7ca05fa8600 608 }
AnnaBridge 157:e7ca05fa8600 609 #endif
AnnaBridge 157:e7ca05fa8600 610
AnnaBridge 157:e7ca05fa8600 611
AnnaBridge 157:e7ca05fa8600 612 /**
AnnaBridge 157:e7ca05fa8600 613 \brief Get Main Stack Pointer Limit
AnnaBridge 157:e7ca05fa8600 614 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
AnnaBridge 157:e7ca05fa8600 615 \return MSPLIM Register value
AnnaBridge 157:e7ca05fa8600 616 */
AnnaBridge 157:e7ca05fa8600 617 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
AnnaBridge 157:e7ca05fa8600 618 {
AnnaBridge 157:e7ca05fa8600 619 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 620
AnnaBridge 157:e7ca05fa8600 621 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 622
AnnaBridge 157:e7ca05fa8600 623 return(result);
AnnaBridge 157:e7ca05fa8600 624 }
AnnaBridge 157:e7ca05fa8600 625
AnnaBridge 157:e7ca05fa8600 626
AnnaBridge 157:e7ca05fa8600 627 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 157:e7ca05fa8600 628 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 629 /**
AnnaBridge 157:e7ca05fa8600 630 \brief Get Main Stack Pointer Limit (non-secure)
AnnaBridge 157:e7ca05fa8600 631 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
AnnaBridge 157:e7ca05fa8600 632 \return MSPLIM Register value
AnnaBridge 157:e7ca05fa8600 633 */
AnnaBridge 157:e7ca05fa8600 634 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
AnnaBridge 157:e7ca05fa8600 635 {
AnnaBridge 157:e7ca05fa8600 636 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 637
AnnaBridge 157:e7ca05fa8600 638 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 639 return(result);
AnnaBridge 157:e7ca05fa8600 640 }
AnnaBridge 157:e7ca05fa8600 641 #endif
AnnaBridge 157:e7ca05fa8600 642
AnnaBridge 157:e7ca05fa8600 643
AnnaBridge 157:e7ca05fa8600 644 /**
AnnaBridge 157:e7ca05fa8600 645 \brief Set Main Stack Pointer Limit
AnnaBridge 157:e7ca05fa8600 646 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
AnnaBridge 157:e7ca05fa8600 647 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
AnnaBridge 157:e7ca05fa8600 648 */
AnnaBridge 157:e7ca05fa8600 649 __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
AnnaBridge 157:e7ca05fa8600 650 {
AnnaBridge 157:e7ca05fa8600 651 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
AnnaBridge 157:e7ca05fa8600 652 }
AnnaBridge 157:e7ca05fa8600 653
AnnaBridge 157:e7ca05fa8600 654
AnnaBridge 157:e7ca05fa8600 655 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 157:e7ca05fa8600 656 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 657 /**
AnnaBridge 157:e7ca05fa8600 658 \brief Set Main Stack Pointer Limit (non-secure)
AnnaBridge 157:e7ca05fa8600 659 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
AnnaBridge 157:e7ca05fa8600 660 \param [in] MainStackPtrLimit Main Stack Pointer value to set
AnnaBridge 157:e7ca05fa8600 661 */
AnnaBridge 157:e7ca05fa8600 662 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
AnnaBridge 157:e7ca05fa8600 663 {
AnnaBridge 157:e7ca05fa8600 664 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
AnnaBridge 157:e7ca05fa8600 665 }
AnnaBridge 157:e7ca05fa8600 666 #endif
AnnaBridge 157:e7ca05fa8600 667
AnnaBridge 157:e7ca05fa8600 668 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 669 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 157:e7ca05fa8600 670
AnnaBridge 157:e7ca05fa8600 671
AnnaBridge 157:e7ca05fa8600 672 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 673 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 674
AnnaBridge 157:e7ca05fa8600 675 /**
AnnaBridge 157:e7ca05fa8600 676 \brief Get FPSCR
AnnaBridge 157:e7ca05fa8600 677 \details Returns the current value of the Floating Point Status/Control register.
AnnaBridge 157:e7ca05fa8600 678 \return Floating Point Status/Control register value
AnnaBridge 157:e7ca05fa8600 679 */
AnnaBridge 157:e7ca05fa8600 680 /* #define __get_FPSCR __builtin_arm_get_fpscr */
AnnaBridge 157:e7ca05fa8600 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 157:e7ca05fa8600 682 {
AnnaBridge 157:e7ca05fa8600 683 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 157:e7ca05fa8600 684 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 157:e7ca05fa8600 685 uint32_t result;
AnnaBridge 157:e7ca05fa8600 686
AnnaBridge 157:e7ca05fa8600 687 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 688 return(result);
AnnaBridge 157:e7ca05fa8600 689 #else
AnnaBridge 157:e7ca05fa8600 690 return(0U);
AnnaBridge 157:e7ca05fa8600 691 #endif
AnnaBridge 157:e7ca05fa8600 692 }
AnnaBridge 157:e7ca05fa8600 693
AnnaBridge 157:e7ca05fa8600 694
AnnaBridge 157:e7ca05fa8600 695 /**
AnnaBridge 157:e7ca05fa8600 696 \brief Set FPSCR
AnnaBridge 157:e7ca05fa8600 697 \details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge 157:e7ca05fa8600 698 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 157:e7ca05fa8600 699 */
AnnaBridge 157:e7ca05fa8600 700 /* #define __set_FPSCR __builtin_arm_set_fpscr */
AnnaBridge 157:e7ca05fa8600 701 __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 157:e7ca05fa8600 702 {
AnnaBridge 157:e7ca05fa8600 703 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 157:e7ca05fa8600 704 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 157:e7ca05fa8600 705 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
AnnaBridge 157:e7ca05fa8600 706 #else
AnnaBridge 157:e7ca05fa8600 707 (void)fpscr;
AnnaBridge 157:e7ca05fa8600 708 #endif
AnnaBridge 157:e7ca05fa8600 709 }
AnnaBridge 157:e7ca05fa8600 710
AnnaBridge 157:e7ca05fa8600 711 #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 712 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 157:e7ca05fa8600 713
AnnaBridge 157:e7ca05fa8600 714
AnnaBridge 157:e7ca05fa8600 715
AnnaBridge 157:e7ca05fa8600 716 /*@} end of CMSIS_Core_RegAccFunctions */
AnnaBridge 157:e7ca05fa8600 717
AnnaBridge 157:e7ca05fa8600 718
AnnaBridge 157:e7ca05fa8600 719 /* ########################## Core Instruction Access ######################### */
AnnaBridge 157:e7ca05fa8600 720 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
AnnaBridge 157:e7ca05fa8600 721 Access to dedicated instructions
AnnaBridge 157:e7ca05fa8600 722 @{
AnnaBridge 157:e7ca05fa8600 723 */
AnnaBridge 157:e7ca05fa8600 724
AnnaBridge 157:e7ca05fa8600 725 /* Define macros for porting to both thumb1 and thumb2.
AnnaBridge 157:e7ca05fa8600 726 * For thumb1, use low register (r0-r7), specified by constraint "l"
AnnaBridge 157:e7ca05fa8600 727 * Otherwise, use general registers, specified by constraint "r" */
AnnaBridge 157:e7ca05fa8600 728 #if defined (__thumb__) && !defined (__thumb2__)
AnnaBridge 157:e7ca05fa8600 729 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
AnnaBridge 157:e7ca05fa8600 730 #define __CMSIS_GCC_USE_REG(r) "l" (r)
AnnaBridge 157:e7ca05fa8600 731 #else
AnnaBridge 157:e7ca05fa8600 732 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
AnnaBridge 157:e7ca05fa8600 733 #define __CMSIS_GCC_USE_REG(r) "r" (r)
AnnaBridge 157:e7ca05fa8600 734 #endif
AnnaBridge 157:e7ca05fa8600 735
AnnaBridge 157:e7ca05fa8600 736 /**
AnnaBridge 157:e7ca05fa8600 737 \brief No Operation
AnnaBridge 157:e7ca05fa8600 738 \details No Operation does nothing. This instruction can be used for code alignment purposes.
AnnaBridge 157:e7ca05fa8600 739 */
AnnaBridge 157:e7ca05fa8600 740 #define __NOP __builtin_arm_nop
AnnaBridge 157:e7ca05fa8600 741
AnnaBridge 157:e7ca05fa8600 742 /**
AnnaBridge 157:e7ca05fa8600 743 \brief Wait For Interrupt
AnnaBridge 157:e7ca05fa8600 744 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
AnnaBridge 157:e7ca05fa8600 745 */
AnnaBridge 157:e7ca05fa8600 746 #define __WFI __builtin_arm_wfi
AnnaBridge 157:e7ca05fa8600 747
AnnaBridge 157:e7ca05fa8600 748
AnnaBridge 157:e7ca05fa8600 749 /**
AnnaBridge 157:e7ca05fa8600 750 \brief Wait For Event
AnnaBridge 157:e7ca05fa8600 751 \details Wait For Event is a hint instruction that permits the processor to enter
AnnaBridge 157:e7ca05fa8600 752 a low-power state until one of a number of events occurs.
AnnaBridge 157:e7ca05fa8600 753 */
AnnaBridge 157:e7ca05fa8600 754 #define __WFE __builtin_arm_wfe
AnnaBridge 157:e7ca05fa8600 755
AnnaBridge 157:e7ca05fa8600 756
AnnaBridge 157:e7ca05fa8600 757 /**
AnnaBridge 157:e7ca05fa8600 758 \brief Send Event
AnnaBridge 157:e7ca05fa8600 759 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
AnnaBridge 157:e7ca05fa8600 760 */
AnnaBridge 157:e7ca05fa8600 761 #define __SEV __builtin_arm_sev
AnnaBridge 157:e7ca05fa8600 762
AnnaBridge 157:e7ca05fa8600 763
AnnaBridge 157:e7ca05fa8600 764 /**
AnnaBridge 157:e7ca05fa8600 765 \brief Instruction Synchronization Barrier
AnnaBridge 157:e7ca05fa8600 766 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge 157:e7ca05fa8600 767 so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge 157:e7ca05fa8600 768 after the instruction has been completed.
AnnaBridge 157:e7ca05fa8600 769 */
AnnaBridge 157:e7ca05fa8600 770 #define __ISB() __builtin_arm_isb(0xF);
AnnaBridge 157:e7ca05fa8600 771
AnnaBridge 157:e7ca05fa8600 772 /**
AnnaBridge 157:e7ca05fa8600 773 \brief Data Synchronization Barrier
AnnaBridge 157:e7ca05fa8600 774 \details Acts as a special kind of Data Memory Barrier.
AnnaBridge 157:e7ca05fa8600 775 It completes when all explicit memory accesses before this instruction complete.
AnnaBridge 157:e7ca05fa8600 776 */
AnnaBridge 157:e7ca05fa8600 777 #define __DSB() __builtin_arm_dsb(0xF);
AnnaBridge 157:e7ca05fa8600 778
AnnaBridge 157:e7ca05fa8600 779
AnnaBridge 157:e7ca05fa8600 780 /**
AnnaBridge 157:e7ca05fa8600 781 \brief Data Memory Barrier
AnnaBridge 157:e7ca05fa8600 782 \details Ensures the apparent order of the explicit memory operations before
AnnaBridge 157:e7ca05fa8600 783 and after the instruction, without ensuring their completion.
AnnaBridge 157:e7ca05fa8600 784 */
AnnaBridge 157:e7ca05fa8600 785 #define __DMB() __builtin_arm_dmb(0xF);
AnnaBridge 157:e7ca05fa8600 786
AnnaBridge 157:e7ca05fa8600 787
AnnaBridge 157:e7ca05fa8600 788 /**
AnnaBridge 157:e7ca05fa8600 789 \brief Reverse byte order (32 bit)
AnnaBridge 157:e7ca05fa8600 790 \details Reverses the byte order in integer value.
AnnaBridge 157:e7ca05fa8600 791 \param [in] value Value to reverse
AnnaBridge 157:e7ca05fa8600 792 \return Reversed value
AnnaBridge 157:e7ca05fa8600 793 */
AnnaBridge 157:e7ca05fa8600 794 #define __REV __builtin_bswap32
AnnaBridge 157:e7ca05fa8600 795
AnnaBridge 157:e7ca05fa8600 796
AnnaBridge 157:e7ca05fa8600 797 /**
AnnaBridge 157:e7ca05fa8600 798 \brief Reverse byte order (16 bit)
AnnaBridge 157:e7ca05fa8600 799 \details Reverses the byte order in two unsigned short values.
AnnaBridge 157:e7ca05fa8600 800 \param [in] value Value to reverse
AnnaBridge 157:e7ca05fa8600 801 \return Reversed value
AnnaBridge 157:e7ca05fa8600 802 */
AnnaBridge 157:e7ca05fa8600 803 #define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
AnnaBridge 157:e7ca05fa8600 804 #if 0
AnnaBridge 157:e7ca05fa8600 805 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
AnnaBridge 157:e7ca05fa8600 806 {
AnnaBridge 157:e7ca05fa8600 807 uint32_t result;
AnnaBridge 157:e7ca05fa8600 808
AnnaBridge 157:e7ca05fa8600 809 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 157:e7ca05fa8600 810 return(result);
AnnaBridge 157:e7ca05fa8600 811 }
AnnaBridge 157:e7ca05fa8600 812 #endif
AnnaBridge 157:e7ca05fa8600 813
AnnaBridge 157:e7ca05fa8600 814
AnnaBridge 157:e7ca05fa8600 815 /**
AnnaBridge 157:e7ca05fa8600 816 \brief Reverse byte order in signed short value
AnnaBridge 157:e7ca05fa8600 817 \details Reverses the byte order in a signed short value with sign extension to integer.
AnnaBridge 157:e7ca05fa8600 818 \param [in] value Value to reverse
AnnaBridge 157:e7ca05fa8600 819 \return Reversed value
AnnaBridge 157:e7ca05fa8600 820 */
AnnaBridge 157:e7ca05fa8600 821 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
AnnaBridge 157:e7ca05fa8600 822 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
AnnaBridge 157:e7ca05fa8600 823 {
AnnaBridge 157:e7ca05fa8600 824 int32_t result;
AnnaBridge 157:e7ca05fa8600 825
AnnaBridge 157:e7ca05fa8600 826 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 157:e7ca05fa8600 827 return(result);
AnnaBridge 157:e7ca05fa8600 828 }
AnnaBridge 157:e7ca05fa8600 829
AnnaBridge 157:e7ca05fa8600 830
AnnaBridge 157:e7ca05fa8600 831 /**
AnnaBridge 157:e7ca05fa8600 832 \brief Rotate Right in unsigned value (32 bit)
AnnaBridge 157:e7ca05fa8600 833 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge 157:e7ca05fa8600 834 \param [in] op1 Value to rotate
AnnaBridge 157:e7ca05fa8600 835 \param [in] op2 Number of Bits to rotate
AnnaBridge 157:e7ca05fa8600 836 \return Rotated value
AnnaBridge 157:e7ca05fa8600 837 */
AnnaBridge 157:e7ca05fa8600 838 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 839 {
AnnaBridge 157:e7ca05fa8600 840 return (op1 >> op2) | (op1 << (32U - op2));
AnnaBridge 157:e7ca05fa8600 841 }
AnnaBridge 157:e7ca05fa8600 842
AnnaBridge 157:e7ca05fa8600 843
AnnaBridge 157:e7ca05fa8600 844 /**
AnnaBridge 157:e7ca05fa8600 845 \brief Breakpoint
AnnaBridge 157:e7ca05fa8600 846 \details Causes the processor to enter Debug state.
AnnaBridge 157:e7ca05fa8600 847 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
AnnaBridge 157:e7ca05fa8600 848 \param [in] value is ignored by the processor.
AnnaBridge 157:e7ca05fa8600 849 If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge 157:e7ca05fa8600 850 */
AnnaBridge 157:e7ca05fa8600 851 #define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge 157:e7ca05fa8600 852
AnnaBridge 157:e7ca05fa8600 853
AnnaBridge 157:e7ca05fa8600 854 /**
AnnaBridge 157:e7ca05fa8600 855 \brief Reverse bit order of value
AnnaBridge 157:e7ca05fa8600 856 \details Reverses the bit order of the given value.
AnnaBridge 157:e7ca05fa8600 857 \param [in] value Value to reverse
AnnaBridge 157:e7ca05fa8600 858 \return Reversed value
AnnaBridge 157:e7ca05fa8600 859 */
AnnaBridge 157:e7ca05fa8600 860 /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
AnnaBridge 157:e7ca05fa8600 861 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
AnnaBridge 157:e7ca05fa8600 862 {
AnnaBridge 157:e7ca05fa8600 863 uint32_t result;
AnnaBridge 157:e7ca05fa8600 864
AnnaBridge 157:e7ca05fa8600 865 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 866 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 867 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 868 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
AnnaBridge 157:e7ca05fa8600 869 #else
AnnaBridge 157:e7ca05fa8600 870 int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
AnnaBridge 157:e7ca05fa8600 871
AnnaBridge 157:e7ca05fa8600 872 result = value; /* r will be reversed bits of v; first get LSB of v */
AnnaBridge 157:e7ca05fa8600 873 for (value >>= 1U; value; value >>= 1U)
AnnaBridge 157:e7ca05fa8600 874 {
AnnaBridge 157:e7ca05fa8600 875 result <<= 1U;
AnnaBridge 157:e7ca05fa8600 876 result |= value & 1U;
AnnaBridge 157:e7ca05fa8600 877 s--;
AnnaBridge 157:e7ca05fa8600 878 }
AnnaBridge 157:e7ca05fa8600 879 result <<= s; /* shift when v's highest bits are zero */
AnnaBridge 157:e7ca05fa8600 880 #endif
AnnaBridge 157:e7ca05fa8600 881 return(result);
AnnaBridge 157:e7ca05fa8600 882 }
AnnaBridge 157:e7ca05fa8600 883
AnnaBridge 157:e7ca05fa8600 884
AnnaBridge 157:e7ca05fa8600 885 /**
AnnaBridge 157:e7ca05fa8600 886 \brief Count leading zeros
AnnaBridge 157:e7ca05fa8600 887 \details Counts the number of leading zeros of a data value.
AnnaBridge 157:e7ca05fa8600 888 \param [in] value Value to count the leading zeros
AnnaBridge 157:e7ca05fa8600 889 \return number of leading zeros in value
AnnaBridge 157:e7ca05fa8600 890 */
AnnaBridge 157:e7ca05fa8600 891 #define __CLZ __builtin_clz
AnnaBridge 157:e7ca05fa8600 892
AnnaBridge 157:e7ca05fa8600 893
AnnaBridge 157:e7ca05fa8600 894 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 895 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 896 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 897 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 157:e7ca05fa8600 898 /**
AnnaBridge 157:e7ca05fa8600 899 \brief LDR Exclusive (8 bit)
AnnaBridge 157:e7ca05fa8600 900 \details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge 157:e7ca05fa8600 901 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 902 \return value of type uint8_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 903 */
AnnaBridge 157:e7ca05fa8600 904 #define __LDREXB (uint8_t)__builtin_arm_ldrex
AnnaBridge 157:e7ca05fa8600 905
AnnaBridge 157:e7ca05fa8600 906
AnnaBridge 157:e7ca05fa8600 907 /**
AnnaBridge 157:e7ca05fa8600 908 \brief LDR Exclusive (16 bit)
AnnaBridge 157:e7ca05fa8600 909 \details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 910 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 911 \return value of type uint16_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 912 */
AnnaBridge 157:e7ca05fa8600 913 #define __LDREXH (uint16_t)__builtin_arm_ldrex
AnnaBridge 157:e7ca05fa8600 914
AnnaBridge 157:e7ca05fa8600 915
AnnaBridge 157:e7ca05fa8600 916 /**
AnnaBridge 157:e7ca05fa8600 917 \brief LDR Exclusive (32 bit)
AnnaBridge 157:e7ca05fa8600 918 \details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 919 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 920 \return value of type uint32_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 921 */
AnnaBridge 157:e7ca05fa8600 922 #define __LDREXW (uint32_t)__builtin_arm_ldrex
AnnaBridge 157:e7ca05fa8600 923
AnnaBridge 157:e7ca05fa8600 924
AnnaBridge 157:e7ca05fa8600 925 /**
AnnaBridge 157:e7ca05fa8600 926 \brief STR Exclusive (8 bit)
AnnaBridge 157:e7ca05fa8600 927 \details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge 157:e7ca05fa8600 928 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 929 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 930 \return 0 Function succeeded
AnnaBridge 157:e7ca05fa8600 931 \return 1 Function failed
AnnaBridge 157:e7ca05fa8600 932 */
AnnaBridge 157:e7ca05fa8600 933 #define __STREXB (uint32_t)__builtin_arm_strex
AnnaBridge 157:e7ca05fa8600 934
AnnaBridge 157:e7ca05fa8600 935
AnnaBridge 157:e7ca05fa8600 936 /**
AnnaBridge 157:e7ca05fa8600 937 \brief STR Exclusive (16 bit)
AnnaBridge 157:e7ca05fa8600 938 \details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 939 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 940 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 941 \return 0 Function succeeded
AnnaBridge 157:e7ca05fa8600 942 \return 1 Function failed
AnnaBridge 157:e7ca05fa8600 943 */
AnnaBridge 157:e7ca05fa8600 944 #define __STREXH (uint32_t)__builtin_arm_strex
AnnaBridge 157:e7ca05fa8600 945
AnnaBridge 157:e7ca05fa8600 946
AnnaBridge 157:e7ca05fa8600 947 /**
AnnaBridge 157:e7ca05fa8600 948 \brief STR Exclusive (32 bit)
AnnaBridge 157:e7ca05fa8600 949 \details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 950 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 951 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 952 \return 0 Function succeeded
AnnaBridge 157:e7ca05fa8600 953 \return 1 Function failed
AnnaBridge 157:e7ca05fa8600 954 */
AnnaBridge 157:e7ca05fa8600 955 #define __STREXW (uint32_t)__builtin_arm_strex
AnnaBridge 157:e7ca05fa8600 956
AnnaBridge 157:e7ca05fa8600 957
AnnaBridge 157:e7ca05fa8600 958 /**
AnnaBridge 157:e7ca05fa8600 959 \brief Remove the exclusive lock
AnnaBridge 157:e7ca05fa8600 960 \details Removes the exclusive lock which is created by LDREX.
AnnaBridge 157:e7ca05fa8600 961 */
AnnaBridge 157:e7ca05fa8600 962 #define __CLREX __builtin_arm_clrex
AnnaBridge 157:e7ca05fa8600 963
AnnaBridge 157:e7ca05fa8600 964 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 965 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 966 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 967 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 157:e7ca05fa8600 968
AnnaBridge 157:e7ca05fa8600 969
AnnaBridge 157:e7ca05fa8600 970 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 971 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 972 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 973 /**
AnnaBridge 157:e7ca05fa8600 974 \brief Signed Saturate
AnnaBridge 157:e7ca05fa8600 975 \details Saturates a signed value.
AnnaBridge 157:e7ca05fa8600 976 \param [in] value Value to be saturated
AnnaBridge 157:e7ca05fa8600 977 \param [in] sat Bit position to saturate to (1..32)
AnnaBridge 157:e7ca05fa8600 978 \return Saturated value
AnnaBridge 157:e7ca05fa8600 979 */
AnnaBridge 157:e7ca05fa8600 980 #define __SSAT __builtin_arm_ssat
AnnaBridge 157:e7ca05fa8600 981
AnnaBridge 157:e7ca05fa8600 982
AnnaBridge 157:e7ca05fa8600 983 /**
AnnaBridge 157:e7ca05fa8600 984 \brief Unsigned Saturate
AnnaBridge 157:e7ca05fa8600 985 \details Saturates an unsigned value.
AnnaBridge 157:e7ca05fa8600 986 \param [in] value Value to be saturated
AnnaBridge 157:e7ca05fa8600 987 \param [in] sat Bit position to saturate to (0..31)
AnnaBridge 157:e7ca05fa8600 988 \return Saturated value
AnnaBridge 157:e7ca05fa8600 989 */
AnnaBridge 157:e7ca05fa8600 990 #define __USAT __builtin_arm_usat
AnnaBridge 157:e7ca05fa8600 991
AnnaBridge 157:e7ca05fa8600 992
AnnaBridge 157:e7ca05fa8600 993 /**
AnnaBridge 157:e7ca05fa8600 994 \brief Rotate Right with Extend (32 bit)
AnnaBridge 157:e7ca05fa8600 995 \details Moves each bit of a bitstring right by one bit.
AnnaBridge 157:e7ca05fa8600 996 The carry input is shifted in at the left end of the bitstring.
AnnaBridge 157:e7ca05fa8600 997 \param [in] value Value to rotate
AnnaBridge 157:e7ca05fa8600 998 \return Rotated value
AnnaBridge 157:e7ca05fa8600 999 */
AnnaBridge 157:e7ca05fa8600 1000 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
AnnaBridge 157:e7ca05fa8600 1001 {
AnnaBridge 157:e7ca05fa8600 1002 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1003
AnnaBridge 157:e7ca05fa8600 1004 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 157:e7ca05fa8600 1005 return(result);
AnnaBridge 157:e7ca05fa8600 1006 }
AnnaBridge 157:e7ca05fa8600 1007
AnnaBridge 157:e7ca05fa8600 1008
AnnaBridge 157:e7ca05fa8600 1009 /**
AnnaBridge 157:e7ca05fa8600 1010 \brief LDRT Unprivileged (8 bit)
AnnaBridge 157:e7ca05fa8600 1011 \details Executes a Unprivileged LDRT instruction for 8 bit value.
AnnaBridge 157:e7ca05fa8600 1012 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1013 \return value of type uint8_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1014 */
AnnaBridge 157:e7ca05fa8600 1015 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
AnnaBridge 157:e7ca05fa8600 1016 {
AnnaBridge 157:e7ca05fa8600 1017 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1018
AnnaBridge 157:e7ca05fa8600 1019 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1020 return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge 157:e7ca05fa8600 1021 }
AnnaBridge 157:e7ca05fa8600 1022
AnnaBridge 157:e7ca05fa8600 1023
AnnaBridge 157:e7ca05fa8600 1024 /**
AnnaBridge 157:e7ca05fa8600 1025 \brief LDRT Unprivileged (16 bit)
AnnaBridge 157:e7ca05fa8600 1026 \details Executes a Unprivileged LDRT instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1027 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1028 \return value of type uint16_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1029 */
AnnaBridge 157:e7ca05fa8600 1030 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
AnnaBridge 157:e7ca05fa8600 1031 {
AnnaBridge 157:e7ca05fa8600 1032 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1033
AnnaBridge 157:e7ca05fa8600 1034 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1035 return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge 157:e7ca05fa8600 1036 }
AnnaBridge 157:e7ca05fa8600 1037
AnnaBridge 157:e7ca05fa8600 1038
AnnaBridge 157:e7ca05fa8600 1039 /**
AnnaBridge 157:e7ca05fa8600 1040 \brief LDRT Unprivileged (32 bit)
AnnaBridge 157:e7ca05fa8600 1041 \details Executes a Unprivileged LDRT instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1042 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1043 \return value of type uint32_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1044 */
AnnaBridge 157:e7ca05fa8600 1045 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
AnnaBridge 157:e7ca05fa8600 1046 {
AnnaBridge 157:e7ca05fa8600 1047 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1048
AnnaBridge 157:e7ca05fa8600 1049 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1050 return(result);
AnnaBridge 157:e7ca05fa8600 1051 }
AnnaBridge 157:e7ca05fa8600 1052
AnnaBridge 157:e7ca05fa8600 1053
AnnaBridge 157:e7ca05fa8600 1054 /**
AnnaBridge 157:e7ca05fa8600 1055 \brief STRT Unprivileged (8 bit)
AnnaBridge 157:e7ca05fa8600 1056 \details Executes a Unprivileged STRT instruction for 8 bit values.
AnnaBridge 157:e7ca05fa8600 1057 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1058 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1059 */
AnnaBridge 157:e7ca05fa8600 1060 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
AnnaBridge 157:e7ca05fa8600 1061 {
AnnaBridge 157:e7ca05fa8600 1062 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1063 }
AnnaBridge 157:e7ca05fa8600 1064
AnnaBridge 157:e7ca05fa8600 1065
AnnaBridge 157:e7ca05fa8600 1066 /**
AnnaBridge 157:e7ca05fa8600 1067 \brief STRT Unprivileged (16 bit)
AnnaBridge 157:e7ca05fa8600 1068 \details Executes a Unprivileged STRT instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1069 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1070 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1071 */
AnnaBridge 157:e7ca05fa8600 1072 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
AnnaBridge 157:e7ca05fa8600 1073 {
AnnaBridge 157:e7ca05fa8600 1074 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1075 }
AnnaBridge 157:e7ca05fa8600 1076
AnnaBridge 157:e7ca05fa8600 1077
AnnaBridge 157:e7ca05fa8600 1078 /**
AnnaBridge 157:e7ca05fa8600 1079 \brief STRT Unprivileged (32 bit)
AnnaBridge 157:e7ca05fa8600 1080 \details Executes a Unprivileged STRT instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1081 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1082 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1083 */
AnnaBridge 157:e7ca05fa8600 1084 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
AnnaBridge 157:e7ca05fa8600 1085 {
AnnaBridge 157:e7ca05fa8600 1086 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
AnnaBridge 157:e7ca05fa8600 1087 }
AnnaBridge 157:e7ca05fa8600 1088
AnnaBridge 157:e7ca05fa8600 1089 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1090 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1091 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 157:e7ca05fa8600 1092
AnnaBridge 157:e7ca05fa8600 1093
AnnaBridge 157:e7ca05fa8600 1094 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1095 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 157:e7ca05fa8600 1096 /**
AnnaBridge 157:e7ca05fa8600 1097 \brief Load-Acquire (8 bit)
AnnaBridge 157:e7ca05fa8600 1098 \details Executes a LDAB instruction for 8 bit value.
AnnaBridge 157:e7ca05fa8600 1099 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1100 \return value of type uint8_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1101 */
AnnaBridge 157:e7ca05fa8600 1102 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
AnnaBridge 157:e7ca05fa8600 1103 {
AnnaBridge 157:e7ca05fa8600 1104 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1105
AnnaBridge 157:e7ca05fa8600 1106 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1107 return ((uint8_t) result);
AnnaBridge 157:e7ca05fa8600 1108 }
AnnaBridge 157:e7ca05fa8600 1109
AnnaBridge 157:e7ca05fa8600 1110
AnnaBridge 157:e7ca05fa8600 1111 /**
AnnaBridge 157:e7ca05fa8600 1112 \brief Load-Acquire (16 bit)
AnnaBridge 157:e7ca05fa8600 1113 \details Executes a LDAH instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1114 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1115 \return value of type uint16_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1116 */
AnnaBridge 157:e7ca05fa8600 1117 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
AnnaBridge 157:e7ca05fa8600 1118 {
AnnaBridge 157:e7ca05fa8600 1119 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1120
AnnaBridge 157:e7ca05fa8600 1121 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1122 return ((uint16_t) result);
AnnaBridge 157:e7ca05fa8600 1123 }
AnnaBridge 157:e7ca05fa8600 1124
AnnaBridge 157:e7ca05fa8600 1125
AnnaBridge 157:e7ca05fa8600 1126 /**
AnnaBridge 157:e7ca05fa8600 1127 \brief Load-Acquire (32 bit)
AnnaBridge 157:e7ca05fa8600 1128 \details Executes a LDA instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1129 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1130 \return value of type uint32_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1131 */
AnnaBridge 157:e7ca05fa8600 1132 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
AnnaBridge 157:e7ca05fa8600 1133 {
AnnaBridge 157:e7ca05fa8600 1134 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1135
AnnaBridge 157:e7ca05fa8600 1136 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1137 return(result);
AnnaBridge 157:e7ca05fa8600 1138 }
AnnaBridge 157:e7ca05fa8600 1139
AnnaBridge 157:e7ca05fa8600 1140
AnnaBridge 157:e7ca05fa8600 1141 /**
AnnaBridge 157:e7ca05fa8600 1142 \brief Store-Release (8 bit)
AnnaBridge 157:e7ca05fa8600 1143 \details Executes a STLB instruction for 8 bit values.
AnnaBridge 157:e7ca05fa8600 1144 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1145 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1146 */
AnnaBridge 157:e7ca05fa8600 1147 __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge 157:e7ca05fa8600 1148 {
AnnaBridge 157:e7ca05fa8600 1149 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1150 }
AnnaBridge 157:e7ca05fa8600 1151
AnnaBridge 157:e7ca05fa8600 1152
AnnaBridge 157:e7ca05fa8600 1153 /**
AnnaBridge 157:e7ca05fa8600 1154 \brief Store-Release (16 bit)
AnnaBridge 157:e7ca05fa8600 1155 \details Executes a STLH instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1156 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1157 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1158 */
AnnaBridge 157:e7ca05fa8600 1159 __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge 157:e7ca05fa8600 1160 {
AnnaBridge 157:e7ca05fa8600 1161 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1162 }
AnnaBridge 157:e7ca05fa8600 1163
AnnaBridge 157:e7ca05fa8600 1164
AnnaBridge 157:e7ca05fa8600 1165 /**
AnnaBridge 157:e7ca05fa8600 1166 \brief Store-Release (32 bit)
AnnaBridge 157:e7ca05fa8600 1167 \details Executes a STL instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1168 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1169 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1170 */
AnnaBridge 157:e7ca05fa8600 1171 __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
AnnaBridge 157:e7ca05fa8600 1172 {
AnnaBridge 157:e7ca05fa8600 1173 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1174 }
AnnaBridge 157:e7ca05fa8600 1175
AnnaBridge 157:e7ca05fa8600 1176
AnnaBridge 157:e7ca05fa8600 1177 /**
AnnaBridge 157:e7ca05fa8600 1178 \brief Load-Acquire Exclusive (8 bit)
AnnaBridge 157:e7ca05fa8600 1179 \details Executes a LDAB exclusive instruction for 8 bit value.
AnnaBridge 157:e7ca05fa8600 1180 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1181 \return value of type uint8_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1182 */
AnnaBridge 157:e7ca05fa8600 1183 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
AnnaBridge 157:e7ca05fa8600 1184
AnnaBridge 157:e7ca05fa8600 1185
AnnaBridge 157:e7ca05fa8600 1186 /**
AnnaBridge 157:e7ca05fa8600 1187 \brief Load-Acquire Exclusive (16 bit)
AnnaBridge 157:e7ca05fa8600 1188 \details Executes a LDAH exclusive instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1189 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1190 \return value of type uint16_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1191 */
AnnaBridge 157:e7ca05fa8600 1192 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
AnnaBridge 157:e7ca05fa8600 1193
AnnaBridge 157:e7ca05fa8600 1194
AnnaBridge 157:e7ca05fa8600 1195 /**
AnnaBridge 157:e7ca05fa8600 1196 \brief Load-Acquire Exclusive (32 bit)
AnnaBridge 157:e7ca05fa8600 1197 \details Executes a LDA exclusive instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1198 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1199 \return value of type uint32_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1200 */
AnnaBridge 157:e7ca05fa8600 1201 #define __LDAEX (uint32_t)__builtin_arm_ldaex
AnnaBridge 157:e7ca05fa8600 1202
AnnaBridge 157:e7ca05fa8600 1203
AnnaBridge 157:e7ca05fa8600 1204 /**
AnnaBridge 157:e7ca05fa8600 1205 \brief Store-Release Exclusive (8 bit)
AnnaBridge 157:e7ca05fa8600 1206 \details Executes a STLB exclusive instruction for 8 bit values.
AnnaBridge 157:e7ca05fa8600 1207 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1208 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1209 \return 0 Function succeeded
AnnaBridge 157:e7ca05fa8600 1210 \return 1 Function failed
AnnaBridge 157:e7ca05fa8600 1211 */
AnnaBridge 157:e7ca05fa8600 1212 #define __STLEXB (uint32_t)__builtin_arm_stlex
AnnaBridge 157:e7ca05fa8600 1213
AnnaBridge 157:e7ca05fa8600 1214
AnnaBridge 157:e7ca05fa8600 1215 /**
AnnaBridge 157:e7ca05fa8600 1216 \brief Store-Release Exclusive (16 bit)
AnnaBridge 157:e7ca05fa8600 1217 \details Executes a STLH exclusive instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1218 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1219 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1220 \return 0 Function succeeded
AnnaBridge 157:e7ca05fa8600 1221 \return 1 Function failed
AnnaBridge 157:e7ca05fa8600 1222 */
AnnaBridge 157:e7ca05fa8600 1223 #define __STLEXH (uint32_t)__builtin_arm_stlex
AnnaBridge 157:e7ca05fa8600 1224
AnnaBridge 157:e7ca05fa8600 1225
AnnaBridge 157:e7ca05fa8600 1226 /**
AnnaBridge 157:e7ca05fa8600 1227 \brief Store-Release Exclusive (32 bit)
AnnaBridge 157:e7ca05fa8600 1228 \details Executes a STL exclusive instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1229 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1230 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1231 \return 0 Function succeeded
AnnaBridge 157:e7ca05fa8600 1232 \return 1 Function failed
AnnaBridge 157:e7ca05fa8600 1233 */
AnnaBridge 157:e7ca05fa8600 1234 #define __STLEX (uint32_t)__builtin_arm_stlex
AnnaBridge 157:e7ca05fa8600 1235
AnnaBridge 157:e7ca05fa8600 1236 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1237 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 157:e7ca05fa8600 1238
AnnaBridge 157:e7ca05fa8600 1239 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
AnnaBridge 157:e7ca05fa8600 1240
AnnaBridge 157:e7ca05fa8600 1241
AnnaBridge 157:e7ca05fa8600 1242 /* ################### Compiler specific Intrinsics ########################### */
AnnaBridge 157:e7ca05fa8600 1243 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
AnnaBridge 157:e7ca05fa8600 1244 Access to dedicated SIMD instructions
AnnaBridge 157:e7ca05fa8600 1245 @{
AnnaBridge 157:e7ca05fa8600 1246 */
AnnaBridge 157:e7ca05fa8600 1247
AnnaBridge 157:e7ca05fa8600 1248 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
AnnaBridge 157:e7ca05fa8600 1249
AnnaBridge 157:e7ca05fa8600 1250 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1251 {
AnnaBridge 157:e7ca05fa8600 1252 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1253
AnnaBridge 157:e7ca05fa8600 1254 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1255 return(result);
AnnaBridge 157:e7ca05fa8600 1256 }
AnnaBridge 157:e7ca05fa8600 1257
AnnaBridge 157:e7ca05fa8600 1258 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1259 {
AnnaBridge 157:e7ca05fa8600 1260 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1261
AnnaBridge 157:e7ca05fa8600 1262 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1263 return(result);
AnnaBridge 157:e7ca05fa8600 1264 }
AnnaBridge 157:e7ca05fa8600 1265
AnnaBridge 157:e7ca05fa8600 1266 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1267 {
AnnaBridge 157:e7ca05fa8600 1268 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1269
AnnaBridge 157:e7ca05fa8600 1270 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1271 return(result);
AnnaBridge 157:e7ca05fa8600 1272 }
AnnaBridge 157:e7ca05fa8600 1273
AnnaBridge 157:e7ca05fa8600 1274 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1275 {
AnnaBridge 157:e7ca05fa8600 1276 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1277
AnnaBridge 157:e7ca05fa8600 1278 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1279 return(result);
AnnaBridge 157:e7ca05fa8600 1280 }
AnnaBridge 157:e7ca05fa8600 1281
AnnaBridge 157:e7ca05fa8600 1282 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1283 {
AnnaBridge 157:e7ca05fa8600 1284 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1285
AnnaBridge 157:e7ca05fa8600 1286 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1287 return(result);
AnnaBridge 157:e7ca05fa8600 1288 }
AnnaBridge 157:e7ca05fa8600 1289
AnnaBridge 157:e7ca05fa8600 1290 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1291 {
AnnaBridge 157:e7ca05fa8600 1292 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1293
AnnaBridge 157:e7ca05fa8600 1294 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1295 return(result);
AnnaBridge 157:e7ca05fa8600 1296 }
AnnaBridge 157:e7ca05fa8600 1297
AnnaBridge 157:e7ca05fa8600 1298
AnnaBridge 157:e7ca05fa8600 1299 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1300 {
AnnaBridge 157:e7ca05fa8600 1301 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1302
AnnaBridge 157:e7ca05fa8600 1303 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1304 return(result);
AnnaBridge 157:e7ca05fa8600 1305 }
AnnaBridge 157:e7ca05fa8600 1306
AnnaBridge 157:e7ca05fa8600 1307 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1308 {
AnnaBridge 157:e7ca05fa8600 1309 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1310
AnnaBridge 157:e7ca05fa8600 1311 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1312 return(result);
AnnaBridge 157:e7ca05fa8600 1313 }
AnnaBridge 157:e7ca05fa8600 1314
AnnaBridge 157:e7ca05fa8600 1315 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1316 {
AnnaBridge 157:e7ca05fa8600 1317 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1318
AnnaBridge 157:e7ca05fa8600 1319 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1320 return(result);
AnnaBridge 157:e7ca05fa8600 1321 }
AnnaBridge 157:e7ca05fa8600 1322
AnnaBridge 157:e7ca05fa8600 1323 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1324 {
AnnaBridge 157:e7ca05fa8600 1325 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1326
AnnaBridge 157:e7ca05fa8600 1327 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1328 return(result);
AnnaBridge 157:e7ca05fa8600 1329 }
AnnaBridge 157:e7ca05fa8600 1330
AnnaBridge 157:e7ca05fa8600 1331 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1332 {
AnnaBridge 157:e7ca05fa8600 1333 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1334
AnnaBridge 157:e7ca05fa8600 1335 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1336 return(result);
AnnaBridge 157:e7ca05fa8600 1337 }
AnnaBridge 157:e7ca05fa8600 1338
AnnaBridge 157:e7ca05fa8600 1339 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1340 {
AnnaBridge 157:e7ca05fa8600 1341 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1342
AnnaBridge 157:e7ca05fa8600 1343 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1344 return(result);
AnnaBridge 157:e7ca05fa8600 1345 }
AnnaBridge 157:e7ca05fa8600 1346
AnnaBridge 157:e7ca05fa8600 1347
AnnaBridge 157:e7ca05fa8600 1348 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1349 {
AnnaBridge 157:e7ca05fa8600 1350 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1351
AnnaBridge 157:e7ca05fa8600 1352 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1353 return(result);
AnnaBridge 157:e7ca05fa8600 1354 }
AnnaBridge 157:e7ca05fa8600 1355
AnnaBridge 157:e7ca05fa8600 1356 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1357 {
AnnaBridge 157:e7ca05fa8600 1358 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1359
AnnaBridge 157:e7ca05fa8600 1360 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1361 return(result);
AnnaBridge 157:e7ca05fa8600 1362 }
AnnaBridge 157:e7ca05fa8600 1363
AnnaBridge 157:e7ca05fa8600 1364 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1365 {
AnnaBridge 157:e7ca05fa8600 1366 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1367
AnnaBridge 157:e7ca05fa8600 1368 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1369 return(result);
AnnaBridge 157:e7ca05fa8600 1370 }
AnnaBridge 157:e7ca05fa8600 1371
AnnaBridge 157:e7ca05fa8600 1372 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1373 {
AnnaBridge 157:e7ca05fa8600 1374 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1375
AnnaBridge 157:e7ca05fa8600 1376 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1377 return(result);
AnnaBridge 157:e7ca05fa8600 1378 }
AnnaBridge 157:e7ca05fa8600 1379
AnnaBridge 157:e7ca05fa8600 1380 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1381 {
AnnaBridge 157:e7ca05fa8600 1382 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1383
AnnaBridge 157:e7ca05fa8600 1384 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1385 return(result);
AnnaBridge 157:e7ca05fa8600 1386 }
AnnaBridge 157:e7ca05fa8600 1387
AnnaBridge 157:e7ca05fa8600 1388 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1389 {
AnnaBridge 157:e7ca05fa8600 1390 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1391
AnnaBridge 157:e7ca05fa8600 1392 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1393 return(result);
AnnaBridge 157:e7ca05fa8600 1394 }
AnnaBridge 157:e7ca05fa8600 1395
AnnaBridge 157:e7ca05fa8600 1396 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1397 {
AnnaBridge 157:e7ca05fa8600 1398 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1399
AnnaBridge 157:e7ca05fa8600 1400 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1401 return(result);
AnnaBridge 157:e7ca05fa8600 1402 }
AnnaBridge 157:e7ca05fa8600 1403
AnnaBridge 157:e7ca05fa8600 1404 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1405 {
AnnaBridge 157:e7ca05fa8600 1406 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1407
AnnaBridge 157:e7ca05fa8600 1408 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1409 return(result);
AnnaBridge 157:e7ca05fa8600 1410 }
AnnaBridge 157:e7ca05fa8600 1411
AnnaBridge 157:e7ca05fa8600 1412 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1413 {
AnnaBridge 157:e7ca05fa8600 1414 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1415
AnnaBridge 157:e7ca05fa8600 1416 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1417 return(result);
AnnaBridge 157:e7ca05fa8600 1418 }
AnnaBridge 157:e7ca05fa8600 1419
AnnaBridge 157:e7ca05fa8600 1420 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1421 {
AnnaBridge 157:e7ca05fa8600 1422 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1423
AnnaBridge 157:e7ca05fa8600 1424 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1425 return(result);
AnnaBridge 157:e7ca05fa8600 1426 }
AnnaBridge 157:e7ca05fa8600 1427
AnnaBridge 157:e7ca05fa8600 1428 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1429 {
AnnaBridge 157:e7ca05fa8600 1430 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1431
AnnaBridge 157:e7ca05fa8600 1432 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1433 return(result);
AnnaBridge 157:e7ca05fa8600 1434 }
AnnaBridge 157:e7ca05fa8600 1435
AnnaBridge 157:e7ca05fa8600 1436 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1437 {
AnnaBridge 157:e7ca05fa8600 1438 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1439
AnnaBridge 157:e7ca05fa8600 1440 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1441 return(result);
AnnaBridge 157:e7ca05fa8600 1442 }
AnnaBridge 157:e7ca05fa8600 1443
AnnaBridge 157:e7ca05fa8600 1444 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1445 {
AnnaBridge 157:e7ca05fa8600 1446 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1447
AnnaBridge 157:e7ca05fa8600 1448 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1449 return(result);
AnnaBridge 157:e7ca05fa8600 1450 }
AnnaBridge 157:e7ca05fa8600 1451
AnnaBridge 157:e7ca05fa8600 1452 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1453 {
AnnaBridge 157:e7ca05fa8600 1454 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1455
AnnaBridge 157:e7ca05fa8600 1456 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1457 return(result);
AnnaBridge 157:e7ca05fa8600 1458 }
AnnaBridge 157:e7ca05fa8600 1459
AnnaBridge 157:e7ca05fa8600 1460 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1461 {
AnnaBridge 157:e7ca05fa8600 1462 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1463
AnnaBridge 157:e7ca05fa8600 1464 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1465 return(result);
AnnaBridge 157:e7ca05fa8600 1466 }
AnnaBridge 157:e7ca05fa8600 1467
AnnaBridge 157:e7ca05fa8600 1468 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1469 {
AnnaBridge 157:e7ca05fa8600 1470 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1471
AnnaBridge 157:e7ca05fa8600 1472 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1473 return(result);
AnnaBridge 157:e7ca05fa8600 1474 }
AnnaBridge 157:e7ca05fa8600 1475
AnnaBridge 157:e7ca05fa8600 1476 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1477 {
AnnaBridge 157:e7ca05fa8600 1478 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1479
AnnaBridge 157:e7ca05fa8600 1480 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1481 return(result);
AnnaBridge 157:e7ca05fa8600 1482 }
AnnaBridge 157:e7ca05fa8600 1483
AnnaBridge 157:e7ca05fa8600 1484 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1485 {
AnnaBridge 157:e7ca05fa8600 1486 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1487
AnnaBridge 157:e7ca05fa8600 1488 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1489 return(result);
AnnaBridge 157:e7ca05fa8600 1490 }
AnnaBridge 157:e7ca05fa8600 1491
AnnaBridge 157:e7ca05fa8600 1492 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1493 {
AnnaBridge 157:e7ca05fa8600 1494 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1495
AnnaBridge 157:e7ca05fa8600 1496 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1497 return(result);
AnnaBridge 157:e7ca05fa8600 1498 }
AnnaBridge 157:e7ca05fa8600 1499
AnnaBridge 157:e7ca05fa8600 1500 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1501 {
AnnaBridge 157:e7ca05fa8600 1502 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1503
AnnaBridge 157:e7ca05fa8600 1504 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1505 return(result);
AnnaBridge 157:e7ca05fa8600 1506 }
AnnaBridge 157:e7ca05fa8600 1507
AnnaBridge 157:e7ca05fa8600 1508 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1509 {
AnnaBridge 157:e7ca05fa8600 1510 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1511
AnnaBridge 157:e7ca05fa8600 1512 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1513 return(result);
AnnaBridge 157:e7ca05fa8600 1514 }
AnnaBridge 157:e7ca05fa8600 1515
AnnaBridge 157:e7ca05fa8600 1516 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1517 {
AnnaBridge 157:e7ca05fa8600 1518 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1519
AnnaBridge 157:e7ca05fa8600 1520 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1521 return(result);
AnnaBridge 157:e7ca05fa8600 1522 }
AnnaBridge 157:e7ca05fa8600 1523
AnnaBridge 157:e7ca05fa8600 1524 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1525 {
AnnaBridge 157:e7ca05fa8600 1526 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1527
AnnaBridge 157:e7ca05fa8600 1528 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1529 return(result);
AnnaBridge 157:e7ca05fa8600 1530 }
AnnaBridge 157:e7ca05fa8600 1531
AnnaBridge 157:e7ca05fa8600 1532 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1533 {
AnnaBridge 157:e7ca05fa8600 1534 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1535
AnnaBridge 157:e7ca05fa8600 1536 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1537 return(result);
AnnaBridge 157:e7ca05fa8600 1538 }
AnnaBridge 157:e7ca05fa8600 1539
AnnaBridge 157:e7ca05fa8600 1540 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1541 {
AnnaBridge 157:e7ca05fa8600 1542 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1543
AnnaBridge 157:e7ca05fa8600 1544 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1545 return(result);
AnnaBridge 157:e7ca05fa8600 1546 }
AnnaBridge 157:e7ca05fa8600 1547
AnnaBridge 157:e7ca05fa8600 1548 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 157:e7ca05fa8600 1549 {
AnnaBridge 157:e7ca05fa8600 1550 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1551
AnnaBridge 157:e7ca05fa8600 1552 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 157:e7ca05fa8600 1553 return(result);
AnnaBridge 157:e7ca05fa8600 1554 }
AnnaBridge 157:e7ca05fa8600 1555
AnnaBridge 157:e7ca05fa8600 1556 #define __SSAT16(ARG1,ARG2) \
AnnaBridge 157:e7ca05fa8600 1557 ({ \
AnnaBridge 157:e7ca05fa8600 1558 int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 157:e7ca05fa8600 1559 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 157:e7ca05fa8600 1560 __RES; \
AnnaBridge 157:e7ca05fa8600 1561 })
AnnaBridge 157:e7ca05fa8600 1562
AnnaBridge 157:e7ca05fa8600 1563 #define __USAT16(ARG1,ARG2) \
AnnaBridge 157:e7ca05fa8600 1564 ({ \
AnnaBridge 157:e7ca05fa8600 1565 uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 157:e7ca05fa8600 1566 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 157:e7ca05fa8600 1567 __RES; \
AnnaBridge 157:e7ca05fa8600 1568 })
AnnaBridge 157:e7ca05fa8600 1569
AnnaBridge 157:e7ca05fa8600 1570 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
AnnaBridge 157:e7ca05fa8600 1571 {
AnnaBridge 157:e7ca05fa8600 1572 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1573
AnnaBridge 157:e7ca05fa8600 1574 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge 157:e7ca05fa8600 1575 return(result);
AnnaBridge 157:e7ca05fa8600 1576 }
AnnaBridge 157:e7ca05fa8600 1577
AnnaBridge 157:e7ca05fa8600 1578 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1579 {
AnnaBridge 157:e7ca05fa8600 1580 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1581
AnnaBridge 157:e7ca05fa8600 1582 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1583 return(result);
AnnaBridge 157:e7ca05fa8600 1584 }
AnnaBridge 157:e7ca05fa8600 1585
AnnaBridge 157:e7ca05fa8600 1586 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
AnnaBridge 157:e7ca05fa8600 1587 {
AnnaBridge 157:e7ca05fa8600 1588 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1589
AnnaBridge 157:e7ca05fa8600 1590 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge 157:e7ca05fa8600 1591 return(result);
AnnaBridge 157:e7ca05fa8600 1592 }
AnnaBridge 157:e7ca05fa8600 1593
AnnaBridge 157:e7ca05fa8600 1594 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1595 {
AnnaBridge 157:e7ca05fa8600 1596 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1597
AnnaBridge 157:e7ca05fa8600 1598 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1599 return(result);
AnnaBridge 157:e7ca05fa8600 1600 }
AnnaBridge 157:e7ca05fa8600 1601
AnnaBridge 157:e7ca05fa8600 1602 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1603 {
AnnaBridge 157:e7ca05fa8600 1604 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1605
AnnaBridge 157:e7ca05fa8600 1606 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1607 return(result);
AnnaBridge 157:e7ca05fa8600 1608 }
AnnaBridge 157:e7ca05fa8600 1609
AnnaBridge 157:e7ca05fa8600 1610 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1611 {
AnnaBridge 157:e7ca05fa8600 1612 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1613
AnnaBridge 157:e7ca05fa8600 1614 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1615 return(result);
AnnaBridge 157:e7ca05fa8600 1616 }
AnnaBridge 157:e7ca05fa8600 1617
AnnaBridge 157:e7ca05fa8600 1618 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 157:e7ca05fa8600 1619 {
AnnaBridge 157:e7ca05fa8600 1620 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1621
AnnaBridge 157:e7ca05fa8600 1622 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 157:e7ca05fa8600 1623 return(result);
AnnaBridge 157:e7ca05fa8600 1624 }
AnnaBridge 157:e7ca05fa8600 1625
AnnaBridge 157:e7ca05fa8600 1626 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 157:e7ca05fa8600 1627 {
AnnaBridge 157:e7ca05fa8600 1628 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1629
AnnaBridge 157:e7ca05fa8600 1630 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 157:e7ca05fa8600 1631 return(result);
AnnaBridge 157:e7ca05fa8600 1632 }
AnnaBridge 157:e7ca05fa8600 1633
AnnaBridge 157:e7ca05fa8600 1634 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 157:e7ca05fa8600 1635 {
AnnaBridge 157:e7ca05fa8600 1636 union llreg_u{
AnnaBridge 157:e7ca05fa8600 1637 uint32_t w32[2];
AnnaBridge 157:e7ca05fa8600 1638 uint64_t w64;
AnnaBridge 157:e7ca05fa8600 1639 } llr;
AnnaBridge 157:e7ca05fa8600 1640 llr.w64 = acc;
AnnaBridge 157:e7ca05fa8600 1641
AnnaBridge 157:e7ca05fa8600 1642 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 157:e7ca05fa8600 1643 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 157:e7ca05fa8600 1644 #else /* Big endian */
AnnaBridge 157:e7ca05fa8600 1645 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 157:e7ca05fa8600 1646 #endif
AnnaBridge 157:e7ca05fa8600 1647
AnnaBridge 157:e7ca05fa8600 1648 return(llr.w64);
AnnaBridge 157:e7ca05fa8600 1649 }
AnnaBridge 157:e7ca05fa8600 1650
AnnaBridge 157:e7ca05fa8600 1651 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 157:e7ca05fa8600 1652 {
AnnaBridge 157:e7ca05fa8600 1653 union llreg_u{
AnnaBridge 157:e7ca05fa8600 1654 uint32_t w32[2];
AnnaBridge 157:e7ca05fa8600 1655 uint64_t w64;
AnnaBridge 157:e7ca05fa8600 1656 } llr;
AnnaBridge 157:e7ca05fa8600 1657 llr.w64 = acc;
AnnaBridge 157:e7ca05fa8600 1658
AnnaBridge 157:e7ca05fa8600 1659 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 157:e7ca05fa8600 1660 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 157:e7ca05fa8600 1661 #else /* Big endian */
AnnaBridge 157:e7ca05fa8600 1662 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 157:e7ca05fa8600 1663 #endif
AnnaBridge 157:e7ca05fa8600 1664
AnnaBridge 157:e7ca05fa8600 1665 return(llr.w64);
AnnaBridge 157:e7ca05fa8600 1666 }
AnnaBridge 157:e7ca05fa8600 1667
AnnaBridge 157:e7ca05fa8600 1668 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1669 {
AnnaBridge 157:e7ca05fa8600 1670 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1671
AnnaBridge 157:e7ca05fa8600 1672 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1673 return(result);
AnnaBridge 157:e7ca05fa8600 1674 }
AnnaBridge 157:e7ca05fa8600 1675
AnnaBridge 157:e7ca05fa8600 1676 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1677 {
AnnaBridge 157:e7ca05fa8600 1678 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1679
AnnaBridge 157:e7ca05fa8600 1680 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1681 return(result);
AnnaBridge 157:e7ca05fa8600 1682 }
AnnaBridge 157:e7ca05fa8600 1683
AnnaBridge 157:e7ca05fa8600 1684 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 157:e7ca05fa8600 1685 {
AnnaBridge 157:e7ca05fa8600 1686 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1687
AnnaBridge 157:e7ca05fa8600 1688 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 157:e7ca05fa8600 1689 return(result);
AnnaBridge 157:e7ca05fa8600 1690 }
AnnaBridge 157:e7ca05fa8600 1691
AnnaBridge 157:e7ca05fa8600 1692 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 157:e7ca05fa8600 1693 {
AnnaBridge 157:e7ca05fa8600 1694 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1695
AnnaBridge 157:e7ca05fa8600 1696 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 157:e7ca05fa8600 1697 return(result);
AnnaBridge 157:e7ca05fa8600 1698 }
AnnaBridge 157:e7ca05fa8600 1699
AnnaBridge 157:e7ca05fa8600 1700 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 157:e7ca05fa8600 1701 {
AnnaBridge 157:e7ca05fa8600 1702 union llreg_u{
AnnaBridge 157:e7ca05fa8600 1703 uint32_t w32[2];
AnnaBridge 157:e7ca05fa8600 1704 uint64_t w64;
AnnaBridge 157:e7ca05fa8600 1705 } llr;
AnnaBridge 157:e7ca05fa8600 1706 llr.w64 = acc;
AnnaBridge 157:e7ca05fa8600 1707
AnnaBridge 157:e7ca05fa8600 1708 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 157:e7ca05fa8600 1709 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 157:e7ca05fa8600 1710 #else /* Big endian */
AnnaBridge 157:e7ca05fa8600 1711 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 157:e7ca05fa8600 1712 #endif
AnnaBridge 157:e7ca05fa8600 1713
AnnaBridge 157:e7ca05fa8600 1714 return(llr.w64);
AnnaBridge 157:e7ca05fa8600 1715 }
AnnaBridge 157:e7ca05fa8600 1716
AnnaBridge 157:e7ca05fa8600 1717 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 157:e7ca05fa8600 1718 {
AnnaBridge 157:e7ca05fa8600 1719 union llreg_u{
AnnaBridge 157:e7ca05fa8600 1720 uint32_t w32[2];
AnnaBridge 157:e7ca05fa8600 1721 uint64_t w64;
AnnaBridge 157:e7ca05fa8600 1722 } llr;
AnnaBridge 157:e7ca05fa8600 1723 llr.w64 = acc;
AnnaBridge 157:e7ca05fa8600 1724
AnnaBridge 157:e7ca05fa8600 1725 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 157:e7ca05fa8600 1726 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 157:e7ca05fa8600 1727 #else /* Big endian */
AnnaBridge 157:e7ca05fa8600 1728 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 157:e7ca05fa8600 1729 #endif
AnnaBridge 157:e7ca05fa8600 1730
AnnaBridge 157:e7ca05fa8600 1731 return(llr.w64);
AnnaBridge 157:e7ca05fa8600 1732 }
AnnaBridge 157:e7ca05fa8600 1733
AnnaBridge 157:e7ca05fa8600 1734 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1735 {
AnnaBridge 157:e7ca05fa8600 1736 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1737
AnnaBridge 157:e7ca05fa8600 1738 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1739 return(result);
AnnaBridge 157:e7ca05fa8600 1740 }
AnnaBridge 157:e7ca05fa8600 1741
AnnaBridge 157:e7ca05fa8600 1742 __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
AnnaBridge 157:e7ca05fa8600 1743 {
AnnaBridge 157:e7ca05fa8600 1744 int32_t result;
AnnaBridge 157:e7ca05fa8600 1745
AnnaBridge 157:e7ca05fa8600 1746 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1747 return(result);
AnnaBridge 157:e7ca05fa8600 1748 }
AnnaBridge 157:e7ca05fa8600 1749
AnnaBridge 157:e7ca05fa8600 1750 __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
AnnaBridge 157:e7ca05fa8600 1751 {
AnnaBridge 157:e7ca05fa8600 1752 int32_t result;
AnnaBridge 157:e7ca05fa8600 1753
AnnaBridge 157:e7ca05fa8600 1754 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1755 return(result);
AnnaBridge 157:e7ca05fa8600 1756 }
AnnaBridge 157:e7ca05fa8600 1757
AnnaBridge 157:e7ca05fa8600 1758 #if 0
AnnaBridge 157:e7ca05fa8600 1759 #define __PKHBT(ARG1,ARG2,ARG3) \
AnnaBridge 157:e7ca05fa8600 1760 ({ \
AnnaBridge 157:e7ca05fa8600 1761 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge 157:e7ca05fa8600 1762 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge 157:e7ca05fa8600 1763 __RES; \
AnnaBridge 157:e7ca05fa8600 1764 })
AnnaBridge 157:e7ca05fa8600 1765
AnnaBridge 157:e7ca05fa8600 1766 #define __PKHTB(ARG1,ARG2,ARG3) \
AnnaBridge 157:e7ca05fa8600 1767 ({ \
AnnaBridge 157:e7ca05fa8600 1768 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge 157:e7ca05fa8600 1769 if (ARG3 == 0) \
AnnaBridge 157:e7ca05fa8600 1770 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
AnnaBridge 157:e7ca05fa8600 1771 else \
AnnaBridge 157:e7ca05fa8600 1772 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge 157:e7ca05fa8600 1773 __RES; \
AnnaBridge 157:e7ca05fa8600 1774 })
AnnaBridge 157:e7ca05fa8600 1775 #endif
AnnaBridge 157:e7ca05fa8600 1776
AnnaBridge 157:e7ca05fa8600 1777 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
AnnaBridge 157:e7ca05fa8600 1778 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
AnnaBridge 157:e7ca05fa8600 1779
AnnaBridge 157:e7ca05fa8600 1780 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
AnnaBridge 157:e7ca05fa8600 1781 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
AnnaBridge 157:e7ca05fa8600 1782
AnnaBridge 157:e7ca05fa8600 1783 __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
AnnaBridge 157:e7ca05fa8600 1784 {
AnnaBridge 157:e7ca05fa8600 1785 int32_t result;
AnnaBridge 157:e7ca05fa8600 1786
AnnaBridge 157:e7ca05fa8600 1787 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 157:e7ca05fa8600 1788 return(result);
AnnaBridge 157:e7ca05fa8600 1789 }
AnnaBridge 157:e7ca05fa8600 1790
AnnaBridge 157:e7ca05fa8600 1791 #endif /* (__ARM_FEATURE_DSP == 1) */
AnnaBridge 157:e7ca05fa8600 1792 /*@} end of group CMSIS_SIMD_intrinsics */
AnnaBridge 157:e7ca05fa8600 1793
AnnaBridge 157:e7ca05fa8600 1794
AnnaBridge 157:e7ca05fa8600 1795 #endif /* __CMSIS_ARMCLANG_H */