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TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim_ex.h@163:e59c8e839560, 2018-03-20 (annotated)

Committer:
AnnaBridge
Date:
Tue Mar 20 13:30:58 2018 +0000
Revision:
163:e59c8e839560
Child:
168:b9e159c1930a
mbed library. Release version 160

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 163:e59c8e839560 1 /**
AnnaBridge 163:e59c8e839560 2 ******************************************************************************
AnnaBridge 163:e59c8e839560 3 * @file stm32f3xx_hal_tim_ex.h
AnnaBridge 163:e59c8e839560 4 * @author MCD Application Team
AnnaBridge 163:e59c8e839560 5 * @version V1.4.0
AnnaBridge 163:e59c8e839560 6 * @date 16-December-2016
AnnaBridge 163:e59c8e839560 7 * @brief Header file of TIM HAL Extended module.
AnnaBridge 163:e59c8e839560 8 ******************************************************************************
AnnaBridge 163:e59c8e839560 9 * @attention
AnnaBridge 163:e59c8e839560 10 *
AnnaBridge 163:e59c8e839560 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 163:e59c8e839560 12 *
AnnaBridge 163:e59c8e839560 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 163:e59c8e839560 14 * are permitted provided that the following conditions are met:
AnnaBridge 163:e59c8e839560 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 163:e59c8e839560 16 * this list of conditions and the following disclaimer.
AnnaBridge 163:e59c8e839560 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 163:e59c8e839560 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 163:e59c8e839560 19 * and/or other materials provided with the distribution.
AnnaBridge 163:e59c8e839560 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 163:e59c8e839560 21 * may be used to endorse or promote products derived from this software
AnnaBridge 163:e59c8e839560 22 * without specific prior written permission.
AnnaBridge 163:e59c8e839560 23 *
AnnaBridge 163:e59c8e839560 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 163:e59c8e839560 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 163:e59c8e839560 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 163:e59c8e839560 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 163:e59c8e839560 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 163:e59c8e839560 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 163:e59c8e839560 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 163:e59c8e839560 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 163:e59c8e839560 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 163:e59c8e839560 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 163:e59c8e839560 34 *
AnnaBridge 163:e59c8e839560 35 ******************************************************************************
AnnaBridge 163:e59c8e839560 36 */
AnnaBridge 163:e59c8e839560 37
AnnaBridge 163:e59c8e839560 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 163:e59c8e839560 39 #ifndef __STM32F3xx_HAL_TIM_EX_H
AnnaBridge 163:e59c8e839560 40 #define __STM32F3xx_HAL_TIM_EX_H
AnnaBridge 163:e59c8e839560 41
AnnaBridge 163:e59c8e839560 42 #ifdef __cplusplus
AnnaBridge 163:e59c8e839560 43 extern "C" {
AnnaBridge 163:e59c8e839560 44 #endif
AnnaBridge 163:e59c8e839560 45
AnnaBridge 163:e59c8e839560 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 47 #include "stm32f3xx_hal_def.h"
AnnaBridge 163:e59c8e839560 48
AnnaBridge 163:e59c8e839560 49 /** @addtogroup STM32F3xx_HAL_Driver
AnnaBridge 163:e59c8e839560 50 * @{
AnnaBridge 163:e59c8e839560 51 */
AnnaBridge 163:e59c8e839560 52
AnnaBridge 163:e59c8e839560 53 /** @addtogroup TIMEx
AnnaBridge 163:e59c8e839560 54 * @{
AnnaBridge 163:e59c8e839560 55 */
AnnaBridge 163:e59c8e839560 56
AnnaBridge 163:e59c8e839560 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 58 /** @defgroup TIMEx_Exported_Types TIMEx Exported Types
AnnaBridge 163:e59c8e839560 59 * @{
AnnaBridge 163:e59c8e839560 60 */
AnnaBridge 163:e59c8e839560 61
AnnaBridge 163:e59c8e839560 62 /**
AnnaBridge 163:e59c8e839560 63 * @brief TIM Hall sensor Configuration Structure definition
AnnaBridge 163:e59c8e839560 64 */
AnnaBridge 163:e59c8e839560 65
AnnaBridge 163:e59c8e839560 66 typedef struct
AnnaBridge 163:e59c8e839560 67 {
AnnaBridge 163:e59c8e839560 68
AnnaBridge 163:e59c8e839560 69 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 163:e59c8e839560 70 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 163:e59c8e839560 71
AnnaBridge 163:e59c8e839560 72 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 163:e59c8e839560 73 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 163:e59c8e839560 74
AnnaBridge 163:e59c8e839560 75 uint32_t IC1Filter; /*!< Specifies the input capture filter.
AnnaBridge 163:e59c8e839560 76 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
AnnaBridge 163:e59c8e839560 77 uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge 163:e59c8e839560 78 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
AnnaBridge 163:e59c8e839560 79 } TIM_HallSensor_InitTypeDef;
AnnaBridge 163:e59c8e839560 80
AnnaBridge 163:e59c8e839560 81 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 163:e59c8e839560 82 /**
AnnaBridge 163:e59c8e839560 83 * @brief TIM Master configuration Structure definition
AnnaBridge 163:e59c8e839560 84 * @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO
AnnaBridge 163:e59c8e839560 85 * output
AnnaBridge 163:e59c8e839560 86 */
AnnaBridge 163:e59c8e839560 87 typedef struct {
AnnaBridge 163:e59c8e839560 88 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
AnnaBridge 163:e59c8e839560 89 This parameter can be a value of @ref TIM_Master_Mode_Selection */
AnnaBridge 163:e59c8e839560 90 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
AnnaBridge 163:e59c8e839560 91 This parameter can be a value of @ref TIM_Master_Slave_Mode */
AnnaBridge 163:e59c8e839560 92 }TIM_MasterConfigTypeDef;
AnnaBridge 163:e59c8e839560 93
AnnaBridge 163:e59c8e839560 94 /**
AnnaBridge 163:e59c8e839560 95 * @brief TIM Break and Dead time configuration Structure definition
AnnaBridge 163:e59c8e839560 96 * @note STM32F373xC and STM32F378xx: single break input with configurable polarity.
AnnaBridge 163:e59c8e839560 97 */
AnnaBridge 163:e59c8e839560 98 typedef struct
AnnaBridge 163:e59c8e839560 99 {
AnnaBridge 163:e59c8e839560 100 uint32_t OffStateRunMode; /*!< TIM off state in run mode
AnnaBridge 163:e59c8e839560 101 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
AnnaBridge 163:e59c8e839560 102 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
AnnaBridge 163:e59c8e839560 103 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
AnnaBridge 163:e59c8e839560 104 uint32_t LockLevel; /*!< TIM Lock level
AnnaBridge 163:e59c8e839560 105 This parameter can be a value of @ref TIM_Lock_level */
AnnaBridge 163:e59c8e839560 106 uint32_t DeadTime; /*!< TIM dead Time
AnnaBridge 163:e59c8e839560 107 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
AnnaBridge 163:e59c8e839560 108 uint32_t BreakState; /*!< TIM Break State
AnnaBridge 163:e59c8e839560 109 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
AnnaBridge 163:e59c8e839560 110 uint32_t BreakPolarity; /*!< TIM Break input polarity
AnnaBridge 163:e59c8e839560 111 This parameter can be a value of @ref TIM_Break_Polarity */
AnnaBridge 163:e59c8e839560 112 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
AnnaBridge 163:e59c8e839560 113 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
AnnaBridge 163:e59c8e839560 114 } TIM_BreakDeadTimeConfigTypeDef;
AnnaBridge 163:e59c8e839560 115
AnnaBridge 163:e59c8e839560 116 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 163:e59c8e839560 117
AnnaBridge 163:e59c8e839560 118 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
AnnaBridge 163:e59c8e839560 119 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
AnnaBridge 163:e59c8e839560 120 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
AnnaBridge 163:e59c8e839560 121 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 163:e59c8e839560 122 /**
AnnaBridge 163:e59c8e839560 123 * @brief TIM Break input(s) and Dead time configuration Structure definition
AnnaBridge 163:e59c8e839560 124 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
AnnaBridge 163:e59c8e839560 125 * filter and polarity.
AnnaBridge 163:e59c8e839560 126 */
AnnaBridge 163:e59c8e839560 127 typedef struct
AnnaBridge 163:e59c8e839560 128 {
AnnaBridge 163:e59c8e839560 129 uint32_t OffStateRunMode; /*!< TIM off state in run mode
AnnaBridge 163:e59c8e839560 130 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
AnnaBridge 163:e59c8e839560 131 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
AnnaBridge 163:e59c8e839560 132 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
AnnaBridge 163:e59c8e839560 133 uint32_t LockLevel; /*!< TIM Lock level
AnnaBridge 163:e59c8e839560 134 This parameter can be a value of @ref TIM_Lock_level */
AnnaBridge 163:e59c8e839560 135 uint32_t DeadTime; /*!< TIM dead Time
AnnaBridge 163:e59c8e839560 136 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
AnnaBridge 163:e59c8e839560 137 uint32_t BreakState; /*!< TIM Break State
AnnaBridge 163:e59c8e839560 138 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
AnnaBridge 163:e59c8e839560 139 uint32_t BreakPolarity; /*!< TIM Break input polarity
AnnaBridge 163:e59c8e839560 140 This parameter can be a value of @ref TIM_Break_Polarity */
AnnaBridge 163:e59c8e839560 141 uint32_t BreakFilter; /*!< Specifies the brek input filter.
AnnaBridge 163:e59c8e839560 142 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
AnnaBridge 163:e59c8e839560 143 uint32_t Break2State; /*!< TIM Break2 State
AnnaBridge 163:e59c8e839560 144 This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
AnnaBridge 163:e59c8e839560 145 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
AnnaBridge 163:e59c8e839560 146 This parameter can be a value of @ref TIMEx_Break2_Polarity */
AnnaBridge 163:e59c8e839560 147 uint32_t Break2Filter; /*!< TIM break2 input filter.
AnnaBridge 163:e59c8e839560 148 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
AnnaBridge 163:e59c8e839560 149 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
AnnaBridge 163:e59c8e839560 150 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
AnnaBridge 163:e59c8e839560 151 } TIM_BreakDeadTimeConfigTypeDef;
AnnaBridge 163:e59c8e839560 152
AnnaBridge 163:e59c8e839560 153 /**
AnnaBridge 163:e59c8e839560 154 * @brief TIM Master configuration Structure definition
AnnaBridge 163:e59c8e839560 155 * @note Advanced timers provide TRGO2 internal line which is redirected
AnnaBridge 163:e59c8e839560 156 * to the ADC
AnnaBridge 163:e59c8e839560 157 */
AnnaBridge 163:e59c8e839560 158 typedef struct {
AnnaBridge 163:e59c8e839560 159 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
AnnaBridge 163:e59c8e839560 160 This parameter can be a value of @ref TIM_Master_Mode_Selection */
AnnaBridge 163:e59c8e839560 161 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
AnnaBridge 163:e59c8e839560 162 This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
AnnaBridge 163:e59c8e839560 163 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
AnnaBridge 163:e59c8e839560 164 This parameter can be a value of @ref TIM_Master_Slave_Mode */
AnnaBridge 163:e59c8e839560 165 }TIM_MasterConfigTypeDef;
AnnaBridge 163:e59c8e839560 166 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 163:e59c8e839560 167 /* STM32F302xC || STM32F303xC || STM32F358xx || */
AnnaBridge 163:e59c8e839560 168 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 163:e59c8e839560 169 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 163:e59c8e839560 170 /**
AnnaBridge 163:e59c8e839560 171 * @}
AnnaBridge 163:e59c8e839560 172 */
AnnaBridge 163:e59c8e839560 173
AnnaBridge 163:e59c8e839560 174 /* Exported constants --------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 175 /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
AnnaBridge 163:e59c8e839560 176 * @{
AnnaBridge 163:e59c8e839560 177 */
AnnaBridge 163:e59c8e839560 178
AnnaBridge 163:e59c8e839560 179 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 163:e59c8e839560 180 /** @defgroup TIMEx_Channel TIMEx Channel
AnnaBridge 163:e59c8e839560 181 * @{
AnnaBridge 163:e59c8e839560 182 */
AnnaBridge 163:e59c8e839560 183 #define TIM_CHANNEL_1 (0x0000U)
AnnaBridge 163:e59c8e839560 184 #define TIM_CHANNEL_2 (0x0004U)
AnnaBridge 163:e59c8e839560 185 #define TIM_CHANNEL_3 (0x0008U)
AnnaBridge 163:e59c8e839560 186 #define TIM_CHANNEL_4 (0x000CU)
AnnaBridge 163:e59c8e839560 187 #define TIM_CHANNEL_ALL (0x0018U)
AnnaBridge 163:e59c8e839560 188 /**
AnnaBridge 163:e59c8e839560 189 * @}
AnnaBridge 163:e59c8e839560 190 */
AnnaBridge 163:e59c8e839560 191
AnnaBridge 163:e59c8e839560 192 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
AnnaBridge 163:e59c8e839560 193 * @{
AnnaBridge 163:e59c8e839560 194 */
AnnaBridge 163:e59c8e839560 195 #define TIM_OCMODE_TIMING (0x0000U)
AnnaBridge 163:e59c8e839560 196 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
AnnaBridge 163:e59c8e839560 197 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
AnnaBridge 163:e59c8e839560 198 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
AnnaBridge 163:e59c8e839560 199 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
AnnaBridge 163:e59c8e839560 200 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
AnnaBridge 163:e59c8e839560 201 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
AnnaBridge 163:e59c8e839560 202 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
AnnaBridge 163:e59c8e839560 203 /**
AnnaBridge 163:e59c8e839560 204 * @}
AnnaBridge 163:e59c8e839560 205 */
AnnaBridge 163:e59c8e839560 206
AnnaBridge 163:e59c8e839560 207 /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
AnnaBridge 163:e59c8e839560 208 * @{
AnnaBridge 163:e59c8e839560 209 */
AnnaBridge 163:e59c8e839560 210 #define TIM_CLEARINPUTSOURCE_ETR (0x0001U)
AnnaBridge 163:e59c8e839560 211 #define TIM_CLEARINPUTSOURCE_NONE (0x0000U)
AnnaBridge 163:e59c8e839560 212 /**
AnnaBridge 163:e59c8e839560 213 * @}
AnnaBridge 163:e59c8e839560 214 */
AnnaBridge 163:e59c8e839560 215
AnnaBridge 163:e59c8e839560 216 /** @defgroup TIMEx_Slave_Mode TIMEx Slave Mode
AnnaBridge 163:e59c8e839560 217 * @{
AnnaBridge 163:e59c8e839560 218 */
AnnaBridge 163:e59c8e839560 219 #define TIM_SLAVEMODE_DISABLE (0x0000U)
AnnaBridge 163:e59c8e839560 220 #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
AnnaBridge 163:e59c8e839560 221 #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
AnnaBridge 163:e59c8e839560 222 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
AnnaBridge 163:e59c8e839560 223 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
AnnaBridge 163:e59c8e839560 224 /**
AnnaBridge 163:e59c8e839560 225 * @}
AnnaBridge 163:e59c8e839560 226 */
AnnaBridge 163:e59c8e839560 227
AnnaBridge 163:e59c8e839560 228 /** @defgroup TIMEx_Event_Source TIMEx Event Source
AnnaBridge 163:e59c8e839560 229 * @{
AnnaBridge 163:e59c8e839560 230 */
AnnaBridge 163:e59c8e839560 231 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
AnnaBridge 163:e59c8e839560 232 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1U */
AnnaBridge 163:e59c8e839560 233 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2U */
AnnaBridge 163:e59c8e839560 234 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3U */
AnnaBridge 163:e59c8e839560 235 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4U */
AnnaBridge 163:e59c8e839560 236 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
AnnaBridge 163:e59c8e839560 237 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
AnnaBridge 163:e59c8e839560 238 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
AnnaBridge 163:e59c8e839560 239 /**
AnnaBridge 163:e59c8e839560 240 * @}
AnnaBridge 163:e59c8e839560 241 */
AnnaBridge 163:e59c8e839560 242
AnnaBridge 163:e59c8e839560 243 /** @defgroup TIMEx_DMA_Base_address TIMEx DMA BAse Address
AnnaBridge 163:e59c8e839560 244 * @{
AnnaBridge 163:e59c8e839560 245 */
AnnaBridge 163:e59c8e839560 246 #define TIM_DMABASE_CR1 (0x00000000U)
AnnaBridge 163:e59c8e839560 247 #define TIM_DMABASE_CR2 (0x00000001U)
AnnaBridge 163:e59c8e839560 248 #define TIM_DMABASE_SMCR (0x00000002U)
AnnaBridge 163:e59c8e839560 249 #define TIM_DMABASE_DIER (0x00000003U)
AnnaBridge 163:e59c8e839560 250 #define TIM_DMABASE_SR (0x00000004U)
AnnaBridge 163:e59c8e839560 251 #define TIM_DMABASE_EGR (0x00000005U)
AnnaBridge 163:e59c8e839560 252 #define TIM_DMABASE_CCMR1 (0x00000006U)
AnnaBridge 163:e59c8e839560 253 #define TIM_DMABASE_CCMR2 (0x00000007U)
AnnaBridge 163:e59c8e839560 254 #define TIM_DMABASE_CCER (0x00000008U)
AnnaBridge 163:e59c8e839560 255 #define TIM_DMABASE_CNT (0x00000009U)
AnnaBridge 163:e59c8e839560 256 #define TIM_DMABASE_PSC (0x0000000AU)
AnnaBridge 163:e59c8e839560 257 #define TIM_DMABASE_ARR (0x0000000BU)
AnnaBridge 163:e59c8e839560 258 #define TIM_DMABASE_RCR (0x0000000CU)
AnnaBridge 163:e59c8e839560 259 #define TIM_DMABASE_CCR1 (0x0000000DU)
AnnaBridge 163:e59c8e839560 260 #define TIM_DMABASE_CCR2 (0x0000000EU)
AnnaBridge 163:e59c8e839560 261 #define TIM_DMABASE_CCR3 (0x0000000FU)
AnnaBridge 163:e59c8e839560 262 #define TIM_DMABASE_CCR4 (0x00000010U)
AnnaBridge 163:e59c8e839560 263 #define TIM_DMABASE_BDTR (0x00000011U)
AnnaBridge 163:e59c8e839560 264 #define TIM_DMABASE_DCR (0x00000012U)
AnnaBridge 163:e59c8e839560 265 #define TIM_DMABASE_OR (0x00000013U)
AnnaBridge 163:e59c8e839560 266 /**
AnnaBridge 163:e59c8e839560 267 * @}
AnnaBridge 163:e59c8e839560 268 */
AnnaBridge 163:e59c8e839560 269 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 163:e59c8e839560 270
AnnaBridge 163:e59c8e839560 271 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
AnnaBridge 163:e59c8e839560 272 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
AnnaBridge 163:e59c8e839560 273 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
AnnaBridge 163:e59c8e839560 274 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 163:e59c8e839560 275 /** @defgroup TIMEx_Channel TIMEx Channel
AnnaBridge 163:e59c8e839560 276 * @{
AnnaBridge 163:e59c8e839560 277 */
AnnaBridge 163:e59c8e839560 278 #define TIM_CHANNEL_1 (0x0000U)
AnnaBridge 163:e59c8e839560 279 #define TIM_CHANNEL_2 (0x0004U)
AnnaBridge 163:e59c8e839560 280 #define TIM_CHANNEL_3 (0x0008U)
AnnaBridge 163:e59c8e839560 281 #define TIM_CHANNEL_4 (0x000CU)
AnnaBridge 163:e59c8e839560 282 #define TIM_CHANNEL_5 (0x0010U)
AnnaBridge 163:e59c8e839560 283 #define TIM_CHANNEL_6 (0x0014U)
AnnaBridge 163:e59c8e839560 284 #define TIM_CHANNEL_ALL (0x003CU)
AnnaBridge 163:e59c8e839560 285 /**
AnnaBridge 163:e59c8e839560 286 * @}
AnnaBridge 163:e59c8e839560 287 */
AnnaBridge 163:e59c8e839560 288
AnnaBridge 163:e59c8e839560 289 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
AnnaBridge 163:e59c8e839560 290 * @{
AnnaBridge 163:e59c8e839560 291 */
AnnaBridge 163:e59c8e839560 292 #define TIM_OCMODE_TIMING (0x0000U)
AnnaBridge 163:e59c8e839560 293 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
AnnaBridge 163:e59c8e839560 294 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
AnnaBridge 163:e59c8e839560 295 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
AnnaBridge 163:e59c8e839560 296 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
AnnaBridge 163:e59c8e839560 297 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
AnnaBridge 163:e59c8e839560 298 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
AnnaBridge 163:e59c8e839560 299 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
AnnaBridge 163:e59c8e839560 300
AnnaBridge 163:e59c8e839560 301 #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
AnnaBridge 163:e59c8e839560 302 #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
AnnaBridge 163:e59c8e839560 303 #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
AnnaBridge 163:e59c8e839560 304 #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
AnnaBridge 163:e59c8e839560 305 #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
AnnaBridge 163:e59c8e839560 306 #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
AnnaBridge 163:e59c8e839560 307
AnnaBridge 163:e59c8e839560 308 /**
AnnaBridge 163:e59c8e839560 309 * @}
AnnaBridge 163:e59c8e839560 310 */
AnnaBridge 163:e59c8e839560 311
AnnaBridge 163:e59c8e839560 312 /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
AnnaBridge 163:e59c8e839560 313 * @{
AnnaBridge 163:e59c8e839560 314 */
AnnaBridge 163:e59c8e839560 315 #define TIM_CLEARINPUTSOURCE_ETR (0x0001U)
AnnaBridge 163:e59c8e839560 316 #define TIM_CLEARINPUTSOURCE_OCREFCLR (0x0002U)
AnnaBridge 163:e59c8e839560 317 #define TIM_CLEARINPUTSOURCE_NONE (0x0000U)
AnnaBridge 163:e59c8e839560 318 /**
AnnaBridge 163:e59c8e839560 319 * @}
AnnaBridge 163:e59c8e839560 320 */
AnnaBridge 163:e59c8e839560 321
AnnaBridge 163:e59c8e839560 322 /** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
AnnaBridge 163:e59c8e839560 323 * @{
AnnaBridge 163:e59c8e839560 324 */
AnnaBridge 163:e59c8e839560 325 #define TIM_BREAK2_DISABLE (0x00000000U)
AnnaBridge 163:e59c8e839560 326 #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
AnnaBridge 163:e59c8e839560 327 /**
AnnaBridge 163:e59c8e839560 328 * @}
AnnaBridge 163:e59c8e839560 329 */
AnnaBridge 163:e59c8e839560 330
AnnaBridge 163:e59c8e839560 331 /** @defgroup TIMEx_Break2_Polarity TIMEx Break Input 2 Polarity
AnnaBridge 163:e59c8e839560 332 * @{
AnnaBridge 163:e59c8e839560 333 */
AnnaBridge 163:e59c8e839560 334 #define TIM_BREAK2POLARITY_LOW (0x00000000U)
AnnaBridge 163:e59c8e839560 335 #define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
AnnaBridge 163:e59c8e839560 336 /**
AnnaBridge 163:e59c8e839560 337 * @}
AnnaBridge 163:e59c8e839560 338 */
AnnaBridge 163:e59c8e839560 339
AnnaBridge 163:e59c8e839560 340 /** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
AnnaBridge 163:e59c8e839560 341 * @{
AnnaBridge 163:e59c8e839560 342 */
AnnaBridge 163:e59c8e839560 343 #define TIM_TRGO2_RESET (0x00000000U)
AnnaBridge 163:e59c8e839560 344 #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
AnnaBridge 163:e59c8e839560 345 #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
AnnaBridge 163:e59c8e839560 346 #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
AnnaBridge 163:e59c8e839560 347 #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
AnnaBridge 163:e59c8e839560 348 #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
AnnaBridge 163:e59c8e839560 349 #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
AnnaBridge 163:e59c8e839560 350 #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
AnnaBridge 163:e59c8e839560 351 #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
AnnaBridge 163:e59c8e839560 352 #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
AnnaBridge 163:e59c8e839560 353 #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
AnnaBridge 163:e59c8e839560 354 #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
AnnaBridge 163:e59c8e839560 355 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
AnnaBridge 163:e59c8e839560 356 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
AnnaBridge 163:e59c8e839560 357 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
AnnaBridge 163:e59c8e839560 358 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
AnnaBridge 163:e59c8e839560 359 /**
AnnaBridge 163:e59c8e839560 360 * @}
AnnaBridge 163:e59c8e839560 361 */
AnnaBridge 163:e59c8e839560 362
AnnaBridge 163:e59c8e839560 363 /** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
AnnaBridge 163:e59c8e839560 364 * @{
AnnaBridge 163:e59c8e839560 365 */
AnnaBridge 163:e59c8e839560 366 #define TIM_SLAVEMODE_DISABLE (0x0000U)
AnnaBridge 163:e59c8e839560 367 #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
AnnaBridge 163:e59c8e839560 368 #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
AnnaBridge 163:e59c8e839560 369 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
AnnaBridge 163:e59c8e839560 370 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
AnnaBridge 163:e59c8e839560 371 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
AnnaBridge 163:e59c8e839560 372 /**
AnnaBridge 163:e59c8e839560 373 * @}
AnnaBridge 163:e59c8e839560 374 */
AnnaBridge 163:e59c8e839560 375
AnnaBridge 163:e59c8e839560 376 /** @defgroup TIM_Event_Source TIMEx Event Source
AnnaBridge 163:e59c8e839560 377 * @{
AnnaBridge 163:e59c8e839560 378 */
AnnaBridge 163:e59c8e839560 379 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
AnnaBridge 163:e59c8e839560 380 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1U */
AnnaBridge 163:e59c8e839560 381 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2U */
AnnaBridge 163:e59c8e839560 382 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3U */
AnnaBridge 163:e59c8e839560 383 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4U */
AnnaBridge 163:e59c8e839560 384 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
AnnaBridge 163:e59c8e839560 385 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
AnnaBridge 163:e59c8e839560 386 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
AnnaBridge 163:e59c8e839560 387 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
AnnaBridge 163:e59c8e839560 388 /**
AnnaBridge 163:e59c8e839560 389 * @}
AnnaBridge 163:e59c8e839560 390 */
AnnaBridge 163:e59c8e839560 391
AnnaBridge 163:e59c8e839560 392 /** @defgroup TIM_DMA_Base_address TIMEx DMA Base Address
AnnaBridge 163:e59c8e839560 393 * @{
AnnaBridge 163:e59c8e839560 394 */
AnnaBridge 163:e59c8e839560 395 #define TIM_DMABASE_CR1 (0x00000000U)
AnnaBridge 163:e59c8e839560 396 #define TIM_DMABASE_CR2 (0x00000001U)
AnnaBridge 163:e59c8e839560 397 #define TIM_DMABASE_SMCR (0x00000002U)
AnnaBridge 163:e59c8e839560 398 #define TIM_DMABASE_DIER (0x00000003U)
AnnaBridge 163:e59c8e839560 399 #define TIM_DMABASE_SR (0x00000004U)
AnnaBridge 163:e59c8e839560 400 #define TIM_DMABASE_EGR (0x00000005U)
AnnaBridge 163:e59c8e839560 401 #define TIM_DMABASE_CCMR1 (0x00000006U)
AnnaBridge 163:e59c8e839560 402 #define TIM_DMABASE_CCMR2 (0x00000007U)
AnnaBridge 163:e59c8e839560 403 #define TIM_DMABASE_CCER (0x00000008U)
AnnaBridge 163:e59c8e839560 404 #define TIM_DMABASE_CNT (0x00000009U)
AnnaBridge 163:e59c8e839560 405 #define TIM_DMABASE_PSC (0x0000000AU)
AnnaBridge 163:e59c8e839560 406 #define TIM_DMABASE_ARR (0x0000000BU)
AnnaBridge 163:e59c8e839560 407 #define TIM_DMABASE_RCR (0x0000000CU)
AnnaBridge 163:e59c8e839560 408 #define TIM_DMABASE_CCR1 (0x0000000DU)
AnnaBridge 163:e59c8e839560 409 #define TIM_DMABASE_CCR2 (0x0000000EU)
AnnaBridge 163:e59c8e839560 410 #define TIM_DMABASE_CCR3 (0x0000000FU)
AnnaBridge 163:e59c8e839560 411 #define TIM_DMABASE_CCR4 (0x00000010U)
AnnaBridge 163:e59c8e839560 412 #define TIM_DMABASE_BDTR (0x00000011U)
AnnaBridge 163:e59c8e839560 413 #define TIM_DMABASE_DCR (0x00000012U)
AnnaBridge 163:e59c8e839560 414 #define TIM_DMABASE_CCMR3 (0x00000015U)
AnnaBridge 163:e59c8e839560 415 #define TIM_DMABASE_CCR5 (0x00000016U)
AnnaBridge 163:e59c8e839560 416 #define TIM_DMABASE_CCR6 (0x00000017U)
AnnaBridge 163:e59c8e839560 417 #define TIM_DMABASE_OR (0x00000018U)
AnnaBridge 163:e59c8e839560 418 /**
AnnaBridge 163:e59c8e839560 419 * @}
AnnaBridge 163:e59c8e839560 420 */
AnnaBridge 163:e59c8e839560 421 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 163:e59c8e839560 422 /* STM32F302xC || STM32F303xC || STM32F358xx || */
AnnaBridge 163:e59c8e839560 423 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 163:e59c8e839560 424 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 163:e59c8e839560 425
AnnaBridge 163:e59c8e839560 426 #if defined(STM32F302xE) || \
AnnaBridge 163:e59c8e839560 427 defined(STM32F302xC) || \
AnnaBridge 163:e59c8e839560 428 defined(STM32F303x8) || defined(STM32F328xx) || \
AnnaBridge 163:e59c8e839560 429 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 163:e59c8e839560 430 /** @defgroup TIMEx_Remap TIMEx Remapping
AnnaBridge 163:e59c8e839560 431 * @{
AnnaBridge 163:e59c8e839560 432 */
AnnaBridge 163:e59c8e839560 433 #define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
AnnaBridge 163:e59c8e839560 434 #define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
AnnaBridge 163:e59c8e839560 435 #define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
AnnaBridge 163:e59c8e839560 436 #define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
AnnaBridge 163:e59c8e839560 437 #define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
AnnaBridge 163:e59c8e839560 438 #define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
AnnaBridge 163:e59c8e839560 439 #define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
AnnaBridge 163:e59c8e839560 440 #define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
AnnaBridge 163:e59c8e839560 441 /**
AnnaBridge 163:e59c8e839560 442 * @}
AnnaBridge 163:e59c8e839560 443 */
AnnaBridge 163:e59c8e839560 444 #endif /* STM32F302xE || */
AnnaBridge 163:e59c8e839560 445 /* STM32F302xC || */
AnnaBridge 163:e59c8e839560 446 /* STM32F303x8 || STM32F328xx || */
AnnaBridge 163:e59c8e839560 447 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
AnnaBridge 163:e59c8e839560 448
AnnaBridge 163:e59c8e839560 449
AnnaBridge 163:e59c8e839560 450 #if defined(STM32F334x8)
AnnaBridge 163:e59c8e839560 451 /** @defgroup TIMEx_Remap TIMEx Remapping 1
AnnaBridge 163:e59c8e839560 452 * @{
AnnaBridge 163:e59c8e839560 453 */
AnnaBridge 163:e59c8e839560 454 #define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
AnnaBridge 163:e59c8e839560 455 #define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
AnnaBridge 163:e59c8e839560 456 #define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
AnnaBridge 163:e59c8e839560 457 #define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
AnnaBridge 163:e59c8e839560 458 #define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
AnnaBridge 163:e59c8e839560 459 #define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
AnnaBridge 163:e59c8e839560 460 #define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
AnnaBridge 163:e59c8e839560 461 #define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
AnnaBridge 163:e59c8e839560 462 /**
AnnaBridge 163:e59c8e839560 463 * @}
AnnaBridge 163:e59c8e839560 464 */
AnnaBridge 163:e59c8e839560 465
AnnaBridge 163:e59c8e839560 466 /** @defgroup TIMEx_Remap2 TIMEx Remapping 2
AnnaBridge 163:e59c8e839560 467 * @{
AnnaBridge 163:e59c8e839560 468 */
AnnaBridge 163:e59c8e839560 469 #define TIM_TIM1_ADC2_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
AnnaBridge 163:e59c8e839560 470 #define TIM_TIM1_ADC2_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC2 AWD1 */
AnnaBridge 163:e59c8e839560 471 #define TIM_TIM1_ADC2_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC2 AWD2 */
AnnaBridge 163:e59c8e839560 472 #define TIM_TIM1_ADC2_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC2 AWD3 */
AnnaBridge 163:e59c8e839560 473 #define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */
AnnaBridge 163:e59c8e839560 474 /**
AnnaBridge 163:e59c8e839560 475 * @}
AnnaBridge 163:e59c8e839560 476 */
AnnaBridge 163:e59c8e839560 477 #endif /* STM32F334x8 */
AnnaBridge 163:e59c8e839560 478
AnnaBridge 163:e59c8e839560 479 #if defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 163:e59c8e839560 480 /** @defgroup TIMEx_Remap TIMEx Remapping 1
AnnaBridge 163:e59c8e839560 481 * @{
AnnaBridge 163:e59c8e839560 482 */
AnnaBridge 163:e59c8e839560 483 #define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
AnnaBridge 163:e59c8e839560 484 #define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
AnnaBridge 163:e59c8e839560 485 #define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
AnnaBridge 163:e59c8e839560 486 #define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
AnnaBridge 163:e59c8e839560 487 #define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
AnnaBridge 163:e59c8e839560 488 #define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */
AnnaBridge 163:e59c8e839560 489 #define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */
AnnaBridge 163:e59c8e839560 490 #define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */
AnnaBridge 163:e59c8e839560 491 #define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
AnnaBridge 163:e59c8e839560 492 #define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
AnnaBridge 163:e59c8e839560 493 #define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
AnnaBridge 163:e59c8e839560 494 #define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
AnnaBridge 163:e59c8e839560 495 /**
AnnaBridge 163:e59c8e839560 496 * @}
AnnaBridge 163:e59c8e839560 497 */
AnnaBridge 163:e59c8e839560 498
AnnaBridge 163:e59c8e839560 499 /** @defgroup TIMEx_Remap2 TIMEx Remapping 2
AnnaBridge 163:e59c8e839560 500 * @{
AnnaBridge 163:e59c8e839560 501 */
AnnaBridge 163:e59c8e839560 502 #define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
AnnaBridge 163:e59c8e839560 503 #define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */
AnnaBridge 163:e59c8e839560 504 #define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */
AnnaBridge 163:e59c8e839560 505 #define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */
AnnaBridge 163:e59c8e839560 506 #define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
AnnaBridge 163:e59c8e839560 507 #define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */
AnnaBridge 163:e59c8e839560 508 #define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */
AnnaBridge 163:e59c8e839560 509 #define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */
AnnaBridge 163:e59c8e839560 510 #define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */
AnnaBridge 163:e59c8e839560 511 /**
AnnaBridge 163:e59c8e839560 512 * @}
AnnaBridge 163:e59c8e839560 513 */
AnnaBridge 163:e59c8e839560 514 #endif /* STM32F303xC || STM32F358xx */
AnnaBridge 163:e59c8e839560 515
AnnaBridge 163:e59c8e839560 516 #if defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 163:e59c8e839560 517 /** @defgroup TIMEx_Remap TIMEx Remapping 1
AnnaBridge 163:e59c8e839560 518 * @{
AnnaBridge 163:e59c8e839560 519 */
AnnaBridge 163:e59c8e839560 520 #define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
AnnaBridge 163:e59c8e839560 521 #define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
AnnaBridge 163:e59c8e839560 522 #define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
AnnaBridge 163:e59c8e839560 523 #define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
AnnaBridge 163:e59c8e839560 524 #define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
AnnaBridge 163:e59c8e839560 525 #define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */
AnnaBridge 163:e59c8e839560 526 #define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */
AnnaBridge 163:e59c8e839560 527 #define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */
AnnaBridge 163:e59c8e839560 528 #define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
AnnaBridge 163:e59c8e839560 529 #define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
AnnaBridge 163:e59c8e839560 530 #define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
AnnaBridge 163:e59c8e839560 531 #define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
AnnaBridge 163:e59c8e839560 532 #define TIM_TIM20_ADC3_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
AnnaBridge 163:e59c8e839560 533 #define TIM_TIM20_ADC3_AWD1 (0x00000001U) /*!< TIM20_ETR is connected to ADC3 AWD1 */
AnnaBridge 163:e59c8e839560 534 #define TIM_TIM20_ADC3_AWD2 (0x00000002U) /*!< TIM20_ETR is connected to ADC3 AWD2 */
AnnaBridge 163:e59c8e839560 535 #define TIM_TIM20_ADC3_AWD3 (0x00000003U) /*!< TIM20_ETR is connected to ADC3 AWD3 */
AnnaBridge 163:e59c8e839560 536 /**
AnnaBridge 163:e59c8e839560 537 * @}
AnnaBridge 163:e59c8e839560 538 */
AnnaBridge 163:e59c8e839560 539
AnnaBridge 163:e59c8e839560 540 /** @defgroup TIMEx_Remap2 TIMEx Remapping 2
AnnaBridge 163:e59c8e839560 541 * @{
AnnaBridge 163:e59c8e839560 542 */
AnnaBridge 163:e59c8e839560 543 #define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
AnnaBridge 163:e59c8e839560 544 #define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */
AnnaBridge 163:e59c8e839560 545 #define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */
AnnaBridge 163:e59c8e839560 546 #define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */
AnnaBridge 163:e59c8e839560 547 #define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
AnnaBridge 163:e59c8e839560 548 #define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */
AnnaBridge 163:e59c8e839560 549 #define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */
AnnaBridge 163:e59c8e839560 550 #define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */
AnnaBridge 163:e59c8e839560 551 #define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */
AnnaBridge 163:e59c8e839560 552 #define TIM_TIM20_ADC4_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
AnnaBridge 163:e59c8e839560 553 #define TIM_TIM20_ADC4_AWD1 (0x00000004U) /*!< TIM20_ETR is connected to ADC4 AWD1 */
AnnaBridge 163:e59c8e839560 554 #define TIM_TIM20_ADC4_AWD2 (0x00000008U) /*!< TIM20_ETR is connected to ADC4 AWD2 */
AnnaBridge 163:e59c8e839560 555 #define TIM_TIM20_ADC4_AWD3 (0x0000000CU) /*!< TIM20_ETR is connected to ADC4 AWD3 */
AnnaBridge 163:e59c8e839560 556 /**
AnnaBridge 163:e59c8e839560 557 * @}
AnnaBridge 163:e59c8e839560 558 */
AnnaBridge 163:e59c8e839560 559 #endif /* STM32F303xE || STM32F398xx */
AnnaBridge 163:e59c8e839560 560
AnnaBridge 163:e59c8e839560 561
AnnaBridge 163:e59c8e839560 562 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 163:e59c8e839560 563 /** @defgroup TIMEx_Remap TIMEx remapping
AnnaBridge 163:e59c8e839560 564 * @{
AnnaBridge 163:e59c8e839560 565 */
AnnaBridge 163:e59c8e839560 566 #define TIM_TIM2_TIM8_TRGO (0x00000000U) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */
AnnaBridge 163:e59c8e839560 567 #define TIM_TIM2_ETH_PTP (0x00000400U) /*!< PTP trigger output is connected to TIM2_ITR1 */
AnnaBridge 163:e59c8e839560 568 #define TIM_TIM2_USBFS_SOF (0x00000800U) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */
AnnaBridge 163:e59c8e839560 569 #define TIM_TIM2_USBHS_SOF (0x00000C00U) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */
AnnaBridge 163:e59c8e839560 570 #define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */
AnnaBridge 163:e59c8e839560 571 #define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */
AnnaBridge 163:e59c8e839560 572 #define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */
AnnaBridge 163:e59c8e839560 573 #define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */
AnnaBridge 163:e59c8e839560 574 /**
AnnaBridge 163:e59c8e839560 575 * @}
AnnaBridge 163:e59c8e839560 576 */
AnnaBridge 163:e59c8e839560 577 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 163:e59c8e839560 578
AnnaBridge 163:e59c8e839560 579 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
AnnaBridge 163:e59c8e839560 580 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
AnnaBridge 163:e59c8e839560 581 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
AnnaBridge 163:e59c8e839560 582 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 163:e59c8e839560 583 /** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1U, 2 or 3
AnnaBridge 163:e59c8e839560 584 * @{
AnnaBridge 163:e59c8e839560 585 */
AnnaBridge 163:e59c8e839560 586 #define TIM_GROUPCH5_NONE 0x00000000 /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
AnnaBridge 163:e59c8e839560 587 #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
AnnaBridge 163:e59c8e839560 588 #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
AnnaBridge 163:e59c8e839560 589 #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
AnnaBridge 163:e59c8e839560 590 /**
AnnaBridge 163:e59c8e839560 591 * @}
AnnaBridge 163:e59c8e839560 592 */
AnnaBridge 163:e59c8e839560 593 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 163:e59c8e839560 594 /* STM32F302xC || STM32F303xC || STM32F358xx || */
AnnaBridge 163:e59c8e839560 595 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 163:e59c8e839560 596 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 163:e59c8e839560 597
AnnaBridge 163:e59c8e839560 598 /**
AnnaBridge 163:e59c8e839560 599 * @}
AnnaBridge 163:e59c8e839560 600 */
AnnaBridge 163:e59c8e839560 601
AnnaBridge 163:e59c8e839560 602
AnnaBridge 163:e59c8e839560 603 /* Private Macros -----------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 604 /** @defgroup TIM_Private_Macros TIM Private Macros
AnnaBridge 163:e59c8e839560 605 * @{
AnnaBridge 163:e59c8e839560 606 */
AnnaBridge 163:e59c8e839560 607 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 163:e59c8e839560 608
AnnaBridge 163:e59c8e839560 609 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 163:e59c8e839560 610 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 163:e59c8e839560 611 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 163:e59c8e839560 612 ((CHANNEL) == TIM_CHANNEL_4) || \
AnnaBridge 163:e59c8e839560 613 ((CHANNEL) == TIM_CHANNEL_ALL))
AnnaBridge 163:e59c8e839560 614
AnnaBridge 163:e59c8e839560 615 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 163:e59c8e839560 616 ((CHANNEL) == TIM_CHANNEL_2))
AnnaBridge 163:e59c8e839560 617
AnnaBridge 163:e59c8e839560 618 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 163:e59c8e839560 619 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 163:e59c8e839560 620 ((CHANNEL) == TIM_CHANNEL_3))
AnnaBridge 163:e59c8e839560 621
AnnaBridge 163:e59c8e839560 622 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
AnnaBridge 163:e59c8e839560 623 ((MODE) == TIM_OCMODE_PWM2))
AnnaBridge 163:e59c8e839560 624
AnnaBridge 163:e59c8e839560 625 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
AnnaBridge 163:e59c8e839560 626 ((MODE) == TIM_OCMODE_ACTIVE) || \
AnnaBridge 163:e59c8e839560 627 ((MODE) == TIM_OCMODE_INACTIVE) || \
AnnaBridge 163:e59c8e839560 628 ((MODE) == TIM_OCMODE_TOGGLE) || \
AnnaBridge 163:e59c8e839560 629 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
AnnaBridge 163:e59c8e839560 630 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
AnnaBridge 163:e59c8e839560 631
AnnaBridge 163:e59c8e839560 632 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
AnnaBridge 163:e59c8e839560 633 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
AnnaBridge 163:e59c8e839560 634
AnnaBridge 163:e59c8e839560 635 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
AnnaBridge 163:e59c8e839560 636 ((MODE) == TIM_SLAVEMODE_RESET) || \
AnnaBridge 163:e59c8e839560 637 ((MODE) == TIM_SLAVEMODE_GATED) || \
AnnaBridge 163:e59c8e839560 638 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
AnnaBridge 163:e59c8e839560 639 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
AnnaBridge 163:e59c8e839560 640
AnnaBridge 163:e59c8e839560 641 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
AnnaBridge 163:e59c8e839560 642
AnnaBridge 163:e59c8e839560 643 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
AnnaBridge 163:e59c8e839560 644 ((BASE) == TIM_DMABASE_CR2) || \
AnnaBridge 163:e59c8e839560 645 ((BASE) == TIM_DMABASE_SMCR) || \
AnnaBridge 163:e59c8e839560 646 ((BASE) == TIM_DMABASE_DIER) || \
AnnaBridge 163:e59c8e839560 647 ((BASE) == TIM_DMABASE_SR) || \
AnnaBridge 163:e59c8e839560 648 ((BASE) == TIM_DMABASE_EGR) || \
AnnaBridge 163:e59c8e839560 649 ((BASE) == TIM_DMABASE_CCMR1) || \
AnnaBridge 163:e59c8e839560 650 ((BASE) == TIM_DMABASE_CCMR2) || \
AnnaBridge 163:e59c8e839560 651 ((BASE) == TIM_DMABASE_CCER) || \
AnnaBridge 163:e59c8e839560 652 ((BASE) == TIM_DMABASE_CNT) || \
AnnaBridge 163:e59c8e839560 653 ((BASE) == TIM_DMABASE_PSC) || \
AnnaBridge 163:e59c8e839560 654 ((BASE) == TIM_DMABASE_ARR) || \
AnnaBridge 163:e59c8e839560 655 ((BASE) == TIM_DMABASE_RCR) || \
AnnaBridge 163:e59c8e839560 656 ((BASE) == TIM_DMABASE_CCR1) || \
AnnaBridge 163:e59c8e839560 657 ((BASE) == TIM_DMABASE_CCR2) || \
AnnaBridge 163:e59c8e839560 658 ((BASE) == TIM_DMABASE_CCR3) || \
AnnaBridge 163:e59c8e839560 659 ((BASE) == TIM_DMABASE_CCR4) || \
AnnaBridge 163:e59c8e839560 660 ((BASE) == TIM_DMABASE_BDTR) || \
AnnaBridge 163:e59c8e839560 661 ((BASE) == TIM_DMABASE_DCR) || \
AnnaBridge 163:e59c8e839560 662 ((BASE) == TIM_DMABASE_OR))
AnnaBridge 163:e59c8e839560 663
AnnaBridge 163:e59c8e839560 664 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 163:e59c8e839560 665
AnnaBridge 163:e59c8e839560 666
AnnaBridge 163:e59c8e839560 667
AnnaBridge 163:e59c8e839560 668 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
AnnaBridge 163:e59c8e839560 669 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
AnnaBridge 163:e59c8e839560 670 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
AnnaBridge 163:e59c8e839560 671 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 163:e59c8e839560 672
AnnaBridge 163:e59c8e839560 673 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 163:e59c8e839560 674 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 163:e59c8e839560 675 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 163:e59c8e839560 676 ((CHANNEL) == TIM_CHANNEL_4) || \
AnnaBridge 163:e59c8e839560 677 ((CHANNEL) == TIM_CHANNEL_5) || \
AnnaBridge 163:e59c8e839560 678 ((CHANNEL) == TIM_CHANNEL_6) || \
AnnaBridge 163:e59c8e839560 679 ((CHANNEL) == TIM_CHANNEL_ALL))
AnnaBridge 163:e59c8e839560 680
AnnaBridge 163:e59c8e839560 681 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 163:e59c8e839560 682 ((CHANNEL) == TIM_CHANNEL_2))
AnnaBridge 163:e59c8e839560 683
AnnaBridge 163:e59c8e839560 684 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 163:e59c8e839560 685 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 163:e59c8e839560 686 ((CHANNEL) == TIM_CHANNEL_3))
AnnaBridge 163:e59c8e839560 687
AnnaBridge 163:e59c8e839560 688 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
AnnaBridge 163:e59c8e839560 689 ((MODE) == TIM_OCMODE_PWM2) || \
AnnaBridge 163:e59c8e839560 690 ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
AnnaBridge 163:e59c8e839560 691 ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
AnnaBridge 163:e59c8e839560 692 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
AnnaBridge 163:e59c8e839560 693 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
AnnaBridge 163:e59c8e839560 694
AnnaBridge 163:e59c8e839560 695 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
AnnaBridge 163:e59c8e839560 696 ((MODE) == TIM_OCMODE_ACTIVE) || \
AnnaBridge 163:e59c8e839560 697 ((MODE) == TIM_OCMODE_INACTIVE) || \
AnnaBridge 163:e59c8e839560 698 ((MODE) == TIM_OCMODE_TOGGLE) || \
AnnaBridge 163:e59c8e839560 699 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
AnnaBridge 163:e59c8e839560 700 ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
AnnaBridge 163:e59c8e839560 701 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
AnnaBridge 163:e59c8e839560 702 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
AnnaBridge 163:e59c8e839560 703
AnnaBridge 163:e59c8e839560 704 #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
AnnaBridge 163:e59c8e839560 705 ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
AnnaBridge 163:e59c8e839560 706 ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
AnnaBridge 163:e59c8e839560 707
AnnaBridge 163:e59c8e839560 708 #define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xFU)
AnnaBridge 163:e59c8e839560 709
AnnaBridge 163:e59c8e839560 710 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
AnnaBridge 163:e59c8e839560 711 ((STATE) == TIM_BREAK2_DISABLE))
AnnaBridge 163:e59c8e839560 712
AnnaBridge 163:e59c8e839560 713 #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) || \
AnnaBridge 163:e59c8e839560 714 ((POLARITY) == TIM_BREAK2POLARITY_HIGH))
AnnaBridge 163:e59c8e839560 715
AnnaBridge 163:e59c8e839560 716 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
AnnaBridge 163:e59c8e839560 717 ((SOURCE) == TIM_TRGO2_ENABLE) || \
AnnaBridge 163:e59c8e839560 718 ((SOURCE) == TIM_TRGO2_UPDATE) || \
AnnaBridge 163:e59c8e839560 719 ((SOURCE) == TIM_TRGO2_OC1) || \
AnnaBridge 163:e59c8e839560 720 ((SOURCE) == TIM_TRGO2_OC1REF) || \
AnnaBridge 163:e59c8e839560 721 ((SOURCE) == TIM_TRGO2_OC2REF) || \
AnnaBridge 163:e59c8e839560 722 ((SOURCE) == TIM_TRGO2_OC3REF) || \
AnnaBridge 163:e59c8e839560 723 ((SOURCE) == TIM_TRGO2_OC3REF) || \
AnnaBridge 163:e59c8e839560 724 ((SOURCE) == TIM_TRGO2_OC4REF) || \
AnnaBridge 163:e59c8e839560 725 ((SOURCE) == TIM_TRGO2_OC5REF) || \
AnnaBridge 163:e59c8e839560 726 ((SOURCE) == TIM_TRGO2_OC6REF) || \
AnnaBridge 163:e59c8e839560 727 ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
AnnaBridge 163:e59c8e839560 728 ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
AnnaBridge 163:e59c8e839560 729 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
AnnaBridge 163:e59c8e839560 730 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
AnnaBridge 163:e59c8e839560 731 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
AnnaBridge 163:e59c8e839560 732 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
AnnaBridge 163:e59c8e839560 733
AnnaBridge 163:e59c8e839560 734 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
AnnaBridge 163:e59c8e839560 735 ((MODE) == TIM_SLAVEMODE_RESET) || \
AnnaBridge 163:e59c8e839560 736 ((MODE) == TIM_SLAVEMODE_GATED) || \
AnnaBridge 163:e59c8e839560 737 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
AnnaBridge 163:e59c8e839560 738 ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
AnnaBridge 163:e59c8e839560 739 ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
AnnaBridge 163:e59c8e839560 740
AnnaBridge 163:e59c8e839560 741 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
AnnaBridge 163:e59c8e839560 742
AnnaBridge 163:e59c8e839560 743 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
AnnaBridge 163:e59c8e839560 744 ((BASE) == TIM_DMABASE_CR2) || \
AnnaBridge 163:e59c8e839560 745 ((BASE) == TIM_DMABASE_SMCR) || \
AnnaBridge 163:e59c8e839560 746 ((BASE) == TIM_DMABASE_DIER) || \
AnnaBridge 163:e59c8e839560 747 ((BASE) == TIM_DMABASE_SR) || \
AnnaBridge 163:e59c8e839560 748 ((BASE) == TIM_DMABASE_EGR) || \
AnnaBridge 163:e59c8e839560 749 ((BASE) == TIM_DMABASE_CCMR1) || \
AnnaBridge 163:e59c8e839560 750 ((BASE) == TIM_DMABASE_CCMR2) || \
AnnaBridge 163:e59c8e839560 751 ((BASE) == TIM_DMABASE_CCER) || \
AnnaBridge 163:e59c8e839560 752 ((BASE) == TIM_DMABASE_CNT) || \
AnnaBridge 163:e59c8e839560 753 ((BASE) == TIM_DMABASE_PSC) || \
AnnaBridge 163:e59c8e839560 754 ((BASE) == TIM_DMABASE_ARR) || \
AnnaBridge 163:e59c8e839560 755 ((BASE) == TIM_DMABASE_RCR) || \
AnnaBridge 163:e59c8e839560 756 ((BASE) == TIM_DMABASE_CCR1) || \
AnnaBridge 163:e59c8e839560 757 ((BASE) == TIM_DMABASE_CCR2) || \
AnnaBridge 163:e59c8e839560 758 ((BASE) == TIM_DMABASE_CCR3) || \
AnnaBridge 163:e59c8e839560 759 ((BASE) == TIM_DMABASE_CCR4) || \
AnnaBridge 163:e59c8e839560 760 ((BASE) == TIM_DMABASE_BDTR) || \
AnnaBridge 163:e59c8e839560 761 ((BASE) == TIM_DMABASE_CCMR3) || \
AnnaBridge 163:e59c8e839560 762 ((BASE) == TIM_DMABASE_CCR5) || \
AnnaBridge 163:e59c8e839560 763 ((BASE) == TIM_DMABASE_CCR6) || \
AnnaBridge 163:e59c8e839560 764 ((BASE) == TIM_DMABASE_OR))
AnnaBridge 163:e59c8e839560 765
AnnaBridge 163:e59c8e839560 766 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 163:e59c8e839560 767 /* STM32F302xC || STM32F303xC || STM32F358xx || */
AnnaBridge 163:e59c8e839560 768 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 163:e59c8e839560 769 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 163:e59c8e839560 770
AnnaBridge 163:e59c8e839560 771 #if defined(STM32F302xE) || \
AnnaBridge 163:e59c8e839560 772 defined(STM32F302xC) || \
AnnaBridge 163:e59c8e839560 773 defined(STM32F303x8) || defined(STM32F328xx) || \
AnnaBridge 163:e59c8e839560 774 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 163:e59c8e839560 775
AnnaBridge 163:e59c8e839560 776 #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
AnnaBridge 163:e59c8e839560 777 ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\
AnnaBridge 163:e59c8e839560 778 ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\
AnnaBridge 163:e59c8e839560 779 ((REMAP) == TIM_TIM1_ADC1_AWD3) ||\
AnnaBridge 163:e59c8e839560 780 ((REMAP) == TIM_TIM16_GPIO) ||\
AnnaBridge 163:e59c8e839560 781 ((REMAP) == TIM_TIM16_RTC) ||\
AnnaBridge 163:e59c8e839560 782 ((REMAP) == TIM_TIM16_HSE) ||\
AnnaBridge 163:e59c8e839560 783 ((REMAP) == TIM_TIM16_MCO))
AnnaBridge 163:e59c8e839560 784
AnnaBridge 163:e59c8e839560 785 #endif /* STM32F302xE || */
AnnaBridge 163:e59c8e839560 786 /* STM32F302xC || */
AnnaBridge 163:e59c8e839560 787 /* STM32F303x8 || STM32F328xx || */
AnnaBridge 163:e59c8e839560 788 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
AnnaBridge 163:e59c8e839560 789
AnnaBridge 163:e59c8e839560 790 #if defined(STM32F334x8)
AnnaBridge 163:e59c8e839560 791 #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
AnnaBridge 163:e59c8e839560 792 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
AnnaBridge 163:e59c8e839560 793 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
AnnaBridge 163:e59c8e839560 794 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
AnnaBridge 163:e59c8e839560 795 ((REMAP1) == TIM_TIM16_GPIO) ||\
AnnaBridge 163:e59c8e839560 796 ((REMAP1) == TIM_TIM16_RTC) ||\
AnnaBridge 163:e59c8e839560 797 ((REMAP1) == TIM_TIM16_HSE) ||\
AnnaBridge 163:e59c8e839560 798 ((REMAP1) == TIM_TIM16_MCO))
AnnaBridge 163:e59c8e839560 799
AnnaBridge 163:e59c8e839560 800 #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC2_NONE) ||\
AnnaBridge 163:e59c8e839560 801 ((REMAP2) == TIM_TIM1_ADC2_AWD1) ||\
AnnaBridge 163:e59c8e839560 802 ((REMAP2) == TIM_TIM1_ADC2_AWD2) ||\
AnnaBridge 163:e59c8e839560 803 ((REMAP2) == TIM_TIM1_ADC2_AWD3) ||\
AnnaBridge 163:e59c8e839560 804 ((REMAP2) == TIM_TIM16_NONE))
AnnaBridge 163:e59c8e839560 805
AnnaBridge 163:e59c8e839560 806 #endif /* STM32F334x8 */
AnnaBridge 163:e59c8e839560 807
AnnaBridge 163:e59c8e839560 808 #if defined(STM32F303xC) || defined(STM32F358xx)
AnnaBridge 163:e59c8e839560 809
AnnaBridge 163:e59c8e839560 810 #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
AnnaBridge 163:e59c8e839560 811 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
AnnaBridge 163:e59c8e839560 812 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
AnnaBridge 163:e59c8e839560 813 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
AnnaBridge 163:e59c8e839560 814 ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
AnnaBridge 163:e59c8e839560 815 ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
AnnaBridge 163:e59c8e839560 816 ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
AnnaBridge 163:e59c8e839560 817 ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
AnnaBridge 163:e59c8e839560 818 ((REMAP1) == TIM_TIM16_GPIO) ||\
AnnaBridge 163:e59c8e839560 819 ((REMAP1) == TIM_TIM16_RTC) ||\
AnnaBridge 163:e59c8e839560 820 ((REMAP1) == TIM_TIM16_HSE) ||\
AnnaBridge 163:e59c8e839560 821 ((REMAP1) == TIM_TIM16_MCO))
AnnaBridge 163:e59c8e839560 822
AnnaBridge 163:e59c8e839560 823 #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
AnnaBridge 163:e59c8e839560 824 ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
AnnaBridge 163:e59c8e839560 825 ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
AnnaBridge 163:e59c8e839560 826 ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
AnnaBridge 163:e59c8e839560 827 ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
AnnaBridge 163:e59c8e839560 828 ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
AnnaBridge 163:e59c8e839560 829 ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
AnnaBridge 163:e59c8e839560 830 ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
AnnaBridge 163:e59c8e839560 831 ((REMAP2) == TIM_TIM16_NONE))
AnnaBridge 163:e59c8e839560 832
AnnaBridge 163:e59c8e839560 833 #endif /* STM32F303xC || STM32F358xx */
AnnaBridge 163:e59c8e839560 834
AnnaBridge 163:e59c8e839560 835 #if defined(STM32F303xE) || defined(STM32F398xx)
AnnaBridge 163:e59c8e839560 836
AnnaBridge 163:e59c8e839560 837 #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
AnnaBridge 163:e59c8e839560 838 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
AnnaBridge 163:e59c8e839560 839 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
AnnaBridge 163:e59c8e839560 840 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
AnnaBridge 163:e59c8e839560 841 ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
AnnaBridge 163:e59c8e839560 842 ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
AnnaBridge 163:e59c8e839560 843 ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
AnnaBridge 163:e59c8e839560 844 ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
AnnaBridge 163:e59c8e839560 845 ((REMAP1) == TIM_TIM16_GPIO) ||\
AnnaBridge 163:e59c8e839560 846 ((REMAP1) == TIM_TIM16_RTC) ||\
AnnaBridge 163:e59c8e839560 847 ((REMAP1) == TIM_TIM16_HSE) ||\
AnnaBridge 163:e59c8e839560 848 ((REMAP1) == TIM_TIM16_MCO) ||\
AnnaBridge 163:e59c8e839560 849 ((REMAP1) == TIM_TIM20_ADC3_NONE) ||\
AnnaBridge 163:e59c8e839560 850 ((REMAP1) == TIM_TIM20_ADC3_AWD1) ||\
AnnaBridge 163:e59c8e839560 851 ((REMAP1) == TIM_TIM20_ADC3_AWD2) ||\
AnnaBridge 163:e59c8e839560 852 ((REMAP1) == TIM_TIM20_ADC3_AWD3))
AnnaBridge 163:e59c8e839560 853
AnnaBridge 163:e59c8e839560 854 #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
AnnaBridge 163:e59c8e839560 855 ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
AnnaBridge 163:e59c8e839560 856 ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
AnnaBridge 163:e59c8e839560 857 ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
AnnaBridge 163:e59c8e839560 858 ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
AnnaBridge 163:e59c8e839560 859 ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
AnnaBridge 163:e59c8e839560 860 ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
AnnaBridge 163:e59c8e839560 861 ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
AnnaBridge 163:e59c8e839560 862 ((REMAP2) == TIM_TIM16_NONE) ||\
AnnaBridge 163:e59c8e839560 863 ((REMAP2) == TIM_TIM20_ADC4_NONE) ||\
AnnaBridge 163:e59c8e839560 864 ((REMAP2) == TIM_TIM20_ADC4_AWD1) ||\
AnnaBridge 163:e59c8e839560 865 ((REMAP2) == TIM_TIM20_ADC4_AWD2) ||\
AnnaBridge 163:e59c8e839560 866 ((REMAP2) == TIM_TIM20_ADC4_AWD3))
AnnaBridge 163:e59c8e839560 867
AnnaBridge 163:e59c8e839560 868 #endif /* STM32F303xE || STM32F398xx */
AnnaBridge 163:e59c8e839560 869
AnnaBridge 163:e59c8e839560 870 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 163:e59c8e839560 871
AnnaBridge 163:e59c8e839560 872 #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) ||\
AnnaBridge 163:e59c8e839560 873 ((REMAP) == TIM_TIM2_ETH_PTP) ||\
AnnaBridge 163:e59c8e839560 874 ((REMAP) == TIM_TIM2_USBFS_SOF) ||\
AnnaBridge 163:e59c8e839560 875 ((REMAP) == TIM_TIM2_USBHS_SOF) ||\
AnnaBridge 163:e59c8e839560 876 ((REMAP) == TIM_TIM14_GPIO) ||\
AnnaBridge 163:e59c8e839560 877 ((REMAP) == TIM_TIM14_RTC) ||\
AnnaBridge 163:e59c8e839560 878 ((REMAP) == TIM_TIM14_HSE) ||\
AnnaBridge 163:e59c8e839560 879 ((REMAP) == TIM_TIM14_MCO))
AnnaBridge 163:e59c8e839560 880
AnnaBridge 163:e59c8e839560 881 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 163:e59c8e839560 882
AnnaBridge 163:e59c8e839560 883
AnnaBridge 163:e59c8e839560 884 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
AnnaBridge 163:e59c8e839560 885 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
AnnaBridge 163:e59c8e839560 886 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
AnnaBridge 163:e59c8e839560 887 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 163:e59c8e839560 888
AnnaBridge 163:e59c8e839560 889 #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFFU) == 0x00000000U))
AnnaBridge 163:e59c8e839560 890
AnnaBridge 163:e59c8e839560 891 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 163:e59c8e839560 892 /* STM32F302xC || STM32F303xC || STM32F358xx || */
AnnaBridge 163:e59c8e839560 893 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 163:e59c8e839560 894 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 163:e59c8e839560 895
AnnaBridge 163:e59c8e839560 896 #define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)
AnnaBridge 163:e59c8e839560 897
AnnaBridge 163:e59c8e839560 898 /**
AnnaBridge 163:e59c8e839560 899 * @}
AnnaBridge 163:e59c8e839560 900 */
AnnaBridge 163:e59c8e839560 901 /* End of private macros -----------------------------------------------------*/
AnnaBridge 163:e59c8e839560 902
AnnaBridge 163:e59c8e839560 903
AnnaBridge 163:e59c8e839560 904 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 905 /** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros
AnnaBridge 163:e59c8e839560 906 * @{
AnnaBridge 163:e59c8e839560 907 */
AnnaBridge 163:e59c8e839560 908
AnnaBridge 163:e59c8e839560 909 #if defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 163:e59c8e839560 910 /**
AnnaBridge 163:e59c8e839560 911 * @brief Sets the TIM Capture Compare Register value on runtime without
AnnaBridge 163:e59c8e839560 912 * calling another time ConfigChannel function.
AnnaBridge 163:e59c8e839560 913 * @param __HANDLE__: TIM handle.
AnnaBridge 163:e59c8e839560 914 * @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge 163:e59c8e839560 915 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 916 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 163:e59c8e839560 917 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 163:e59c8e839560 918 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 163:e59c8e839560 919 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 163:e59c8e839560 920 * @param __COMPARE__: specifies the Capture Compare register new value.
AnnaBridge 163:e59c8e839560 921 * @retval None
AnnaBridge 163:e59c8e839560 922 */
AnnaBridge 163:e59c8e839560 923 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
AnnaBridge 163:e59c8e839560 924 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
AnnaBridge 163:e59c8e839560 925
AnnaBridge 163:e59c8e839560 926 /**
AnnaBridge 163:e59c8e839560 927 * @brief Gets the TIM Capture Compare Register value on runtime
AnnaBridge 163:e59c8e839560 928 * @param __HANDLE__: TIM handle.
AnnaBridge 163:e59c8e839560 929 * @param __CHANNEL__: TIM Channel associated with the capture compare register
AnnaBridge 163:e59c8e839560 930 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 931 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
AnnaBridge 163:e59c8e839560 932 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
AnnaBridge 163:e59c8e839560 933 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
AnnaBridge 163:e59c8e839560 934 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
AnnaBridge 163:e59c8e839560 935 * @retval None
AnnaBridge 163:e59c8e839560 936 */
AnnaBridge 163:e59c8e839560 937 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 938 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
AnnaBridge 163:e59c8e839560 939
AnnaBridge 163:e59c8e839560 940 /**
AnnaBridge 163:e59c8e839560 941 * @brief Sets the TIM Output compare preload.
AnnaBridge 163:e59c8e839560 942 * @param __HANDLE__: TIM handle.
AnnaBridge 163:e59c8e839560 943 * @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge 163:e59c8e839560 944 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 945 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 163:e59c8e839560 946 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 163:e59c8e839560 947 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 163:e59c8e839560 948 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 163:e59c8e839560 949 * @retval None
AnnaBridge 163:e59c8e839560 950 */
AnnaBridge 163:e59c8e839560 951 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 952 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
AnnaBridge 163:e59c8e839560 953 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
AnnaBridge 163:e59c8e839560 954 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
AnnaBridge 163:e59c8e839560 955 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
AnnaBridge 163:e59c8e839560 956
AnnaBridge 163:e59c8e839560 957 /**
AnnaBridge 163:e59c8e839560 958 * @brief Resets the TIM Output compare preload.
AnnaBridge 163:e59c8e839560 959 * @param __HANDLE__: TIM handle.
AnnaBridge 163:e59c8e839560 960 * @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge 163:e59c8e839560 961 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 962 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 163:e59c8e839560 963 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 163:e59c8e839560 964 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 163:e59c8e839560 965 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 163:e59c8e839560 966 * @retval None
AnnaBridge 163:e59c8e839560 967 */
AnnaBridge 163:e59c8e839560 968 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 969 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
AnnaBridge 163:e59c8e839560 970 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
AnnaBridge 163:e59c8e839560 971 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
AnnaBridge 163:e59c8e839560 972 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
AnnaBridge 163:e59c8e839560 973
AnnaBridge 163:e59c8e839560 974 #endif /* STM32F373xC || STM32F378xx */
AnnaBridge 163:e59c8e839560 975
AnnaBridge 163:e59c8e839560 976 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
AnnaBridge 163:e59c8e839560 977 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
AnnaBridge 163:e59c8e839560 978 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
AnnaBridge 163:e59c8e839560 979 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 163:e59c8e839560 980 /**
AnnaBridge 163:e59c8e839560 981 * @brief Sets the TIM Capture Compare Register value on runtime without
AnnaBridge 163:e59c8e839560 982 * calling another time ConfigChannel function.
AnnaBridge 163:e59c8e839560 983 * @param __HANDLE__: TIM handle.
AnnaBridge 163:e59c8e839560 984 * @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge 163:e59c8e839560 985 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 986 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 163:e59c8e839560 987 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 163:e59c8e839560 988 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 163:e59c8e839560 989 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 163:e59c8e839560 990 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
AnnaBridge 163:e59c8e839560 991 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
AnnaBridge 163:e59c8e839560 992 * @param __COMPARE__: specifies the Capture Compare register new value.
AnnaBridge 163:e59c8e839560 993 * @retval None
AnnaBridge 163:e59c8e839560 994 */
AnnaBridge 163:e59c8e839560 995 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
AnnaBridge 163:e59c8e839560 996 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
AnnaBridge 163:e59c8e839560 997 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
AnnaBridge 163:e59c8e839560 998 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
AnnaBridge 163:e59c8e839560 999 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
AnnaBridge 163:e59c8e839560 1000 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
AnnaBridge 163:e59c8e839560 1001 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
AnnaBridge 163:e59c8e839560 1002
AnnaBridge 163:e59c8e839560 1003 /**
AnnaBridge 163:e59c8e839560 1004 * @brief Gets the TIM Capture Compare Register value on runtime
AnnaBridge 163:e59c8e839560 1005 * @param __HANDLE__: TIM handle.
AnnaBridge 163:e59c8e839560 1006 * @param __CHANNEL__: TIM Channel associated with the capture compare register
AnnaBridge 163:e59c8e839560 1007 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1008 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
AnnaBridge 163:e59c8e839560 1009 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
AnnaBridge 163:e59c8e839560 1010 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
AnnaBridge 163:e59c8e839560 1011 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
AnnaBridge 163:e59c8e839560 1012 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
AnnaBridge 163:e59c8e839560 1013 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
AnnaBridge 163:e59c8e839560 1014 * @retval None
AnnaBridge 163:e59c8e839560 1015 */
AnnaBridge 163:e59c8e839560 1016 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 1017 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
AnnaBridge 163:e59c8e839560 1018 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
AnnaBridge 163:e59c8e839560 1019 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
AnnaBridge 163:e59c8e839560 1020 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
AnnaBridge 163:e59c8e839560 1021 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
AnnaBridge 163:e59c8e839560 1022 ((__HANDLE__)->Instance->CCR6))
AnnaBridge 163:e59c8e839560 1023
AnnaBridge 163:e59c8e839560 1024 /**
AnnaBridge 163:e59c8e839560 1025 * @brief Sets the TIM Output compare preload.
AnnaBridge 163:e59c8e839560 1026 * @param __HANDLE__: TIM handle.
AnnaBridge 163:e59c8e839560 1027 * @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge 163:e59c8e839560 1028 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1029 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 163:e59c8e839560 1030 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 163:e59c8e839560 1031 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 163:e59c8e839560 1032 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 163:e59c8e839560 1033 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
AnnaBridge 163:e59c8e839560 1034 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
AnnaBridge 163:e59c8e839560 1035 * @retval None
AnnaBridge 163:e59c8e839560 1036 */
AnnaBridge 163:e59c8e839560 1037 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 1038 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
AnnaBridge 163:e59c8e839560 1039 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
AnnaBridge 163:e59c8e839560 1040 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
AnnaBridge 163:e59c8e839560 1041 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
AnnaBridge 163:e59c8e839560 1042 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
AnnaBridge 163:e59c8e839560 1043 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
AnnaBridge 163:e59c8e839560 1044
AnnaBridge 163:e59c8e839560 1045 /**
AnnaBridge 163:e59c8e839560 1046 * @brief Resets the TIM Output compare preload.
AnnaBridge 163:e59c8e839560 1047 * @param __HANDLE__: TIM handle.
AnnaBridge 163:e59c8e839560 1048 * @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge 163:e59c8e839560 1049 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1050 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 163:e59c8e839560 1051 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 163:e59c8e839560 1052 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 163:e59c8e839560 1053 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 163:e59c8e839560 1054 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
AnnaBridge 163:e59c8e839560 1055 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
AnnaBridge 163:e59c8e839560 1056 * @retval None
AnnaBridge 163:e59c8e839560 1057 */
AnnaBridge 163:e59c8e839560 1058 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 1059 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
AnnaBridge 163:e59c8e839560 1060 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
AnnaBridge 163:e59c8e839560 1061 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
AnnaBridge 163:e59c8e839560 1062 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
AnnaBridge 163:e59c8e839560 1063 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
AnnaBridge 163:e59c8e839560 1064 ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
AnnaBridge 163:e59c8e839560 1065
AnnaBridge 163:e59c8e839560 1066 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 163:e59c8e839560 1067 /* STM32F302xC || STM32F303xC || STM32F358xx || */
AnnaBridge 163:e59c8e839560 1068 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 163:e59c8e839560 1069 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 163:e59c8e839560 1070 /**
AnnaBridge 163:e59c8e839560 1071 * @}
AnnaBridge 163:e59c8e839560 1072 */
AnnaBridge 163:e59c8e839560 1073
AnnaBridge 163:e59c8e839560 1074 /* Exported functions --------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 1075 /** @addtogroup TIMEx_Exported_Functions
AnnaBridge 163:e59c8e839560 1076 * @{
AnnaBridge 163:e59c8e839560 1077 */
AnnaBridge 163:e59c8e839560 1078
AnnaBridge 163:e59c8e839560 1079 /** @addtogroup TIMEx_Exported_Functions_Group1
AnnaBridge 163:e59c8e839560 1080 * @{
AnnaBridge 163:e59c8e839560 1081 */
AnnaBridge 163:e59c8e839560 1082 /* Timer Hall Sensor functions **********************************************/
AnnaBridge 163:e59c8e839560 1083 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
AnnaBridge 163:e59c8e839560 1084 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1085
AnnaBridge 163:e59c8e839560 1086 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1087 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1088
AnnaBridge 163:e59c8e839560 1089 /* Blocking mode: Polling */
AnnaBridge 163:e59c8e839560 1090 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1091 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1092 /* Non-Blocking mode: Interrupt */
AnnaBridge 163:e59c8e839560 1093 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1094 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1095 /* Non-Blocking mode: DMA */
AnnaBridge 163:e59c8e839560 1096 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
AnnaBridge 163:e59c8e839560 1097 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1098 /**
AnnaBridge 163:e59c8e839560 1099 * @}
AnnaBridge 163:e59c8e839560 1100 */
AnnaBridge 163:e59c8e839560 1101
AnnaBridge 163:e59c8e839560 1102 /** @addtogroup TIMEx_Exported_Functions_Group2
AnnaBridge 163:e59c8e839560 1103 * @{
AnnaBridge 163:e59c8e839560 1104 */
AnnaBridge 163:e59c8e839560 1105 /* Timer Complementary Output Compare functions *****************************/
AnnaBridge 163:e59c8e839560 1106 /* Blocking mode: Polling */
AnnaBridge 163:e59c8e839560 1107 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1108 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1109
AnnaBridge 163:e59c8e839560 1110 /* Non-Blocking mode: Interrupt */
AnnaBridge 163:e59c8e839560 1111 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1112 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1113
AnnaBridge 163:e59c8e839560 1114 /* Non-Blocking mode: DMA */
AnnaBridge 163:e59c8e839560 1115 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 163:e59c8e839560 1116 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1117 /**
AnnaBridge 163:e59c8e839560 1118 * @}
AnnaBridge 163:e59c8e839560 1119 */
AnnaBridge 163:e59c8e839560 1120
AnnaBridge 163:e59c8e839560 1121 /** @addtogroup TIMEx_Exported_Functions_Group3
AnnaBridge 163:e59c8e839560 1122 * @{
AnnaBridge 163:e59c8e839560 1123 */
AnnaBridge 163:e59c8e839560 1124 /* Timer Complementary PWM functions ****************************************/
AnnaBridge 163:e59c8e839560 1125 /* Blocking mode: Polling */
AnnaBridge 163:e59c8e839560 1126 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1127 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1128
AnnaBridge 163:e59c8e839560 1129 /* Non-Blocking mode: Interrupt */
AnnaBridge 163:e59c8e839560 1130 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1131 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1132 /* Non-Blocking mode: DMA */
AnnaBridge 163:e59c8e839560 1133 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 163:e59c8e839560 1134 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1135 /**
AnnaBridge 163:e59c8e839560 1136 * @}
AnnaBridge 163:e59c8e839560 1137 */
AnnaBridge 163:e59c8e839560 1138
AnnaBridge 163:e59c8e839560 1139 /** @addtogroup TIMEx_Exported_Functions_Group4
AnnaBridge 163:e59c8e839560 1140 * @{
AnnaBridge 163:e59c8e839560 1141 */
AnnaBridge 163:e59c8e839560 1142 /* Timer Complementary One Pulse functions **********************************/
AnnaBridge 163:e59c8e839560 1143 /* Blocking mode: Polling */
AnnaBridge 163:e59c8e839560 1144 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 163:e59c8e839560 1145 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 163:e59c8e839560 1146
AnnaBridge 163:e59c8e839560 1147 /* Non-Blocking mode: Interrupt */
AnnaBridge 163:e59c8e839560 1148 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 163:e59c8e839560 1149 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 163:e59c8e839560 1150 /**
AnnaBridge 163:e59c8e839560 1151 * @}
AnnaBridge 163:e59c8e839560 1152 */
AnnaBridge 163:e59c8e839560 1153
AnnaBridge 163:e59c8e839560 1154 /** @addtogroup TIMEx_Exported_Functions_Group5
AnnaBridge 163:e59c8e839560 1155 * @{
AnnaBridge 163:e59c8e839560 1156 */
AnnaBridge 163:e59c8e839560 1157 /* Extended Control functions ************************************************/
AnnaBridge 163:e59c8e839560 1158 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
AnnaBridge 163:e59c8e839560 1159 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
AnnaBridge 163:e59c8e839560 1160 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
AnnaBridge 163:e59c8e839560 1161 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
AnnaBridge 163:e59c8e839560 1162 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
AnnaBridge 163:e59c8e839560 1163
AnnaBridge 163:e59c8e839560 1164 #if defined(STM32F303xE) || defined(STM32F398xx) || \
AnnaBridge 163:e59c8e839560 1165 defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F334x8)
AnnaBridge 163:e59c8e839560 1166 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
AnnaBridge 163:e59c8e839560 1167 #endif /* STM32F303xE || STM32F398xx || */
AnnaBridge 163:e59c8e839560 1168 /* STM32F303xC || STM32F358xx */
AnnaBridge 163:e59c8e839560 1169
AnnaBridge 163:e59c8e839560 1170 #if defined(STM32F302xE) || \
AnnaBridge 163:e59c8e839560 1171 defined(STM32F302xC) || \
AnnaBridge 163:e59c8e839560 1172 defined(STM32F303x8) || defined(STM32F328xx) || \
AnnaBridge 163:e59c8e839560 1173 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
AnnaBridge 163:e59c8e839560 1174 defined(STM32F373xC) || defined(STM32F378xx)
AnnaBridge 163:e59c8e839560 1175 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
AnnaBridge 163:e59c8e839560 1176 #endif /* STM32F302xE || */
AnnaBridge 163:e59c8e839560 1177 /* STM32F302xC || */
AnnaBridge 163:e59c8e839560 1178 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 163:e59c8e839560 1179 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
AnnaBridge 163:e59c8e839560 1180 /* STM32F373xC || STM32F378xx */
AnnaBridge 163:e59c8e839560 1181
AnnaBridge 163:e59c8e839560 1182 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
AnnaBridge 163:e59c8e839560 1183 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
AnnaBridge 163:e59c8e839560 1184 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
AnnaBridge 163:e59c8e839560 1185 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
AnnaBridge 163:e59c8e839560 1186 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
AnnaBridge 163:e59c8e839560 1187 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
AnnaBridge 163:e59c8e839560 1188 /* STM32F302xC || STM32F303xC || STM32F358xx || */
AnnaBridge 163:e59c8e839560 1189 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
AnnaBridge 163:e59c8e839560 1190 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
AnnaBridge 163:e59c8e839560 1191 /**
AnnaBridge 163:e59c8e839560 1192 * @}
AnnaBridge 163:e59c8e839560 1193 */
AnnaBridge 163:e59c8e839560 1194
AnnaBridge 163:e59c8e839560 1195 /** @addtogroup TIMEx_Exported_Functions_Group6
AnnaBridge 163:e59c8e839560 1196 * @{
AnnaBridge 163:e59c8e839560 1197 */
AnnaBridge 163:e59c8e839560 1198 /* Extended Callback *********************************************************/
AnnaBridge 163:e59c8e839560 1199 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1200 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1201 /**
AnnaBridge 163:e59c8e839560 1202 * @}
AnnaBridge 163:e59c8e839560 1203 */
AnnaBridge 163:e59c8e839560 1204
AnnaBridge 163:e59c8e839560 1205 /** @addtogroup TIMEx_Exported_Functions_Group7
AnnaBridge 163:e59c8e839560 1206 * @{
AnnaBridge 163:e59c8e839560 1207 */
AnnaBridge 163:e59c8e839560 1208 /* Extended Peripheral State functions **************************************/
AnnaBridge 163:e59c8e839560 1209 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1210 /**
AnnaBridge 163:e59c8e839560 1211 * @}
AnnaBridge 163:e59c8e839560 1212 */
AnnaBridge 163:e59c8e839560 1213
AnnaBridge 163:e59c8e839560 1214 /**
AnnaBridge 163:e59c8e839560 1215 * @}
AnnaBridge 163:e59c8e839560 1216 */
AnnaBridge 163:e59c8e839560 1217 /* End of exported functions -------------------------------------------------*/
AnnaBridge 163:e59c8e839560 1218
AnnaBridge 163:e59c8e839560 1219 /* Private functions----------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 1220 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
AnnaBridge 163:e59c8e839560 1221 * @{
AnnaBridge 163:e59c8e839560 1222 */
AnnaBridge 163:e59c8e839560 1223 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 163:e59c8e839560 1224 /**
AnnaBridge 163:e59c8e839560 1225 * @}
AnnaBridge 163:e59c8e839560 1226 */
AnnaBridge 163:e59c8e839560 1227 /* End of private functions --------------------------------------------------*/
AnnaBridge 163:e59c8e839560 1228
AnnaBridge 163:e59c8e839560 1229 /**
AnnaBridge 163:e59c8e839560 1230 * @}
AnnaBridge 163:e59c8e839560 1231 */
AnnaBridge 163:e59c8e839560 1232
AnnaBridge 163:e59c8e839560 1233 /**
AnnaBridge 163:e59c8e839560 1234 * @}
AnnaBridge 163:e59c8e839560 1235 */
AnnaBridge 163:e59c8e839560 1236
AnnaBridge 163:e59c8e839560 1237 #ifdef __cplusplus
AnnaBridge 163:e59c8e839560 1238 }
AnnaBridge 163:e59c8e839560 1239 #endif
AnnaBridge 163:e59c8e839560 1240
AnnaBridge 163:e59c8e839560 1241
AnnaBridge 163:e59c8e839560 1242 #endif /* __STM32F3xx_HAL_TIM_EX_H */
AnnaBridge 163:e59c8e839560 1243
AnnaBridge 163:e59c8e839560 1244 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/