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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F401RE/core_cm7.h@102:da0ca467f8b5, 2015-07-08 (annotated)

Committer:
Kojto
Date:
Wed Jul 08 11:22:30 2015 +0100
Revision:
102:da0ca467f8b5
Child:
128:9bcdf88f62b0
Release 102 of the mbed library



Changes:

- new platform: MPS2

- K64f - mac address fix

- Freescale Kinetis - Serial NC handling fix

- Asynch constnes fixes

- startup files .s - change extension to .S

- APPNEARME_MICRONFCBOARD rename to MICRONFCBOARD

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 102:da0ca467f8b5 1 /**************************************************************************//**
Kojto 102:da0ca467f8b5 2 * @file core_cm7.h
Kojto 102:da0ca467f8b5 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
Kojto 102:da0ca467f8b5 4 * @version V4.10
Kojto 102:da0ca467f8b5 5 * @date 18. March 2015
Kojto 102:da0ca467f8b5 6 *
Kojto 102:da0ca467f8b5 7 * @note
Kojto 102:da0ca467f8b5 8 *
Kojto 102:da0ca467f8b5 9 ******************************************************************************/
Kojto 102:da0ca467f8b5 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 102:da0ca467f8b5 11
Kojto 102:da0ca467f8b5 12 All rights reserved.
Kojto 102:da0ca467f8b5 13 Redistribution and use in source and binary forms, with or without
Kojto 102:da0ca467f8b5 14 modification, are permitted provided that the following conditions are met:
Kojto 102:da0ca467f8b5 15 - Redistributions of source code must retain the above copyright
Kojto 102:da0ca467f8b5 16 notice, this list of conditions and the following disclaimer.
Kojto 102:da0ca467f8b5 17 - Redistributions in binary form must reproduce the above copyright
Kojto 102:da0ca467f8b5 18 notice, this list of conditions and the following disclaimer in the
Kojto 102:da0ca467f8b5 19 documentation and/or other materials provided with the distribution.
Kojto 102:da0ca467f8b5 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 102:da0ca467f8b5 21 to endorse or promote products derived from this software without
Kojto 102:da0ca467f8b5 22 specific prior written permission.
Kojto 102:da0ca467f8b5 23 *
Kojto 102:da0ca467f8b5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 102:da0ca467f8b5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 102:da0ca467f8b5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 102:da0ca467f8b5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 102:da0ca467f8b5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 102:da0ca467f8b5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 102:da0ca467f8b5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 102:da0ca467f8b5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 102:da0ca467f8b5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 102:da0ca467f8b5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 102:da0ca467f8b5 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 102:da0ca467f8b5 35 ---------------------------------------------------------------------------*/
Kojto 102:da0ca467f8b5 36
Kojto 102:da0ca467f8b5 37
Kojto 102:da0ca467f8b5 38 #if defined ( __ICCARM__ )
Kojto 102:da0ca467f8b5 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 102:da0ca467f8b5 40 #endif
Kojto 102:da0ca467f8b5 41
Kojto 102:da0ca467f8b5 42 #ifndef __CORE_CM7_H_GENERIC
Kojto 102:da0ca467f8b5 43 #define __CORE_CM7_H_GENERIC
Kojto 102:da0ca467f8b5 44
Kojto 102:da0ca467f8b5 45 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 46 extern "C" {
Kojto 102:da0ca467f8b5 47 #endif
Kojto 102:da0ca467f8b5 48
Kojto 102:da0ca467f8b5 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 102:da0ca467f8b5 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 102:da0ca467f8b5 51
Kojto 102:da0ca467f8b5 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 102:da0ca467f8b5 53 Function definitions in header files are used to allow 'inlining'.
Kojto 102:da0ca467f8b5 54
Kojto 102:da0ca467f8b5 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 102:da0ca467f8b5 56 Unions are used for effective representation of core registers.
Kojto 102:da0ca467f8b5 57
Kojto 102:da0ca467f8b5 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 102:da0ca467f8b5 59 Function-like macros are used to allow more efficient code.
Kojto 102:da0ca467f8b5 60 */
Kojto 102:da0ca467f8b5 61
Kojto 102:da0ca467f8b5 62
Kojto 102:da0ca467f8b5 63 /*******************************************************************************
Kojto 102:da0ca467f8b5 64 * CMSIS definitions
Kojto 102:da0ca467f8b5 65 ******************************************************************************/
Kojto 102:da0ca467f8b5 66 /** \ingroup Cortex_M7
Kojto 102:da0ca467f8b5 67 @{
Kojto 102:da0ca467f8b5 68 */
Kojto 102:da0ca467f8b5 69
Kojto 102:da0ca467f8b5 70 /* CMSIS CM7 definitions */
Kojto 102:da0ca467f8b5 71 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 102:da0ca467f8b5 72 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 102:da0ca467f8b5 73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
Kojto 102:da0ca467f8b5 74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 102:da0ca467f8b5 75
Kojto 102:da0ca467f8b5 76 #define __CORTEX_M (0x07) /*!< Cortex-M Core */
Kojto 102:da0ca467f8b5 77
Kojto 102:da0ca467f8b5 78
Kojto 102:da0ca467f8b5 79 #if defined ( __CC_ARM )
Kojto 102:da0ca467f8b5 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 102:da0ca467f8b5 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 102:da0ca467f8b5 82 #define __STATIC_INLINE static __inline
Kojto 102:da0ca467f8b5 83
Kojto 102:da0ca467f8b5 84 #elif defined ( __GNUC__ )
Kojto 102:da0ca467f8b5 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 102:da0ca467f8b5 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 102:da0ca467f8b5 87 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 88
Kojto 102:da0ca467f8b5 89 #elif defined ( __ICCARM__ )
Kojto 102:da0ca467f8b5 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 102:da0ca467f8b5 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 102:da0ca467f8b5 92 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 93
Kojto 102:da0ca467f8b5 94 #elif defined ( __TMS470__ )
Kojto 102:da0ca467f8b5 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 102:da0ca467f8b5 96 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 97
Kojto 102:da0ca467f8b5 98 #elif defined ( __TASKING__ )
Kojto 102:da0ca467f8b5 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 102:da0ca467f8b5 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 102:da0ca467f8b5 101 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 102
Kojto 102:da0ca467f8b5 103 #elif defined ( __CSMC__ )
Kojto 102:da0ca467f8b5 104 #define __packed
Kojto 102:da0ca467f8b5 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 102:da0ca467f8b5 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 102:da0ca467f8b5 107 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 108
Kojto 102:da0ca467f8b5 109 #endif
Kojto 102:da0ca467f8b5 110
Kojto 102:da0ca467f8b5 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 102:da0ca467f8b5 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Kojto 102:da0ca467f8b5 113 */
Kojto 102:da0ca467f8b5 114 #if defined ( __CC_ARM )
Kojto 102:da0ca467f8b5 115 #if defined __TARGET_FPU_VFP
Kojto 102:da0ca467f8b5 116 #if (__FPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 117 #define __FPU_USED 1
Kojto 102:da0ca467f8b5 118 #else
Kojto 102:da0ca467f8b5 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 120 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 121 #endif
Kojto 102:da0ca467f8b5 122 #else
Kojto 102:da0ca467f8b5 123 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 124 #endif
Kojto 102:da0ca467f8b5 125
Kojto 102:da0ca467f8b5 126 #elif defined ( __GNUC__ )
Kojto 102:da0ca467f8b5 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 102:da0ca467f8b5 128 #if (__FPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 129 #define __FPU_USED 1
Kojto 102:da0ca467f8b5 130 #else
Kojto 102:da0ca467f8b5 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 132 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 133 #endif
Kojto 102:da0ca467f8b5 134 #else
Kojto 102:da0ca467f8b5 135 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 136 #endif
Kojto 102:da0ca467f8b5 137
Kojto 102:da0ca467f8b5 138 #elif defined ( __ICCARM__ )
Kojto 102:da0ca467f8b5 139 #if defined __ARMVFP__
Kojto 102:da0ca467f8b5 140 #if (__FPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 141 #define __FPU_USED 1
Kojto 102:da0ca467f8b5 142 #else
Kojto 102:da0ca467f8b5 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 144 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 145 #endif
Kojto 102:da0ca467f8b5 146 #else
Kojto 102:da0ca467f8b5 147 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 148 #endif
Kojto 102:da0ca467f8b5 149
Kojto 102:da0ca467f8b5 150 #elif defined ( __TMS470__ )
Kojto 102:da0ca467f8b5 151 #if defined __TI_VFP_SUPPORT__
Kojto 102:da0ca467f8b5 152 #if (__FPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 153 #define __FPU_USED 1
Kojto 102:da0ca467f8b5 154 #else
Kojto 102:da0ca467f8b5 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 156 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 157 #endif
Kojto 102:da0ca467f8b5 158 #else
Kojto 102:da0ca467f8b5 159 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 160 #endif
Kojto 102:da0ca467f8b5 161
Kojto 102:da0ca467f8b5 162 #elif defined ( __TASKING__ )
Kojto 102:da0ca467f8b5 163 #if defined __FPU_VFP__
Kojto 102:da0ca467f8b5 164 #if (__FPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 165 #define __FPU_USED 1
Kojto 102:da0ca467f8b5 166 #else
Kojto 102:da0ca467f8b5 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 168 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 169 #endif
Kojto 102:da0ca467f8b5 170 #else
Kojto 102:da0ca467f8b5 171 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 172 #endif
Kojto 102:da0ca467f8b5 173
Kojto 102:da0ca467f8b5 174 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 102:da0ca467f8b5 175 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 102:da0ca467f8b5 176 #if (__FPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 177 #define __FPU_USED 1
Kojto 102:da0ca467f8b5 178 #else
Kojto 102:da0ca467f8b5 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 180 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 181 #endif
Kojto 102:da0ca467f8b5 182 #else
Kojto 102:da0ca467f8b5 183 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 184 #endif
Kojto 102:da0ca467f8b5 185 #endif
Kojto 102:da0ca467f8b5 186
Kojto 102:da0ca467f8b5 187 #include <stdint.h> /* standard types definitions */
Kojto 102:da0ca467f8b5 188 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 102:da0ca467f8b5 189 #include <core_cmFunc.h> /* Core Function Access */
Kojto 102:da0ca467f8b5 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Kojto 102:da0ca467f8b5 191
Kojto 102:da0ca467f8b5 192 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 193 }
Kojto 102:da0ca467f8b5 194 #endif
Kojto 102:da0ca467f8b5 195
Kojto 102:da0ca467f8b5 196 #endif /* __CORE_CM7_H_GENERIC */
Kojto 102:da0ca467f8b5 197
Kojto 102:da0ca467f8b5 198 #ifndef __CMSIS_GENERIC
Kojto 102:da0ca467f8b5 199
Kojto 102:da0ca467f8b5 200 #ifndef __CORE_CM7_H_DEPENDANT
Kojto 102:da0ca467f8b5 201 #define __CORE_CM7_H_DEPENDANT
Kojto 102:da0ca467f8b5 202
Kojto 102:da0ca467f8b5 203 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 204 extern "C" {
Kojto 102:da0ca467f8b5 205 #endif
Kojto 102:da0ca467f8b5 206
Kojto 102:da0ca467f8b5 207 /* check device defines and use defaults */
Kojto 102:da0ca467f8b5 208 #if defined __CHECK_DEVICE_DEFINES
Kojto 102:da0ca467f8b5 209 #ifndef __CM7_REV
Kojto 102:da0ca467f8b5 210 #define __CM7_REV 0x0000
Kojto 102:da0ca467f8b5 211 #warning "__CM7_REV not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 212 #endif
Kojto 102:da0ca467f8b5 213
Kojto 102:da0ca467f8b5 214 #ifndef __FPU_PRESENT
Kojto 102:da0ca467f8b5 215 #define __FPU_PRESENT 0
Kojto 102:da0ca467f8b5 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 217 #endif
Kojto 102:da0ca467f8b5 218
Kojto 102:da0ca467f8b5 219 #ifndef __MPU_PRESENT
Kojto 102:da0ca467f8b5 220 #define __MPU_PRESENT 0
Kojto 102:da0ca467f8b5 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 222 #endif
Kojto 102:da0ca467f8b5 223
Kojto 102:da0ca467f8b5 224 #ifndef __ICACHE_PRESENT
Kojto 102:da0ca467f8b5 225 #define __ICACHE_PRESENT 0
Kojto 102:da0ca467f8b5 226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 227 #endif
Kojto 102:da0ca467f8b5 228
Kojto 102:da0ca467f8b5 229 #ifndef __DCACHE_PRESENT
Kojto 102:da0ca467f8b5 230 #define __DCACHE_PRESENT 0
Kojto 102:da0ca467f8b5 231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 232 #endif
Kojto 102:da0ca467f8b5 233
Kojto 102:da0ca467f8b5 234 #ifndef __DTCM_PRESENT
Kojto 102:da0ca467f8b5 235 #define __DTCM_PRESENT 0
Kojto 102:da0ca467f8b5 236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 237 #endif
Kojto 102:da0ca467f8b5 238
Kojto 102:da0ca467f8b5 239 #ifndef __NVIC_PRIO_BITS
Kojto 102:da0ca467f8b5 240 #define __NVIC_PRIO_BITS 3
Kojto 102:da0ca467f8b5 241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 242 #endif
Kojto 102:da0ca467f8b5 243
Kojto 102:da0ca467f8b5 244 #ifndef __Vendor_SysTickConfig
Kojto 102:da0ca467f8b5 245 #define __Vendor_SysTickConfig 0
Kojto 102:da0ca467f8b5 246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 247 #endif
Kojto 102:da0ca467f8b5 248 #endif
Kojto 102:da0ca467f8b5 249
Kojto 102:da0ca467f8b5 250 /* IO definitions (access restrictions to peripheral registers) */
Kojto 102:da0ca467f8b5 251 /**
Kojto 102:da0ca467f8b5 252 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 102:da0ca467f8b5 253
Kojto 102:da0ca467f8b5 254 <strong>IO Type Qualifiers</strong> are used
Kojto 102:da0ca467f8b5 255 \li to specify the access to peripheral variables.
Kojto 102:da0ca467f8b5 256 \li for automatic generation of peripheral register debug information.
Kojto 102:da0ca467f8b5 257 */
Kojto 102:da0ca467f8b5 258 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 259 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 102:da0ca467f8b5 260 #else
Kojto 102:da0ca467f8b5 261 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 102:da0ca467f8b5 262 #endif
Kojto 102:da0ca467f8b5 263 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 102:da0ca467f8b5 264 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 102:da0ca467f8b5 265
Kojto 102:da0ca467f8b5 266 /*@} end of group Cortex_M7 */
Kojto 102:da0ca467f8b5 267
Kojto 102:da0ca467f8b5 268
Kojto 102:da0ca467f8b5 269
Kojto 102:da0ca467f8b5 270 /*******************************************************************************
Kojto 102:da0ca467f8b5 271 * Register Abstraction
Kojto 102:da0ca467f8b5 272 Core Register contain:
Kojto 102:da0ca467f8b5 273 - Core Register
Kojto 102:da0ca467f8b5 274 - Core NVIC Register
Kojto 102:da0ca467f8b5 275 - Core SCB Register
Kojto 102:da0ca467f8b5 276 - Core SysTick Register
Kojto 102:da0ca467f8b5 277 - Core Debug Register
Kojto 102:da0ca467f8b5 278 - Core MPU Register
Kojto 102:da0ca467f8b5 279 - Core FPU Register
Kojto 102:da0ca467f8b5 280 ******************************************************************************/
Kojto 102:da0ca467f8b5 281 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 102:da0ca467f8b5 282 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 102:da0ca467f8b5 283 */
Kojto 102:da0ca467f8b5 284
Kojto 102:da0ca467f8b5 285 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 286 \defgroup CMSIS_CORE Status and Control Registers
Kojto 102:da0ca467f8b5 287 \brief Core Register type definitions.
Kojto 102:da0ca467f8b5 288 @{
Kojto 102:da0ca467f8b5 289 */
Kojto 102:da0ca467f8b5 290
Kojto 102:da0ca467f8b5 291 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 102:da0ca467f8b5 292 */
Kojto 102:da0ca467f8b5 293 typedef union
Kojto 102:da0ca467f8b5 294 {
Kojto 102:da0ca467f8b5 295 struct
Kojto 102:da0ca467f8b5 296 {
Kojto 102:da0ca467f8b5 297 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 102:da0ca467f8b5 298 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 102:da0ca467f8b5 299 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 102:da0ca467f8b5 300 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 102:da0ca467f8b5 301 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 102:da0ca467f8b5 302 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 102:da0ca467f8b5 303 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 102:da0ca467f8b5 304 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 102:da0ca467f8b5 305 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 306 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 307 } APSR_Type;
Kojto 102:da0ca467f8b5 308
Kojto 102:da0ca467f8b5 309 /* APSR Register Definitions */
Kojto 102:da0ca467f8b5 310 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 102:da0ca467f8b5 311 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 102:da0ca467f8b5 312
Kojto 102:da0ca467f8b5 313 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 102:da0ca467f8b5 314 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 102:da0ca467f8b5 315
Kojto 102:da0ca467f8b5 316 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 102:da0ca467f8b5 317 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 102:da0ca467f8b5 318
Kojto 102:da0ca467f8b5 319 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 102:da0ca467f8b5 320 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 102:da0ca467f8b5 321
Kojto 102:da0ca467f8b5 322 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Kojto 102:da0ca467f8b5 323 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Kojto 102:da0ca467f8b5 324
Kojto 102:da0ca467f8b5 325 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
Kojto 102:da0ca467f8b5 326 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
Kojto 102:da0ca467f8b5 327
Kojto 102:da0ca467f8b5 328
Kojto 102:da0ca467f8b5 329 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 102:da0ca467f8b5 330 */
Kojto 102:da0ca467f8b5 331 typedef union
Kojto 102:da0ca467f8b5 332 {
Kojto 102:da0ca467f8b5 333 struct
Kojto 102:da0ca467f8b5 334 {
Kojto 102:da0ca467f8b5 335 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 102:da0ca467f8b5 336 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 102:da0ca467f8b5 337 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 338 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 339 } IPSR_Type;
Kojto 102:da0ca467f8b5 340
Kojto 102:da0ca467f8b5 341 /* IPSR Register Definitions */
Kojto 102:da0ca467f8b5 342 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 102:da0ca467f8b5 343 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 102:da0ca467f8b5 344
Kojto 102:da0ca467f8b5 345
Kojto 102:da0ca467f8b5 346 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 102:da0ca467f8b5 347 */
Kojto 102:da0ca467f8b5 348 typedef union
Kojto 102:da0ca467f8b5 349 {
Kojto 102:da0ca467f8b5 350 struct
Kojto 102:da0ca467f8b5 351 {
Kojto 102:da0ca467f8b5 352 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 102:da0ca467f8b5 353 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 102:da0ca467f8b5 354 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 102:da0ca467f8b5 355 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 102:da0ca467f8b5 356 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 102:da0ca467f8b5 357 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 102:da0ca467f8b5 358 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 102:da0ca467f8b5 359 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 102:da0ca467f8b5 360 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 102:da0ca467f8b5 361 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 102:da0ca467f8b5 362 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 102:da0ca467f8b5 363 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 364 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 365 } xPSR_Type;
Kojto 102:da0ca467f8b5 366
Kojto 102:da0ca467f8b5 367 /* xPSR Register Definitions */
Kojto 102:da0ca467f8b5 368 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 102:da0ca467f8b5 369 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 102:da0ca467f8b5 370
Kojto 102:da0ca467f8b5 371 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 102:da0ca467f8b5 372 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 102:da0ca467f8b5 373
Kojto 102:da0ca467f8b5 374 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 102:da0ca467f8b5 375 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 102:da0ca467f8b5 376
Kojto 102:da0ca467f8b5 377 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 102:da0ca467f8b5 378 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 102:da0ca467f8b5 379
Kojto 102:da0ca467f8b5 380 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Kojto 102:da0ca467f8b5 381 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Kojto 102:da0ca467f8b5 382
Kojto 102:da0ca467f8b5 383 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Kojto 102:da0ca467f8b5 384 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Kojto 102:da0ca467f8b5 385
Kojto 102:da0ca467f8b5 386 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 102:da0ca467f8b5 387 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 102:da0ca467f8b5 388
Kojto 102:da0ca467f8b5 389 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
Kojto 102:da0ca467f8b5 390 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
Kojto 102:da0ca467f8b5 391
Kojto 102:da0ca467f8b5 392 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 102:da0ca467f8b5 393 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 102:da0ca467f8b5 394
Kojto 102:da0ca467f8b5 395
Kojto 102:da0ca467f8b5 396 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 102:da0ca467f8b5 397 */
Kojto 102:da0ca467f8b5 398 typedef union
Kojto 102:da0ca467f8b5 399 {
Kojto 102:da0ca467f8b5 400 struct
Kojto 102:da0ca467f8b5 401 {
Kojto 102:da0ca467f8b5 402 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 102:da0ca467f8b5 403 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 102:da0ca467f8b5 404 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 102:da0ca467f8b5 405 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 102:da0ca467f8b5 406 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 407 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 408 } CONTROL_Type;
Kojto 102:da0ca467f8b5 409
Kojto 102:da0ca467f8b5 410 /* CONTROL Register Definitions */
Kojto 102:da0ca467f8b5 411 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
Kojto 102:da0ca467f8b5 412 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
Kojto 102:da0ca467f8b5 413
Kojto 102:da0ca467f8b5 414 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 102:da0ca467f8b5 415 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 102:da0ca467f8b5 416
Kojto 102:da0ca467f8b5 417 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 102:da0ca467f8b5 418 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 102:da0ca467f8b5 419
Kojto 102:da0ca467f8b5 420 /*@} end of group CMSIS_CORE */
Kojto 102:da0ca467f8b5 421
Kojto 102:da0ca467f8b5 422
Kojto 102:da0ca467f8b5 423 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 424 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 102:da0ca467f8b5 425 \brief Type definitions for the NVIC Registers
Kojto 102:da0ca467f8b5 426 @{
Kojto 102:da0ca467f8b5 427 */
Kojto 102:da0ca467f8b5 428
Kojto 102:da0ca467f8b5 429 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 102:da0ca467f8b5 430 */
Kojto 102:da0ca467f8b5 431 typedef struct
Kojto 102:da0ca467f8b5 432 {
Kojto 102:da0ca467f8b5 433 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 102:da0ca467f8b5 434 uint32_t RESERVED0[24];
Kojto 102:da0ca467f8b5 435 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 102:da0ca467f8b5 436 uint32_t RSERVED1[24];
Kojto 102:da0ca467f8b5 437 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 102:da0ca467f8b5 438 uint32_t RESERVED2[24];
Kojto 102:da0ca467f8b5 439 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 102:da0ca467f8b5 440 uint32_t RESERVED3[24];
Kojto 102:da0ca467f8b5 441 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Kojto 102:da0ca467f8b5 442 uint32_t RESERVED4[56];
Kojto 102:da0ca467f8b5 443 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Kojto 102:da0ca467f8b5 444 uint32_t RESERVED5[644];
Kojto 102:da0ca467f8b5 445 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Kojto 102:da0ca467f8b5 446 } NVIC_Type;
Kojto 102:da0ca467f8b5 447
Kojto 102:da0ca467f8b5 448 /* Software Triggered Interrupt Register Definitions */
Kojto 102:da0ca467f8b5 449 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Kojto 102:da0ca467f8b5 450 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Kojto 102:da0ca467f8b5 451
Kojto 102:da0ca467f8b5 452 /*@} end of group CMSIS_NVIC */
Kojto 102:da0ca467f8b5 453
Kojto 102:da0ca467f8b5 454
Kojto 102:da0ca467f8b5 455 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 456 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 102:da0ca467f8b5 457 \brief Type definitions for the System Control Block Registers
Kojto 102:da0ca467f8b5 458 @{
Kojto 102:da0ca467f8b5 459 */
Kojto 102:da0ca467f8b5 460
Kojto 102:da0ca467f8b5 461 /** \brief Structure type to access the System Control Block (SCB).
Kojto 102:da0ca467f8b5 462 */
Kojto 102:da0ca467f8b5 463 typedef struct
Kojto 102:da0ca467f8b5 464 {
Kojto 102:da0ca467f8b5 465 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 102:da0ca467f8b5 466 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 102:da0ca467f8b5 467 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 102:da0ca467f8b5 468 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 102:da0ca467f8b5 469 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 102:da0ca467f8b5 470 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 102:da0ca467f8b5 471 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Kojto 102:da0ca467f8b5 472 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 102:da0ca467f8b5 473 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Kojto 102:da0ca467f8b5 474 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Kojto 102:da0ca467f8b5 475 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Kojto 102:da0ca467f8b5 476 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Kojto 102:da0ca467f8b5 477 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Kojto 102:da0ca467f8b5 478 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Kojto 102:da0ca467f8b5 479 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Kojto 102:da0ca467f8b5 480 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Kojto 102:da0ca467f8b5 481 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Kojto 102:da0ca467f8b5 482 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Kojto 102:da0ca467f8b5 483 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Kojto 102:da0ca467f8b5 484 uint32_t RESERVED0[1];
Kojto 102:da0ca467f8b5 485 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
Kojto 102:da0ca467f8b5 486 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
Kojto 102:da0ca467f8b5 487 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
Kojto 102:da0ca467f8b5 488 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
Kojto 102:da0ca467f8b5 489 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Kojto 102:da0ca467f8b5 490 uint32_t RESERVED3[93];
Kojto 102:da0ca467f8b5 491 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
Kojto 102:da0ca467f8b5 492 uint32_t RESERVED4[15];
Kojto 102:da0ca467f8b5 493 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
Kojto 102:da0ca467f8b5 494 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
Kojto 102:da0ca467f8b5 495 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
Kojto 102:da0ca467f8b5 496 uint32_t RESERVED5[1];
Kojto 102:da0ca467f8b5 497 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
Kojto 102:da0ca467f8b5 498 uint32_t RESERVED6[1];
Kojto 102:da0ca467f8b5 499 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
Kojto 102:da0ca467f8b5 500 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
Kojto 102:da0ca467f8b5 501 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
Kojto 102:da0ca467f8b5 502 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
Kojto 102:da0ca467f8b5 503 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
Kojto 102:da0ca467f8b5 504 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
Kojto 102:da0ca467f8b5 505 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
Kojto 102:da0ca467f8b5 506 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
Kojto 102:da0ca467f8b5 507 uint32_t RESERVED7[6];
Kojto 102:da0ca467f8b5 508 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
Kojto 102:da0ca467f8b5 509 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
Kojto 102:da0ca467f8b5 510 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
Kojto 102:da0ca467f8b5 511 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
Kojto 102:da0ca467f8b5 512 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
Kojto 102:da0ca467f8b5 513 uint32_t RESERVED8[1];
Kojto 102:da0ca467f8b5 514 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
Kojto 102:da0ca467f8b5 515 } SCB_Type;
Kojto 102:da0ca467f8b5 516
Kojto 102:da0ca467f8b5 517 /* SCB CPUID Register Definitions */
Kojto 102:da0ca467f8b5 518 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 102:da0ca467f8b5 519 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 102:da0ca467f8b5 520
Kojto 102:da0ca467f8b5 521 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 102:da0ca467f8b5 522 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 102:da0ca467f8b5 523
Kojto 102:da0ca467f8b5 524 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 102:da0ca467f8b5 525 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 102:da0ca467f8b5 526
Kojto 102:da0ca467f8b5 527 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 102:da0ca467f8b5 528 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 102:da0ca467f8b5 529
Kojto 102:da0ca467f8b5 530 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 102:da0ca467f8b5 531 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 102:da0ca467f8b5 532
Kojto 102:da0ca467f8b5 533 /* SCB Interrupt Control State Register Definitions */
Kojto 102:da0ca467f8b5 534 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 102:da0ca467f8b5 535 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 102:da0ca467f8b5 536
Kojto 102:da0ca467f8b5 537 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 102:da0ca467f8b5 538 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 102:da0ca467f8b5 539
Kojto 102:da0ca467f8b5 540 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 102:da0ca467f8b5 541 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 102:da0ca467f8b5 542
Kojto 102:da0ca467f8b5 543 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 102:da0ca467f8b5 544 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 102:da0ca467f8b5 545
Kojto 102:da0ca467f8b5 546 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 102:da0ca467f8b5 547 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 102:da0ca467f8b5 548
Kojto 102:da0ca467f8b5 549 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 102:da0ca467f8b5 550 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 102:da0ca467f8b5 551
Kojto 102:da0ca467f8b5 552 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 102:da0ca467f8b5 553 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 102:da0ca467f8b5 554
Kojto 102:da0ca467f8b5 555 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 102:da0ca467f8b5 556 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 102:da0ca467f8b5 557
Kojto 102:da0ca467f8b5 558 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Kojto 102:da0ca467f8b5 559 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Kojto 102:da0ca467f8b5 560
Kojto 102:da0ca467f8b5 561 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 102:da0ca467f8b5 562 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 102:da0ca467f8b5 563
Kojto 102:da0ca467f8b5 564 /* SCB Vector Table Offset Register Definitions */
Kojto 102:da0ca467f8b5 565 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kojto 102:da0ca467f8b5 566 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 102:da0ca467f8b5 567
Kojto 102:da0ca467f8b5 568 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 102:da0ca467f8b5 569 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 102:da0ca467f8b5 570 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 102:da0ca467f8b5 571
Kojto 102:da0ca467f8b5 572 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 102:da0ca467f8b5 573 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 102:da0ca467f8b5 574
Kojto 102:da0ca467f8b5 575 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 102:da0ca467f8b5 576 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 102:da0ca467f8b5 577
Kojto 102:da0ca467f8b5 578 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Kojto 102:da0ca467f8b5 579 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Kojto 102:da0ca467f8b5 580
Kojto 102:da0ca467f8b5 581 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 102:da0ca467f8b5 582 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 102:da0ca467f8b5 583
Kojto 102:da0ca467f8b5 584 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 102:da0ca467f8b5 585 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 102:da0ca467f8b5 586
Kojto 102:da0ca467f8b5 587 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kojto 102:da0ca467f8b5 588 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
Kojto 102:da0ca467f8b5 589
Kojto 102:da0ca467f8b5 590 /* SCB System Control Register Definitions */
Kojto 102:da0ca467f8b5 591 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 102:da0ca467f8b5 592 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 102:da0ca467f8b5 593
Kojto 102:da0ca467f8b5 594 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 102:da0ca467f8b5 595 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 102:da0ca467f8b5 596
Kojto 102:da0ca467f8b5 597 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 102:da0ca467f8b5 598 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 102:da0ca467f8b5 599
Kojto 102:da0ca467f8b5 600 /* SCB Configuration Control Register Definitions */
Kojto 102:da0ca467f8b5 601 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
Kojto 102:da0ca467f8b5 602 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
Kojto 102:da0ca467f8b5 603
Kojto 102:da0ca467f8b5 604 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
Kojto 102:da0ca467f8b5 605 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
Kojto 102:da0ca467f8b5 606
Kojto 102:da0ca467f8b5 607 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
Kojto 102:da0ca467f8b5 608 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
Kojto 102:da0ca467f8b5 609
Kojto 102:da0ca467f8b5 610 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 102:da0ca467f8b5 611 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 102:da0ca467f8b5 612
Kojto 102:da0ca467f8b5 613 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Kojto 102:da0ca467f8b5 614 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Kojto 102:da0ca467f8b5 615
Kojto 102:da0ca467f8b5 616 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Kojto 102:da0ca467f8b5 617 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Kojto 102:da0ca467f8b5 618
Kojto 102:da0ca467f8b5 619 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 102:da0ca467f8b5 620 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 102:da0ca467f8b5 621
Kojto 102:da0ca467f8b5 622 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Kojto 102:da0ca467f8b5 623 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Kojto 102:da0ca467f8b5 624
Kojto 102:da0ca467f8b5 625 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 102:da0ca467f8b5 626 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
Kojto 102:da0ca467f8b5 627
Kojto 102:da0ca467f8b5 628 /* SCB System Handler Control and State Register Definitions */
Kojto 102:da0ca467f8b5 629 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Kojto 102:da0ca467f8b5 630 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Kojto 102:da0ca467f8b5 631
Kojto 102:da0ca467f8b5 632 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Kojto 102:da0ca467f8b5 633 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Kojto 102:da0ca467f8b5 634
Kojto 102:da0ca467f8b5 635 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Kojto 102:da0ca467f8b5 636 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Kojto 102:da0ca467f8b5 637
Kojto 102:da0ca467f8b5 638 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 102:da0ca467f8b5 639 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 102:da0ca467f8b5 640
Kojto 102:da0ca467f8b5 641 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Kojto 102:da0ca467f8b5 642 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Kojto 102:da0ca467f8b5 643
Kojto 102:da0ca467f8b5 644 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Kojto 102:da0ca467f8b5 645 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Kojto 102:da0ca467f8b5 646
Kojto 102:da0ca467f8b5 647 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Kojto 102:da0ca467f8b5 648 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Kojto 102:da0ca467f8b5 649
Kojto 102:da0ca467f8b5 650 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Kojto 102:da0ca467f8b5 651 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Kojto 102:da0ca467f8b5 652
Kojto 102:da0ca467f8b5 653 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Kojto 102:da0ca467f8b5 654 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Kojto 102:da0ca467f8b5 655
Kojto 102:da0ca467f8b5 656 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Kojto 102:da0ca467f8b5 657 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Kojto 102:da0ca467f8b5 658
Kojto 102:da0ca467f8b5 659 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Kojto 102:da0ca467f8b5 660 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Kojto 102:da0ca467f8b5 661
Kojto 102:da0ca467f8b5 662 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Kojto 102:da0ca467f8b5 663 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Kojto 102:da0ca467f8b5 664
Kojto 102:da0ca467f8b5 665 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Kojto 102:da0ca467f8b5 666 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Kojto 102:da0ca467f8b5 667
Kojto 102:da0ca467f8b5 668 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 102:da0ca467f8b5 669 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Kojto 102:da0ca467f8b5 670
Kojto 102:da0ca467f8b5 671 /* SCB Configurable Fault Status Registers Definitions */
Kojto 102:da0ca467f8b5 672 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Kojto 102:da0ca467f8b5 673 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Kojto 102:da0ca467f8b5 674
Kojto 102:da0ca467f8b5 675 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Kojto 102:da0ca467f8b5 676 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Kojto 102:da0ca467f8b5 677
Kojto 102:da0ca467f8b5 678 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 102:da0ca467f8b5 679 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Kojto 102:da0ca467f8b5 680
Kojto 102:da0ca467f8b5 681 /* SCB Hard Fault Status Registers Definitions */
Kojto 102:da0ca467f8b5 682 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Kojto 102:da0ca467f8b5 683 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Kojto 102:da0ca467f8b5 684
Kojto 102:da0ca467f8b5 685 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Kojto 102:da0ca467f8b5 686 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Kojto 102:da0ca467f8b5 687
Kojto 102:da0ca467f8b5 688 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Kojto 102:da0ca467f8b5 689 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Kojto 102:da0ca467f8b5 690
Kojto 102:da0ca467f8b5 691 /* SCB Debug Fault Status Register Definitions */
Kojto 102:da0ca467f8b5 692 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Kojto 102:da0ca467f8b5 693 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Kojto 102:da0ca467f8b5 694
Kojto 102:da0ca467f8b5 695 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Kojto 102:da0ca467f8b5 696 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Kojto 102:da0ca467f8b5 697
Kojto 102:da0ca467f8b5 698 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Kojto 102:da0ca467f8b5 699 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Kojto 102:da0ca467f8b5 700
Kojto 102:da0ca467f8b5 701 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Kojto 102:da0ca467f8b5 702 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Kojto 102:da0ca467f8b5 703
Kojto 102:da0ca467f8b5 704 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kojto 102:da0ca467f8b5 705 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Kojto 102:da0ca467f8b5 706
Kojto 102:da0ca467f8b5 707 /* Cache Level ID register */
Kojto 102:da0ca467f8b5 708 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
Kojto 102:da0ca467f8b5 709 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
Kojto 102:da0ca467f8b5 710
Kojto 102:da0ca467f8b5 711 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
Kojto 102:da0ca467f8b5 712 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
Kojto 102:da0ca467f8b5 713
Kojto 102:da0ca467f8b5 714 /* Cache Type register */
Kojto 102:da0ca467f8b5 715 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
Kojto 102:da0ca467f8b5 716 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
Kojto 102:da0ca467f8b5 717
Kojto 102:da0ca467f8b5 718 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
Kojto 102:da0ca467f8b5 719 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
Kojto 102:da0ca467f8b5 720
Kojto 102:da0ca467f8b5 721 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
Kojto 102:da0ca467f8b5 722 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
Kojto 102:da0ca467f8b5 723
Kojto 102:da0ca467f8b5 724 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
Kojto 102:da0ca467f8b5 725 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
Kojto 102:da0ca467f8b5 726
Kojto 102:da0ca467f8b5 727 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
Kojto 102:da0ca467f8b5 728 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
Kojto 102:da0ca467f8b5 729
Kojto 102:da0ca467f8b5 730 /* Cache Size ID Register */
Kojto 102:da0ca467f8b5 731 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
Kojto 102:da0ca467f8b5 732 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
Kojto 102:da0ca467f8b5 733
Kojto 102:da0ca467f8b5 734 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
Kojto 102:da0ca467f8b5 735 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
Kojto 102:da0ca467f8b5 736
Kojto 102:da0ca467f8b5 737 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
Kojto 102:da0ca467f8b5 738 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
Kojto 102:da0ca467f8b5 739
Kojto 102:da0ca467f8b5 740 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
Kojto 102:da0ca467f8b5 741 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
Kojto 102:da0ca467f8b5 742
Kojto 102:da0ca467f8b5 743 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
Kojto 102:da0ca467f8b5 744 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
Kojto 102:da0ca467f8b5 745
Kojto 102:da0ca467f8b5 746 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
Kojto 102:da0ca467f8b5 747 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
Kojto 102:da0ca467f8b5 748
Kojto 102:da0ca467f8b5 749 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
Kojto 102:da0ca467f8b5 750 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
Kojto 102:da0ca467f8b5 751
Kojto 102:da0ca467f8b5 752 /* Cache Size Selection Register */
Kojto 102:da0ca467f8b5 753 #define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
Kojto 102:da0ca467f8b5 754 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
Kojto 102:da0ca467f8b5 755
Kojto 102:da0ca467f8b5 756 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
Kojto 102:da0ca467f8b5 757 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
Kojto 102:da0ca467f8b5 758
Kojto 102:da0ca467f8b5 759 /* SCB Software Triggered Interrupt Register */
Kojto 102:da0ca467f8b5 760 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
Kojto 102:da0ca467f8b5 761 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
Kojto 102:da0ca467f8b5 762
Kojto 102:da0ca467f8b5 763 /* Instruction Tightly-Coupled Memory Control Register*/
Kojto 102:da0ca467f8b5 764 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
Kojto 102:da0ca467f8b5 765 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
Kojto 102:da0ca467f8b5 766
Kojto 102:da0ca467f8b5 767 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
Kojto 102:da0ca467f8b5 768 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
Kojto 102:da0ca467f8b5 769
Kojto 102:da0ca467f8b5 770 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
Kojto 102:da0ca467f8b5 771 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
Kojto 102:da0ca467f8b5 772
Kojto 102:da0ca467f8b5 773 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
Kojto 102:da0ca467f8b5 774 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
Kojto 102:da0ca467f8b5 775
Kojto 102:da0ca467f8b5 776 /* Data Tightly-Coupled Memory Control Registers */
Kojto 102:da0ca467f8b5 777 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
Kojto 102:da0ca467f8b5 778 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
Kojto 102:da0ca467f8b5 779
Kojto 102:da0ca467f8b5 780 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
Kojto 102:da0ca467f8b5 781 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
Kojto 102:da0ca467f8b5 782
Kojto 102:da0ca467f8b5 783 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
Kojto 102:da0ca467f8b5 784 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
Kojto 102:da0ca467f8b5 785
Kojto 102:da0ca467f8b5 786 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
Kojto 102:da0ca467f8b5 787 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
Kojto 102:da0ca467f8b5 788
Kojto 102:da0ca467f8b5 789 /* AHBP Control Register */
Kojto 102:da0ca467f8b5 790 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
Kojto 102:da0ca467f8b5 791 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
Kojto 102:da0ca467f8b5 792
Kojto 102:da0ca467f8b5 793 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
Kojto 102:da0ca467f8b5 794 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
Kojto 102:da0ca467f8b5 795
Kojto 102:da0ca467f8b5 796 /* L1 Cache Control Register */
Kojto 102:da0ca467f8b5 797 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
Kojto 102:da0ca467f8b5 798 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
Kojto 102:da0ca467f8b5 799
Kojto 102:da0ca467f8b5 800 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
Kojto 102:da0ca467f8b5 801 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
Kojto 102:da0ca467f8b5 802
Kojto 102:da0ca467f8b5 803 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
Kojto 102:da0ca467f8b5 804 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
Kojto 102:da0ca467f8b5 805
Kojto 102:da0ca467f8b5 806 /* AHBS control register */
Kojto 102:da0ca467f8b5 807 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
Kojto 102:da0ca467f8b5 808 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
Kojto 102:da0ca467f8b5 809
Kojto 102:da0ca467f8b5 810 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
Kojto 102:da0ca467f8b5 811 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
Kojto 102:da0ca467f8b5 812
Kojto 102:da0ca467f8b5 813 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
Kojto 102:da0ca467f8b5 814 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
Kojto 102:da0ca467f8b5 815
Kojto 102:da0ca467f8b5 816 /* Auxiliary Bus Fault Status Register */
Kojto 102:da0ca467f8b5 817 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
Kojto 102:da0ca467f8b5 818 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
Kojto 102:da0ca467f8b5 819
Kojto 102:da0ca467f8b5 820 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
Kojto 102:da0ca467f8b5 821 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
Kojto 102:da0ca467f8b5 822
Kojto 102:da0ca467f8b5 823 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
Kojto 102:da0ca467f8b5 824 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
Kojto 102:da0ca467f8b5 825
Kojto 102:da0ca467f8b5 826 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
Kojto 102:da0ca467f8b5 827 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
Kojto 102:da0ca467f8b5 828
Kojto 102:da0ca467f8b5 829 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
Kojto 102:da0ca467f8b5 830 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
Kojto 102:da0ca467f8b5 831
Kojto 102:da0ca467f8b5 832 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
Kojto 102:da0ca467f8b5 833 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
Kojto 102:da0ca467f8b5 834
Kojto 102:da0ca467f8b5 835 /*@} end of group CMSIS_SCB */
Kojto 102:da0ca467f8b5 836
Kojto 102:da0ca467f8b5 837
Kojto 102:da0ca467f8b5 838 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 839 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto 102:da0ca467f8b5 840 \brief Type definitions for the System Control and ID Register not in the SCB
Kojto 102:da0ca467f8b5 841 @{
Kojto 102:da0ca467f8b5 842 */
Kojto 102:da0ca467f8b5 843
Kojto 102:da0ca467f8b5 844 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto 102:da0ca467f8b5 845 */
Kojto 102:da0ca467f8b5 846 typedef struct
Kojto 102:da0ca467f8b5 847 {
Kojto 102:da0ca467f8b5 848 uint32_t RESERVED0[1];
Kojto 102:da0ca467f8b5 849 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Kojto 102:da0ca467f8b5 850 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Kojto 102:da0ca467f8b5 851 } SCnSCB_Type;
Kojto 102:da0ca467f8b5 852
Kojto 102:da0ca467f8b5 853 /* Interrupt Controller Type Register Definitions */
Kojto 102:da0ca467f8b5 854 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Kojto 102:da0ca467f8b5 855 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Kojto 102:da0ca467f8b5 856
Kojto 102:da0ca467f8b5 857 /* Auxiliary Control Register Definitions */
Kojto 102:da0ca467f8b5 858 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
Kojto 102:da0ca467f8b5 859 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
Kojto 102:da0ca467f8b5 860
Kojto 102:da0ca467f8b5 861 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
Kojto 102:da0ca467f8b5 862 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
Kojto 102:da0ca467f8b5 863
Kojto 102:da0ca467f8b5 864 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
Kojto 102:da0ca467f8b5 865 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
Kojto 102:da0ca467f8b5 866
Kojto 102:da0ca467f8b5 867 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
Kojto 102:da0ca467f8b5 868 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
Kojto 102:da0ca467f8b5 869
Kojto 102:da0ca467f8b5 870 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Kojto 102:da0ca467f8b5 871 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Kojto 102:da0ca467f8b5 872
Kojto 102:da0ca467f8b5 873 /*@} end of group CMSIS_SCnotSCB */
Kojto 102:da0ca467f8b5 874
Kojto 102:da0ca467f8b5 875
Kojto 102:da0ca467f8b5 876 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 877 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 102:da0ca467f8b5 878 \brief Type definitions for the System Timer Registers.
Kojto 102:da0ca467f8b5 879 @{
Kojto 102:da0ca467f8b5 880 */
Kojto 102:da0ca467f8b5 881
Kojto 102:da0ca467f8b5 882 /** \brief Structure type to access the System Timer (SysTick).
Kojto 102:da0ca467f8b5 883 */
Kojto 102:da0ca467f8b5 884 typedef struct
Kojto 102:da0ca467f8b5 885 {
Kojto 102:da0ca467f8b5 886 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 102:da0ca467f8b5 887 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 102:da0ca467f8b5 888 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 102:da0ca467f8b5 889 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 102:da0ca467f8b5 890 } SysTick_Type;
Kojto 102:da0ca467f8b5 891
Kojto 102:da0ca467f8b5 892 /* SysTick Control / Status Register Definitions */
Kojto 102:da0ca467f8b5 893 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 102:da0ca467f8b5 894 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 102:da0ca467f8b5 895
Kojto 102:da0ca467f8b5 896 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 102:da0ca467f8b5 897 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 102:da0ca467f8b5 898
Kojto 102:da0ca467f8b5 899 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 102:da0ca467f8b5 900 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 102:da0ca467f8b5 901
Kojto 102:da0ca467f8b5 902 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 102:da0ca467f8b5 903 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 102:da0ca467f8b5 904
Kojto 102:da0ca467f8b5 905 /* SysTick Reload Register Definitions */
Kojto 102:da0ca467f8b5 906 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 102:da0ca467f8b5 907 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 102:da0ca467f8b5 908
Kojto 102:da0ca467f8b5 909 /* SysTick Current Register Definitions */
Kojto 102:da0ca467f8b5 910 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 102:da0ca467f8b5 911 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 102:da0ca467f8b5 912
Kojto 102:da0ca467f8b5 913 /* SysTick Calibration Register Definitions */
Kojto 102:da0ca467f8b5 914 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 102:da0ca467f8b5 915 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 102:da0ca467f8b5 916
Kojto 102:da0ca467f8b5 917 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 102:da0ca467f8b5 918 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 102:da0ca467f8b5 919
Kojto 102:da0ca467f8b5 920 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 102:da0ca467f8b5 921 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 102:da0ca467f8b5 922
Kojto 102:da0ca467f8b5 923 /*@} end of group CMSIS_SysTick */
Kojto 102:da0ca467f8b5 924
Kojto 102:da0ca467f8b5 925
Kojto 102:da0ca467f8b5 926 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 927 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto 102:da0ca467f8b5 928 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto 102:da0ca467f8b5 929 @{
Kojto 102:da0ca467f8b5 930 */
Kojto 102:da0ca467f8b5 931
Kojto 102:da0ca467f8b5 932 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto 102:da0ca467f8b5 933 */
Kojto 102:da0ca467f8b5 934 typedef struct
Kojto 102:da0ca467f8b5 935 {
Kojto 102:da0ca467f8b5 936 __O union
Kojto 102:da0ca467f8b5 937 {
Kojto 102:da0ca467f8b5 938 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Kojto 102:da0ca467f8b5 939 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Kojto 102:da0ca467f8b5 940 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Kojto 102:da0ca467f8b5 941 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Kojto 102:da0ca467f8b5 942 uint32_t RESERVED0[864];
Kojto 102:da0ca467f8b5 943 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Kojto 102:da0ca467f8b5 944 uint32_t RESERVED1[15];
Kojto 102:da0ca467f8b5 945 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Kojto 102:da0ca467f8b5 946 uint32_t RESERVED2[15];
Kojto 102:da0ca467f8b5 947 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Kojto 102:da0ca467f8b5 948 uint32_t RESERVED3[29];
Kojto 102:da0ca467f8b5 949 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Kojto 102:da0ca467f8b5 950 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Kojto 102:da0ca467f8b5 951 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Kojto 102:da0ca467f8b5 952 uint32_t RESERVED4[43];
Kojto 102:da0ca467f8b5 953 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Kojto 102:da0ca467f8b5 954 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Kojto 102:da0ca467f8b5 955 uint32_t RESERVED5[6];
Kojto 102:da0ca467f8b5 956 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Kojto 102:da0ca467f8b5 957 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Kojto 102:da0ca467f8b5 958 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Kojto 102:da0ca467f8b5 959 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Kojto 102:da0ca467f8b5 960 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Kojto 102:da0ca467f8b5 961 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Kojto 102:da0ca467f8b5 962 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Kojto 102:da0ca467f8b5 963 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Kojto 102:da0ca467f8b5 964 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Kojto 102:da0ca467f8b5 965 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Kojto 102:da0ca467f8b5 966 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Kojto 102:da0ca467f8b5 967 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Kojto 102:da0ca467f8b5 968 } ITM_Type;
Kojto 102:da0ca467f8b5 969
Kojto 102:da0ca467f8b5 970 /* ITM Trace Privilege Register Definitions */
Kojto 102:da0ca467f8b5 971 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kojto 102:da0ca467f8b5 972 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Kojto 102:da0ca467f8b5 973
Kojto 102:da0ca467f8b5 974 /* ITM Trace Control Register Definitions */
Kojto 102:da0ca467f8b5 975 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Kojto 102:da0ca467f8b5 976 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Kojto 102:da0ca467f8b5 977
Kojto 102:da0ca467f8b5 978 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
Kojto 102:da0ca467f8b5 979 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Kojto 102:da0ca467f8b5 980
Kojto 102:da0ca467f8b5 981 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
Kojto 102:da0ca467f8b5 982 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Kojto 102:da0ca467f8b5 983
Kojto 102:da0ca467f8b5 984 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Kojto 102:da0ca467f8b5 985 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Kojto 102:da0ca467f8b5 986
Kojto 102:da0ca467f8b5 987 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Kojto 102:da0ca467f8b5 988 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Kojto 102:da0ca467f8b5 989
Kojto 102:da0ca467f8b5 990 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Kojto 102:da0ca467f8b5 991 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Kojto 102:da0ca467f8b5 992
Kojto 102:da0ca467f8b5 993 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Kojto 102:da0ca467f8b5 994 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Kojto 102:da0ca467f8b5 995
Kojto 102:da0ca467f8b5 996 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Kojto 102:da0ca467f8b5 997 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Kojto 102:da0ca467f8b5 998
Kojto 102:da0ca467f8b5 999 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kojto 102:da0ca467f8b5 1000 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Kojto 102:da0ca467f8b5 1001
Kojto 102:da0ca467f8b5 1002 /* ITM Integration Write Register Definitions */
Kojto 102:da0ca467f8b5 1003 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kojto 102:da0ca467f8b5 1004 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Kojto 102:da0ca467f8b5 1005
Kojto 102:da0ca467f8b5 1006 /* ITM Integration Read Register Definitions */
Kojto 102:da0ca467f8b5 1007 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kojto 102:da0ca467f8b5 1008 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Kojto 102:da0ca467f8b5 1009
Kojto 102:da0ca467f8b5 1010 /* ITM Integration Mode Control Register Definitions */
Kojto 102:da0ca467f8b5 1011 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kojto 102:da0ca467f8b5 1012 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Kojto 102:da0ca467f8b5 1013
Kojto 102:da0ca467f8b5 1014 /* ITM Lock Status Register Definitions */
Kojto 102:da0ca467f8b5 1015 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Kojto 102:da0ca467f8b5 1016 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Kojto 102:da0ca467f8b5 1017
Kojto 102:da0ca467f8b5 1018 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Kojto 102:da0ca467f8b5 1019 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Kojto 102:da0ca467f8b5 1020
Kojto 102:da0ca467f8b5 1021 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kojto 102:da0ca467f8b5 1022 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Kojto 102:da0ca467f8b5 1023
Kojto 102:da0ca467f8b5 1024 /*@}*/ /* end of group CMSIS_ITM */
Kojto 102:da0ca467f8b5 1025
Kojto 102:da0ca467f8b5 1026
Kojto 102:da0ca467f8b5 1027 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 1028 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto 102:da0ca467f8b5 1029 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto 102:da0ca467f8b5 1030 @{
Kojto 102:da0ca467f8b5 1031 */
Kojto 102:da0ca467f8b5 1032
Kojto 102:da0ca467f8b5 1033 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto 102:da0ca467f8b5 1034 */
Kojto 102:da0ca467f8b5 1035 typedef struct
Kojto 102:da0ca467f8b5 1036 {
Kojto 102:da0ca467f8b5 1037 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Kojto 102:da0ca467f8b5 1038 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Kojto 102:da0ca467f8b5 1039 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Kojto 102:da0ca467f8b5 1040 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Kojto 102:da0ca467f8b5 1041 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Kojto 102:da0ca467f8b5 1042 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Kojto 102:da0ca467f8b5 1043 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Kojto 102:da0ca467f8b5 1044 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Kojto 102:da0ca467f8b5 1045 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Kojto 102:da0ca467f8b5 1046 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Kojto 102:da0ca467f8b5 1047 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Kojto 102:da0ca467f8b5 1048 uint32_t RESERVED0[1];
Kojto 102:da0ca467f8b5 1049 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Kojto 102:da0ca467f8b5 1050 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Kojto 102:da0ca467f8b5 1051 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Kojto 102:da0ca467f8b5 1052 uint32_t RESERVED1[1];
Kojto 102:da0ca467f8b5 1053 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Kojto 102:da0ca467f8b5 1054 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Kojto 102:da0ca467f8b5 1055 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Kojto 102:da0ca467f8b5 1056 uint32_t RESERVED2[1];
Kojto 102:da0ca467f8b5 1057 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Kojto 102:da0ca467f8b5 1058 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Kojto 102:da0ca467f8b5 1059 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Kojto 102:da0ca467f8b5 1060 uint32_t RESERVED3[981];
Kojto 102:da0ca467f8b5 1061 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
Kojto 102:da0ca467f8b5 1062 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
Kojto 102:da0ca467f8b5 1063 } DWT_Type;
Kojto 102:da0ca467f8b5 1064
Kojto 102:da0ca467f8b5 1065 /* DWT Control Register Definitions */
Kojto 102:da0ca467f8b5 1066 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
Kojto 102:da0ca467f8b5 1067 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Kojto 102:da0ca467f8b5 1068
Kojto 102:da0ca467f8b5 1069 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
Kojto 102:da0ca467f8b5 1070 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Kojto 102:da0ca467f8b5 1071
Kojto 102:da0ca467f8b5 1072 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
Kojto 102:da0ca467f8b5 1073 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Kojto 102:da0ca467f8b5 1074
Kojto 102:da0ca467f8b5 1075 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
Kojto 102:da0ca467f8b5 1076 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Kojto 102:da0ca467f8b5 1077
Kojto 102:da0ca467f8b5 1078 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
Kojto 102:da0ca467f8b5 1079 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Kojto 102:da0ca467f8b5 1080
Kojto 102:da0ca467f8b5 1081 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
Kojto 102:da0ca467f8b5 1082 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Kojto 102:da0ca467f8b5 1083
Kojto 102:da0ca467f8b5 1084 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
Kojto 102:da0ca467f8b5 1085 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Kojto 102:da0ca467f8b5 1086
Kojto 102:da0ca467f8b5 1087 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
Kojto 102:da0ca467f8b5 1088 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Kojto 102:da0ca467f8b5 1089
Kojto 102:da0ca467f8b5 1090 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
Kojto 102:da0ca467f8b5 1091 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Kojto 102:da0ca467f8b5 1092
Kojto 102:da0ca467f8b5 1093 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
Kojto 102:da0ca467f8b5 1094 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Kojto 102:da0ca467f8b5 1095
Kojto 102:da0ca467f8b5 1096 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
Kojto 102:da0ca467f8b5 1097 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Kojto 102:da0ca467f8b5 1098
Kojto 102:da0ca467f8b5 1099 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
Kojto 102:da0ca467f8b5 1100 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Kojto 102:da0ca467f8b5 1101
Kojto 102:da0ca467f8b5 1102 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
Kojto 102:da0ca467f8b5 1103 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Kojto 102:da0ca467f8b5 1104
Kojto 102:da0ca467f8b5 1105 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
Kojto 102:da0ca467f8b5 1106 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Kojto 102:da0ca467f8b5 1107
Kojto 102:da0ca467f8b5 1108 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
Kojto 102:da0ca467f8b5 1109 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Kojto 102:da0ca467f8b5 1110
Kojto 102:da0ca467f8b5 1111 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
Kojto 102:da0ca467f8b5 1112 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Kojto 102:da0ca467f8b5 1113
Kojto 102:da0ca467f8b5 1114 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
Kojto 102:da0ca467f8b5 1115 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Kojto 102:da0ca467f8b5 1116
Kojto 102:da0ca467f8b5 1117 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Kojto 102:da0ca467f8b5 1118 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Kojto 102:da0ca467f8b5 1119
Kojto 102:da0ca467f8b5 1120 /* DWT CPI Count Register Definitions */
Kojto 102:da0ca467f8b5 1121 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Kojto 102:da0ca467f8b5 1122 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Kojto 102:da0ca467f8b5 1123
Kojto 102:da0ca467f8b5 1124 /* DWT Exception Overhead Count Register Definitions */
Kojto 102:da0ca467f8b5 1125 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Kojto 102:da0ca467f8b5 1126 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Kojto 102:da0ca467f8b5 1127
Kojto 102:da0ca467f8b5 1128 /* DWT Sleep Count Register Definitions */
Kojto 102:da0ca467f8b5 1129 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 102:da0ca467f8b5 1130 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Kojto 102:da0ca467f8b5 1131
Kojto 102:da0ca467f8b5 1132 /* DWT LSU Count Register Definitions */
Kojto 102:da0ca467f8b5 1133 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Kojto 102:da0ca467f8b5 1134 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Kojto 102:da0ca467f8b5 1135
Kojto 102:da0ca467f8b5 1136 /* DWT Folded-instruction Count Register Definitions */
Kojto 102:da0ca467f8b5 1137 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 102:da0ca467f8b5 1138 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Kojto 102:da0ca467f8b5 1139
Kojto 102:da0ca467f8b5 1140 /* DWT Comparator Mask Register Definitions */
Kojto 102:da0ca467f8b5 1141 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Kojto 102:da0ca467f8b5 1142 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
Kojto 102:da0ca467f8b5 1143
Kojto 102:da0ca467f8b5 1144 /* DWT Comparator Function Register Definitions */
Kojto 102:da0ca467f8b5 1145 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
Kojto 102:da0ca467f8b5 1146 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Kojto 102:da0ca467f8b5 1147
Kojto 102:da0ca467f8b5 1148 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
Kojto 102:da0ca467f8b5 1149 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Kojto 102:da0ca467f8b5 1150
Kojto 102:da0ca467f8b5 1151 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
Kojto 102:da0ca467f8b5 1152 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Kojto 102:da0ca467f8b5 1153
Kojto 102:da0ca467f8b5 1154 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
Kojto 102:da0ca467f8b5 1155 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Kojto 102:da0ca467f8b5 1156
Kojto 102:da0ca467f8b5 1157 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
Kojto 102:da0ca467f8b5 1158 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Kojto 102:da0ca467f8b5 1159
Kojto 102:da0ca467f8b5 1160 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
Kojto 102:da0ca467f8b5 1161 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Kojto 102:da0ca467f8b5 1162
Kojto 102:da0ca467f8b5 1163 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
Kojto 102:da0ca467f8b5 1164 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Kojto 102:da0ca467f8b5 1165
Kojto 102:da0ca467f8b5 1166 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
Kojto 102:da0ca467f8b5 1167 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Kojto 102:da0ca467f8b5 1168
Kojto 102:da0ca467f8b5 1169 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Kojto 102:da0ca467f8b5 1170 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
Kojto 102:da0ca467f8b5 1171
Kojto 102:da0ca467f8b5 1172 /*@}*/ /* end of group CMSIS_DWT */
Kojto 102:da0ca467f8b5 1173
Kojto 102:da0ca467f8b5 1174
Kojto 102:da0ca467f8b5 1175 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 1176 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto 102:da0ca467f8b5 1177 \brief Type definitions for the Trace Port Interface (TPI)
Kojto 102:da0ca467f8b5 1178 @{
Kojto 102:da0ca467f8b5 1179 */
Kojto 102:da0ca467f8b5 1180
Kojto 102:da0ca467f8b5 1181 /** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto 102:da0ca467f8b5 1182 */
Kojto 102:da0ca467f8b5 1183 typedef struct
Kojto 102:da0ca467f8b5 1184 {
Kojto 102:da0ca467f8b5 1185 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Kojto 102:da0ca467f8b5 1186 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Kojto 102:da0ca467f8b5 1187 uint32_t RESERVED0[2];
Kojto 102:da0ca467f8b5 1188 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Kojto 102:da0ca467f8b5 1189 uint32_t RESERVED1[55];
Kojto 102:da0ca467f8b5 1190 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Kojto 102:da0ca467f8b5 1191 uint32_t RESERVED2[131];
Kojto 102:da0ca467f8b5 1192 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Kojto 102:da0ca467f8b5 1193 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Kojto 102:da0ca467f8b5 1194 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Kojto 102:da0ca467f8b5 1195 uint32_t RESERVED3[759];
Kojto 102:da0ca467f8b5 1196 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Kojto 102:da0ca467f8b5 1197 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Kojto 102:da0ca467f8b5 1198 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Kojto 102:da0ca467f8b5 1199 uint32_t RESERVED4[1];
Kojto 102:da0ca467f8b5 1200 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Kojto 102:da0ca467f8b5 1201 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Kojto 102:da0ca467f8b5 1202 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Kojto 102:da0ca467f8b5 1203 uint32_t RESERVED5[39];
Kojto 102:da0ca467f8b5 1204 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Kojto 102:da0ca467f8b5 1205 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Kojto 102:da0ca467f8b5 1206 uint32_t RESERVED7[8];
Kojto 102:da0ca467f8b5 1207 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Kojto 102:da0ca467f8b5 1208 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Kojto 102:da0ca467f8b5 1209 } TPI_Type;
Kojto 102:da0ca467f8b5 1210
Kojto 102:da0ca467f8b5 1211 /* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto 102:da0ca467f8b5 1212 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Kojto 102:da0ca467f8b5 1213 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Kojto 102:da0ca467f8b5 1214
Kojto 102:da0ca467f8b5 1215 /* TPI Selected Pin Protocol Register Definitions */
Kojto 102:da0ca467f8b5 1216 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Kojto 102:da0ca467f8b5 1217 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Kojto 102:da0ca467f8b5 1218
Kojto 102:da0ca467f8b5 1219 /* TPI Formatter and Flush Status Register Definitions */
Kojto 102:da0ca467f8b5 1220 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
Kojto 102:da0ca467f8b5 1221 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Kojto 102:da0ca467f8b5 1222
Kojto 102:da0ca467f8b5 1223 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
Kojto 102:da0ca467f8b5 1224 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Kojto 102:da0ca467f8b5 1225
Kojto 102:da0ca467f8b5 1226 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
Kojto 102:da0ca467f8b5 1227 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Kojto 102:da0ca467f8b5 1228
Kojto 102:da0ca467f8b5 1229 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Kojto 102:da0ca467f8b5 1230 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Kojto 102:da0ca467f8b5 1231
Kojto 102:da0ca467f8b5 1232 /* TPI Formatter and Flush Control Register Definitions */
Kojto 102:da0ca467f8b5 1233 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
Kojto 102:da0ca467f8b5 1234 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Kojto 102:da0ca467f8b5 1235
Kojto 102:da0ca467f8b5 1236 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
Kojto 102:da0ca467f8b5 1237 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Kojto 102:da0ca467f8b5 1238
Kojto 102:da0ca467f8b5 1239 /* TPI TRIGGER Register Definitions */
Kojto 102:da0ca467f8b5 1240 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Kojto 102:da0ca467f8b5 1241 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Kojto 102:da0ca467f8b5 1242
Kojto 102:da0ca467f8b5 1243 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto 102:da0ca467f8b5 1244 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
Kojto 102:da0ca467f8b5 1245 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Kojto 102:da0ca467f8b5 1246
Kojto 102:da0ca467f8b5 1247 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
Kojto 102:da0ca467f8b5 1248 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Kojto 102:da0ca467f8b5 1249
Kojto 102:da0ca467f8b5 1250 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
Kojto 102:da0ca467f8b5 1251 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Kojto 102:da0ca467f8b5 1252
Kojto 102:da0ca467f8b5 1253 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
Kojto 102:da0ca467f8b5 1254 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Kojto 102:da0ca467f8b5 1255
Kojto 102:da0ca467f8b5 1256 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
Kojto 102:da0ca467f8b5 1257 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Kojto 102:da0ca467f8b5 1258
Kojto 102:da0ca467f8b5 1259 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
Kojto 102:da0ca467f8b5 1260 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Kojto 102:da0ca467f8b5 1261
Kojto 102:da0ca467f8b5 1262 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Kojto 102:da0ca467f8b5 1263 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Kojto 102:da0ca467f8b5 1264
Kojto 102:da0ca467f8b5 1265 /* TPI ITATBCTR2 Register Definitions */
Kojto 102:da0ca467f8b5 1266 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 102:da0ca467f8b5 1267 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Kojto 102:da0ca467f8b5 1268
Kojto 102:da0ca467f8b5 1269 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto 102:da0ca467f8b5 1270 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
Kojto 102:da0ca467f8b5 1271 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Kojto 102:da0ca467f8b5 1272
Kojto 102:da0ca467f8b5 1273 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
Kojto 102:da0ca467f8b5 1274 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Kojto 102:da0ca467f8b5 1275
Kojto 102:da0ca467f8b5 1276 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
Kojto 102:da0ca467f8b5 1277 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Kojto 102:da0ca467f8b5 1278
Kojto 102:da0ca467f8b5 1279 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
Kojto 102:da0ca467f8b5 1280 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Kojto 102:da0ca467f8b5 1281
Kojto 102:da0ca467f8b5 1282 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
Kojto 102:da0ca467f8b5 1283 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Kojto 102:da0ca467f8b5 1284
Kojto 102:da0ca467f8b5 1285 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
Kojto 102:da0ca467f8b5 1286 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Kojto 102:da0ca467f8b5 1287
Kojto 102:da0ca467f8b5 1288 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Kojto 102:da0ca467f8b5 1289 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Kojto 102:da0ca467f8b5 1290
Kojto 102:da0ca467f8b5 1291 /* TPI ITATBCTR0 Register Definitions */
Kojto 102:da0ca467f8b5 1292 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 102:da0ca467f8b5 1293 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Kojto 102:da0ca467f8b5 1294
Kojto 102:da0ca467f8b5 1295 /* TPI Integration Mode Control Register Definitions */
Kojto 102:da0ca467f8b5 1296 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Kojto 102:da0ca467f8b5 1297 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Kojto 102:da0ca467f8b5 1298
Kojto 102:da0ca467f8b5 1299 /* TPI DEVID Register Definitions */
Kojto 102:da0ca467f8b5 1300 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
Kojto 102:da0ca467f8b5 1301 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Kojto 102:da0ca467f8b5 1302
Kojto 102:da0ca467f8b5 1303 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
Kojto 102:da0ca467f8b5 1304 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Kojto 102:da0ca467f8b5 1305
Kojto 102:da0ca467f8b5 1306 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
Kojto 102:da0ca467f8b5 1307 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Kojto 102:da0ca467f8b5 1308
Kojto 102:da0ca467f8b5 1309 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
Kojto 102:da0ca467f8b5 1310 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Kojto 102:da0ca467f8b5 1311
Kojto 102:da0ca467f8b5 1312 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
Kojto 102:da0ca467f8b5 1313 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Kojto 102:da0ca467f8b5 1314
Kojto 102:da0ca467f8b5 1315 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Kojto 102:da0ca467f8b5 1316 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Kojto 102:da0ca467f8b5 1317
Kojto 102:da0ca467f8b5 1318 /* TPI DEVTYPE Register Definitions */
Kojto 102:da0ca467f8b5 1319 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
Kojto 102:da0ca467f8b5 1320 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Kojto 102:da0ca467f8b5 1321
Kojto 102:da0ca467f8b5 1322 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Kojto 102:da0ca467f8b5 1323 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Kojto 102:da0ca467f8b5 1324
Kojto 102:da0ca467f8b5 1325 /*@}*/ /* end of group CMSIS_TPI */
Kojto 102:da0ca467f8b5 1326
Kojto 102:da0ca467f8b5 1327
Kojto 102:da0ca467f8b5 1328 #if (__MPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 1329 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 1330 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 102:da0ca467f8b5 1331 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 102:da0ca467f8b5 1332 @{
Kojto 102:da0ca467f8b5 1333 */
Kojto 102:da0ca467f8b5 1334
Kojto 102:da0ca467f8b5 1335 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 102:da0ca467f8b5 1336 */
Kojto 102:da0ca467f8b5 1337 typedef struct
Kojto 102:da0ca467f8b5 1338 {
Kojto 102:da0ca467f8b5 1339 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 102:da0ca467f8b5 1340 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 102:da0ca467f8b5 1341 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 102:da0ca467f8b5 1342 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 102:da0ca467f8b5 1343 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 102:da0ca467f8b5 1344 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Kojto 102:da0ca467f8b5 1345 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Kojto 102:da0ca467f8b5 1346 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Kojto 102:da0ca467f8b5 1347 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Kojto 102:da0ca467f8b5 1348 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Kojto 102:da0ca467f8b5 1349 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Kojto 102:da0ca467f8b5 1350 } MPU_Type;
Kojto 102:da0ca467f8b5 1351
Kojto 102:da0ca467f8b5 1352 /* MPU Type Register */
Kojto 102:da0ca467f8b5 1353 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 102:da0ca467f8b5 1354 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 102:da0ca467f8b5 1355
Kojto 102:da0ca467f8b5 1356 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 102:da0ca467f8b5 1357 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 102:da0ca467f8b5 1358
Kojto 102:da0ca467f8b5 1359 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 102:da0ca467f8b5 1360 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 102:da0ca467f8b5 1361
Kojto 102:da0ca467f8b5 1362 /* MPU Control Register */
Kojto 102:da0ca467f8b5 1363 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 102:da0ca467f8b5 1364 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 102:da0ca467f8b5 1365
Kojto 102:da0ca467f8b5 1366 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 102:da0ca467f8b5 1367 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 102:da0ca467f8b5 1368
Kojto 102:da0ca467f8b5 1369 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 102:da0ca467f8b5 1370 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 102:da0ca467f8b5 1371
Kojto 102:da0ca467f8b5 1372 /* MPU Region Number Register */
Kojto 102:da0ca467f8b5 1373 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 102:da0ca467f8b5 1374 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 102:da0ca467f8b5 1375
Kojto 102:da0ca467f8b5 1376 /* MPU Region Base Address Register */
Kojto 102:da0ca467f8b5 1377 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Kojto 102:da0ca467f8b5 1378 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 102:da0ca467f8b5 1379
Kojto 102:da0ca467f8b5 1380 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 102:da0ca467f8b5 1381 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 102:da0ca467f8b5 1382
Kojto 102:da0ca467f8b5 1383 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 102:da0ca467f8b5 1384 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 102:da0ca467f8b5 1385
Kojto 102:da0ca467f8b5 1386 /* MPU Region Attribute and Size Register */
Kojto 102:da0ca467f8b5 1387 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 102:da0ca467f8b5 1388 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 102:da0ca467f8b5 1389
Kojto 102:da0ca467f8b5 1390 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 102:da0ca467f8b5 1391 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 102:da0ca467f8b5 1392
Kojto 102:da0ca467f8b5 1393 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 102:da0ca467f8b5 1394 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 102:da0ca467f8b5 1395
Kojto 102:da0ca467f8b5 1396 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 102:da0ca467f8b5 1397 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 102:da0ca467f8b5 1398
Kojto 102:da0ca467f8b5 1399 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 102:da0ca467f8b5 1400 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 102:da0ca467f8b5 1401
Kojto 102:da0ca467f8b5 1402 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 102:da0ca467f8b5 1403 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 102:da0ca467f8b5 1404
Kojto 102:da0ca467f8b5 1405 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 102:da0ca467f8b5 1406 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 102:da0ca467f8b5 1407
Kojto 102:da0ca467f8b5 1408 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 102:da0ca467f8b5 1409 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 102:da0ca467f8b5 1410
Kojto 102:da0ca467f8b5 1411 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 102:da0ca467f8b5 1412 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 102:da0ca467f8b5 1413
Kojto 102:da0ca467f8b5 1414 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 102:da0ca467f8b5 1415 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 102:da0ca467f8b5 1416
Kojto 102:da0ca467f8b5 1417 /*@} end of group CMSIS_MPU */
Kojto 102:da0ca467f8b5 1418 #endif
Kojto 102:da0ca467f8b5 1419
Kojto 102:da0ca467f8b5 1420
Kojto 102:da0ca467f8b5 1421 #if (__FPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 1422 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 1423 \defgroup CMSIS_FPU Floating Point Unit (FPU)
Kojto 102:da0ca467f8b5 1424 \brief Type definitions for the Floating Point Unit (FPU)
Kojto 102:da0ca467f8b5 1425 @{
Kojto 102:da0ca467f8b5 1426 */
Kojto 102:da0ca467f8b5 1427
Kojto 102:da0ca467f8b5 1428 /** \brief Structure type to access the Floating Point Unit (FPU).
Kojto 102:da0ca467f8b5 1429 */
Kojto 102:da0ca467f8b5 1430 typedef struct
Kojto 102:da0ca467f8b5 1431 {
Kojto 102:da0ca467f8b5 1432 uint32_t RESERVED0[1];
Kojto 102:da0ca467f8b5 1433 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
Kojto 102:da0ca467f8b5 1434 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
Kojto 102:da0ca467f8b5 1435 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
Kojto 102:da0ca467f8b5 1436 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
Kojto 102:da0ca467f8b5 1437 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
Kojto 102:da0ca467f8b5 1438 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
Kojto 102:da0ca467f8b5 1439 } FPU_Type;
Kojto 102:da0ca467f8b5 1440
Kojto 102:da0ca467f8b5 1441 /* Floating-Point Context Control Register */
Kojto 102:da0ca467f8b5 1442 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
Kojto 102:da0ca467f8b5 1443 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
Kojto 102:da0ca467f8b5 1444
Kojto 102:da0ca467f8b5 1445 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
Kojto 102:da0ca467f8b5 1446 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
Kojto 102:da0ca467f8b5 1447
Kojto 102:da0ca467f8b5 1448 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
Kojto 102:da0ca467f8b5 1449 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
Kojto 102:da0ca467f8b5 1450
Kojto 102:da0ca467f8b5 1451 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
Kojto 102:da0ca467f8b5 1452 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
Kojto 102:da0ca467f8b5 1453
Kojto 102:da0ca467f8b5 1454 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
Kojto 102:da0ca467f8b5 1455 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
Kojto 102:da0ca467f8b5 1456
Kojto 102:da0ca467f8b5 1457 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
Kojto 102:da0ca467f8b5 1458 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
Kojto 102:da0ca467f8b5 1459
Kojto 102:da0ca467f8b5 1460 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
Kojto 102:da0ca467f8b5 1461 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
Kojto 102:da0ca467f8b5 1462
Kojto 102:da0ca467f8b5 1463 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
Kojto 102:da0ca467f8b5 1464 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
Kojto 102:da0ca467f8b5 1465
Kojto 102:da0ca467f8b5 1466 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
Kojto 102:da0ca467f8b5 1467 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
Kojto 102:da0ca467f8b5 1468
Kojto 102:da0ca467f8b5 1469 /* Floating-Point Context Address Register */
Kojto 102:da0ca467f8b5 1470 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
Kojto 102:da0ca467f8b5 1471 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
Kojto 102:da0ca467f8b5 1472
Kojto 102:da0ca467f8b5 1473 /* Floating-Point Default Status Control Register */
Kojto 102:da0ca467f8b5 1474 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
Kojto 102:da0ca467f8b5 1475 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
Kojto 102:da0ca467f8b5 1476
Kojto 102:da0ca467f8b5 1477 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
Kojto 102:da0ca467f8b5 1478 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
Kojto 102:da0ca467f8b5 1479
Kojto 102:da0ca467f8b5 1480 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
Kojto 102:da0ca467f8b5 1481 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
Kojto 102:da0ca467f8b5 1482
Kojto 102:da0ca467f8b5 1483 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
Kojto 102:da0ca467f8b5 1484 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
Kojto 102:da0ca467f8b5 1485
Kojto 102:da0ca467f8b5 1486 /* Media and FP Feature Register 0 */
Kojto 102:da0ca467f8b5 1487 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
Kojto 102:da0ca467f8b5 1488 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
Kojto 102:da0ca467f8b5 1489
Kojto 102:da0ca467f8b5 1490 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
Kojto 102:da0ca467f8b5 1491 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
Kojto 102:da0ca467f8b5 1492
Kojto 102:da0ca467f8b5 1493 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
Kojto 102:da0ca467f8b5 1494 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
Kojto 102:da0ca467f8b5 1495
Kojto 102:da0ca467f8b5 1496 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
Kojto 102:da0ca467f8b5 1497 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
Kojto 102:da0ca467f8b5 1498
Kojto 102:da0ca467f8b5 1499 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
Kojto 102:da0ca467f8b5 1500 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
Kojto 102:da0ca467f8b5 1501
Kojto 102:da0ca467f8b5 1502 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
Kojto 102:da0ca467f8b5 1503 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
Kojto 102:da0ca467f8b5 1504
Kojto 102:da0ca467f8b5 1505 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
Kojto 102:da0ca467f8b5 1506 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
Kojto 102:da0ca467f8b5 1507
Kojto 102:da0ca467f8b5 1508 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
Kojto 102:da0ca467f8b5 1509 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
Kojto 102:da0ca467f8b5 1510
Kojto 102:da0ca467f8b5 1511 /* Media and FP Feature Register 1 */
Kojto 102:da0ca467f8b5 1512 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
Kojto 102:da0ca467f8b5 1513 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
Kojto 102:da0ca467f8b5 1514
Kojto 102:da0ca467f8b5 1515 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
Kojto 102:da0ca467f8b5 1516 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
Kojto 102:da0ca467f8b5 1517
Kojto 102:da0ca467f8b5 1518 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
Kojto 102:da0ca467f8b5 1519 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
Kojto 102:da0ca467f8b5 1520
Kojto 102:da0ca467f8b5 1521 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
Kojto 102:da0ca467f8b5 1522 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
Kojto 102:da0ca467f8b5 1523
Kojto 102:da0ca467f8b5 1524 /* Media and FP Feature Register 2 */
Kojto 102:da0ca467f8b5 1525
Kojto 102:da0ca467f8b5 1526 /*@} end of group CMSIS_FPU */
Kojto 102:da0ca467f8b5 1527 #endif
Kojto 102:da0ca467f8b5 1528
Kojto 102:da0ca467f8b5 1529
Kojto 102:da0ca467f8b5 1530 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 1531 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 102:da0ca467f8b5 1532 \brief Type definitions for the Core Debug Registers
Kojto 102:da0ca467f8b5 1533 @{
Kojto 102:da0ca467f8b5 1534 */
Kojto 102:da0ca467f8b5 1535
Kojto 102:da0ca467f8b5 1536 /** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto 102:da0ca467f8b5 1537 */
Kojto 102:da0ca467f8b5 1538 typedef struct
Kojto 102:da0ca467f8b5 1539 {
Kojto 102:da0ca467f8b5 1540 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Kojto 102:da0ca467f8b5 1541 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Kojto 102:da0ca467f8b5 1542 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Kojto 102:da0ca467f8b5 1543 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Kojto 102:da0ca467f8b5 1544 } CoreDebug_Type;
Kojto 102:da0ca467f8b5 1545
Kojto 102:da0ca467f8b5 1546 /* Debug Halting Control and Status Register */
Kojto 102:da0ca467f8b5 1547 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Kojto 102:da0ca467f8b5 1548 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Kojto 102:da0ca467f8b5 1549
Kojto 102:da0ca467f8b5 1550 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Kojto 102:da0ca467f8b5 1551 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Kojto 102:da0ca467f8b5 1552
Kojto 102:da0ca467f8b5 1553 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Kojto 102:da0ca467f8b5 1554 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Kojto 102:da0ca467f8b5 1555
Kojto 102:da0ca467f8b5 1556 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Kojto 102:da0ca467f8b5 1557 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Kojto 102:da0ca467f8b5 1558
Kojto 102:da0ca467f8b5 1559 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Kojto 102:da0ca467f8b5 1560 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Kojto 102:da0ca467f8b5 1561
Kojto 102:da0ca467f8b5 1562 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Kojto 102:da0ca467f8b5 1563 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Kojto 102:da0ca467f8b5 1564
Kojto 102:da0ca467f8b5 1565 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Kojto 102:da0ca467f8b5 1566 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Kojto 102:da0ca467f8b5 1567
Kojto 102:da0ca467f8b5 1568 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Kojto 102:da0ca467f8b5 1569 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Kojto 102:da0ca467f8b5 1570
Kojto 102:da0ca467f8b5 1571 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Kojto 102:da0ca467f8b5 1572 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Kojto 102:da0ca467f8b5 1573
Kojto 102:da0ca467f8b5 1574 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Kojto 102:da0ca467f8b5 1575 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Kojto 102:da0ca467f8b5 1576
Kojto 102:da0ca467f8b5 1577 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Kojto 102:da0ca467f8b5 1578 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Kojto 102:da0ca467f8b5 1579
Kojto 102:da0ca467f8b5 1580 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 102:da0ca467f8b5 1581 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Kojto 102:da0ca467f8b5 1582
Kojto 102:da0ca467f8b5 1583 /* Debug Core Register Selector Register */
Kojto 102:da0ca467f8b5 1584 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Kojto 102:da0ca467f8b5 1585 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Kojto 102:da0ca467f8b5 1586
Kojto 102:da0ca467f8b5 1587 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 102:da0ca467f8b5 1588 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Kojto 102:da0ca467f8b5 1589
Kojto 102:da0ca467f8b5 1590 /* Debug Exception and Monitor Control Register */
Kojto 102:da0ca467f8b5 1591 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Kojto 102:da0ca467f8b5 1592 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Kojto 102:da0ca467f8b5 1593
Kojto 102:da0ca467f8b5 1594 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Kojto 102:da0ca467f8b5 1595 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Kojto 102:da0ca467f8b5 1596
Kojto 102:da0ca467f8b5 1597 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Kojto 102:da0ca467f8b5 1598 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Kojto 102:da0ca467f8b5 1599
Kojto 102:da0ca467f8b5 1600 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Kojto 102:da0ca467f8b5 1601 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Kojto 102:da0ca467f8b5 1602
Kojto 102:da0ca467f8b5 1603 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Kojto 102:da0ca467f8b5 1604 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Kojto 102:da0ca467f8b5 1605
Kojto 102:da0ca467f8b5 1606 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Kojto 102:da0ca467f8b5 1607 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Kojto 102:da0ca467f8b5 1608
Kojto 102:da0ca467f8b5 1609 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Kojto 102:da0ca467f8b5 1610 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Kojto 102:da0ca467f8b5 1611
Kojto 102:da0ca467f8b5 1612 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Kojto 102:da0ca467f8b5 1613 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Kojto 102:da0ca467f8b5 1614
Kojto 102:da0ca467f8b5 1615 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Kojto 102:da0ca467f8b5 1616 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Kojto 102:da0ca467f8b5 1617
Kojto 102:da0ca467f8b5 1618 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Kojto 102:da0ca467f8b5 1619 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Kojto 102:da0ca467f8b5 1620
Kojto 102:da0ca467f8b5 1621 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Kojto 102:da0ca467f8b5 1622 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Kojto 102:da0ca467f8b5 1623
Kojto 102:da0ca467f8b5 1624 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Kojto 102:da0ca467f8b5 1625 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Kojto 102:da0ca467f8b5 1626
Kojto 102:da0ca467f8b5 1627 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 102:da0ca467f8b5 1628 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Kojto 102:da0ca467f8b5 1629
Kojto 102:da0ca467f8b5 1630 /*@} end of group CMSIS_CoreDebug */
Kojto 102:da0ca467f8b5 1631
Kojto 102:da0ca467f8b5 1632
Kojto 102:da0ca467f8b5 1633 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 1634 \defgroup CMSIS_core_base Core Definitions
Kojto 102:da0ca467f8b5 1635 \brief Definitions for base addresses, unions, and structures.
Kojto 102:da0ca467f8b5 1636 @{
Kojto 102:da0ca467f8b5 1637 */
Kojto 102:da0ca467f8b5 1638
Kojto 102:da0ca467f8b5 1639 /* Memory mapping of Cortex-M4 Hardware */
Kojto 102:da0ca467f8b5 1640 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 102:da0ca467f8b5 1641 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Kojto 102:da0ca467f8b5 1642 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Kojto 102:da0ca467f8b5 1643 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Kojto 102:da0ca467f8b5 1644 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Kojto 102:da0ca467f8b5 1645 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 102:da0ca467f8b5 1646 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 102:da0ca467f8b5 1647 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 102:da0ca467f8b5 1648
Kojto 102:da0ca467f8b5 1649 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Kojto 102:da0ca467f8b5 1650 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 102:da0ca467f8b5 1651 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 102:da0ca467f8b5 1652 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 102:da0ca467f8b5 1653 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Kojto 102:da0ca467f8b5 1654 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Kojto 102:da0ca467f8b5 1655 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Kojto 102:da0ca467f8b5 1656 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Kojto 102:da0ca467f8b5 1657
Kojto 102:da0ca467f8b5 1658 #if (__MPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 1659 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 102:da0ca467f8b5 1660 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 102:da0ca467f8b5 1661 #endif
Kojto 102:da0ca467f8b5 1662
Kojto 102:da0ca467f8b5 1663 #if (__FPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 1664 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
Kojto 102:da0ca467f8b5 1665 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
Kojto 102:da0ca467f8b5 1666 #endif
Kojto 102:da0ca467f8b5 1667
Kojto 102:da0ca467f8b5 1668 /*@} */
Kojto 102:da0ca467f8b5 1669
Kojto 102:da0ca467f8b5 1670
Kojto 102:da0ca467f8b5 1671
Kojto 102:da0ca467f8b5 1672 /*******************************************************************************
Kojto 102:da0ca467f8b5 1673 * Hardware Abstraction Layer
Kojto 102:da0ca467f8b5 1674 Core Function Interface contains:
Kojto 102:da0ca467f8b5 1675 - Core NVIC Functions
Kojto 102:da0ca467f8b5 1676 - Core SysTick Functions
Kojto 102:da0ca467f8b5 1677 - Core Debug Functions
Kojto 102:da0ca467f8b5 1678 - Core Register Access Functions
Kojto 102:da0ca467f8b5 1679 ******************************************************************************/
Kojto 102:da0ca467f8b5 1680 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 102:da0ca467f8b5 1681 */
Kojto 102:da0ca467f8b5 1682
Kojto 102:da0ca467f8b5 1683
Kojto 102:da0ca467f8b5 1684
Kojto 102:da0ca467f8b5 1685 /* ########################## NVIC functions #################################### */
Kojto 102:da0ca467f8b5 1686 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 102:da0ca467f8b5 1687 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 102:da0ca467f8b5 1688 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 102:da0ca467f8b5 1689 @{
Kojto 102:da0ca467f8b5 1690 */
Kojto 102:da0ca467f8b5 1691
Kojto 102:da0ca467f8b5 1692 /** \brief Set Priority Grouping
Kojto 102:da0ca467f8b5 1693
Kojto 102:da0ca467f8b5 1694 The function sets the priority grouping field using the required unlock sequence.
Kojto 102:da0ca467f8b5 1695 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto 102:da0ca467f8b5 1696 Only values from 0..7 are used.
Kojto 102:da0ca467f8b5 1697 In case of a conflict between priority grouping and available
Kojto 102:da0ca467f8b5 1698 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 102:da0ca467f8b5 1699
Kojto 102:da0ca467f8b5 1700 \param [in] PriorityGroup Priority grouping field.
Kojto 102:da0ca467f8b5 1701 */
Kojto 102:da0ca467f8b5 1702 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto 102:da0ca467f8b5 1703 {
Kojto 102:da0ca467f8b5 1704 uint32_t reg_value;
Kojto 102:da0ca467f8b5 1705 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 102:da0ca467f8b5 1706
Kojto 102:da0ca467f8b5 1707 reg_value = SCB->AIRCR; /* read old register configuration */
Kojto 102:da0ca467f8b5 1708 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto 102:da0ca467f8b5 1709 reg_value = (reg_value |
Kojto 102:da0ca467f8b5 1710 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 102:da0ca467f8b5 1711 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Kojto 102:da0ca467f8b5 1712 SCB->AIRCR = reg_value;
Kojto 102:da0ca467f8b5 1713 }
Kojto 102:da0ca467f8b5 1714
Kojto 102:da0ca467f8b5 1715
Kojto 102:da0ca467f8b5 1716 /** \brief Get Priority Grouping
Kojto 102:da0ca467f8b5 1717
Kojto 102:da0ca467f8b5 1718 The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto 102:da0ca467f8b5 1719
Kojto 102:da0ca467f8b5 1720 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto 102:da0ca467f8b5 1721 */
Kojto 102:da0ca467f8b5 1722 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kojto 102:da0ca467f8b5 1723 {
Kojto 102:da0ca467f8b5 1724 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto 102:da0ca467f8b5 1725 }
Kojto 102:da0ca467f8b5 1726
Kojto 102:da0ca467f8b5 1727
Kojto 102:da0ca467f8b5 1728 /** \brief Enable External Interrupt
Kojto 102:da0ca467f8b5 1729
Kojto 102:da0ca467f8b5 1730 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 102:da0ca467f8b5 1731
Kojto 102:da0ca467f8b5 1732 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 1733 */
Kojto 102:da0ca467f8b5 1734 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 1735 {
Kojto 102:da0ca467f8b5 1736 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 102:da0ca467f8b5 1737 }
Kojto 102:da0ca467f8b5 1738
Kojto 102:da0ca467f8b5 1739
Kojto 102:da0ca467f8b5 1740 /** \brief Disable External Interrupt
Kojto 102:da0ca467f8b5 1741
Kojto 102:da0ca467f8b5 1742 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 102:da0ca467f8b5 1743
Kojto 102:da0ca467f8b5 1744 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 1745 */
Kojto 102:da0ca467f8b5 1746 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 1747 {
Kojto 102:da0ca467f8b5 1748 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 102:da0ca467f8b5 1749 }
Kojto 102:da0ca467f8b5 1750
Kojto 102:da0ca467f8b5 1751
Kojto 102:da0ca467f8b5 1752 /** \brief Get Pending Interrupt
Kojto 102:da0ca467f8b5 1753
Kojto 102:da0ca467f8b5 1754 The function reads the pending register in the NVIC and returns the pending bit
Kojto 102:da0ca467f8b5 1755 for the specified interrupt.
Kojto 102:da0ca467f8b5 1756
Kojto 102:da0ca467f8b5 1757 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 1758
Kojto 102:da0ca467f8b5 1759 \return 0 Interrupt status is not pending.
Kojto 102:da0ca467f8b5 1760 \return 1 Interrupt status is pending.
Kojto 102:da0ca467f8b5 1761 */
Kojto 102:da0ca467f8b5 1762 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 1763 {
Kojto 102:da0ca467f8b5 1764 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 102:da0ca467f8b5 1765 }
Kojto 102:da0ca467f8b5 1766
Kojto 102:da0ca467f8b5 1767
Kojto 102:da0ca467f8b5 1768 /** \brief Set Pending Interrupt
Kojto 102:da0ca467f8b5 1769
Kojto 102:da0ca467f8b5 1770 The function sets the pending bit of an external interrupt.
Kojto 102:da0ca467f8b5 1771
Kojto 102:da0ca467f8b5 1772 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 1773 */
Kojto 102:da0ca467f8b5 1774 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 1775 {
Kojto 102:da0ca467f8b5 1776 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 102:da0ca467f8b5 1777 }
Kojto 102:da0ca467f8b5 1778
Kojto 102:da0ca467f8b5 1779
Kojto 102:da0ca467f8b5 1780 /** \brief Clear Pending Interrupt
Kojto 102:da0ca467f8b5 1781
Kojto 102:da0ca467f8b5 1782 The function clears the pending bit of an external interrupt.
Kojto 102:da0ca467f8b5 1783
Kojto 102:da0ca467f8b5 1784 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 1785 */
Kojto 102:da0ca467f8b5 1786 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 1787 {
Kojto 102:da0ca467f8b5 1788 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 102:da0ca467f8b5 1789 }
Kojto 102:da0ca467f8b5 1790
Kojto 102:da0ca467f8b5 1791
Kojto 102:da0ca467f8b5 1792 /** \brief Get Active Interrupt
Kojto 102:da0ca467f8b5 1793
Kojto 102:da0ca467f8b5 1794 The function reads the active register in NVIC and returns the active bit.
Kojto 102:da0ca467f8b5 1795
Kojto 102:da0ca467f8b5 1796 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 1797
Kojto 102:da0ca467f8b5 1798 \return 0 Interrupt status is not active.
Kojto 102:da0ca467f8b5 1799 \return 1 Interrupt status is active.
Kojto 102:da0ca467f8b5 1800 */
Kojto 102:da0ca467f8b5 1801 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 1802 {
Kojto 102:da0ca467f8b5 1803 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 102:da0ca467f8b5 1804 }
Kojto 102:da0ca467f8b5 1805
Kojto 102:da0ca467f8b5 1806
Kojto 102:da0ca467f8b5 1807 /** \brief Set Interrupt Priority
Kojto 102:da0ca467f8b5 1808
Kojto 102:da0ca467f8b5 1809 The function sets the priority of an interrupt.
Kojto 102:da0ca467f8b5 1810
Kojto 102:da0ca467f8b5 1811 \note The priority cannot be set for every core interrupt.
Kojto 102:da0ca467f8b5 1812
Kojto 102:da0ca467f8b5 1813 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 1814 \param [in] priority Priority to set.
Kojto 102:da0ca467f8b5 1815 */
Kojto 102:da0ca467f8b5 1816 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 102:da0ca467f8b5 1817 {
Kojto 102:da0ca467f8b5 1818 if((int32_t)IRQn < 0) {
Kojto 102:da0ca467f8b5 1819 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 102:da0ca467f8b5 1820 }
Kojto 102:da0ca467f8b5 1821 else {
Kojto 102:da0ca467f8b5 1822 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 102:da0ca467f8b5 1823 }
Kojto 102:da0ca467f8b5 1824 }
Kojto 102:da0ca467f8b5 1825
Kojto 102:da0ca467f8b5 1826
Kojto 102:da0ca467f8b5 1827 /** \brief Get Interrupt Priority
Kojto 102:da0ca467f8b5 1828
Kojto 102:da0ca467f8b5 1829 The function reads the priority of an interrupt. The interrupt
Kojto 102:da0ca467f8b5 1830 number can be positive to specify an external (device specific)
Kojto 102:da0ca467f8b5 1831 interrupt, or negative to specify an internal (core) interrupt.
Kojto 102:da0ca467f8b5 1832
Kojto 102:da0ca467f8b5 1833
Kojto 102:da0ca467f8b5 1834 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 1835 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 102:da0ca467f8b5 1836 priority bits of the microcontroller.
Kojto 102:da0ca467f8b5 1837 */
Kojto 102:da0ca467f8b5 1838 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 1839 {
Kojto 102:da0ca467f8b5 1840
Kojto 102:da0ca467f8b5 1841 if((int32_t)IRQn < 0) {
Kojto 102:da0ca467f8b5 1842 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto 102:da0ca467f8b5 1843 }
Kojto 102:da0ca467f8b5 1844 else {
Kojto 102:da0ca467f8b5 1845 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto 102:da0ca467f8b5 1846 }
Kojto 102:da0ca467f8b5 1847 }
Kojto 102:da0ca467f8b5 1848
Kojto 102:da0ca467f8b5 1849
Kojto 102:da0ca467f8b5 1850 /** \brief Encode Priority
Kojto 102:da0ca467f8b5 1851
Kojto 102:da0ca467f8b5 1852 The function encodes the priority for an interrupt with the given priority group,
Kojto 102:da0ca467f8b5 1853 preemptive priority value, and subpriority value.
Kojto 102:da0ca467f8b5 1854 In case of a conflict between priority grouping and available
Kojto 102:da0ca467f8b5 1855 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 102:da0ca467f8b5 1856
Kojto 102:da0ca467f8b5 1857 \param [in] PriorityGroup Used priority group.
Kojto 102:da0ca467f8b5 1858 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto 102:da0ca467f8b5 1859 \param [in] SubPriority Subpriority value (starting from 0).
Kojto 102:da0ca467f8b5 1860 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto 102:da0ca467f8b5 1861 */
Kojto 102:da0ca467f8b5 1862 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto 102:da0ca467f8b5 1863 {
Kojto 102:da0ca467f8b5 1864 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 102:da0ca467f8b5 1865 uint32_t PreemptPriorityBits;
Kojto 102:da0ca467f8b5 1866 uint32_t SubPriorityBits;
Kojto 102:da0ca467f8b5 1867
Kojto 102:da0ca467f8b5 1868 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 102:da0ca467f8b5 1869 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 102:da0ca467f8b5 1870
Kojto 102:da0ca467f8b5 1871 return (
Kojto 102:da0ca467f8b5 1872 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Kojto 102:da0ca467f8b5 1873 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto 102:da0ca467f8b5 1874 );
Kojto 102:da0ca467f8b5 1875 }
Kojto 102:da0ca467f8b5 1876
Kojto 102:da0ca467f8b5 1877
Kojto 102:da0ca467f8b5 1878 /** \brief Decode Priority
Kojto 102:da0ca467f8b5 1879
Kojto 102:da0ca467f8b5 1880 The function decodes an interrupt priority value with a given priority group to
Kojto 102:da0ca467f8b5 1881 preemptive priority value and subpriority value.
Kojto 102:da0ca467f8b5 1882 In case of a conflict between priority grouping and available
Kojto 102:da0ca467f8b5 1883 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto 102:da0ca467f8b5 1884
Kojto 102:da0ca467f8b5 1885 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto 102:da0ca467f8b5 1886 \param [in] PriorityGroup Used priority group.
Kojto 102:da0ca467f8b5 1887 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto 102:da0ca467f8b5 1888 \param [out] pSubPriority Subpriority value (starting from 0).
Kojto 102:da0ca467f8b5 1889 */
Kojto 102:da0ca467f8b5 1890 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto 102:da0ca467f8b5 1891 {
Kojto 102:da0ca467f8b5 1892 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 102:da0ca467f8b5 1893 uint32_t PreemptPriorityBits;
Kojto 102:da0ca467f8b5 1894 uint32_t SubPriorityBits;
Kojto 102:da0ca467f8b5 1895
Kojto 102:da0ca467f8b5 1896 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 102:da0ca467f8b5 1897 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 102:da0ca467f8b5 1898
Kojto 102:da0ca467f8b5 1899 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto 102:da0ca467f8b5 1900 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto 102:da0ca467f8b5 1901 }
Kojto 102:da0ca467f8b5 1902
Kojto 102:da0ca467f8b5 1903
Kojto 102:da0ca467f8b5 1904 /** \brief System Reset
Kojto 102:da0ca467f8b5 1905
Kojto 102:da0ca467f8b5 1906 The function initiates a system reset request to reset the MCU.
Kojto 102:da0ca467f8b5 1907 */
Kojto 102:da0ca467f8b5 1908 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 102:da0ca467f8b5 1909 {
Kojto 102:da0ca467f8b5 1910 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 102:da0ca467f8b5 1911 buffered write are completed before reset */
Kojto 102:da0ca467f8b5 1912 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 102:da0ca467f8b5 1913 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 102:da0ca467f8b5 1914 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto 102:da0ca467f8b5 1915 __DSB(); /* Ensure completion of memory access */
Kojto 102:da0ca467f8b5 1916 while(1) { __NOP(); } /* wait until reset */
Kojto 102:da0ca467f8b5 1917 }
Kojto 102:da0ca467f8b5 1918
Kojto 102:da0ca467f8b5 1919 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 102:da0ca467f8b5 1920
Kojto 102:da0ca467f8b5 1921
Kojto 102:da0ca467f8b5 1922 /* ########################## FPU functions #################################### */
Kojto 102:da0ca467f8b5 1923 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 102:da0ca467f8b5 1924 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Kojto 102:da0ca467f8b5 1925 \brief Function that provides FPU type.
Kojto 102:da0ca467f8b5 1926 @{
Kojto 102:da0ca467f8b5 1927 */
Kojto 102:da0ca467f8b5 1928
Kojto 102:da0ca467f8b5 1929 /**
Kojto 102:da0ca467f8b5 1930 \fn uint32_t SCB_GetFPUType(void)
Kojto 102:da0ca467f8b5 1931 \brief get FPU type
Kojto 102:da0ca467f8b5 1932 \returns
Kojto 102:da0ca467f8b5 1933 - \b 0: No FPU
Kojto 102:da0ca467f8b5 1934 - \b 1: Single precision FPU
Kojto 102:da0ca467f8b5 1935 - \b 2: Double + Single precision FPU
Kojto 102:da0ca467f8b5 1936 */
Kojto 102:da0ca467f8b5 1937 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Kojto 102:da0ca467f8b5 1938 {
Kojto 102:da0ca467f8b5 1939 uint32_t mvfr0;
Kojto 102:da0ca467f8b5 1940
Kojto 102:da0ca467f8b5 1941 mvfr0 = SCB->MVFR0;
Kojto 102:da0ca467f8b5 1942 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
Kojto 102:da0ca467f8b5 1943 return 2UL; // Double + Single precision FPU
Kojto 102:da0ca467f8b5 1944 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
Kojto 102:da0ca467f8b5 1945 return 1UL; // Single precision FPU
Kojto 102:da0ca467f8b5 1946 } else {
Kojto 102:da0ca467f8b5 1947 return 0UL; // No FPU
Kojto 102:da0ca467f8b5 1948 }
Kojto 102:da0ca467f8b5 1949 }
Kojto 102:da0ca467f8b5 1950
Kojto 102:da0ca467f8b5 1951
Kojto 102:da0ca467f8b5 1952 /*@} end of CMSIS_Core_FpuFunctions */
Kojto 102:da0ca467f8b5 1953
Kojto 102:da0ca467f8b5 1954
Kojto 102:da0ca467f8b5 1955
Kojto 102:da0ca467f8b5 1956 /* ########################## Cache functions #################################### */
Kojto 102:da0ca467f8b5 1957 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 102:da0ca467f8b5 1958 \defgroup CMSIS_Core_CacheFunctions Cache Functions
Kojto 102:da0ca467f8b5 1959 \brief Functions that configure Instruction and Data cache.
Kojto 102:da0ca467f8b5 1960 @{
Kojto 102:da0ca467f8b5 1961 */
Kojto 102:da0ca467f8b5 1962
Kojto 102:da0ca467f8b5 1963 /* Cache Size ID Register Macros */
Kojto 102:da0ca467f8b5 1964 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
Kojto 102:da0ca467f8b5 1965 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
Kojto 102:da0ca467f8b5 1966 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
Kojto 102:da0ca467f8b5 1967
Kojto 102:da0ca467f8b5 1968
Kojto 102:da0ca467f8b5 1969 /** \brief Enable I-Cache
Kojto 102:da0ca467f8b5 1970
Kojto 102:da0ca467f8b5 1971 The function turns on I-Cache
Kojto 102:da0ca467f8b5 1972 */
Kojto 102:da0ca467f8b5 1973 __STATIC_INLINE void SCB_EnableICache (void)
Kojto 102:da0ca467f8b5 1974 {
Kojto 102:da0ca467f8b5 1975 #if (__ICACHE_PRESENT == 1)
Kojto 102:da0ca467f8b5 1976 __DSB();
Kojto 102:da0ca467f8b5 1977 __ISB();
Kojto 102:da0ca467f8b5 1978 SCB->ICIALLU = 0UL; // invalidate I-Cache
Kojto 102:da0ca467f8b5 1979 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
Kojto 102:da0ca467f8b5 1980 __DSB();
Kojto 102:da0ca467f8b5 1981 __ISB();
Kojto 102:da0ca467f8b5 1982 #endif
Kojto 102:da0ca467f8b5 1983 }
Kojto 102:da0ca467f8b5 1984
Kojto 102:da0ca467f8b5 1985
Kojto 102:da0ca467f8b5 1986 /** \brief Disable I-Cache
Kojto 102:da0ca467f8b5 1987
Kojto 102:da0ca467f8b5 1988 The function turns off I-Cache
Kojto 102:da0ca467f8b5 1989 */
Kojto 102:da0ca467f8b5 1990 __STATIC_INLINE void SCB_DisableICache (void)
Kojto 102:da0ca467f8b5 1991 {
Kojto 102:da0ca467f8b5 1992 #if (__ICACHE_PRESENT == 1)
Kojto 102:da0ca467f8b5 1993 __DSB();
Kojto 102:da0ca467f8b5 1994 __ISB();
Kojto 102:da0ca467f8b5 1995 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
Kojto 102:da0ca467f8b5 1996 SCB->ICIALLU = 0UL; // invalidate I-Cache
Kojto 102:da0ca467f8b5 1997 __DSB();
Kojto 102:da0ca467f8b5 1998 __ISB();
Kojto 102:da0ca467f8b5 1999 #endif
Kojto 102:da0ca467f8b5 2000 }
Kojto 102:da0ca467f8b5 2001
Kojto 102:da0ca467f8b5 2002
Kojto 102:da0ca467f8b5 2003 /** \brief Invalidate I-Cache
Kojto 102:da0ca467f8b5 2004
Kojto 102:da0ca467f8b5 2005 The function invalidates I-Cache
Kojto 102:da0ca467f8b5 2006 */
Kojto 102:da0ca467f8b5 2007 __STATIC_INLINE void SCB_InvalidateICache (void)
Kojto 102:da0ca467f8b5 2008 {
Kojto 102:da0ca467f8b5 2009 #if (__ICACHE_PRESENT == 1)
Kojto 102:da0ca467f8b5 2010 __DSB();
Kojto 102:da0ca467f8b5 2011 __ISB();
Kojto 102:da0ca467f8b5 2012 SCB->ICIALLU = 0UL;
Kojto 102:da0ca467f8b5 2013 __DSB();
Kojto 102:da0ca467f8b5 2014 __ISB();
Kojto 102:da0ca467f8b5 2015 #endif
Kojto 102:da0ca467f8b5 2016 }
Kojto 102:da0ca467f8b5 2017
Kojto 102:da0ca467f8b5 2018
Kojto 102:da0ca467f8b5 2019 /** \brief Enable D-Cache
Kojto 102:da0ca467f8b5 2020
Kojto 102:da0ca467f8b5 2021 The function turns on D-Cache
Kojto 102:da0ca467f8b5 2022 */
Kojto 102:da0ca467f8b5 2023 __STATIC_INLINE void SCB_EnableDCache (void)
Kojto 102:da0ca467f8b5 2024 {
Kojto 102:da0ca467f8b5 2025 #if (__DCACHE_PRESENT == 1)
Kojto 102:da0ca467f8b5 2026 uint32_t ccsidr, sshift, wshift, sw;
Kojto 102:da0ca467f8b5 2027 uint32_t sets, ways;
Kojto 102:da0ca467f8b5 2028
Kojto 102:da0ca467f8b5 2029 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 102:da0ca467f8b5 2030 ccsidr = SCB->CCSIDR;
Kojto 102:da0ca467f8b5 2031 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 102:da0ca467f8b5 2032 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 102:da0ca467f8b5 2033 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 102:da0ca467f8b5 2034 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 102:da0ca467f8b5 2035
Kojto 102:da0ca467f8b5 2036 __DSB();
Kojto 102:da0ca467f8b5 2037
Kojto 102:da0ca467f8b5 2038 do { // invalidate D-Cache
Kojto 102:da0ca467f8b5 2039 uint32_t tmpways = ways;
Kojto 102:da0ca467f8b5 2040 do {
Kojto 102:da0ca467f8b5 2041 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 102:da0ca467f8b5 2042 SCB->DCISW = sw;
Kojto 102:da0ca467f8b5 2043 } while(tmpways--);
Kojto 102:da0ca467f8b5 2044 } while(sets--);
Kojto 102:da0ca467f8b5 2045 __DSB();
Kojto 102:da0ca467f8b5 2046
Kojto 102:da0ca467f8b5 2047 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
Kojto 102:da0ca467f8b5 2048
Kojto 102:da0ca467f8b5 2049 __DSB();
Kojto 102:da0ca467f8b5 2050 __ISB();
Kojto 102:da0ca467f8b5 2051 #endif
Kojto 102:da0ca467f8b5 2052 }
Kojto 102:da0ca467f8b5 2053
Kojto 102:da0ca467f8b5 2054
Kojto 102:da0ca467f8b5 2055 /** \brief Disable D-Cache
Kojto 102:da0ca467f8b5 2056
Kojto 102:da0ca467f8b5 2057 The function turns off D-Cache
Kojto 102:da0ca467f8b5 2058 */
Kojto 102:da0ca467f8b5 2059 __STATIC_INLINE void SCB_DisableDCache (void)
Kojto 102:da0ca467f8b5 2060 {
Kojto 102:da0ca467f8b5 2061 #if (__DCACHE_PRESENT == 1)
Kojto 102:da0ca467f8b5 2062 uint32_t ccsidr, sshift, wshift, sw;
Kojto 102:da0ca467f8b5 2063 uint32_t sets, ways;
Kojto 102:da0ca467f8b5 2064
Kojto 102:da0ca467f8b5 2065 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 102:da0ca467f8b5 2066 ccsidr = SCB->CCSIDR;
Kojto 102:da0ca467f8b5 2067 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 102:da0ca467f8b5 2068 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 102:da0ca467f8b5 2069 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 102:da0ca467f8b5 2070 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 102:da0ca467f8b5 2071
Kojto 102:da0ca467f8b5 2072 __DSB();
Kojto 102:da0ca467f8b5 2073
Kojto 102:da0ca467f8b5 2074 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
Kojto 102:da0ca467f8b5 2075
Kojto 102:da0ca467f8b5 2076 do { // clean & invalidate D-Cache
Kojto 102:da0ca467f8b5 2077 uint32_t tmpways = ways;
Kojto 102:da0ca467f8b5 2078 do {
Kojto 102:da0ca467f8b5 2079 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 102:da0ca467f8b5 2080 SCB->DCCISW = sw;
Kojto 102:da0ca467f8b5 2081 } while(tmpways--);
Kojto 102:da0ca467f8b5 2082 } while(sets--);
Kojto 102:da0ca467f8b5 2083
Kojto 102:da0ca467f8b5 2084
Kojto 102:da0ca467f8b5 2085 __DSB();
Kojto 102:da0ca467f8b5 2086 __ISB();
Kojto 102:da0ca467f8b5 2087 #endif
Kojto 102:da0ca467f8b5 2088 }
Kojto 102:da0ca467f8b5 2089
Kojto 102:da0ca467f8b5 2090
Kojto 102:da0ca467f8b5 2091 /** \brief Invalidate D-Cache
Kojto 102:da0ca467f8b5 2092
Kojto 102:da0ca467f8b5 2093 The function invalidates D-Cache
Kojto 102:da0ca467f8b5 2094 */
Kojto 102:da0ca467f8b5 2095 __STATIC_INLINE void SCB_InvalidateDCache (void)
Kojto 102:da0ca467f8b5 2096 {
Kojto 102:da0ca467f8b5 2097 #if (__DCACHE_PRESENT == 1)
Kojto 102:da0ca467f8b5 2098 uint32_t ccsidr, sshift, wshift, sw;
Kojto 102:da0ca467f8b5 2099 uint32_t sets, ways;
Kojto 102:da0ca467f8b5 2100
Kojto 102:da0ca467f8b5 2101 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 102:da0ca467f8b5 2102 ccsidr = SCB->CCSIDR;
Kojto 102:da0ca467f8b5 2103 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 102:da0ca467f8b5 2104 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 102:da0ca467f8b5 2105 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 102:da0ca467f8b5 2106 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 102:da0ca467f8b5 2107
Kojto 102:da0ca467f8b5 2108 __DSB();
Kojto 102:da0ca467f8b5 2109
Kojto 102:da0ca467f8b5 2110 do { // invalidate D-Cache
Kojto 102:da0ca467f8b5 2111 uint32_t tmpways = ways;
Kojto 102:da0ca467f8b5 2112 do {
Kojto 102:da0ca467f8b5 2113 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 102:da0ca467f8b5 2114 SCB->DCISW = sw;
Kojto 102:da0ca467f8b5 2115 } while(tmpways--);
Kojto 102:da0ca467f8b5 2116 } while(sets--);
Kojto 102:da0ca467f8b5 2117
Kojto 102:da0ca467f8b5 2118 __DSB();
Kojto 102:da0ca467f8b5 2119 __ISB();
Kojto 102:da0ca467f8b5 2120 #endif
Kojto 102:da0ca467f8b5 2121 }
Kojto 102:da0ca467f8b5 2122
Kojto 102:da0ca467f8b5 2123
Kojto 102:da0ca467f8b5 2124 /** \brief Clean D-Cache
Kojto 102:da0ca467f8b5 2125
Kojto 102:da0ca467f8b5 2126 The function cleans D-Cache
Kojto 102:da0ca467f8b5 2127 */
Kojto 102:da0ca467f8b5 2128 __STATIC_INLINE void SCB_CleanDCache (void)
Kojto 102:da0ca467f8b5 2129 {
Kojto 102:da0ca467f8b5 2130 #if (__DCACHE_PRESENT == 1)
Kojto 102:da0ca467f8b5 2131 uint32_t ccsidr, sshift, wshift, sw;
Kojto 102:da0ca467f8b5 2132 uint32_t sets, ways;
Kojto 102:da0ca467f8b5 2133
Kojto 102:da0ca467f8b5 2134 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 102:da0ca467f8b5 2135 ccsidr = SCB->CCSIDR;
Kojto 102:da0ca467f8b5 2136 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 102:da0ca467f8b5 2137 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 102:da0ca467f8b5 2138 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 102:da0ca467f8b5 2139 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 102:da0ca467f8b5 2140
Kojto 102:da0ca467f8b5 2141 __DSB();
Kojto 102:da0ca467f8b5 2142
Kojto 102:da0ca467f8b5 2143 do { // clean D-Cache
Kojto 102:da0ca467f8b5 2144 uint32_t tmpways = ways;
Kojto 102:da0ca467f8b5 2145 do {
Kojto 102:da0ca467f8b5 2146 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 102:da0ca467f8b5 2147 SCB->DCCSW = sw;
Kojto 102:da0ca467f8b5 2148 } while(tmpways--);
Kojto 102:da0ca467f8b5 2149 } while(sets--);
Kojto 102:da0ca467f8b5 2150
Kojto 102:da0ca467f8b5 2151 __DSB();
Kojto 102:da0ca467f8b5 2152 __ISB();
Kojto 102:da0ca467f8b5 2153 #endif
Kojto 102:da0ca467f8b5 2154 }
Kojto 102:da0ca467f8b5 2155
Kojto 102:da0ca467f8b5 2156
Kojto 102:da0ca467f8b5 2157 /** \brief Clean & Invalidate D-Cache
Kojto 102:da0ca467f8b5 2158
Kojto 102:da0ca467f8b5 2159 The function cleans and Invalidates D-Cache
Kojto 102:da0ca467f8b5 2160 */
Kojto 102:da0ca467f8b5 2161 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
Kojto 102:da0ca467f8b5 2162 {
Kojto 102:da0ca467f8b5 2163 #if (__DCACHE_PRESENT == 1)
Kojto 102:da0ca467f8b5 2164 uint32_t ccsidr, sshift, wshift, sw;
Kojto 102:da0ca467f8b5 2165 uint32_t sets, ways;
Kojto 102:da0ca467f8b5 2166
Kojto 102:da0ca467f8b5 2167 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 102:da0ca467f8b5 2168 ccsidr = SCB->CCSIDR;
Kojto 102:da0ca467f8b5 2169 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 102:da0ca467f8b5 2170 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 102:da0ca467f8b5 2171 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 102:da0ca467f8b5 2172 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 102:da0ca467f8b5 2173
Kojto 102:da0ca467f8b5 2174 __DSB();
Kojto 102:da0ca467f8b5 2175
Kojto 102:da0ca467f8b5 2176 do { // clean & invalidate D-Cache
Kojto 102:da0ca467f8b5 2177 uint32_t tmpways = ways;
Kojto 102:da0ca467f8b5 2178 do {
Kojto 102:da0ca467f8b5 2179 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 102:da0ca467f8b5 2180 SCB->DCCISW = sw;
Kojto 102:da0ca467f8b5 2181 } while(tmpways--);
Kojto 102:da0ca467f8b5 2182 } while(sets--);
Kojto 102:da0ca467f8b5 2183
Kojto 102:da0ca467f8b5 2184 __DSB();
Kojto 102:da0ca467f8b5 2185 __ISB();
Kojto 102:da0ca467f8b5 2186 #endif
Kojto 102:da0ca467f8b5 2187 }
Kojto 102:da0ca467f8b5 2188
Kojto 102:da0ca467f8b5 2189
Kojto 102:da0ca467f8b5 2190 /**
Kojto 102:da0ca467f8b5 2191 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Kojto 102:da0ca467f8b5 2192 \brief D-Cache Invalidate by address
Kojto 102:da0ca467f8b5 2193 \param[in] addr address (aligned to 32-byte boundary)
Kojto 102:da0ca467f8b5 2194 \param[in] dsize size of memory block (in number of bytes)
Kojto 102:da0ca467f8b5 2195 */
Kojto 102:da0ca467f8b5 2196 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Kojto 102:da0ca467f8b5 2197 {
Kojto 102:da0ca467f8b5 2198 #if (__DCACHE_PRESENT == 1)
Kojto 102:da0ca467f8b5 2199 int32_t op_size = dsize;
Kojto 102:da0ca467f8b5 2200 uint32_t op_addr = (uint32_t)addr;
Kojto 102:da0ca467f8b5 2201 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Kojto 102:da0ca467f8b5 2202
Kojto 102:da0ca467f8b5 2203 __DSB();
Kojto 102:da0ca467f8b5 2204
Kojto 102:da0ca467f8b5 2205 while (op_size > 0) {
Kojto 102:da0ca467f8b5 2206 SCB->DCIMVAC = op_addr;
Kojto 102:da0ca467f8b5 2207 op_addr += linesize;
Kojto 102:da0ca467f8b5 2208 op_size -= (int32_t)linesize;
Kojto 102:da0ca467f8b5 2209 }
Kojto 102:da0ca467f8b5 2210
Kojto 102:da0ca467f8b5 2211 __DSB();
Kojto 102:da0ca467f8b5 2212 __ISB();
Kojto 102:da0ca467f8b5 2213 #endif
Kojto 102:da0ca467f8b5 2214 }
Kojto 102:da0ca467f8b5 2215
Kojto 102:da0ca467f8b5 2216
Kojto 102:da0ca467f8b5 2217 /**
Kojto 102:da0ca467f8b5 2218 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Kojto 102:da0ca467f8b5 2219 \brief D-Cache Clean by address
Kojto 102:da0ca467f8b5 2220 \param[in] addr address (aligned to 32-byte boundary)
Kojto 102:da0ca467f8b5 2221 \param[in] dsize size of memory block (in number of bytes)
Kojto 102:da0ca467f8b5 2222 */
Kojto 102:da0ca467f8b5 2223 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
Kojto 102:da0ca467f8b5 2224 {
Kojto 102:da0ca467f8b5 2225 #if (__DCACHE_PRESENT == 1)
Kojto 102:da0ca467f8b5 2226 int32_t op_size = dsize;
Kojto 102:da0ca467f8b5 2227 uint32_t op_addr = (uint32_t) addr;
Kojto 102:da0ca467f8b5 2228 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Kojto 102:da0ca467f8b5 2229
Kojto 102:da0ca467f8b5 2230 __DSB();
Kojto 102:da0ca467f8b5 2231
Kojto 102:da0ca467f8b5 2232 while (op_size > 0) {
Kojto 102:da0ca467f8b5 2233 SCB->DCCMVAC = op_addr;
Kojto 102:da0ca467f8b5 2234 op_addr += linesize;
Kojto 102:da0ca467f8b5 2235 op_size -= (int32_t)linesize;
Kojto 102:da0ca467f8b5 2236 }
Kojto 102:da0ca467f8b5 2237
Kojto 102:da0ca467f8b5 2238 __DSB();
Kojto 102:da0ca467f8b5 2239 __ISB();
Kojto 102:da0ca467f8b5 2240 #endif
Kojto 102:da0ca467f8b5 2241 }
Kojto 102:da0ca467f8b5 2242
Kojto 102:da0ca467f8b5 2243
Kojto 102:da0ca467f8b5 2244 /**
Kojto 102:da0ca467f8b5 2245 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Kojto 102:da0ca467f8b5 2246 \brief D-Cache Clean and Invalidate by address
Kojto 102:da0ca467f8b5 2247 \param[in] addr address (aligned to 32-byte boundary)
Kojto 102:da0ca467f8b5 2248 \param[in] dsize size of memory block (in number of bytes)
Kojto 102:da0ca467f8b5 2249 */
Kojto 102:da0ca467f8b5 2250 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Kojto 102:da0ca467f8b5 2251 {
Kojto 102:da0ca467f8b5 2252 #if (__DCACHE_PRESENT == 1)
Kojto 102:da0ca467f8b5 2253 int32_t op_size = dsize;
Kojto 102:da0ca467f8b5 2254 uint32_t op_addr = (uint32_t) addr;
Kojto 102:da0ca467f8b5 2255 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Kojto 102:da0ca467f8b5 2256
Kojto 102:da0ca467f8b5 2257 __DSB();
Kojto 102:da0ca467f8b5 2258
Kojto 102:da0ca467f8b5 2259 while (op_size > 0) {
Kojto 102:da0ca467f8b5 2260 SCB->DCCIMVAC = op_addr;
Kojto 102:da0ca467f8b5 2261 op_addr += linesize;
Kojto 102:da0ca467f8b5 2262 op_size -= (int32_t)linesize;
Kojto 102:da0ca467f8b5 2263 }
Kojto 102:da0ca467f8b5 2264
Kojto 102:da0ca467f8b5 2265 __DSB();
Kojto 102:da0ca467f8b5 2266 __ISB();
Kojto 102:da0ca467f8b5 2267 #endif
Kojto 102:da0ca467f8b5 2268 }
Kojto 102:da0ca467f8b5 2269
Kojto 102:da0ca467f8b5 2270
Kojto 102:da0ca467f8b5 2271 /*@} end of CMSIS_Core_CacheFunctions */
Kojto 102:da0ca467f8b5 2272
Kojto 102:da0ca467f8b5 2273
Kojto 102:da0ca467f8b5 2274
Kojto 102:da0ca467f8b5 2275 /* ################################## SysTick function ############################################ */
Kojto 102:da0ca467f8b5 2276 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 102:da0ca467f8b5 2277 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 102:da0ca467f8b5 2278 \brief Functions that configure the System.
Kojto 102:da0ca467f8b5 2279 @{
Kojto 102:da0ca467f8b5 2280 */
Kojto 102:da0ca467f8b5 2281
Kojto 102:da0ca467f8b5 2282 #if (__Vendor_SysTickConfig == 0)
Kojto 102:da0ca467f8b5 2283
Kojto 102:da0ca467f8b5 2284 /** \brief System Tick Configuration
Kojto 102:da0ca467f8b5 2285
Kojto 102:da0ca467f8b5 2286 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 102:da0ca467f8b5 2287 Counter is in free running mode to generate periodic interrupts.
Kojto 102:da0ca467f8b5 2288
Kojto 102:da0ca467f8b5 2289 \param [in] ticks Number of ticks between two interrupts.
Kojto 102:da0ca467f8b5 2290
Kojto 102:da0ca467f8b5 2291 \return 0 Function succeeded.
Kojto 102:da0ca467f8b5 2292 \return 1 Function failed.
Kojto 102:da0ca467f8b5 2293
Kojto 102:da0ca467f8b5 2294 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 102:da0ca467f8b5 2295 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 102:da0ca467f8b5 2296 must contain a vendor-specific implementation of this function.
Kojto 102:da0ca467f8b5 2297
Kojto 102:da0ca467f8b5 2298 */
Kojto 102:da0ca467f8b5 2299 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 102:da0ca467f8b5 2300 {
Kojto 102:da0ca467f8b5 2301 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto 102:da0ca467f8b5 2302
Kojto 102:da0ca467f8b5 2303 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 102:da0ca467f8b5 2304 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 102:da0ca467f8b5 2305 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 102:da0ca467f8b5 2306 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 102:da0ca467f8b5 2307 SysTick_CTRL_TICKINT_Msk |
Kojto 102:da0ca467f8b5 2308 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 102:da0ca467f8b5 2309 return (0UL); /* Function successful */
Kojto 102:da0ca467f8b5 2310 }
Kojto 102:da0ca467f8b5 2311
Kojto 102:da0ca467f8b5 2312 #endif
Kojto 102:da0ca467f8b5 2313
Kojto 102:da0ca467f8b5 2314 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 102:da0ca467f8b5 2315
Kojto 102:da0ca467f8b5 2316
Kojto 102:da0ca467f8b5 2317
Kojto 102:da0ca467f8b5 2318 /* ##################################### Debug In/Output function ########################################### */
Kojto 102:da0ca467f8b5 2319 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 102:da0ca467f8b5 2320 \defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto 102:da0ca467f8b5 2321 \brief Functions that access the ITM debug interface.
Kojto 102:da0ca467f8b5 2322 @{
Kojto 102:da0ca467f8b5 2323 */
Kojto 102:da0ca467f8b5 2324
Kojto 102:da0ca467f8b5 2325 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Kojto 102:da0ca467f8b5 2326 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Kojto 102:da0ca467f8b5 2327
Kojto 102:da0ca467f8b5 2328
Kojto 102:da0ca467f8b5 2329 /** \brief ITM Send Character
Kojto 102:da0ca467f8b5 2330
Kojto 102:da0ca467f8b5 2331 The function transmits a character via the ITM channel 0, and
Kojto 102:da0ca467f8b5 2332 \li Just returns when no debugger is connected that has booked the output.
Kojto 102:da0ca467f8b5 2333 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto 102:da0ca467f8b5 2334
Kojto 102:da0ca467f8b5 2335 \param [in] ch Character to transmit.
Kojto 102:da0ca467f8b5 2336
Kojto 102:da0ca467f8b5 2337 \returns Character to transmit.
Kojto 102:da0ca467f8b5 2338 */
Kojto 102:da0ca467f8b5 2339 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto 102:da0ca467f8b5 2340 {
Kojto 102:da0ca467f8b5 2341 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto 102:da0ca467f8b5 2342 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto 102:da0ca467f8b5 2343 {
Kojto 102:da0ca467f8b5 2344 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto 102:da0ca467f8b5 2345 ITM->PORT[0].u8 = (uint8_t)ch;
Kojto 102:da0ca467f8b5 2346 }
Kojto 102:da0ca467f8b5 2347 return (ch);
Kojto 102:da0ca467f8b5 2348 }
Kojto 102:da0ca467f8b5 2349
Kojto 102:da0ca467f8b5 2350
Kojto 102:da0ca467f8b5 2351 /** \brief ITM Receive Character
Kojto 102:da0ca467f8b5 2352
Kojto 102:da0ca467f8b5 2353 The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto 102:da0ca467f8b5 2354
Kojto 102:da0ca467f8b5 2355 \return Received character.
Kojto 102:da0ca467f8b5 2356 \return -1 No character pending.
Kojto 102:da0ca467f8b5 2357 */
Kojto 102:da0ca467f8b5 2358 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto 102:da0ca467f8b5 2359 int32_t ch = -1; /* no character available */
Kojto 102:da0ca467f8b5 2360
Kojto 102:da0ca467f8b5 2361 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto 102:da0ca467f8b5 2362 ch = ITM_RxBuffer;
Kojto 102:da0ca467f8b5 2363 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto 102:da0ca467f8b5 2364 }
Kojto 102:da0ca467f8b5 2365
Kojto 102:da0ca467f8b5 2366 return (ch);
Kojto 102:da0ca467f8b5 2367 }
Kojto 102:da0ca467f8b5 2368
Kojto 102:da0ca467f8b5 2369
Kojto 102:da0ca467f8b5 2370 /** \brief ITM Check Character
Kojto 102:da0ca467f8b5 2371
Kojto 102:da0ca467f8b5 2372 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto 102:da0ca467f8b5 2373
Kojto 102:da0ca467f8b5 2374 \return 0 No character available.
Kojto 102:da0ca467f8b5 2375 \return 1 Character available.
Kojto 102:da0ca467f8b5 2376 */
Kojto 102:da0ca467f8b5 2377 __STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto 102:da0ca467f8b5 2378
Kojto 102:da0ca467f8b5 2379 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto 102:da0ca467f8b5 2380 return (0); /* no character available */
Kojto 102:da0ca467f8b5 2381 } else {
Kojto 102:da0ca467f8b5 2382 return (1); /* character available */
Kojto 102:da0ca467f8b5 2383 }
Kojto 102:da0ca467f8b5 2384 }
Kojto 102:da0ca467f8b5 2385
Kojto 102:da0ca467f8b5 2386 /*@} end of CMSIS_core_DebugFunctions */
Kojto 102:da0ca467f8b5 2387
Kojto 102:da0ca467f8b5 2388
Kojto 102:da0ca467f8b5 2389
Kojto 102:da0ca467f8b5 2390
Kojto 102:da0ca467f8b5 2391 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 2392 }
Kojto 102:da0ca467f8b5 2393 #endif
Kojto 102:da0ca467f8b5 2394
Kojto 102:da0ca467f8b5 2395 #endif /* __CORE_CM7_H_DEPENDANT */
Kojto 102:da0ca467f8b5 2396
Kojto 102:da0ca467f8b5 2397 #endif /* __CMSIS_GENERIC */