mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_bus.h@165:d1b4690b3f8b, 2018-04-19 (annotated)

Committer:
AnnaBridge
Date:
Thu Apr 19 14:31:27 2018 +0100
Revision:
165:d1b4690b3f8b
Parent:
128:9bcdf88f62b0 
mbed library. Release version 161

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_ll_bus.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @brief Header file of BUS LL module.
<> 128:9bcdf88f62b0 6
<> 128:9bcdf88f62b0 7 @verbatim
<> 128:9bcdf88f62b0 8 ##### RCC Limitations #####
<> 128:9bcdf88f62b0 9 ==============================================================================
<> 128:9bcdf88f62b0 10 [..]
<> 128:9bcdf88f62b0 11 A delay between an RCC peripheral clock enable and the effective peripheral
<> 128:9bcdf88f62b0 12 enabling should be taken into account in order to manage the peripheral read/write
<> 128:9bcdf88f62b0 13 from/to registers.
<> 128:9bcdf88f62b0 14 (+) This delay depends on the peripheral mapping.
<> 128:9bcdf88f62b0 15 (++) AHB & APB peripherals, 1 dummy read is necessary
<> 128:9bcdf88f62b0 16
<> 128:9bcdf88f62b0 17 [..]
<> 128:9bcdf88f62b0 18 Workarounds:
<> 128:9bcdf88f62b0 19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
<> 128:9bcdf88f62b0 20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
<> 128:9bcdf88f62b0 21
<> 128:9bcdf88f62b0 22 @endverbatim
<> 128:9bcdf88f62b0 23 ******************************************************************************
<> 128:9bcdf88f62b0 24 * @attention
<> 128:9bcdf88f62b0 25 *
AnnaBridge 165:d1b4690b3f8b 26 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 27 *
<> 128:9bcdf88f62b0 28 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 29 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 30 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 31 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 32 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 33 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 34 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 36 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 37 * without specific prior written permission.
<> 128:9bcdf88f62b0 38 *
<> 128:9bcdf88f62b0 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 49 *
<> 128:9bcdf88f62b0 50 ******************************************************************************
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 54 #ifndef __STM32L1xx_LL_BUS_H
<> 128:9bcdf88f62b0 55 #define __STM32L1xx_LL_BUS_H
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 #ifdef __cplusplus
<> 128:9bcdf88f62b0 58 extern "C" {
<> 128:9bcdf88f62b0 59 #endif
<> 128:9bcdf88f62b0 60
<> 128:9bcdf88f62b0 61 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 62 #include "stm32l1xx.h"
<> 128:9bcdf88f62b0 63
<> 128:9bcdf88f62b0 64 /** @addtogroup STM32L1xx_LL_Driver
<> 128:9bcdf88f62b0 65 * @{
<> 128:9bcdf88f62b0 66 */
<> 128:9bcdf88f62b0 67
<> 128:9bcdf88f62b0 68 #if defined(RCC)
<> 128:9bcdf88f62b0 69
<> 128:9bcdf88f62b0 70 /** @defgroup BUS_LL BUS
<> 128:9bcdf88f62b0 71 * @{
<> 128:9bcdf88f62b0 72 */
<> 128:9bcdf88f62b0 73
<> 128:9bcdf88f62b0 74 /* Private types -------------------------------------------------------------*/
<> 128:9bcdf88f62b0 75 /* Private variables ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 76
<> 128:9bcdf88f62b0 77 /* Private constants ---------------------------------------------------------*/
<> 128:9bcdf88f62b0 78
<> 128:9bcdf88f62b0 79 /* Private macros ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 80
<> 128:9bcdf88f62b0 81 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 82 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 83 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
<> 128:9bcdf88f62b0 84 * @{
<> 128:9bcdf88f62b0 85 */
<> 128:9bcdf88f62b0 86
<> 128:9bcdf88f62b0 87 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
<> 128:9bcdf88f62b0 88 * @{
<> 128:9bcdf88f62b0 89 */
AnnaBridge 165:d1b4690b3f8b 90 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
<> 128:9bcdf88f62b0 91 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
<> 128:9bcdf88f62b0 92 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
<> 128:9bcdf88f62b0 93 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
<> 128:9bcdf88f62b0 94 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
<> 128:9bcdf88f62b0 95 #if defined(GPIOE)
<> 128:9bcdf88f62b0 96 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
<> 128:9bcdf88f62b0 97 #endif/*GPIOE*/
<> 128:9bcdf88f62b0 98 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN
<> 128:9bcdf88f62b0 99 #if defined(GPIOF)
<> 128:9bcdf88f62b0 100 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
<> 128:9bcdf88f62b0 101 #endif/*GPIOF*/
<> 128:9bcdf88f62b0 102 #if defined(GPIOG)
<> 128:9bcdf88f62b0 103 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN
<> 128:9bcdf88f62b0 104 #endif/*GPIOG*/
<> 128:9bcdf88f62b0 105 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBLPENR_SRAMLPEN
<> 128:9bcdf88f62b0 106 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
<> 128:9bcdf88f62b0 107 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
<> 128:9bcdf88f62b0 108 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
<> 128:9bcdf88f62b0 109 #if defined(DMA2)
<> 128:9bcdf88f62b0 110 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
<> 128:9bcdf88f62b0 111 #endif/*DMA2*/
<> 128:9bcdf88f62b0 112 #if defined(AES)
<> 128:9bcdf88f62b0 113 #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN
<> 128:9bcdf88f62b0 114 #endif/*AES*/
<> 128:9bcdf88f62b0 115 #if defined(FSMC_Bank1)
<> 128:9bcdf88f62b0 116 #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
<> 128:9bcdf88f62b0 117 #endif/*FSMC_Bank1*/
<> 128:9bcdf88f62b0 118 /**
<> 128:9bcdf88f62b0 119 * @}
<> 128:9bcdf88f62b0 120 */
<> 128:9bcdf88f62b0 121
<> 128:9bcdf88f62b0 122 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
<> 128:9bcdf88f62b0 123 * @{
<> 128:9bcdf88f62b0 124 */
AnnaBridge 165:d1b4690b3f8b 125 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
<> 128:9bcdf88f62b0 126 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
<> 128:9bcdf88f62b0 127 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
<> 128:9bcdf88f62b0 128 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
<> 128:9bcdf88f62b0 129 #if defined(TIM5)
<> 128:9bcdf88f62b0 130 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
<> 128:9bcdf88f62b0 131 #endif /*TIM5*/
<> 128:9bcdf88f62b0 132 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
<> 128:9bcdf88f62b0 133 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
<> 128:9bcdf88f62b0 134 #if defined(LCD)
<> 128:9bcdf88f62b0 135 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN
<> 128:9bcdf88f62b0 136 #endif /*LCD*/
<> 128:9bcdf88f62b0 137 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
<> 128:9bcdf88f62b0 138 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
<> 128:9bcdf88f62b0 139 #if defined(SPI3)
<> 128:9bcdf88f62b0 140 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
<> 128:9bcdf88f62b0 141 #endif /*SPI3*/
<> 128:9bcdf88f62b0 142 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
<> 128:9bcdf88f62b0 143 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
<> 128:9bcdf88f62b0 144 #if defined(UART4)
<> 128:9bcdf88f62b0 145 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
<> 128:9bcdf88f62b0 146 #endif /*UART4*/
<> 128:9bcdf88f62b0 147 #if defined(UART5)
<> 128:9bcdf88f62b0 148 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
<> 128:9bcdf88f62b0 149 #endif /*UART5*/
<> 128:9bcdf88f62b0 150 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
<> 128:9bcdf88f62b0 151 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
<> 128:9bcdf88f62b0 152 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
<> 128:9bcdf88f62b0 153 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
<> 128:9bcdf88f62b0 154 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
<> 128:9bcdf88f62b0 155 #define LL_APB1_GRP1_PERIPH_COMP RCC_APB1ENR_COMPEN
<> 128:9bcdf88f62b0 156 #if defined(OPAMP)
<> 128:9bcdf88f62b0 157 /* Note: Peripherals COMP and OPAMP share the same clock domain */
<> 128:9bcdf88f62b0 158 #define LL_APB1_GRP1_PERIPH_OPAMP LL_APB1_GRP1_PERIPH_COMP
<> 128:9bcdf88f62b0 159 #endif
<> 128:9bcdf88f62b0 160 /**
<> 128:9bcdf88f62b0 161 * @}
<> 128:9bcdf88f62b0 162 */
<> 128:9bcdf88f62b0 163
<> 128:9bcdf88f62b0 164 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
<> 128:9bcdf88f62b0 165 * @{
<> 128:9bcdf88f62b0 166 */
AnnaBridge 165:d1b4690b3f8b 167 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
<> 128:9bcdf88f62b0 168 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
<> 128:9bcdf88f62b0 169 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
<> 128:9bcdf88f62b0 170 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
<> 128:9bcdf88f62b0 171 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
<> 128:9bcdf88f62b0 172 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
<> 128:9bcdf88f62b0 173 #if defined(SDIO)
<> 128:9bcdf88f62b0 174 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
<> 128:9bcdf88f62b0 175 #endif /*SDIO*/
<> 128:9bcdf88f62b0 176 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
<> 128:9bcdf88f62b0 177 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
<> 128:9bcdf88f62b0 178 /**
<> 128:9bcdf88f62b0 179 * @}
<> 128:9bcdf88f62b0 180 */
<> 128:9bcdf88f62b0 181
<> 128:9bcdf88f62b0 182 /**
<> 128:9bcdf88f62b0 183 * @}
<> 128:9bcdf88f62b0 184 */
<> 128:9bcdf88f62b0 185
<> 128:9bcdf88f62b0 186 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 187
<> 128:9bcdf88f62b0 188 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 189 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
<> 128:9bcdf88f62b0 190 * @{
<> 128:9bcdf88f62b0 191 */
<> 128:9bcdf88f62b0 192
<> 128:9bcdf88f62b0 193 /** @defgroup BUS_LL_EF_AHB1 AHB1
<> 128:9bcdf88f62b0 194 * @{
<> 128:9bcdf88f62b0 195 */
<> 128:9bcdf88f62b0 196
<> 128:9bcdf88f62b0 197 /**
<> 128:9bcdf88f62b0 198 * @brief Enable AHB1 peripherals clock.
<> 128:9bcdf88f62b0 199 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 200 * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 201 * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 202 * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 203 * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 204 * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 205 * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 206 * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 207 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 208 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 209 * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 210 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 211 * AHBENR AESEN LL_AHB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 212 * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock
<> 128:9bcdf88f62b0 213 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 214 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 128:9bcdf88f62b0 215 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 128:9bcdf88f62b0 216 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 128:9bcdf88f62b0 217 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 128:9bcdf88f62b0 218 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 128:9bcdf88f62b0 219 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 128:9bcdf88f62b0 220 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 128:9bcdf88f62b0 221 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 128:9bcdf88f62b0 222 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 128:9bcdf88f62b0 223 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 128:9bcdf88f62b0 224 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 128:9bcdf88f62b0 225 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 128:9bcdf88f62b0 226 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 128:9bcdf88f62b0 227 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 128:9bcdf88f62b0 228 *
<> 128:9bcdf88f62b0 229 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 230 * @retval None
<> 128:9bcdf88f62b0 231 */
<> 128:9bcdf88f62b0 232 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
<> 128:9bcdf88f62b0 233 {
<> 128:9bcdf88f62b0 234 __IO uint32_t tmpreg;
<> 128:9bcdf88f62b0 235 SET_BIT(RCC->AHBENR, Periphs);
<> 128:9bcdf88f62b0 236 /* Delay after an RCC peripheral clock enabling */
<> 128:9bcdf88f62b0 237 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
<> 128:9bcdf88f62b0 238 (void)tmpreg;
<> 128:9bcdf88f62b0 239 }
<> 128:9bcdf88f62b0 240
<> 128:9bcdf88f62b0 241 /**
<> 128:9bcdf88f62b0 242 * @brief Check if AHB1 peripheral clock is enabled or not
<> 128:9bcdf88f62b0 243 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 244 * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 245 * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 246 * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 247 * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 248 * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 249 * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 250 * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 251 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 252 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 253 * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 254 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 255 * AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 256 * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock
<> 128:9bcdf88f62b0 257 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 258 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 128:9bcdf88f62b0 259 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 128:9bcdf88f62b0 260 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 128:9bcdf88f62b0 261 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 128:9bcdf88f62b0 262 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 128:9bcdf88f62b0 263 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 128:9bcdf88f62b0 264 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 128:9bcdf88f62b0 265 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 128:9bcdf88f62b0 266 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 128:9bcdf88f62b0 267 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 128:9bcdf88f62b0 268 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 128:9bcdf88f62b0 269 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 128:9bcdf88f62b0 270 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 128:9bcdf88f62b0 271 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 128:9bcdf88f62b0 272 *
<> 128:9bcdf88f62b0 273 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 274 * @retval State of Periphs (1 or 0).
<> 128:9bcdf88f62b0 275 */
<> 128:9bcdf88f62b0 276 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
<> 128:9bcdf88f62b0 277 {
<> 128:9bcdf88f62b0 278 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
<> 128:9bcdf88f62b0 279 }
<> 128:9bcdf88f62b0 280
<> 128:9bcdf88f62b0 281 /**
<> 128:9bcdf88f62b0 282 * @brief Disable AHB1 peripherals clock.
<> 128:9bcdf88f62b0 283 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 284 * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 285 * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 286 * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 287 * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 288 * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 289 * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 290 * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 291 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 292 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 293 * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 294 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 295 * AHBENR AESEN LL_AHB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 296 * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock
<> 128:9bcdf88f62b0 297 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 298 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 128:9bcdf88f62b0 299 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 128:9bcdf88f62b0 300 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 128:9bcdf88f62b0 301 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 128:9bcdf88f62b0 302 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 128:9bcdf88f62b0 303 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 128:9bcdf88f62b0 304 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 128:9bcdf88f62b0 305 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 128:9bcdf88f62b0 306 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 128:9bcdf88f62b0 307 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 128:9bcdf88f62b0 308 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 128:9bcdf88f62b0 309 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 128:9bcdf88f62b0 310 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 128:9bcdf88f62b0 311 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 128:9bcdf88f62b0 312 *
<> 128:9bcdf88f62b0 313 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 314 * @retval None
<> 128:9bcdf88f62b0 315 */
<> 128:9bcdf88f62b0 316 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
<> 128:9bcdf88f62b0 317 {
<> 128:9bcdf88f62b0 318 CLEAR_BIT(RCC->AHBENR, Periphs);
<> 128:9bcdf88f62b0 319 }
<> 128:9bcdf88f62b0 320
<> 128:9bcdf88f62b0 321 /**
<> 128:9bcdf88f62b0 322 * @brief Force AHB1 peripherals reset.
<> 128:9bcdf88f62b0 323 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 324 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 325 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 326 * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 327 * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 328 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 329 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 330 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 331 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 332 * AHBRSTR FLITFRST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 333 * AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 334 * AHBRSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 335 * AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 336 * AHBRSTR FSMCRST LL_AHB1_GRP1_ForceReset
<> 128:9bcdf88f62b0 337 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 338 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
<> 128:9bcdf88f62b0 339 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 128:9bcdf88f62b0 340 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 128:9bcdf88f62b0 341 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 128:9bcdf88f62b0 342 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 128:9bcdf88f62b0 343 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 128:9bcdf88f62b0 344 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 128:9bcdf88f62b0 345 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 128:9bcdf88f62b0 346 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 128:9bcdf88f62b0 347 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 128:9bcdf88f62b0 348 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 128:9bcdf88f62b0 349 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 128:9bcdf88f62b0 350 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 128:9bcdf88f62b0 351 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 128:9bcdf88f62b0 352 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 128:9bcdf88f62b0 353 *
<> 128:9bcdf88f62b0 354 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 355 * @retval None
<> 128:9bcdf88f62b0 356 */
<> 128:9bcdf88f62b0 357 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
<> 128:9bcdf88f62b0 358 {
<> 128:9bcdf88f62b0 359 SET_BIT(RCC->AHBRSTR, Periphs);
<> 128:9bcdf88f62b0 360 }
<> 128:9bcdf88f62b0 361
<> 128:9bcdf88f62b0 362 /**
<> 128:9bcdf88f62b0 363 * @brief Release AHB1 peripherals reset.
<> 128:9bcdf88f62b0 364 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 365 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 366 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 367 * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 368 * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 369 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 370 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 371 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 372 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 373 * AHBRSTR FLITFRST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 374 * AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 375 * AHBRSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 376 * AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 377 * AHBRSTR FSMCRST LL_AHB1_GRP1_ReleaseReset
<> 128:9bcdf88f62b0 378 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 379 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
<> 128:9bcdf88f62b0 380 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 128:9bcdf88f62b0 381 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 128:9bcdf88f62b0 382 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 128:9bcdf88f62b0 383 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 128:9bcdf88f62b0 384 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 128:9bcdf88f62b0 385 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 128:9bcdf88f62b0 386 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 128:9bcdf88f62b0 387 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 128:9bcdf88f62b0 388 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 128:9bcdf88f62b0 389 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 128:9bcdf88f62b0 390 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 128:9bcdf88f62b0 391 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 128:9bcdf88f62b0 392 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 128:9bcdf88f62b0 393 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 128:9bcdf88f62b0 394 *
<> 128:9bcdf88f62b0 395 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 396 * @retval None
<> 128:9bcdf88f62b0 397 */
<> 128:9bcdf88f62b0 398 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
<> 128:9bcdf88f62b0 399 {
<> 128:9bcdf88f62b0 400 CLEAR_BIT(RCC->AHBRSTR, Periphs);
<> 128:9bcdf88f62b0 401 }
<> 128:9bcdf88f62b0 402
<> 128:9bcdf88f62b0 403 /**
<> 128:9bcdf88f62b0 404 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
<> 128:9bcdf88f62b0 405 * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 406 * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 407 * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 408 * AHBLPENR GPIODLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 409 * AHBLPENR GPIOELPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 410 * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 411 * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 412 * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 413 * AHBLPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 414 * AHBLPENR FLITFLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 415 * AHBLPENR SRAMLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 416 * AHBLPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 417 * AHBLPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 418 * AHBLPENR AESLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 419 * AHBLPENR FSMCLPEN LL_AHB1_GRP1_EnableClockSleep
<> 128:9bcdf88f62b0 420 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 421 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 128:9bcdf88f62b0 422 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 128:9bcdf88f62b0 423 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 128:9bcdf88f62b0 424 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 128:9bcdf88f62b0 425 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 128:9bcdf88f62b0 426 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 128:9bcdf88f62b0 427 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 128:9bcdf88f62b0 428 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 128:9bcdf88f62b0 429 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 128:9bcdf88f62b0 430 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 128:9bcdf88f62b0 431 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
<> 128:9bcdf88f62b0 432 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 128:9bcdf88f62b0 433 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 128:9bcdf88f62b0 434 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 128:9bcdf88f62b0 435 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 128:9bcdf88f62b0 436 *
<> 128:9bcdf88f62b0 437 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 438 * @retval None
<> 128:9bcdf88f62b0 439 */
<> 128:9bcdf88f62b0 440 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
<> 128:9bcdf88f62b0 441 {
<> 128:9bcdf88f62b0 442 __IO uint32_t tmpreg;
<> 128:9bcdf88f62b0 443 SET_BIT(RCC->AHBLPENR, Periphs);
<> 128:9bcdf88f62b0 444 /* Delay after an RCC peripheral clock enabling */
<> 128:9bcdf88f62b0 445 tmpreg = READ_BIT(RCC->AHBLPENR, Periphs);
<> 128:9bcdf88f62b0 446 (void)tmpreg;
<> 128:9bcdf88f62b0 447 }
<> 128:9bcdf88f62b0 448
<> 128:9bcdf88f62b0 449 /**
<> 128:9bcdf88f62b0 450 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
<> 128:9bcdf88f62b0 451 * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 452 * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 453 * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 454 * AHBLPENR GPIODLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 455 * AHBLPENR GPIOELPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 456 * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 457 * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 458 * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 459 * AHBLPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 460 * AHBLPENR FLITFLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 461 * AHBLPENR SRAMLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 462 * AHBLPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 463 * AHBLPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 464 * AHBLPENR AESLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 465 * AHBLPENR FSMCLPEN LL_AHB1_GRP1_DisableClockSleep
<> 128:9bcdf88f62b0 466 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 467 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 128:9bcdf88f62b0 468 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 128:9bcdf88f62b0 469 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 128:9bcdf88f62b0 470 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 128:9bcdf88f62b0 471 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 128:9bcdf88f62b0 472 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 128:9bcdf88f62b0 473 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 128:9bcdf88f62b0 474 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 128:9bcdf88f62b0 475 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 128:9bcdf88f62b0 476 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 128:9bcdf88f62b0 477 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
<> 128:9bcdf88f62b0 478 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 128:9bcdf88f62b0 479 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 128:9bcdf88f62b0 480 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 128:9bcdf88f62b0 481 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 128:9bcdf88f62b0 482 *
<> 128:9bcdf88f62b0 483 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 484 * @retval None
<> 128:9bcdf88f62b0 485 */
<> 128:9bcdf88f62b0 486 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
<> 128:9bcdf88f62b0 487 {
<> 128:9bcdf88f62b0 488 CLEAR_BIT(RCC->AHBLPENR, Periphs);
<> 128:9bcdf88f62b0 489 }
<> 128:9bcdf88f62b0 490
<> 128:9bcdf88f62b0 491 /**
<> 128:9bcdf88f62b0 492 * @}
<> 128:9bcdf88f62b0 493 */
<> 128:9bcdf88f62b0 494
<> 128:9bcdf88f62b0 495 /** @defgroup BUS_LL_EF_APB1 APB1
<> 128:9bcdf88f62b0 496 * @{
<> 128:9bcdf88f62b0 497 */
<> 128:9bcdf88f62b0 498
<> 128:9bcdf88f62b0 499 /**
<> 128:9bcdf88f62b0 500 * @brief Enable APB1 peripherals clock.
<> 128:9bcdf88f62b0 501 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 502 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 503 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 504 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 505 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 506 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 507 * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 508 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 509 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 510 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 511 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 512 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 513 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 514 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 515 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 516 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 517 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 518 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 519 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 520 * APB1ENR COMPEN LL_APB1_GRP1_EnableClock
<> 128:9bcdf88f62b0 521 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 522 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 128:9bcdf88f62b0 523 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 128:9bcdf88f62b0 524 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 128:9bcdf88f62b0 525 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 128:9bcdf88f62b0 526 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 128:9bcdf88f62b0 527 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 128:9bcdf88f62b0 528 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 128:9bcdf88f62b0 529 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 128:9bcdf88f62b0 530 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 128:9bcdf88f62b0 531 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 128:9bcdf88f62b0 532 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 128:9bcdf88f62b0 533 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 128:9bcdf88f62b0 534 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 128:9bcdf88f62b0 535 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 128:9bcdf88f62b0 536 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 128:9bcdf88f62b0 537 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 128:9bcdf88f62b0 538 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 128:9bcdf88f62b0 539 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 128:9bcdf88f62b0 540 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 128:9bcdf88f62b0 541 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 128:9bcdf88f62b0 542 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 128:9bcdf88f62b0 543 *
<> 128:9bcdf88f62b0 544 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 545 * @retval None
<> 128:9bcdf88f62b0 546 */
<> 128:9bcdf88f62b0 547 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
<> 128:9bcdf88f62b0 548 {
<> 128:9bcdf88f62b0 549 __IO uint32_t tmpreg;
<> 128:9bcdf88f62b0 550 SET_BIT(RCC->APB1ENR, Periphs);
<> 128:9bcdf88f62b0 551 /* Delay after an RCC peripheral clock enabling */
<> 128:9bcdf88f62b0 552 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
<> 128:9bcdf88f62b0 553 (void)tmpreg;
<> 128:9bcdf88f62b0 554 }
<> 128:9bcdf88f62b0 555
<> 128:9bcdf88f62b0 556 /**
<> 128:9bcdf88f62b0 557 * @brief Check if APB1 peripheral clock is enabled or not
<> 128:9bcdf88f62b0 558 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 559 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 560 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 561 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 562 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 563 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 564 * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 565 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 566 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 567 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 568 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 569 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 570 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 571 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 572 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 573 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 574 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 575 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 576 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 577 * APB1ENR COMPEN LL_APB1_GRP1_IsEnabledClock
<> 128:9bcdf88f62b0 578 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 579 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 128:9bcdf88f62b0 580 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 128:9bcdf88f62b0 581 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 128:9bcdf88f62b0 582 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 128:9bcdf88f62b0 583 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 128:9bcdf88f62b0 584 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 128:9bcdf88f62b0 585 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 128:9bcdf88f62b0 586 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 128:9bcdf88f62b0 587 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 128:9bcdf88f62b0 588 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 128:9bcdf88f62b0 589 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 128:9bcdf88f62b0 590 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 128:9bcdf88f62b0 591 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 128:9bcdf88f62b0 592 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 128:9bcdf88f62b0 593 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 128:9bcdf88f62b0 594 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 128:9bcdf88f62b0 595 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 128:9bcdf88f62b0 596 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 128:9bcdf88f62b0 597 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 128:9bcdf88f62b0 598 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 128:9bcdf88f62b0 599 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 128:9bcdf88f62b0 600 *
<> 128:9bcdf88f62b0 601 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 602 * @retval State of Periphs (1 or 0).
<> 128:9bcdf88f62b0 603 */
<> 128:9bcdf88f62b0 604 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
<> 128:9bcdf88f62b0 605 {
<> 128:9bcdf88f62b0 606 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
<> 128:9bcdf88f62b0 607 }
<> 128:9bcdf88f62b0 608
<> 128:9bcdf88f62b0 609 /**
<> 128:9bcdf88f62b0 610 * @brief Disable APB1 peripherals clock.
<> 128:9bcdf88f62b0 611 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 612 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 613 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 614 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 615 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 616 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 617 * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 618 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 619 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 620 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 621 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 622 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 623 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 624 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 625 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 626 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 627 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 628 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 629 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 630 * APB1ENR COMPEN LL_APB1_GRP1_DisableClock
<> 128:9bcdf88f62b0 631 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 632 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 128:9bcdf88f62b0 633 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 128:9bcdf88f62b0 634 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 128:9bcdf88f62b0 635 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 128:9bcdf88f62b0 636 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 128:9bcdf88f62b0 637 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 128:9bcdf88f62b0 638 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 128:9bcdf88f62b0 639 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 128:9bcdf88f62b0 640 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 128:9bcdf88f62b0 641 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 128:9bcdf88f62b0 642 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 128:9bcdf88f62b0 643 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 128:9bcdf88f62b0 644 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 128:9bcdf88f62b0 645 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 128:9bcdf88f62b0 646 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 128:9bcdf88f62b0 647 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 128:9bcdf88f62b0 648 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 128:9bcdf88f62b0 649 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 128:9bcdf88f62b0 650 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 128:9bcdf88f62b0 651 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 128:9bcdf88f62b0 652 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 128:9bcdf88f62b0 653 *
<> 128:9bcdf88f62b0 654 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 655 * @retval None
<> 128:9bcdf88f62b0 656 */
<> 128:9bcdf88f62b0 657 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
<> 128:9bcdf88f62b0 658 {
<> 128:9bcdf88f62b0 659 CLEAR_BIT(RCC->APB1ENR, Periphs);
<> 128:9bcdf88f62b0 660 }
<> 128:9bcdf88f62b0 661
<> 128:9bcdf88f62b0 662 /**
<> 128:9bcdf88f62b0 663 * @brief Force APB1 peripherals reset.
<> 128:9bcdf88f62b0 664 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 665 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 666 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 667 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 668 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 669 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 670 * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 671 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 672 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 673 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 674 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 675 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 676 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 677 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 678 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 679 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 680 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 681 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 682 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 683 * APB1RSTR COMPRST LL_APB1_GRP1_ForceReset
<> 128:9bcdf88f62b0 684 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 685 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
<> 128:9bcdf88f62b0 686 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 128:9bcdf88f62b0 687 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 128:9bcdf88f62b0 688 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 128:9bcdf88f62b0 689 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 128:9bcdf88f62b0 690 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 128:9bcdf88f62b0 691 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 128:9bcdf88f62b0 692 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 128:9bcdf88f62b0 693 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 128:9bcdf88f62b0 694 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 128:9bcdf88f62b0 695 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 128:9bcdf88f62b0 696 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 128:9bcdf88f62b0 697 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 128:9bcdf88f62b0 698 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 128:9bcdf88f62b0 699 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 128:9bcdf88f62b0 700 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 128:9bcdf88f62b0 701 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 128:9bcdf88f62b0 702 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 128:9bcdf88f62b0 703 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 128:9bcdf88f62b0 704 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 128:9bcdf88f62b0 705 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 128:9bcdf88f62b0 706 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 128:9bcdf88f62b0 707 *
<> 128:9bcdf88f62b0 708 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 709 * @retval None
<> 128:9bcdf88f62b0 710 */
<> 128:9bcdf88f62b0 711 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
<> 128:9bcdf88f62b0 712 {
<> 128:9bcdf88f62b0 713 SET_BIT(RCC->APB1RSTR, Periphs);
<> 128:9bcdf88f62b0 714 }
<> 128:9bcdf88f62b0 715
<> 128:9bcdf88f62b0 716 /**
<> 128:9bcdf88f62b0 717 * @brief Release APB1 peripherals reset.
<> 128:9bcdf88f62b0 718 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 719 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 720 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 721 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 722 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 723 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 724 * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 725 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 726 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 727 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 728 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 729 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 730 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 731 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 732 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 733 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 734 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 735 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 736 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 737 * APB1RSTR COMPRST LL_APB1_GRP1_ReleaseReset
<> 128:9bcdf88f62b0 738 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 739 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
<> 128:9bcdf88f62b0 740 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 128:9bcdf88f62b0 741 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 128:9bcdf88f62b0 742 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 128:9bcdf88f62b0 743 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 128:9bcdf88f62b0 744 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 128:9bcdf88f62b0 745 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 128:9bcdf88f62b0 746 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 128:9bcdf88f62b0 747 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 128:9bcdf88f62b0 748 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 128:9bcdf88f62b0 749 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 128:9bcdf88f62b0 750 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 128:9bcdf88f62b0 751 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 128:9bcdf88f62b0 752 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 128:9bcdf88f62b0 753 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 128:9bcdf88f62b0 754 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 128:9bcdf88f62b0 755 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 128:9bcdf88f62b0 756 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 128:9bcdf88f62b0 757 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 128:9bcdf88f62b0 758 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 128:9bcdf88f62b0 759 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 128:9bcdf88f62b0 760 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 128:9bcdf88f62b0 761 *
<> 128:9bcdf88f62b0 762 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 763 * @retval None
<> 128:9bcdf88f62b0 764 */
<> 128:9bcdf88f62b0 765 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
<> 128:9bcdf88f62b0 766 {
<> 128:9bcdf88f62b0 767 CLEAR_BIT(RCC->APB1RSTR, Periphs);
<> 128:9bcdf88f62b0 768 }
<> 128:9bcdf88f62b0 769
<> 128:9bcdf88f62b0 770 /**
<> 128:9bcdf88f62b0 771 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
<> 128:9bcdf88f62b0 772 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 773 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 774 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 775 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 776 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 777 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 778 * APB1LPENR LCDLPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 779 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 780 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 781 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 782 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 783 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 784 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 785 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 786 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 787 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 788 * APB1LPENR USBLPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 789 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 790 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 791 * APB1LPENR COMPLPEN LL_APB1_GRP1_EnableClockSleep
<> 128:9bcdf88f62b0 792 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 793 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 128:9bcdf88f62b0 794 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 128:9bcdf88f62b0 795 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 128:9bcdf88f62b0 796 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 128:9bcdf88f62b0 797 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 128:9bcdf88f62b0 798 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 128:9bcdf88f62b0 799 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 128:9bcdf88f62b0 800 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 128:9bcdf88f62b0 801 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 128:9bcdf88f62b0 802 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 128:9bcdf88f62b0 803 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 128:9bcdf88f62b0 804 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 128:9bcdf88f62b0 805 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 128:9bcdf88f62b0 806 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 128:9bcdf88f62b0 807 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 128:9bcdf88f62b0 808 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 128:9bcdf88f62b0 809 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 128:9bcdf88f62b0 810 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 128:9bcdf88f62b0 811 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 128:9bcdf88f62b0 812 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 128:9bcdf88f62b0 813 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 128:9bcdf88f62b0 814 *
<> 128:9bcdf88f62b0 815 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 816 * @retval None
<> 128:9bcdf88f62b0 817 */
<> 128:9bcdf88f62b0 818 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
<> 128:9bcdf88f62b0 819 {
<> 128:9bcdf88f62b0 820 __IO uint32_t tmpreg;
<> 128:9bcdf88f62b0 821 SET_BIT(RCC->APB1LPENR, Periphs);
<> 128:9bcdf88f62b0 822 /* Delay after an RCC peripheral clock enabling */
<> 128:9bcdf88f62b0 823 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
<> 128:9bcdf88f62b0 824 (void)tmpreg;
<> 128:9bcdf88f62b0 825 }
<> 128:9bcdf88f62b0 826
<> 128:9bcdf88f62b0 827 /**
<> 128:9bcdf88f62b0 828 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
<> 128:9bcdf88f62b0 829 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 830 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 831 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 832 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 833 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 834 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 835 * APB1LPENR LCDLPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 836 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 837 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 838 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 839 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 840 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 841 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 842 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 843 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 844 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 845 * APB1LPENR USBLPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 846 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 847 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 848 * APB1LPENR COMPLPEN LL_APB1_GRP1_DisableClockSleep
<> 128:9bcdf88f62b0 849 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 850 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 128:9bcdf88f62b0 851 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 128:9bcdf88f62b0 852 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 128:9bcdf88f62b0 853 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 128:9bcdf88f62b0 854 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 128:9bcdf88f62b0 855 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 128:9bcdf88f62b0 856 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 128:9bcdf88f62b0 857 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 128:9bcdf88f62b0 858 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 128:9bcdf88f62b0 859 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 128:9bcdf88f62b0 860 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 128:9bcdf88f62b0 861 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 128:9bcdf88f62b0 862 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 128:9bcdf88f62b0 863 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 128:9bcdf88f62b0 864 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 128:9bcdf88f62b0 865 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 128:9bcdf88f62b0 866 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 128:9bcdf88f62b0 867 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 128:9bcdf88f62b0 868 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 128:9bcdf88f62b0 869 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 128:9bcdf88f62b0 870 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 128:9bcdf88f62b0 871 *
<> 128:9bcdf88f62b0 872 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 873 * @retval None
<> 128:9bcdf88f62b0 874 */
<> 128:9bcdf88f62b0 875 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
<> 128:9bcdf88f62b0 876 {
<> 128:9bcdf88f62b0 877 CLEAR_BIT(RCC->APB1LPENR, Periphs);
<> 128:9bcdf88f62b0 878 }
<> 128:9bcdf88f62b0 879
<> 128:9bcdf88f62b0 880 /**
<> 128:9bcdf88f62b0 881 * @}
<> 128:9bcdf88f62b0 882 */
<> 128:9bcdf88f62b0 883
<> 128:9bcdf88f62b0 884 /** @defgroup BUS_LL_EF_APB2 APB2
<> 128:9bcdf88f62b0 885 * @{
<> 128:9bcdf88f62b0 886 */
<> 128:9bcdf88f62b0 887
<> 128:9bcdf88f62b0 888 /**
<> 128:9bcdf88f62b0 889 * @brief Enable APB2 peripherals clock.
<> 128:9bcdf88f62b0 890 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 891 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 892 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 893 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 894 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 895 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 896 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
<> 128:9bcdf88f62b0 897 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
<> 128:9bcdf88f62b0 898 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 899 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 128:9bcdf88f62b0 900 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 128:9bcdf88f62b0 901 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 128:9bcdf88f62b0 902 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 128:9bcdf88f62b0 903 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 128:9bcdf88f62b0 904 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 128:9bcdf88f62b0 905 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 128:9bcdf88f62b0 906 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 128:9bcdf88f62b0 907 *
<> 128:9bcdf88f62b0 908 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 909 * @retval None
<> 128:9bcdf88f62b0 910 */
<> 128:9bcdf88f62b0 911 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
<> 128:9bcdf88f62b0 912 {
<> 128:9bcdf88f62b0 913 __IO uint32_t tmpreg;
<> 128:9bcdf88f62b0 914 SET_BIT(RCC->APB2ENR, Periphs);
<> 128:9bcdf88f62b0 915 /* Delay after an RCC peripheral clock enabling */
<> 128:9bcdf88f62b0 916 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
<> 128:9bcdf88f62b0 917 (void)tmpreg;
<> 128:9bcdf88f62b0 918 }
<> 128:9bcdf88f62b0 919
<> 128:9bcdf88f62b0 920 /**
<> 128:9bcdf88f62b0 921 * @brief Check if APB2 peripheral clock is enabled or not
<> 128:9bcdf88f62b0 922 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 923 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 924 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 925 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 926 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 927 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 928 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
<> 128:9bcdf88f62b0 929 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
<> 128:9bcdf88f62b0 930 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 931 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 128:9bcdf88f62b0 932 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 128:9bcdf88f62b0 933 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 128:9bcdf88f62b0 934 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 128:9bcdf88f62b0 935 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 128:9bcdf88f62b0 936 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 128:9bcdf88f62b0 937 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 128:9bcdf88f62b0 938 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 128:9bcdf88f62b0 939 *
<> 128:9bcdf88f62b0 940 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 941 * @retval State of Periphs (1 or 0).
<> 128:9bcdf88f62b0 942 */
<> 128:9bcdf88f62b0 943 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
<> 128:9bcdf88f62b0 944 {
<> 128:9bcdf88f62b0 945 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
<> 128:9bcdf88f62b0 946 }
<> 128:9bcdf88f62b0 947
<> 128:9bcdf88f62b0 948 /**
<> 128:9bcdf88f62b0 949 * @brief Disable APB2 peripherals clock.
<> 128:9bcdf88f62b0 950 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 951 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 952 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 953 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 954 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 955 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 956 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
<> 128:9bcdf88f62b0 957 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
<> 128:9bcdf88f62b0 958 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 959 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 128:9bcdf88f62b0 960 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 128:9bcdf88f62b0 961 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 128:9bcdf88f62b0 962 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 128:9bcdf88f62b0 963 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 128:9bcdf88f62b0 964 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 128:9bcdf88f62b0 965 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 128:9bcdf88f62b0 966 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 128:9bcdf88f62b0 967 *
<> 128:9bcdf88f62b0 968 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 969 * @retval None
<> 128:9bcdf88f62b0 970 */
<> 128:9bcdf88f62b0 971 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
<> 128:9bcdf88f62b0 972 {
<> 128:9bcdf88f62b0 973 CLEAR_BIT(RCC->APB2ENR, Periphs);
<> 128:9bcdf88f62b0 974 }
<> 128:9bcdf88f62b0 975
<> 128:9bcdf88f62b0 976 /**
<> 128:9bcdf88f62b0 977 * @brief Force APB2 peripherals reset.
<> 128:9bcdf88f62b0 978 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 979 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 980 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 981 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 982 * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 983 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 984 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
<> 128:9bcdf88f62b0 985 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
<> 128:9bcdf88f62b0 986 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 987 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
<> 128:9bcdf88f62b0 988 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 128:9bcdf88f62b0 989 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 128:9bcdf88f62b0 990 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 128:9bcdf88f62b0 991 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 128:9bcdf88f62b0 992 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 128:9bcdf88f62b0 993 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 128:9bcdf88f62b0 994 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 128:9bcdf88f62b0 995 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 128:9bcdf88f62b0 996 *
<> 128:9bcdf88f62b0 997 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 998 * @retval None
<> 128:9bcdf88f62b0 999 */
<> 128:9bcdf88f62b0 1000 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
<> 128:9bcdf88f62b0 1001 {
<> 128:9bcdf88f62b0 1002 SET_BIT(RCC->APB2RSTR, Periphs);
<> 128:9bcdf88f62b0 1003 }
<> 128:9bcdf88f62b0 1004
<> 128:9bcdf88f62b0 1005 /**
<> 128:9bcdf88f62b0 1006 * @brief Release APB2 peripherals reset.
<> 128:9bcdf88f62b0 1007 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 1008 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 1009 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 1010 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 1011 * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 1012 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 1013 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
<> 128:9bcdf88f62b0 1014 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
<> 128:9bcdf88f62b0 1015 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 1016 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
<> 128:9bcdf88f62b0 1017 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 128:9bcdf88f62b0 1018 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 128:9bcdf88f62b0 1019 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 128:9bcdf88f62b0 1020 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 128:9bcdf88f62b0 1021 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 128:9bcdf88f62b0 1022 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 128:9bcdf88f62b0 1023 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 128:9bcdf88f62b0 1024 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 128:9bcdf88f62b0 1025 *
<> 128:9bcdf88f62b0 1026 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 1027 * @retval None
<> 128:9bcdf88f62b0 1028 */
<> 128:9bcdf88f62b0 1029 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
<> 128:9bcdf88f62b0 1030 {
<> 128:9bcdf88f62b0 1031 CLEAR_BIT(RCC->APB2RSTR, Periphs);
<> 128:9bcdf88f62b0 1032 }
<> 128:9bcdf88f62b0 1033
<> 128:9bcdf88f62b0 1034 /**
<> 128:9bcdf88f62b0 1035 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
<> 128:9bcdf88f62b0 1036 * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 1037 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 1038 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 1039 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 1040 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 1041 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 1042 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
<> 128:9bcdf88f62b0 1043 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep
<> 128:9bcdf88f62b0 1044 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 1045 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 128:9bcdf88f62b0 1046 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 128:9bcdf88f62b0 1047 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 128:9bcdf88f62b0 1048 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 128:9bcdf88f62b0 1049 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 128:9bcdf88f62b0 1050 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 128:9bcdf88f62b0 1051 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 128:9bcdf88f62b0 1052 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 128:9bcdf88f62b0 1053 *
<> 128:9bcdf88f62b0 1054 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 1055 * @retval None
<> 128:9bcdf88f62b0 1056 */
<> 128:9bcdf88f62b0 1057 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
<> 128:9bcdf88f62b0 1058 {
<> 128:9bcdf88f62b0 1059 __IO uint32_t tmpreg;
<> 128:9bcdf88f62b0 1060 SET_BIT(RCC->APB2LPENR, Periphs);
<> 128:9bcdf88f62b0 1061 /* Delay after an RCC peripheral clock enabling */
<> 128:9bcdf88f62b0 1062 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
<> 128:9bcdf88f62b0 1063 (void)tmpreg;
<> 128:9bcdf88f62b0 1064 }
<> 128:9bcdf88f62b0 1065
<> 128:9bcdf88f62b0 1066 /**
<> 128:9bcdf88f62b0 1067 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
<> 128:9bcdf88f62b0 1068 * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 1069 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 1070 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 1071 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 1072 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 1073 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 1074 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
<> 128:9bcdf88f62b0 1075 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep
<> 128:9bcdf88f62b0 1076 * @param Periphs This parameter can be a combination of the following values:
<> 128:9bcdf88f62b0 1077 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 128:9bcdf88f62b0 1078 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 128:9bcdf88f62b0 1079 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 128:9bcdf88f62b0 1080 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 128:9bcdf88f62b0 1081 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 128:9bcdf88f62b0 1082 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 128:9bcdf88f62b0 1083 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 128:9bcdf88f62b0 1084 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 128:9bcdf88f62b0 1085 *
<> 128:9bcdf88f62b0 1086 * (*) value not defined in all devices.
<> 128:9bcdf88f62b0 1087 * @retval None
<> 128:9bcdf88f62b0 1088 */
<> 128:9bcdf88f62b0 1089 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
<> 128:9bcdf88f62b0 1090 {
<> 128:9bcdf88f62b0 1091 CLEAR_BIT(RCC->APB2LPENR, Periphs);
<> 128:9bcdf88f62b0 1092 }
<> 128:9bcdf88f62b0 1093
<> 128:9bcdf88f62b0 1094 /**
<> 128:9bcdf88f62b0 1095 * @}
<> 128:9bcdf88f62b0 1096 */
<> 128:9bcdf88f62b0 1097
<> 128:9bcdf88f62b0 1098
<> 128:9bcdf88f62b0 1099 /**
<> 128:9bcdf88f62b0 1100 * @}
<> 128:9bcdf88f62b0 1101 */
<> 128:9bcdf88f62b0 1102
<> 128:9bcdf88f62b0 1103 /**
<> 128:9bcdf88f62b0 1104 * @}
<> 128:9bcdf88f62b0 1105 */
<> 128:9bcdf88f62b0 1106
<> 128:9bcdf88f62b0 1107 #endif /* defined(RCC) */
<> 128:9bcdf88f62b0 1108
<> 128:9bcdf88f62b0 1109 /**
<> 128:9bcdf88f62b0 1110 * @}
<> 128:9bcdf88f62b0 1111 */
<> 128:9bcdf88f62b0 1112
<> 128:9bcdf88f62b0 1113 #ifdef __cplusplus
<> 128:9bcdf88f62b0 1114 }
<> 128:9bcdf88f62b0 1115 #endif
<> 128:9bcdf88f62b0 1116
<> 128:9bcdf88f62b0 1117 #endif /* __STM32L1xx_LL_BUS_H */
<> 128:9bcdf88f62b0 1118
<> 128:9bcdf88f62b0 1119 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/