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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rtc.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:: Kojto
Date:: Tue Oct 28 16:40:41 2014 +0000
Revision:: 90:cb3d968589d8

Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/*
Kojto	90:cb3d968589d8	2	** ###################################################################
Kojto	90:cb3d968589d8	3	** Compilers: Keil ARM C/C++ Compiler
Kojto	90:cb3d968589d8	4	** Freescale C/C++ for Embedded ARM
Kojto	90:cb3d968589d8	5	** GNU C Compiler
Kojto	90:cb3d968589d8	6	** IAR ANSI C/C++ Compiler for ARM
Kojto	90:cb3d968589d8	7	**
Kojto	90:cb3d968589d8	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto	90:cb3d968589d8	9	** Version: rev. 2.5, 2014-02-10
Kojto	90:cb3d968589d8	10	** Build: b140604
Kojto	90:cb3d968589d8	11	**
Kojto	90:cb3d968589d8	12	** Abstract:
Kojto	90:cb3d968589d8	13	** Extension to the CMSIS register access layer header.
Kojto	90:cb3d968589d8	14	**
Kojto	90:cb3d968589d8	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto	90:cb3d968589d8	16	** All rights reserved.
Kojto	90:cb3d968589d8	17	**
Kojto	90:cb3d968589d8	18	** Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	19	** are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	20	**
Kojto	90:cb3d968589d8	21	** o Redistributions of source code must retain the above copyright notice, this list
Kojto	90:cb3d968589d8	22	** of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	**
Kojto	90:cb3d968589d8	24	** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto	90:cb3d968589d8	25	** list of conditions and the following disclaimer in the documentation and/or
Kojto	90:cb3d968589d8	26	** other materials provided with the distribution.
Kojto	90:cb3d968589d8	27	**
Kojto	90:cb3d968589d8	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto	90:cb3d968589d8	29	** contributors may be used to endorse or promote products derived from this
Kojto	90:cb3d968589d8	30	** software without specific prior written permission.
Kojto	90:cb3d968589d8	31	**
Kojto	90:cb3d968589d8	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	90:cb3d968589d8	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	90:cb3d968589d8	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	90:cb3d968589d8	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	90:cb3d968589d8	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	90:cb3d968589d8	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	90:cb3d968589d8	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	90:cb3d968589d8	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	90:cb3d968589d8	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	42	**
Kojto	90:cb3d968589d8	43	** http: www.freescale.com
Kojto	90:cb3d968589d8	44	** mail: support@freescale.com
Kojto	90:cb3d968589d8	45	**
Kojto	90:cb3d968589d8	46	** Revisions:
Kojto	90:cb3d968589d8	47	** - rev. 1.0 (2013-08-12)
Kojto	90:cb3d968589d8	48	** Initial version.
Kojto	90:cb3d968589d8	49	** - rev. 2.0 (2013-10-29)
Kojto	90:cb3d968589d8	50	** Register accessor macros added to the memory map.
Kojto	90:cb3d968589d8	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto	90:cb3d968589d8	52	** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto	90:cb3d968589d8	53	** System initialization updated.
Kojto	90:cb3d968589d8	54	** MCG - registers updated.
Kojto	90:cb3d968589d8	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto	90:cb3d968589d8	56	** - rev. 2.1 (2013-10-30)
Kojto	90:cb3d968589d8	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto	90:cb3d968589d8	58	** - rev. 2.2 (2013-12-09)
Kojto	90:cb3d968589d8	59	** DMA - EARS register removed.
Kojto	90:cb3d968589d8	60	** AIPS0, AIPS1 - MPRA register updated.
Kojto	90:cb3d968589d8	61	** - rev. 2.3 (2014-01-24)
Kojto	90:cb3d968589d8	62	** Update according to reference manual rev. 2
Kojto	90:cb3d968589d8	63	** ENET, MCG, MCM, SIM, USB - registers updated
Kojto	90:cb3d968589d8	64	** - rev. 2.4 (2014-02-10)
Kojto	90:cb3d968589d8	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	67	** - rev. 2.5 (2014-02-10)
Kojto	90:cb3d968589d8	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto	90:cb3d968589d8	71	**
Kojto	90:cb3d968589d8	72	** ###################################################################
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/*
Kojto	90:cb3d968589d8	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto	90:cb3d968589d8	77	*
Kojto	90:cb3d968589d8	78	* This file was generated automatically and any changes may be lost.
Kojto	90:cb3d968589d8	79	*/
Kojto	90:cb3d968589d8	80	#ifndef __HW_RTC_REGISTERS_H__
Kojto	90:cb3d968589d8	81	#define __HW_RTC_REGISTERS_H__
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	#include "MK64F12.h"
Kojto	90:cb3d968589d8	84	#include "fsl_bitaccess.h"
Kojto	90:cb3d968589d8	85
Kojto	90:cb3d968589d8	86	/*
Kojto	90:cb3d968589d8	87	* MK64F12 RTC
Kojto	90:cb3d968589d8	88	*
Kojto	90:cb3d968589d8	89	* Secure Real Time Clock
Kojto	90:cb3d968589d8	90	*
Kojto	90:cb3d968589d8	91	* Registers defined in this header file:
Kojto	90:cb3d968589d8	92	* - HW_RTC_TSR - RTC Time Seconds Register
Kojto	90:cb3d968589d8	93	* - HW_RTC_TPR - RTC Time Prescaler Register
Kojto	90:cb3d968589d8	94	* - HW_RTC_TAR - RTC Time Alarm Register
Kojto	90:cb3d968589d8	95	* - HW_RTC_TCR - RTC Time Compensation Register
Kojto	90:cb3d968589d8	96	* - HW_RTC_CR - RTC Control Register
Kojto	90:cb3d968589d8	97	* - HW_RTC_SR - RTC Status Register
Kojto	90:cb3d968589d8	98	* - HW_RTC_LR - RTC Lock Register
Kojto	90:cb3d968589d8	99	* - HW_RTC_IER - RTC Interrupt Enable Register
Kojto	90:cb3d968589d8	100	* - HW_RTC_WAR - RTC Write Access Register
Kojto	90:cb3d968589d8	101	* - HW_RTC_RAR - RTC Read Access Register
Kojto	90:cb3d968589d8	102	*
Kojto	90:cb3d968589d8	103	* - hw_rtc_t - Struct containing all module registers.
Kojto	90:cb3d968589d8	104	*/
Kojto	90:cb3d968589d8	105
Kojto	90:cb3d968589d8	106	#define HW_RTC_INSTANCE_COUNT (1U) /!< Number of instances of the RTC module. /
Kojto	90:cb3d968589d8	107
Kojto	90:cb3d968589d8	108	/*******************************************************************************
Kojto	90:cb3d968589d8	109	* HW_RTC_TSR - RTC Time Seconds Register
Kojto	90:cb3d968589d8	110	******************************************************************************/
Kojto	90:cb3d968589d8	111
Kojto	90:cb3d968589d8	112	/*!
Kojto	90:cb3d968589d8	113	* @brief HW_RTC_TSR - RTC Time Seconds Register (RW)
Kojto	90:cb3d968589d8	114	*
Kojto	90:cb3d968589d8	115	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	116	*/
Kojto	90:cb3d968589d8	117	typedef union _hw_rtc_tsr
Kojto	90:cb3d968589d8	118	{
Kojto	90:cb3d968589d8	119	uint32_t U;
Kojto	90:cb3d968589d8	120	struct _hw_rtc_tsr_bitfields
Kojto	90:cb3d968589d8	121	{
Kojto	90:cb3d968589d8	122	uint32_t TSR : 32; /!< [31:0] Time Seconds Register /
Kojto	90:cb3d968589d8	123	} B;
Kojto	90:cb3d968589d8	124	} hw_rtc_tsr_t;
Kojto	90:cb3d968589d8	125
Kojto	90:cb3d968589d8	126	/*!
Kojto	90:cb3d968589d8	127	* @name Constants and macros for entire RTC_TSR register
Kojto	90:cb3d968589d8	128	*/
Kojto	90:cb3d968589d8	129	/@{/
Kojto	90:cb3d968589d8	130	#define HW_RTC_TSR_ADDR(x) ((x) + 0x0U)
Kojto	90:cb3d968589d8	131
Kojto	90:cb3d968589d8	132	#define HW_RTC_TSR(x) ((__IO hw_rtc_tsr_t ) HW_RTC_TSR_ADDR(x))
Kojto	90:cb3d968589d8	133	#define HW_RTC_TSR_RD(x) (HW_RTC_TSR(x).U)
Kojto	90:cb3d968589d8	134	#define HW_RTC_TSR_WR(x, v) (HW_RTC_TSR(x).U = (v))
Kojto	90:cb3d968589d8	135	#define HW_RTC_TSR_SET(x, v) (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	136	#define HW_RTC_TSR_CLR(x, v) (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	137	#define HW_RTC_TSR_TOG(x, v) (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	138	/@}/
Kojto	90:cb3d968589d8	139
Kojto	90:cb3d968589d8	140	/*
Kojto	90:cb3d968589d8	141	* Constants & macros for individual RTC_TSR bitfields
Kojto	90:cb3d968589d8	142	*/
Kojto	90:cb3d968589d8	143
Kojto	90:cb3d968589d8	144	/*!
Kojto	90:cb3d968589d8	145	* @name Register RTC_TSR, field TSR[31:0] (RW)
Kojto	90:cb3d968589d8	146	*
Kojto	90:cb3d968589d8	147	* When the time counter is enabled, the TSR is read only and increments once a
Kojto	90:cb3d968589d8	148	* second provided SR[TOF] or SR[TIF] are not set. The time counter will read as
Kojto	90:cb3d968589d8	149	* zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the
Kojto	90:cb3d968589d8	150	* TSR can be read or written. Writing to the TSR when the time counter is
Kojto	90:cb3d968589d8	151	* disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is
Kojto	90:cb3d968589d8	152	* supported, but not recommended because TSR will read as zero when SR[TIF] or
Kojto	90:cb3d968589d8	153	* SR[TOF] are set (indicating the time is invalid).
Kojto	90:cb3d968589d8	154	*/
Kojto	90:cb3d968589d8	155	/@{/
Kojto	90:cb3d968589d8	156	#define BP_RTC_TSR_TSR (0U) /!< Bit position for RTC_TSR_TSR. /
Kojto	90:cb3d968589d8	157	#define BM_RTC_TSR_TSR (0xFFFFFFFFU) /!< Bit mask for RTC_TSR_TSR. /
Kojto	90:cb3d968589d8	158	#define BS_RTC_TSR_TSR (32U) /!< Bit field size in bits for RTC_TSR_TSR. /
Kojto	90:cb3d968589d8	159
Kojto	90:cb3d968589d8	160	/! @brief Read current value of the RTC_TSR_TSR field. /
Kojto	90:cb3d968589d8	161	#define BR_RTC_TSR_TSR(x) (HW_RTC_TSR(x).U)
Kojto	90:cb3d968589d8	162
Kojto	90:cb3d968589d8	163	/! @brief Format value for bitfield RTC_TSR_TSR. /
Kojto	90:cb3d968589d8	164	#define BF_RTC_TSR_TSR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TSR_TSR) & BM_RTC_TSR_TSR)
Kojto	90:cb3d968589d8	165
Kojto	90:cb3d968589d8	166	/! @brief Set the TSR field to a new value. /
Kojto	90:cb3d968589d8	167	#define BW_RTC_TSR_TSR(x, v) (HW_RTC_TSR_WR(x, v))
Kojto	90:cb3d968589d8	168	/@}/
Kojto	90:cb3d968589d8	169
Kojto	90:cb3d968589d8	170	/*******************************************************************************
Kojto	90:cb3d968589d8	171	* HW_RTC_TPR - RTC Time Prescaler Register
Kojto	90:cb3d968589d8	172	******************************************************************************/
Kojto	90:cb3d968589d8	173
Kojto	90:cb3d968589d8	174	/*!
Kojto	90:cb3d968589d8	175	* @brief HW_RTC_TPR - RTC Time Prescaler Register (RW)
Kojto	90:cb3d968589d8	176	*
Kojto	90:cb3d968589d8	177	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	178	*/
Kojto	90:cb3d968589d8	179	typedef union _hw_rtc_tpr
Kojto	90:cb3d968589d8	180	{
Kojto	90:cb3d968589d8	181	uint32_t U;
Kojto	90:cb3d968589d8	182	struct _hw_rtc_tpr_bitfields
Kojto	90:cb3d968589d8	183	{
Kojto	90:cb3d968589d8	184	uint32_t TPR : 16; /!< [15:0] Time Prescaler Register /
Kojto	90:cb3d968589d8	185	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	186	} B;
Kojto	90:cb3d968589d8	187	} hw_rtc_tpr_t;
Kojto	90:cb3d968589d8	188
Kojto	90:cb3d968589d8	189	/*!
Kojto	90:cb3d968589d8	190	* @name Constants and macros for entire RTC_TPR register
Kojto	90:cb3d968589d8	191	*/
Kojto	90:cb3d968589d8	192	/@{/
Kojto	90:cb3d968589d8	193	#define HW_RTC_TPR_ADDR(x) ((x) + 0x4U)
Kojto	90:cb3d968589d8	194
Kojto	90:cb3d968589d8	195	#define HW_RTC_TPR(x) ((__IO hw_rtc_tpr_t ) HW_RTC_TPR_ADDR(x))
Kojto	90:cb3d968589d8	196	#define HW_RTC_TPR_RD(x) (HW_RTC_TPR(x).U)
Kojto	90:cb3d968589d8	197	#define HW_RTC_TPR_WR(x, v) (HW_RTC_TPR(x).U = (v))
Kojto	90:cb3d968589d8	198	#define HW_RTC_TPR_SET(x, v) (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	199	#define HW_RTC_TPR_CLR(x, v) (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	200	#define HW_RTC_TPR_TOG(x, v) (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	201	/@}/
Kojto	90:cb3d968589d8	202
Kojto	90:cb3d968589d8	203	/*
Kojto	90:cb3d968589d8	204	* Constants & macros for individual RTC_TPR bitfields
Kojto	90:cb3d968589d8	205	*/
Kojto	90:cb3d968589d8	206
Kojto	90:cb3d968589d8	207	/*!
Kojto	90:cb3d968589d8	208	* @name Register RTC_TPR, field TPR[15:0] (RW)
Kojto	90:cb3d968589d8	209	*
Kojto	90:cb3d968589d8	210	* When the time counter is enabled, the TPR is read only and increments every
Kojto	90:cb3d968589d8	211	* 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
Kojto	90:cb3d968589d8	212	* SR[TIF] are set. When the time counter is disabled, the TPR can be read or
Kojto	90:cb3d968589d8	213	* written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
Kojto	90:cb3d968589d8	214	* to a logic zero.
Kojto	90:cb3d968589d8	215	*/
Kojto	90:cb3d968589d8	216	/@{/
Kojto	90:cb3d968589d8	217	#define BP_RTC_TPR_TPR (0U) /!< Bit position for RTC_TPR_TPR. /
Kojto	90:cb3d968589d8	218	#define BM_RTC_TPR_TPR (0x0000FFFFU) /!< Bit mask for RTC_TPR_TPR. /
Kojto	90:cb3d968589d8	219	#define BS_RTC_TPR_TPR (16U) /!< Bit field size in bits for RTC_TPR_TPR. /
Kojto	90:cb3d968589d8	220
Kojto	90:cb3d968589d8	221	/! @brief Read current value of the RTC_TPR_TPR field. /
Kojto	90:cb3d968589d8	222	#define BR_RTC_TPR_TPR(x) (HW_RTC_TPR(x).B.TPR)
Kojto	90:cb3d968589d8	223
Kojto	90:cb3d968589d8	224	/! @brief Format value for bitfield RTC_TPR_TPR. /
Kojto	90:cb3d968589d8	225	#define BF_RTC_TPR_TPR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TPR_TPR) & BM_RTC_TPR_TPR)
Kojto	90:cb3d968589d8	226
Kojto	90:cb3d968589d8	227	/! @brief Set the TPR field to a new value. /
Kojto	90:cb3d968589d8	228	#define BW_RTC_TPR_TPR(x, v) (HW_RTC_TPR_WR(x, (HW_RTC_TPR_RD(x) & ~BM_RTC_TPR_TPR) \| BF_RTC_TPR_TPR(v)))
Kojto	90:cb3d968589d8	229	/@}/
Kojto	90:cb3d968589d8	230
Kojto	90:cb3d968589d8	231	/*******************************************************************************
Kojto	90:cb3d968589d8	232	* HW_RTC_TAR - RTC Time Alarm Register
Kojto	90:cb3d968589d8	233	******************************************************************************/
Kojto	90:cb3d968589d8	234
Kojto	90:cb3d968589d8	235	/*!
Kojto	90:cb3d968589d8	236	* @brief HW_RTC_TAR - RTC Time Alarm Register (RW)
Kojto	90:cb3d968589d8	237	*
Kojto	90:cb3d968589d8	238	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	239	*/
Kojto	90:cb3d968589d8	240	typedef union _hw_rtc_tar
Kojto	90:cb3d968589d8	241	{
Kojto	90:cb3d968589d8	242	uint32_t U;
Kojto	90:cb3d968589d8	243	struct _hw_rtc_tar_bitfields
Kojto	90:cb3d968589d8	244	{
Kojto	90:cb3d968589d8	245	uint32_t TAR : 32; /!< [31:0] Time Alarm Register /
Kojto	90:cb3d968589d8	246	} B;
Kojto	90:cb3d968589d8	247	} hw_rtc_tar_t;
Kojto	90:cb3d968589d8	248
Kojto	90:cb3d968589d8	249	/*!
Kojto	90:cb3d968589d8	250	* @name Constants and macros for entire RTC_TAR register
Kojto	90:cb3d968589d8	251	*/
Kojto	90:cb3d968589d8	252	/@{/
Kojto	90:cb3d968589d8	253	#define HW_RTC_TAR_ADDR(x) ((x) + 0x8U)
Kojto	90:cb3d968589d8	254
Kojto	90:cb3d968589d8	255	#define HW_RTC_TAR(x) ((__IO hw_rtc_tar_t ) HW_RTC_TAR_ADDR(x))
Kojto	90:cb3d968589d8	256	#define HW_RTC_TAR_RD(x) (HW_RTC_TAR(x).U)
Kojto	90:cb3d968589d8	257	#define HW_RTC_TAR_WR(x, v) (HW_RTC_TAR(x).U = (v))
Kojto	90:cb3d968589d8	258	#define HW_RTC_TAR_SET(x, v) (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	259	#define HW_RTC_TAR_CLR(x, v) (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	260	#define HW_RTC_TAR_TOG(x, v) (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	261	/@}/
Kojto	90:cb3d968589d8	262
Kojto	90:cb3d968589d8	263	/*
Kojto	90:cb3d968589d8	264	* Constants & macros for individual RTC_TAR bitfields
Kojto	90:cb3d968589d8	265	*/
Kojto	90:cb3d968589d8	266
Kojto	90:cb3d968589d8	267	/*!
Kojto	90:cb3d968589d8	268	* @name Register RTC_TAR, field TAR[31:0] (RW)
Kojto	90:cb3d968589d8	269	*
Kojto	90:cb3d968589d8	270	* When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR]
Kojto	90:cb3d968589d8	271	* equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the
Kojto	90:cb3d968589d8	272	* SR[TAF].
Kojto	90:cb3d968589d8	273	*/
Kojto	90:cb3d968589d8	274	/@{/
Kojto	90:cb3d968589d8	275	#define BP_RTC_TAR_TAR (0U) /!< Bit position for RTC_TAR_TAR. /
Kojto	90:cb3d968589d8	276	#define BM_RTC_TAR_TAR (0xFFFFFFFFU) /!< Bit mask for RTC_TAR_TAR. /
Kojto	90:cb3d968589d8	277	#define BS_RTC_TAR_TAR (32U) /!< Bit field size in bits for RTC_TAR_TAR. /
Kojto	90:cb3d968589d8	278
Kojto	90:cb3d968589d8	279	/! @brief Read current value of the RTC_TAR_TAR field. /
Kojto	90:cb3d968589d8	280	#define BR_RTC_TAR_TAR(x) (HW_RTC_TAR(x).U)
Kojto	90:cb3d968589d8	281
Kojto	90:cb3d968589d8	282	/! @brief Format value for bitfield RTC_TAR_TAR. /
Kojto	90:cb3d968589d8	283	#define BF_RTC_TAR_TAR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TAR_TAR) & BM_RTC_TAR_TAR)
Kojto	90:cb3d968589d8	284
Kojto	90:cb3d968589d8	285	/! @brief Set the TAR field to a new value. /
Kojto	90:cb3d968589d8	286	#define BW_RTC_TAR_TAR(x, v) (HW_RTC_TAR_WR(x, v))
Kojto	90:cb3d968589d8	287	/@}/
Kojto	90:cb3d968589d8	288
Kojto	90:cb3d968589d8	289	/*******************************************************************************
Kojto	90:cb3d968589d8	290	* HW_RTC_TCR - RTC Time Compensation Register
Kojto	90:cb3d968589d8	291	******************************************************************************/
Kojto	90:cb3d968589d8	292
Kojto	90:cb3d968589d8	293	/*!
Kojto	90:cb3d968589d8	294	* @brief HW_RTC_TCR - RTC Time Compensation Register (RW)
Kojto	90:cb3d968589d8	295	*
Kojto	90:cb3d968589d8	296	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	297	*/
Kojto	90:cb3d968589d8	298	typedef union _hw_rtc_tcr
Kojto	90:cb3d968589d8	299	{
Kojto	90:cb3d968589d8	300	uint32_t U;
Kojto	90:cb3d968589d8	301	struct _hw_rtc_tcr_bitfields
Kojto	90:cb3d968589d8	302	{
Kojto	90:cb3d968589d8	303	uint32_t TCR : 8; /!< [7:0] Time Compensation Register /
Kojto	90:cb3d968589d8	304	uint32_t CIR : 8; /!< [15:8] Compensation Interval Register /
Kojto	90:cb3d968589d8	305	uint32_t TCV : 8; /!< [23:16] Time Compensation Value /
Kojto	90:cb3d968589d8	306	uint32_t CIC : 8; /!< [31:24] Compensation Interval Counter /
Kojto	90:cb3d968589d8	307	} B;
Kojto	90:cb3d968589d8	308	} hw_rtc_tcr_t;
Kojto	90:cb3d968589d8	309
Kojto	90:cb3d968589d8	310	/*!
Kojto	90:cb3d968589d8	311	* @name Constants and macros for entire RTC_TCR register
Kojto	90:cb3d968589d8	312	*/
Kojto	90:cb3d968589d8	313	/@{/
Kojto	90:cb3d968589d8	314	#define HW_RTC_TCR_ADDR(x) ((x) + 0xCU)
Kojto	90:cb3d968589d8	315
Kojto	90:cb3d968589d8	316	#define HW_RTC_TCR(x) ((__IO hw_rtc_tcr_t ) HW_RTC_TCR_ADDR(x))
Kojto	90:cb3d968589d8	317	#define HW_RTC_TCR_RD(x) (HW_RTC_TCR(x).U)
Kojto	90:cb3d968589d8	318	#define HW_RTC_TCR_WR(x, v) (HW_RTC_TCR(x).U = (v))
Kojto	90:cb3d968589d8	319	#define HW_RTC_TCR_SET(x, v) (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	320	#define HW_RTC_TCR_CLR(x, v) (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	321	#define HW_RTC_TCR_TOG(x, v) (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	322	/@}/
Kojto	90:cb3d968589d8	323
Kojto	90:cb3d968589d8	324	/*
Kojto	90:cb3d968589d8	325	* Constants & macros for individual RTC_TCR bitfields
Kojto	90:cb3d968589d8	326	*/
Kojto	90:cb3d968589d8	327
Kojto	90:cb3d968589d8	328	/*!
Kojto	90:cb3d968589d8	329	* @name Register RTC_TCR, field TCR[7:0] (RW)
Kojto	90:cb3d968589d8	330	*
Kojto	90:cb3d968589d8	331	* Configures the number of 32.768 kHz clock cycles in each second. This
Kojto	90:cb3d968589d8	332	* register is double buffered and writes do not take affect until the end of the
Kojto	90:cb3d968589d8	333	* current compensation interval.
Kojto	90:cb3d968589d8	334	*
Kojto	90:cb3d968589d8	335	* Values:
Kojto	90:cb3d968589d8	336	* - 10000000 - Time Prescaler Register overflows every 32896 clock cycles.
Kojto	90:cb3d968589d8	337	* - 11111111 - Time Prescaler Register overflows every 32769 clock cycles.
Kojto	90:cb3d968589d8	338	* - 0 - Time Prescaler Register overflows every 32768 clock cycles.
Kojto	90:cb3d968589d8	339	* - 1 - Time Prescaler Register overflows every 32767 clock cycles.
Kojto	90:cb3d968589d8	340	* - 1111111 - Time Prescaler Register overflows every 32641 clock cycles.
Kojto	90:cb3d968589d8	341	*/
Kojto	90:cb3d968589d8	342	/@{/
Kojto	90:cb3d968589d8	343	#define BP_RTC_TCR_TCR (0U) /!< Bit position for RTC_TCR_TCR. /
Kojto	90:cb3d968589d8	344	#define BM_RTC_TCR_TCR (0x000000FFU) /!< Bit mask for RTC_TCR_TCR. /
Kojto	90:cb3d968589d8	345	#define BS_RTC_TCR_TCR (8U) /!< Bit field size in bits for RTC_TCR_TCR. /
Kojto	90:cb3d968589d8	346
Kojto	90:cb3d968589d8	347	/! @brief Read current value of the RTC_TCR_TCR field. /
Kojto	90:cb3d968589d8	348	#define BR_RTC_TCR_TCR(x) (HW_RTC_TCR(x).B.TCR)
Kojto	90:cb3d968589d8	349
Kojto	90:cb3d968589d8	350	/! @brief Format value for bitfield RTC_TCR_TCR. /
Kojto	90:cb3d968589d8	351	#define BF_RTC_TCR_TCR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TCR_TCR) & BM_RTC_TCR_TCR)
Kojto	90:cb3d968589d8	352
Kojto	90:cb3d968589d8	353	/! @brief Set the TCR field to a new value. /
Kojto	90:cb3d968589d8	354	#define BW_RTC_TCR_TCR(x, v) (HW_RTC_TCR_WR(x, (HW_RTC_TCR_RD(x) & ~BM_RTC_TCR_TCR) \| BF_RTC_TCR_TCR(v)))
Kojto	90:cb3d968589d8	355	/@}/
Kojto	90:cb3d968589d8	356
Kojto	90:cb3d968589d8	357	/*!
Kojto	90:cb3d968589d8	358	* @name Register RTC_TCR, field CIR[15:8] (RW)
Kojto	90:cb3d968589d8	359	*
Kojto	90:cb3d968589d8	360	* Configures the compensation interval in seconds from 1 to 256 to control how
Kojto	90:cb3d968589d8	361	* frequently the TCR should adjust the number of 32.768 kHz cycles in each
Kojto	90:cb3d968589d8	362	* second. The value written should be one less than the number of seconds. For
Kojto	90:cb3d968589d8	363	* example, write zero to configure for a compensation interval of one second. This
Kojto	90:cb3d968589d8	364	* register is double buffered and writes do not take affect until the end of the
Kojto	90:cb3d968589d8	365	* current compensation interval.
Kojto	90:cb3d968589d8	366	*/
Kojto	90:cb3d968589d8	367	/@{/
Kojto	90:cb3d968589d8	368	#define BP_RTC_TCR_CIR (8U) /!< Bit position for RTC_TCR_CIR. /
Kojto	90:cb3d968589d8	369	#define BM_RTC_TCR_CIR (0x0000FF00U) /!< Bit mask for RTC_TCR_CIR. /
Kojto	90:cb3d968589d8	370	#define BS_RTC_TCR_CIR (8U) /!< Bit field size in bits for RTC_TCR_CIR. /
Kojto	90:cb3d968589d8	371
Kojto	90:cb3d968589d8	372	/! @brief Read current value of the RTC_TCR_CIR field. /
Kojto	90:cb3d968589d8	373	#define BR_RTC_TCR_CIR(x) (HW_RTC_TCR(x).B.CIR)
Kojto	90:cb3d968589d8	374
Kojto	90:cb3d968589d8	375	/! @brief Format value for bitfield RTC_TCR_CIR. /
Kojto	90:cb3d968589d8	376	#define BF_RTC_TCR_CIR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_TCR_CIR) & BM_RTC_TCR_CIR)
Kojto	90:cb3d968589d8	377
Kojto	90:cb3d968589d8	378	/! @brief Set the CIR field to a new value. /
Kojto	90:cb3d968589d8	379	#define BW_RTC_TCR_CIR(x, v) (HW_RTC_TCR_WR(x, (HW_RTC_TCR_RD(x) & ~BM_RTC_TCR_CIR) \| BF_RTC_TCR_CIR(v)))
Kojto	90:cb3d968589d8	380	/@}/
Kojto	90:cb3d968589d8	381
Kojto	90:cb3d968589d8	382	/*!
Kojto	90:cb3d968589d8	383	* @name Register RTC_TCR, field TCV[23:16] (RO)
Kojto	90:cb3d968589d8	384	*
Kojto	90:cb3d968589d8	385	* Current value used by the compensation logic for the present second interval.
Kojto	90:cb3d968589d8	386	* Updated once a second if the CIC equals 0 with the contents of the TCR field.
Kojto	90:cb3d968589d8	387	* If the CIC does not equal zero then it is loaded with zero (compensation is
Kojto	90:cb3d968589d8	388	* not enabled for that second increment).
Kojto	90:cb3d968589d8	389	*/
Kojto	90:cb3d968589d8	390	/@{/
Kojto	90:cb3d968589d8	391	#define BP_RTC_TCR_TCV (16U) /!< Bit position for RTC_TCR_TCV. /
Kojto	90:cb3d968589d8	392	#define BM_RTC_TCR_TCV (0x00FF0000U) /!< Bit mask for RTC_TCR_TCV. /
Kojto	90:cb3d968589d8	393	#define BS_RTC_TCR_TCV (8U) /!< Bit field size in bits for RTC_TCR_TCV. /
Kojto	90:cb3d968589d8	394
Kojto	90:cb3d968589d8	395	/! @brief Read current value of the RTC_TCR_TCV field. /
Kojto	90:cb3d968589d8	396	#define BR_RTC_TCR_TCV(x) (HW_RTC_TCR(x).B.TCV)
Kojto	90:cb3d968589d8	397	/@}/
Kojto	90:cb3d968589d8	398
Kojto	90:cb3d968589d8	399	/*!
Kojto	90:cb3d968589d8	400	* @name Register RTC_TCR, field CIC[31:24] (RO)
Kojto	90:cb3d968589d8	401	*
Kojto	90:cb3d968589d8	402	* Current value of the compensation interval counter. If the compensation
Kojto	90:cb3d968589d8	403	* interval counter equals zero then it is loaded with the contents of the CIR. If the
Kojto	90:cb3d968589d8	404	* CIC does not equal zero then it is decremented once a second.
Kojto	90:cb3d968589d8	405	*/
Kojto	90:cb3d968589d8	406	/@{/
Kojto	90:cb3d968589d8	407	#define BP_RTC_TCR_CIC (24U) /!< Bit position for RTC_TCR_CIC. /
Kojto	90:cb3d968589d8	408	#define BM_RTC_TCR_CIC (0xFF000000U) /!< Bit mask for RTC_TCR_CIC. /
Kojto	90:cb3d968589d8	409	#define BS_RTC_TCR_CIC (8U) /!< Bit field size in bits for RTC_TCR_CIC. /
Kojto	90:cb3d968589d8	410
Kojto	90:cb3d968589d8	411	/! @brief Read current value of the RTC_TCR_CIC field. /
Kojto	90:cb3d968589d8	412	#define BR_RTC_TCR_CIC(x) (HW_RTC_TCR(x).B.CIC)
Kojto	90:cb3d968589d8	413	/@}/
Kojto	90:cb3d968589d8	414
Kojto	90:cb3d968589d8	415	/*******************************************************************************
Kojto	90:cb3d968589d8	416	* HW_RTC_CR - RTC Control Register
Kojto	90:cb3d968589d8	417	******************************************************************************/
Kojto	90:cb3d968589d8	418
Kojto	90:cb3d968589d8	419	/*!
Kojto	90:cb3d968589d8	420	* @brief HW_RTC_CR - RTC Control Register (RW)
Kojto	90:cb3d968589d8	421	*
Kojto	90:cb3d968589d8	422	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	423	*/
Kojto	90:cb3d968589d8	424	typedef union _hw_rtc_cr
Kojto	90:cb3d968589d8	425	{
Kojto	90:cb3d968589d8	426	uint32_t U;
Kojto	90:cb3d968589d8	427	struct _hw_rtc_cr_bitfields
Kojto	90:cb3d968589d8	428	{
Kojto	90:cb3d968589d8	429	uint32_t SWR : 1; /!< [0] Software Reset /
Kojto	90:cb3d968589d8	430	uint32_t WPE : 1; /!< [1] Wakeup Pin Enable /
Kojto	90:cb3d968589d8	431	uint32_t SUP : 1; /!< [2] Supervisor Access /
Kojto	90:cb3d968589d8	432	uint32_t UM : 1; /!< [3] Update Mode /
Kojto	90:cb3d968589d8	433	uint32_t WPS : 1; /!< [4] Wakeup Pin Select /
Kojto	90:cb3d968589d8	434	uint32_t RESERVED0 : 3; /!< [7:5] /
Kojto	90:cb3d968589d8	435	uint32_t OSCE : 1; /!< [8] Oscillator Enable /
Kojto	90:cb3d968589d8	436	uint32_t CLKO : 1; /!< [9] Clock Output /
Kojto	90:cb3d968589d8	437	uint32_t SC16P : 1; /!< [10] Oscillator 16pF Load Configure /
Kojto	90:cb3d968589d8	438	uint32_t SC8P : 1; /!< [11] Oscillator 8pF Load Configure /
Kojto	90:cb3d968589d8	439	uint32_t SC4P : 1; /!< [12] Oscillator 4pF Load Configure /
Kojto	90:cb3d968589d8	440	uint32_t SC2P : 1; /!< [13] Oscillator 2pF Load Configure /
Kojto	90:cb3d968589d8	441	uint32_t RESERVED1 : 18; /!< [31:14] /
Kojto	90:cb3d968589d8	442	} B;
Kojto	90:cb3d968589d8	443	} hw_rtc_cr_t;
Kojto	90:cb3d968589d8	444
Kojto	90:cb3d968589d8	445	/*!
Kojto	90:cb3d968589d8	446	* @name Constants and macros for entire RTC_CR register
Kojto	90:cb3d968589d8	447	*/
Kojto	90:cb3d968589d8	448	/@{/
Kojto	90:cb3d968589d8	449	#define HW_RTC_CR_ADDR(x) ((x) + 0x10U)
Kojto	90:cb3d968589d8	450
Kojto	90:cb3d968589d8	451	#define HW_RTC_CR(x) ((__IO hw_rtc_cr_t ) HW_RTC_CR_ADDR(x))
Kojto	90:cb3d968589d8	452	#define HW_RTC_CR_RD(x) (HW_RTC_CR(x).U)
Kojto	90:cb3d968589d8	453	#define HW_RTC_CR_WR(x, v) (HW_RTC_CR(x).U = (v))
Kojto	90:cb3d968589d8	454	#define HW_RTC_CR_SET(x, v) (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	455	#define HW_RTC_CR_CLR(x, v) (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	456	#define HW_RTC_CR_TOG(x, v) (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	457	/@}/
Kojto	90:cb3d968589d8	458
Kojto	90:cb3d968589d8	459	/*
Kojto	90:cb3d968589d8	460	* Constants & macros for individual RTC_CR bitfields
Kojto	90:cb3d968589d8	461	*/
Kojto	90:cb3d968589d8	462
Kojto	90:cb3d968589d8	463	/*!
Kojto	90:cb3d968589d8	464	* @name Register RTC_CR, field SWR[0] (RW)
Kojto	90:cb3d968589d8	465	*
Kojto	90:cb3d968589d8	466	* Values:
Kojto	90:cb3d968589d8	467	* - 0 - No effect.
Kojto	90:cb3d968589d8	468	* - 1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
Kojto	90:cb3d968589d8	469	* RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
Kojto	90:cb3d968589d8	470	* explicitly clearing it.
Kojto	90:cb3d968589d8	471	*/
Kojto	90:cb3d968589d8	472	/@{/
Kojto	90:cb3d968589d8	473	#define BP_RTC_CR_SWR (0U) /!< Bit position for RTC_CR_SWR. /
Kojto	90:cb3d968589d8	474	#define BM_RTC_CR_SWR (0x00000001U) /!< Bit mask for RTC_CR_SWR. /
Kojto	90:cb3d968589d8	475	#define BS_RTC_CR_SWR (1U) /!< Bit field size in bits for RTC_CR_SWR. /
Kojto	90:cb3d968589d8	476
Kojto	90:cb3d968589d8	477	/! @brief Read current value of the RTC_CR_SWR field. /
Kojto	90:cb3d968589d8	478	#define BR_RTC_CR_SWR(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SWR))
Kojto	90:cb3d968589d8	479
Kojto	90:cb3d968589d8	480	/! @brief Format value for bitfield RTC_CR_SWR. /
Kojto	90:cb3d968589d8	481	#define BF_RTC_CR_SWR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SWR) & BM_RTC_CR_SWR)
Kojto	90:cb3d968589d8	482
Kojto	90:cb3d968589d8	483	/! @brief Set the SWR field to a new value. /
Kojto	90:cb3d968589d8	484	#define BW_RTC_CR_SWR(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SWR) = (v))
Kojto	90:cb3d968589d8	485	/@}/
Kojto	90:cb3d968589d8	486
Kojto	90:cb3d968589d8	487	/*!
Kojto	90:cb3d968589d8	488	* @name Register RTC_CR, field WPE[1] (RW)
Kojto	90:cb3d968589d8	489	*
Kojto	90:cb3d968589d8	490	* The wakeup pin is optional and not available on all devices.
Kojto	90:cb3d968589d8	491	*
Kojto	90:cb3d968589d8	492	* Values:
Kojto	90:cb3d968589d8	493	* - 0 - Wakeup pin is disabled.
Kojto	90:cb3d968589d8	494	* - 1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
Kojto	90:cb3d968589d8	495	* asserts or the wakeup pin is turned on.
Kojto	90:cb3d968589d8	496	*/
Kojto	90:cb3d968589d8	497	/@{/
Kojto	90:cb3d968589d8	498	#define BP_RTC_CR_WPE (1U) /!< Bit position for RTC_CR_WPE. /
Kojto	90:cb3d968589d8	499	#define BM_RTC_CR_WPE (0x00000002U) /!< Bit mask for RTC_CR_WPE. /
Kojto	90:cb3d968589d8	500	#define BS_RTC_CR_WPE (1U) /!< Bit field size in bits for RTC_CR_WPE. /
Kojto	90:cb3d968589d8	501
Kojto	90:cb3d968589d8	502	/! @brief Read current value of the RTC_CR_WPE field. /
Kojto	90:cb3d968589d8	503	#define BR_RTC_CR_WPE(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPE))
Kojto	90:cb3d968589d8	504
Kojto	90:cb3d968589d8	505	/! @brief Format value for bitfield RTC_CR_WPE. /
Kojto	90:cb3d968589d8	506	#define BF_RTC_CR_WPE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_WPE) & BM_RTC_CR_WPE)
Kojto	90:cb3d968589d8	507
Kojto	90:cb3d968589d8	508	/! @brief Set the WPE field to a new value. /
Kojto	90:cb3d968589d8	509	#define BW_RTC_CR_WPE(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPE) = (v))
Kojto	90:cb3d968589d8	510	/@}/
Kojto	90:cb3d968589d8	511
Kojto	90:cb3d968589d8	512	/*!
Kojto	90:cb3d968589d8	513	* @name Register RTC_CR, field SUP[2] (RW)
Kojto	90:cb3d968589d8	514	*
Kojto	90:cb3d968589d8	515	* Values:
Kojto	90:cb3d968589d8	516	* - 0 - Non-supervisor mode write accesses are not supported and generate a bus
Kojto	90:cb3d968589d8	517	* error.
Kojto	90:cb3d968589d8	518	* - 1 - Non-supervisor mode write accesses are supported.
Kojto	90:cb3d968589d8	519	*/
Kojto	90:cb3d968589d8	520	/@{/
Kojto	90:cb3d968589d8	521	#define BP_RTC_CR_SUP (2U) /!< Bit position for RTC_CR_SUP. /
Kojto	90:cb3d968589d8	522	#define BM_RTC_CR_SUP (0x00000004U) /!< Bit mask for RTC_CR_SUP. /
Kojto	90:cb3d968589d8	523	#define BS_RTC_CR_SUP (1U) /!< Bit field size in bits for RTC_CR_SUP. /
Kojto	90:cb3d968589d8	524
Kojto	90:cb3d968589d8	525	/! @brief Read current value of the RTC_CR_SUP field. /
Kojto	90:cb3d968589d8	526	#define BR_RTC_CR_SUP(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SUP))
Kojto	90:cb3d968589d8	527
Kojto	90:cb3d968589d8	528	/! @brief Format value for bitfield RTC_CR_SUP. /
Kojto	90:cb3d968589d8	529	#define BF_RTC_CR_SUP(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SUP) & BM_RTC_CR_SUP)
Kojto	90:cb3d968589d8	530
Kojto	90:cb3d968589d8	531	/! @brief Set the SUP field to a new value. /
Kojto	90:cb3d968589d8	532	#define BW_RTC_CR_SUP(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SUP) = (v))
Kojto	90:cb3d968589d8	533	/@}/
Kojto	90:cb3d968589d8	534
Kojto	90:cb3d968589d8	535	/*!
Kojto	90:cb3d968589d8	536	* @name Register RTC_CR, field UM[3] (RW)
Kojto	90:cb3d968589d8	537	*
Kojto	90:cb3d968589d8	538	* Allows SR[TCE] to be written even when the Status Register is locked. When
Kojto	90:cb3d968589d8	539	* set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
Kojto	90:cb3d968589d8	540	* the SR[TCE] is clear.
Kojto	90:cb3d968589d8	541	*
Kojto	90:cb3d968589d8	542	* Values:
Kojto	90:cb3d968589d8	543	* - 0 - Registers cannot be written when locked.
Kojto	90:cb3d968589d8	544	* - 1 - Registers can be written when locked under limited conditions.
Kojto	90:cb3d968589d8	545	*/
Kojto	90:cb3d968589d8	546	/@{/
Kojto	90:cb3d968589d8	547	#define BP_RTC_CR_UM (3U) /!< Bit position for RTC_CR_UM. /
Kojto	90:cb3d968589d8	548	#define BM_RTC_CR_UM (0x00000008U) /!< Bit mask for RTC_CR_UM. /
Kojto	90:cb3d968589d8	549	#define BS_RTC_CR_UM (1U) /!< Bit field size in bits for RTC_CR_UM. /
Kojto	90:cb3d968589d8	550
Kojto	90:cb3d968589d8	551	/! @brief Read current value of the RTC_CR_UM field. /
Kojto	90:cb3d968589d8	552	#define BR_RTC_CR_UM(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_UM))
Kojto	90:cb3d968589d8	553
Kojto	90:cb3d968589d8	554	/! @brief Format value for bitfield RTC_CR_UM. /
Kojto	90:cb3d968589d8	555	#define BF_RTC_CR_UM(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_UM) & BM_RTC_CR_UM)
Kojto	90:cb3d968589d8	556
Kojto	90:cb3d968589d8	557	/! @brief Set the UM field to a new value. /
Kojto	90:cb3d968589d8	558	#define BW_RTC_CR_UM(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_UM) = (v))
Kojto	90:cb3d968589d8	559	/@}/
Kojto	90:cb3d968589d8	560
Kojto	90:cb3d968589d8	561	/*!
Kojto	90:cb3d968589d8	562	* @name Register RTC_CR, field WPS[4] (RW)
Kojto	90:cb3d968589d8	563	*
Kojto	90:cb3d968589d8	564	* The wakeup pin is optional and not available on all devices.
Kojto	90:cb3d968589d8	565	*
Kojto	90:cb3d968589d8	566	* Values:
Kojto	90:cb3d968589d8	567	* - 0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
Kojto	90:cb3d968589d8	568	* asserts or the wakeup pin is turned on.
Kojto	90:cb3d968589d8	569	* - 1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin
Kojto	90:cb3d968589d8	570	* is turned on and the 32kHz clock is output to other peripherals.
Kojto	90:cb3d968589d8	571	*/
Kojto	90:cb3d968589d8	572	/@{/
Kojto	90:cb3d968589d8	573	#define BP_RTC_CR_WPS (4U) /!< Bit position for RTC_CR_WPS. /
Kojto	90:cb3d968589d8	574	#define BM_RTC_CR_WPS (0x00000010U) /!< Bit mask for RTC_CR_WPS. /
Kojto	90:cb3d968589d8	575	#define BS_RTC_CR_WPS (1U) /!< Bit field size in bits for RTC_CR_WPS. /
Kojto	90:cb3d968589d8	576
Kojto	90:cb3d968589d8	577	/! @brief Read current value of the RTC_CR_WPS field. /
Kojto	90:cb3d968589d8	578	#define BR_RTC_CR_WPS(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPS))
Kojto	90:cb3d968589d8	579
Kojto	90:cb3d968589d8	580	/! @brief Format value for bitfield RTC_CR_WPS. /
Kojto	90:cb3d968589d8	581	#define BF_RTC_CR_WPS(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_WPS) & BM_RTC_CR_WPS)
Kojto	90:cb3d968589d8	582
Kojto	90:cb3d968589d8	583	/! @brief Set the WPS field to a new value. /
Kojto	90:cb3d968589d8	584	#define BW_RTC_CR_WPS(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPS) = (v))
Kojto	90:cb3d968589d8	585	/@}/
Kojto	90:cb3d968589d8	586
Kojto	90:cb3d968589d8	587	/*!
Kojto	90:cb3d968589d8	588	* @name Register RTC_CR, field OSCE[8] (RW)
Kojto	90:cb3d968589d8	589	*
Kojto	90:cb3d968589d8	590	* Values:
Kojto	90:cb3d968589d8	591	* - 0 - 32.768 kHz oscillator is disabled.
Kojto	90:cb3d968589d8	592	* - 1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
Kojto	90:cb3d968589d8	593	* oscillator startup time before enabling the time counter to allow the 32.768
Kojto	90:cb3d968589d8	594	* kHz clock time to stabilize.
Kojto	90:cb3d968589d8	595	*/
Kojto	90:cb3d968589d8	596	/@{/
Kojto	90:cb3d968589d8	597	#define BP_RTC_CR_OSCE (8U) /!< Bit position for RTC_CR_OSCE. /
Kojto	90:cb3d968589d8	598	#define BM_RTC_CR_OSCE (0x00000100U) /!< Bit mask for RTC_CR_OSCE. /
Kojto	90:cb3d968589d8	599	#define BS_RTC_CR_OSCE (1U) /!< Bit field size in bits for RTC_CR_OSCE. /
Kojto	90:cb3d968589d8	600
Kojto	90:cb3d968589d8	601	/! @brief Read current value of the RTC_CR_OSCE field. /
Kojto	90:cb3d968589d8	602	#define BR_RTC_CR_OSCE(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_OSCE))
Kojto	90:cb3d968589d8	603
Kojto	90:cb3d968589d8	604	/! @brief Format value for bitfield RTC_CR_OSCE. /
Kojto	90:cb3d968589d8	605	#define BF_RTC_CR_OSCE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_OSCE) & BM_RTC_CR_OSCE)
Kojto	90:cb3d968589d8	606
Kojto	90:cb3d968589d8	607	/! @brief Set the OSCE field to a new value. /
Kojto	90:cb3d968589d8	608	#define BW_RTC_CR_OSCE(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_OSCE) = (v))
Kojto	90:cb3d968589d8	609	/@}/
Kojto	90:cb3d968589d8	610
Kojto	90:cb3d968589d8	611	/*!
Kojto	90:cb3d968589d8	612	* @name Register RTC_CR, field CLKO[9] (RW)
Kojto	90:cb3d968589d8	613	*
Kojto	90:cb3d968589d8	614	* Values:
Kojto	90:cb3d968589d8	615	* - 0 - The 32 kHz clock is output to other peripherals.
Kojto	90:cb3d968589d8	616	* - 1 - The 32 kHz clock is not output to other peripherals.
Kojto	90:cb3d968589d8	617	*/
Kojto	90:cb3d968589d8	618	/@{/
Kojto	90:cb3d968589d8	619	#define BP_RTC_CR_CLKO (9U) /!< Bit position for RTC_CR_CLKO. /
Kojto	90:cb3d968589d8	620	#define BM_RTC_CR_CLKO (0x00000200U) /!< Bit mask for RTC_CR_CLKO. /
Kojto	90:cb3d968589d8	621	#define BS_RTC_CR_CLKO (1U) /!< Bit field size in bits for RTC_CR_CLKO. /
Kojto	90:cb3d968589d8	622
Kojto	90:cb3d968589d8	623	/! @brief Read current value of the RTC_CR_CLKO field. /
Kojto	90:cb3d968589d8	624	#define BR_RTC_CR_CLKO(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_CLKO))
Kojto	90:cb3d968589d8	625
Kojto	90:cb3d968589d8	626	/! @brief Format value for bitfield RTC_CR_CLKO. /
Kojto	90:cb3d968589d8	627	#define BF_RTC_CR_CLKO(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_CLKO) & BM_RTC_CR_CLKO)
Kojto	90:cb3d968589d8	628
Kojto	90:cb3d968589d8	629	/! @brief Set the CLKO field to a new value. /
Kojto	90:cb3d968589d8	630	#define BW_RTC_CR_CLKO(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_CLKO) = (v))
Kojto	90:cb3d968589d8	631	/@}/
Kojto	90:cb3d968589d8	632
Kojto	90:cb3d968589d8	633	/*!
Kojto	90:cb3d968589d8	634	* @name Register RTC_CR, field SC16P[10] (RW)
Kojto	90:cb3d968589d8	635	*
Kojto	90:cb3d968589d8	636	* Values:
Kojto	90:cb3d968589d8	637	* - 0 - Disable the load.
Kojto	90:cb3d968589d8	638	* - 1 - Enable the additional load.
Kojto	90:cb3d968589d8	639	*/
Kojto	90:cb3d968589d8	640	/@{/
Kojto	90:cb3d968589d8	641	#define BP_RTC_CR_SC16P (10U) /!< Bit position for RTC_CR_SC16P. /
Kojto	90:cb3d968589d8	642	#define BM_RTC_CR_SC16P (0x00000400U) /!< Bit mask for RTC_CR_SC16P. /
Kojto	90:cb3d968589d8	643	#define BS_RTC_CR_SC16P (1U) /!< Bit field size in bits for RTC_CR_SC16P. /
Kojto	90:cb3d968589d8	644
Kojto	90:cb3d968589d8	645	/! @brief Read current value of the RTC_CR_SC16P field. /
Kojto	90:cb3d968589d8	646	#define BR_RTC_CR_SC16P(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC16P))
Kojto	90:cb3d968589d8	647
Kojto	90:cb3d968589d8	648	/! @brief Format value for bitfield RTC_CR_SC16P. /
Kojto	90:cb3d968589d8	649	#define BF_RTC_CR_SC16P(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC16P) & BM_RTC_CR_SC16P)
Kojto	90:cb3d968589d8	650
Kojto	90:cb3d968589d8	651	/! @brief Set the SC16P field to a new value. /
Kojto	90:cb3d968589d8	652	#define BW_RTC_CR_SC16P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC16P) = (v))
Kojto	90:cb3d968589d8	653	/@}/
Kojto	90:cb3d968589d8	654
Kojto	90:cb3d968589d8	655	/*!
Kojto	90:cb3d968589d8	656	* @name Register RTC_CR, field SC8P[11] (RW)
Kojto	90:cb3d968589d8	657	*
Kojto	90:cb3d968589d8	658	* Values:
Kojto	90:cb3d968589d8	659	* - 0 - Disable the load.
Kojto	90:cb3d968589d8	660	* - 1 - Enable the additional load.
Kojto	90:cb3d968589d8	661	*/
Kojto	90:cb3d968589d8	662	/@{/
Kojto	90:cb3d968589d8	663	#define BP_RTC_CR_SC8P (11U) /!< Bit position for RTC_CR_SC8P. /
Kojto	90:cb3d968589d8	664	#define BM_RTC_CR_SC8P (0x00000800U) /!< Bit mask for RTC_CR_SC8P. /
Kojto	90:cb3d968589d8	665	#define BS_RTC_CR_SC8P (1U) /!< Bit field size in bits for RTC_CR_SC8P. /
Kojto	90:cb3d968589d8	666
Kojto	90:cb3d968589d8	667	/! @brief Read current value of the RTC_CR_SC8P field. /
Kojto	90:cb3d968589d8	668	#define BR_RTC_CR_SC8P(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC8P))
Kojto	90:cb3d968589d8	669
Kojto	90:cb3d968589d8	670	/! @brief Format value for bitfield RTC_CR_SC8P. /
Kojto	90:cb3d968589d8	671	#define BF_RTC_CR_SC8P(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC8P) & BM_RTC_CR_SC8P)
Kojto	90:cb3d968589d8	672
Kojto	90:cb3d968589d8	673	/! @brief Set the SC8P field to a new value. /
Kojto	90:cb3d968589d8	674	#define BW_RTC_CR_SC8P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC8P) = (v))
Kojto	90:cb3d968589d8	675	/@}/
Kojto	90:cb3d968589d8	676
Kojto	90:cb3d968589d8	677	/*!
Kojto	90:cb3d968589d8	678	* @name Register RTC_CR, field SC4P[12] (RW)
Kojto	90:cb3d968589d8	679	*
Kojto	90:cb3d968589d8	680	* Values:
Kojto	90:cb3d968589d8	681	* - 0 - Disable the load.
Kojto	90:cb3d968589d8	682	* - 1 - Enable the additional load.
Kojto	90:cb3d968589d8	683	*/
Kojto	90:cb3d968589d8	684	/@{/
Kojto	90:cb3d968589d8	685	#define BP_RTC_CR_SC4P (12U) /!< Bit position for RTC_CR_SC4P. /
Kojto	90:cb3d968589d8	686	#define BM_RTC_CR_SC4P (0x00001000U) /!< Bit mask for RTC_CR_SC4P. /
Kojto	90:cb3d968589d8	687	#define BS_RTC_CR_SC4P (1U) /!< Bit field size in bits for RTC_CR_SC4P. /
Kojto	90:cb3d968589d8	688
Kojto	90:cb3d968589d8	689	/! @brief Read current value of the RTC_CR_SC4P field. /
Kojto	90:cb3d968589d8	690	#define BR_RTC_CR_SC4P(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC4P))
Kojto	90:cb3d968589d8	691
Kojto	90:cb3d968589d8	692	/! @brief Format value for bitfield RTC_CR_SC4P. /
Kojto	90:cb3d968589d8	693	#define BF_RTC_CR_SC4P(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC4P) & BM_RTC_CR_SC4P)
Kojto	90:cb3d968589d8	694
Kojto	90:cb3d968589d8	695	/! @brief Set the SC4P field to a new value. /
Kojto	90:cb3d968589d8	696	#define BW_RTC_CR_SC4P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC4P) = (v))
Kojto	90:cb3d968589d8	697	/@}/
Kojto	90:cb3d968589d8	698
Kojto	90:cb3d968589d8	699	/*!
Kojto	90:cb3d968589d8	700	* @name Register RTC_CR, field SC2P[13] (RW)
Kojto	90:cb3d968589d8	701	*
Kojto	90:cb3d968589d8	702	* Values:
Kojto	90:cb3d968589d8	703	* - 0 - Disable the load.
Kojto	90:cb3d968589d8	704	* - 1 - Enable the additional load.
Kojto	90:cb3d968589d8	705	*/
Kojto	90:cb3d968589d8	706	/@{/
Kojto	90:cb3d968589d8	707	#define BP_RTC_CR_SC2P (13U) /!< Bit position for RTC_CR_SC2P. /
Kojto	90:cb3d968589d8	708	#define BM_RTC_CR_SC2P (0x00002000U) /!< Bit mask for RTC_CR_SC2P. /
Kojto	90:cb3d968589d8	709	#define BS_RTC_CR_SC2P (1U) /!< Bit field size in bits for RTC_CR_SC2P. /
Kojto	90:cb3d968589d8	710
Kojto	90:cb3d968589d8	711	/! @brief Read current value of the RTC_CR_SC2P field. /
Kojto	90:cb3d968589d8	712	#define BR_RTC_CR_SC2P(x) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC2P))
Kojto	90:cb3d968589d8	713
Kojto	90:cb3d968589d8	714	/! @brief Format value for bitfield RTC_CR_SC2P. /
Kojto	90:cb3d968589d8	715	#define BF_RTC_CR_SC2P(v) ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC2P) & BM_RTC_CR_SC2P)
Kojto	90:cb3d968589d8	716
Kojto	90:cb3d968589d8	717	/! @brief Set the SC2P field to a new value. /
Kojto	90:cb3d968589d8	718	#define BW_RTC_CR_SC2P(x, v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC2P) = (v))
Kojto	90:cb3d968589d8	719	/@}/
Kojto	90:cb3d968589d8	720
Kojto	90:cb3d968589d8	721	/*******************************************************************************
Kojto	90:cb3d968589d8	722	* HW_RTC_SR - RTC Status Register
Kojto	90:cb3d968589d8	723	******************************************************************************/
Kojto	90:cb3d968589d8	724
Kojto	90:cb3d968589d8	725	/*!
Kojto	90:cb3d968589d8	726	* @brief HW_RTC_SR - RTC Status Register (RW)
Kojto	90:cb3d968589d8	727	*
Kojto	90:cb3d968589d8	728	* Reset value: 0x00000001U
Kojto	90:cb3d968589d8	729	*/
Kojto	90:cb3d968589d8	730	typedef union _hw_rtc_sr
Kojto	90:cb3d968589d8	731	{
Kojto	90:cb3d968589d8	732	uint32_t U;
Kojto	90:cb3d968589d8	733	struct _hw_rtc_sr_bitfields
Kojto	90:cb3d968589d8	734	{
Kojto	90:cb3d968589d8	735	uint32_t TIF : 1; /!< [0] Time Invalid Flag /
Kojto	90:cb3d968589d8	736	uint32_t TOF : 1; /!< [1] Time Overflow Flag /
Kojto	90:cb3d968589d8	737	uint32_t TAF : 1; /!< [2] Time Alarm Flag /
Kojto	90:cb3d968589d8	738	uint32_t RESERVED0 : 1; /!< [3] /
Kojto	90:cb3d968589d8	739	uint32_t TCE : 1; /!< [4] Time Counter Enable /
Kojto	90:cb3d968589d8	740	uint32_t RESERVED1 : 27; /!< [31:5] /
Kojto	90:cb3d968589d8	741	} B;
Kojto	90:cb3d968589d8	742	} hw_rtc_sr_t;
Kojto	90:cb3d968589d8	743
Kojto	90:cb3d968589d8	744	/*!
Kojto	90:cb3d968589d8	745	* @name Constants and macros for entire RTC_SR register
Kojto	90:cb3d968589d8	746	*/
Kojto	90:cb3d968589d8	747	/@{/
Kojto	90:cb3d968589d8	748	#define HW_RTC_SR_ADDR(x) ((x) + 0x14U)
Kojto	90:cb3d968589d8	749
Kojto	90:cb3d968589d8	750	#define HW_RTC_SR(x) ((__IO hw_rtc_sr_t ) HW_RTC_SR_ADDR(x))
Kojto	90:cb3d968589d8	751	#define HW_RTC_SR_RD(x) (HW_RTC_SR(x).U)
Kojto	90:cb3d968589d8	752	#define HW_RTC_SR_WR(x, v) (HW_RTC_SR(x).U = (v))
Kojto	90:cb3d968589d8	753	#define HW_RTC_SR_SET(x, v) (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	754	#define HW_RTC_SR_CLR(x, v) (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	755	#define HW_RTC_SR_TOG(x, v) (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	756	/@}/
Kojto	90:cb3d968589d8	757
Kojto	90:cb3d968589d8	758	/*
Kojto	90:cb3d968589d8	759	* Constants & macros for individual RTC_SR bitfields
Kojto	90:cb3d968589d8	760	*/
Kojto	90:cb3d968589d8	761
Kojto	90:cb3d968589d8	762	/*!
Kojto	90:cb3d968589d8	763	* @name Register RTC_SR, field TIF[0] (RO)
Kojto	90:cb3d968589d8	764	*
Kojto	90:cb3d968589d8	765	* The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
Kojto	90:cb3d968589d8	766	* do not increment and read as zero when this bit is set. This bit is cleared by
Kojto	90:cb3d968589d8	767	* writing the TSR register when the time counter is disabled.
Kojto	90:cb3d968589d8	768	*
Kojto	90:cb3d968589d8	769	* Values:
Kojto	90:cb3d968589d8	770	* - 0 - Time is valid.
Kojto	90:cb3d968589d8	771	* - 1 - Time is invalid and time counter is read as zero.
Kojto	90:cb3d968589d8	772	*/
Kojto	90:cb3d968589d8	773	/@{/
Kojto	90:cb3d968589d8	774	#define BP_RTC_SR_TIF (0U) /!< Bit position for RTC_SR_TIF. /
Kojto	90:cb3d968589d8	775	#define BM_RTC_SR_TIF (0x00000001U) /!< Bit mask for RTC_SR_TIF. /
Kojto	90:cb3d968589d8	776	#define BS_RTC_SR_TIF (1U) /!< Bit field size in bits for RTC_SR_TIF. /
Kojto	90:cb3d968589d8	777
Kojto	90:cb3d968589d8	778	/! @brief Read current value of the RTC_SR_TIF field. /
Kojto	90:cb3d968589d8	779	#define BR_RTC_SR_TIF(x) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TIF))
Kojto	90:cb3d968589d8	780	/@}/
Kojto	90:cb3d968589d8	781
Kojto	90:cb3d968589d8	782	/*!
Kojto	90:cb3d968589d8	783	* @name Register RTC_SR, field TOF[1] (RO)
Kojto	90:cb3d968589d8	784	*
Kojto	90:cb3d968589d8	785	* Time overflow flag is set when the time counter is enabled and overflows. The
Kojto	90:cb3d968589d8	786	* TSR and TPR do not increment and read as zero when this bit is set. This bit
Kojto	90:cb3d968589d8	787	* is cleared by writing the TSR register when the time counter is disabled.
Kojto	90:cb3d968589d8	788	*
Kojto	90:cb3d968589d8	789	* Values:
Kojto	90:cb3d968589d8	790	* - 0 - Time overflow has not occurred.
Kojto	90:cb3d968589d8	791	* - 1 - Time overflow has occurred and time counter is read as zero.
Kojto	90:cb3d968589d8	792	*/
Kojto	90:cb3d968589d8	793	/@{/
Kojto	90:cb3d968589d8	794	#define BP_RTC_SR_TOF (1U) /!< Bit position for RTC_SR_TOF. /
Kojto	90:cb3d968589d8	795	#define BM_RTC_SR_TOF (0x00000002U) /!< Bit mask for RTC_SR_TOF. /
Kojto	90:cb3d968589d8	796	#define BS_RTC_SR_TOF (1U) /!< Bit field size in bits for RTC_SR_TOF. /
Kojto	90:cb3d968589d8	797
Kojto	90:cb3d968589d8	798	/! @brief Read current value of the RTC_SR_TOF field. /
Kojto	90:cb3d968589d8	799	#define BR_RTC_SR_TOF(x) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TOF))
Kojto	90:cb3d968589d8	800	/@}/
Kojto	90:cb3d968589d8	801
Kojto	90:cb3d968589d8	802	/*!
Kojto	90:cb3d968589d8	803	* @name Register RTC_SR, field TAF[2] (RO)
Kojto	90:cb3d968589d8	804	*
Kojto	90:cb3d968589d8	805	* Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
Kojto	90:cb3d968589d8	806	* increments. This bit is cleared by writing the TAR register.
Kojto	90:cb3d968589d8	807	*
Kojto	90:cb3d968589d8	808	* Values:
Kojto	90:cb3d968589d8	809	* - 0 - Time alarm has not occurred.
Kojto	90:cb3d968589d8	810	* - 1 - Time alarm has occurred.
Kojto	90:cb3d968589d8	811	*/
Kojto	90:cb3d968589d8	812	/@{/
Kojto	90:cb3d968589d8	813	#define BP_RTC_SR_TAF (2U) /!< Bit position for RTC_SR_TAF. /
Kojto	90:cb3d968589d8	814	#define BM_RTC_SR_TAF (0x00000004U) /!< Bit mask for RTC_SR_TAF. /
Kojto	90:cb3d968589d8	815	#define BS_RTC_SR_TAF (1U) /!< Bit field size in bits for RTC_SR_TAF. /
Kojto	90:cb3d968589d8	816
Kojto	90:cb3d968589d8	817	/! @brief Read current value of the RTC_SR_TAF field. /
Kojto	90:cb3d968589d8	818	#define BR_RTC_SR_TAF(x) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TAF))
Kojto	90:cb3d968589d8	819	/@}/
Kojto	90:cb3d968589d8	820
Kojto	90:cb3d968589d8	821	/*!
Kojto	90:cb3d968589d8	822	* @name Register RTC_SR, field TCE[4] (RW)
Kojto	90:cb3d968589d8	823	*
Kojto	90:cb3d968589d8	824	* When time counter is disabled the TSR register and TPR register are
Kojto	90:cb3d968589d8	825	* writeable, but do not increment. When time counter is enabled the TSR register and TPR
Kojto	90:cb3d968589d8	826	* register are not writeable, but increment.
Kojto	90:cb3d968589d8	827	*
Kojto	90:cb3d968589d8	828	* Values:
Kojto	90:cb3d968589d8	829	* - 0 - Time counter is disabled.
Kojto	90:cb3d968589d8	830	* - 1 - Time counter is enabled.
Kojto	90:cb3d968589d8	831	*/
Kojto	90:cb3d968589d8	832	/@{/
Kojto	90:cb3d968589d8	833	#define BP_RTC_SR_TCE (4U) /!< Bit position for RTC_SR_TCE. /
Kojto	90:cb3d968589d8	834	#define BM_RTC_SR_TCE (0x00000010U) /!< Bit mask for RTC_SR_TCE. /
Kojto	90:cb3d968589d8	835	#define BS_RTC_SR_TCE (1U) /!< Bit field size in bits for RTC_SR_TCE. /
Kojto	90:cb3d968589d8	836
Kojto	90:cb3d968589d8	837	/! @brief Read current value of the RTC_SR_TCE field. /
Kojto	90:cb3d968589d8	838	#define BR_RTC_SR_TCE(x) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TCE))
Kojto	90:cb3d968589d8	839
Kojto	90:cb3d968589d8	840	/! @brief Format value for bitfield RTC_SR_TCE. /
Kojto	90:cb3d968589d8	841	#define BF_RTC_SR_TCE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_SR_TCE) & BM_RTC_SR_TCE)
Kojto	90:cb3d968589d8	842
Kojto	90:cb3d968589d8	843	/! @brief Set the TCE field to a new value. /
Kojto	90:cb3d968589d8	844	#define BW_RTC_SR_TCE(x, v) (BITBAND_ACCESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TCE) = (v))
Kojto	90:cb3d968589d8	845	/@}/
Kojto	90:cb3d968589d8	846
Kojto	90:cb3d968589d8	847	/*******************************************************************************
Kojto	90:cb3d968589d8	848	* HW_RTC_LR - RTC Lock Register
Kojto	90:cb3d968589d8	849	******************************************************************************/
Kojto	90:cb3d968589d8	850
Kojto	90:cb3d968589d8	851	/*!
Kojto	90:cb3d968589d8	852	* @brief HW_RTC_LR - RTC Lock Register (RW)
Kojto	90:cb3d968589d8	853	*
Kojto	90:cb3d968589d8	854	* Reset value: 0x000000FFU
Kojto	90:cb3d968589d8	855	*/
Kojto	90:cb3d968589d8	856	typedef union _hw_rtc_lr
Kojto	90:cb3d968589d8	857	{
Kojto	90:cb3d968589d8	858	uint32_t U;
Kojto	90:cb3d968589d8	859	struct _hw_rtc_lr_bitfields
Kojto	90:cb3d968589d8	860	{
Kojto	90:cb3d968589d8	861	uint32_t RESERVED0 : 3; /!< [2:0] /
Kojto	90:cb3d968589d8	862	uint32_t TCL : 1; /!< [3] Time Compensation Lock /
Kojto	90:cb3d968589d8	863	uint32_t CRL : 1; /!< [4] Control Register Lock /
Kojto	90:cb3d968589d8	864	uint32_t SRL : 1; /!< [5] Status Register Lock /
Kojto	90:cb3d968589d8	865	uint32_t LRL : 1; /!< [6] Lock Register Lock /
Kojto	90:cb3d968589d8	866	uint32_t RESERVED1 : 25; /!< [31:7] /
Kojto	90:cb3d968589d8	867	} B;
Kojto	90:cb3d968589d8	868	} hw_rtc_lr_t;
Kojto	90:cb3d968589d8	869
Kojto	90:cb3d968589d8	870	/*!
Kojto	90:cb3d968589d8	871	* @name Constants and macros for entire RTC_LR register
Kojto	90:cb3d968589d8	872	*/
Kojto	90:cb3d968589d8	873	/@{/
Kojto	90:cb3d968589d8	874	#define HW_RTC_LR_ADDR(x) ((x) + 0x18U)
Kojto	90:cb3d968589d8	875
Kojto	90:cb3d968589d8	876	#define HW_RTC_LR(x) ((__IO hw_rtc_lr_t ) HW_RTC_LR_ADDR(x))
Kojto	90:cb3d968589d8	877	#define HW_RTC_LR_RD(x) (HW_RTC_LR(x).U)
Kojto	90:cb3d968589d8	878	#define HW_RTC_LR_WR(x, v) (HW_RTC_LR(x).U = (v))
Kojto	90:cb3d968589d8	879	#define HW_RTC_LR_SET(x, v) (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	880	#define HW_RTC_LR_CLR(x, v) (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	881	#define HW_RTC_LR_TOG(x, v) (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	882	/@}/
Kojto	90:cb3d968589d8	883
Kojto	90:cb3d968589d8	884	/*
Kojto	90:cb3d968589d8	885	* Constants & macros for individual RTC_LR bitfields
Kojto	90:cb3d968589d8	886	*/
Kojto	90:cb3d968589d8	887
Kojto	90:cb3d968589d8	888	/*!
Kojto	90:cb3d968589d8	889	* @name Register RTC_LR, field TCL[3] (RW)
Kojto	90:cb3d968589d8	890	*
Kojto	90:cb3d968589d8	891	* After being cleared, this bit can be set only by VBAT POR or software reset.
Kojto	90:cb3d968589d8	892	*
Kojto	90:cb3d968589d8	893	* Values:
Kojto	90:cb3d968589d8	894	* - 0 - Time Compensation Register is locked and writes are ignored.
Kojto	90:cb3d968589d8	895	* - 1 - Time Compensation Register is not locked and writes complete as normal.
Kojto	90:cb3d968589d8	896	*/
Kojto	90:cb3d968589d8	897	/@{/
Kojto	90:cb3d968589d8	898	#define BP_RTC_LR_TCL (3U) /!< Bit position for RTC_LR_TCL. /
Kojto	90:cb3d968589d8	899	#define BM_RTC_LR_TCL (0x00000008U) /!< Bit mask for RTC_LR_TCL. /
Kojto	90:cb3d968589d8	900	#define BS_RTC_LR_TCL (1U) /!< Bit field size in bits for RTC_LR_TCL. /
Kojto	90:cb3d968589d8	901
Kojto	90:cb3d968589d8	902	/! @brief Read current value of the RTC_LR_TCL field. /
Kojto	90:cb3d968589d8	903	#define BR_RTC_LR_TCL(x) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_TCL))
Kojto	90:cb3d968589d8	904
Kojto	90:cb3d968589d8	905	/! @brief Format value for bitfield RTC_LR_TCL. /
Kojto	90:cb3d968589d8	906	#define BF_RTC_LR_TCL(v) ((uint32_t)((uint32_t)(v) << BP_RTC_LR_TCL) & BM_RTC_LR_TCL)
Kojto	90:cb3d968589d8	907
Kojto	90:cb3d968589d8	908	/! @brief Set the TCL field to a new value. /
Kojto	90:cb3d968589d8	909	#define BW_RTC_LR_TCL(x, v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_TCL) = (v))
Kojto	90:cb3d968589d8	910	/@}/
Kojto	90:cb3d968589d8	911
Kojto	90:cb3d968589d8	912	/*!
Kojto	90:cb3d968589d8	913	* @name Register RTC_LR, field CRL[4] (RW)
Kojto	90:cb3d968589d8	914	*
Kojto	90:cb3d968589d8	915	* After being cleared, this bit can only be set by VBAT POR.
Kojto	90:cb3d968589d8	916	*
Kojto	90:cb3d968589d8	917	* Values:
Kojto	90:cb3d968589d8	918	* - 0 - Control Register is locked and writes are ignored.
Kojto	90:cb3d968589d8	919	* - 1 - Control Register is not locked and writes complete as normal.
Kojto	90:cb3d968589d8	920	*/
Kojto	90:cb3d968589d8	921	/@{/
Kojto	90:cb3d968589d8	922	#define BP_RTC_LR_CRL (4U) /!< Bit position for RTC_LR_CRL. /
Kojto	90:cb3d968589d8	923	#define BM_RTC_LR_CRL (0x00000010U) /!< Bit mask for RTC_LR_CRL. /
Kojto	90:cb3d968589d8	924	#define BS_RTC_LR_CRL (1U) /!< Bit field size in bits for RTC_LR_CRL. /
Kojto	90:cb3d968589d8	925
Kojto	90:cb3d968589d8	926	/! @brief Read current value of the RTC_LR_CRL field. /
Kojto	90:cb3d968589d8	927	#define BR_RTC_LR_CRL(x) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_CRL))
Kojto	90:cb3d968589d8	928
Kojto	90:cb3d968589d8	929	/! @brief Format value for bitfield RTC_LR_CRL. /
Kojto	90:cb3d968589d8	930	#define BF_RTC_LR_CRL(v) ((uint32_t)((uint32_t)(v) << BP_RTC_LR_CRL) & BM_RTC_LR_CRL)
Kojto	90:cb3d968589d8	931
Kojto	90:cb3d968589d8	932	/! @brief Set the CRL field to a new value. /
Kojto	90:cb3d968589d8	933	#define BW_RTC_LR_CRL(x, v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_CRL) = (v))
Kojto	90:cb3d968589d8	934	/@}/
Kojto	90:cb3d968589d8	935
Kojto	90:cb3d968589d8	936	/*!
Kojto	90:cb3d968589d8	937	* @name Register RTC_LR, field SRL[5] (RW)
Kojto	90:cb3d968589d8	938	*
Kojto	90:cb3d968589d8	939	* After being cleared, this bit can be set only by VBAT POR or software reset.
Kojto	90:cb3d968589d8	940	*
Kojto	90:cb3d968589d8	941	* Values:
Kojto	90:cb3d968589d8	942	* - 0 - Status Register is locked and writes are ignored.
Kojto	90:cb3d968589d8	943	* - 1 - Status Register is not locked and writes complete as normal.
Kojto	90:cb3d968589d8	944	*/
Kojto	90:cb3d968589d8	945	/@{/
Kojto	90:cb3d968589d8	946	#define BP_RTC_LR_SRL (5U) /!< Bit position for RTC_LR_SRL. /
Kojto	90:cb3d968589d8	947	#define BM_RTC_LR_SRL (0x00000020U) /!< Bit mask for RTC_LR_SRL. /
Kojto	90:cb3d968589d8	948	#define BS_RTC_LR_SRL (1U) /!< Bit field size in bits for RTC_LR_SRL. /
Kojto	90:cb3d968589d8	949
Kojto	90:cb3d968589d8	950	/! @brief Read current value of the RTC_LR_SRL field. /
Kojto	90:cb3d968589d8	951	#define BR_RTC_LR_SRL(x) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_SRL))
Kojto	90:cb3d968589d8	952
Kojto	90:cb3d968589d8	953	/! @brief Format value for bitfield RTC_LR_SRL. /
Kojto	90:cb3d968589d8	954	#define BF_RTC_LR_SRL(v) ((uint32_t)((uint32_t)(v) << BP_RTC_LR_SRL) & BM_RTC_LR_SRL)
Kojto	90:cb3d968589d8	955
Kojto	90:cb3d968589d8	956	/! @brief Set the SRL field to a new value. /
Kojto	90:cb3d968589d8	957	#define BW_RTC_LR_SRL(x, v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_SRL) = (v))
Kojto	90:cb3d968589d8	958	/@}/
Kojto	90:cb3d968589d8	959
Kojto	90:cb3d968589d8	960	/*!
Kojto	90:cb3d968589d8	961	* @name Register RTC_LR, field LRL[6] (RW)
Kojto	90:cb3d968589d8	962	*
Kojto	90:cb3d968589d8	963	* After being cleared, this bit can be set only by VBAT POR or software reset.
Kojto	90:cb3d968589d8	964	*
Kojto	90:cb3d968589d8	965	* Values:
Kojto	90:cb3d968589d8	966	* - 0 - Lock Register is locked and writes are ignored.
Kojto	90:cb3d968589d8	967	* - 1 - Lock Register is not locked and writes complete as normal.
Kojto	90:cb3d968589d8	968	*/
Kojto	90:cb3d968589d8	969	/@{/
Kojto	90:cb3d968589d8	970	#define BP_RTC_LR_LRL (6U) /!< Bit position for RTC_LR_LRL. /
Kojto	90:cb3d968589d8	971	#define BM_RTC_LR_LRL (0x00000040U) /!< Bit mask for RTC_LR_LRL. /
Kojto	90:cb3d968589d8	972	#define BS_RTC_LR_LRL (1U) /!< Bit field size in bits for RTC_LR_LRL. /
Kojto	90:cb3d968589d8	973
Kojto	90:cb3d968589d8	974	/! @brief Read current value of the RTC_LR_LRL field. /
Kojto	90:cb3d968589d8	975	#define BR_RTC_LR_LRL(x) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_LRL))
Kojto	90:cb3d968589d8	976
Kojto	90:cb3d968589d8	977	/! @brief Format value for bitfield RTC_LR_LRL. /
Kojto	90:cb3d968589d8	978	#define BF_RTC_LR_LRL(v) ((uint32_t)((uint32_t)(v) << BP_RTC_LR_LRL) & BM_RTC_LR_LRL)
Kojto	90:cb3d968589d8	979
Kojto	90:cb3d968589d8	980	/! @brief Set the LRL field to a new value. /
Kojto	90:cb3d968589d8	981	#define BW_RTC_LR_LRL(x, v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_LRL) = (v))
Kojto	90:cb3d968589d8	982	/@}/
Kojto	90:cb3d968589d8	983
Kojto	90:cb3d968589d8	984	/*******************************************************************************
Kojto	90:cb3d968589d8	985	* HW_RTC_IER - RTC Interrupt Enable Register
Kojto	90:cb3d968589d8	986	******************************************************************************/
Kojto	90:cb3d968589d8	987
Kojto	90:cb3d968589d8	988	/*!
Kojto	90:cb3d968589d8	989	* @brief HW_RTC_IER - RTC Interrupt Enable Register (RW)
Kojto	90:cb3d968589d8	990	*
Kojto	90:cb3d968589d8	991	* Reset value: 0x00000007U
Kojto	90:cb3d968589d8	992	*/
Kojto	90:cb3d968589d8	993	typedef union _hw_rtc_ier
Kojto	90:cb3d968589d8	994	{
Kojto	90:cb3d968589d8	995	uint32_t U;
Kojto	90:cb3d968589d8	996	struct _hw_rtc_ier_bitfields
Kojto	90:cb3d968589d8	997	{
Kojto	90:cb3d968589d8	998	uint32_t TIIE : 1; /!< [0] Time Invalid Interrupt Enable /
Kojto	90:cb3d968589d8	999	uint32_t TOIE : 1; /!< [1] Time Overflow Interrupt Enable /
Kojto	90:cb3d968589d8	1000	uint32_t TAIE : 1; /!< [2] Time Alarm Interrupt Enable /
Kojto	90:cb3d968589d8	1001	uint32_t RESERVED0 : 1; /!< [3] /
Kojto	90:cb3d968589d8	1002	uint32_t TSIE : 1; /!< [4] Time Seconds Interrupt Enable /
Kojto	90:cb3d968589d8	1003	uint32_t RESERVED1 : 2; /!< [6:5] /
Kojto	90:cb3d968589d8	1004	uint32_t WPON : 1; /!< [7] Wakeup Pin On /
Kojto	90:cb3d968589d8	1005	uint32_t RESERVED2 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	1006	} B;
Kojto	90:cb3d968589d8	1007	} hw_rtc_ier_t;
Kojto	90:cb3d968589d8	1008
Kojto	90:cb3d968589d8	1009	/*!
Kojto	90:cb3d968589d8	1010	* @name Constants and macros for entire RTC_IER register
Kojto	90:cb3d968589d8	1011	*/
Kojto	90:cb3d968589d8	1012	/@{/
Kojto	90:cb3d968589d8	1013	#define HW_RTC_IER_ADDR(x) ((x) + 0x1CU)
Kojto	90:cb3d968589d8	1014
Kojto	90:cb3d968589d8	1015	#define HW_RTC_IER(x) ((__IO hw_rtc_ier_t ) HW_RTC_IER_ADDR(x))
Kojto	90:cb3d968589d8	1016	#define HW_RTC_IER_RD(x) (HW_RTC_IER(x).U)
Kojto	90:cb3d968589d8	1017	#define HW_RTC_IER_WR(x, v) (HW_RTC_IER(x).U = (v))
Kojto	90:cb3d968589d8	1018	#define HW_RTC_IER_SET(x, v) (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1019	#define HW_RTC_IER_CLR(x, v) (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1020	#define HW_RTC_IER_TOG(x, v) (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1021	/@}/
Kojto	90:cb3d968589d8	1022
Kojto	90:cb3d968589d8	1023	/*
Kojto	90:cb3d968589d8	1024	* Constants & macros for individual RTC_IER bitfields
Kojto	90:cb3d968589d8	1025	*/
Kojto	90:cb3d968589d8	1026
Kojto	90:cb3d968589d8	1027	/*!
Kojto	90:cb3d968589d8	1028	* @name Register RTC_IER, field TIIE[0] (RW)
Kojto	90:cb3d968589d8	1029	*
Kojto	90:cb3d968589d8	1030	* Values:
Kojto	90:cb3d968589d8	1031	* - 0 - Time invalid flag does not generate an interrupt.
Kojto	90:cb3d968589d8	1032	* - 1 - Time invalid flag does generate an interrupt.
Kojto	90:cb3d968589d8	1033	*/
Kojto	90:cb3d968589d8	1034	/@{/
Kojto	90:cb3d968589d8	1035	#define BP_RTC_IER_TIIE (0U) /!< Bit position for RTC_IER_TIIE. /
Kojto	90:cb3d968589d8	1036	#define BM_RTC_IER_TIIE (0x00000001U) /!< Bit mask for RTC_IER_TIIE. /
Kojto	90:cb3d968589d8	1037	#define BS_RTC_IER_TIIE (1U) /!< Bit field size in bits for RTC_IER_TIIE. /
Kojto	90:cb3d968589d8	1038
Kojto	90:cb3d968589d8	1039	/! @brief Read current value of the RTC_IER_TIIE field. /
Kojto	90:cb3d968589d8	1040	#define BR_RTC_IER_TIIE(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TIIE))
Kojto	90:cb3d968589d8	1041
Kojto	90:cb3d968589d8	1042	/! @brief Format value for bitfield RTC_IER_TIIE. /
Kojto	90:cb3d968589d8	1043	#define BF_RTC_IER_TIIE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TIIE) & BM_RTC_IER_TIIE)
Kojto	90:cb3d968589d8	1044
Kojto	90:cb3d968589d8	1045	/! @brief Set the TIIE field to a new value. /
Kojto	90:cb3d968589d8	1046	#define BW_RTC_IER_TIIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TIIE) = (v))
Kojto	90:cb3d968589d8	1047	/@}/
Kojto	90:cb3d968589d8	1048
Kojto	90:cb3d968589d8	1049	/*!
Kojto	90:cb3d968589d8	1050	* @name Register RTC_IER, field TOIE[1] (RW)
Kojto	90:cb3d968589d8	1051	*
Kojto	90:cb3d968589d8	1052	* Values:
Kojto	90:cb3d968589d8	1053	* - 0 - Time overflow flag does not generate an interrupt.
Kojto	90:cb3d968589d8	1054	* - 1 - Time overflow flag does generate an interrupt.
Kojto	90:cb3d968589d8	1055	*/
Kojto	90:cb3d968589d8	1056	/@{/
Kojto	90:cb3d968589d8	1057	#define BP_RTC_IER_TOIE (1U) /!< Bit position for RTC_IER_TOIE. /
Kojto	90:cb3d968589d8	1058	#define BM_RTC_IER_TOIE (0x00000002U) /!< Bit mask for RTC_IER_TOIE. /
Kojto	90:cb3d968589d8	1059	#define BS_RTC_IER_TOIE (1U) /!< Bit field size in bits for RTC_IER_TOIE. /
Kojto	90:cb3d968589d8	1060
Kojto	90:cb3d968589d8	1061	/! @brief Read current value of the RTC_IER_TOIE field. /
Kojto	90:cb3d968589d8	1062	#define BR_RTC_IER_TOIE(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TOIE))
Kojto	90:cb3d968589d8	1063
Kojto	90:cb3d968589d8	1064	/! @brief Format value for bitfield RTC_IER_TOIE. /
Kojto	90:cb3d968589d8	1065	#define BF_RTC_IER_TOIE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TOIE) & BM_RTC_IER_TOIE)
Kojto	90:cb3d968589d8	1066
Kojto	90:cb3d968589d8	1067	/! @brief Set the TOIE field to a new value. /
Kojto	90:cb3d968589d8	1068	#define BW_RTC_IER_TOIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TOIE) = (v))
Kojto	90:cb3d968589d8	1069	/@}/
Kojto	90:cb3d968589d8	1070
Kojto	90:cb3d968589d8	1071	/*!
Kojto	90:cb3d968589d8	1072	* @name Register RTC_IER, field TAIE[2] (RW)
Kojto	90:cb3d968589d8	1073	*
Kojto	90:cb3d968589d8	1074	* Values:
Kojto	90:cb3d968589d8	1075	* - 0 - Time alarm flag does not generate an interrupt.
Kojto	90:cb3d968589d8	1076	* - 1 - Time alarm flag does generate an interrupt.
Kojto	90:cb3d968589d8	1077	*/
Kojto	90:cb3d968589d8	1078	/@{/
Kojto	90:cb3d968589d8	1079	#define BP_RTC_IER_TAIE (2U) /!< Bit position for RTC_IER_TAIE. /
Kojto	90:cb3d968589d8	1080	#define BM_RTC_IER_TAIE (0x00000004U) /!< Bit mask for RTC_IER_TAIE. /
Kojto	90:cb3d968589d8	1081	#define BS_RTC_IER_TAIE (1U) /!< Bit field size in bits for RTC_IER_TAIE. /
Kojto	90:cb3d968589d8	1082
Kojto	90:cb3d968589d8	1083	/! @brief Read current value of the RTC_IER_TAIE field. /
Kojto	90:cb3d968589d8	1084	#define BR_RTC_IER_TAIE(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TAIE))
Kojto	90:cb3d968589d8	1085
Kojto	90:cb3d968589d8	1086	/! @brief Format value for bitfield RTC_IER_TAIE. /
Kojto	90:cb3d968589d8	1087	#define BF_RTC_IER_TAIE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TAIE) & BM_RTC_IER_TAIE)
Kojto	90:cb3d968589d8	1088
Kojto	90:cb3d968589d8	1089	/! @brief Set the TAIE field to a new value. /
Kojto	90:cb3d968589d8	1090	#define BW_RTC_IER_TAIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TAIE) = (v))
Kojto	90:cb3d968589d8	1091	/@}/
Kojto	90:cb3d968589d8	1092
Kojto	90:cb3d968589d8	1093	/*!
Kojto	90:cb3d968589d8	1094	* @name Register RTC_IER, field TSIE[4] (RW)
Kojto	90:cb3d968589d8	1095	*
Kojto	90:cb3d968589d8	1096	* The seconds interrupt is an edge-sensitive interrupt with a dedicated
Kojto	90:cb3d968589d8	1097	* interrupt vector. It is generated once a second and requires no software overhead
Kojto	90:cb3d968589d8	1098	* (there is no corresponding status flag to clear).
Kojto	90:cb3d968589d8	1099	*
Kojto	90:cb3d968589d8	1100	* Values:
Kojto	90:cb3d968589d8	1101	* - 0 - Seconds interrupt is disabled.
Kojto	90:cb3d968589d8	1102	* - 1 - Seconds interrupt is enabled.
Kojto	90:cb3d968589d8	1103	*/
Kojto	90:cb3d968589d8	1104	/@{/
Kojto	90:cb3d968589d8	1105	#define BP_RTC_IER_TSIE (4U) /!< Bit position for RTC_IER_TSIE. /
Kojto	90:cb3d968589d8	1106	#define BM_RTC_IER_TSIE (0x00000010U) /!< Bit mask for RTC_IER_TSIE. /
Kojto	90:cb3d968589d8	1107	#define BS_RTC_IER_TSIE (1U) /!< Bit field size in bits for RTC_IER_TSIE. /
Kojto	90:cb3d968589d8	1108
Kojto	90:cb3d968589d8	1109	/! @brief Read current value of the RTC_IER_TSIE field. /
Kojto	90:cb3d968589d8	1110	#define BR_RTC_IER_TSIE(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TSIE))
Kojto	90:cb3d968589d8	1111
Kojto	90:cb3d968589d8	1112	/! @brief Format value for bitfield RTC_IER_TSIE. /
Kojto	90:cb3d968589d8	1113	#define BF_RTC_IER_TSIE(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TSIE) & BM_RTC_IER_TSIE)
Kojto	90:cb3d968589d8	1114
Kojto	90:cb3d968589d8	1115	/! @brief Set the TSIE field to a new value. /
Kojto	90:cb3d968589d8	1116	#define BW_RTC_IER_TSIE(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TSIE) = (v))
Kojto	90:cb3d968589d8	1117	/@}/
Kojto	90:cb3d968589d8	1118
Kojto	90:cb3d968589d8	1119	/*!
Kojto	90:cb3d968589d8	1120	* @name Register RTC_IER, field WPON[7] (RW)
Kojto	90:cb3d968589d8	1121	*
Kojto	90:cb3d968589d8	1122	* The wakeup pin is optional and not available on all devices. Whenever the
Kojto	90:cb3d968589d8	1123	* wakeup pin is enabled and this bit is set, the wakeup pin will assert.
Kojto	90:cb3d968589d8	1124	*
Kojto	90:cb3d968589d8	1125	* Values:
Kojto	90:cb3d968589d8	1126	* - 0 - No effect.
Kojto	90:cb3d968589d8	1127	* - 1 - If the wakeup pin is enabled, then the wakeup pin will assert.
Kojto	90:cb3d968589d8	1128	*/
Kojto	90:cb3d968589d8	1129	/@{/
Kojto	90:cb3d968589d8	1130	#define BP_RTC_IER_WPON (7U) /!< Bit position for RTC_IER_WPON. /
Kojto	90:cb3d968589d8	1131	#define BM_RTC_IER_WPON (0x00000080U) /!< Bit mask for RTC_IER_WPON. /
Kojto	90:cb3d968589d8	1132	#define BS_RTC_IER_WPON (1U) /!< Bit field size in bits for RTC_IER_WPON. /
Kojto	90:cb3d968589d8	1133
Kojto	90:cb3d968589d8	1134	/! @brief Read current value of the RTC_IER_WPON field. /
Kojto	90:cb3d968589d8	1135	#define BR_RTC_IER_WPON(x) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_WPON))
Kojto	90:cb3d968589d8	1136
Kojto	90:cb3d968589d8	1137	/! @brief Format value for bitfield RTC_IER_WPON. /
Kojto	90:cb3d968589d8	1138	#define BF_RTC_IER_WPON(v) ((uint32_t)((uint32_t)(v) << BP_RTC_IER_WPON) & BM_RTC_IER_WPON)
Kojto	90:cb3d968589d8	1139
Kojto	90:cb3d968589d8	1140	/! @brief Set the WPON field to a new value. /
Kojto	90:cb3d968589d8	1141	#define BW_RTC_IER_WPON(x, v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_WPON) = (v))
Kojto	90:cb3d968589d8	1142	/@}/
Kojto	90:cb3d968589d8	1143
Kojto	90:cb3d968589d8	1144	/*******************************************************************************
Kojto	90:cb3d968589d8	1145	* HW_RTC_WAR - RTC Write Access Register
Kojto	90:cb3d968589d8	1146	******************************************************************************/
Kojto	90:cb3d968589d8	1147
Kojto	90:cb3d968589d8	1148	/*!
Kojto	90:cb3d968589d8	1149	* @brief HW_RTC_WAR - RTC Write Access Register (RW)
Kojto	90:cb3d968589d8	1150	*
Kojto	90:cb3d968589d8	1151	* Reset value: 0x000000FFU
Kojto	90:cb3d968589d8	1152	*/
Kojto	90:cb3d968589d8	1153	typedef union _hw_rtc_war
Kojto	90:cb3d968589d8	1154	{
Kojto	90:cb3d968589d8	1155	uint32_t U;
Kojto	90:cb3d968589d8	1156	struct _hw_rtc_war_bitfields
Kojto	90:cb3d968589d8	1157	{
Kojto	90:cb3d968589d8	1158	uint32_t TSRW : 1; /!< [0] Time Seconds Register Write /
Kojto	90:cb3d968589d8	1159	uint32_t TPRW : 1; /!< [1] Time Prescaler Register Write /
Kojto	90:cb3d968589d8	1160	uint32_t TARW : 1; /!< [2] Time Alarm Register Write /
Kojto	90:cb3d968589d8	1161	uint32_t TCRW : 1; /!< [3] Time Compensation Register Write /
Kojto	90:cb3d968589d8	1162	uint32_t CRW : 1; /!< [4] Control Register Write /
Kojto	90:cb3d968589d8	1163	uint32_t SRW : 1; /!< [5] Status Register Write /
Kojto	90:cb3d968589d8	1164	uint32_t LRW : 1; /!< [6] Lock Register Write /
Kojto	90:cb3d968589d8	1165	uint32_t IERW : 1; /!< [7] Interrupt Enable Register Write /
Kojto	90:cb3d968589d8	1166	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	1167	} B;
Kojto	90:cb3d968589d8	1168	} hw_rtc_war_t;
Kojto	90:cb3d968589d8	1169
Kojto	90:cb3d968589d8	1170	/*!
Kojto	90:cb3d968589d8	1171	* @name Constants and macros for entire RTC_WAR register
Kojto	90:cb3d968589d8	1172	*/
Kojto	90:cb3d968589d8	1173	/@{/
Kojto	90:cb3d968589d8	1174	#define HW_RTC_WAR_ADDR(x) ((x) + 0x800U)
Kojto	90:cb3d968589d8	1175
Kojto	90:cb3d968589d8	1176	#define HW_RTC_WAR(x) ((__IO hw_rtc_war_t ) HW_RTC_WAR_ADDR(x))
Kojto	90:cb3d968589d8	1177	#define HW_RTC_WAR_RD(x) (HW_RTC_WAR(x).U)
Kojto	90:cb3d968589d8	1178	#define HW_RTC_WAR_WR(x, v) (HW_RTC_WAR(x).U = (v))
Kojto	90:cb3d968589d8	1179	#define HW_RTC_WAR_SET(x, v) (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1180	#define HW_RTC_WAR_CLR(x, v) (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1181	#define HW_RTC_WAR_TOG(x, v) (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1182	/@}/
Kojto	90:cb3d968589d8	1183
Kojto	90:cb3d968589d8	1184	/*
Kojto	90:cb3d968589d8	1185	* Constants & macros for individual RTC_WAR bitfields
Kojto	90:cb3d968589d8	1186	*/
Kojto	90:cb3d968589d8	1187
Kojto	90:cb3d968589d8	1188	/*!
Kojto	90:cb3d968589d8	1189	* @name Register RTC_WAR, field TSRW[0] (RW)
Kojto	90:cb3d968589d8	1190	*
Kojto	90:cb3d968589d8	1191	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1192	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1193	*
Kojto	90:cb3d968589d8	1194	* Values:
Kojto	90:cb3d968589d8	1195	* - 0 - Writes to the Time Seconds Register are ignored.
Kojto	90:cb3d968589d8	1196	* - 1 - Writes to the Time Seconds Register complete as normal.
Kojto	90:cb3d968589d8	1197	*/
Kojto	90:cb3d968589d8	1198	/@{/
Kojto	90:cb3d968589d8	1199	#define BP_RTC_WAR_TSRW (0U) /!< Bit position for RTC_WAR_TSRW. /
Kojto	90:cb3d968589d8	1200	#define BM_RTC_WAR_TSRW (0x00000001U) /!< Bit mask for RTC_WAR_TSRW. /
Kojto	90:cb3d968589d8	1201	#define BS_RTC_WAR_TSRW (1U) /!< Bit field size in bits for RTC_WAR_TSRW. /
Kojto	90:cb3d968589d8	1202
Kojto	90:cb3d968589d8	1203	/! @brief Read current value of the RTC_WAR_TSRW field. /
Kojto	90:cb3d968589d8	1204	#define BR_RTC_WAR_TSRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TSRW))
Kojto	90:cb3d968589d8	1205
Kojto	90:cb3d968589d8	1206	/! @brief Format value for bitfield RTC_WAR_TSRW. /
Kojto	90:cb3d968589d8	1207	#define BF_RTC_WAR_TSRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TSRW) & BM_RTC_WAR_TSRW)
Kojto	90:cb3d968589d8	1208
Kojto	90:cb3d968589d8	1209	/! @brief Set the TSRW field to a new value. /
Kojto	90:cb3d968589d8	1210	#define BW_RTC_WAR_TSRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TSRW) = (v))
Kojto	90:cb3d968589d8	1211	/@}/
Kojto	90:cb3d968589d8	1212
Kojto	90:cb3d968589d8	1213	/*!
Kojto	90:cb3d968589d8	1214	* @name Register RTC_WAR, field TPRW[1] (RW)
Kojto	90:cb3d968589d8	1215	*
Kojto	90:cb3d968589d8	1216	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1217	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1218	*
Kojto	90:cb3d968589d8	1219	* Values:
Kojto	90:cb3d968589d8	1220	* - 0 - Writes to the Time Prescaler Register are ignored.
Kojto	90:cb3d968589d8	1221	* - 1 - Writes to the Time Prescaler Register complete as normal.
Kojto	90:cb3d968589d8	1222	*/
Kojto	90:cb3d968589d8	1223	/@{/
Kojto	90:cb3d968589d8	1224	#define BP_RTC_WAR_TPRW (1U) /!< Bit position for RTC_WAR_TPRW. /
Kojto	90:cb3d968589d8	1225	#define BM_RTC_WAR_TPRW (0x00000002U) /!< Bit mask for RTC_WAR_TPRW. /
Kojto	90:cb3d968589d8	1226	#define BS_RTC_WAR_TPRW (1U) /!< Bit field size in bits for RTC_WAR_TPRW. /
Kojto	90:cb3d968589d8	1227
Kojto	90:cb3d968589d8	1228	/! @brief Read current value of the RTC_WAR_TPRW field. /
Kojto	90:cb3d968589d8	1229	#define BR_RTC_WAR_TPRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TPRW))
Kojto	90:cb3d968589d8	1230
Kojto	90:cb3d968589d8	1231	/! @brief Format value for bitfield RTC_WAR_TPRW. /
Kojto	90:cb3d968589d8	1232	#define BF_RTC_WAR_TPRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TPRW) & BM_RTC_WAR_TPRW)
Kojto	90:cb3d968589d8	1233
Kojto	90:cb3d968589d8	1234	/! @brief Set the TPRW field to a new value. /
Kojto	90:cb3d968589d8	1235	#define BW_RTC_WAR_TPRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TPRW) = (v))
Kojto	90:cb3d968589d8	1236	/@}/
Kojto	90:cb3d968589d8	1237
Kojto	90:cb3d968589d8	1238	/*!
Kojto	90:cb3d968589d8	1239	* @name Register RTC_WAR, field TARW[2] (RW)
Kojto	90:cb3d968589d8	1240	*
Kojto	90:cb3d968589d8	1241	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1242	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1243	*
Kojto	90:cb3d968589d8	1244	* Values:
Kojto	90:cb3d968589d8	1245	* - 0 - Writes to the Time Alarm Register are ignored.
Kojto	90:cb3d968589d8	1246	* - 1 - Writes to the Time Alarm Register complete as normal.
Kojto	90:cb3d968589d8	1247	*/
Kojto	90:cb3d968589d8	1248	/@{/
Kojto	90:cb3d968589d8	1249	#define BP_RTC_WAR_TARW (2U) /!< Bit position for RTC_WAR_TARW. /
Kojto	90:cb3d968589d8	1250	#define BM_RTC_WAR_TARW (0x00000004U) /!< Bit mask for RTC_WAR_TARW. /
Kojto	90:cb3d968589d8	1251	#define BS_RTC_WAR_TARW (1U) /!< Bit field size in bits for RTC_WAR_TARW. /
Kojto	90:cb3d968589d8	1252
Kojto	90:cb3d968589d8	1253	/! @brief Read current value of the RTC_WAR_TARW field. /
Kojto	90:cb3d968589d8	1254	#define BR_RTC_WAR_TARW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TARW))
Kojto	90:cb3d968589d8	1255
Kojto	90:cb3d968589d8	1256	/! @brief Format value for bitfield RTC_WAR_TARW. /
Kojto	90:cb3d968589d8	1257	#define BF_RTC_WAR_TARW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TARW) & BM_RTC_WAR_TARW)
Kojto	90:cb3d968589d8	1258
Kojto	90:cb3d968589d8	1259	/! @brief Set the TARW field to a new value. /
Kojto	90:cb3d968589d8	1260	#define BW_RTC_WAR_TARW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TARW) = (v))
Kojto	90:cb3d968589d8	1261	/@}/
Kojto	90:cb3d968589d8	1262
Kojto	90:cb3d968589d8	1263	/*!
Kojto	90:cb3d968589d8	1264	* @name Register RTC_WAR, field TCRW[3] (RW)
Kojto	90:cb3d968589d8	1265	*
Kojto	90:cb3d968589d8	1266	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1267	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1268	*
Kojto	90:cb3d968589d8	1269	* Values:
Kojto	90:cb3d968589d8	1270	* - 0 - Writes to the Time Compensation Register are ignored.
Kojto	90:cb3d968589d8	1271	* - 1 - Writes to the Time Compensation Register complete as normal.
Kojto	90:cb3d968589d8	1272	*/
Kojto	90:cb3d968589d8	1273	/@{/
Kojto	90:cb3d968589d8	1274	#define BP_RTC_WAR_TCRW (3U) /!< Bit position for RTC_WAR_TCRW. /
Kojto	90:cb3d968589d8	1275	#define BM_RTC_WAR_TCRW (0x00000008U) /!< Bit mask for RTC_WAR_TCRW. /
Kojto	90:cb3d968589d8	1276	#define BS_RTC_WAR_TCRW (1U) /!< Bit field size in bits for RTC_WAR_TCRW. /
Kojto	90:cb3d968589d8	1277
Kojto	90:cb3d968589d8	1278	/! @brief Read current value of the RTC_WAR_TCRW field. /
Kojto	90:cb3d968589d8	1279	#define BR_RTC_WAR_TCRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TCRW))
Kojto	90:cb3d968589d8	1280
Kojto	90:cb3d968589d8	1281	/! @brief Format value for bitfield RTC_WAR_TCRW. /
Kojto	90:cb3d968589d8	1282	#define BF_RTC_WAR_TCRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TCRW) & BM_RTC_WAR_TCRW)
Kojto	90:cb3d968589d8	1283
Kojto	90:cb3d968589d8	1284	/! @brief Set the TCRW field to a new value. /
Kojto	90:cb3d968589d8	1285	#define BW_RTC_WAR_TCRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TCRW) = (v))
Kojto	90:cb3d968589d8	1286	/@}/
Kojto	90:cb3d968589d8	1287
Kojto	90:cb3d968589d8	1288	/*!
Kojto	90:cb3d968589d8	1289	* @name Register RTC_WAR, field CRW[4] (RW)
Kojto	90:cb3d968589d8	1290	*
Kojto	90:cb3d968589d8	1291	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1292	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1293	*
Kojto	90:cb3d968589d8	1294	* Values:
Kojto	90:cb3d968589d8	1295	* - 0 - Writes to the Control Register are ignored.
Kojto	90:cb3d968589d8	1296	* - 1 - Writes to the Control Register complete as normal.
Kojto	90:cb3d968589d8	1297	*/
Kojto	90:cb3d968589d8	1298	/@{/
Kojto	90:cb3d968589d8	1299	#define BP_RTC_WAR_CRW (4U) /!< Bit position for RTC_WAR_CRW. /
Kojto	90:cb3d968589d8	1300	#define BM_RTC_WAR_CRW (0x00000010U) /!< Bit mask for RTC_WAR_CRW. /
Kojto	90:cb3d968589d8	1301	#define BS_RTC_WAR_CRW (1U) /!< Bit field size in bits for RTC_WAR_CRW. /
Kojto	90:cb3d968589d8	1302
Kojto	90:cb3d968589d8	1303	/! @brief Read current value of the RTC_WAR_CRW field. /
Kojto	90:cb3d968589d8	1304	#define BR_RTC_WAR_CRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_CRW))
Kojto	90:cb3d968589d8	1305
Kojto	90:cb3d968589d8	1306	/! @brief Format value for bitfield RTC_WAR_CRW. /
Kojto	90:cb3d968589d8	1307	#define BF_RTC_WAR_CRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_CRW) & BM_RTC_WAR_CRW)
Kojto	90:cb3d968589d8	1308
Kojto	90:cb3d968589d8	1309	/! @brief Set the CRW field to a new value. /
Kojto	90:cb3d968589d8	1310	#define BW_RTC_WAR_CRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_CRW) = (v))
Kojto	90:cb3d968589d8	1311	/@}/
Kojto	90:cb3d968589d8	1312
Kojto	90:cb3d968589d8	1313	/*!
Kojto	90:cb3d968589d8	1314	* @name Register RTC_WAR, field SRW[5] (RW)
Kojto	90:cb3d968589d8	1315	*
Kojto	90:cb3d968589d8	1316	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1317	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1318	*
Kojto	90:cb3d968589d8	1319	* Values:
Kojto	90:cb3d968589d8	1320	* - 0 - Writes to the Status Register are ignored.
Kojto	90:cb3d968589d8	1321	* - 1 - Writes to the Status Register complete as normal.
Kojto	90:cb3d968589d8	1322	*/
Kojto	90:cb3d968589d8	1323	/@{/
Kojto	90:cb3d968589d8	1324	#define BP_RTC_WAR_SRW (5U) /!< Bit position for RTC_WAR_SRW. /
Kojto	90:cb3d968589d8	1325	#define BM_RTC_WAR_SRW (0x00000020U) /!< Bit mask for RTC_WAR_SRW. /
Kojto	90:cb3d968589d8	1326	#define BS_RTC_WAR_SRW (1U) /!< Bit field size in bits for RTC_WAR_SRW. /
Kojto	90:cb3d968589d8	1327
Kojto	90:cb3d968589d8	1328	/! @brief Read current value of the RTC_WAR_SRW field. /
Kojto	90:cb3d968589d8	1329	#define BR_RTC_WAR_SRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_SRW))
Kojto	90:cb3d968589d8	1330
Kojto	90:cb3d968589d8	1331	/! @brief Format value for bitfield RTC_WAR_SRW. /
Kojto	90:cb3d968589d8	1332	#define BF_RTC_WAR_SRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_SRW) & BM_RTC_WAR_SRW)
Kojto	90:cb3d968589d8	1333
Kojto	90:cb3d968589d8	1334	/! @brief Set the SRW field to a new value. /
Kojto	90:cb3d968589d8	1335	#define BW_RTC_WAR_SRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_SRW) = (v))
Kojto	90:cb3d968589d8	1336	/@}/
Kojto	90:cb3d968589d8	1337
Kojto	90:cb3d968589d8	1338	/*!
Kojto	90:cb3d968589d8	1339	* @name Register RTC_WAR, field LRW[6] (RW)
Kojto	90:cb3d968589d8	1340	*
Kojto	90:cb3d968589d8	1341	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1342	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1343	*
Kojto	90:cb3d968589d8	1344	* Values:
Kojto	90:cb3d968589d8	1345	* - 0 - Writes to the Lock Register are ignored.
Kojto	90:cb3d968589d8	1346	* - 1 - Writes to the Lock Register complete as normal.
Kojto	90:cb3d968589d8	1347	*/
Kojto	90:cb3d968589d8	1348	/@{/
Kojto	90:cb3d968589d8	1349	#define BP_RTC_WAR_LRW (6U) /!< Bit position for RTC_WAR_LRW. /
Kojto	90:cb3d968589d8	1350	#define BM_RTC_WAR_LRW (0x00000040U) /!< Bit mask for RTC_WAR_LRW. /
Kojto	90:cb3d968589d8	1351	#define BS_RTC_WAR_LRW (1U) /!< Bit field size in bits for RTC_WAR_LRW. /
Kojto	90:cb3d968589d8	1352
Kojto	90:cb3d968589d8	1353	/! @brief Read current value of the RTC_WAR_LRW field. /
Kojto	90:cb3d968589d8	1354	#define BR_RTC_WAR_LRW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_LRW))
Kojto	90:cb3d968589d8	1355
Kojto	90:cb3d968589d8	1356	/! @brief Format value for bitfield RTC_WAR_LRW. /
Kojto	90:cb3d968589d8	1357	#define BF_RTC_WAR_LRW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_LRW) & BM_RTC_WAR_LRW)
Kojto	90:cb3d968589d8	1358
Kojto	90:cb3d968589d8	1359	/! @brief Set the LRW field to a new value. /
Kojto	90:cb3d968589d8	1360	#define BW_RTC_WAR_LRW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_LRW) = (v))
Kojto	90:cb3d968589d8	1361	/@}/
Kojto	90:cb3d968589d8	1362
Kojto	90:cb3d968589d8	1363	/*!
Kojto	90:cb3d968589d8	1364	* @name Register RTC_WAR, field IERW[7] (RW)
Kojto	90:cb3d968589d8	1365	*
Kojto	90:cb3d968589d8	1366	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1367	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1368	*
Kojto	90:cb3d968589d8	1369	* Values:
Kojto	90:cb3d968589d8	1370	* - 0 - Writes to the Interupt Enable Register are ignored.
Kojto	90:cb3d968589d8	1371	* - 1 - Writes to the Interrupt Enable Register complete as normal.
Kojto	90:cb3d968589d8	1372	*/
Kojto	90:cb3d968589d8	1373	/@{/
Kojto	90:cb3d968589d8	1374	#define BP_RTC_WAR_IERW (7U) /!< Bit position for RTC_WAR_IERW. /
Kojto	90:cb3d968589d8	1375	#define BM_RTC_WAR_IERW (0x00000080U) /!< Bit mask for RTC_WAR_IERW. /
Kojto	90:cb3d968589d8	1376	#define BS_RTC_WAR_IERW (1U) /!< Bit field size in bits for RTC_WAR_IERW. /
Kojto	90:cb3d968589d8	1377
Kojto	90:cb3d968589d8	1378	/! @brief Read current value of the RTC_WAR_IERW field. /
Kojto	90:cb3d968589d8	1379	#define BR_RTC_WAR_IERW(x) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_IERW))
Kojto	90:cb3d968589d8	1380
Kojto	90:cb3d968589d8	1381	/! @brief Format value for bitfield RTC_WAR_IERW. /
Kojto	90:cb3d968589d8	1382	#define BF_RTC_WAR_IERW(v) ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_IERW) & BM_RTC_WAR_IERW)
Kojto	90:cb3d968589d8	1383
Kojto	90:cb3d968589d8	1384	/! @brief Set the IERW field to a new value. /
Kojto	90:cb3d968589d8	1385	#define BW_RTC_WAR_IERW(x, v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_IERW) = (v))
Kojto	90:cb3d968589d8	1386	/@}/
Kojto	90:cb3d968589d8	1387
Kojto	90:cb3d968589d8	1388	/*******************************************************************************
Kojto	90:cb3d968589d8	1389	* HW_RTC_RAR - RTC Read Access Register
Kojto	90:cb3d968589d8	1390	******************************************************************************/
Kojto	90:cb3d968589d8	1391
Kojto	90:cb3d968589d8	1392	/*!
Kojto	90:cb3d968589d8	1393	* @brief HW_RTC_RAR - RTC Read Access Register (RW)
Kojto	90:cb3d968589d8	1394	*
Kojto	90:cb3d968589d8	1395	* Reset value: 0x000000FFU
Kojto	90:cb3d968589d8	1396	*/
Kojto	90:cb3d968589d8	1397	typedef union _hw_rtc_rar
Kojto	90:cb3d968589d8	1398	{
Kojto	90:cb3d968589d8	1399	uint32_t U;
Kojto	90:cb3d968589d8	1400	struct _hw_rtc_rar_bitfields
Kojto	90:cb3d968589d8	1401	{
Kojto	90:cb3d968589d8	1402	uint32_t TSRR : 1; /!< [0] Time Seconds Register Read /
Kojto	90:cb3d968589d8	1403	uint32_t TPRR : 1; /!< [1] Time Prescaler Register Read /
Kojto	90:cb3d968589d8	1404	uint32_t TARR : 1; /!< [2] Time Alarm Register Read /
Kojto	90:cb3d968589d8	1405	uint32_t TCRR : 1; /!< [3] Time Compensation Register Read /
Kojto	90:cb3d968589d8	1406	uint32_t CRR : 1; /!< [4] Control Register Read /
Kojto	90:cb3d968589d8	1407	uint32_t SRR : 1; /!< [5] Status Register Read /
Kojto	90:cb3d968589d8	1408	uint32_t LRR : 1; /!< [6] Lock Register Read /
Kojto	90:cb3d968589d8	1409	uint32_t IERR : 1; /!< [7] Interrupt Enable Register Read /
Kojto	90:cb3d968589d8	1410	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	1411	} B;
Kojto	90:cb3d968589d8	1412	} hw_rtc_rar_t;
Kojto	90:cb3d968589d8	1413
Kojto	90:cb3d968589d8	1414	/*!
Kojto	90:cb3d968589d8	1415	* @name Constants and macros for entire RTC_RAR register
Kojto	90:cb3d968589d8	1416	*/
Kojto	90:cb3d968589d8	1417	/@{/
Kojto	90:cb3d968589d8	1418	#define HW_RTC_RAR_ADDR(x) ((x) + 0x804U)
Kojto	90:cb3d968589d8	1419
Kojto	90:cb3d968589d8	1420	#define HW_RTC_RAR(x) ((__IO hw_rtc_rar_t ) HW_RTC_RAR_ADDR(x))
Kojto	90:cb3d968589d8	1421	#define HW_RTC_RAR_RD(x) (HW_RTC_RAR(x).U)
Kojto	90:cb3d968589d8	1422	#define HW_RTC_RAR_WR(x, v) (HW_RTC_RAR(x).U = (v))
Kojto	90:cb3d968589d8	1423	#define HW_RTC_RAR_SET(x, v) (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1424	#define HW_RTC_RAR_CLR(x, v) (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1425	#define HW_RTC_RAR_TOG(x, v) (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1426	/@}/
Kojto	90:cb3d968589d8	1427
Kojto	90:cb3d968589d8	1428	/*
Kojto	90:cb3d968589d8	1429	* Constants & macros for individual RTC_RAR bitfields
Kojto	90:cb3d968589d8	1430	*/
Kojto	90:cb3d968589d8	1431
Kojto	90:cb3d968589d8	1432	/*!
Kojto	90:cb3d968589d8	1433	* @name Register RTC_RAR, field TSRR[0] (RW)
Kojto	90:cb3d968589d8	1434	*
Kojto	90:cb3d968589d8	1435	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1436	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1437	*
Kojto	90:cb3d968589d8	1438	* Values:
Kojto	90:cb3d968589d8	1439	* - 0 - Reads to the Time Seconds Register are ignored.
Kojto	90:cb3d968589d8	1440	* - 1 - Reads to the Time Seconds Register complete as normal.
Kojto	90:cb3d968589d8	1441	*/
Kojto	90:cb3d968589d8	1442	/@{/
Kojto	90:cb3d968589d8	1443	#define BP_RTC_RAR_TSRR (0U) /!< Bit position for RTC_RAR_TSRR. /
Kojto	90:cb3d968589d8	1444	#define BM_RTC_RAR_TSRR (0x00000001U) /!< Bit mask for RTC_RAR_TSRR. /
Kojto	90:cb3d968589d8	1445	#define BS_RTC_RAR_TSRR (1U) /!< Bit field size in bits for RTC_RAR_TSRR. /
Kojto	90:cb3d968589d8	1446
Kojto	90:cb3d968589d8	1447	/! @brief Read current value of the RTC_RAR_TSRR field. /
Kojto	90:cb3d968589d8	1448	#define BR_RTC_RAR_TSRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TSRR))
Kojto	90:cb3d968589d8	1449
Kojto	90:cb3d968589d8	1450	/! @brief Format value for bitfield RTC_RAR_TSRR. /
Kojto	90:cb3d968589d8	1451	#define BF_RTC_RAR_TSRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TSRR) & BM_RTC_RAR_TSRR)
Kojto	90:cb3d968589d8	1452
Kojto	90:cb3d968589d8	1453	/! @brief Set the TSRR field to a new value. /
Kojto	90:cb3d968589d8	1454	#define BW_RTC_RAR_TSRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TSRR) = (v))
Kojto	90:cb3d968589d8	1455	/@}/
Kojto	90:cb3d968589d8	1456
Kojto	90:cb3d968589d8	1457	/*!
Kojto	90:cb3d968589d8	1458	* @name Register RTC_RAR, field TPRR[1] (RW)
Kojto	90:cb3d968589d8	1459	*
Kojto	90:cb3d968589d8	1460	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1461	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1462	*
Kojto	90:cb3d968589d8	1463	* Values:
Kojto	90:cb3d968589d8	1464	* - 0 - Reads to the Time Pprescaler Register are ignored.
Kojto	90:cb3d968589d8	1465	* - 1 - Reads to the Time Prescaler Register complete as normal.
Kojto	90:cb3d968589d8	1466	*/
Kojto	90:cb3d968589d8	1467	/@{/
Kojto	90:cb3d968589d8	1468	#define BP_RTC_RAR_TPRR (1U) /!< Bit position for RTC_RAR_TPRR. /
Kojto	90:cb3d968589d8	1469	#define BM_RTC_RAR_TPRR (0x00000002U) /!< Bit mask for RTC_RAR_TPRR. /
Kojto	90:cb3d968589d8	1470	#define BS_RTC_RAR_TPRR (1U) /!< Bit field size in bits for RTC_RAR_TPRR. /
Kojto	90:cb3d968589d8	1471
Kojto	90:cb3d968589d8	1472	/! @brief Read current value of the RTC_RAR_TPRR field. /
Kojto	90:cb3d968589d8	1473	#define BR_RTC_RAR_TPRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TPRR))
Kojto	90:cb3d968589d8	1474
Kojto	90:cb3d968589d8	1475	/! @brief Format value for bitfield RTC_RAR_TPRR. /
Kojto	90:cb3d968589d8	1476	#define BF_RTC_RAR_TPRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TPRR) & BM_RTC_RAR_TPRR)
Kojto	90:cb3d968589d8	1477
Kojto	90:cb3d968589d8	1478	/! @brief Set the TPRR field to a new value. /
Kojto	90:cb3d968589d8	1479	#define BW_RTC_RAR_TPRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TPRR) = (v))
Kojto	90:cb3d968589d8	1480	/@}/
Kojto	90:cb3d968589d8	1481
Kojto	90:cb3d968589d8	1482	/*!
Kojto	90:cb3d968589d8	1483	* @name Register RTC_RAR, field TARR[2] (RW)
Kojto	90:cb3d968589d8	1484	*
Kojto	90:cb3d968589d8	1485	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1486	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1487	*
Kojto	90:cb3d968589d8	1488	* Values:
Kojto	90:cb3d968589d8	1489	* - 0 - Reads to the Time Alarm Register are ignored.
Kojto	90:cb3d968589d8	1490	* - 1 - Reads to the Time Alarm Register complete as normal.
Kojto	90:cb3d968589d8	1491	*/
Kojto	90:cb3d968589d8	1492	/@{/
Kojto	90:cb3d968589d8	1493	#define BP_RTC_RAR_TARR (2U) /!< Bit position for RTC_RAR_TARR. /
Kojto	90:cb3d968589d8	1494	#define BM_RTC_RAR_TARR (0x00000004U) /!< Bit mask for RTC_RAR_TARR. /
Kojto	90:cb3d968589d8	1495	#define BS_RTC_RAR_TARR (1U) /!< Bit field size in bits for RTC_RAR_TARR. /
Kojto	90:cb3d968589d8	1496
Kojto	90:cb3d968589d8	1497	/! @brief Read current value of the RTC_RAR_TARR field. /
Kojto	90:cb3d968589d8	1498	#define BR_RTC_RAR_TARR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TARR))
Kojto	90:cb3d968589d8	1499
Kojto	90:cb3d968589d8	1500	/! @brief Format value for bitfield RTC_RAR_TARR. /
Kojto	90:cb3d968589d8	1501	#define BF_RTC_RAR_TARR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TARR) & BM_RTC_RAR_TARR)
Kojto	90:cb3d968589d8	1502
Kojto	90:cb3d968589d8	1503	/! @brief Set the TARR field to a new value. /
Kojto	90:cb3d968589d8	1504	#define BW_RTC_RAR_TARR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TARR) = (v))
Kojto	90:cb3d968589d8	1505	/@}/
Kojto	90:cb3d968589d8	1506
Kojto	90:cb3d968589d8	1507	/*!
Kojto	90:cb3d968589d8	1508	* @name Register RTC_RAR, field TCRR[3] (RW)
Kojto	90:cb3d968589d8	1509	*
Kojto	90:cb3d968589d8	1510	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1511	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1512	*
Kojto	90:cb3d968589d8	1513	* Values:
Kojto	90:cb3d968589d8	1514	* - 0 - Reads to the Time Compensation Register are ignored.
Kojto	90:cb3d968589d8	1515	* - 1 - Reads to the Time Compensation Register complete as normal.
Kojto	90:cb3d968589d8	1516	*/
Kojto	90:cb3d968589d8	1517	/@{/
Kojto	90:cb3d968589d8	1518	#define BP_RTC_RAR_TCRR (3U) /!< Bit position for RTC_RAR_TCRR. /
Kojto	90:cb3d968589d8	1519	#define BM_RTC_RAR_TCRR (0x00000008U) /!< Bit mask for RTC_RAR_TCRR. /
Kojto	90:cb3d968589d8	1520	#define BS_RTC_RAR_TCRR (1U) /!< Bit field size in bits for RTC_RAR_TCRR. /
Kojto	90:cb3d968589d8	1521
Kojto	90:cb3d968589d8	1522	/! @brief Read current value of the RTC_RAR_TCRR field. /
Kojto	90:cb3d968589d8	1523	#define BR_RTC_RAR_TCRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TCRR))
Kojto	90:cb3d968589d8	1524
Kojto	90:cb3d968589d8	1525	/! @brief Format value for bitfield RTC_RAR_TCRR. /
Kojto	90:cb3d968589d8	1526	#define BF_RTC_RAR_TCRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TCRR) & BM_RTC_RAR_TCRR)
Kojto	90:cb3d968589d8	1527
Kojto	90:cb3d968589d8	1528	/! @brief Set the TCRR field to a new value. /
Kojto	90:cb3d968589d8	1529	#define BW_RTC_RAR_TCRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TCRR) = (v))
Kojto	90:cb3d968589d8	1530	/@}/
Kojto	90:cb3d968589d8	1531
Kojto	90:cb3d968589d8	1532	/*!
Kojto	90:cb3d968589d8	1533	* @name Register RTC_RAR, field CRR[4] (RW)
Kojto	90:cb3d968589d8	1534	*
Kojto	90:cb3d968589d8	1535	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1536	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1537	*
Kojto	90:cb3d968589d8	1538	* Values:
Kojto	90:cb3d968589d8	1539	* - 0 - Reads to the Control Register are ignored.
Kojto	90:cb3d968589d8	1540	* - 1 - Reads to the Control Register complete as normal.
Kojto	90:cb3d968589d8	1541	*/
Kojto	90:cb3d968589d8	1542	/@{/
Kojto	90:cb3d968589d8	1543	#define BP_RTC_RAR_CRR (4U) /!< Bit position for RTC_RAR_CRR. /
Kojto	90:cb3d968589d8	1544	#define BM_RTC_RAR_CRR (0x00000010U) /!< Bit mask for RTC_RAR_CRR. /
Kojto	90:cb3d968589d8	1545	#define BS_RTC_RAR_CRR (1U) /!< Bit field size in bits for RTC_RAR_CRR. /
Kojto	90:cb3d968589d8	1546
Kojto	90:cb3d968589d8	1547	/! @brief Read current value of the RTC_RAR_CRR field. /
Kojto	90:cb3d968589d8	1548	#define BR_RTC_RAR_CRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_CRR))
Kojto	90:cb3d968589d8	1549
Kojto	90:cb3d968589d8	1550	/! @brief Format value for bitfield RTC_RAR_CRR. /
Kojto	90:cb3d968589d8	1551	#define BF_RTC_RAR_CRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_CRR) & BM_RTC_RAR_CRR)
Kojto	90:cb3d968589d8	1552
Kojto	90:cb3d968589d8	1553	/! @brief Set the CRR field to a new value. /
Kojto	90:cb3d968589d8	1554	#define BW_RTC_RAR_CRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_CRR) = (v))
Kojto	90:cb3d968589d8	1555	/@}/
Kojto	90:cb3d968589d8	1556
Kojto	90:cb3d968589d8	1557	/*!
Kojto	90:cb3d968589d8	1558	* @name Register RTC_RAR, field SRR[5] (RW)
Kojto	90:cb3d968589d8	1559	*
Kojto	90:cb3d968589d8	1560	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1561	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1562	*
Kojto	90:cb3d968589d8	1563	* Values:
Kojto	90:cb3d968589d8	1564	* - 0 - Reads to the Status Register are ignored.
Kojto	90:cb3d968589d8	1565	* - 1 - Reads to the Status Register complete as normal.
Kojto	90:cb3d968589d8	1566	*/
Kojto	90:cb3d968589d8	1567	/@{/
Kojto	90:cb3d968589d8	1568	#define BP_RTC_RAR_SRR (5U) /!< Bit position for RTC_RAR_SRR. /
Kojto	90:cb3d968589d8	1569	#define BM_RTC_RAR_SRR (0x00000020U) /!< Bit mask for RTC_RAR_SRR. /
Kojto	90:cb3d968589d8	1570	#define BS_RTC_RAR_SRR (1U) /!< Bit field size in bits for RTC_RAR_SRR. /
Kojto	90:cb3d968589d8	1571
Kojto	90:cb3d968589d8	1572	/! @brief Read current value of the RTC_RAR_SRR field. /
Kojto	90:cb3d968589d8	1573	#define BR_RTC_RAR_SRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_SRR))
Kojto	90:cb3d968589d8	1574
Kojto	90:cb3d968589d8	1575	/! @brief Format value for bitfield RTC_RAR_SRR. /
Kojto	90:cb3d968589d8	1576	#define BF_RTC_RAR_SRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_SRR) & BM_RTC_RAR_SRR)
Kojto	90:cb3d968589d8	1577
Kojto	90:cb3d968589d8	1578	/! @brief Set the SRR field to a new value. /
Kojto	90:cb3d968589d8	1579	#define BW_RTC_RAR_SRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_SRR) = (v))
Kojto	90:cb3d968589d8	1580	/@}/
Kojto	90:cb3d968589d8	1581
Kojto	90:cb3d968589d8	1582	/*!
Kojto	90:cb3d968589d8	1583	* @name Register RTC_RAR, field LRR[6] (RW)
Kojto	90:cb3d968589d8	1584	*
Kojto	90:cb3d968589d8	1585	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1586	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1587	*
Kojto	90:cb3d968589d8	1588	* Values:
Kojto	90:cb3d968589d8	1589	* - 0 - Reads to the Lock Register are ignored.
Kojto	90:cb3d968589d8	1590	* - 1 - Reads to the Lock Register complete as normal.
Kojto	90:cb3d968589d8	1591	*/
Kojto	90:cb3d968589d8	1592	/@{/
Kojto	90:cb3d968589d8	1593	#define BP_RTC_RAR_LRR (6U) /!< Bit position for RTC_RAR_LRR. /
Kojto	90:cb3d968589d8	1594	#define BM_RTC_RAR_LRR (0x00000040U) /!< Bit mask for RTC_RAR_LRR. /
Kojto	90:cb3d968589d8	1595	#define BS_RTC_RAR_LRR (1U) /!< Bit field size in bits for RTC_RAR_LRR. /
Kojto	90:cb3d968589d8	1596
Kojto	90:cb3d968589d8	1597	/! @brief Read current value of the RTC_RAR_LRR field. /
Kojto	90:cb3d968589d8	1598	#define BR_RTC_RAR_LRR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_LRR))
Kojto	90:cb3d968589d8	1599
Kojto	90:cb3d968589d8	1600	/! @brief Format value for bitfield RTC_RAR_LRR. /
Kojto	90:cb3d968589d8	1601	#define BF_RTC_RAR_LRR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_LRR) & BM_RTC_RAR_LRR)
Kojto	90:cb3d968589d8	1602
Kojto	90:cb3d968589d8	1603	/! @brief Set the LRR field to a new value. /
Kojto	90:cb3d968589d8	1604	#define BW_RTC_RAR_LRR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_LRR) = (v))
Kojto	90:cb3d968589d8	1605	/@}/
Kojto	90:cb3d968589d8	1606
Kojto	90:cb3d968589d8	1607	/*!
Kojto	90:cb3d968589d8	1608	* @name Register RTC_RAR, field IERR[7] (RW)
Kojto	90:cb3d968589d8	1609	*
Kojto	90:cb3d968589d8	1610	* After being cleared, this bit is set only by system reset. It is not affected
Kojto	90:cb3d968589d8	1611	* by VBAT POR or software reset.
Kojto	90:cb3d968589d8	1612	*
Kojto	90:cb3d968589d8	1613	* Values:
Kojto	90:cb3d968589d8	1614	* - 0 - Reads to the Interrupt Enable Register are ignored.
Kojto	90:cb3d968589d8	1615	* - 1 - Reads to the Interrupt Enable Register complete as normal.
Kojto	90:cb3d968589d8	1616	*/
Kojto	90:cb3d968589d8	1617	/@{/
Kojto	90:cb3d968589d8	1618	#define BP_RTC_RAR_IERR (7U) /!< Bit position for RTC_RAR_IERR. /
Kojto	90:cb3d968589d8	1619	#define BM_RTC_RAR_IERR (0x00000080U) /!< Bit mask for RTC_RAR_IERR. /
Kojto	90:cb3d968589d8	1620	#define BS_RTC_RAR_IERR (1U) /!< Bit field size in bits for RTC_RAR_IERR. /
Kojto	90:cb3d968589d8	1621
Kojto	90:cb3d968589d8	1622	/! @brief Read current value of the RTC_RAR_IERR field. /
Kojto	90:cb3d968589d8	1623	#define BR_RTC_RAR_IERR(x) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_IERR))
Kojto	90:cb3d968589d8	1624
Kojto	90:cb3d968589d8	1625	/! @brief Format value for bitfield RTC_RAR_IERR. /
Kojto	90:cb3d968589d8	1626	#define BF_RTC_RAR_IERR(v) ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_IERR) & BM_RTC_RAR_IERR)
Kojto	90:cb3d968589d8	1627
Kojto	90:cb3d968589d8	1628	/! @brief Set the IERR field to a new value. /
Kojto	90:cb3d968589d8	1629	#define BW_RTC_RAR_IERR(x, v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_IERR) = (v))
Kojto	90:cb3d968589d8	1630	/@}/
Kojto	90:cb3d968589d8	1631
Kojto	90:cb3d968589d8	1632	/*******************************************************************************
Kojto	90:cb3d968589d8	1633	* hw_rtc_t - module struct
Kojto	90:cb3d968589d8	1634	******************************************************************************/
Kojto	90:cb3d968589d8	1635	/*!
Kojto	90:cb3d968589d8	1636	* @brief All RTC module registers.
Kojto	90:cb3d968589d8	1637	*/
Kojto	90:cb3d968589d8	1638	#pragma pack(1)
Kojto	90:cb3d968589d8	1639	typedef struct _hw_rtc
Kojto	90:cb3d968589d8	1640	{
Kojto	90:cb3d968589d8	1641	__IO hw_rtc_tsr_t TSR; /!< [0x0] RTC Time Seconds Register /
Kojto	90:cb3d968589d8	1642	__IO hw_rtc_tpr_t TPR; /!< [0x4] RTC Time Prescaler Register /
Kojto	90:cb3d968589d8	1643	__IO hw_rtc_tar_t TAR; /!< [0x8] RTC Time Alarm Register /
Kojto	90:cb3d968589d8	1644	__IO hw_rtc_tcr_t TCR; /!< [0xC] RTC Time Compensation Register /
Kojto	90:cb3d968589d8	1645	__IO hw_rtc_cr_t CR; /!< [0x10] RTC Control Register /
Kojto	90:cb3d968589d8	1646	__IO hw_rtc_sr_t SR; /!< [0x14] RTC Status Register /
Kojto	90:cb3d968589d8	1647	__IO hw_rtc_lr_t LR; /!< [0x18] RTC Lock Register /
Kojto	90:cb3d968589d8	1648	__IO hw_rtc_ier_t IER; /!< [0x1C] RTC Interrupt Enable Register /
Kojto	90:cb3d968589d8	1649	uint8_t _reserved0[2016];
Kojto	90:cb3d968589d8	1650	__IO hw_rtc_war_t WAR; /!< [0x800] RTC Write Access Register /
Kojto	90:cb3d968589d8	1651	__IO hw_rtc_rar_t RAR; /!< [0x804] RTC Read Access Register /
Kojto	90:cb3d968589d8	1652	} hw_rtc_t;
Kojto	90:cb3d968589d8	1653	#pragma pack()
Kojto	90:cb3d968589d8	1654
Kojto	90:cb3d968589d8	1655	/! @brief Macro to access all RTC registers. /
Kojto	90:cb3d968589d8	1656	/! @param x RTC module instance base address. /
Kojto	90:cb3d968589d8	1657	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto	90:cb3d968589d8	1658	* use the '&' operator, like <code>&HW_RTC(RTC_BASE)</code>. */
Kojto	90:cb3d968589d8	1659	#define HW_RTC(x) ((hw_rtc_t )(x))
Kojto	90:cb3d968589d8	1660
Kojto	90:cb3d968589d8	1661	#endif /* __HW_RTC_REGISTERS_H__ */
Kojto	90:cb3d968589d8	1662	/* EOF */