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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_lptmr.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:
Kojto
Date:
Tue Oct 28 16:40:41 2014 +0000
Revision:
90:cb3d968589d8
Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_LPTMR_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_LPTMR_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 LPTMR
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * Low Power Timer
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_LPTMR_CSR - Low Power Timer Control Status Register
Kojto 90:cb3d968589d8 93 * - HW_LPTMR_PSR - Low Power Timer Prescale Register
Kojto 90:cb3d968589d8 94 * - HW_LPTMR_CMR - Low Power Timer Compare Register
Kojto 90:cb3d968589d8 95 * - HW_LPTMR_CNR - Low Power Timer Counter Register
Kojto 90:cb3d968589d8 96 *
Kojto 90:cb3d968589d8 97 * - hw_lptmr_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 98 */
Kojto 90:cb3d968589d8 99
Kojto 90:cb3d968589d8 100 #define HW_LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
Kojto 90:cb3d968589d8 101
Kojto 90:cb3d968589d8 102 /*******************************************************************************
Kojto 90:cb3d968589d8 103 * HW_LPTMR_CSR - Low Power Timer Control Status Register
Kojto 90:cb3d968589d8 104 ******************************************************************************/
Kojto 90:cb3d968589d8 105
Kojto 90:cb3d968589d8 106 /*!
Kojto 90:cb3d968589d8 107 * @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW)
Kojto 90:cb3d968589d8 108 *
Kojto 90:cb3d968589d8 109 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 110 */
Kojto 90:cb3d968589d8 111 typedef union _hw_lptmr_csr
Kojto 90:cb3d968589d8 112 {
Kojto 90:cb3d968589d8 113 uint32_t U;
Kojto 90:cb3d968589d8 114 struct _hw_lptmr_csr_bitfields
Kojto 90:cb3d968589d8 115 {
Kojto 90:cb3d968589d8 116 uint32_t TEN : 1; /*!< [0] Timer Enable */
Kojto 90:cb3d968589d8 117 uint32_t TMS : 1; /*!< [1] Timer Mode Select */
Kojto 90:cb3d968589d8 118 uint32_t TFC : 1; /*!< [2] Timer Free-Running Counter */
Kojto 90:cb3d968589d8 119 uint32_t TPP : 1; /*!< [3] Timer Pin Polarity */
Kojto 90:cb3d968589d8 120 uint32_t TPS : 2; /*!< [5:4] Timer Pin Select */
Kojto 90:cb3d968589d8 121 uint32_t TIE : 1; /*!< [6] Timer Interrupt Enable */
Kojto 90:cb3d968589d8 122 uint32_t TCF : 1; /*!< [7] Timer Compare Flag */
Kojto 90:cb3d968589d8 123 uint32_t RESERVED0 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 124 } B;
Kojto 90:cb3d968589d8 125 } hw_lptmr_csr_t;
Kojto 90:cb3d968589d8 126
Kojto 90:cb3d968589d8 127 /*!
Kojto 90:cb3d968589d8 128 * @name Constants and macros for entire LPTMR_CSR register
Kojto 90:cb3d968589d8 129 */
Kojto 90:cb3d968589d8 130 /*@{*/
Kojto 90:cb3d968589d8 131 #define HW_LPTMR_CSR_ADDR(x) ((x) + 0x0U)
Kojto 90:cb3d968589d8 132
Kojto 90:cb3d968589d8 133 #define HW_LPTMR_CSR(x) (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR(x))
Kojto 90:cb3d968589d8 134 #define HW_LPTMR_CSR_RD(x) (HW_LPTMR_CSR(x).U)
Kojto 90:cb3d968589d8 135 #define HW_LPTMR_CSR_WR(x, v) (HW_LPTMR_CSR(x).U = (v))
Kojto 90:cb3d968589d8 136 #define HW_LPTMR_CSR_SET(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) | (v)))
Kojto 90:cb3d968589d8 137 #define HW_LPTMR_CSR_CLR(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 138 #define HW_LPTMR_CSR_TOG(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 139 /*@}*/
Kojto 90:cb3d968589d8 140
Kojto 90:cb3d968589d8 141 /*
Kojto 90:cb3d968589d8 142 * Constants & macros for individual LPTMR_CSR bitfields
Kojto 90:cb3d968589d8 143 */
Kojto 90:cb3d968589d8 144
Kojto 90:cb3d968589d8 145 /*!
Kojto 90:cb3d968589d8 146 * @name Register LPTMR_CSR, field TEN[0] (RW)
Kojto 90:cb3d968589d8 147 *
Kojto 90:cb3d968589d8 148 * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
Kojto 90:cb3d968589d8 149 * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
Kojto 90:cb3d968589d8 150 * CSR[5:1] must not be altered.
Kojto 90:cb3d968589d8 151 *
Kojto 90:cb3d968589d8 152 * Values:
Kojto 90:cb3d968589d8 153 * - 0 - LPTMR is disabled and internal logic is reset.
Kojto 90:cb3d968589d8 154 * - 1 - LPTMR is enabled.
Kojto 90:cb3d968589d8 155 */
Kojto 90:cb3d968589d8 156 /*@{*/
Kojto 90:cb3d968589d8 157 #define BP_LPTMR_CSR_TEN (0U) /*!< Bit position for LPTMR_CSR_TEN. */
Kojto 90:cb3d968589d8 158 #define BM_LPTMR_CSR_TEN (0x00000001U) /*!< Bit mask for LPTMR_CSR_TEN. */
Kojto 90:cb3d968589d8 159 #define BS_LPTMR_CSR_TEN (1U) /*!< Bit field size in bits for LPTMR_CSR_TEN. */
Kojto 90:cb3d968589d8 160
Kojto 90:cb3d968589d8 161 /*! @brief Read current value of the LPTMR_CSR_TEN field. */
Kojto 90:cb3d968589d8 162 #define BR_LPTMR_CSR_TEN(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN))
Kojto 90:cb3d968589d8 163
Kojto 90:cb3d968589d8 164 /*! @brief Format value for bitfield LPTMR_CSR_TEN. */
Kojto 90:cb3d968589d8 165 #define BF_LPTMR_CSR_TEN(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TEN) & BM_LPTMR_CSR_TEN)
Kojto 90:cb3d968589d8 166
Kojto 90:cb3d968589d8 167 /*! @brief Set the TEN field to a new value. */
Kojto 90:cb3d968589d8 168 #define BW_LPTMR_CSR_TEN(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN) = (v))
Kojto 90:cb3d968589d8 169 /*@}*/
Kojto 90:cb3d968589d8 170
Kojto 90:cb3d968589d8 171 /*!
Kojto 90:cb3d968589d8 172 * @name Register LPTMR_CSR, field TMS[1] (RW)
Kojto 90:cb3d968589d8 173 *
Kojto 90:cb3d968589d8 174 * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
Kojto 90:cb3d968589d8 175 * disabled.
Kojto 90:cb3d968589d8 176 *
Kojto 90:cb3d968589d8 177 * Values:
Kojto 90:cb3d968589d8 178 * - 0 - Time Counter mode.
Kojto 90:cb3d968589d8 179 * - 1 - Pulse Counter mode.
Kojto 90:cb3d968589d8 180 */
Kojto 90:cb3d968589d8 181 /*@{*/
Kojto 90:cb3d968589d8 182 #define BP_LPTMR_CSR_TMS (1U) /*!< Bit position for LPTMR_CSR_TMS. */
Kojto 90:cb3d968589d8 183 #define BM_LPTMR_CSR_TMS (0x00000002U) /*!< Bit mask for LPTMR_CSR_TMS. */
Kojto 90:cb3d968589d8 184 #define BS_LPTMR_CSR_TMS (1U) /*!< Bit field size in bits for LPTMR_CSR_TMS. */
Kojto 90:cb3d968589d8 185
Kojto 90:cb3d968589d8 186 /*! @brief Read current value of the LPTMR_CSR_TMS field. */
Kojto 90:cb3d968589d8 187 #define BR_LPTMR_CSR_TMS(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS))
Kojto 90:cb3d968589d8 188
Kojto 90:cb3d968589d8 189 /*! @brief Format value for bitfield LPTMR_CSR_TMS. */
Kojto 90:cb3d968589d8 190 #define BF_LPTMR_CSR_TMS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TMS) & BM_LPTMR_CSR_TMS)
Kojto 90:cb3d968589d8 191
Kojto 90:cb3d968589d8 192 /*! @brief Set the TMS field to a new value. */
Kojto 90:cb3d968589d8 193 #define BW_LPTMR_CSR_TMS(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS) = (v))
Kojto 90:cb3d968589d8 194 /*@}*/
Kojto 90:cb3d968589d8 195
Kojto 90:cb3d968589d8 196 /*!
Kojto 90:cb3d968589d8 197 * @name Register LPTMR_CSR, field TFC[2] (RW)
Kojto 90:cb3d968589d8 198 *
Kojto 90:cb3d968589d8 199 * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
Kojto 90:cb3d968589d8 200 * TFC configures the CNR to reset on overflow. TFC must be altered only when the
Kojto 90:cb3d968589d8 201 * LPTMR is disabled.
Kojto 90:cb3d968589d8 202 *
Kojto 90:cb3d968589d8 203 * Values:
Kojto 90:cb3d968589d8 204 * - 0 - CNR is reset whenever TCF is set.
Kojto 90:cb3d968589d8 205 * - 1 - CNR is reset on overflow.
Kojto 90:cb3d968589d8 206 */
Kojto 90:cb3d968589d8 207 /*@{*/
Kojto 90:cb3d968589d8 208 #define BP_LPTMR_CSR_TFC (2U) /*!< Bit position for LPTMR_CSR_TFC. */
Kojto 90:cb3d968589d8 209 #define BM_LPTMR_CSR_TFC (0x00000004U) /*!< Bit mask for LPTMR_CSR_TFC. */
Kojto 90:cb3d968589d8 210 #define BS_LPTMR_CSR_TFC (1U) /*!< Bit field size in bits for LPTMR_CSR_TFC. */
Kojto 90:cb3d968589d8 211
Kojto 90:cb3d968589d8 212 /*! @brief Read current value of the LPTMR_CSR_TFC field. */
Kojto 90:cb3d968589d8 213 #define BR_LPTMR_CSR_TFC(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC))
Kojto 90:cb3d968589d8 214
Kojto 90:cb3d968589d8 215 /*! @brief Format value for bitfield LPTMR_CSR_TFC. */
Kojto 90:cb3d968589d8 216 #define BF_LPTMR_CSR_TFC(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TFC) & BM_LPTMR_CSR_TFC)
Kojto 90:cb3d968589d8 217
Kojto 90:cb3d968589d8 218 /*! @brief Set the TFC field to a new value. */
Kojto 90:cb3d968589d8 219 #define BW_LPTMR_CSR_TFC(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC) = (v))
Kojto 90:cb3d968589d8 220 /*@}*/
Kojto 90:cb3d968589d8 221
Kojto 90:cb3d968589d8 222 /*!
Kojto 90:cb3d968589d8 223 * @name Register LPTMR_CSR, field TPP[3] (RW)
Kojto 90:cb3d968589d8 224 *
Kojto 90:cb3d968589d8 225 * Configures the polarity of the input source in Pulse Counter mode. TPP must
Kojto 90:cb3d968589d8 226 * be changed only when the LPTMR is disabled.
Kojto 90:cb3d968589d8 227 *
Kojto 90:cb3d968589d8 228 * Values:
Kojto 90:cb3d968589d8 229 * - 0 - Pulse Counter input source is active-high, and the CNR will increment
Kojto 90:cb3d968589d8 230 * on the rising-edge.
Kojto 90:cb3d968589d8 231 * - 1 - Pulse Counter input source is active-low, and the CNR will increment on
Kojto 90:cb3d968589d8 232 * the falling-edge.
Kojto 90:cb3d968589d8 233 */
Kojto 90:cb3d968589d8 234 /*@{*/
Kojto 90:cb3d968589d8 235 #define BP_LPTMR_CSR_TPP (3U) /*!< Bit position for LPTMR_CSR_TPP. */
Kojto 90:cb3d968589d8 236 #define BM_LPTMR_CSR_TPP (0x00000008U) /*!< Bit mask for LPTMR_CSR_TPP. */
Kojto 90:cb3d968589d8 237 #define BS_LPTMR_CSR_TPP (1U) /*!< Bit field size in bits for LPTMR_CSR_TPP. */
Kojto 90:cb3d968589d8 238
Kojto 90:cb3d968589d8 239 /*! @brief Read current value of the LPTMR_CSR_TPP field. */
Kojto 90:cb3d968589d8 240 #define BR_LPTMR_CSR_TPP(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP))
Kojto 90:cb3d968589d8 241
Kojto 90:cb3d968589d8 242 /*! @brief Format value for bitfield LPTMR_CSR_TPP. */
Kojto 90:cb3d968589d8 243 #define BF_LPTMR_CSR_TPP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPP) & BM_LPTMR_CSR_TPP)
Kojto 90:cb3d968589d8 244
Kojto 90:cb3d968589d8 245 /*! @brief Set the TPP field to a new value. */
Kojto 90:cb3d968589d8 246 #define BW_LPTMR_CSR_TPP(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP) = (v))
Kojto 90:cb3d968589d8 247 /*@}*/
Kojto 90:cb3d968589d8 248
Kojto 90:cb3d968589d8 249 /*!
Kojto 90:cb3d968589d8 250 * @name Register LPTMR_CSR, field TPS[5:4] (RW)
Kojto 90:cb3d968589d8 251 *
Kojto 90:cb3d968589d8 252 * Configures the input source to be used in Pulse Counter mode. TPS must be
Kojto 90:cb3d968589d8 253 * altered only when the LPTMR is disabled. The input connections vary by device.
Kojto 90:cb3d968589d8 254 * See the chip configuration details for information on the connections to these
Kojto 90:cb3d968589d8 255 * inputs.
Kojto 90:cb3d968589d8 256 *
Kojto 90:cb3d968589d8 257 * Values:
Kojto 90:cb3d968589d8 258 * - 00 - Pulse counter input 0 is selected.
Kojto 90:cb3d968589d8 259 * - 01 - Pulse counter input 1 is selected.
Kojto 90:cb3d968589d8 260 * - 10 - Pulse counter input 2 is selected.
Kojto 90:cb3d968589d8 261 * - 11 - Pulse counter input 3 is selected.
Kojto 90:cb3d968589d8 262 */
Kojto 90:cb3d968589d8 263 /*@{*/
Kojto 90:cb3d968589d8 264 #define BP_LPTMR_CSR_TPS (4U) /*!< Bit position for LPTMR_CSR_TPS. */
Kojto 90:cb3d968589d8 265 #define BM_LPTMR_CSR_TPS (0x00000030U) /*!< Bit mask for LPTMR_CSR_TPS. */
Kojto 90:cb3d968589d8 266 #define BS_LPTMR_CSR_TPS (2U) /*!< Bit field size in bits for LPTMR_CSR_TPS. */
Kojto 90:cb3d968589d8 267
Kojto 90:cb3d968589d8 268 /*! @brief Read current value of the LPTMR_CSR_TPS field. */
Kojto 90:cb3d968589d8 269 #define BR_LPTMR_CSR_TPS(x) (HW_LPTMR_CSR(x).B.TPS)
Kojto 90:cb3d968589d8 270
Kojto 90:cb3d968589d8 271 /*! @brief Format value for bitfield LPTMR_CSR_TPS. */
Kojto 90:cb3d968589d8 272 #define BF_LPTMR_CSR_TPS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPS) & BM_LPTMR_CSR_TPS)
Kojto 90:cb3d968589d8 273
Kojto 90:cb3d968589d8 274 /*! @brief Set the TPS field to a new value. */
Kojto 90:cb3d968589d8 275 #define BW_LPTMR_CSR_TPS(x, v) (HW_LPTMR_CSR_WR(x, (HW_LPTMR_CSR_RD(x) & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v)))
Kojto 90:cb3d968589d8 276 /*@}*/
Kojto 90:cb3d968589d8 277
Kojto 90:cb3d968589d8 278 /*!
Kojto 90:cb3d968589d8 279 * @name Register LPTMR_CSR, field TIE[6] (RW)
Kojto 90:cb3d968589d8 280 *
Kojto 90:cb3d968589d8 281 * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
Kojto 90:cb3d968589d8 282 *
Kojto 90:cb3d968589d8 283 * Values:
Kojto 90:cb3d968589d8 284 * - 0 - Timer interrupt disabled.
Kojto 90:cb3d968589d8 285 * - 1 - Timer interrupt enabled.
Kojto 90:cb3d968589d8 286 */
Kojto 90:cb3d968589d8 287 /*@{*/
Kojto 90:cb3d968589d8 288 #define BP_LPTMR_CSR_TIE (6U) /*!< Bit position for LPTMR_CSR_TIE. */
Kojto 90:cb3d968589d8 289 #define BM_LPTMR_CSR_TIE (0x00000040U) /*!< Bit mask for LPTMR_CSR_TIE. */
Kojto 90:cb3d968589d8 290 #define BS_LPTMR_CSR_TIE (1U) /*!< Bit field size in bits for LPTMR_CSR_TIE. */
Kojto 90:cb3d968589d8 291
Kojto 90:cb3d968589d8 292 /*! @brief Read current value of the LPTMR_CSR_TIE field. */
Kojto 90:cb3d968589d8 293 #define BR_LPTMR_CSR_TIE(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE))
Kojto 90:cb3d968589d8 294
Kojto 90:cb3d968589d8 295 /*! @brief Format value for bitfield LPTMR_CSR_TIE. */
Kojto 90:cb3d968589d8 296 #define BF_LPTMR_CSR_TIE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TIE) & BM_LPTMR_CSR_TIE)
Kojto 90:cb3d968589d8 297
Kojto 90:cb3d968589d8 298 /*! @brief Set the TIE field to a new value. */
Kojto 90:cb3d968589d8 299 #define BW_LPTMR_CSR_TIE(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE) = (v))
Kojto 90:cb3d968589d8 300 /*@}*/
Kojto 90:cb3d968589d8 301
Kojto 90:cb3d968589d8 302 /*!
Kojto 90:cb3d968589d8 303 * @name Register LPTMR_CSR, field TCF[7] (W1C)
Kojto 90:cb3d968589d8 304 *
Kojto 90:cb3d968589d8 305 * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
Kojto 90:cb3d968589d8 306 * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
Kojto 90:cb3d968589d8 307 *
Kojto 90:cb3d968589d8 308 * Values:
Kojto 90:cb3d968589d8 309 * - 0 - The value of CNR is not equal to CMR and increments.
Kojto 90:cb3d968589d8 310 * - 1 - The value of CNR is equal to CMR and increments.
Kojto 90:cb3d968589d8 311 */
Kojto 90:cb3d968589d8 312 /*@{*/
Kojto 90:cb3d968589d8 313 #define BP_LPTMR_CSR_TCF (7U) /*!< Bit position for LPTMR_CSR_TCF. */
Kojto 90:cb3d968589d8 314 #define BM_LPTMR_CSR_TCF (0x00000080U) /*!< Bit mask for LPTMR_CSR_TCF. */
Kojto 90:cb3d968589d8 315 #define BS_LPTMR_CSR_TCF (1U) /*!< Bit field size in bits for LPTMR_CSR_TCF. */
Kojto 90:cb3d968589d8 316
Kojto 90:cb3d968589d8 317 /*! @brief Read current value of the LPTMR_CSR_TCF field. */
Kojto 90:cb3d968589d8 318 #define BR_LPTMR_CSR_TCF(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF))
Kojto 90:cb3d968589d8 319
Kojto 90:cb3d968589d8 320 /*! @brief Format value for bitfield LPTMR_CSR_TCF. */
Kojto 90:cb3d968589d8 321 #define BF_LPTMR_CSR_TCF(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TCF) & BM_LPTMR_CSR_TCF)
Kojto 90:cb3d968589d8 322
Kojto 90:cb3d968589d8 323 /*! @brief Set the TCF field to a new value. */
Kojto 90:cb3d968589d8 324 #define BW_LPTMR_CSR_TCF(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF) = (v))
Kojto 90:cb3d968589d8 325 /*@}*/
Kojto 90:cb3d968589d8 326
Kojto 90:cb3d968589d8 327 /*******************************************************************************
Kojto 90:cb3d968589d8 328 * HW_LPTMR_PSR - Low Power Timer Prescale Register
Kojto 90:cb3d968589d8 329 ******************************************************************************/
Kojto 90:cb3d968589d8 330
Kojto 90:cb3d968589d8 331 /*!
Kojto 90:cb3d968589d8 332 * @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW)
Kojto 90:cb3d968589d8 333 *
Kojto 90:cb3d968589d8 334 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 335 */
Kojto 90:cb3d968589d8 336 typedef union _hw_lptmr_psr
Kojto 90:cb3d968589d8 337 {
Kojto 90:cb3d968589d8 338 uint32_t U;
Kojto 90:cb3d968589d8 339 struct _hw_lptmr_psr_bitfields
Kojto 90:cb3d968589d8 340 {
Kojto 90:cb3d968589d8 341 uint32_t PCS : 2; /*!< [1:0] Prescaler Clock Select */
Kojto 90:cb3d968589d8 342 uint32_t PBYP : 1; /*!< [2] Prescaler Bypass */
Kojto 90:cb3d968589d8 343 uint32_t PRESCALE : 4; /*!< [6:3] Prescale Value */
Kojto 90:cb3d968589d8 344 uint32_t RESERVED0 : 25; /*!< [31:7] */
Kojto 90:cb3d968589d8 345 } B;
Kojto 90:cb3d968589d8 346 } hw_lptmr_psr_t;
Kojto 90:cb3d968589d8 347
Kojto 90:cb3d968589d8 348 /*!
Kojto 90:cb3d968589d8 349 * @name Constants and macros for entire LPTMR_PSR register
Kojto 90:cb3d968589d8 350 */
Kojto 90:cb3d968589d8 351 /*@{*/
Kojto 90:cb3d968589d8 352 #define HW_LPTMR_PSR_ADDR(x) ((x) + 0x4U)
Kojto 90:cb3d968589d8 353
Kojto 90:cb3d968589d8 354 #define HW_LPTMR_PSR(x) (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR(x))
Kojto 90:cb3d968589d8 355 #define HW_LPTMR_PSR_RD(x) (HW_LPTMR_PSR(x).U)
Kojto 90:cb3d968589d8 356 #define HW_LPTMR_PSR_WR(x, v) (HW_LPTMR_PSR(x).U = (v))
Kojto 90:cb3d968589d8 357 #define HW_LPTMR_PSR_SET(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) | (v)))
Kojto 90:cb3d968589d8 358 #define HW_LPTMR_PSR_CLR(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 359 #define HW_LPTMR_PSR_TOG(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 360 /*@}*/
Kojto 90:cb3d968589d8 361
Kojto 90:cb3d968589d8 362 /*
Kojto 90:cb3d968589d8 363 * Constants & macros for individual LPTMR_PSR bitfields
Kojto 90:cb3d968589d8 364 */
Kojto 90:cb3d968589d8 365
Kojto 90:cb3d968589d8 366 /*!
Kojto 90:cb3d968589d8 367 * @name Register LPTMR_PSR, field PCS[1:0] (RW)
Kojto 90:cb3d968589d8 368 *
Kojto 90:cb3d968589d8 369 * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
Kojto 90:cb3d968589d8 370 * be altered only when the LPTMR is disabled. The clock connections vary by
Kojto 90:cb3d968589d8 371 * device. See the chip configuration details for information on the connections to
Kojto 90:cb3d968589d8 372 * these inputs.
Kojto 90:cb3d968589d8 373 *
Kojto 90:cb3d968589d8 374 * Values:
Kojto 90:cb3d968589d8 375 * - 00 - Prescaler/glitch filter clock 0 selected.
Kojto 90:cb3d968589d8 376 * - 01 - Prescaler/glitch filter clock 1 selected.
Kojto 90:cb3d968589d8 377 * - 10 - Prescaler/glitch filter clock 2 selected.
Kojto 90:cb3d968589d8 378 * - 11 - Prescaler/glitch filter clock 3 selected.
Kojto 90:cb3d968589d8 379 */
Kojto 90:cb3d968589d8 380 /*@{*/
Kojto 90:cb3d968589d8 381 #define BP_LPTMR_PSR_PCS (0U) /*!< Bit position for LPTMR_PSR_PCS. */
Kojto 90:cb3d968589d8 382 #define BM_LPTMR_PSR_PCS (0x00000003U) /*!< Bit mask for LPTMR_PSR_PCS. */
Kojto 90:cb3d968589d8 383 #define BS_LPTMR_PSR_PCS (2U) /*!< Bit field size in bits for LPTMR_PSR_PCS. */
Kojto 90:cb3d968589d8 384
Kojto 90:cb3d968589d8 385 /*! @brief Read current value of the LPTMR_PSR_PCS field. */
Kojto 90:cb3d968589d8 386 #define BR_LPTMR_PSR_PCS(x) (HW_LPTMR_PSR(x).B.PCS)
Kojto 90:cb3d968589d8 387
Kojto 90:cb3d968589d8 388 /*! @brief Format value for bitfield LPTMR_PSR_PCS. */
Kojto 90:cb3d968589d8 389 #define BF_LPTMR_PSR_PCS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PCS) & BM_LPTMR_PSR_PCS)
Kojto 90:cb3d968589d8 390
Kojto 90:cb3d968589d8 391 /*! @brief Set the PCS field to a new value. */
Kojto 90:cb3d968589d8 392 #define BW_LPTMR_PSR_PCS(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v)))
Kojto 90:cb3d968589d8 393 /*@}*/
Kojto 90:cb3d968589d8 394
Kojto 90:cb3d968589d8 395 /*!
Kojto 90:cb3d968589d8 396 * @name Register LPTMR_PSR, field PBYP[2] (RW)
Kojto 90:cb3d968589d8 397 *
Kojto 90:cb3d968589d8 398 * When PBYP is set, the selected prescaler clock in Time Counter mode or
Kojto 90:cb3d968589d8 399 * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
Kojto 90:cb3d968589d8 400 * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
Kojto 90:cb3d968589d8 401 * must be altered only when the LPTMR is disabled.
Kojto 90:cb3d968589d8 402 *
Kojto 90:cb3d968589d8 403 * Values:
Kojto 90:cb3d968589d8 404 * - 0 - Prescaler/glitch filter is enabled.
Kojto 90:cb3d968589d8 405 * - 1 - Prescaler/glitch filter is bypassed.
Kojto 90:cb3d968589d8 406 */
Kojto 90:cb3d968589d8 407 /*@{*/
Kojto 90:cb3d968589d8 408 #define BP_LPTMR_PSR_PBYP (2U) /*!< Bit position for LPTMR_PSR_PBYP. */
Kojto 90:cb3d968589d8 409 #define BM_LPTMR_PSR_PBYP (0x00000004U) /*!< Bit mask for LPTMR_PSR_PBYP. */
Kojto 90:cb3d968589d8 410 #define BS_LPTMR_PSR_PBYP (1U) /*!< Bit field size in bits for LPTMR_PSR_PBYP. */
Kojto 90:cb3d968589d8 411
Kojto 90:cb3d968589d8 412 /*! @brief Read current value of the LPTMR_PSR_PBYP field. */
Kojto 90:cb3d968589d8 413 #define BR_LPTMR_PSR_PBYP(x) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP))
Kojto 90:cb3d968589d8 414
Kojto 90:cb3d968589d8 415 /*! @brief Format value for bitfield LPTMR_PSR_PBYP. */
Kojto 90:cb3d968589d8 416 #define BF_LPTMR_PSR_PBYP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PBYP) & BM_LPTMR_PSR_PBYP)
Kojto 90:cb3d968589d8 417
Kojto 90:cb3d968589d8 418 /*! @brief Set the PBYP field to a new value. */
Kojto 90:cb3d968589d8 419 #define BW_LPTMR_PSR_PBYP(x, v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP) = (v))
Kojto 90:cb3d968589d8 420 /*@}*/
Kojto 90:cb3d968589d8 421
Kojto 90:cb3d968589d8 422 /*!
Kojto 90:cb3d968589d8 423 * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
Kojto 90:cb3d968589d8 424 *
Kojto 90:cb3d968589d8 425 * Configures the size of the Prescaler in Time Counter mode or width of the
Kojto 90:cb3d968589d8 426 * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
Kojto 90:cb3d968589d8 427 * is disabled.
Kojto 90:cb3d968589d8 428 *
Kojto 90:cb3d968589d8 429 * Values:
Kojto 90:cb3d968589d8 430 * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
Kojto 90:cb3d968589d8 431 * support this configuration.
Kojto 90:cb3d968589d8 432 * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
Kojto 90:cb3d968589d8 433 * change on input pin after 2 rising clock edges.
Kojto 90:cb3d968589d8 434 * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
Kojto 90:cb3d968589d8 435 * change on input pin after 4 rising clock edges.
Kojto 90:cb3d968589d8 436 * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
Kojto 90:cb3d968589d8 437 * recognizes change on input pin after 8 rising clock edges.
Kojto 90:cb3d968589d8 438 * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
Kojto 90:cb3d968589d8 439 * recognizes change on input pin after 16 rising clock edges.
Kojto 90:cb3d968589d8 440 * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
Kojto 90:cb3d968589d8 441 * recognizes change on input pin after 32 rising clock edges.
Kojto 90:cb3d968589d8 442 * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
Kojto 90:cb3d968589d8 443 * recognizes change on input pin after 64 rising clock edges.
Kojto 90:cb3d968589d8 444 * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
Kojto 90:cb3d968589d8 445 * recognizes change on input pin after 128 rising clock edges.
Kojto 90:cb3d968589d8 446 * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
Kojto 90:cb3d968589d8 447 * recognizes change on input pin after 256 rising clock edges.
Kojto 90:cb3d968589d8 448 * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
Kojto 90:cb3d968589d8 449 * recognizes change on input pin after 512 rising clock edges.
Kojto 90:cb3d968589d8 450 * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
Kojto 90:cb3d968589d8 451 * recognizes change on input pin after 1024 rising clock edges.
Kojto 90:cb3d968589d8 452 * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
Kojto 90:cb3d968589d8 453 * recognizes change on input pin after 2048 rising clock edges.
Kojto 90:cb3d968589d8 454 * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
Kojto 90:cb3d968589d8 455 * recognizes change on input pin after 4096 rising clock edges.
Kojto 90:cb3d968589d8 456 * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
Kojto 90:cb3d968589d8 457 * recognizes change on input pin after 8192 rising clock edges.
Kojto 90:cb3d968589d8 458 * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
Kojto 90:cb3d968589d8 459 * recognizes change on input pin after 16,384 rising clock edges.
Kojto 90:cb3d968589d8 460 * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
Kojto 90:cb3d968589d8 461 * recognizes change on input pin after 32,768 rising clock edges.
Kojto 90:cb3d968589d8 462 */
Kojto 90:cb3d968589d8 463 /*@{*/
Kojto 90:cb3d968589d8 464 #define BP_LPTMR_PSR_PRESCALE (3U) /*!< Bit position for LPTMR_PSR_PRESCALE. */
Kojto 90:cb3d968589d8 465 #define BM_LPTMR_PSR_PRESCALE (0x00000078U) /*!< Bit mask for LPTMR_PSR_PRESCALE. */
Kojto 90:cb3d968589d8 466 #define BS_LPTMR_PSR_PRESCALE (4U) /*!< Bit field size in bits for LPTMR_PSR_PRESCALE. */
Kojto 90:cb3d968589d8 467
Kojto 90:cb3d968589d8 468 /*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
Kojto 90:cb3d968589d8 469 #define BR_LPTMR_PSR_PRESCALE(x) (HW_LPTMR_PSR(x).B.PRESCALE)
Kojto 90:cb3d968589d8 470
Kojto 90:cb3d968589d8 471 /*! @brief Format value for bitfield LPTMR_PSR_PRESCALE. */
Kojto 90:cb3d968589d8 472 #define BF_LPTMR_PSR_PRESCALE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PRESCALE) & BM_LPTMR_PSR_PRESCALE)
Kojto 90:cb3d968589d8 473
Kojto 90:cb3d968589d8 474 /*! @brief Set the PRESCALE field to a new value. */
Kojto 90:cb3d968589d8 475 #define BW_LPTMR_PSR_PRESCALE(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v)))
Kojto 90:cb3d968589d8 476 /*@}*/
Kojto 90:cb3d968589d8 477
Kojto 90:cb3d968589d8 478 /*******************************************************************************
Kojto 90:cb3d968589d8 479 * HW_LPTMR_CMR - Low Power Timer Compare Register
Kojto 90:cb3d968589d8 480 ******************************************************************************/
Kojto 90:cb3d968589d8 481
Kojto 90:cb3d968589d8 482 /*!
Kojto 90:cb3d968589d8 483 * @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW)
Kojto 90:cb3d968589d8 484 *
Kojto 90:cb3d968589d8 485 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 486 */
Kojto 90:cb3d968589d8 487 typedef union _hw_lptmr_cmr
Kojto 90:cb3d968589d8 488 {
Kojto 90:cb3d968589d8 489 uint32_t U;
Kojto 90:cb3d968589d8 490 struct _hw_lptmr_cmr_bitfields
Kojto 90:cb3d968589d8 491 {
Kojto 90:cb3d968589d8 492 uint32_t COMPARE : 16; /*!< [15:0] Compare Value */
Kojto 90:cb3d968589d8 493 uint32_t RESERVED0 : 16; /*!< [31:16] */
Kojto 90:cb3d968589d8 494 } B;
Kojto 90:cb3d968589d8 495 } hw_lptmr_cmr_t;
Kojto 90:cb3d968589d8 496
Kojto 90:cb3d968589d8 497 /*!
Kojto 90:cb3d968589d8 498 * @name Constants and macros for entire LPTMR_CMR register
Kojto 90:cb3d968589d8 499 */
Kojto 90:cb3d968589d8 500 /*@{*/
Kojto 90:cb3d968589d8 501 #define HW_LPTMR_CMR_ADDR(x) ((x) + 0x8U)
Kojto 90:cb3d968589d8 502
Kojto 90:cb3d968589d8 503 #define HW_LPTMR_CMR(x) (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR(x))
Kojto 90:cb3d968589d8 504 #define HW_LPTMR_CMR_RD(x) (HW_LPTMR_CMR(x).U)
Kojto 90:cb3d968589d8 505 #define HW_LPTMR_CMR_WR(x, v) (HW_LPTMR_CMR(x).U = (v))
Kojto 90:cb3d968589d8 506 #define HW_LPTMR_CMR_SET(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) | (v)))
Kojto 90:cb3d968589d8 507 #define HW_LPTMR_CMR_CLR(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 508 #define HW_LPTMR_CMR_TOG(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 509 /*@}*/
Kojto 90:cb3d968589d8 510
Kojto 90:cb3d968589d8 511 /*
Kojto 90:cb3d968589d8 512 * Constants & macros for individual LPTMR_CMR bitfields
Kojto 90:cb3d968589d8 513 */
Kojto 90:cb3d968589d8 514
Kojto 90:cb3d968589d8 515 /*!
Kojto 90:cb3d968589d8 516 * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
Kojto 90:cb3d968589d8 517 *
Kojto 90:cb3d968589d8 518 * When the LPTMR is enabled and the CNR equals the value in the CMR and
Kojto 90:cb3d968589d8 519 * increments, TCF is set and the hardware trigger asserts until the next time the CNR
Kojto 90:cb3d968589d8 520 * increments. If the CMR is 0, the hardware trigger will remain asserted until
Kojto 90:cb3d968589d8 521 * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
Kojto 90:cb3d968589d8 522 * when TCF is set.
Kojto 90:cb3d968589d8 523 */
Kojto 90:cb3d968589d8 524 /*@{*/
Kojto 90:cb3d968589d8 525 #define BP_LPTMR_CMR_COMPARE (0U) /*!< Bit position for LPTMR_CMR_COMPARE. */
Kojto 90:cb3d968589d8 526 #define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) /*!< Bit mask for LPTMR_CMR_COMPARE. */
Kojto 90:cb3d968589d8 527 #define BS_LPTMR_CMR_COMPARE (16U) /*!< Bit field size in bits for LPTMR_CMR_COMPARE. */
Kojto 90:cb3d968589d8 528
Kojto 90:cb3d968589d8 529 /*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
Kojto 90:cb3d968589d8 530 #define BR_LPTMR_CMR_COMPARE(x) (HW_LPTMR_CMR(x).B.COMPARE)
Kojto 90:cb3d968589d8 531
Kojto 90:cb3d968589d8 532 /*! @brief Format value for bitfield LPTMR_CMR_COMPARE. */
Kojto 90:cb3d968589d8 533 #define BF_LPTMR_CMR_COMPARE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CMR_COMPARE) & BM_LPTMR_CMR_COMPARE)
Kojto 90:cb3d968589d8 534
Kojto 90:cb3d968589d8 535 /*! @brief Set the COMPARE field to a new value. */
Kojto 90:cb3d968589d8 536 #define BW_LPTMR_CMR_COMPARE(x, v) (HW_LPTMR_CMR_WR(x, (HW_LPTMR_CMR_RD(x) & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v)))
Kojto 90:cb3d968589d8 537 /*@}*/
Kojto 90:cb3d968589d8 538
Kojto 90:cb3d968589d8 539 /*******************************************************************************
Kojto 90:cb3d968589d8 540 * HW_LPTMR_CNR - Low Power Timer Counter Register
Kojto 90:cb3d968589d8 541 ******************************************************************************/
Kojto 90:cb3d968589d8 542
Kojto 90:cb3d968589d8 543 /*!
Kojto 90:cb3d968589d8 544 * @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW)
Kojto 90:cb3d968589d8 545 *
Kojto 90:cb3d968589d8 546 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 547 */
Kojto 90:cb3d968589d8 548 typedef union _hw_lptmr_cnr
Kojto 90:cb3d968589d8 549 {
Kojto 90:cb3d968589d8 550 uint32_t U;
Kojto 90:cb3d968589d8 551 struct _hw_lptmr_cnr_bitfields
Kojto 90:cb3d968589d8 552 {
Kojto 90:cb3d968589d8 553 uint32_t COUNTER : 16; /*!< [15:0] Counter Value */
Kojto 90:cb3d968589d8 554 uint32_t RESERVED0 : 16; /*!< [31:16] */
Kojto 90:cb3d968589d8 555 } B;
Kojto 90:cb3d968589d8 556 } hw_lptmr_cnr_t;
Kojto 90:cb3d968589d8 557
Kojto 90:cb3d968589d8 558 /*!
Kojto 90:cb3d968589d8 559 * @name Constants and macros for entire LPTMR_CNR register
Kojto 90:cb3d968589d8 560 */
Kojto 90:cb3d968589d8 561 /*@{*/
Kojto 90:cb3d968589d8 562 #define HW_LPTMR_CNR_ADDR(x) ((x) + 0xCU)
Kojto 90:cb3d968589d8 563
Kojto 90:cb3d968589d8 564 #define HW_LPTMR_CNR(x) (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR(x))
Kojto 90:cb3d968589d8 565 #define HW_LPTMR_CNR_RD(x) (HW_LPTMR_CNR(x).U)
Kojto 90:cb3d968589d8 566 #define HW_LPTMR_CNR_WR(x, v) (HW_LPTMR_CNR(x).U = (v))
Kojto 90:cb3d968589d8 567 #define HW_LPTMR_CNR_SET(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) | (v)))
Kojto 90:cb3d968589d8 568 #define HW_LPTMR_CNR_CLR(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 569 #define HW_LPTMR_CNR_TOG(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 570 /*@}*/
Kojto 90:cb3d968589d8 571
Kojto 90:cb3d968589d8 572 /*
Kojto 90:cb3d968589d8 573 * Constants & macros for individual LPTMR_CNR bitfields
Kojto 90:cb3d968589d8 574 */
Kojto 90:cb3d968589d8 575
Kojto 90:cb3d968589d8 576 /*!
Kojto 90:cb3d968589d8 577 * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
Kojto 90:cb3d968589d8 578 */
Kojto 90:cb3d968589d8 579 /*@{*/
Kojto 90:cb3d968589d8 580 #define BP_LPTMR_CNR_COUNTER (0U) /*!< Bit position for LPTMR_CNR_COUNTER. */
Kojto 90:cb3d968589d8 581 #define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) /*!< Bit mask for LPTMR_CNR_COUNTER. */
Kojto 90:cb3d968589d8 582 #define BS_LPTMR_CNR_COUNTER (16U) /*!< Bit field size in bits for LPTMR_CNR_COUNTER. */
Kojto 90:cb3d968589d8 583
Kojto 90:cb3d968589d8 584 /*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
Kojto 90:cb3d968589d8 585 #define BR_LPTMR_CNR_COUNTER(x) (HW_LPTMR_CNR(x).B.COUNTER)
Kojto 90:cb3d968589d8 586
Kojto 90:cb3d968589d8 587 /*! @brief Format value for bitfield LPTMR_CNR_COUNTER. */
Kojto 90:cb3d968589d8 588 #define BF_LPTMR_CNR_COUNTER(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CNR_COUNTER) & BM_LPTMR_CNR_COUNTER)
Kojto 90:cb3d968589d8 589
Kojto 90:cb3d968589d8 590 /*! @brief Set the COUNTER field to a new value. */
Kojto 90:cb3d968589d8 591 #define BW_LPTMR_CNR_COUNTER(x, v) (HW_LPTMR_CNR_WR(x, (HW_LPTMR_CNR_RD(x) & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v)))
Kojto 90:cb3d968589d8 592 /*@}*/
Kojto 90:cb3d968589d8 593
Kojto 90:cb3d968589d8 594 /*******************************************************************************
Kojto 90:cb3d968589d8 595 * hw_lptmr_t - module struct
Kojto 90:cb3d968589d8 596 ******************************************************************************/
Kojto 90:cb3d968589d8 597 /*!
Kojto 90:cb3d968589d8 598 * @brief All LPTMR module registers.
Kojto 90:cb3d968589d8 599 */
Kojto 90:cb3d968589d8 600 #pragma pack(1)
Kojto 90:cb3d968589d8 601 typedef struct _hw_lptmr
Kojto 90:cb3d968589d8 602 {
Kojto 90:cb3d968589d8 603 __IO hw_lptmr_csr_t CSR; /*!< [0x0] Low Power Timer Control Status Register */
Kojto 90:cb3d968589d8 604 __IO hw_lptmr_psr_t PSR; /*!< [0x4] Low Power Timer Prescale Register */
Kojto 90:cb3d968589d8 605 __IO hw_lptmr_cmr_t CMR; /*!< [0x8] Low Power Timer Compare Register */
Kojto 90:cb3d968589d8 606 __IO hw_lptmr_cnr_t CNR; /*!< [0xC] Low Power Timer Counter Register */
Kojto 90:cb3d968589d8 607 } hw_lptmr_t;
Kojto 90:cb3d968589d8 608 #pragma pack()
Kojto 90:cb3d968589d8 609
Kojto 90:cb3d968589d8 610 /*! @brief Macro to access all LPTMR registers. */
Kojto 90:cb3d968589d8 611 /*! @param x LPTMR module instance base address. */
Kojto 90:cb3d968589d8 612 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 613 * use the '&' operator, like <code>&HW_LPTMR(LPTMR0_BASE)</code>. */
Kojto 90:cb3d968589d8 614 #define HW_LPTMR(x) (*(hw_lptmr_t *)(x))
Kojto 90:cb3d968589d8 615
Kojto 90:cb3d968589d8 616 #endif /* __HW_LPTMR_REGISTERS_H__ */
Kojto 90:cb3d968589d8 617 /* EOF */