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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dma.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:
Kojto
Date:
Tue Oct 28 16:40:41 2014 +0000
Revision:
90:cb3d968589d8
Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_DMA_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_DMA_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 DMA
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * Enhanced direct memory access controller
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_DMA_CR - Control Register
Kojto 90:cb3d968589d8 93 * - HW_DMA_ES - Error Status Register
Kojto 90:cb3d968589d8 94 * - HW_DMA_ERQ - Enable Request Register
Kojto 90:cb3d968589d8 95 * - HW_DMA_EEI - Enable Error Interrupt Register
Kojto 90:cb3d968589d8 96 * - HW_DMA_CEEI - Clear Enable Error Interrupt Register
Kojto 90:cb3d968589d8 97 * - HW_DMA_SEEI - Set Enable Error Interrupt Register
Kojto 90:cb3d968589d8 98 * - HW_DMA_CERQ - Clear Enable Request Register
Kojto 90:cb3d968589d8 99 * - HW_DMA_SERQ - Set Enable Request Register
Kojto 90:cb3d968589d8 100 * - HW_DMA_CDNE - Clear DONE Status Bit Register
Kojto 90:cb3d968589d8 101 * - HW_DMA_SSRT - Set START Bit Register
Kojto 90:cb3d968589d8 102 * - HW_DMA_CERR - Clear Error Register
Kojto 90:cb3d968589d8 103 * - HW_DMA_CINT - Clear Interrupt Request Register
Kojto 90:cb3d968589d8 104 * - HW_DMA_INT - Interrupt Request Register
Kojto 90:cb3d968589d8 105 * - HW_DMA_ERR - Error Register
Kojto 90:cb3d968589d8 106 * - HW_DMA_HRS - Hardware Request Status Register
Kojto 90:cb3d968589d8 107 * - HW_DMA_DCHPRIn - Channel n Priority Register
Kojto 90:cb3d968589d8 108 * - HW_DMA_TCDn_SADDR - TCD Source Address
Kojto 90:cb3d968589d8 109 * - HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
Kojto 90:cb3d968589d8 110 * - HW_DMA_TCDn_ATTR - TCD Transfer Attributes
Kojto 90:cb3d968589d8 111 * - HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
Kojto 90:cb3d968589d8 112 * - HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
Kojto 90:cb3d968589d8 113 * - HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
Kojto 90:cb3d968589d8 114 * - HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
Kojto 90:cb3d968589d8 115 * - HW_DMA_TCDn_DADDR - TCD Destination Address
Kojto 90:cb3d968589d8 116 * - HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
Kojto 90:cb3d968589d8 117 * - HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
Kojto 90:cb3d968589d8 118 * - HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
Kojto 90:cb3d968589d8 119 * - HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
Kojto 90:cb3d968589d8 120 * - HW_DMA_TCDn_CSR - TCD Control and Status
Kojto 90:cb3d968589d8 121 * - HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
Kojto 90:cb3d968589d8 122 * - HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
Kojto 90:cb3d968589d8 123 *
Kojto 90:cb3d968589d8 124 * - hw_dma_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 125 */
Kojto 90:cb3d968589d8 126
Kojto 90:cb3d968589d8 127 #define HW_DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
Kojto 90:cb3d968589d8 128
Kojto 90:cb3d968589d8 129 /*******************************************************************************
Kojto 90:cb3d968589d8 130 * HW_DMA_CR - Control Register
Kojto 90:cb3d968589d8 131 ******************************************************************************/
Kojto 90:cb3d968589d8 132
Kojto 90:cb3d968589d8 133 /*!
Kojto 90:cb3d968589d8 134 * @brief HW_DMA_CR - Control Register (RW)
Kojto 90:cb3d968589d8 135 *
Kojto 90:cb3d968589d8 136 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 137 *
Kojto 90:cb3d968589d8 138 * The CR defines the basic operating configuration of the DMA. Arbitration can
Kojto 90:cb3d968589d8 139 * be configured to use either a fixed-priority or a round-robin scheme. For
Kojto 90:cb3d968589d8 140 * fixed-priority arbitration, the highest priority channel requesting service is
Kojto 90:cb3d968589d8 141 * selected to execute. The channel priority registers assign the priorities; see
Kojto 90:cb3d968589d8 142 * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
Kojto 90:cb3d968589d8 143 * ignored and channels are cycled through (from high to low channel number)
Kojto 90:cb3d968589d8 144 * without regard to priority. For correct operation, writes to the CR register must
Kojto 90:cb3d968589d8 145 * be performed only when the DMA channels are inactive; that is, when
Kojto 90:cb3d968589d8 146 * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
Kojto 90:cb3d968589d8 147 * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
Kojto 90:cb3d968589d8 148 * minor loop completion. When minor loop offsets are enabled, the minor loop
Kojto 90:cb3d968589d8 149 * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
Kojto 90:cb3d968589d8 150 * destination address (TCDn_DADDR), or to both prior to the addresses being
Kojto 90:cb3d968589d8 151 * written back into the TCD. If the major loop is complete, the minor loop offset is
Kojto 90:cb3d968589d8 152 * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
Kojto 90:cb3d968589d8 153 * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
Kojto 90:cb3d968589d8 154 * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
Kojto 90:cb3d968589d8 155 * is used to specify multiple fields: a source enable bit (SMLOE) to specify
Kojto 90:cb3d968589d8 156 * the minor loop offset should be applied to the source address (TCDn_SADDR) upon
Kojto 90:cb3d968589d8 157 * minor loop completion, a destination enable bit (DMLOE) to specify the minor
Kojto 90:cb3d968589d8 158 * loop offset should be applied to the destination address (TCDn_DADDR) upon
Kojto 90:cb3d968589d8 159 * minor loop completion, and the sign extended minor loop offset value (MLOFF). The
Kojto 90:cb3d968589d8 160 * same offset value (MLOFF) is used for both source and destination minor loop
Kojto 90:cb3d968589d8 161 * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
Kojto 90:cb3d968589d8 162 * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
Kojto 90:cb3d968589d8 163 * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
Kojto 90:cb3d968589d8 164 * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
Kojto 90:cb3d968589d8 165 * assigned to the NBYTES field.
Kojto 90:cb3d968589d8 166 */
Kojto 90:cb3d968589d8 167 typedef union _hw_dma_cr
Kojto 90:cb3d968589d8 168 {
Kojto 90:cb3d968589d8 169 uint32_t U;
Kojto 90:cb3d968589d8 170 struct _hw_dma_cr_bitfields
Kojto 90:cb3d968589d8 171 {
Kojto 90:cb3d968589d8 172 uint32_t RESERVED0 : 1; /*!< [0] Reserved. */
Kojto 90:cb3d968589d8 173 uint32_t EDBG : 1; /*!< [1] Enable Debug */
Kojto 90:cb3d968589d8 174 uint32_t ERCA : 1; /*!< [2] Enable Round Robin Channel Arbitration */
Kojto 90:cb3d968589d8 175 uint32_t RESERVED1 : 1; /*!< [3] Reserved. */
Kojto 90:cb3d968589d8 176 uint32_t HOE : 1; /*!< [4] Halt On Error */
Kojto 90:cb3d968589d8 177 uint32_t HALT : 1; /*!< [5] Halt DMA Operations */
Kojto 90:cb3d968589d8 178 uint32_t CLM : 1; /*!< [6] Continuous Link Mode */
Kojto 90:cb3d968589d8 179 uint32_t EMLM : 1; /*!< [7] Enable Minor Loop Mapping */
Kojto 90:cb3d968589d8 180 uint32_t RESERVED2 : 8; /*!< [15:8] */
Kojto 90:cb3d968589d8 181 uint32_t ECX : 1; /*!< [16] Error Cancel Transfer */
Kojto 90:cb3d968589d8 182 uint32_t CX : 1; /*!< [17] Cancel Transfer */
Kojto 90:cb3d968589d8 183 uint32_t RESERVED3 : 14; /*!< [31:18] */
Kojto 90:cb3d968589d8 184 } B;
Kojto 90:cb3d968589d8 185 } hw_dma_cr_t;
Kojto 90:cb3d968589d8 186
Kojto 90:cb3d968589d8 187 /*!
Kojto 90:cb3d968589d8 188 * @name Constants and macros for entire DMA_CR register
Kojto 90:cb3d968589d8 189 */
Kojto 90:cb3d968589d8 190 /*@{*/
Kojto 90:cb3d968589d8 191 #define HW_DMA_CR_ADDR(x) ((x) + 0x0U)
Kojto 90:cb3d968589d8 192
Kojto 90:cb3d968589d8 193 #define HW_DMA_CR(x) (*(__IO hw_dma_cr_t *) HW_DMA_CR_ADDR(x))
Kojto 90:cb3d968589d8 194 #define HW_DMA_CR_RD(x) (HW_DMA_CR(x).U)
Kojto 90:cb3d968589d8 195 #define HW_DMA_CR_WR(x, v) (HW_DMA_CR(x).U = (v))
Kojto 90:cb3d968589d8 196 #define HW_DMA_CR_SET(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) | (v)))
Kojto 90:cb3d968589d8 197 #define HW_DMA_CR_CLR(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 198 #define HW_DMA_CR_TOG(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 199 /*@}*/
Kojto 90:cb3d968589d8 200
Kojto 90:cb3d968589d8 201 /*
Kojto 90:cb3d968589d8 202 * Constants & macros for individual DMA_CR bitfields
Kojto 90:cb3d968589d8 203 */
Kojto 90:cb3d968589d8 204
Kojto 90:cb3d968589d8 205 /*!
Kojto 90:cb3d968589d8 206 * @name Register DMA_CR, field EDBG[1] (RW)
Kojto 90:cb3d968589d8 207 *
Kojto 90:cb3d968589d8 208 * Values:
Kojto 90:cb3d968589d8 209 * - 0 - When in debug mode, the DMA continues to operate.
Kojto 90:cb3d968589d8 210 * - 1 - When in debug mode, the DMA stalls the start of a new channel.
Kojto 90:cb3d968589d8 211 * Executing channels are allowed to complete. Channel execution resumes when the
Kojto 90:cb3d968589d8 212 * system exits debug mode or the EDBG bit is cleared.
Kojto 90:cb3d968589d8 213 */
Kojto 90:cb3d968589d8 214 /*@{*/
Kojto 90:cb3d968589d8 215 #define BP_DMA_CR_EDBG (1U) /*!< Bit position for DMA_CR_EDBG. */
Kojto 90:cb3d968589d8 216 #define BM_DMA_CR_EDBG (0x00000002U) /*!< Bit mask for DMA_CR_EDBG. */
Kojto 90:cb3d968589d8 217 #define BS_DMA_CR_EDBG (1U) /*!< Bit field size in bits for DMA_CR_EDBG. */
Kojto 90:cb3d968589d8 218
Kojto 90:cb3d968589d8 219 /*! @brief Read current value of the DMA_CR_EDBG field. */
Kojto 90:cb3d968589d8 220 #define BR_DMA_CR_EDBG(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG))
Kojto 90:cb3d968589d8 221
Kojto 90:cb3d968589d8 222 /*! @brief Format value for bitfield DMA_CR_EDBG. */
Kojto 90:cb3d968589d8 223 #define BF_DMA_CR_EDBG(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EDBG) & BM_DMA_CR_EDBG)
Kojto 90:cb3d968589d8 224
Kojto 90:cb3d968589d8 225 /*! @brief Set the EDBG field to a new value. */
Kojto 90:cb3d968589d8 226 #define BW_DMA_CR_EDBG(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG) = (v))
Kojto 90:cb3d968589d8 227 /*@}*/
Kojto 90:cb3d968589d8 228
Kojto 90:cb3d968589d8 229 /*!
Kojto 90:cb3d968589d8 230 * @name Register DMA_CR, field ERCA[2] (RW)
Kojto 90:cb3d968589d8 231 *
Kojto 90:cb3d968589d8 232 * Values:
Kojto 90:cb3d968589d8 233 * - 0 - Fixed priority arbitration is used for channel selection .
Kojto 90:cb3d968589d8 234 * - 1 - Round robin arbitration is used for channel selection .
Kojto 90:cb3d968589d8 235 */
Kojto 90:cb3d968589d8 236 /*@{*/
Kojto 90:cb3d968589d8 237 #define BP_DMA_CR_ERCA (2U) /*!< Bit position for DMA_CR_ERCA. */
Kojto 90:cb3d968589d8 238 #define BM_DMA_CR_ERCA (0x00000004U) /*!< Bit mask for DMA_CR_ERCA. */
Kojto 90:cb3d968589d8 239 #define BS_DMA_CR_ERCA (1U) /*!< Bit field size in bits for DMA_CR_ERCA. */
Kojto 90:cb3d968589d8 240
Kojto 90:cb3d968589d8 241 /*! @brief Read current value of the DMA_CR_ERCA field. */
Kojto 90:cb3d968589d8 242 #define BR_DMA_CR_ERCA(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA))
Kojto 90:cb3d968589d8 243
Kojto 90:cb3d968589d8 244 /*! @brief Format value for bitfield DMA_CR_ERCA. */
Kojto 90:cb3d968589d8 245 #define BF_DMA_CR_ERCA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ERCA) & BM_DMA_CR_ERCA)
Kojto 90:cb3d968589d8 246
Kojto 90:cb3d968589d8 247 /*! @brief Set the ERCA field to a new value. */
Kojto 90:cb3d968589d8 248 #define BW_DMA_CR_ERCA(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA) = (v))
Kojto 90:cb3d968589d8 249 /*@}*/
Kojto 90:cb3d968589d8 250
Kojto 90:cb3d968589d8 251 /*!
Kojto 90:cb3d968589d8 252 * @name Register DMA_CR, field HOE[4] (RW)
Kojto 90:cb3d968589d8 253 *
Kojto 90:cb3d968589d8 254 * Values:
Kojto 90:cb3d968589d8 255 * - 0 - Normal operation
Kojto 90:cb3d968589d8 256 * - 1 - Any error causes the HALT bit to set. Subsequently, all service
Kojto 90:cb3d968589d8 257 * requests are ignored until the HALT bit is cleared.
Kojto 90:cb3d968589d8 258 */
Kojto 90:cb3d968589d8 259 /*@{*/
Kojto 90:cb3d968589d8 260 #define BP_DMA_CR_HOE (4U) /*!< Bit position for DMA_CR_HOE. */
Kojto 90:cb3d968589d8 261 #define BM_DMA_CR_HOE (0x00000010U) /*!< Bit mask for DMA_CR_HOE. */
Kojto 90:cb3d968589d8 262 #define BS_DMA_CR_HOE (1U) /*!< Bit field size in bits for DMA_CR_HOE. */
Kojto 90:cb3d968589d8 263
Kojto 90:cb3d968589d8 264 /*! @brief Read current value of the DMA_CR_HOE field. */
Kojto 90:cb3d968589d8 265 #define BR_DMA_CR_HOE(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE))
Kojto 90:cb3d968589d8 266
Kojto 90:cb3d968589d8 267 /*! @brief Format value for bitfield DMA_CR_HOE. */
Kojto 90:cb3d968589d8 268 #define BF_DMA_CR_HOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HOE) & BM_DMA_CR_HOE)
Kojto 90:cb3d968589d8 269
Kojto 90:cb3d968589d8 270 /*! @brief Set the HOE field to a new value. */
Kojto 90:cb3d968589d8 271 #define BW_DMA_CR_HOE(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE) = (v))
Kojto 90:cb3d968589d8 272 /*@}*/
Kojto 90:cb3d968589d8 273
Kojto 90:cb3d968589d8 274 /*!
Kojto 90:cb3d968589d8 275 * @name Register DMA_CR, field HALT[5] (RW)
Kojto 90:cb3d968589d8 276 *
Kojto 90:cb3d968589d8 277 * Values:
Kojto 90:cb3d968589d8 278 * - 0 - Normal operation
Kojto 90:cb3d968589d8 279 * - 1 - Stall the start of any new channels. Executing channels are allowed to
Kojto 90:cb3d968589d8 280 * complete. Channel execution resumes when this bit is cleared.
Kojto 90:cb3d968589d8 281 */
Kojto 90:cb3d968589d8 282 /*@{*/
Kojto 90:cb3d968589d8 283 #define BP_DMA_CR_HALT (5U) /*!< Bit position for DMA_CR_HALT. */
Kojto 90:cb3d968589d8 284 #define BM_DMA_CR_HALT (0x00000020U) /*!< Bit mask for DMA_CR_HALT. */
Kojto 90:cb3d968589d8 285 #define BS_DMA_CR_HALT (1U) /*!< Bit field size in bits for DMA_CR_HALT. */
Kojto 90:cb3d968589d8 286
Kojto 90:cb3d968589d8 287 /*! @brief Read current value of the DMA_CR_HALT field. */
Kojto 90:cb3d968589d8 288 #define BR_DMA_CR_HALT(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT))
Kojto 90:cb3d968589d8 289
Kojto 90:cb3d968589d8 290 /*! @brief Format value for bitfield DMA_CR_HALT. */
Kojto 90:cb3d968589d8 291 #define BF_DMA_CR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HALT) & BM_DMA_CR_HALT)
Kojto 90:cb3d968589d8 292
Kojto 90:cb3d968589d8 293 /*! @brief Set the HALT field to a new value. */
Kojto 90:cb3d968589d8 294 #define BW_DMA_CR_HALT(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT) = (v))
Kojto 90:cb3d968589d8 295 /*@}*/
Kojto 90:cb3d968589d8 296
Kojto 90:cb3d968589d8 297 /*!
Kojto 90:cb3d968589d8 298 * @name Register DMA_CR, field CLM[6] (RW)
Kojto 90:cb3d968589d8 299 *
Kojto 90:cb3d968589d8 300 * Values:
Kojto 90:cb3d968589d8 301 * - 0 - A minor loop channel link made to itself goes through channel
Kojto 90:cb3d968589d8 302 * arbitration before being activated again.
Kojto 90:cb3d968589d8 303 * - 1 - A minor loop channel link made to itself does not go through channel
Kojto 90:cb3d968589d8 304 * arbitration before being activated again. Upon minor loop completion, the
Kojto 90:cb3d968589d8 305 * channel activates again if that channel has a minor loop channel link
Kojto 90:cb3d968589d8 306 * enabled and the link channel is itself. This effectively applies the minor loop
Kojto 90:cb3d968589d8 307 * offsets and restarts the next minor loop.
Kojto 90:cb3d968589d8 308 */
Kojto 90:cb3d968589d8 309 /*@{*/
Kojto 90:cb3d968589d8 310 #define BP_DMA_CR_CLM (6U) /*!< Bit position for DMA_CR_CLM. */
Kojto 90:cb3d968589d8 311 #define BM_DMA_CR_CLM (0x00000040U) /*!< Bit mask for DMA_CR_CLM. */
Kojto 90:cb3d968589d8 312 #define BS_DMA_CR_CLM (1U) /*!< Bit field size in bits for DMA_CR_CLM. */
Kojto 90:cb3d968589d8 313
Kojto 90:cb3d968589d8 314 /*! @brief Read current value of the DMA_CR_CLM field. */
Kojto 90:cb3d968589d8 315 #define BR_DMA_CR_CLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM))
Kojto 90:cb3d968589d8 316
Kojto 90:cb3d968589d8 317 /*! @brief Format value for bitfield DMA_CR_CLM. */
Kojto 90:cb3d968589d8 318 #define BF_DMA_CR_CLM(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CLM) & BM_DMA_CR_CLM)
Kojto 90:cb3d968589d8 319
Kojto 90:cb3d968589d8 320 /*! @brief Set the CLM field to a new value. */
Kojto 90:cb3d968589d8 321 #define BW_DMA_CR_CLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM) = (v))
Kojto 90:cb3d968589d8 322 /*@}*/
Kojto 90:cb3d968589d8 323
Kojto 90:cb3d968589d8 324 /*!
Kojto 90:cb3d968589d8 325 * @name Register DMA_CR, field EMLM[7] (RW)
Kojto 90:cb3d968589d8 326 *
Kojto 90:cb3d968589d8 327 * Values:
Kojto 90:cb3d968589d8 328 * - 0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
Kojto 90:cb3d968589d8 329 * - 1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
Kojto 90:cb3d968589d8 330 * an offset field, and the NBYTES field. The individual enable fields allow
Kojto 90:cb3d968589d8 331 * the minor loop offset to be applied to the source address, the destination
Kojto 90:cb3d968589d8 332 * address, or both. The NBYTES field is reduced when either offset is
Kojto 90:cb3d968589d8 333 * enabled.
Kojto 90:cb3d968589d8 334 */
Kojto 90:cb3d968589d8 335 /*@{*/
Kojto 90:cb3d968589d8 336 #define BP_DMA_CR_EMLM (7U) /*!< Bit position for DMA_CR_EMLM. */
Kojto 90:cb3d968589d8 337 #define BM_DMA_CR_EMLM (0x00000080U) /*!< Bit mask for DMA_CR_EMLM. */
Kojto 90:cb3d968589d8 338 #define BS_DMA_CR_EMLM (1U) /*!< Bit field size in bits for DMA_CR_EMLM. */
Kojto 90:cb3d968589d8 339
Kojto 90:cb3d968589d8 340 /*! @brief Read current value of the DMA_CR_EMLM field. */
Kojto 90:cb3d968589d8 341 #define BR_DMA_CR_EMLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM))
Kojto 90:cb3d968589d8 342
Kojto 90:cb3d968589d8 343 /*! @brief Format value for bitfield DMA_CR_EMLM. */
Kojto 90:cb3d968589d8 344 #define BF_DMA_CR_EMLM(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EMLM) & BM_DMA_CR_EMLM)
Kojto 90:cb3d968589d8 345
Kojto 90:cb3d968589d8 346 /*! @brief Set the EMLM field to a new value. */
Kojto 90:cb3d968589d8 347 #define BW_DMA_CR_EMLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM) = (v))
Kojto 90:cb3d968589d8 348 /*@}*/
Kojto 90:cb3d968589d8 349
Kojto 90:cb3d968589d8 350 /*!
Kojto 90:cb3d968589d8 351 * @name Register DMA_CR, field ECX[16] (RW)
Kojto 90:cb3d968589d8 352 *
Kojto 90:cb3d968589d8 353 * Values:
Kojto 90:cb3d968589d8 354 * - 0 - Normal operation
Kojto 90:cb3d968589d8 355 * - 1 - Cancel the remaining data transfer in the same fashion as the CX bit.
Kojto 90:cb3d968589d8 356 * Stop the executing channel and force the minor loop to finish. The cancel
Kojto 90:cb3d968589d8 357 * takes effect after the last write of the current read/write sequence. The
Kojto 90:cb3d968589d8 358 * ECX bit clears itself after the cancel is honored. In addition to
Kojto 90:cb3d968589d8 359 * cancelling the transfer, ECX treats the cancel as an error condition, thus updating
Kojto 90:cb3d968589d8 360 * the Error Status register (DMAx_ES) and generating an optional error
Kojto 90:cb3d968589d8 361 * interrupt.
Kojto 90:cb3d968589d8 362 */
Kojto 90:cb3d968589d8 363 /*@{*/
Kojto 90:cb3d968589d8 364 #define BP_DMA_CR_ECX (16U) /*!< Bit position for DMA_CR_ECX. */
Kojto 90:cb3d968589d8 365 #define BM_DMA_CR_ECX (0x00010000U) /*!< Bit mask for DMA_CR_ECX. */
Kojto 90:cb3d968589d8 366 #define BS_DMA_CR_ECX (1U) /*!< Bit field size in bits for DMA_CR_ECX. */
Kojto 90:cb3d968589d8 367
Kojto 90:cb3d968589d8 368 /*! @brief Read current value of the DMA_CR_ECX field. */
Kojto 90:cb3d968589d8 369 #define BR_DMA_CR_ECX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX))
Kojto 90:cb3d968589d8 370
Kojto 90:cb3d968589d8 371 /*! @brief Format value for bitfield DMA_CR_ECX. */
Kojto 90:cb3d968589d8 372 #define BF_DMA_CR_ECX(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ECX) & BM_DMA_CR_ECX)
Kojto 90:cb3d968589d8 373
Kojto 90:cb3d968589d8 374 /*! @brief Set the ECX field to a new value. */
Kojto 90:cb3d968589d8 375 #define BW_DMA_CR_ECX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX) = (v))
Kojto 90:cb3d968589d8 376 /*@}*/
Kojto 90:cb3d968589d8 377
Kojto 90:cb3d968589d8 378 /*!
Kojto 90:cb3d968589d8 379 * @name Register DMA_CR, field CX[17] (RW)
Kojto 90:cb3d968589d8 380 *
Kojto 90:cb3d968589d8 381 * Values:
Kojto 90:cb3d968589d8 382 * - 0 - Normal operation
Kojto 90:cb3d968589d8 383 * - 1 - Cancel the remaining data transfer. Stop the executing channel and
Kojto 90:cb3d968589d8 384 * force the minor loop to finish. The cancel takes effect after the last write
Kojto 90:cb3d968589d8 385 * of the current read/write sequence. The CX bit clears itself after the
Kojto 90:cb3d968589d8 386 * cancel has been honored. This cancel retires the channel normally as if the
Kojto 90:cb3d968589d8 387 * minor loop was completed.
Kojto 90:cb3d968589d8 388 */
Kojto 90:cb3d968589d8 389 /*@{*/
Kojto 90:cb3d968589d8 390 #define BP_DMA_CR_CX (17U) /*!< Bit position for DMA_CR_CX. */
Kojto 90:cb3d968589d8 391 #define BM_DMA_CR_CX (0x00020000U) /*!< Bit mask for DMA_CR_CX. */
Kojto 90:cb3d968589d8 392 #define BS_DMA_CR_CX (1U) /*!< Bit field size in bits for DMA_CR_CX. */
Kojto 90:cb3d968589d8 393
Kojto 90:cb3d968589d8 394 /*! @brief Read current value of the DMA_CR_CX field. */
Kojto 90:cb3d968589d8 395 #define BR_DMA_CR_CX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX))
Kojto 90:cb3d968589d8 396
Kojto 90:cb3d968589d8 397 /*! @brief Format value for bitfield DMA_CR_CX. */
Kojto 90:cb3d968589d8 398 #define BF_DMA_CR_CX(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CX) & BM_DMA_CR_CX)
Kojto 90:cb3d968589d8 399
Kojto 90:cb3d968589d8 400 /*! @brief Set the CX field to a new value. */
Kojto 90:cb3d968589d8 401 #define BW_DMA_CR_CX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX) = (v))
Kojto 90:cb3d968589d8 402 /*@}*/
Kojto 90:cb3d968589d8 403
Kojto 90:cb3d968589d8 404 /*******************************************************************************
Kojto 90:cb3d968589d8 405 * HW_DMA_ES - Error Status Register
Kojto 90:cb3d968589d8 406 ******************************************************************************/
Kojto 90:cb3d968589d8 407
Kojto 90:cb3d968589d8 408 /*!
Kojto 90:cb3d968589d8 409 * @brief HW_DMA_ES - Error Status Register (RO)
Kojto 90:cb3d968589d8 410 *
Kojto 90:cb3d968589d8 411 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 412 *
Kojto 90:cb3d968589d8 413 * The ES provides information concerning the last recorded channel error.
Kojto 90:cb3d968589d8 414 * Channel errors can be caused by: A configuration error, that is: An illegal setting
Kojto 90:cb3d968589d8 415 * in the transfer-control descriptor, or An illegal priority register setting
Kojto 90:cb3d968589d8 416 * in fixed-arbitration An error termination to a bus master read or write cycle
Kojto 90:cb3d968589d8 417 * See the Error Reporting and Handling section for more details.
Kojto 90:cb3d968589d8 418 */
Kojto 90:cb3d968589d8 419 typedef union _hw_dma_es
Kojto 90:cb3d968589d8 420 {
Kojto 90:cb3d968589d8 421 uint32_t U;
Kojto 90:cb3d968589d8 422 struct _hw_dma_es_bitfields
Kojto 90:cb3d968589d8 423 {
Kojto 90:cb3d968589d8 424 uint32_t DBE : 1; /*!< [0] Destination Bus Error */
Kojto 90:cb3d968589d8 425 uint32_t SBE : 1; /*!< [1] Source Bus Error */
Kojto 90:cb3d968589d8 426 uint32_t SGE : 1; /*!< [2] Scatter/Gather Configuration Error */
Kojto 90:cb3d968589d8 427 uint32_t NCE : 1; /*!< [3] NBYTES/CITER Configuration Error */
Kojto 90:cb3d968589d8 428 uint32_t DOE : 1; /*!< [4] Destination Offset Error */
Kojto 90:cb3d968589d8 429 uint32_t DAE : 1; /*!< [5] Destination Address Error */
Kojto 90:cb3d968589d8 430 uint32_t SOE : 1; /*!< [6] Source Offset Error */
Kojto 90:cb3d968589d8 431 uint32_t SAE : 1; /*!< [7] Source Address Error */
Kojto 90:cb3d968589d8 432 uint32_t ERRCHN : 4; /*!< [11:8] Error Channel Number or Canceled
Kojto 90:cb3d968589d8 433 * Channel Number */
Kojto 90:cb3d968589d8 434 uint32_t RESERVED0 : 2; /*!< [13:12] */
Kojto 90:cb3d968589d8 435 uint32_t CPE : 1; /*!< [14] Channel Priority Error */
Kojto 90:cb3d968589d8 436 uint32_t RESERVED1 : 1; /*!< [15] */
Kojto 90:cb3d968589d8 437 uint32_t ECX : 1; /*!< [16] Transfer Canceled */
Kojto 90:cb3d968589d8 438 uint32_t RESERVED2 : 14; /*!< [30:17] */
Kojto 90:cb3d968589d8 439 uint32_t VLD : 1; /*!< [31] */
Kojto 90:cb3d968589d8 440 } B;
Kojto 90:cb3d968589d8 441 } hw_dma_es_t;
Kojto 90:cb3d968589d8 442
Kojto 90:cb3d968589d8 443 /*!
Kojto 90:cb3d968589d8 444 * @name Constants and macros for entire DMA_ES register
Kojto 90:cb3d968589d8 445 */
Kojto 90:cb3d968589d8 446 /*@{*/
Kojto 90:cb3d968589d8 447 #define HW_DMA_ES_ADDR(x) ((x) + 0x4U)
Kojto 90:cb3d968589d8 448
Kojto 90:cb3d968589d8 449 #define HW_DMA_ES(x) (*(__I hw_dma_es_t *) HW_DMA_ES_ADDR(x))
Kojto 90:cb3d968589d8 450 #define HW_DMA_ES_RD(x) (HW_DMA_ES(x).U)
Kojto 90:cb3d968589d8 451 /*@}*/
Kojto 90:cb3d968589d8 452
Kojto 90:cb3d968589d8 453 /*
Kojto 90:cb3d968589d8 454 * Constants & macros for individual DMA_ES bitfields
Kojto 90:cb3d968589d8 455 */
Kojto 90:cb3d968589d8 456
Kojto 90:cb3d968589d8 457 /*!
Kojto 90:cb3d968589d8 458 * @name Register DMA_ES, field DBE[0] (RO)
Kojto 90:cb3d968589d8 459 *
Kojto 90:cb3d968589d8 460 * Values:
Kojto 90:cb3d968589d8 461 * - 0 - No destination bus error
Kojto 90:cb3d968589d8 462 * - 1 - The last recorded error was a bus error on a destination write
Kojto 90:cb3d968589d8 463 */
Kojto 90:cb3d968589d8 464 /*@{*/
Kojto 90:cb3d968589d8 465 #define BP_DMA_ES_DBE (0U) /*!< Bit position for DMA_ES_DBE. */
Kojto 90:cb3d968589d8 466 #define BM_DMA_ES_DBE (0x00000001U) /*!< Bit mask for DMA_ES_DBE. */
Kojto 90:cb3d968589d8 467 #define BS_DMA_ES_DBE (1U) /*!< Bit field size in bits for DMA_ES_DBE. */
Kojto 90:cb3d968589d8 468
Kojto 90:cb3d968589d8 469 /*! @brief Read current value of the DMA_ES_DBE field. */
Kojto 90:cb3d968589d8 470 #define BR_DMA_ES_DBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DBE))
Kojto 90:cb3d968589d8 471 /*@}*/
Kojto 90:cb3d968589d8 472
Kojto 90:cb3d968589d8 473 /*!
Kojto 90:cb3d968589d8 474 * @name Register DMA_ES, field SBE[1] (RO)
Kojto 90:cb3d968589d8 475 *
Kojto 90:cb3d968589d8 476 * Values:
Kojto 90:cb3d968589d8 477 * - 0 - No source bus error
Kojto 90:cb3d968589d8 478 * - 1 - The last recorded error was a bus error on a source read
Kojto 90:cb3d968589d8 479 */
Kojto 90:cb3d968589d8 480 /*@{*/
Kojto 90:cb3d968589d8 481 #define BP_DMA_ES_SBE (1U) /*!< Bit position for DMA_ES_SBE. */
Kojto 90:cb3d968589d8 482 #define BM_DMA_ES_SBE (0x00000002U) /*!< Bit mask for DMA_ES_SBE. */
Kojto 90:cb3d968589d8 483 #define BS_DMA_ES_SBE (1U) /*!< Bit field size in bits for DMA_ES_SBE. */
Kojto 90:cb3d968589d8 484
Kojto 90:cb3d968589d8 485 /*! @brief Read current value of the DMA_ES_SBE field. */
Kojto 90:cb3d968589d8 486 #define BR_DMA_ES_SBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SBE))
Kojto 90:cb3d968589d8 487 /*@}*/
Kojto 90:cb3d968589d8 488
Kojto 90:cb3d968589d8 489 /*!
Kojto 90:cb3d968589d8 490 * @name Register DMA_ES, field SGE[2] (RO)
Kojto 90:cb3d968589d8 491 *
Kojto 90:cb3d968589d8 492 * Values:
Kojto 90:cb3d968589d8 493 * - 0 - No scatter/gather configuration error
Kojto 90:cb3d968589d8 494 * - 1 - The last recorded error was a configuration error detected in the
Kojto 90:cb3d968589d8 495 * TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather
Kojto 90:cb3d968589d8 496 * operation after major loop completion if TCDn_CSR[ESG] is enabled.
Kojto 90:cb3d968589d8 497 * TCDn_DLASTSGA is not on a 32 byte boundary.
Kojto 90:cb3d968589d8 498 */
Kojto 90:cb3d968589d8 499 /*@{*/
Kojto 90:cb3d968589d8 500 #define BP_DMA_ES_SGE (2U) /*!< Bit position for DMA_ES_SGE. */
Kojto 90:cb3d968589d8 501 #define BM_DMA_ES_SGE (0x00000004U) /*!< Bit mask for DMA_ES_SGE. */
Kojto 90:cb3d968589d8 502 #define BS_DMA_ES_SGE (1U) /*!< Bit field size in bits for DMA_ES_SGE. */
Kojto 90:cb3d968589d8 503
Kojto 90:cb3d968589d8 504 /*! @brief Read current value of the DMA_ES_SGE field. */
Kojto 90:cb3d968589d8 505 #define BR_DMA_ES_SGE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SGE))
Kojto 90:cb3d968589d8 506 /*@}*/
Kojto 90:cb3d968589d8 507
Kojto 90:cb3d968589d8 508 /*!
Kojto 90:cb3d968589d8 509 * @name Register DMA_ES, field NCE[3] (RO)
Kojto 90:cb3d968589d8 510 *
Kojto 90:cb3d968589d8 511 * Values:
Kojto 90:cb3d968589d8 512 * - 0 - No NBYTES/CITER configuration error
Kojto 90:cb3d968589d8 513 * - 1 - The last recorded error was a configuration error detected in the
Kojto 90:cb3d968589d8 514 * TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
Kojto 90:cb3d968589d8 515 * TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
Kojto 90:cb3d968589d8 516 * TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
Kojto 90:cb3d968589d8 517 */
Kojto 90:cb3d968589d8 518 /*@{*/
Kojto 90:cb3d968589d8 519 #define BP_DMA_ES_NCE (3U) /*!< Bit position for DMA_ES_NCE. */
Kojto 90:cb3d968589d8 520 #define BM_DMA_ES_NCE (0x00000008U) /*!< Bit mask for DMA_ES_NCE. */
Kojto 90:cb3d968589d8 521 #define BS_DMA_ES_NCE (1U) /*!< Bit field size in bits for DMA_ES_NCE. */
Kojto 90:cb3d968589d8 522
Kojto 90:cb3d968589d8 523 /*! @brief Read current value of the DMA_ES_NCE field. */
Kojto 90:cb3d968589d8 524 #define BR_DMA_ES_NCE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_NCE))
Kojto 90:cb3d968589d8 525 /*@}*/
Kojto 90:cb3d968589d8 526
Kojto 90:cb3d968589d8 527 /*!
Kojto 90:cb3d968589d8 528 * @name Register DMA_ES, field DOE[4] (RO)
Kojto 90:cb3d968589d8 529 *
Kojto 90:cb3d968589d8 530 * Values:
Kojto 90:cb3d968589d8 531 * - 0 - No destination offset configuration error
Kojto 90:cb3d968589d8 532 * - 1 - The last recorded error was a configuration error detected in the
Kojto 90:cb3d968589d8 533 * TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
Kojto 90:cb3d968589d8 534 */
Kojto 90:cb3d968589d8 535 /*@{*/
Kojto 90:cb3d968589d8 536 #define BP_DMA_ES_DOE (4U) /*!< Bit position for DMA_ES_DOE. */
Kojto 90:cb3d968589d8 537 #define BM_DMA_ES_DOE (0x00000010U) /*!< Bit mask for DMA_ES_DOE. */
Kojto 90:cb3d968589d8 538 #define BS_DMA_ES_DOE (1U) /*!< Bit field size in bits for DMA_ES_DOE. */
Kojto 90:cb3d968589d8 539
Kojto 90:cb3d968589d8 540 /*! @brief Read current value of the DMA_ES_DOE field. */
Kojto 90:cb3d968589d8 541 #define BR_DMA_ES_DOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DOE))
Kojto 90:cb3d968589d8 542 /*@}*/
Kojto 90:cb3d968589d8 543
Kojto 90:cb3d968589d8 544 /*!
Kojto 90:cb3d968589d8 545 * @name Register DMA_ES, field DAE[5] (RO)
Kojto 90:cb3d968589d8 546 *
Kojto 90:cb3d968589d8 547 * Values:
Kojto 90:cb3d968589d8 548 * - 0 - No destination address configuration error
Kojto 90:cb3d968589d8 549 * - 1 - The last recorded error was a configuration error detected in the
Kojto 90:cb3d968589d8 550 * TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
Kojto 90:cb3d968589d8 551 */
Kojto 90:cb3d968589d8 552 /*@{*/
Kojto 90:cb3d968589d8 553 #define BP_DMA_ES_DAE (5U) /*!< Bit position for DMA_ES_DAE. */
Kojto 90:cb3d968589d8 554 #define BM_DMA_ES_DAE (0x00000020U) /*!< Bit mask for DMA_ES_DAE. */
Kojto 90:cb3d968589d8 555 #define BS_DMA_ES_DAE (1U) /*!< Bit field size in bits for DMA_ES_DAE. */
Kojto 90:cb3d968589d8 556
Kojto 90:cb3d968589d8 557 /*! @brief Read current value of the DMA_ES_DAE field. */
Kojto 90:cb3d968589d8 558 #define BR_DMA_ES_DAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DAE))
Kojto 90:cb3d968589d8 559 /*@}*/
Kojto 90:cb3d968589d8 560
Kojto 90:cb3d968589d8 561 /*!
Kojto 90:cb3d968589d8 562 * @name Register DMA_ES, field SOE[6] (RO)
Kojto 90:cb3d968589d8 563 *
Kojto 90:cb3d968589d8 564 * Values:
Kojto 90:cb3d968589d8 565 * - 0 - No source offset configuration error
Kojto 90:cb3d968589d8 566 * - 1 - The last recorded error was a configuration error detected in the
Kojto 90:cb3d968589d8 567 * TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
Kojto 90:cb3d968589d8 568 */
Kojto 90:cb3d968589d8 569 /*@{*/
Kojto 90:cb3d968589d8 570 #define BP_DMA_ES_SOE (6U) /*!< Bit position for DMA_ES_SOE. */
Kojto 90:cb3d968589d8 571 #define BM_DMA_ES_SOE (0x00000040U) /*!< Bit mask for DMA_ES_SOE. */
Kojto 90:cb3d968589d8 572 #define BS_DMA_ES_SOE (1U) /*!< Bit field size in bits for DMA_ES_SOE. */
Kojto 90:cb3d968589d8 573
Kojto 90:cb3d968589d8 574 /*! @brief Read current value of the DMA_ES_SOE field. */
Kojto 90:cb3d968589d8 575 #define BR_DMA_ES_SOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SOE))
Kojto 90:cb3d968589d8 576 /*@}*/
Kojto 90:cb3d968589d8 577
Kojto 90:cb3d968589d8 578 /*!
Kojto 90:cb3d968589d8 579 * @name Register DMA_ES, field SAE[7] (RO)
Kojto 90:cb3d968589d8 580 *
Kojto 90:cb3d968589d8 581 * Values:
Kojto 90:cb3d968589d8 582 * - 0 - No source address configuration error.
Kojto 90:cb3d968589d8 583 * - 1 - The last recorded error was a configuration error detected in the
Kojto 90:cb3d968589d8 584 * TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
Kojto 90:cb3d968589d8 585 */
Kojto 90:cb3d968589d8 586 /*@{*/
Kojto 90:cb3d968589d8 587 #define BP_DMA_ES_SAE (7U) /*!< Bit position for DMA_ES_SAE. */
Kojto 90:cb3d968589d8 588 #define BM_DMA_ES_SAE (0x00000080U) /*!< Bit mask for DMA_ES_SAE. */
Kojto 90:cb3d968589d8 589 #define BS_DMA_ES_SAE (1U) /*!< Bit field size in bits for DMA_ES_SAE. */
Kojto 90:cb3d968589d8 590
Kojto 90:cb3d968589d8 591 /*! @brief Read current value of the DMA_ES_SAE field. */
Kojto 90:cb3d968589d8 592 #define BR_DMA_ES_SAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SAE))
Kojto 90:cb3d968589d8 593 /*@}*/
Kojto 90:cb3d968589d8 594
Kojto 90:cb3d968589d8 595 /*!
Kojto 90:cb3d968589d8 596 * @name Register DMA_ES, field ERRCHN[11:8] (RO)
Kojto 90:cb3d968589d8 597 *
Kojto 90:cb3d968589d8 598 * The channel number of the last recorded error (excluding CPE errors) or last
Kojto 90:cb3d968589d8 599 * recorded error canceled transfer.
Kojto 90:cb3d968589d8 600 */
Kojto 90:cb3d968589d8 601 /*@{*/
Kojto 90:cb3d968589d8 602 #define BP_DMA_ES_ERRCHN (8U) /*!< Bit position for DMA_ES_ERRCHN. */
Kojto 90:cb3d968589d8 603 #define BM_DMA_ES_ERRCHN (0x00000F00U) /*!< Bit mask for DMA_ES_ERRCHN. */
Kojto 90:cb3d968589d8 604 #define BS_DMA_ES_ERRCHN (4U) /*!< Bit field size in bits for DMA_ES_ERRCHN. */
Kojto 90:cb3d968589d8 605
Kojto 90:cb3d968589d8 606 /*! @brief Read current value of the DMA_ES_ERRCHN field. */
Kojto 90:cb3d968589d8 607 #define BR_DMA_ES_ERRCHN(x) (HW_DMA_ES(x).B.ERRCHN)
Kojto 90:cb3d968589d8 608 /*@}*/
Kojto 90:cb3d968589d8 609
Kojto 90:cb3d968589d8 610 /*!
Kojto 90:cb3d968589d8 611 * @name Register DMA_ES, field CPE[14] (RO)
Kojto 90:cb3d968589d8 612 *
Kojto 90:cb3d968589d8 613 * Values:
Kojto 90:cb3d968589d8 614 * - 0 - No channel priority error
Kojto 90:cb3d968589d8 615 * - 1 - The last recorded error was a configuration error in the channel
Kojto 90:cb3d968589d8 616 * priorities . Channel priorities are not unique.
Kojto 90:cb3d968589d8 617 */
Kojto 90:cb3d968589d8 618 /*@{*/
Kojto 90:cb3d968589d8 619 #define BP_DMA_ES_CPE (14U) /*!< Bit position for DMA_ES_CPE. */
Kojto 90:cb3d968589d8 620 #define BM_DMA_ES_CPE (0x00004000U) /*!< Bit mask for DMA_ES_CPE. */
Kojto 90:cb3d968589d8 621 #define BS_DMA_ES_CPE (1U) /*!< Bit field size in bits for DMA_ES_CPE. */
Kojto 90:cb3d968589d8 622
Kojto 90:cb3d968589d8 623 /*! @brief Read current value of the DMA_ES_CPE field. */
Kojto 90:cb3d968589d8 624 #define BR_DMA_ES_CPE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_CPE))
Kojto 90:cb3d968589d8 625 /*@}*/
Kojto 90:cb3d968589d8 626
Kojto 90:cb3d968589d8 627 /*!
Kojto 90:cb3d968589d8 628 * @name Register DMA_ES, field ECX[16] (RO)
Kojto 90:cb3d968589d8 629 *
Kojto 90:cb3d968589d8 630 * Values:
Kojto 90:cb3d968589d8 631 * - 0 - No canceled transfers
Kojto 90:cb3d968589d8 632 * - 1 - The last recorded entry was a canceled transfer by the error cancel
Kojto 90:cb3d968589d8 633 * transfer input
Kojto 90:cb3d968589d8 634 */
Kojto 90:cb3d968589d8 635 /*@{*/
Kojto 90:cb3d968589d8 636 #define BP_DMA_ES_ECX (16U) /*!< Bit position for DMA_ES_ECX. */
Kojto 90:cb3d968589d8 637 #define BM_DMA_ES_ECX (0x00010000U) /*!< Bit mask for DMA_ES_ECX. */
Kojto 90:cb3d968589d8 638 #define BS_DMA_ES_ECX (1U) /*!< Bit field size in bits for DMA_ES_ECX. */
Kojto 90:cb3d968589d8 639
Kojto 90:cb3d968589d8 640 /*! @brief Read current value of the DMA_ES_ECX field. */
Kojto 90:cb3d968589d8 641 #define BR_DMA_ES_ECX(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_ECX))
Kojto 90:cb3d968589d8 642 /*@}*/
Kojto 90:cb3d968589d8 643
Kojto 90:cb3d968589d8 644 /*!
Kojto 90:cb3d968589d8 645 * @name Register DMA_ES, field VLD[31] (RO)
Kojto 90:cb3d968589d8 646 *
Kojto 90:cb3d968589d8 647 * Logical OR of all ERR status bits
Kojto 90:cb3d968589d8 648 *
Kojto 90:cb3d968589d8 649 * Values:
Kojto 90:cb3d968589d8 650 * - 0 - No ERR bits are set
Kojto 90:cb3d968589d8 651 * - 1 - At least one ERR bit is set indicating a valid error exists that has
Kojto 90:cb3d968589d8 652 * not been cleared
Kojto 90:cb3d968589d8 653 */
Kojto 90:cb3d968589d8 654 /*@{*/
Kojto 90:cb3d968589d8 655 #define BP_DMA_ES_VLD (31U) /*!< Bit position for DMA_ES_VLD. */
Kojto 90:cb3d968589d8 656 #define BM_DMA_ES_VLD (0x80000000U) /*!< Bit mask for DMA_ES_VLD. */
Kojto 90:cb3d968589d8 657 #define BS_DMA_ES_VLD (1U) /*!< Bit field size in bits for DMA_ES_VLD. */
Kojto 90:cb3d968589d8 658
Kojto 90:cb3d968589d8 659 /*! @brief Read current value of the DMA_ES_VLD field. */
Kojto 90:cb3d968589d8 660 #define BR_DMA_ES_VLD(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_VLD))
Kojto 90:cb3d968589d8 661 /*@}*/
Kojto 90:cb3d968589d8 662
Kojto 90:cb3d968589d8 663 /*******************************************************************************
Kojto 90:cb3d968589d8 664 * HW_DMA_ERQ - Enable Request Register
Kojto 90:cb3d968589d8 665 ******************************************************************************/
Kojto 90:cb3d968589d8 666
Kojto 90:cb3d968589d8 667 /*!
Kojto 90:cb3d968589d8 668 * @brief HW_DMA_ERQ - Enable Request Register (RW)
Kojto 90:cb3d968589d8 669 *
Kojto 90:cb3d968589d8 670 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 671 *
Kojto 90:cb3d968589d8 672 * The ERQ register provides a bit map for the 16 implemented channels to enable
Kojto 90:cb3d968589d8 673 * the request signal for each channel. The state of any given channel enable is
Kojto 90:cb3d968589d8 674 * directly affected by writes to this register; it is also affected by writes
Kojto 90:cb3d968589d8 675 * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
Kojto 90:cb3d968589d8 676 * for a single channel can easily be modified without needing to perform a
Kojto 90:cb3d968589d8 677 * read-modify-write sequence to the ERQ. DMA request input signals and this enable
Kojto 90:cb3d968589d8 678 * request flag must be asserted before a channel's hardware service request is
Kojto 90:cb3d968589d8 679 * accepted. The state of the DMA enable request flag does not affect a channel
Kojto 90:cb3d968589d8 680 * service request made explicitly through software or a linked channel request.
Kojto 90:cb3d968589d8 681 */
Kojto 90:cb3d968589d8 682 typedef union _hw_dma_erq
Kojto 90:cb3d968589d8 683 {
Kojto 90:cb3d968589d8 684 uint32_t U;
Kojto 90:cb3d968589d8 685 struct _hw_dma_erq_bitfields
Kojto 90:cb3d968589d8 686 {
Kojto 90:cb3d968589d8 687 uint32_t ERQ0 : 1; /*!< [0] Enable DMA Request 0 */
Kojto 90:cb3d968589d8 688 uint32_t ERQ1 : 1; /*!< [1] Enable DMA Request 1 */
Kojto 90:cb3d968589d8 689 uint32_t ERQ2 : 1; /*!< [2] Enable DMA Request 2 */
Kojto 90:cb3d968589d8 690 uint32_t ERQ3 : 1; /*!< [3] Enable DMA Request 3 */
Kojto 90:cb3d968589d8 691 uint32_t ERQ4 : 1; /*!< [4] Enable DMA Request 4 */
Kojto 90:cb3d968589d8 692 uint32_t ERQ5 : 1; /*!< [5] Enable DMA Request 5 */
Kojto 90:cb3d968589d8 693 uint32_t ERQ6 : 1; /*!< [6] Enable DMA Request 6 */
Kojto 90:cb3d968589d8 694 uint32_t ERQ7 : 1; /*!< [7] Enable DMA Request 7 */
Kojto 90:cb3d968589d8 695 uint32_t ERQ8 : 1; /*!< [8] Enable DMA Request 8 */
Kojto 90:cb3d968589d8 696 uint32_t ERQ9 : 1; /*!< [9] Enable DMA Request 9 */
Kojto 90:cb3d968589d8 697 uint32_t ERQ10 : 1; /*!< [10] Enable DMA Request 10 */
Kojto 90:cb3d968589d8 698 uint32_t ERQ11 : 1; /*!< [11] Enable DMA Request 11 */
Kojto 90:cb3d968589d8 699 uint32_t ERQ12 : 1; /*!< [12] Enable DMA Request 12 */
Kojto 90:cb3d968589d8 700 uint32_t ERQ13 : 1; /*!< [13] Enable DMA Request 13 */
Kojto 90:cb3d968589d8 701 uint32_t ERQ14 : 1; /*!< [14] Enable DMA Request 14 */
Kojto 90:cb3d968589d8 702 uint32_t ERQ15 : 1; /*!< [15] Enable DMA Request 15 */
Kojto 90:cb3d968589d8 703 uint32_t RESERVED0 : 16; /*!< [31:16] */
Kojto 90:cb3d968589d8 704 } B;
Kojto 90:cb3d968589d8 705 } hw_dma_erq_t;
Kojto 90:cb3d968589d8 706
Kojto 90:cb3d968589d8 707 /*!
Kojto 90:cb3d968589d8 708 * @name Constants and macros for entire DMA_ERQ register
Kojto 90:cb3d968589d8 709 */
Kojto 90:cb3d968589d8 710 /*@{*/
Kojto 90:cb3d968589d8 711 #define HW_DMA_ERQ_ADDR(x) ((x) + 0xCU)
Kojto 90:cb3d968589d8 712
Kojto 90:cb3d968589d8 713 #define HW_DMA_ERQ(x) (*(__IO hw_dma_erq_t *) HW_DMA_ERQ_ADDR(x))
Kojto 90:cb3d968589d8 714 #define HW_DMA_ERQ_RD(x) (HW_DMA_ERQ(x).U)
Kojto 90:cb3d968589d8 715 #define HW_DMA_ERQ_WR(x, v) (HW_DMA_ERQ(x).U = (v))
Kojto 90:cb3d968589d8 716 #define HW_DMA_ERQ_SET(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) | (v)))
Kojto 90:cb3d968589d8 717 #define HW_DMA_ERQ_CLR(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 718 #define HW_DMA_ERQ_TOG(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 719 /*@}*/
Kojto 90:cb3d968589d8 720
Kojto 90:cb3d968589d8 721 /*
Kojto 90:cb3d968589d8 722 * Constants & macros for individual DMA_ERQ bitfields
Kojto 90:cb3d968589d8 723 */
Kojto 90:cb3d968589d8 724
Kojto 90:cb3d968589d8 725 /*!
Kojto 90:cb3d968589d8 726 * @name Register DMA_ERQ, field ERQ0[0] (RW)
Kojto 90:cb3d968589d8 727 *
Kojto 90:cb3d968589d8 728 * Values:
Kojto 90:cb3d968589d8 729 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 730 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 731 */
Kojto 90:cb3d968589d8 732 /*@{*/
Kojto 90:cb3d968589d8 733 #define BP_DMA_ERQ_ERQ0 (0U) /*!< Bit position for DMA_ERQ_ERQ0. */
Kojto 90:cb3d968589d8 734 #define BM_DMA_ERQ_ERQ0 (0x00000001U) /*!< Bit mask for DMA_ERQ_ERQ0. */
Kojto 90:cb3d968589d8 735 #define BS_DMA_ERQ_ERQ0 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ0. */
Kojto 90:cb3d968589d8 736
Kojto 90:cb3d968589d8 737 /*! @brief Read current value of the DMA_ERQ_ERQ0 field. */
Kojto 90:cb3d968589d8 738 #define BR_DMA_ERQ_ERQ0(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0))
Kojto 90:cb3d968589d8 739
Kojto 90:cb3d968589d8 740 /*! @brief Format value for bitfield DMA_ERQ_ERQ0. */
Kojto 90:cb3d968589d8 741 #define BF_DMA_ERQ_ERQ0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ0) & BM_DMA_ERQ_ERQ0)
Kojto 90:cb3d968589d8 742
Kojto 90:cb3d968589d8 743 /*! @brief Set the ERQ0 field to a new value. */
Kojto 90:cb3d968589d8 744 #define BW_DMA_ERQ_ERQ0(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0) = (v))
Kojto 90:cb3d968589d8 745 /*@}*/
Kojto 90:cb3d968589d8 746
Kojto 90:cb3d968589d8 747 /*!
Kojto 90:cb3d968589d8 748 * @name Register DMA_ERQ, field ERQ1[1] (RW)
Kojto 90:cb3d968589d8 749 *
Kojto 90:cb3d968589d8 750 * Values:
Kojto 90:cb3d968589d8 751 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 752 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 753 */
Kojto 90:cb3d968589d8 754 /*@{*/
Kojto 90:cb3d968589d8 755 #define BP_DMA_ERQ_ERQ1 (1U) /*!< Bit position for DMA_ERQ_ERQ1. */
Kojto 90:cb3d968589d8 756 #define BM_DMA_ERQ_ERQ1 (0x00000002U) /*!< Bit mask for DMA_ERQ_ERQ1. */
Kojto 90:cb3d968589d8 757 #define BS_DMA_ERQ_ERQ1 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ1. */
Kojto 90:cb3d968589d8 758
Kojto 90:cb3d968589d8 759 /*! @brief Read current value of the DMA_ERQ_ERQ1 field. */
Kojto 90:cb3d968589d8 760 #define BR_DMA_ERQ_ERQ1(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1))
Kojto 90:cb3d968589d8 761
Kojto 90:cb3d968589d8 762 /*! @brief Format value for bitfield DMA_ERQ_ERQ1. */
Kojto 90:cb3d968589d8 763 #define BF_DMA_ERQ_ERQ1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ1) & BM_DMA_ERQ_ERQ1)
Kojto 90:cb3d968589d8 764
Kojto 90:cb3d968589d8 765 /*! @brief Set the ERQ1 field to a new value. */
Kojto 90:cb3d968589d8 766 #define BW_DMA_ERQ_ERQ1(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1) = (v))
Kojto 90:cb3d968589d8 767 /*@}*/
Kojto 90:cb3d968589d8 768
Kojto 90:cb3d968589d8 769 /*!
Kojto 90:cb3d968589d8 770 * @name Register DMA_ERQ, field ERQ2[2] (RW)
Kojto 90:cb3d968589d8 771 *
Kojto 90:cb3d968589d8 772 * Values:
Kojto 90:cb3d968589d8 773 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 774 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 775 */
Kojto 90:cb3d968589d8 776 /*@{*/
Kojto 90:cb3d968589d8 777 #define BP_DMA_ERQ_ERQ2 (2U) /*!< Bit position for DMA_ERQ_ERQ2. */
Kojto 90:cb3d968589d8 778 #define BM_DMA_ERQ_ERQ2 (0x00000004U) /*!< Bit mask for DMA_ERQ_ERQ2. */
Kojto 90:cb3d968589d8 779 #define BS_DMA_ERQ_ERQ2 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ2. */
Kojto 90:cb3d968589d8 780
Kojto 90:cb3d968589d8 781 /*! @brief Read current value of the DMA_ERQ_ERQ2 field. */
Kojto 90:cb3d968589d8 782 #define BR_DMA_ERQ_ERQ2(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2))
Kojto 90:cb3d968589d8 783
Kojto 90:cb3d968589d8 784 /*! @brief Format value for bitfield DMA_ERQ_ERQ2. */
Kojto 90:cb3d968589d8 785 #define BF_DMA_ERQ_ERQ2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ2) & BM_DMA_ERQ_ERQ2)
Kojto 90:cb3d968589d8 786
Kojto 90:cb3d968589d8 787 /*! @brief Set the ERQ2 field to a new value. */
Kojto 90:cb3d968589d8 788 #define BW_DMA_ERQ_ERQ2(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2) = (v))
Kojto 90:cb3d968589d8 789 /*@}*/
Kojto 90:cb3d968589d8 790
Kojto 90:cb3d968589d8 791 /*!
Kojto 90:cb3d968589d8 792 * @name Register DMA_ERQ, field ERQ3[3] (RW)
Kojto 90:cb3d968589d8 793 *
Kojto 90:cb3d968589d8 794 * Values:
Kojto 90:cb3d968589d8 795 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 796 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 797 */
Kojto 90:cb3d968589d8 798 /*@{*/
Kojto 90:cb3d968589d8 799 #define BP_DMA_ERQ_ERQ3 (3U) /*!< Bit position for DMA_ERQ_ERQ3. */
Kojto 90:cb3d968589d8 800 #define BM_DMA_ERQ_ERQ3 (0x00000008U) /*!< Bit mask for DMA_ERQ_ERQ3. */
Kojto 90:cb3d968589d8 801 #define BS_DMA_ERQ_ERQ3 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ3. */
Kojto 90:cb3d968589d8 802
Kojto 90:cb3d968589d8 803 /*! @brief Read current value of the DMA_ERQ_ERQ3 field. */
Kojto 90:cb3d968589d8 804 #define BR_DMA_ERQ_ERQ3(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3))
Kojto 90:cb3d968589d8 805
Kojto 90:cb3d968589d8 806 /*! @brief Format value for bitfield DMA_ERQ_ERQ3. */
Kojto 90:cb3d968589d8 807 #define BF_DMA_ERQ_ERQ3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ3) & BM_DMA_ERQ_ERQ3)
Kojto 90:cb3d968589d8 808
Kojto 90:cb3d968589d8 809 /*! @brief Set the ERQ3 field to a new value. */
Kojto 90:cb3d968589d8 810 #define BW_DMA_ERQ_ERQ3(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3) = (v))
Kojto 90:cb3d968589d8 811 /*@}*/
Kojto 90:cb3d968589d8 812
Kojto 90:cb3d968589d8 813 /*!
Kojto 90:cb3d968589d8 814 * @name Register DMA_ERQ, field ERQ4[4] (RW)
Kojto 90:cb3d968589d8 815 *
Kojto 90:cb3d968589d8 816 * Values:
Kojto 90:cb3d968589d8 817 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 818 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 819 */
Kojto 90:cb3d968589d8 820 /*@{*/
Kojto 90:cb3d968589d8 821 #define BP_DMA_ERQ_ERQ4 (4U) /*!< Bit position for DMA_ERQ_ERQ4. */
Kojto 90:cb3d968589d8 822 #define BM_DMA_ERQ_ERQ4 (0x00000010U) /*!< Bit mask for DMA_ERQ_ERQ4. */
Kojto 90:cb3d968589d8 823 #define BS_DMA_ERQ_ERQ4 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ4. */
Kojto 90:cb3d968589d8 824
Kojto 90:cb3d968589d8 825 /*! @brief Read current value of the DMA_ERQ_ERQ4 field. */
Kojto 90:cb3d968589d8 826 #define BR_DMA_ERQ_ERQ4(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4))
Kojto 90:cb3d968589d8 827
Kojto 90:cb3d968589d8 828 /*! @brief Format value for bitfield DMA_ERQ_ERQ4. */
Kojto 90:cb3d968589d8 829 #define BF_DMA_ERQ_ERQ4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ4) & BM_DMA_ERQ_ERQ4)
Kojto 90:cb3d968589d8 830
Kojto 90:cb3d968589d8 831 /*! @brief Set the ERQ4 field to a new value. */
Kojto 90:cb3d968589d8 832 #define BW_DMA_ERQ_ERQ4(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4) = (v))
Kojto 90:cb3d968589d8 833 /*@}*/
Kojto 90:cb3d968589d8 834
Kojto 90:cb3d968589d8 835 /*!
Kojto 90:cb3d968589d8 836 * @name Register DMA_ERQ, field ERQ5[5] (RW)
Kojto 90:cb3d968589d8 837 *
Kojto 90:cb3d968589d8 838 * Values:
Kojto 90:cb3d968589d8 839 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 840 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 841 */
Kojto 90:cb3d968589d8 842 /*@{*/
Kojto 90:cb3d968589d8 843 #define BP_DMA_ERQ_ERQ5 (5U) /*!< Bit position for DMA_ERQ_ERQ5. */
Kojto 90:cb3d968589d8 844 #define BM_DMA_ERQ_ERQ5 (0x00000020U) /*!< Bit mask for DMA_ERQ_ERQ5. */
Kojto 90:cb3d968589d8 845 #define BS_DMA_ERQ_ERQ5 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ5. */
Kojto 90:cb3d968589d8 846
Kojto 90:cb3d968589d8 847 /*! @brief Read current value of the DMA_ERQ_ERQ5 field. */
Kojto 90:cb3d968589d8 848 #define BR_DMA_ERQ_ERQ5(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5))
Kojto 90:cb3d968589d8 849
Kojto 90:cb3d968589d8 850 /*! @brief Format value for bitfield DMA_ERQ_ERQ5. */
Kojto 90:cb3d968589d8 851 #define BF_DMA_ERQ_ERQ5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ5) & BM_DMA_ERQ_ERQ5)
Kojto 90:cb3d968589d8 852
Kojto 90:cb3d968589d8 853 /*! @brief Set the ERQ5 field to a new value. */
Kojto 90:cb3d968589d8 854 #define BW_DMA_ERQ_ERQ5(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5) = (v))
Kojto 90:cb3d968589d8 855 /*@}*/
Kojto 90:cb3d968589d8 856
Kojto 90:cb3d968589d8 857 /*!
Kojto 90:cb3d968589d8 858 * @name Register DMA_ERQ, field ERQ6[6] (RW)
Kojto 90:cb3d968589d8 859 *
Kojto 90:cb3d968589d8 860 * Values:
Kojto 90:cb3d968589d8 861 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 862 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 863 */
Kojto 90:cb3d968589d8 864 /*@{*/
Kojto 90:cb3d968589d8 865 #define BP_DMA_ERQ_ERQ6 (6U) /*!< Bit position for DMA_ERQ_ERQ6. */
Kojto 90:cb3d968589d8 866 #define BM_DMA_ERQ_ERQ6 (0x00000040U) /*!< Bit mask for DMA_ERQ_ERQ6. */
Kojto 90:cb3d968589d8 867 #define BS_DMA_ERQ_ERQ6 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ6. */
Kojto 90:cb3d968589d8 868
Kojto 90:cb3d968589d8 869 /*! @brief Read current value of the DMA_ERQ_ERQ6 field. */
Kojto 90:cb3d968589d8 870 #define BR_DMA_ERQ_ERQ6(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6))
Kojto 90:cb3d968589d8 871
Kojto 90:cb3d968589d8 872 /*! @brief Format value for bitfield DMA_ERQ_ERQ6. */
Kojto 90:cb3d968589d8 873 #define BF_DMA_ERQ_ERQ6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ6) & BM_DMA_ERQ_ERQ6)
Kojto 90:cb3d968589d8 874
Kojto 90:cb3d968589d8 875 /*! @brief Set the ERQ6 field to a new value. */
Kojto 90:cb3d968589d8 876 #define BW_DMA_ERQ_ERQ6(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6) = (v))
Kojto 90:cb3d968589d8 877 /*@}*/
Kojto 90:cb3d968589d8 878
Kojto 90:cb3d968589d8 879 /*!
Kojto 90:cb3d968589d8 880 * @name Register DMA_ERQ, field ERQ7[7] (RW)
Kojto 90:cb3d968589d8 881 *
Kojto 90:cb3d968589d8 882 * Values:
Kojto 90:cb3d968589d8 883 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 884 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 885 */
Kojto 90:cb3d968589d8 886 /*@{*/
Kojto 90:cb3d968589d8 887 #define BP_DMA_ERQ_ERQ7 (7U) /*!< Bit position for DMA_ERQ_ERQ7. */
Kojto 90:cb3d968589d8 888 #define BM_DMA_ERQ_ERQ7 (0x00000080U) /*!< Bit mask for DMA_ERQ_ERQ7. */
Kojto 90:cb3d968589d8 889 #define BS_DMA_ERQ_ERQ7 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ7. */
Kojto 90:cb3d968589d8 890
Kojto 90:cb3d968589d8 891 /*! @brief Read current value of the DMA_ERQ_ERQ7 field. */
Kojto 90:cb3d968589d8 892 #define BR_DMA_ERQ_ERQ7(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7))
Kojto 90:cb3d968589d8 893
Kojto 90:cb3d968589d8 894 /*! @brief Format value for bitfield DMA_ERQ_ERQ7. */
Kojto 90:cb3d968589d8 895 #define BF_DMA_ERQ_ERQ7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ7) & BM_DMA_ERQ_ERQ7)
Kojto 90:cb3d968589d8 896
Kojto 90:cb3d968589d8 897 /*! @brief Set the ERQ7 field to a new value. */
Kojto 90:cb3d968589d8 898 #define BW_DMA_ERQ_ERQ7(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7) = (v))
Kojto 90:cb3d968589d8 899 /*@}*/
Kojto 90:cb3d968589d8 900
Kojto 90:cb3d968589d8 901 /*!
Kojto 90:cb3d968589d8 902 * @name Register DMA_ERQ, field ERQ8[8] (RW)
Kojto 90:cb3d968589d8 903 *
Kojto 90:cb3d968589d8 904 * Values:
Kojto 90:cb3d968589d8 905 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 906 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 907 */
Kojto 90:cb3d968589d8 908 /*@{*/
Kojto 90:cb3d968589d8 909 #define BP_DMA_ERQ_ERQ8 (8U) /*!< Bit position for DMA_ERQ_ERQ8. */
Kojto 90:cb3d968589d8 910 #define BM_DMA_ERQ_ERQ8 (0x00000100U) /*!< Bit mask for DMA_ERQ_ERQ8. */
Kojto 90:cb3d968589d8 911 #define BS_DMA_ERQ_ERQ8 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ8. */
Kojto 90:cb3d968589d8 912
Kojto 90:cb3d968589d8 913 /*! @brief Read current value of the DMA_ERQ_ERQ8 field. */
Kojto 90:cb3d968589d8 914 #define BR_DMA_ERQ_ERQ8(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8))
Kojto 90:cb3d968589d8 915
Kojto 90:cb3d968589d8 916 /*! @brief Format value for bitfield DMA_ERQ_ERQ8. */
Kojto 90:cb3d968589d8 917 #define BF_DMA_ERQ_ERQ8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ8) & BM_DMA_ERQ_ERQ8)
Kojto 90:cb3d968589d8 918
Kojto 90:cb3d968589d8 919 /*! @brief Set the ERQ8 field to a new value. */
Kojto 90:cb3d968589d8 920 #define BW_DMA_ERQ_ERQ8(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8) = (v))
Kojto 90:cb3d968589d8 921 /*@}*/
Kojto 90:cb3d968589d8 922
Kojto 90:cb3d968589d8 923 /*!
Kojto 90:cb3d968589d8 924 * @name Register DMA_ERQ, field ERQ9[9] (RW)
Kojto 90:cb3d968589d8 925 *
Kojto 90:cb3d968589d8 926 * Values:
Kojto 90:cb3d968589d8 927 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 928 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 929 */
Kojto 90:cb3d968589d8 930 /*@{*/
Kojto 90:cb3d968589d8 931 #define BP_DMA_ERQ_ERQ9 (9U) /*!< Bit position for DMA_ERQ_ERQ9. */
Kojto 90:cb3d968589d8 932 #define BM_DMA_ERQ_ERQ9 (0x00000200U) /*!< Bit mask for DMA_ERQ_ERQ9. */
Kojto 90:cb3d968589d8 933 #define BS_DMA_ERQ_ERQ9 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ9. */
Kojto 90:cb3d968589d8 934
Kojto 90:cb3d968589d8 935 /*! @brief Read current value of the DMA_ERQ_ERQ9 field. */
Kojto 90:cb3d968589d8 936 #define BR_DMA_ERQ_ERQ9(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9))
Kojto 90:cb3d968589d8 937
Kojto 90:cb3d968589d8 938 /*! @brief Format value for bitfield DMA_ERQ_ERQ9. */
Kojto 90:cb3d968589d8 939 #define BF_DMA_ERQ_ERQ9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ9) & BM_DMA_ERQ_ERQ9)
Kojto 90:cb3d968589d8 940
Kojto 90:cb3d968589d8 941 /*! @brief Set the ERQ9 field to a new value. */
Kojto 90:cb3d968589d8 942 #define BW_DMA_ERQ_ERQ9(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9) = (v))
Kojto 90:cb3d968589d8 943 /*@}*/
Kojto 90:cb3d968589d8 944
Kojto 90:cb3d968589d8 945 /*!
Kojto 90:cb3d968589d8 946 * @name Register DMA_ERQ, field ERQ10[10] (RW)
Kojto 90:cb3d968589d8 947 *
Kojto 90:cb3d968589d8 948 * Values:
Kojto 90:cb3d968589d8 949 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 950 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 951 */
Kojto 90:cb3d968589d8 952 /*@{*/
Kojto 90:cb3d968589d8 953 #define BP_DMA_ERQ_ERQ10 (10U) /*!< Bit position for DMA_ERQ_ERQ10. */
Kojto 90:cb3d968589d8 954 #define BM_DMA_ERQ_ERQ10 (0x00000400U) /*!< Bit mask for DMA_ERQ_ERQ10. */
Kojto 90:cb3d968589d8 955 #define BS_DMA_ERQ_ERQ10 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ10. */
Kojto 90:cb3d968589d8 956
Kojto 90:cb3d968589d8 957 /*! @brief Read current value of the DMA_ERQ_ERQ10 field. */
Kojto 90:cb3d968589d8 958 #define BR_DMA_ERQ_ERQ10(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10))
Kojto 90:cb3d968589d8 959
Kojto 90:cb3d968589d8 960 /*! @brief Format value for bitfield DMA_ERQ_ERQ10. */
Kojto 90:cb3d968589d8 961 #define BF_DMA_ERQ_ERQ10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ10) & BM_DMA_ERQ_ERQ10)
Kojto 90:cb3d968589d8 962
Kojto 90:cb3d968589d8 963 /*! @brief Set the ERQ10 field to a new value. */
Kojto 90:cb3d968589d8 964 #define BW_DMA_ERQ_ERQ10(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10) = (v))
Kojto 90:cb3d968589d8 965 /*@}*/
Kojto 90:cb3d968589d8 966
Kojto 90:cb3d968589d8 967 /*!
Kojto 90:cb3d968589d8 968 * @name Register DMA_ERQ, field ERQ11[11] (RW)
Kojto 90:cb3d968589d8 969 *
Kojto 90:cb3d968589d8 970 * Values:
Kojto 90:cb3d968589d8 971 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 972 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 973 */
Kojto 90:cb3d968589d8 974 /*@{*/
Kojto 90:cb3d968589d8 975 #define BP_DMA_ERQ_ERQ11 (11U) /*!< Bit position for DMA_ERQ_ERQ11. */
Kojto 90:cb3d968589d8 976 #define BM_DMA_ERQ_ERQ11 (0x00000800U) /*!< Bit mask for DMA_ERQ_ERQ11. */
Kojto 90:cb3d968589d8 977 #define BS_DMA_ERQ_ERQ11 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ11. */
Kojto 90:cb3d968589d8 978
Kojto 90:cb3d968589d8 979 /*! @brief Read current value of the DMA_ERQ_ERQ11 field. */
Kojto 90:cb3d968589d8 980 #define BR_DMA_ERQ_ERQ11(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11))
Kojto 90:cb3d968589d8 981
Kojto 90:cb3d968589d8 982 /*! @brief Format value for bitfield DMA_ERQ_ERQ11. */
Kojto 90:cb3d968589d8 983 #define BF_DMA_ERQ_ERQ11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ11) & BM_DMA_ERQ_ERQ11)
Kojto 90:cb3d968589d8 984
Kojto 90:cb3d968589d8 985 /*! @brief Set the ERQ11 field to a new value. */
Kojto 90:cb3d968589d8 986 #define BW_DMA_ERQ_ERQ11(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11) = (v))
Kojto 90:cb3d968589d8 987 /*@}*/
Kojto 90:cb3d968589d8 988
Kojto 90:cb3d968589d8 989 /*!
Kojto 90:cb3d968589d8 990 * @name Register DMA_ERQ, field ERQ12[12] (RW)
Kojto 90:cb3d968589d8 991 *
Kojto 90:cb3d968589d8 992 * Values:
Kojto 90:cb3d968589d8 993 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 994 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 995 */
Kojto 90:cb3d968589d8 996 /*@{*/
Kojto 90:cb3d968589d8 997 #define BP_DMA_ERQ_ERQ12 (12U) /*!< Bit position for DMA_ERQ_ERQ12. */
Kojto 90:cb3d968589d8 998 #define BM_DMA_ERQ_ERQ12 (0x00001000U) /*!< Bit mask for DMA_ERQ_ERQ12. */
Kojto 90:cb3d968589d8 999 #define BS_DMA_ERQ_ERQ12 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ12. */
Kojto 90:cb3d968589d8 1000
Kojto 90:cb3d968589d8 1001 /*! @brief Read current value of the DMA_ERQ_ERQ12 field. */
Kojto 90:cb3d968589d8 1002 #define BR_DMA_ERQ_ERQ12(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12))
Kojto 90:cb3d968589d8 1003
Kojto 90:cb3d968589d8 1004 /*! @brief Format value for bitfield DMA_ERQ_ERQ12. */
Kojto 90:cb3d968589d8 1005 #define BF_DMA_ERQ_ERQ12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ12) & BM_DMA_ERQ_ERQ12)
Kojto 90:cb3d968589d8 1006
Kojto 90:cb3d968589d8 1007 /*! @brief Set the ERQ12 field to a new value. */
Kojto 90:cb3d968589d8 1008 #define BW_DMA_ERQ_ERQ12(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12) = (v))
Kojto 90:cb3d968589d8 1009 /*@}*/
Kojto 90:cb3d968589d8 1010
Kojto 90:cb3d968589d8 1011 /*!
Kojto 90:cb3d968589d8 1012 * @name Register DMA_ERQ, field ERQ13[13] (RW)
Kojto 90:cb3d968589d8 1013 *
Kojto 90:cb3d968589d8 1014 * Values:
Kojto 90:cb3d968589d8 1015 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 1016 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 1017 */
Kojto 90:cb3d968589d8 1018 /*@{*/
Kojto 90:cb3d968589d8 1019 #define BP_DMA_ERQ_ERQ13 (13U) /*!< Bit position for DMA_ERQ_ERQ13. */
Kojto 90:cb3d968589d8 1020 #define BM_DMA_ERQ_ERQ13 (0x00002000U) /*!< Bit mask for DMA_ERQ_ERQ13. */
Kojto 90:cb3d968589d8 1021 #define BS_DMA_ERQ_ERQ13 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ13. */
Kojto 90:cb3d968589d8 1022
Kojto 90:cb3d968589d8 1023 /*! @brief Read current value of the DMA_ERQ_ERQ13 field. */
Kojto 90:cb3d968589d8 1024 #define BR_DMA_ERQ_ERQ13(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13))
Kojto 90:cb3d968589d8 1025
Kojto 90:cb3d968589d8 1026 /*! @brief Format value for bitfield DMA_ERQ_ERQ13. */
Kojto 90:cb3d968589d8 1027 #define BF_DMA_ERQ_ERQ13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ13) & BM_DMA_ERQ_ERQ13)
Kojto 90:cb3d968589d8 1028
Kojto 90:cb3d968589d8 1029 /*! @brief Set the ERQ13 field to a new value. */
Kojto 90:cb3d968589d8 1030 #define BW_DMA_ERQ_ERQ13(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13) = (v))
Kojto 90:cb3d968589d8 1031 /*@}*/
Kojto 90:cb3d968589d8 1032
Kojto 90:cb3d968589d8 1033 /*!
Kojto 90:cb3d968589d8 1034 * @name Register DMA_ERQ, field ERQ14[14] (RW)
Kojto 90:cb3d968589d8 1035 *
Kojto 90:cb3d968589d8 1036 * Values:
Kojto 90:cb3d968589d8 1037 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 1038 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 1039 */
Kojto 90:cb3d968589d8 1040 /*@{*/
Kojto 90:cb3d968589d8 1041 #define BP_DMA_ERQ_ERQ14 (14U) /*!< Bit position for DMA_ERQ_ERQ14. */
Kojto 90:cb3d968589d8 1042 #define BM_DMA_ERQ_ERQ14 (0x00004000U) /*!< Bit mask for DMA_ERQ_ERQ14. */
Kojto 90:cb3d968589d8 1043 #define BS_DMA_ERQ_ERQ14 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ14. */
Kojto 90:cb3d968589d8 1044
Kojto 90:cb3d968589d8 1045 /*! @brief Read current value of the DMA_ERQ_ERQ14 field. */
Kojto 90:cb3d968589d8 1046 #define BR_DMA_ERQ_ERQ14(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14))
Kojto 90:cb3d968589d8 1047
Kojto 90:cb3d968589d8 1048 /*! @brief Format value for bitfield DMA_ERQ_ERQ14. */
Kojto 90:cb3d968589d8 1049 #define BF_DMA_ERQ_ERQ14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ14) & BM_DMA_ERQ_ERQ14)
Kojto 90:cb3d968589d8 1050
Kojto 90:cb3d968589d8 1051 /*! @brief Set the ERQ14 field to a new value. */
Kojto 90:cb3d968589d8 1052 #define BW_DMA_ERQ_ERQ14(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14) = (v))
Kojto 90:cb3d968589d8 1053 /*@}*/
Kojto 90:cb3d968589d8 1054
Kojto 90:cb3d968589d8 1055 /*!
Kojto 90:cb3d968589d8 1056 * @name Register DMA_ERQ, field ERQ15[15] (RW)
Kojto 90:cb3d968589d8 1057 *
Kojto 90:cb3d968589d8 1058 * Values:
Kojto 90:cb3d968589d8 1059 * - 0 - The DMA request signal for the corresponding channel is disabled
Kojto 90:cb3d968589d8 1060 * - 1 - The DMA request signal for the corresponding channel is enabled
Kojto 90:cb3d968589d8 1061 */
Kojto 90:cb3d968589d8 1062 /*@{*/
Kojto 90:cb3d968589d8 1063 #define BP_DMA_ERQ_ERQ15 (15U) /*!< Bit position for DMA_ERQ_ERQ15. */
Kojto 90:cb3d968589d8 1064 #define BM_DMA_ERQ_ERQ15 (0x00008000U) /*!< Bit mask for DMA_ERQ_ERQ15. */
Kojto 90:cb3d968589d8 1065 #define BS_DMA_ERQ_ERQ15 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ15. */
Kojto 90:cb3d968589d8 1066
Kojto 90:cb3d968589d8 1067 /*! @brief Read current value of the DMA_ERQ_ERQ15 field. */
Kojto 90:cb3d968589d8 1068 #define BR_DMA_ERQ_ERQ15(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15))
Kojto 90:cb3d968589d8 1069
Kojto 90:cb3d968589d8 1070 /*! @brief Format value for bitfield DMA_ERQ_ERQ15. */
Kojto 90:cb3d968589d8 1071 #define BF_DMA_ERQ_ERQ15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ15) & BM_DMA_ERQ_ERQ15)
Kojto 90:cb3d968589d8 1072
Kojto 90:cb3d968589d8 1073 /*! @brief Set the ERQ15 field to a new value. */
Kojto 90:cb3d968589d8 1074 #define BW_DMA_ERQ_ERQ15(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15) = (v))
Kojto 90:cb3d968589d8 1075 /*@}*/
Kojto 90:cb3d968589d8 1076
Kojto 90:cb3d968589d8 1077 /*******************************************************************************
Kojto 90:cb3d968589d8 1078 * HW_DMA_EEI - Enable Error Interrupt Register
Kojto 90:cb3d968589d8 1079 ******************************************************************************/
Kojto 90:cb3d968589d8 1080
Kojto 90:cb3d968589d8 1081 /*!
Kojto 90:cb3d968589d8 1082 * @brief HW_DMA_EEI - Enable Error Interrupt Register (RW)
Kojto 90:cb3d968589d8 1083 *
Kojto 90:cb3d968589d8 1084 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 1085 *
Kojto 90:cb3d968589d8 1086 * The EEI register provides a bit map for the 16 channels to enable the error
Kojto 90:cb3d968589d8 1087 * interrupt signal for each channel. The state of any given channel's error
Kojto 90:cb3d968589d8 1088 * interrupt enable is directly affected by writes to this register; it is also
Kojto 90:cb3d968589d8 1089 * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
Kojto 90:cb3d968589d8 1090 * interrupt enable for a single channel can easily be modified without the need to
Kojto 90:cb3d968589d8 1091 * perform a read-modify-write sequence to the EEI register. The DMA error
Kojto 90:cb3d968589d8 1092 * indicator and the error interrupt enable flag must be asserted before an error
Kojto 90:cb3d968589d8 1093 * interrupt request for a given channel is asserted to the interrupt controller.
Kojto 90:cb3d968589d8 1094 */
Kojto 90:cb3d968589d8 1095 typedef union _hw_dma_eei
Kojto 90:cb3d968589d8 1096 {
Kojto 90:cb3d968589d8 1097 uint32_t U;
Kojto 90:cb3d968589d8 1098 struct _hw_dma_eei_bitfields
Kojto 90:cb3d968589d8 1099 {
Kojto 90:cb3d968589d8 1100 uint32_t EEI0 : 1; /*!< [0] Enable Error Interrupt 0 */
Kojto 90:cb3d968589d8 1101 uint32_t EEI1 : 1; /*!< [1] Enable Error Interrupt 1 */
Kojto 90:cb3d968589d8 1102 uint32_t EEI2 : 1; /*!< [2] Enable Error Interrupt 2 */
Kojto 90:cb3d968589d8 1103 uint32_t EEI3 : 1; /*!< [3] Enable Error Interrupt 3 */
Kojto 90:cb3d968589d8 1104 uint32_t EEI4 : 1; /*!< [4] Enable Error Interrupt 4 */
Kojto 90:cb3d968589d8 1105 uint32_t EEI5 : 1; /*!< [5] Enable Error Interrupt 5 */
Kojto 90:cb3d968589d8 1106 uint32_t EEI6 : 1; /*!< [6] Enable Error Interrupt 6 */
Kojto 90:cb3d968589d8 1107 uint32_t EEI7 : 1; /*!< [7] Enable Error Interrupt 7 */
Kojto 90:cb3d968589d8 1108 uint32_t EEI8 : 1; /*!< [8] Enable Error Interrupt 8 */
Kojto 90:cb3d968589d8 1109 uint32_t EEI9 : 1; /*!< [9] Enable Error Interrupt 9 */
Kojto 90:cb3d968589d8 1110 uint32_t EEI10 : 1; /*!< [10] Enable Error Interrupt 10 */
Kojto 90:cb3d968589d8 1111 uint32_t EEI11 : 1; /*!< [11] Enable Error Interrupt 11 */
Kojto 90:cb3d968589d8 1112 uint32_t EEI12 : 1; /*!< [12] Enable Error Interrupt 12 */
Kojto 90:cb3d968589d8 1113 uint32_t EEI13 : 1; /*!< [13] Enable Error Interrupt 13 */
Kojto 90:cb3d968589d8 1114 uint32_t EEI14 : 1; /*!< [14] Enable Error Interrupt 14 */
Kojto 90:cb3d968589d8 1115 uint32_t EEI15 : 1; /*!< [15] Enable Error Interrupt 15 */
Kojto 90:cb3d968589d8 1116 uint32_t RESERVED0 : 16; /*!< [31:16] */
Kojto 90:cb3d968589d8 1117 } B;
Kojto 90:cb3d968589d8 1118 } hw_dma_eei_t;
Kojto 90:cb3d968589d8 1119
Kojto 90:cb3d968589d8 1120 /*!
Kojto 90:cb3d968589d8 1121 * @name Constants and macros for entire DMA_EEI register
Kojto 90:cb3d968589d8 1122 */
Kojto 90:cb3d968589d8 1123 /*@{*/
Kojto 90:cb3d968589d8 1124 #define HW_DMA_EEI_ADDR(x) ((x) + 0x14U)
Kojto 90:cb3d968589d8 1125
Kojto 90:cb3d968589d8 1126 #define HW_DMA_EEI(x) (*(__IO hw_dma_eei_t *) HW_DMA_EEI_ADDR(x))
Kojto 90:cb3d968589d8 1127 #define HW_DMA_EEI_RD(x) (HW_DMA_EEI(x).U)
Kojto 90:cb3d968589d8 1128 #define HW_DMA_EEI_WR(x, v) (HW_DMA_EEI(x).U = (v))
Kojto 90:cb3d968589d8 1129 #define HW_DMA_EEI_SET(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) | (v)))
Kojto 90:cb3d968589d8 1130 #define HW_DMA_EEI_CLR(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 1131 #define HW_DMA_EEI_TOG(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 1132 /*@}*/
Kojto 90:cb3d968589d8 1133
Kojto 90:cb3d968589d8 1134 /*
Kojto 90:cb3d968589d8 1135 * Constants & macros for individual DMA_EEI bitfields
Kojto 90:cb3d968589d8 1136 */
Kojto 90:cb3d968589d8 1137
Kojto 90:cb3d968589d8 1138 /*!
Kojto 90:cb3d968589d8 1139 * @name Register DMA_EEI, field EEI0[0] (RW)
Kojto 90:cb3d968589d8 1140 *
Kojto 90:cb3d968589d8 1141 * Values:
Kojto 90:cb3d968589d8 1142 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1143 * interrupt
Kojto 90:cb3d968589d8 1144 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1145 * an error interrupt request
Kojto 90:cb3d968589d8 1146 */
Kojto 90:cb3d968589d8 1147 /*@{*/
Kojto 90:cb3d968589d8 1148 #define BP_DMA_EEI_EEI0 (0U) /*!< Bit position for DMA_EEI_EEI0. */
Kojto 90:cb3d968589d8 1149 #define BM_DMA_EEI_EEI0 (0x00000001U) /*!< Bit mask for DMA_EEI_EEI0. */
Kojto 90:cb3d968589d8 1150 #define BS_DMA_EEI_EEI0 (1U) /*!< Bit field size in bits for DMA_EEI_EEI0. */
Kojto 90:cb3d968589d8 1151
Kojto 90:cb3d968589d8 1152 /*! @brief Read current value of the DMA_EEI_EEI0 field. */
Kojto 90:cb3d968589d8 1153 #define BR_DMA_EEI_EEI0(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0))
Kojto 90:cb3d968589d8 1154
Kojto 90:cb3d968589d8 1155 /*! @brief Format value for bitfield DMA_EEI_EEI0. */
Kojto 90:cb3d968589d8 1156 #define BF_DMA_EEI_EEI0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI0) & BM_DMA_EEI_EEI0)
Kojto 90:cb3d968589d8 1157
Kojto 90:cb3d968589d8 1158 /*! @brief Set the EEI0 field to a new value. */
Kojto 90:cb3d968589d8 1159 #define BW_DMA_EEI_EEI0(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0) = (v))
Kojto 90:cb3d968589d8 1160 /*@}*/
Kojto 90:cb3d968589d8 1161
Kojto 90:cb3d968589d8 1162 /*!
Kojto 90:cb3d968589d8 1163 * @name Register DMA_EEI, field EEI1[1] (RW)
Kojto 90:cb3d968589d8 1164 *
Kojto 90:cb3d968589d8 1165 * Values:
Kojto 90:cb3d968589d8 1166 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1167 * interrupt
Kojto 90:cb3d968589d8 1168 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1169 * an error interrupt request
Kojto 90:cb3d968589d8 1170 */
Kojto 90:cb3d968589d8 1171 /*@{*/
Kojto 90:cb3d968589d8 1172 #define BP_DMA_EEI_EEI1 (1U) /*!< Bit position for DMA_EEI_EEI1. */
Kojto 90:cb3d968589d8 1173 #define BM_DMA_EEI_EEI1 (0x00000002U) /*!< Bit mask for DMA_EEI_EEI1. */
Kojto 90:cb3d968589d8 1174 #define BS_DMA_EEI_EEI1 (1U) /*!< Bit field size in bits for DMA_EEI_EEI1. */
Kojto 90:cb3d968589d8 1175
Kojto 90:cb3d968589d8 1176 /*! @brief Read current value of the DMA_EEI_EEI1 field. */
Kojto 90:cb3d968589d8 1177 #define BR_DMA_EEI_EEI1(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1))
Kojto 90:cb3d968589d8 1178
Kojto 90:cb3d968589d8 1179 /*! @brief Format value for bitfield DMA_EEI_EEI1. */
Kojto 90:cb3d968589d8 1180 #define BF_DMA_EEI_EEI1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI1) & BM_DMA_EEI_EEI1)
Kojto 90:cb3d968589d8 1181
Kojto 90:cb3d968589d8 1182 /*! @brief Set the EEI1 field to a new value. */
Kojto 90:cb3d968589d8 1183 #define BW_DMA_EEI_EEI1(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1) = (v))
Kojto 90:cb3d968589d8 1184 /*@}*/
Kojto 90:cb3d968589d8 1185
Kojto 90:cb3d968589d8 1186 /*!
Kojto 90:cb3d968589d8 1187 * @name Register DMA_EEI, field EEI2[2] (RW)
Kojto 90:cb3d968589d8 1188 *
Kojto 90:cb3d968589d8 1189 * Values:
Kojto 90:cb3d968589d8 1190 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1191 * interrupt
Kojto 90:cb3d968589d8 1192 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1193 * an error interrupt request
Kojto 90:cb3d968589d8 1194 */
Kojto 90:cb3d968589d8 1195 /*@{*/
Kojto 90:cb3d968589d8 1196 #define BP_DMA_EEI_EEI2 (2U) /*!< Bit position for DMA_EEI_EEI2. */
Kojto 90:cb3d968589d8 1197 #define BM_DMA_EEI_EEI2 (0x00000004U) /*!< Bit mask for DMA_EEI_EEI2. */
Kojto 90:cb3d968589d8 1198 #define BS_DMA_EEI_EEI2 (1U) /*!< Bit field size in bits for DMA_EEI_EEI2. */
Kojto 90:cb3d968589d8 1199
Kojto 90:cb3d968589d8 1200 /*! @brief Read current value of the DMA_EEI_EEI2 field. */
Kojto 90:cb3d968589d8 1201 #define BR_DMA_EEI_EEI2(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2))
Kojto 90:cb3d968589d8 1202
Kojto 90:cb3d968589d8 1203 /*! @brief Format value for bitfield DMA_EEI_EEI2. */
Kojto 90:cb3d968589d8 1204 #define BF_DMA_EEI_EEI2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI2) & BM_DMA_EEI_EEI2)
Kojto 90:cb3d968589d8 1205
Kojto 90:cb3d968589d8 1206 /*! @brief Set the EEI2 field to a new value. */
Kojto 90:cb3d968589d8 1207 #define BW_DMA_EEI_EEI2(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2) = (v))
Kojto 90:cb3d968589d8 1208 /*@}*/
Kojto 90:cb3d968589d8 1209
Kojto 90:cb3d968589d8 1210 /*!
Kojto 90:cb3d968589d8 1211 * @name Register DMA_EEI, field EEI3[3] (RW)
Kojto 90:cb3d968589d8 1212 *
Kojto 90:cb3d968589d8 1213 * Values:
Kojto 90:cb3d968589d8 1214 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1215 * interrupt
Kojto 90:cb3d968589d8 1216 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1217 * an error interrupt request
Kojto 90:cb3d968589d8 1218 */
Kojto 90:cb3d968589d8 1219 /*@{*/
Kojto 90:cb3d968589d8 1220 #define BP_DMA_EEI_EEI3 (3U) /*!< Bit position for DMA_EEI_EEI3. */
Kojto 90:cb3d968589d8 1221 #define BM_DMA_EEI_EEI3 (0x00000008U) /*!< Bit mask for DMA_EEI_EEI3. */
Kojto 90:cb3d968589d8 1222 #define BS_DMA_EEI_EEI3 (1U) /*!< Bit field size in bits for DMA_EEI_EEI3. */
Kojto 90:cb3d968589d8 1223
Kojto 90:cb3d968589d8 1224 /*! @brief Read current value of the DMA_EEI_EEI3 field. */
Kojto 90:cb3d968589d8 1225 #define BR_DMA_EEI_EEI3(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3))
Kojto 90:cb3d968589d8 1226
Kojto 90:cb3d968589d8 1227 /*! @brief Format value for bitfield DMA_EEI_EEI3. */
Kojto 90:cb3d968589d8 1228 #define BF_DMA_EEI_EEI3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI3) & BM_DMA_EEI_EEI3)
Kojto 90:cb3d968589d8 1229
Kojto 90:cb3d968589d8 1230 /*! @brief Set the EEI3 field to a new value. */
Kojto 90:cb3d968589d8 1231 #define BW_DMA_EEI_EEI3(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3) = (v))
Kojto 90:cb3d968589d8 1232 /*@}*/
Kojto 90:cb3d968589d8 1233
Kojto 90:cb3d968589d8 1234 /*!
Kojto 90:cb3d968589d8 1235 * @name Register DMA_EEI, field EEI4[4] (RW)
Kojto 90:cb3d968589d8 1236 *
Kojto 90:cb3d968589d8 1237 * Values:
Kojto 90:cb3d968589d8 1238 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1239 * interrupt
Kojto 90:cb3d968589d8 1240 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1241 * an error interrupt request
Kojto 90:cb3d968589d8 1242 */
Kojto 90:cb3d968589d8 1243 /*@{*/
Kojto 90:cb3d968589d8 1244 #define BP_DMA_EEI_EEI4 (4U) /*!< Bit position for DMA_EEI_EEI4. */
Kojto 90:cb3d968589d8 1245 #define BM_DMA_EEI_EEI4 (0x00000010U) /*!< Bit mask for DMA_EEI_EEI4. */
Kojto 90:cb3d968589d8 1246 #define BS_DMA_EEI_EEI4 (1U) /*!< Bit field size in bits for DMA_EEI_EEI4. */
Kojto 90:cb3d968589d8 1247
Kojto 90:cb3d968589d8 1248 /*! @brief Read current value of the DMA_EEI_EEI4 field. */
Kojto 90:cb3d968589d8 1249 #define BR_DMA_EEI_EEI4(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4))
Kojto 90:cb3d968589d8 1250
Kojto 90:cb3d968589d8 1251 /*! @brief Format value for bitfield DMA_EEI_EEI4. */
Kojto 90:cb3d968589d8 1252 #define BF_DMA_EEI_EEI4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI4) & BM_DMA_EEI_EEI4)
Kojto 90:cb3d968589d8 1253
Kojto 90:cb3d968589d8 1254 /*! @brief Set the EEI4 field to a new value. */
Kojto 90:cb3d968589d8 1255 #define BW_DMA_EEI_EEI4(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4) = (v))
Kojto 90:cb3d968589d8 1256 /*@}*/
Kojto 90:cb3d968589d8 1257
Kojto 90:cb3d968589d8 1258 /*!
Kojto 90:cb3d968589d8 1259 * @name Register DMA_EEI, field EEI5[5] (RW)
Kojto 90:cb3d968589d8 1260 *
Kojto 90:cb3d968589d8 1261 * Values:
Kojto 90:cb3d968589d8 1262 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1263 * interrupt
Kojto 90:cb3d968589d8 1264 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1265 * an error interrupt request
Kojto 90:cb3d968589d8 1266 */
Kojto 90:cb3d968589d8 1267 /*@{*/
Kojto 90:cb3d968589d8 1268 #define BP_DMA_EEI_EEI5 (5U) /*!< Bit position for DMA_EEI_EEI5. */
Kojto 90:cb3d968589d8 1269 #define BM_DMA_EEI_EEI5 (0x00000020U) /*!< Bit mask for DMA_EEI_EEI5. */
Kojto 90:cb3d968589d8 1270 #define BS_DMA_EEI_EEI5 (1U) /*!< Bit field size in bits for DMA_EEI_EEI5. */
Kojto 90:cb3d968589d8 1271
Kojto 90:cb3d968589d8 1272 /*! @brief Read current value of the DMA_EEI_EEI5 field. */
Kojto 90:cb3d968589d8 1273 #define BR_DMA_EEI_EEI5(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5))
Kojto 90:cb3d968589d8 1274
Kojto 90:cb3d968589d8 1275 /*! @brief Format value for bitfield DMA_EEI_EEI5. */
Kojto 90:cb3d968589d8 1276 #define BF_DMA_EEI_EEI5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI5) & BM_DMA_EEI_EEI5)
Kojto 90:cb3d968589d8 1277
Kojto 90:cb3d968589d8 1278 /*! @brief Set the EEI5 field to a new value. */
Kojto 90:cb3d968589d8 1279 #define BW_DMA_EEI_EEI5(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5) = (v))
Kojto 90:cb3d968589d8 1280 /*@}*/
Kojto 90:cb3d968589d8 1281
Kojto 90:cb3d968589d8 1282 /*!
Kojto 90:cb3d968589d8 1283 * @name Register DMA_EEI, field EEI6[6] (RW)
Kojto 90:cb3d968589d8 1284 *
Kojto 90:cb3d968589d8 1285 * Values:
Kojto 90:cb3d968589d8 1286 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1287 * interrupt
Kojto 90:cb3d968589d8 1288 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1289 * an error interrupt request
Kojto 90:cb3d968589d8 1290 */
Kojto 90:cb3d968589d8 1291 /*@{*/
Kojto 90:cb3d968589d8 1292 #define BP_DMA_EEI_EEI6 (6U) /*!< Bit position for DMA_EEI_EEI6. */
Kojto 90:cb3d968589d8 1293 #define BM_DMA_EEI_EEI6 (0x00000040U) /*!< Bit mask for DMA_EEI_EEI6. */
Kojto 90:cb3d968589d8 1294 #define BS_DMA_EEI_EEI6 (1U) /*!< Bit field size in bits for DMA_EEI_EEI6. */
Kojto 90:cb3d968589d8 1295
Kojto 90:cb3d968589d8 1296 /*! @brief Read current value of the DMA_EEI_EEI6 field. */
Kojto 90:cb3d968589d8 1297 #define BR_DMA_EEI_EEI6(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6))
Kojto 90:cb3d968589d8 1298
Kojto 90:cb3d968589d8 1299 /*! @brief Format value for bitfield DMA_EEI_EEI6. */
Kojto 90:cb3d968589d8 1300 #define BF_DMA_EEI_EEI6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI6) & BM_DMA_EEI_EEI6)
Kojto 90:cb3d968589d8 1301
Kojto 90:cb3d968589d8 1302 /*! @brief Set the EEI6 field to a new value. */
Kojto 90:cb3d968589d8 1303 #define BW_DMA_EEI_EEI6(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6) = (v))
Kojto 90:cb3d968589d8 1304 /*@}*/
Kojto 90:cb3d968589d8 1305
Kojto 90:cb3d968589d8 1306 /*!
Kojto 90:cb3d968589d8 1307 * @name Register DMA_EEI, field EEI7[7] (RW)
Kojto 90:cb3d968589d8 1308 *
Kojto 90:cb3d968589d8 1309 * Values:
Kojto 90:cb3d968589d8 1310 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1311 * interrupt
Kojto 90:cb3d968589d8 1312 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1313 * an error interrupt request
Kojto 90:cb3d968589d8 1314 */
Kojto 90:cb3d968589d8 1315 /*@{*/
Kojto 90:cb3d968589d8 1316 #define BP_DMA_EEI_EEI7 (7U) /*!< Bit position for DMA_EEI_EEI7. */
Kojto 90:cb3d968589d8 1317 #define BM_DMA_EEI_EEI7 (0x00000080U) /*!< Bit mask for DMA_EEI_EEI7. */
Kojto 90:cb3d968589d8 1318 #define BS_DMA_EEI_EEI7 (1U) /*!< Bit field size in bits for DMA_EEI_EEI7. */
Kojto 90:cb3d968589d8 1319
Kojto 90:cb3d968589d8 1320 /*! @brief Read current value of the DMA_EEI_EEI7 field. */
Kojto 90:cb3d968589d8 1321 #define BR_DMA_EEI_EEI7(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7))
Kojto 90:cb3d968589d8 1322
Kojto 90:cb3d968589d8 1323 /*! @brief Format value for bitfield DMA_EEI_EEI7. */
Kojto 90:cb3d968589d8 1324 #define BF_DMA_EEI_EEI7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI7) & BM_DMA_EEI_EEI7)
Kojto 90:cb3d968589d8 1325
Kojto 90:cb3d968589d8 1326 /*! @brief Set the EEI7 field to a new value. */
Kojto 90:cb3d968589d8 1327 #define BW_DMA_EEI_EEI7(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7) = (v))
Kojto 90:cb3d968589d8 1328 /*@}*/
Kojto 90:cb3d968589d8 1329
Kojto 90:cb3d968589d8 1330 /*!
Kojto 90:cb3d968589d8 1331 * @name Register DMA_EEI, field EEI8[8] (RW)
Kojto 90:cb3d968589d8 1332 *
Kojto 90:cb3d968589d8 1333 * Values:
Kojto 90:cb3d968589d8 1334 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1335 * interrupt
Kojto 90:cb3d968589d8 1336 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1337 * an error interrupt request
Kojto 90:cb3d968589d8 1338 */
Kojto 90:cb3d968589d8 1339 /*@{*/
Kojto 90:cb3d968589d8 1340 #define BP_DMA_EEI_EEI8 (8U) /*!< Bit position for DMA_EEI_EEI8. */
Kojto 90:cb3d968589d8 1341 #define BM_DMA_EEI_EEI8 (0x00000100U) /*!< Bit mask for DMA_EEI_EEI8. */
Kojto 90:cb3d968589d8 1342 #define BS_DMA_EEI_EEI8 (1U) /*!< Bit field size in bits for DMA_EEI_EEI8. */
Kojto 90:cb3d968589d8 1343
Kojto 90:cb3d968589d8 1344 /*! @brief Read current value of the DMA_EEI_EEI8 field. */
Kojto 90:cb3d968589d8 1345 #define BR_DMA_EEI_EEI8(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8))
Kojto 90:cb3d968589d8 1346
Kojto 90:cb3d968589d8 1347 /*! @brief Format value for bitfield DMA_EEI_EEI8. */
Kojto 90:cb3d968589d8 1348 #define BF_DMA_EEI_EEI8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI8) & BM_DMA_EEI_EEI8)
Kojto 90:cb3d968589d8 1349
Kojto 90:cb3d968589d8 1350 /*! @brief Set the EEI8 field to a new value. */
Kojto 90:cb3d968589d8 1351 #define BW_DMA_EEI_EEI8(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8) = (v))
Kojto 90:cb3d968589d8 1352 /*@}*/
Kojto 90:cb3d968589d8 1353
Kojto 90:cb3d968589d8 1354 /*!
Kojto 90:cb3d968589d8 1355 * @name Register DMA_EEI, field EEI9[9] (RW)
Kojto 90:cb3d968589d8 1356 *
Kojto 90:cb3d968589d8 1357 * Values:
Kojto 90:cb3d968589d8 1358 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1359 * interrupt
Kojto 90:cb3d968589d8 1360 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1361 * an error interrupt request
Kojto 90:cb3d968589d8 1362 */
Kojto 90:cb3d968589d8 1363 /*@{*/
Kojto 90:cb3d968589d8 1364 #define BP_DMA_EEI_EEI9 (9U) /*!< Bit position for DMA_EEI_EEI9. */
Kojto 90:cb3d968589d8 1365 #define BM_DMA_EEI_EEI9 (0x00000200U) /*!< Bit mask for DMA_EEI_EEI9. */
Kojto 90:cb3d968589d8 1366 #define BS_DMA_EEI_EEI9 (1U) /*!< Bit field size in bits for DMA_EEI_EEI9. */
Kojto 90:cb3d968589d8 1367
Kojto 90:cb3d968589d8 1368 /*! @brief Read current value of the DMA_EEI_EEI9 field. */
Kojto 90:cb3d968589d8 1369 #define BR_DMA_EEI_EEI9(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9))
Kojto 90:cb3d968589d8 1370
Kojto 90:cb3d968589d8 1371 /*! @brief Format value for bitfield DMA_EEI_EEI9. */
Kojto 90:cb3d968589d8 1372 #define BF_DMA_EEI_EEI9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI9) & BM_DMA_EEI_EEI9)
Kojto 90:cb3d968589d8 1373
Kojto 90:cb3d968589d8 1374 /*! @brief Set the EEI9 field to a new value. */
Kojto 90:cb3d968589d8 1375 #define BW_DMA_EEI_EEI9(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9) = (v))
Kojto 90:cb3d968589d8 1376 /*@}*/
Kojto 90:cb3d968589d8 1377
Kojto 90:cb3d968589d8 1378 /*!
Kojto 90:cb3d968589d8 1379 * @name Register DMA_EEI, field EEI10[10] (RW)
Kojto 90:cb3d968589d8 1380 *
Kojto 90:cb3d968589d8 1381 * Values:
Kojto 90:cb3d968589d8 1382 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1383 * interrupt
Kojto 90:cb3d968589d8 1384 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1385 * an error interrupt request
Kojto 90:cb3d968589d8 1386 */
Kojto 90:cb3d968589d8 1387 /*@{*/
Kojto 90:cb3d968589d8 1388 #define BP_DMA_EEI_EEI10 (10U) /*!< Bit position for DMA_EEI_EEI10. */
Kojto 90:cb3d968589d8 1389 #define BM_DMA_EEI_EEI10 (0x00000400U) /*!< Bit mask for DMA_EEI_EEI10. */
Kojto 90:cb3d968589d8 1390 #define BS_DMA_EEI_EEI10 (1U) /*!< Bit field size in bits for DMA_EEI_EEI10. */
Kojto 90:cb3d968589d8 1391
Kojto 90:cb3d968589d8 1392 /*! @brief Read current value of the DMA_EEI_EEI10 field. */
Kojto 90:cb3d968589d8 1393 #define BR_DMA_EEI_EEI10(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10))
Kojto 90:cb3d968589d8 1394
Kojto 90:cb3d968589d8 1395 /*! @brief Format value for bitfield DMA_EEI_EEI10. */
Kojto 90:cb3d968589d8 1396 #define BF_DMA_EEI_EEI10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI10) & BM_DMA_EEI_EEI10)
Kojto 90:cb3d968589d8 1397
Kojto 90:cb3d968589d8 1398 /*! @brief Set the EEI10 field to a new value. */
Kojto 90:cb3d968589d8 1399 #define BW_DMA_EEI_EEI10(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10) = (v))
Kojto 90:cb3d968589d8 1400 /*@}*/
Kojto 90:cb3d968589d8 1401
Kojto 90:cb3d968589d8 1402 /*!
Kojto 90:cb3d968589d8 1403 * @name Register DMA_EEI, field EEI11[11] (RW)
Kojto 90:cb3d968589d8 1404 *
Kojto 90:cb3d968589d8 1405 * Values:
Kojto 90:cb3d968589d8 1406 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1407 * interrupt
Kojto 90:cb3d968589d8 1408 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1409 * an error interrupt request
Kojto 90:cb3d968589d8 1410 */
Kojto 90:cb3d968589d8 1411 /*@{*/
Kojto 90:cb3d968589d8 1412 #define BP_DMA_EEI_EEI11 (11U) /*!< Bit position for DMA_EEI_EEI11. */
Kojto 90:cb3d968589d8 1413 #define BM_DMA_EEI_EEI11 (0x00000800U) /*!< Bit mask for DMA_EEI_EEI11. */
Kojto 90:cb3d968589d8 1414 #define BS_DMA_EEI_EEI11 (1U) /*!< Bit field size in bits for DMA_EEI_EEI11. */
Kojto 90:cb3d968589d8 1415
Kojto 90:cb3d968589d8 1416 /*! @brief Read current value of the DMA_EEI_EEI11 field. */
Kojto 90:cb3d968589d8 1417 #define BR_DMA_EEI_EEI11(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11))
Kojto 90:cb3d968589d8 1418
Kojto 90:cb3d968589d8 1419 /*! @brief Format value for bitfield DMA_EEI_EEI11. */
Kojto 90:cb3d968589d8 1420 #define BF_DMA_EEI_EEI11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI11) & BM_DMA_EEI_EEI11)
Kojto 90:cb3d968589d8 1421
Kojto 90:cb3d968589d8 1422 /*! @brief Set the EEI11 field to a new value. */
Kojto 90:cb3d968589d8 1423 #define BW_DMA_EEI_EEI11(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11) = (v))
Kojto 90:cb3d968589d8 1424 /*@}*/
Kojto 90:cb3d968589d8 1425
Kojto 90:cb3d968589d8 1426 /*!
Kojto 90:cb3d968589d8 1427 * @name Register DMA_EEI, field EEI12[12] (RW)
Kojto 90:cb3d968589d8 1428 *
Kojto 90:cb3d968589d8 1429 * Values:
Kojto 90:cb3d968589d8 1430 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1431 * interrupt
Kojto 90:cb3d968589d8 1432 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1433 * an error interrupt request
Kojto 90:cb3d968589d8 1434 */
Kojto 90:cb3d968589d8 1435 /*@{*/
Kojto 90:cb3d968589d8 1436 #define BP_DMA_EEI_EEI12 (12U) /*!< Bit position for DMA_EEI_EEI12. */
Kojto 90:cb3d968589d8 1437 #define BM_DMA_EEI_EEI12 (0x00001000U) /*!< Bit mask for DMA_EEI_EEI12. */
Kojto 90:cb3d968589d8 1438 #define BS_DMA_EEI_EEI12 (1U) /*!< Bit field size in bits for DMA_EEI_EEI12. */
Kojto 90:cb3d968589d8 1439
Kojto 90:cb3d968589d8 1440 /*! @brief Read current value of the DMA_EEI_EEI12 field. */
Kojto 90:cb3d968589d8 1441 #define BR_DMA_EEI_EEI12(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12))
Kojto 90:cb3d968589d8 1442
Kojto 90:cb3d968589d8 1443 /*! @brief Format value for bitfield DMA_EEI_EEI12. */
Kojto 90:cb3d968589d8 1444 #define BF_DMA_EEI_EEI12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI12) & BM_DMA_EEI_EEI12)
Kojto 90:cb3d968589d8 1445
Kojto 90:cb3d968589d8 1446 /*! @brief Set the EEI12 field to a new value. */
Kojto 90:cb3d968589d8 1447 #define BW_DMA_EEI_EEI12(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12) = (v))
Kojto 90:cb3d968589d8 1448 /*@}*/
Kojto 90:cb3d968589d8 1449
Kojto 90:cb3d968589d8 1450 /*!
Kojto 90:cb3d968589d8 1451 * @name Register DMA_EEI, field EEI13[13] (RW)
Kojto 90:cb3d968589d8 1452 *
Kojto 90:cb3d968589d8 1453 * Values:
Kojto 90:cb3d968589d8 1454 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1455 * interrupt
Kojto 90:cb3d968589d8 1456 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1457 * an error interrupt request
Kojto 90:cb3d968589d8 1458 */
Kojto 90:cb3d968589d8 1459 /*@{*/
Kojto 90:cb3d968589d8 1460 #define BP_DMA_EEI_EEI13 (13U) /*!< Bit position for DMA_EEI_EEI13. */
Kojto 90:cb3d968589d8 1461 #define BM_DMA_EEI_EEI13 (0x00002000U) /*!< Bit mask for DMA_EEI_EEI13. */
Kojto 90:cb3d968589d8 1462 #define BS_DMA_EEI_EEI13 (1U) /*!< Bit field size in bits for DMA_EEI_EEI13. */
Kojto 90:cb3d968589d8 1463
Kojto 90:cb3d968589d8 1464 /*! @brief Read current value of the DMA_EEI_EEI13 field. */
Kojto 90:cb3d968589d8 1465 #define BR_DMA_EEI_EEI13(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13))
Kojto 90:cb3d968589d8 1466
Kojto 90:cb3d968589d8 1467 /*! @brief Format value for bitfield DMA_EEI_EEI13. */
Kojto 90:cb3d968589d8 1468 #define BF_DMA_EEI_EEI13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI13) & BM_DMA_EEI_EEI13)
Kojto 90:cb3d968589d8 1469
Kojto 90:cb3d968589d8 1470 /*! @brief Set the EEI13 field to a new value. */
Kojto 90:cb3d968589d8 1471 #define BW_DMA_EEI_EEI13(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13) = (v))
Kojto 90:cb3d968589d8 1472 /*@}*/
Kojto 90:cb3d968589d8 1473
Kojto 90:cb3d968589d8 1474 /*!
Kojto 90:cb3d968589d8 1475 * @name Register DMA_EEI, field EEI14[14] (RW)
Kojto 90:cb3d968589d8 1476 *
Kojto 90:cb3d968589d8 1477 * Values:
Kojto 90:cb3d968589d8 1478 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1479 * interrupt
Kojto 90:cb3d968589d8 1480 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1481 * an error interrupt request
Kojto 90:cb3d968589d8 1482 */
Kojto 90:cb3d968589d8 1483 /*@{*/
Kojto 90:cb3d968589d8 1484 #define BP_DMA_EEI_EEI14 (14U) /*!< Bit position for DMA_EEI_EEI14. */
Kojto 90:cb3d968589d8 1485 #define BM_DMA_EEI_EEI14 (0x00004000U) /*!< Bit mask for DMA_EEI_EEI14. */
Kojto 90:cb3d968589d8 1486 #define BS_DMA_EEI_EEI14 (1U) /*!< Bit field size in bits for DMA_EEI_EEI14. */
Kojto 90:cb3d968589d8 1487
Kojto 90:cb3d968589d8 1488 /*! @brief Read current value of the DMA_EEI_EEI14 field. */
Kojto 90:cb3d968589d8 1489 #define BR_DMA_EEI_EEI14(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14))
Kojto 90:cb3d968589d8 1490
Kojto 90:cb3d968589d8 1491 /*! @brief Format value for bitfield DMA_EEI_EEI14. */
Kojto 90:cb3d968589d8 1492 #define BF_DMA_EEI_EEI14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI14) & BM_DMA_EEI_EEI14)
Kojto 90:cb3d968589d8 1493
Kojto 90:cb3d968589d8 1494 /*! @brief Set the EEI14 field to a new value. */
Kojto 90:cb3d968589d8 1495 #define BW_DMA_EEI_EEI14(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14) = (v))
Kojto 90:cb3d968589d8 1496 /*@}*/
Kojto 90:cb3d968589d8 1497
Kojto 90:cb3d968589d8 1498 /*!
Kojto 90:cb3d968589d8 1499 * @name Register DMA_EEI, field EEI15[15] (RW)
Kojto 90:cb3d968589d8 1500 *
Kojto 90:cb3d968589d8 1501 * Values:
Kojto 90:cb3d968589d8 1502 * - 0 - The error signal for corresponding channel does not generate an error
Kojto 90:cb3d968589d8 1503 * interrupt
Kojto 90:cb3d968589d8 1504 * - 1 - The assertion of the error signal for corresponding channel generates
Kojto 90:cb3d968589d8 1505 * an error interrupt request
Kojto 90:cb3d968589d8 1506 */
Kojto 90:cb3d968589d8 1507 /*@{*/
Kojto 90:cb3d968589d8 1508 #define BP_DMA_EEI_EEI15 (15U) /*!< Bit position for DMA_EEI_EEI15. */
Kojto 90:cb3d968589d8 1509 #define BM_DMA_EEI_EEI15 (0x00008000U) /*!< Bit mask for DMA_EEI_EEI15. */
Kojto 90:cb3d968589d8 1510 #define BS_DMA_EEI_EEI15 (1U) /*!< Bit field size in bits for DMA_EEI_EEI15. */
Kojto 90:cb3d968589d8 1511
Kojto 90:cb3d968589d8 1512 /*! @brief Read current value of the DMA_EEI_EEI15 field. */
Kojto 90:cb3d968589d8 1513 #define BR_DMA_EEI_EEI15(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15))
Kojto 90:cb3d968589d8 1514
Kojto 90:cb3d968589d8 1515 /*! @brief Format value for bitfield DMA_EEI_EEI15. */
Kojto 90:cb3d968589d8 1516 #define BF_DMA_EEI_EEI15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI15) & BM_DMA_EEI_EEI15)
Kojto 90:cb3d968589d8 1517
Kojto 90:cb3d968589d8 1518 /*! @brief Set the EEI15 field to a new value. */
Kojto 90:cb3d968589d8 1519 #define BW_DMA_EEI_EEI15(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15) = (v))
Kojto 90:cb3d968589d8 1520 /*@}*/
Kojto 90:cb3d968589d8 1521
Kojto 90:cb3d968589d8 1522 /*******************************************************************************
Kojto 90:cb3d968589d8 1523 * HW_DMA_CEEI - Clear Enable Error Interrupt Register
Kojto 90:cb3d968589d8 1524 ******************************************************************************/
Kojto 90:cb3d968589d8 1525
Kojto 90:cb3d968589d8 1526 /*!
Kojto 90:cb3d968589d8 1527 * @brief HW_DMA_CEEI - Clear Enable Error Interrupt Register (WO)
Kojto 90:cb3d968589d8 1528 *
Kojto 90:cb3d968589d8 1529 * Reset value: 0x00U
Kojto 90:cb3d968589d8 1530 *
Kojto 90:cb3d968589d8 1531 * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
Kojto 90:cb3d968589d8 1532 * the EEI to disable the error interrupt for a given channel. The data value on a
Kojto 90:cb3d968589d8 1533 * register write causes the corresponding bit in the EEI to be cleared. Setting
Kojto 90:cb3d968589d8 1534 * the CAEE bit provides a global clear function, forcing the EEI contents to be
Kojto 90:cb3d968589d8 1535 * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
Kojto 90:cb3d968589d8 1536 * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
Kojto 90:cb3d968589d8 1537 * Reads of this register return all zeroes.
Kojto 90:cb3d968589d8 1538 */
Kojto 90:cb3d968589d8 1539 typedef union _hw_dma_ceei
Kojto 90:cb3d968589d8 1540 {
Kojto 90:cb3d968589d8 1541 uint8_t U;
Kojto 90:cb3d968589d8 1542 struct _hw_dma_ceei_bitfields
Kojto 90:cb3d968589d8 1543 {
Kojto 90:cb3d968589d8 1544 uint8_t CEEI : 4; /*!< [3:0] Clear Enable Error Interrupt */
Kojto 90:cb3d968589d8 1545 uint8_t RESERVED0 : 2; /*!< [5:4] */
Kojto 90:cb3d968589d8 1546 uint8_t CAEE : 1; /*!< [6] Clear All Enable Error Interrupts */
Kojto 90:cb3d968589d8 1547 uint8_t NOP : 1; /*!< [7] No Op enable */
Kojto 90:cb3d968589d8 1548 } B;
Kojto 90:cb3d968589d8 1549 } hw_dma_ceei_t;
Kojto 90:cb3d968589d8 1550
Kojto 90:cb3d968589d8 1551 /*!
Kojto 90:cb3d968589d8 1552 * @name Constants and macros for entire DMA_CEEI register
Kojto 90:cb3d968589d8 1553 */
Kojto 90:cb3d968589d8 1554 /*@{*/
Kojto 90:cb3d968589d8 1555 #define HW_DMA_CEEI_ADDR(x) ((x) + 0x18U)
Kojto 90:cb3d968589d8 1556
Kojto 90:cb3d968589d8 1557 #define HW_DMA_CEEI(x) (*(__O hw_dma_ceei_t *) HW_DMA_CEEI_ADDR(x))
Kojto 90:cb3d968589d8 1558 #define HW_DMA_CEEI_RD(x) (HW_DMA_CEEI(x).U)
Kojto 90:cb3d968589d8 1559 #define HW_DMA_CEEI_WR(x, v) (HW_DMA_CEEI(x).U = (v))
Kojto 90:cb3d968589d8 1560 /*@}*/
Kojto 90:cb3d968589d8 1561
Kojto 90:cb3d968589d8 1562 /*
Kojto 90:cb3d968589d8 1563 * Constants & macros for individual DMA_CEEI bitfields
Kojto 90:cb3d968589d8 1564 */
Kojto 90:cb3d968589d8 1565
Kojto 90:cb3d968589d8 1566 /*!
Kojto 90:cb3d968589d8 1567 * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
Kojto 90:cb3d968589d8 1568 *
Kojto 90:cb3d968589d8 1569 * Clears the corresponding bit in EEI
Kojto 90:cb3d968589d8 1570 */
Kojto 90:cb3d968589d8 1571 /*@{*/
Kojto 90:cb3d968589d8 1572 #define BP_DMA_CEEI_CEEI (0U) /*!< Bit position for DMA_CEEI_CEEI. */
Kojto 90:cb3d968589d8 1573 #define BM_DMA_CEEI_CEEI (0x0FU) /*!< Bit mask for DMA_CEEI_CEEI. */
Kojto 90:cb3d968589d8 1574 #define BS_DMA_CEEI_CEEI (4U) /*!< Bit field size in bits for DMA_CEEI_CEEI. */
Kojto 90:cb3d968589d8 1575
Kojto 90:cb3d968589d8 1576 /*! @brief Format value for bitfield DMA_CEEI_CEEI. */
Kojto 90:cb3d968589d8 1577 #define BF_DMA_CEEI_CEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CEEI) & BM_DMA_CEEI_CEEI)
Kojto 90:cb3d968589d8 1578
Kojto 90:cb3d968589d8 1579 /*! @brief Set the CEEI field to a new value. */
Kojto 90:cb3d968589d8 1580 #define BW_DMA_CEEI_CEEI(x, v) (HW_DMA_CEEI_WR(x, (HW_DMA_CEEI_RD(x) & ~BM_DMA_CEEI_CEEI) | BF_DMA_CEEI_CEEI(v)))
Kojto 90:cb3d968589d8 1581 /*@}*/
Kojto 90:cb3d968589d8 1582
Kojto 90:cb3d968589d8 1583 /*!
Kojto 90:cb3d968589d8 1584 * @name Register DMA_CEEI, field CAEE[6] (WORZ)
Kojto 90:cb3d968589d8 1585 *
Kojto 90:cb3d968589d8 1586 * Values:
Kojto 90:cb3d968589d8 1587 * - 0 - Clear only the EEI bit specified in the CEEI field
Kojto 90:cb3d968589d8 1588 * - 1 - Clear all bits in EEI
Kojto 90:cb3d968589d8 1589 */
Kojto 90:cb3d968589d8 1590 /*@{*/
Kojto 90:cb3d968589d8 1591 #define BP_DMA_CEEI_CAEE (6U) /*!< Bit position for DMA_CEEI_CAEE. */
Kojto 90:cb3d968589d8 1592 #define BM_DMA_CEEI_CAEE (0x40U) /*!< Bit mask for DMA_CEEI_CAEE. */
Kojto 90:cb3d968589d8 1593 #define BS_DMA_CEEI_CAEE (1U) /*!< Bit field size in bits for DMA_CEEI_CAEE. */
Kojto 90:cb3d968589d8 1594
Kojto 90:cb3d968589d8 1595 /*! @brief Format value for bitfield DMA_CEEI_CAEE. */
Kojto 90:cb3d968589d8 1596 #define BF_DMA_CEEI_CAEE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CAEE) & BM_DMA_CEEI_CAEE)
Kojto 90:cb3d968589d8 1597
Kojto 90:cb3d968589d8 1598 /*! @brief Set the CAEE field to a new value. */
Kojto 90:cb3d968589d8 1599 #define BW_DMA_CEEI_CAEE(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_CAEE) = (v))
Kojto 90:cb3d968589d8 1600 /*@}*/
Kojto 90:cb3d968589d8 1601
Kojto 90:cb3d968589d8 1602 /*!
Kojto 90:cb3d968589d8 1603 * @name Register DMA_CEEI, field NOP[7] (WORZ)
Kojto 90:cb3d968589d8 1604 *
Kojto 90:cb3d968589d8 1605 * Values:
Kojto 90:cb3d968589d8 1606 * - 0 - Normal operation
Kojto 90:cb3d968589d8 1607 * - 1 - No operation, ignore the other bits in this register
Kojto 90:cb3d968589d8 1608 */
Kojto 90:cb3d968589d8 1609 /*@{*/
Kojto 90:cb3d968589d8 1610 #define BP_DMA_CEEI_NOP (7U) /*!< Bit position for DMA_CEEI_NOP. */
Kojto 90:cb3d968589d8 1611 #define BM_DMA_CEEI_NOP (0x80U) /*!< Bit mask for DMA_CEEI_NOP. */
Kojto 90:cb3d968589d8 1612 #define BS_DMA_CEEI_NOP (1U) /*!< Bit field size in bits for DMA_CEEI_NOP. */
Kojto 90:cb3d968589d8 1613
Kojto 90:cb3d968589d8 1614 /*! @brief Format value for bitfield DMA_CEEI_NOP. */
Kojto 90:cb3d968589d8 1615 #define BF_DMA_CEEI_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_NOP) & BM_DMA_CEEI_NOP)
Kojto 90:cb3d968589d8 1616
Kojto 90:cb3d968589d8 1617 /*! @brief Set the NOP field to a new value. */
Kojto 90:cb3d968589d8 1618 #define BW_DMA_CEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_NOP) = (v))
Kojto 90:cb3d968589d8 1619 /*@}*/
Kojto 90:cb3d968589d8 1620
Kojto 90:cb3d968589d8 1621 /*******************************************************************************
Kojto 90:cb3d968589d8 1622 * HW_DMA_SEEI - Set Enable Error Interrupt Register
Kojto 90:cb3d968589d8 1623 ******************************************************************************/
Kojto 90:cb3d968589d8 1624
Kojto 90:cb3d968589d8 1625 /*!
Kojto 90:cb3d968589d8 1626 * @brief HW_DMA_SEEI - Set Enable Error Interrupt Register (WO)
Kojto 90:cb3d968589d8 1627 *
Kojto 90:cb3d968589d8 1628 * Reset value: 0x00U
Kojto 90:cb3d968589d8 1629 *
Kojto 90:cb3d968589d8 1630 * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
Kojto 90:cb3d968589d8 1631 * EEI to enable the error interrupt for a given channel. The data value on a
Kojto 90:cb3d968589d8 1632 * register write causes the corresponding bit in the EEI to be set. Setting the
Kojto 90:cb3d968589d8 1633 * SAEE bit provides a global set function, forcing the entire EEI contents to be
Kojto 90:cb3d968589d8 1634 * set. If the NOP bit is set, the command is ignored. This allows you to write
Kojto 90:cb3d968589d8 1635 * multiple-byte registers as a 32-bit word. Reads of this register return all
Kojto 90:cb3d968589d8 1636 * zeroes.
Kojto 90:cb3d968589d8 1637 */
Kojto 90:cb3d968589d8 1638 typedef union _hw_dma_seei
Kojto 90:cb3d968589d8 1639 {
Kojto 90:cb3d968589d8 1640 uint8_t U;
Kojto 90:cb3d968589d8 1641 struct _hw_dma_seei_bitfields
Kojto 90:cb3d968589d8 1642 {
Kojto 90:cb3d968589d8 1643 uint8_t SEEI : 4; /*!< [3:0] Set Enable Error Interrupt */
Kojto 90:cb3d968589d8 1644 uint8_t RESERVED0 : 2; /*!< [5:4] */
Kojto 90:cb3d968589d8 1645 uint8_t SAEE : 1; /*!< [6] Sets All Enable Error Interrupts */
Kojto 90:cb3d968589d8 1646 uint8_t NOP : 1; /*!< [7] No Op enable */
Kojto 90:cb3d968589d8 1647 } B;
Kojto 90:cb3d968589d8 1648 } hw_dma_seei_t;
Kojto 90:cb3d968589d8 1649
Kojto 90:cb3d968589d8 1650 /*!
Kojto 90:cb3d968589d8 1651 * @name Constants and macros for entire DMA_SEEI register
Kojto 90:cb3d968589d8 1652 */
Kojto 90:cb3d968589d8 1653 /*@{*/
Kojto 90:cb3d968589d8 1654 #define HW_DMA_SEEI_ADDR(x) ((x) + 0x19U)
Kojto 90:cb3d968589d8 1655
Kojto 90:cb3d968589d8 1656 #define HW_DMA_SEEI(x) (*(__O hw_dma_seei_t *) HW_DMA_SEEI_ADDR(x))
Kojto 90:cb3d968589d8 1657 #define HW_DMA_SEEI_RD(x) (HW_DMA_SEEI(x).U)
Kojto 90:cb3d968589d8 1658 #define HW_DMA_SEEI_WR(x, v) (HW_DMA_SEEI(x).U = (v))
Kojto 90:cb3d968589d8 1659 /*@}*/
Kojto 90:cb3d968589d8 1660
Kojto 90:cb3d968589d8 1661 /*
Kojto 90:cb3d968589d8 1662 * Constants & macros for individual DMA_SEEI bitfields
Kojto 90:cb3d968589d8 1663 */
Kojto 90:cb3d968589d8 1664
Kojto 90:cb3d968589d8 1665 /*!
Kojto 90:cb3d968589d8 1666 * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
Kojto 90:cb3d968589d8 1667 *
Kojto 90:cb3d968589d8 1668 * Sets the corresponding bit in EEI
Kojto 90:cb3d968589d8 1669 */
Kojto 90:cb3d968589d8 1670 /*@{*/
Kojto 90:cb3d968589d8 1671 #define BP_DMA_SEEI_SEEI (0U) /*!< Bit position for DMA_SEEI_SEEI. */
Kojto 90:cb3d968589d8 1672 #define BM_DMA_SEEI_SEEI (0x0FU) /*!< Bit mask for DMA_SEEI_SEEI. */
Kojto 90:cb3d968589d8 1673 #define BS_DMA_SEEI_SEEI (4U) /*!< Bit field size in bits for DMA_SEEI_SEEI. */
Kojto 90:cb3d968589d8 1674
Kojto 90:cb3d968589d8 1675 /*! @brief Format value for bitfield DMA_SEEI_SEEI. */
Kojto 90:cb3d968589d8 1676 #define BF_DMA_SEEI_SEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SEEI) & BM_DMA_SEEI_SEEI)
Kojto 90:cb3d968589d8 1677
Kojto 90:cb3d968589d8 1678 /*! @brief Set the SEEI field to a new value. */
Kojto 90:cb3d968589d8 1679 #define BW_DMA_SEEI_SEEI(x, v) (HW_DMA_SEEI_WR(x, (HW_DMA_SEEI_RD(x) & ~BM_DMA_SEEI_SEEI) | BF_DMA_SEEI_SEEI(v)))
Kojto 90:cb3d968589d8 1680 /*@}*/
Kojto 90:cb3d968589d8 1681
Kojto 90:cb3d968589d8 1682 /*!
Kojto 90:cb3d968589d8 1683 * @name Register DMA_SEEI, field SAEE[6] (WORZ)
Kojto 90:cb3d968589d8 1684 *
Kojto 90:cb3d968589d8 1685 * Values:
Kojto 90:cb3d968589d8 1686 * - 0 - Set only the EEI bit specified in the SEEI field.
Kojto 90:cb3d968589d8 1687 * - 1 - Sets all bits in EEI
Kojto 90:cb3d968589d8 1688 */
Kojto 90:cb3d968589d8 1689 /*@{*/
Kojto 90:cb3d968589d8 1690 #define BP_DMA_SEEI_SAEE (6U) /*!< Bit position for DMA_SEEI_SAEE. */
Kojto 90:cb3d968589d8 1691 #define BM_DMA_SEEI_SAEE (0x40U) /*!< Bit mask for DMA_SEEI_SAEE. */
Kojto 90:cb3d968589d8 1692 #define BS_DMA_SEEI_SAEE (1U) /*!< Bit field size in bits for DMA_SEEI_SAEE. */
Kojto 90:cb3d968589d8 1693
Kojto 90:cb3d968589d8 1694 /*! @brief Format value for bitfield DMA_SEEI_SAEE. */
Kojto 90:cb3d968589d8 1695 #define BF_DMA_SEEI_SAEE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SAEE) & BM_DMA_SEEI_SAEE)
Kojto 90:cb3d968589d8 1696
Kojto 90:cb3d968589d8 1697 /*! @brief Set the SAEE field to a new value. */
Kojto 90:cb3d968589d8 1698 #define BW_DMA_SEEI_SAEE(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_SAEE) = (v))
Kojto 90:cb3d968589d8 1699 /*@}*/
Kojto 90:cb3d968589d8 1700
Kojto 90:cb3d968589d8 1701 /*!
Kojto 90:cb3d968589d8 1702 * @name Register DMA_SEEI, field NOP[7] (WORZ)
Kojto 90:cb3d968589d8 1703 *
Kojto 90:cb3d968589d8 1704 * Values:
Kojto 90:cb3d968589d8 1705 * - 0 - Normal operation
Kojto 90:cb3d968589d8 1706 * - 1 - No operation, ignore the other bits in this register
Kojto 90:cb3d968589d8 1707 */
Kojto 90:cb3d968589d8 1708 /*@{*/
Kojto 90:cb3d968589d8 1709 #define BP_DMA_SEEI_NOP (7U) /*!< Bit position for DMA_SEEI_NOP. */
Kojto 90:cb3d968589d8 1710 #define BM_DMA_SEEI_NOP (0x80U) /*!< Bit mask for DMA_SEEI_NOP. */
Kojto 90:cb3d968589d8 1711 #define BS_DMA_SEEI_NOP (1U) /*!< Bit field size in bits for DMA_SEEI_NOP. */
Kojto 90:cb3d968589d8 1712
Kojto 90:cb3d968589d8 1713 /*! @brief Format value for bitfield DMA_SEEI_NOP. */
Kojto 90:cb3d968589d8 1714 #define BF_DMA_SEEI_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_NOP) & BM_DMA_SEEI_NOP)
Kojto 90:cb3d968589d8 1715
Kojto 90:cb3d968589d8 1716 /*! @brief Set the NOP field to a new value. */
Kojto 90:cb3d968589d8 1717 #define BW_DMA_SEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_NOP) = (v))
Kojto 90:cb3d968589d8 1718 /*@}*/
Kojto 90:cb3d968589d8 1719
Kojto 90:cb3d968589d8 1720 /*******************************************************************************
Kojto 90:cb3d968589d8 1721 * HW_DMA_CERQ - Clear Enable Request Register
Kojto 90:cb3d968589d8 1722 ******************************************************************************/
Kojto 90:cb3d968589d8 1723
Kojto 90:cb3d968589d8 1724 /*!
Kojto 90:cb3d968589d8 1725 * @brief HW_DMA_CERQ - Clear Enable Request Register (WO)
Kojto 90:cb3d968589d8 1726 *
Kojto 90:cb3d968589d8 1727 * Reset value: 0x00U
Kojto 90:cb3d968589d8 1728 *
Kojto 90:cb3d968589d8 1729 * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
Kojto 90:cb3d968589d8 1730 * the ERQ to disable the DMA request for a given channel. The data value on a
Kojto 90:cb3d968589d8 1731 * register write causes the corresponding bit in the ERQ to be cleared. Setting the
Kojto 90:cb3d968589d8 1732 * CAER bit provides a global clear function, forcing the entire contents of the
Kojto 90:cb3d968589d8 1733 * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
Kojto 90:cb3d968589d8 1734 * command is ignored. This allows you to write multiple-byte registers as a 32-bit
Kojto 90:cb3d968589d8 1735 * word. Reads of this register return all zeroes.
Kojto 90:cb3d968589d8 1736 */
Kojto 90:cb3d968589d8 1737 typedef union _hw_dma_cerq
Kojto 90:cb3d968589d8 1738 {
Kojto 90:cb3d968589d8 1739 uint8_t U;
Kojto 90:cb3d968589d8 1740 struct _hw_dma_cerq_bitfields
Kojto 90:cb3d968589d8 1741 {
Kojto 90:cb3d968589d8 1742 uint8_t CERQ : 4; /*!< [3:0] Clear Enable Request */
Kojto 90:cb3d968589d8 1743 uint8_t RESERVED0 : 2; /*!< [5:4] */
Kojto 90:cb3d968589d8 1744 uint8_t CAER : 1; /*!< [6] Clear All Enable Requests */
Kojto 90:cb3d968589d8 1745 uint8_t NOP : 1; /*!< [7] No Op enable */
Kojto 90:cb3d968589d8 1746 } B;
Kojto 90:cb3d968589d8 1747 } hw_dma_cerq_t;
Kojto 90:cb3d968589d8 1748
Kojto 90:cb3d968589d8 1749 /*!
Kojto 90:cb3d968589d8 1750 * @name Constants and macros for entire DMA_CERQ register
Kojto 90:cb3d968589d8 1751 */
Kojto 90:cb3d968589d8 1752 /*@{*/
Kojto 90:cb3d968589d8 1753 #define HW_DMA_CERQ_ADDR(x) ((x) + 0x1AU)
Kojto 90:cb3d968589d8 1754
Kojto 90:cb3d968589d8 1755 #define HW_DMA_CERQ(x) (*(__O hw_dma_cerq_t *) HW_DMA_CERQ_ADDR(x))
Kojto 90:cb3d968589d8 1756 #define HW_DMA_CERQ_RD(x) (HW_DMA_CERQ(x).U)
Kojto 90:cb3d968589d8 1757 #define HW_DMA_CERQ_WR(x, v) (HW_DMA_CERQ(x).U = (v))
Kojto 90:cb3d968589d8 1758 /*@}*/
Kojto 90:cb3d968589d8 1759
Kojto 90:cb3d968589d8 1760 /*
Kojto 90:cb3d968589d8 1761 * Constants & macros for individual DMA_CERQ bitfields
Kojto 90:cb3d968589d8 1762 */
Kojto 90:cb3d968589d8 1763
Kojto 90:cb3d968589d8 1764 /*!
Kojto 90:cb3d968589d8 1765 * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
Kojto 90:cb3d968589d8 1766 *
Kojto 90:cb3d968589d8 1767 * Clears the corresponding bit in ERQ
Kojto 90:cb3d968589d8 1768 */
Kojto 90:cb3d968589d8 1769 /*@{*/
Kojto 90:cb3d968589d8 1770 #define BP_DMA_CERQ_CERQ (0U) /*!< Bit position for DMA_CERQ_CERQ. */
Kojto 90:cb3d968589d8 1771 #define BM_DMA_CERQ_CERQ (0x0FU) /*!< Bit mask for DMA_CERQ_CERQ. */
Kojto 90:cb3d968589d8 1772 #define BS_DMA_CERQ_CERQ (4U) /*!< Bit field size in bits for DMA_CERQ_CERQ. */
Kojto 90:cb3d968589d8 1773
Kojto 90:cb3d968589d8 1774 /*! @brief Format value for bitfield DMA_CERQ_CERQ. */
Kojto 90:cb3d968589d8 1775 #define BF_DMA_CERQ_CERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CERQ) & BM_DMA_CERQ_CERQ)
Kojto 90:cb3d968589d8 1776
Kojto 90:cb3d968589d8 1777 /*! @brief Set the CERQ field to a new value. */
Kojto 90:cb3d968589d8 1778 #define BW_DMA_CERQ_CERQ(x, v) (HW_DMA_CERQ_WR(x, (HW_DMA_CERQ_RD(x) & ~BM_DMA_CERQ_CERQ) | BF_DMA_CERQ_CERQ(v)))
Kojto 90:cb3d968589d8 1779 /*@}*/
Kojto 90:cb3d968589d8 1780
Kojto 90:cb3d968589d8 1781 /*!
Kojto 90:cb3d968589d8 1782 * @name Register DMA_CERQ, field CAER[6] (WORZ)
Kojto 90:cb3d968589d8 1783 *
Kojto 90:cb3d968589d8 1784 * Values:
Kojto 90:cb3d968589d8 1785 * - 0 - Clear only the ERQ bit specified in the CERQ field
Kojto 90:cb3d968589d8 1786 * - 1 - Clear all bits in ERQ
Kojto 90:cb3d968589d8 1787 */
Kojto 90:cb3d968589d8 1788 /*@{*/
Kojto 90:cb3d968589d8 1789 #define BP_DMA_CERQ_CAER (6U) /*!< Bit position for DMA_CERQ_CAER. */
Kojto 90:cb3d968589d8 1790 #define BM_DMA_CERQ_CAER (0x40U) /*!< Bit mask for DMA_CERQ_CAER. */
Kojto 90:cb3d968589d8 1791 #define BS_DMA_CERQ_CAER (1U) /*!< Bit field size in bits for DMA_CERQ_CAER. */
Kojto 90:cb3d968589d8 1792
Kojto 90:cb3d968589d8 1793 /*! @brief Format value for bitfield DMA_CERQ_CAER. */
Kojto 90:cb3d968589d8 1794 #define BF_DMA_CERQ_CAER(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CAER) & BM_DMA_CERQ_CAER)
Kojto 90:cb3d968589d8 1795
Kojto 90:cb3d968589d8 1796 /*! @brief Set the CAER field to a new value. */
Kojto 90:cb3d968589d8 1797 #define BW_DMA_CERQ_CAER(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_CAER) = (v))
Kojto 90:cb3d968589d8 1798 /*@}*/
Kojto 90:cb3d968589d8 1799
Kojto 90:cb3d968589d8 1800 /*!
Kojto 90:cb3d968589d8 1801 * @name Register DMA_CERQ, field NOP[7] (WORZ)
Kojto 90:cb3d968589d8 1802 *
Kojto 90:cb3d968589d8 1803 * Values:
Kojto 90:cb3d968589d8 1804 * - 0 - Normal operation
Kojto 90:cb3d968589d8 1805 * - 1 - No operation, ignore the other bits in this register
Kojto 90:cb3d968589d8 1806 */
Kojto 90:cb3d968589d8 1807 /*@{*/
Kojto 90:cb3d968589d8 1808 #define BP_DMA_CERQ_NOP (7U) /*!< Bit position for DMA_CERQ_NOP. */
Kojto 90:cb3d968589d8 1809 #define BM_DMA_CERQ_NOP (0x80U) /*!< Bit mask for DMA_CERQ_NOP. */
Kojto 90:cb3d968589d8 1810 #define BS_DMA_CERQ_NOP (1U) /*!< Bit field size in bits for DMA_CERQ_NOP. */
Kojto 90:cb3d968589d8 1811
Kojto 90:cb3d968589d8 1812 /*! @brief Format value for bitfield DMA_CERQ_NOP. */
Kojto 90:cb3d968589d8 1813 #define BF_DMA_CERQ_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_NOP) & BM_DMA_CERQ_NOP)
Kojto 90:cb3d968589d8 1814
Kojto 90:cb3d968589d8 1815 /*! @brief Set the NOP field to a new value. */
Kojto 90:cb3d968589d8 1816 #define BW_DMA_CERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_NOP) = (v))
Kojto 90:cb3d968589d8 1817 /*@}*/
Kojto 90:cb3d968589d8 1818
Kojto 90:cb3d968589d8 1819 /*******************************************************************************
Kojto 90:cb3d968589d8 1820 * HW_DMA_SERQ - Set Enable Request Register
Kojto 90:cb3d968589d8 1821 ******************************************************************************/
Kojto 90:cb3d968589d8 1822
Kojto 90:cb3d968589d8 1823 /*!
Kojto 90:cb3d968589d8 1824 * @brief HW_DMA_SERQ - Set Enable Request Register (WO)
Kojto 90:cb3d968589d8 1825 *
Kojto 90:cb3d968589d8 1826 * Reset value: 0x00U
Kojto 90:cb3d968589d8 1827 *
Kojto 90:cb3d968589d8 1828 * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
Kojto 90:cb3d968589d8 1829 * ERQ to enable the DMA request for a given channel. The data value on a
Kojto 90:cb3d968589d8 1830 * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
Kojto 90:cb3d968589d8 1831 * bit provides a global set function, forcing the entire contents of ERQ to be
Kojto 90:cb3d968589d8 1832 * set. If the NOP bit is set, the command is ignored. This allows you to write
Kojto 90:cb3d968589d8 1833 * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
Kojto 90:cb3d968589d8 1834 */
Kojto 90:cb3d968589d8 1835 typedef union _hw_dma_serq
Kojto 90:cb3d968589d8 1836 {
Kojto 90:cb3d968589d8 1837 uint8_t U;
Kojto 90:cb3d968589d8 1838 struct _hw_dma_serq_bitfields
Kojto 90:cb3d968589d8 1839 {
Kojto 90:cb3d968589d8 1840 uint8_t SERQ : 4; /*!< [3:0] Set enable request */
Kojto 90:cb3d968589d8 1841 uint8_t RESERVED0 : 2; /*!< [5:4] */
Kojto 90:cb3d968589d8 1842 uint8_t SAER : 1; /*!< [6] Set All Enable Requests */
Kojto 90:cb3d968589d8 1843 uint8_t NOP : 1; /*!< [7] No Op enable */
Kojto 90:cb3d968589d8 1844 } B;
Kojto 90:cb3d968589d8 1845 } hw_dma_serq_t;
Kojto 90:cb3d968589d8 1846
Kojto 90:cb3d968589d8 1847 /*!
Kojto 90:cb3d968589d8 1848 * @name Constants and macros for entire DMA_SERQ register
Kojto 90:cb3d968589d8 1849 */
Kojto 90:cb3d968589d8 1850 /*@{*/
Kojto 90:cb3d968589d8 1851 #define HW_DMA_SERQ_ADDR(x) ((x) + 0x1BU)
Kojto 90:cb3d968589d8 1852
Kojto 90:cb3d968589d8 1853 #define HW_DMA_SERQ(x) (*(__O hw_dma_serq_t *) HW_DMA_SERQ_ADDR(x))
Kojto 90:cb3d968589d8 1854 #define HW_DMA_SERQ_RD(x) (HW_DMA_SERQ(x).U)
Kojto 90:cb3d968589d8 1855 #define HW_DMA_SERQ_WR(x, v) (HW_DMA_SERQ(x).U = (v))
Kojto 90:cb3d968589d8 1856 /*@}*/
Kojto 90:cb3d968589d8 1857
Kojto 90:cb3d968589d8 1858 /*
Kojto 90:cb3d968589d8 1859 * Constants & macros for individual DMA_SERQ bitfields
Kojto 90:cb3d968589d8 1860 */
Kojto 90:cb3d968589d8 1861
Kojto 90:cb3d968589d8 1862 /*!
Kojto 90:cb3d968589d8 1863 * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
Kojto 90:cb3d968589d8 1864 *
Kojto 90:cb3d968589d8 1865 * Sets the corresponding bit in ERQ
Kojto 90:cb3d968589d8 1866 */
Kojto 90:cb3d968589d8 1867 /*@{*/
Kojto 90:cb3d968589d8 1868 #define BP_DMA_SERQ_SERQ (0U) /*!< Bit position for DMA_SERQ_SERQ. */
Kojto 90:cb3d968589d8 1869 #define BM_DMA_SERQ_SERQ (0x0FU) /*!< Bit mask for DMA_SERQ_SERQ. */
Kojto 90:cb3d968589d8 1870 #define BS_DMA_SERQ_SERQ (4U) /*!< Bit field size in bits for DMA_SERQ_SERQ. */
Kojto 90:cb3d968589d8 1871
Kojto 90:cb3d968589d8 1872 /*! @brief Format value for bitfield DMA_SERQ_SERQ. */
Kojto 90:cb3d968589d8 1873 #define BF_DMA_SERQ_SERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SERQ) & BM_DMA_SERQ_SERQ)
Kojto 90:cb3d968589d8 1874
Kojto 90:cb3d968589d8 1875 /*! @brief Set the SERQ field to a new value. */
Kojto 90:cb3d968589d8 1876 #define BW_DMA_SERQ_SERQ(x, v) (HW_DMA_SERQ_WR(x, (HW_DMA_SERQ_RD(x) & ~BM_DMA_SERQ_SERQ) | BF_DMA_SERQ_SERQ(v)))
Kojto 90:cb3d968589d8 1877 /*@}*/
Kojto 90:cb3d968589d8 1878
Kojto 90:cb3d968589d8 1879 /*!
Kojto 90:cb3d968589d8 1880 * @name Register DMA_SERQ, field SAER[6] (WORZ)
Kojto 90:cb3d968589d8 1881 *
Kojto 90:cb3d968589d8 1882 * Values:
Kojto 90:cb3d968589d8 1883 * - 0 - Set only the ERQ bit specified in the SERQ field
Kojto 90:cb3d968589d8 1884 * - 1 - Set all bits in ERQ
Kojto 90:cb3d968589d8 1885 */
Kojto 90:cb3d968589d8 1886 /*@{*/
Kojto 90:cb3d968589d8 1887 #define BP_DMA_SERQ_SAER (6U) /*!< Bit position for DMA_SERQ_SAER. */
Kojto 90:cb3d968589d8 1888 #define BM_DMA_SERQ_SAER (0x40U) /*!< Bit mask for DMA_SERQ_SAER. */
Kojto 90:cb3d968589d8 1889 #define BS_DMA_SERQ_SAER (1U) /*!< Bit field size in bits for DMA_SERQ_SAER. */
Kojto 90:cb3d968589d8 1890
Kojto 90:cb3d968589d8 1891 /*! @brief Format value for bitfield DMA_SERQ_SAER. */
Kojto 90:cb3d968589d8 1892 #define BF_DMA_SERQ_SAER(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SAER) & BM_DMA_SERQ_SAER)
Kojto 90:cb3d968589d8 1893
Kojto 90:cb3d968589d8 1894 /*! @brief Set the SAER field to a new value. */
Kojto 90:cb3d968589d8 1895 #define BW_DMA_SERQ_SAER(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_SAER) = (v))
Kojto 90:cb3d968589d8 1896 /*@}*/
Kojto 90:cb3d968589d8 1897
Kojto 90:cb3d968589d8 1898 /*!
Kojto 90:cb3d968589d8 1899 * @name Register DMA_SERQ, field NOP[7] (WORZ)
Kojto 90:cb3d968589d8 1900 *
Kojto 90:cb3d968589d8 1901 * Values:
Kojto 90:cb3d968589d8 1902 * - 0 - Normal operation
Kojto 90:cb3d968589d8 1903 * - 1 - No operation, ignore the other bits in this register
Kojto 90:cb3d968589d8 1904 */
Kojto 90:cb3d968589d8 1905 /*@{*/
Kojto 90:cb3d968589d8 1906 #define BP_DMA_SERQ_NOP (7U) /*!< Bit position for DMA_SERQ_NOP. */
Kojto 90:cb3d968589d8 1907 #define BM_DMA_SERQ_NOP (0x80U) /*!< Bit mask for DMA_SERQ_NOP. */
Kojto 90:cb3d968589d8 1908 #define BS_DMA_SERQ_NOP (1U) /*!< Bit field size in bits for DMA_SERQ_NOP. */
Kojto 90:cb3d968589d8 1909
Kojto 90:cb3d968589d8 1910 /*! @brief Format value for bitfield DMA_SERQ_NOP. */
Kojto 90:cb3d968589d8 1911 #define BF_DMA_SERQ_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_NOP) & BM_DMA_SERQ_NOP)
Kojto 90:cb3d968589d8 1912
Kojto 90:cb3d968589d8 1913 /*! @brief Set the NOP field to a new value. */
Kojto 90:cb3d968589d8 1914 #define BW_DMA_SERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_NOP) = (v))
Kojto 90:cb3d968589d8 1915 /*@}*/
Kojto 90:cb3d968589d8 1916
Kojto 90:cb3d968589d8 1917 /*******************************************************************************
Kojto 90:cb3d968589d8 1918 * HW_DMA_CDNE - Clear DONE Status Bit Register
Kojto 90:cb3d968589d8 1919 ******************************************************************************/
Kojto 90:cb3d968589d8 1920
Kojto 90:cb3d968589d8 1921 /*!
Kojto 90:cb3d968589d8 1922 * @brief HW_DMA_CDNE - Clear DONE Status Bit Register (WO)
Kojto 90:cb3d968589d8 1923 *
Kojto 90:cb3d968589d8 1924 * Reset value: 0x00U
Kojto 90:cb3d968589d8 1925 *
Kojto 90:cb3d968589d8 1926 * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
Kojto 90:cb3d968589d8 1927 * the TCD of the given channel. The data value on a register write causes the
Kojto 90:cb3d968589d8 1928 * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
Kojto 90:cb3d968589d8 1929 * the CADN bit provides a global clear function, forcing all DONE bits to be
Kojto 90:cb3d968589d8 1930 * cleared. If the NOP bit is set, the command is ignored. This allows you to write
Kojto 90:cb3d968589d8 1931 * multiple-byte registers as a 32-bit word. Reads of this register return all
Kojto 90:cb3d968589d8 1932 * zeroes.
Kojto 90:cb3d968589d8 1933 */
Kojto 90:cb3d968589d8 1934 typedef union _hw_dma_cdne
Kojto 90:cb3d968589d8 1935 {
Kojto 90:cb3d968589d8 1936 uint8_t U;
Kojto 90:cb3d968589d8 1937 struct _hw_dma_cdne_bitfields
Kojto 90:cb3d968589d8 1938 {
Kojto 90:cb3d968589d8 1939 uint8_t CDNE : 4; /*!< [3:0] Clear DONE Bit */
Kojto 90:cb3d968589d8 1940 uint8_t RESERVED0 : 2; /*!< [5:4] */
Kojto 90:cb3d968589d8 1941 uint8_t CADN : 1; /*!< [6] Clears All DONE Bits */
Kojto 90:cb3d968589d8 1942 uint8_t NOP : 1; /*!< [7] No Op enable */
Kojto 90:cb3d968589d8 1943 } B;
Kojto 90:cb3d968589d8 1944 } hw_dma_cdne_t;
Kojto 90:cb3d968589d8 1945
Kojto 90:cb3d968589d8 1946 /*!
Kojto 90:cb3d968589d8 1947 * @name Constants and macros for entire DMA_CDNE register
Kojto 90:cb3d968589d8 1948 */
Kojto 90:cb3d968589d8 1949 /*@{*/
Kojto 90:cb3d968589d8 1950 #define HW_DMA_CDNE_ADDR(x) ((x) + 0x1CU)
Kojto 90:cb3d968589d8 1951
Kojto 90:cb3d968589d8 1952 #define HW_DMA_CDNE(x) (*(__O hw_dma_cdne_t *) HW_DMA_CDNE_ADDR(x))
Kojto 90:cb3d968589d8 1953 #define HW_DMA_CDNE_RD(x) (HW_DMA_CDNE(x).U)
Kojto 90:cb3d968589d8 1954 #define HW_DMA_CDNE_WR(x, v) (HW_DMA_CDNE(x).U = (v))
Kojto 90:cb3d968589d8 1955 /*@}*/
Kojto 90:cb3d968589d8 1956
Kojto 90:cb3d968589d8 1957 /*
Kojto 90:cb3d968589d8 1958 * Constants & macros for individual DMA_CDNE bitfields
Kojto 90:cb3d968589d8 1959 */
Kojto 90:cb3d968589d8 1960
Kojto 90:cb3d968589d8 1961 /*!
Kojto 90:cb3d968589d8 1962 * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
Kojto 90:cb3d968589d8 1963 *
Kojto 90:cb3d968589d8 1964 * Clears the corresponding bit in TCDn_CSR[DONE]
Kojto 90:cb3d968589d8 1965 */
Kojto 90:cb3d968589d8 1966 /*@{*/
Kojto 90:cb3d968589d8 1967 #define BP_DMA_CDNE_CDNE (0U) /*!< Bit position for DMA_CDNE_CDNE. */
Kojto 90:cb3d968589d8 1968 #define BM_DMA_CDNE_CDNE (0x0FU) /*!< Bit mask for DMA_CDNE_CDNE. */
Kojto 90:cb3d968589d8 1969 #define BS_DMA_CDNE_CDNE (4U) /*!< Bit field size in bits for DMA_CDNE_CDNE. */
Kojto 90:cb3d968589d8 1970
Kojto 90:cb3d968589d8 1971 /*! @brief Format value for bitfield DMA_CDNE_CDNE. */
Kojto 90:cb3d968589d8 1972 #define BF_DMA_CDNE_CDNE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CDNE) & BM_DMA_CDNE_CDNE)
Kojto 90:cb3d968589d8 1973
Kojto 90:cb3d968589d8 1974 /*! @brief Set the CDNE field to a new value. */
Kojto 90:cb3d968589d8 1975 #define BW_DMA_CDNE_CDNE(x, v) (HW_DMA_CDNE_WR(x, (HW_DMA_CDNE_RD(x) & ~BM_DMA_CDNE_CDNE) | BF_DMA_CDNE_CDNE(v)))
Kojto 90:cb3d968589d8 1976 /*@}*/
Kojto 90:cb3d968589d8 1977
Kojto 90:cb3d968589d8 1978 /*!
Kojto 90:cb3d968589d8 1979 * @name Register DMA_CDNE, field CADN[6] (WORZ)
Kojto 90:cb3d968589d8 1980 *
Kojto 90:cb3d968589d8 1981 * Values:
Kojto 90:cb3d968589d8 1982 * - 0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
Kojto 90:cb3d968589d8 1983 * - 1 - Clears all bits in TCDn_CSR[DONE]
Kojto 90:cb3d968589d8 1984 */
Kojto 90:cb3d968589d8 1985 /*@{*/
Kojto 90:cb3d968589d8 1986 #define BP_DMA_CDNE_CADN (6U) /*!< Bit position for DMA_CDNE_CADN. */
Kojto 90:cb3d968589d8 1987 #define BM_DMA_CDNE_CADN (0x40U) /*!< Bit mask for DMA_CDNE_CADN. */
Kojto 90:cb3d968589d8 1988 #define BS_DMA_CDNE_CADN (1U) /*!< Bit field size in bits for DMA_CDNE_CADN. */
Kojto 90:cb3d968589d8 1989
Kojto 90:cb3d968589d8 1990 /*! @brief Format value for bitfield DMA_CDNE_CADN. */
Kojto 90:cb3d968589d8 1991 #define BF_DMA_CDNE_CADN(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CADN) & BM_DMA_CDNE_CADN)
Kojto 90:cb3d968589d8 1992
Kojto 90:cb3d968589d8 1993 /*! @brief Set the CADN field to a new value. */
Kojto 90:cb3d968589d8 1994 #define BW_DMA_CDNE_CADN(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_CADN) = (v))
Kojto 90:cb3d968589d8 1995 /*@}*/
Kojto 90:cb3d968589d8 1996
Kojto 90:cb3d968589d8 1997 /*!
Kojto 90:cb3d968589d8 1998 * @name Register DMA_CDNE, field NOP[7] (WORZ)
Kojto 90:cb3d968589d8 1999 *
Kojto 90:cb3d968589d8 2000 * Values:
Kojto 90:cb3d968589d8 2001 * - 0 - Normal operation
Kojto 90:cb3d968589d8 2002 * - 1 - No operation, ignore the other bits in this register
Kojto 90:cb3d968589d8 2003 */
Kojto 90:cb3d968589d8 2004 /*@{*/
Kojto 90:cb3d968589d8 2005 #define BP_DMA_CDNE_NOP (7U) /*!< Bit position for DMA_CDNE_NOP. */
Kojto 90:cb3d968589d8 2006 #define BM_DMA_CDNE_NOP (0x80U) /*!< Bit mask for DMA_CDNE_NOP. */
Kojto 90:cb3d968589d8 2007 #define BS_DMA_CDNE_NOP (1U) /*!< Bit field size in bits for DMA_CDNE_NOP. */
Kojto 90:cb3d968589d8 2008
Kojto 90:cb3d968589d8 2009 /*! @brief Format value for bitfield DMA_CDNE_NOP. */
Kojto 90:cb3d968589d8 2010 #define BF_DMA_CDNE_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_NOP) & BM_DMA_CDNE_NOP)
Kojto 90:cb3d968589d8 2011
Kojto 90:cb3d968589d8 2012 /*! @brief Set the NOP field to a new value. */
Kojto 90:cb3d968589d8 2013 #define BW_DMA_CDNE_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_NOP) = (v))
Kojto 90:cb3d968589d8 2014 /*@}*/
Kojto 90:cb3d968589d8 2015
Kojto 90:cb3d968589d8 2016 /*******************************************************************************
Kojto 90:cb3d968589d8 2017 * HW_DMA_SSRT - Set START Bit Register
Kojto 90:cb3d968589d8 2018 ******************************************************************************/
Kojto 90:cb3d968589d8 2019
Kojto 90:cb3d968589d8 2020 /*!
Kojto 90:cb3d968589d8 2021 * @brief HW_DMA_SSRT - Set START Bit Register (WO)
Kojto 90:cb3d968589d8 2022 *
Kojto 90:cb3d968589d8 2023 * Reset value: 0x00U
Kojto 90:cb3d968589d8 2024 *
Kojto 90:cb3d968589d8 2025 * The SSRT provides a simple memory-mapped mechanism to set the START bit in
Kojto 90:cb3d968589d8 2026 * the TCD of the given channel. The data value on a register write causes the
Kojto 90:cb3d968589d8 2027 * START bit in the corresponding transfer control descriptor to be set. Setting the
Kojto 90:cb3d968589d8 2028 * SAST bit provides a global set function, forcing all START bits to be set. If
Kojto 90:cb3d968589d8 2029 * the NOP bit is set, the command is ignored. This allows you to write
Kojto 90:cb3d968589d8 2030 * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
Kojto 90:cb3d968589d8 2031 */
Kojto 90:cb3d968589d8 2032 typedef union _hw_dma_ssrt
Kojto 90:cb3d968589d8 2033 {
Kojto 90:cb3d968589d8 2034 uint8_t U;
Kojto 90:cb3d968589d8 2035 struct _hw_dma_ssrt_bitfields
Kojto 90:cb3d968589d8 2036 {
Kojto 90:cb3d968589d8 2037 uint8_t SSRT : 4; /*!< [3:0] Set START Bit */
Kojto 90:cb3d968589d8 2038 uint8_t RESERVED0 : 2; /*!< [5:4] */
Kojto 90:cb3d968589d8 2039 uint8_t SAST : 1; /*!< [6] Set All START Bits (activates all
Kojto 90:cb3d968589d8 2040 * channels) */
Kojto 90:cb3d968589d8 2041 uint8_t NOP : 1; /*!< [7] No Op enable */
Kojto 90:cb3d968589d8 2042 } B;
Kojto 90:cb3d968589d8 2043 } hw_dma_ssrt_t;
Kojto 90:cb3d968589d8 2044
Kojto 90:cb3d968589d8 2045 /*!
Kojto 90:cb3d968589d8 2046 * @name Constants and macros for entire DMA_SSRT register
Kojto 90:cb3d968589d8 2047 */
Kojto 90:cb3d968589d8 2048 /*@{*/
Kojto 90:cb3d968589d8 2049 #define HW_DMA_SSRT_ADDR(x) ((x) + 0x1DU)
Kojto 90:cb3d968589d8 2050
Kojto 90:cb3d968589d8 2051 #define HW_DMA_SSRT(x) (*(__O hw_dma_ssrt_t *) HW_DMA_SSRT_ADDR(x))
Kojto 90:cb3d968589d8 2052 #define HW_DMA_SSRT_RD(x) (HW_DMA_SSRT(x).U)
Kojto 90:cb3d968589d8 2053 #define HW_DMA_SSRT_WR(x, v) (HW_DMA_SSRT(x).U = (v))
Kojto 90:cb3d968589d8 2054 /*@}*/
Kojto 90:cb3d968589d8 2055
Kojto 90:cb3d968589d8 2056 /*
Kojto 90:cb3d968589d8 2057 * Constants & macros for individual DMA_SSRT bitfields
Kojto 90:cb3d968589d8 2058 */
Kojto 90:cb3d968589d8 2059
Kojto 90:cb3d968589d8 2060 /*!
Kojto 90:cb3d968589d8 2061 * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
Kojto 90:cb3d968589d8 2062 *
Kojto 90:cb3d968589d8 2063 * Sets the corresponding bit in TCDn_CSR[START]
Kojto 90:cb3d968589d8 2064 */
Kojto 90:cb3d968589d8 2065 /*@{*/
Kojto 90:cb3d968589d8 2066 #define BP_DMA_SSRT_SSRT (0U) /*!< Bit position for DMA_SSRT_SSRT. */
Kojto 90:cb3d968589d8 2067 #define BM_DMA_SSRT_SSRT (0x0FU) /*!< Bit mask for DMA_SSRT_SSRT. */
Kojto 90:cb3d968589d8 2068 #define BS_DMA_SSRT_SSRT (4U) /*!< Bit field size in bits for DMA_SSRT_SSRT. */
Kojto 90:cb3d968589d8 2069
Kojto 90:cb3d968589d8 2070 /*! @brief Format value for bitfield DMA_SSRT_SSRT. */
Kojto 90:cb3d968589d8 2071 #define BF_DMA_SSRT_SSRT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SSRT) & BM_DMA_SSRT_SSRT)
Kojto 90:cb3d968589d8 2072
Kojto 90:cb3d968589d8 2073 /*! @brief Set the SSRT field to a new value. */
Kojto 90:cb3d968589d8 2074 #define BW_DMA_SSRT_SSRT(x, v) (HW_DMA_SSRT_WR(x, (HW_DMA_SSRT_RD(x) & ~BM_DMA_SSRT_SSRT) | BF_DMA_SSRT_SSRT(v)))
Kojto 90:cb3d968589d8 2075 /*@}*/
Kojto 90:cb3d968589d8 2076
Kojto 90:cb3d968589d8 2077 /*!
Kojto 90:cb3d968589d8 2078 * @name Register DMA_SSRT, field SAST[6] (WORZ)
Kojto 90:cb3d968589d8 2079 *
Kojto 90:cb3d968589d8 2080 * Values:
Kojto 90:cb3d968589d8 2081 * - 0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
Kojto 90:cb3d968589d8 2082 * - 1 - Set all bits in TCDn_CSR[START]
Kojto 90:cb3d968589d8 2083 */
Kojto 90:cb3d968589d8 2084 /*@{*/
Kojto 90:cb3d968589d8 2085 #define BP_DMA_SSRT_SAST (6U) /*!< Bit position for DMA_SSRT_SAST. */
Kojto 90:cb3d968589d8 2086 #define BM_DMA_SSRT_SAST (0x40U) /*!< Bit mask for DMA_SSRT_SAST. */
Kojto 90:cb3d968589d8 2087 #define BS_DMA_SSRT_SAST (1U) /*!< Bit field size in bits for DMA_SSRT_SAST. */
Kojto 90:cb3d968589d8 2088
Kojto 90:cb3d968589d8 2089 /*! @brief Format value for bitfield DMA_SSRT_SAST. */
Kojto 90:cb3d968589d8 2090 #define BF_DMA_SSRT_SAST(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SAST) & BM_DMA_SSRT_SAST)
Kojto 90:cb3d968589d8 2091
Kojto 90:cb3d968589d8 2092 /*! @brief Set the SAST field to a new value. */
Kojto 90:cb3d968589d8 2093 #define BW_DMA_SSRT_SAST(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_SAST) = (v))
Kojto 90:cb3d968589d8 2094 /*@}*/
Kojto 90:cb3d968589d8 2095
Kojto 90:cb3d968589d8 2096 /*!
Kojto 90:cb3d968589d8 2097 * @name Register DMA_SSRT, field NOP[7] (WORZ)
Kojto 90:cb3d968589d8 2098 *
Kojto 90:cb3d968589d8 2099 * Values:
Kojto 90:cb3d968589d8 2100 * - 0 - Normal operation
Kojto 90:cb3d968589d8 2101 * - 1 - No operation, ignore the other bits in this register
Kojto 90:cb3d968589d8 2102 */
Kojto 90:cb3d968589d8 2103 /*@{*/
Kojto 90:cb3d968589d8 2104 #define BP_DMA_SSRT_NOP (7U) /*!< Bit position for DMA_SSRT_NOP. */
Kojto 90:cb3d968589d8 2105 #define BM_DMA_SSRT_NOP (0x80U) /*!< Bit mask for DMA_SSRT_NOP. */
Kojto 90:cb3d968589d8 2106 #define BS_DMA_SSRT_NOP (1U) /*!< Bit field size in bits for DMA_SSRT_NOP. */
Kojto 90:cb3d968589d8 2107
Kojto 90:cb3d968589d8 2108 /*! @brief Format value for bitfield DMA_SSRT_NOP. */
Kojto 90:cb3d968589d8 2109 #define BF_DMA_SSRT_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_NOP) & BM_DMA_SSRT_NOP)
Kojto 90:cb3d968589d8 2110
Kojto 90:cb3d968589d8 2111 /*! @brief Set the NOP field to a new value. */
Kojto 90:cb3d968589d8 2112 #define BW_DMA_SSRT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_NOP) = (v))
Kojto 90:cb3d968589d8 2113 /*@}*/
Kojto 90:cb3d968589d8 2114
Kojto 90:cb3d968589d8 2115 /*******************************************************************************
Kojto 90:cb3d968589d8 2116 * HW_DMA_CERR - Clear Error Register
Kojto 90:cb3d968589d8 2117 ******************************************************************************/
Kojto 90:cb3d968589d8 2118
Kojto 90:cb3d968589d8 2119 /*!
Kojto 90:cb3d968589d8 2120 * @brief HW_DMA_CERR - Clear Error Register (WO)
Kojto 90:cb3d968589d8 2121 *
Kojto 90:cb3d968589d8 2122 * Reset value: 0x00U
Kojto 90:cb3d968589d8 2123 *
Kojto 90:cb3d968589d8 2124 * The CERR provides a simple memory-mapped mechanism to clear a given bit in
Kojto 90:cb3d968589d8 2125 * the ERR to disable the error condition flag for a given channel. The given value
Kojto 90:cb3d968589d8 2126 * on a register write causes the corresponding bit in the ERR to be cleared.
Kojto 90:cb3d968589d8 2127 * Setting the CAEI bit provides a global clear function, forcing the ERR contents
Kojto 90:cb3d968589d8 2128 * to be cleared, clearing all channel error indicators. If the NOP bit is set,
Kojto 90:cb3d968589d8 2129 * the command is ignored. This allows you to write multiple-byte registers as a
Kojto 90:cb3d968589d8 2130 * 32-bit word. Reads of this register return all zeroes.
Kojto 90:cb3d968589d8 2131 */
Kojto 90:cb3d968589d8 2132 typedef union _hw_dma_cerr
Kojto 90:cb3d968589d8 2133 {
Kojto 90:cb3d968589d8 2134 uint8_t U;
Kojto 90:cb3d968589d8 2135 struct _hw_dma_cerr_bitfields
Kojto 90:cb3d968589d8 2136 {
Kojto 90:cb3d968589d8 2137 uint8_t CERR : 4; /*!< [3:0] Clear Error Indicator */
Kojto 90:cb3d968589d8 2138 uint8_t RESERVED0 : 2; /*!< [5:4] */
Kojto 90:cb3d968589d8 2139 uint8_t CAEI : 1; /*!< [6] Clear All Error Indicators */
Kojto 90:cb3d968589d8 2140 uint8_t NOP : 1; /*!< [7] No Op enable */
Kojto 90:cb3d968589d8 2141 } B;
Kojto 90:cb3d968589d8 2142 } hw_dma_cerr_t;
Kojto 90:cb3d968589d8 2143
Kojto 90:cb3d968589d8 2144 /*!
Kojto 90:cb3d968589d8 2145 * @name Constants and macros for entire DMA_CERR register
Kojto 90:cb3d968589d8 2146 */
Kojto 90:cb3d968589d8 2147 /*@{*/
Kojto 90:cb3d968589d8 2148 #define HW_DMA_CERR_ADDR(x) ((x) + 0x1EU)
Kojto 90:cb3d968589d8 2149
Kojto 90:cb3d968589d8 2150 #define HW_DMA_CERR(x) (*(__O hw_dma_cerr_t *) HW_DMA_CERR_ADDR(x))
Kojto 90:cb3d968589d8 2151 #define HW_DMA_CERR_RD(x) (HW_DMA_CERR(x).U)
Kojto 90:cb3d968589d8 2152 #define HW_DMA_CERR_WR(x, v) (HW_DMA_CERR(x).U = (v))
Kojto 90:cb3d968589d8 2153 /*@}*/
Kojto 90:cb3d968589d8 2154
Kojto 90:cb3d968589d8 2155 /*
Kojto 90:cb3d968589d8 2156 * Constants & macros for individual DMA_CERR bitfields
Kojto 90:cb3d968589d8 2157 */
Kojto 90:cb3d968589d8 2158
Kojto 90:cb3d968589d8 2159 /*!
Kojto 90:cb3d968589d8 2160 * @name Register DMA_CERR, field CERR[3:0] (WORZ)
Kojto 90:cb3d968589d8 2161 *
Kojto 90:cb3d968589d8 2162 * Clears the corresponding bit in ERR
Kojto 90:cb3d968589d8 2163 */
Kojto 90:cb3d968589d8 2164 /*@{*/
Kojto 90:cb3d968589d8 2165 #define BP_DMA_CERR_CERR (0U) /*!< Bit position for DMA_CERR_CERR. */
Kojto 90:cb3d968589d8 2166 #define BM_DMA_CERR_CERR (0x0FU) /*!< Bit mask for DMA_CERR_CERR. */
Kojto 90:cb3d968589d8 2167 #define BS_DMA_CERR_CERR (4U) /*!< Bit field size in bits for DMA_CERR_CERR. */
Kojto 90:cb3d968589d8 2168
Kojto 90:cb3d968589d8 2169 /*! @brief Format value for bitfield DMA_CERR_CERR. */
Kojto 90:cb3d968589d8 2170 #define BF_DMA_CERR_CERR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CERR) & BM_DMA_CERR_CERR)
Kojto 90:cb3d968589d8 2171
Kojto 90:cb3d968589d8 2172 /*! @brief Set the CERR field to a new value. */
Kojto 90:cb3d968589d8 2173 #define BW_DMA_CERR_CERR(x, v) (HW_DMA_CERR_WR(x, (HW_DMA_CERR_RD(x) & ~BM_DMA_CERR_CERR) | BF_DMA_CERR_CERR(v)))
Kojto 90:cb3d968589d8 2174 /*@}*/
Kojto 90:cb3d968589d8 2175
Kojto 90:cb3d968589d8 2176 /*!
Kojto 90:cb3d968589d8 2177 * @name Register DMA_CERR, field CAEI[6] (WORZ)
Kojto 90:cb3d968589d8 2178 *
Kojto 90:cb3d968589d8 2179 * Values:
Kojto 90:cb3d968589d8 2180 * - 0 - Clear only the ERR bit specified in the CERR field
Kojto 90:cb3d968589d8 2181 * - 1 - Clear all bits in ERR
Kojto 90:cb3d968589d8 2182 */
Kojto 90:cb3d968589d8 2183 /*@{*/
Kojto 90:cb3d968589d8 2184 #define BP_DMA_CERR_CAEI (6U) /*!< Bit position for DMA_CERR_CAEI. */
Kojto 90:cb3d968589d8 2185 #define BM_DMA_CERR_CAEI (0x40U) /*!< Bit mask for DMA_CERR_CAEI. */
Kojto 90:cb3d968589d8 2186 #define BS_DMA_CERR_CAEI (1U) /*!< Bit field size in bits for DMA_CERR_CAEI. */
Kojto 90:cb3d968589d8 2187
Kojto 90:cb3d968589d8 2188 /*! @brief Format value for bitfield DMA_CERR_CAEI. */
Kojto 90:cb3d968589d8 2189 #define BF_DMA_CERR_CAEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CAEI) & BM_DMA_CERR_CAEI)
Kojto 90:cb3d968589d8 2190
Kojto 90:cb3d968589d8 2191 /*! @brief Set the CAEI field to a new value. */
Kojto 90:cb3d968589d8 2192 #define BW_DMA_CERR_CAEI(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_CAEI) = (v))
Kojto 90:cb3d968589d8 2193 /*@}*/
Kojto 90:cb3d968589d8 2194
Kojto 90:cb3d968589d8 2195 /*!
Kojto 90:cb3d968589d8 2196 * @name Register DMA_CERR, field NOP[7] (WORZ)
Kojto 90:cb3d968589d8 2197 *
Kojto 90:cb3d968589d8 2198 * Values:
Kojto 90:cb3d968589d8 2199 * - 0 - Normal operation
Kojto 90:cb3d968589d8 2200 * - 1 - No operation, ignore the other bits in this register
Kojto 90:cb3d968589d8 2201 */
Kojto 90:cb3d968589d8 2202 /*@{*/
Kojto 90:cb3d968589d8 2203 #define BP_DMA_CERR_NOP (7U) /*!< Bit position for DMA_CERR_NOP. */
Kojto 90:cb3d968589d8 2204 #define BM_DMA_CERR_NOP (0x80U) /*!< Bit mask for DMA_CERR_NOP. */
Kojto 90:cb3d968589d8 2205 #define BS_DMA_CERR_NOP (1U) /*!< Bit field size in bits for DMA_CERR_NOP. */
Kojto 90:cb3d968589d8 2206
Kojto 90:cb3d968589d8 2207 /*! @brief Format value for bitfield DMA_CERR_NOP. */
Kojto 90:cb3d968589d8 2208 #define BF_DMA_CERR_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_NOP) & BM_DMA_CERR_NOP)
Kojto 90:cb3d968589d8 2209
Kojto 90:cb3d968589d8 2210 /*! @brief Set the NOP field to a new value. */
Kojto 90:cb3d968589d8 2211 #define BW_DMA_CERR_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_NOP) = (v))
Kojto 90:cb3d968589d8 2212 /*@}*/
Kojto 90:cb3d968589d8 2213
Kojto 90:cb3d968589d8 2214 /*******************************************************************************
Kojto 90:cb3d968589d8 2215 * HW_DMA_CINT - Clear Interrupt Request Register
Kojto 90:cb3d968589d8 2216 ******************************************************************************/
Kojto 90:cb3d968589d8 2217
Kojto 90:cb3d968589d8 2218 /*!
Kojto 90:cb3d968589d8 2219 * @brief HW_DMA_CINT - Clear Interrupt Request Register (WO)
Kojto 90:cb3d968589d8 2220 *
Kojto 90:cb3d968589d8 2221 * Reset value: 0x00U
Kojto 90:cb3d968589d8 2222 *
Kojto 90:cb3d968589d8 2223 * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
Kojto 90:cb3d968589d8 2224 * the INT to disable the interrupt request for a given channel. The given value
Kojto 90:cb3d968589d8 2225 * on a register write causes the corresponding bit in the INT to be cleared.
Kojto 90:cb3d968589d8 2226 * Setting the CAIR bit provides a global clear function, forcing the entire contents
Kojto 90:cb3d968589d8 2227 * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
Kojto 90:cb3d968589d8 2228 * bit is set, the command is ignored. This allows you to write multiple-byte
Kojto 90:cb3d968589d8 2229 * registers as a 32-bit word. Reads of this register return all zeroes.
Kojto 90:cb3d968589d8 2230 */
Kojto 90:cb3d968589d8 2231 typedef union _hw_dma_cint
Kojto 90:cb3d968589d8 2232 {
Kojto 90:cb3d968589d8 2233 uint8_t U;
Kojto 90:cb3d968589d8 2234 struct _hw_dma_cint_bitfields
Kojto 90:cb3d968589d8 2235 {
Kojto 90:cb3d968589d8 2236 uint8_t CINT : 4; /*!< [3:0] Clear Interrupt Request */
Kojto 90:cb3d968589d8 2237 uint8_t RESERVED0 : 2; /*!< [5:4] */
Kojto 90:cb3d968589d8 2238 uint8_t CAIR : 1; /*!< [6] Clear All Interrupt Requests */
Kojto 90:cb3d968589d8 2239 uint8_t NOP : 1; /*!< [7] No Op enable */
Kojto 90:cb3d968589d8 2240 } B;
Kojto 90:cb3d968589d8 2241 } hw_dma_cint_t;
Kojto 90:cb3d968589d8 2242
Kojto 90:cb3d968589d8 2243 /*!
Kojto 90:cb3d968589d8 2244 * @name Constants and macros for entire DMA_CINT register
Kojto 90:cb3d968589d8 2245 */
Kojto 90:cb3d968589d8 2246 /*@{*/
Kojto 90:cb3d968589d8 2247 #define HW_DMA_CINT_ADDR(x) ((x) + 0x1FU)
Kojto 90:cb3d968589d8 2248
Kojto 90:cb3d968589d8 2249 #define HW_DMA_CINT(x) (*(__O hw_dma_cint_t *) HW_DMA_CINT_ADDR(x))
Kojto 90:cb3d968589d8 2250 #define HW_DMA_CINT_RD(x) (HW_DMA_CINT(x).U)
Kojto 90:cb3d968589d8 2251 #define HW_DMA_CINT_WR(x, v) (HW_DMA_CINT(x).U = (v))
Kojto 90:cb3d968589d8 2252 /*@}*/
Kojto 90:cb3d968589d8 2253
Kojto 90:cb3d968589d8 2254 /*
Kojto 90:cb3d968589d8 2255 * Constants & macros for individual DMA_CINT bitfields
Kojto 90:cb3d968589d8 2256 */
Kojto 90:cb3d968589d8 2257
Kojto 90:cb3d968589d8 2258 /*!
Kojto 90:cb3d968589d8 2259 * @name Register DMA_CINT, field CINT[3:0] (WORZ)
Kojto 90:cb3d968589d8 2260 *
Kojto 90:cb3d968589d8 2261 * Clears the corresponding bit in INT
Kojto 90:cb3d968589d8 2262 */
Kojto 90:cb3d968589d8 2263 /*@{*/
Kojto 90:cb3d968589d8 2264 #define BP_DMA_CINT_CINT (0U) /*!< Bit position for DMA_CINT_CINT. */
Kojto 90:cb3d968589d8 2265 #define BM_DMA_CINT_CINT (0x0FU) /*!< Bit mask for DMA_CINT_CINT. */
Kojto 90:cb3d968589d8 2266 #define BS_DMA_CINT_CINT (4U) /*!< Bit field size in bits for DMA_CINT_CINT. */
Kojto 90:cb3d968589d8 2267
Kojto 90:cb3d968589d8 2268 /*! @brief Format value for bitfield DMA_CINT_CINT. */
Kojto 90:cb3d968589d8 2269 #define BF_DMA_CINT_CINT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CINT) & BM_DMA_CINT_CINT)
Kojto 90:cb3d968589d8 2270
Kojto 90:cb3d968589d8 2271 /*! @brief Set the CINT field to a new value. */
Kojto 90:cb3d968589d8 2272 #define BW_DMA_CINT_CINT(x, v) (HW_DMA_CINT_WR(x, (HW_DMA_CINT_RD(x) & ~BM_DMA_CINT_CINT) | BF_DMA_CINT_CINT(v)))
Kojto 90:cb3d968589d8 2273 /*@}*/
Kojto 90:cb3d968589d8 2274
Kojto 90:cb3d968589d8 2275 /*!
Kojto 90:cb3d968589d8 2276 * @name Register DMA_CINT, field CAIR[6] (WORZ)
Kojto 90:cb3d968589d8 2277 *
Kojto 90:cb3d968589d8 2278 * Values:
Kojto 90:cb3d968589d8 2279 * - 0 - Clear only the INT bit specified in the CINT field
Kojto 90:cb3d968589d8 2280 * - 1 - Clear all bits in INT
Kojto 90:cb3d968589d8 2281 */
Kojto 90:cb3d968589d8 2282 /*@{*/
Kojto 90:cb3d968589d8 2283 #define BP_DMA_CINT_CAIR (6U) /*!< Bit position for DMA_CINT_CAIR. */
Kojto 90:cb3d968589d8 2284 #define BM_DMA_CINT_CAIR (0x40U) /*!< Bit mask for DMA_CINT_CAIR. */
Kojto 90:cb3d968589d8 2285 #define BS_DMA_CINT_CAIR (1U) /*!< Bit field size in bits for DMA_CINT_CAIR. */
Kojto 90:cb3d968589d8 2286
Kojto 90:cb3d968589d8 2287 /*! @brief Format value for bitfield DMA_CINT_CAIR. */
Kojto 90:cb3d968589d8 2288 #define BF_DMA_CINT_CAIR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CAIR) & BM_DMA_CINT_CAIR)
Kojto 90:cb3d968589d8 2289
Kojto 90:cb3d968589d8 2290 /*! @brief Set the CAIR field to a new value. */
Kojto 90:cb3d968589d8 2291 #define BW_DMA_CINT_CAIR(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_CAIR) = (v))
Kojto 90:cb3d968589d8 2292 /*@}*/
Kojto 90:cb3d968589d8 2293
Kojto 90:cb3d968589d8 2294 /*!
Kojto 90:cb3d968589d8 2295 * @name Register DMA_CINT, field NOP[7] (WORZ)
Kojto 90:cb3d968589d8 2296 *
Kojto 90:cb3d968589d8 2297 * Values:
Kojto 90:cb3d968589d8 2298 * - 0 - Normal operation
Kojto 90:cb3d968589d8 2299 * - 1 - No operation, ignore the other bits in this register
Kojto 90:cb3d968589d8 2300 */
Kojto 90:cb3d968589d8 2301 /*@{*/
Kojto 90:cb3d968589d8 2302 #define BP_DMA_CINT_NOP (7U) /*!< Bit position for DMA_CINT_NOP. */
Kojto 90:cb3d968589d8 2303 #define BM_DMA_CINT_NOP (0x80U) /*!< Bit mask for DMA_CINT_NOP. */
Kojto 90:cb3d968589d8 2304 #define BS_DMA_CINT_NOP (1U) /*!< Bit field size in bits for DMA_CINT_NOP. */
Kojto 90:cb3d968589d8 2305
Kojto 90:cb3d968589d8 2306 /*! @brief Format value for bitfield DMA_CINT_NOP. */
Kojto 90:cb3d968589d8 2307 #define BF_DMA_CINT_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_NOP) & BM_DMA_CINT_NOP)
Kojto 90:cb3d968589d8 2308
Kojto 90:cb3d968589d8 2309 /*! @brief Set the NOP field to a new value. */
Kojto 90:cb3d968589d8 2310 #define BW_DMA_CINT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_NOP) = (v))
Kojto 90:cb3d968589d8 2311 /*@}*/
Kojto 90:cb3d968589d8 2312
Kojto 90:cb3d968589d8 2313 /*******************************************************************************
Kojto 90:cb3d968589d8 2314 * HW_DMA_INT - Interrupt Request Register
Kojto 90:cb3d968589d8 2315 ******************************************************************************/
Kojto 90:cb3d968589d8 2316
Kojto 90:cb3d968589d8 2317 /*!
Kojto 90:cb3d968589d8 2318 * @brief HW_DMA_INT - Interrupt Request Register (RW)
Kojto 90:cb3d968589d8 2319 *
Kojto 90:cb3d968589d8 2320 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 2321 *
Kojto 90:cb3d968589d8 2322 * The INT register provides a bit map for the 16 channels signaling the
Kojto 90:cb3d968589d8 2323 * presence of an interrupt request for each channel. Depending on the appropriate bit
Kojto 90:cb3d968589d8 2324 * setting in the transfer-control descriptors, the eDMA engine generates an
Kojto 90:cb3d968589d8 2325 * interrupt on data transfer completion. The outputs of this register are directly
Kojto 90:cb3d968589d8 2326 * routed to the interrupt controller (INTC). During the interrupt-service routine
Kojto 90:cb3d968589d8 2327 * associated with any given channel, it is the software's responsibility to
Kojto 90:cb3d968589d8 2328 * clear the appropriate bit, negating the interrupt request. Typically, a write to
Kojto 90:cb3d968589d8 2329 * the CINT register in the interrupt service routine is used for this purpose.
Kojto 90:cb3d968589d8 2330 * The state of any given channel's interrupt request is directly affected by
Kojto 90:cb3d968589d8 2331 * writes to this register; it is also affected by writes to the CINT register. On
Kojto 90:cb3d968589d8 2332 * writes to INT, a 1 in any bit position clears the corresponding channel's
Kojto 90:cb3d968589d8 2333 * interrupt request. A zero in any bit position has no affect on the corresponding
Kojto 90:cb3d968589d8 2334 * channel's current interrupt status. The CINT register is provided so the interrupt
Kojto 90:cb3d968589d8 2335 * request for a single channel can easily be cleared without the need to
Kojto 90:cb3d968589d8 2336 * perform a read-modify-write sequence to the INT register.
Kojto 90:cb3d968589d8 2337 */
Kojto 90:cb3d968589d8 2338 typedef union _hw_dma_int
Kojto 90:cb3d968589d8 2339 {
Kojto 90:cb3d968589d8 2340 uint32_t U;
Kojto 90:cb3d968589d8 2341 struct _hw_dma_int_bitfields
Kojto 90:cb3d968589d8 2342 {
Kojto 90:cb3d968589d8 2343 uint32_t INT0 : 1; /*!< [0] Interrupt Request 0 */
Kojto 90:cb3d968589d8 2344 uint32_t INT1 : 1; /*!< [1] Interrupt Request 1 */
Kojto 90:cb3d968589d8 2345 uint32_t INT2 : 1; /*!< [2] Interrupt Request 2 */
Kojto 90:cb3d968589d8 2346 uint32_t INT3 : 1; /*!< [3] Interrupt Request 3 */
Kojto 90:cb3d968589d8 2347 uint32_t INT4 : 1; /*!< [4] Interrupt Request 4 */
Kojto 90:cb3d968589d8 2348 uint32_t INT5 : 1; /*!< [5] Interrupt Request 5 */
Kojto 90:cb3d968589d8 2349 uint32_t INT6 : 1; /*!< [6] Interrupt Request 6 */
Kojto 90:cb3d968589d8 2350 uint32_t INT7 : 1; /*!< [7] Interrupt Request 7 */
Kojto 90:cb3d968589d8 2351 uint32_t INT8 : 1; /*!< [8] Interrupt Request 8 */
Kojto 90:cb3d968589d8 2352 uint32_t INT9 : 1; /*!< [9] Interrupt Request 9 */
Kojto 90:cb3d968589d8 2353 uint32_t INT10 : 1; /*!< [10] Interrupt Request 10 */
Kojto 90:cb3d968589d8 2354 uint32_t INT11 : 1; /*!< [11] Interrupt Request 11 */
Kojto 90:cb3d968589d8 2355 uint32_t INT12 : 1; /*!< [12] Interrupt Request 12 */
Kojto 90:cb3d968589d8 2356 uint32_t INT13 : 1; /*!< [13] Interrupt Request 13 */
Kojto 90:cb3d968589d8 2357 uint32_t INT14 : 1; /*!< [14] Interrupt Request 14 */
Kojto 90:cb3d968589d8 2358 uint32_t INT15 : 1; /*!< [15] Interrupt Request 15 */
Kojto 90:cb3d968589d8 2359 uint32_t RESERVED0 : 16; /*!< [31:16] */
Kojto 90:cb3d968589d8 2360 } B;
Kojto 90:cb3d968589d8 2361 } hw_dma_int_t;
Kojto 90:cb3d968589d8 2362
Kojto 90:cb3d968589d8 2363 /*!
Kojto 90:cb3d968589d8 2364 * @name Constants and macros for entire DMA_INT register
Kojto 90:cb3d968589d8 2365 */
Kojto 90:cb3d968589d8 2366 /*@{*/
Kojto 90:cb3d968589d8 2367 #define HW_DMA_INT_ADDR(x) ((x) + 0x24U)
Kojto 90:cb3d968589d8 2368
Kojto 90:cb3d968589d8 2369 #define HW_DMA_INT(x) (*(__IO hw_dma_int_t *) HW_DMA_INT_ADDR(x))
Kojto 90:cb3d968589d8 2370 #define HW_DMA_INT_RD(x) (HW_DMA_INT(x).U)
Kojto 90:cb3d968589d8 2371 #define HW_DMA_INT_WR(x, v) (HW_DMA_INT(x).U = (v))
Kojto 90:cb3d968589d8 2372 #define HW_DMA_INT_SET(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) | (v)))
Kojto 90:cb3d968589d8 2373 #define HW_DMA_INT_CLR(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 2374 #define HW_DMA_INT_TOG(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 2375 /*@}*/
Kojto 90:cb3d968589d8 2376
Kojto 90:cb3d968589d8 2377 /*
Kojto 90:cb3d968589d8 2378 * Constants & macros for individual DMA_INT bitfields
Kojto 90:cb3d968589d8 2379 */
Kojto 90:cb3d968589d8 2380
Kojto 90:cb3d968589d8 2381 /*!
Kojto 90:cb3d968589d8 2382 * @name Register DMA_INT, field INT0[0] (W1C)
Kojto 90:cb3d968589d8 2383 *
Kojto 90:cb3d968589d8 2384 * Values:
Kojto 90:cb3d968589d8 2385 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2386 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2387 */
Kojto 90:cb3d968589d8 2388 /*@{*/
Kojto 90:cb3d968589d8 2389 #define BP_DMA_INT_INT0 (0U) /*!< Bit position for DMA_INT_INT0. */
Kojto 90:cb3d968589d8 2390 #define BM_DMA_INT_INT0 (0x00000001U) /*!< Bit mask for DMA_INT_INT0. */
Kojto 90:cb3d968589d8 2391 #define BS_DMA_INT_INT0 (1U) /*!< Bit field size in bits for DMA_INT_INT0. */
Kojto 90:cb3d968589d8 2392
Kojto 90:cb3d968589d8 2393 /*! @brief Read current value of the DMA_INT_INT0 field. */
Kojto 90:cb3d968589d8 2394 #define BR_DMA_INT_INT0(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0))
Kojto 90:cb3d968589d8 2395
Kojto 90:cb3d968589d8 2396 /*! @brief Format value for bitfield DMA_INT_INT0. */
Kojto 90:cb3d968589d8 2397 #define BF_DMA_INT_INT0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT0) & BM_DMA_INT_INT0)
Kojto 90:cb3d968589d8 2398
Kojto 90:cb3d968589d8 2399 /*! @brief Set the INT0 field to a new value. */
Kojto 90:cb3d968589d8 2400 #define BW_DMA_INT_INT0(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0) = (v))
Kojto 90:cb3d968589d8 2401 /*@}*/
Kojto 90:cb3d968589d8 2402
Kojto 90:cb3d968589d8 2403 /*!
Kojto 90:cb3d968589d8 2404 * @name Register DMA_INT, field INT1[1] (W1C)
Kojto 90:cb3d968589d8 2405 *
Kojto 90:cb3d968589d8 2406 * Values:
Kojto 90:cb3d968589d8 2407 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2408 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2409 */
Kojto 90:cb3d968589d8 2410 /*@{*/
Kojto 90:cb3d968589d8 2411 #define BP_DMA_INT_INT1 (1U) /*!< Bit position for DMA_INT_INT1. */
Kojto 90:cb3d968589d8 2412 #define BM_DMA_INT_INT1 (0x00000002U) /*!< Bit mask for DMA_INT_INT1. */
Kojto 90:cb3d968589d8 2413 #define BS_DMA_INT_INT1 (1U) /*!< Bit field size in bits for DMA_INT_INT1. */
Kojto 90:cb3d968589d8 2414
Kojto 90:cb3d968589d8 2415 /*! @brief Read current value of the DMA_INT_INT1 field. */
Kojto 90:cb3d968589d8 2416 #define BR_DMA_INT_INT1(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1))
Kojto 90:cb3d968589d8 2417
Kojto 90:cb3d968589d8 2418 /*! @brief Format value for bitfield DMA_INT_INT1. */
Kojto 90:cb3d968589d8 2419 #define BF_DMA_INT_INT1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT1) & BM_DMA_INT_INT1)
Kojto 90:cb3d968589d8 2420
Kojto 90:cb3d968589d8 2421 /*! @brief Set the INT1 field to a new value. */
Kojto 90:cb3d968589d8 2422 #define BW_DMA_INT_INT1(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1) = (v))
Kojto 90:cb3d968589d8 2423 /*@}*/
Kojto 90:cb3d968589d8 2424
Kojto 90:cb3d968589d8 2425 /*!
Kojto 90:cb3d968589d8 2426 * @name Register DMA_INT, field INT2[2] (W1C)
Kojto 90:cb3d968589d8 2427 *
Kojto 90:cb3d968589d8 2428 * Values:
Kojto 90:cb3d968589d8 2429 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2430 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2431 */
Kojto 90:cb3d968589d8 2432 /*@{*/
Kojto 90:cb3d968589d8 2433 #define BP_DMA_INT_INT2 (2U) /*!< Bit position for DMA_INT_INT2. */
Kojto 90:cb3d968589d8 2434 #define BM_DMA_INT_INT2 (0x00000004U) /*!< Bit mask for DMA_INT_INT2. */
Kojto 90:cb3d968589d8 2435 #define BS_DMA_INT_INT2 (1U) /*!< Bit field size in bits for DMA_INT_INT2. */
Kojto 90:cb3d968589d8 2436
Kojto 90:cb3d968589d8 2437 /*! @brief Read current value of the DMA_INT_INT2 field. */
Kojto 90:cb3d968589d8 2438 #define BR_DMA_INT_INT2(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2))
Kojto 90:cb3d968589d8 2439
Kojto 90:cb3d968589d8 2440 /*! @brief Format value for bitfield DMA_INT_INT2. */
Kojto 90:cb3d968589d8 2441 #define BF_DMA_INT_INT2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT2) & BM_DMA_INT_INT2)
Kojto 90:cb3d968589d8 2442
Kojto 90:cb3d968589d8 2443 /*! @brief Set the INT2 field to a new value. */
Kojto 90:cb3d968589d8 2444 #define BW_DMA_INT_INT2(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2) = (v))
Kojto 90:cb3d968589d8 2445 /*@}*/
Kojto 90:cb3d968589d8 2446
Kojto 90:cb3d968589d8 2447 /*!
Kojto 90:cb3d968589d8 2448 * @name Register DMA_INT, field INT3[3] (W1C)
Kojto 90:cb3d968589d8 2449 *
Kojto 90:cb3d968589d8 2450 * Values:
Kojto 90:cb3d968589d8 2451 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2452 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2453 */
Kojto 90:cb3d968589d8 2454 /*@{*/
Kojto 90:cb3d968589d8 2455 #define BP_DMA_INT_INT3 (3U) /*!< Bit position for DMA_INT_INT3. */
Kojto 90:cb3d968589d8 2456 #define BM_DMA_INT_INT3 (0x00000008U) /*!< Bit mask for DMA_INT_INT3. */
Kojto 90:cb3d968589d8 2457 #define BS_DMA_INT_INT3 (1U) /*!< Bit field size in bits for DMA_INT_INT3. */
Kojto 90:cb3d968589d8 2458
Kojto 90:cb3d968589d8 2459 /*! @brief Read current value of the DMA_INT_INT3 field. */
Kojto 90:cb3d968589d8 2460 #define BR_DMA_INT_INT3(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3))
Kojto 90:cb3d968589d8 2461
Kojto 90:cb3d968589d8 2462 /*! @brief Format value for bitfield DMA_INT_INT3. */
Kojto 90:cb3d968589d8 2463 #define BF_DMA_INT_INT3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT3) & BM_DMA_INT_INT3)
Kojto 90:cb3d968589d8 2464
Kojto 90:cb3d968589d8 2465 /*! @brief Set the INT3 field to a new value. */
Kojto 90:cb3d968589d8 2466 #define BW_DMA_INT_INT3(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3) = (v))
Kojto 90:cb3d968589d8 2467 /*@}*/
Kojto 90:cb3d968589d8 2468
Kojto 90:cb3d968589d8 2469 /*!
Kojto 90:cb3d968589d8 2470 * @name Register DMA_INT, field INT4[4] (W1C)
Kojto 90:cb3d968589d8 2471 *
Kojto 90:cb3d968589d8 2472 * Values:
Kojto 90:cb3d968589d8 2473 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2474 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2475 */
Kojto 90:cb3d968589d8 2476 /*@{*/
Kojto 90:cb3d968589d8 2477 #define BP_DMA_INT_INT4 (4U) /*!< Bit position for DMA_INT_INT4. */
Kojto 90:cb3d968589d8 2478 #define BM_DMA_INT_INT4 (0x00000010U) /*!< Bit mask for DMA_INT_INT4. */
Kojto 90:cb3d968589d8 2479 #define BS_DMA_INT_INT4 (1U) /*!< Bit field size in bits for DMA_INT_INT4. */
Kojto 90:cb3d968589d8 2480
Kojto 90:cb3d968589d8 2481 /*! @brief Read current value of the DMA_INT_INT4 field. */
Kojto 90:cb3d968589d8 2482 #define BR_DMA_INT_INT4(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4))
Kojto 90:cb3d968589d8 2483
Kojto 90:cb3d968589d8 2484 /*! @brief Format value for bitfield DMA_INT_INT4. */
Kojto 90:cb3d968589d8 2485 #define BF_DMA_INT_INT4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT4) & BM_DMA_INT_INT4)
Kojto 90:cb3d968589d8 2486
Kojto 90:cb3d968589d8 2487 /*! @brief Set the INT4 field to a new value. */
Kojto 90:cb3d968589d8 2488 #define BW_DMA_INT_INT4(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4) = (v))
Kojto 90:cb3d968589d8 2489 /*@}*/
Kojto 90:cb3d968589d8 2490
Kojto 90:cb3d968589d8 2491 /*!
Kojto 90:cb3d968589d8 2492 * @name Register DMA_INT, field INT5[5] (W1C)
Kojto 90:cb3d968589d8 2493 *
Kojto 90:cb3d968589d8 2494 * Values:
Kojto 90:cb3d968589d8 2495 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2496 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2497 */
Kojto 90:cb3d968589d8 2498 /*@{*/
Kojto 90:cb3d968589d8 2499 #define BP_DMA_INT_INT5 (5U) /*!< Bit position for DMA_INT_INT5. */
Kojto 90:cb3d968589d8 2500 #define BM_DMA_INT_INT5 (0x00000020U) /*!< Bit mask for DMA_INT_INT5. */
Kojto 90:cb3d968589d8 2501 #define BS_DMA_INT_INT5 (1U) /*!< Bit field size in bits for DMA_INT_INT5. */
Kojto 90:cb3d968589d8 2502
Kojto 90:cb3d968589d8 2503 /*! @brief Read current value of the DMA_INT_INT5 field. */
Kojto 90:cb3d968589d8 2504 #define BR_DMA_INT_INT5(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5))
Kojto 90:cb3d968589d8 2505
Kojto 90:cb3d968589d8 2506 /*! @brief Format value for bitfield DMA_INT_INT5. */
Kojto 90:cb3d968589d8 2507 #define BF_DMA_INT_INT5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT5) & BM_DMA_INT_INT5)
Kojto 90:cb3d968589d8 2508
Kojto 90:cb3d968589d8 2509 /*! @brief Set the INT5 field to a new value. */
Kojto 90:cb3d968589d8 2510 #define BW_DMA_INT_INT5(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5) = (v))
Kojto 90:cb3d968589d8 2511 /*@}*/
Kojto 90:cb3d968589d8 2512
Kojto 90:cb3d968589d8 2513 /*!
Kojto 90:cb3d968589d8 2514 * @name Register DMA_INT, field INT6[6] (W1C)
Kojto 90:cb3d968589d8 2515 *
Kojto 90:cb3d968589d8 2516 * Values:
Kojto 90:cb3d968589d8 2517 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2518 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2519 */
Kojto 90:cb3d968589d8 2520 /*@{*/
Kojto 90:cb3d968589d8 2521 #define BP_DMA_INT_INT6 (6U) /*!< Bit position for DMA_INT_INT6. */
Kojto 90:cb3d968589d8 2522 #define BM_DMA_INT_INT6 (0x00000040U) /*!< Bit mask for DMA_INT_INT6. */
Kojto 90:cb3d968589d8 2523 #define BS_DMA_INT_INT6 (1U) /*!< Bit field size in bits for DMA_INT_INT6. */
Kojto 90:cb3d968589d8 2524
Kojto 90:cb3d968589d8 2525 /*! @brief Read current value of the DMA_INT_INT6 field. */
Kojto 90:cb3d968589d8 2526 #define BR_DMA_INT_INT6(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6))
Kojto 90:cb3d968589d8 2527
Kojto 90:cb3d968589d8 2528 /*! @brief Format value for bitfield DMA_INT_INT6. */
Kojto 90:cb3d968589d8 2529 #define BF_DMA_INT_INT6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT6) & BM_DMA_INT_INT6)
Kojto 90:cb3d968589d8 2530
Kojto 90:cb3d968589d8 2531 /*! @brief Set the INT6 field to a new value. */
Kojto 90:cb3d968589d8 2532 #define BW_DMA_INT_INT6(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6) = (v))
Kojto 90:cb3d968589d8 2533 /*@}*/
Kojto 90:cb3d968589d8 2534
Kojto 90:cb3d968589d8 2535 /*!
Kojto 90:cb3d968589d8 2536 * @name Register DMA_INT, field INT7[7] (W1C)
Kojto 90:cb3d968589d8 2537 *
Kojto 90:cb3d968589d8 2538 * Values:
Kojto 90:cb3d968589d8 2539 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2540 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2541 */
Kojto 90:cb3d968589d8 2542 /*@{*/
Kojto 90:cb3d968589d8 2543 #define BP_DMA_INT_INT7 (7U) /*!< Bit position for DMA_INT_INT7. */
Kojto 90:cb3d968589d8 2544 #define BM_DMA_INT_INT7 (0x00000080U) /*!< Bit mask for DMA_INT_INT7. */
Kojto 90:cb3d968589d8 2545 #define BS_DMA_INT_INT7 (1U) /*!< Bit field size in bits for DMA_INT_INT7. */
Kojto 90:cb3d968589d8 2546
Kojto 90:cb3d968589d8 2547 /*! @brief Read current value of the DMA_INT_INT7 field. */
Kojto 90:cb3d968589d8 2548 #define BR_DMA_INT_INT7(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7))
Kojto 90:cb3d968589d8 2549
Kojto 90:cb3d968589d8 2550 /*! @brief Format value for bitfield DMA_INT_INT7. */
Kojto 90:cb3d968589d8 2551 #define BF_DMA_INT_INT7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT7) & BM_DMA_INT_INT7)
Kojto 90:cb3d968589d8 2552
Kojto 90:cb3d968589d8 2553 /*! @brief Set the INT7 field to a new value. */
Kojto 90:cb3d968589d8 2554 #define BW_DMA_INT_INT7(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7) = (v))
Kojto 90:cb3d968589d8 2555 /*@}*/
Kojto 90:cb3d968589d8 2556
Kojto 90:cb3d968589d8 2557 /*!
Kojto 90:cb3d968589d8 2558 * @name Register DMA_INT, field INT8[8] (W1C)
Kojto 90:cb3d968589d8 2559 *
Kojto 90:cb3d968589d8 2560 * Values:
Kojto 90:cb3d968589d8 2561 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2562 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2563 */
Kojto 90:cb3d968589d8 2564 /*@{*/
Kojto 90:cb3d968589d8 2565 #define BP_DMA_INT_INT8 (8U) /*!< Bit position for DMA_INT_INT8. */
Kojto 90:cb3d968589d8 2566 #define BM_DMA_INT_INT8 (0x00000100U) /*!< Bit mask for DMA_INT_INT8. */
Kojto 90:cb3d968589d8 2567 #define BS_DMA_INT_INT8 (1U) /*!< Bit field size in bits for DMA_INT_INT8. */
Kojto 90:cb3d968589d8 2568
Kojto 90:cb3d968589d8 2569 /*! @brief Read current value of the DMA_INT_INT8 field. */
Kojto 90:cb3d968589d8 2570 #define BR_DMA_INT_INT8(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8))
Kojto 90:cb3d968589d8 2571
Kojto 90:cb3d968589d8 2572 /*! @brief Format value for bitfield DMA_INT_INT8. */
Kojto 90:cb3d968589d8 2573 #define BF_DMA_INT_INT8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT8) & BM_DMA_INT_INT8)
Kojto 90:cb3d968589d8 2574
Kojto 90:cb3d968589d8 2575 /*! @brief Set the INT8 field to a new value. */
Kojto 90:cb3d968589d8 2576 #define BW_DMA_INT_INT8(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8) = (v))
Kojto 90:cb3d968589d8 2577 /*@}*/
Kojto 90:cb3d968589d8 2578
Kojto 90:cb3d968589d8 2579 /*!
Kojto 90:cb3d968589d8 2580 * @name Register DMA_INT, field INT9[9] (W1C)
Kojto 90:cb3d968589d8 2581 *
Kojto 90:cb3d968589d8 2582 * Values:
Kojto 90:cb3d968589d8 2583 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2584 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2585 */
Kojto 90:cb3d968589d8 2586 /*@{*/
Kojto 90:cb3d968589d8 2587 #define BP_DMA_INT_INT9 (9U) /*!< Bit position for DMA_INT_INT9. */
Kojto 90:cb3d968589d8 2588 #define BM_DMA_INT_INT9 (0x00000200U) /*!< Bit mask for DMA_INT_INT9. */
Kojto 90:cb3d968589d8 2589 #define BS_DMA_INT_INT9 (1U) /*!< Bit field size in bits for DMA_INT_INT9. */
Kojto 90:cb3d968589d8 2590
Kojto 90:cb3d968589d8 2591 /*! @brief Read current value of the DMA_INT_INT9 field. */
Kojto 90:cb3d968589d8 2592 #define BR_DMA_INT_INT9(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9))
Kojto 90:cb3d968589d8 2593
Kojto 90:cb3d968589d8 2594 /*! @brief Format value for bitfield DMA_INT_INT9. */
Kojto 90:cb3d968589d8 2595 #define BF_DMA_INT_INT9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT9) & BM_DMA_INT_INT9)
Kojto 90:cb3d968589d8 2596
Kojto 90:cb3d968589d8 2597 /*! @brief Set the INT9 field to a new value. */
Kojto 90:cb3d968589d8 2598 #define BW_DMA_INT_INT9(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9) = (v))
Kojto 90:cb3d968589d8 2599 /*@}*/
Kojto 90:cb3d968589d8 2600
Kojto 90:cb3d968589d8 2601 /*!
Kojto 90:cb3d968589d8 2602 * @name Register DMA_INT, field INT10[10] (W1C)
Kojto 90:cb3d968589d8 2603 *
Kojto 90:cb3d968589d8 2604 * Values:
Kojto 90:cb3d968589d8 2605 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2606 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2607 */
Kojto 90:cb3d968589d8 2608 /*@{*/
Kojto 90:cb3d968589d8 2609 #define BP_DMA_INT_INT10 (10U) /*!< Bit position for DMA_INT_INT10. */
Kojto 90:cb3d968589d8 2610 #define BM_DMA_INT_INT10 (0x00000400U) /*!< Bit mask for DMA_INT_INT10. */
Kojto 90:cb3d968589d8 2611 #define BS_DMA_INT_INT10 (1U) /*!< Bit field size in bits for DMA_INT_INT10. */
Kojto 90:cb3d968589d8 2612
Kojto 90:cb3d968589d8 2613 /*! @brief Read current value of the DMA_INT_INT10 field. */
Kojto 90:cb3d968589d8 2614 #define BR_DMA_INT_INT10(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10))
Kojto 90:cb3d968589d8 2615
Kojto 90:cb3d968589d8 2616 /*! @brief Format value for bitfield DMA_INT_INT10. */
Kojto 90:cb3d968589d8 2617 #define BF_DMA_INT_INT10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT10) & BM_DMA_INT_INT10)
Kojto 90:cb3d968589d8 2618
Kojto 90:cb3d968589d8 2619 /*! @brief Set the INT10 field to a new value. */
Kojto 90:cb3d968589d8 2620 #define BW_DMA_INT_INT10(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10) = (v))
Kojto 90:cb3d968589d8 2621 /*@}*/
Kojto 90:cb3d968589d8 2622
Kojto 90:cb3d968589d8 2623 /*!
Kojto 90:cb3d968589d8 2624 * @name Register DMA_INT, field INT11[11] (W1C)
Kojto 90:cb3d968589d8 2625 *
Kojto 90:cb3d968589d8 2626 * Values:
Kojto 90:cb3d968589d8 2627 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2628 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2629 */
Kojto 90:cb3d968589d8 2630 /*@{*/
Kojto 90:cb3d968589d8 2631 #define BP_DMA_INT_INT11 (11U) /*!< Bit position for DMA_INT_INT11. */
Kojto 90:cb3d968589d8 2632 #define BM_DMA_INT_INT11 (0x00000800U) /*!< Bit mask for DMA_INT_INT11. */
Kojto 90:cb3d968589d8 2633 #define BS_DMA_INT_INT11 (1U) /*!< Bit field size in bits for DMA_INT_INT11. */
Kojto 90:cb3d968589d8 2634
Kojto 90:cb3d968589d8 2635 /*! @brief Read current value of the DMA_INT_INT11 field. */
Kojto 90:cb3d968589d8 2636 #define BR_DMA_INT_INT11(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11))
Kojto 90:cb3d968589d8 2637
Kojto 90:cb3d968589d8 2638 /*! @brief Format value for bitfield DMA_INT_INT11. */
Kojto 90:cb3d968589d8 2639 #define BF_DMA_INT_INT11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT11) & BM_DMA_INT_INT11)
Kojto 90:cb3d968589d8 2640
Kojto 90:cb3d968589d8 2641 /*! @brief Set the INT11 field to a new value. */
Kojto 90:cb3d968589d8 2642 #define BW_DMA_INT_INT11(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11) = (v))
Kojto 90:cb3d968589d8 2643 /*@}*/
Kojto 90:cb3d968589d8 2644
Kojto 90:cb3d968589d8 2645 /*!
Kojto 90:cb3d968589d8 2646 * @name Register DMA_INT, field INT12[12] (W1C)
Kojto 90:cb3d968589d8 2647 *
Kojto 90:cb3d968589d8 2648 * Values:
Kojto 90:cb3d968589d8 2649 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2650 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2651 */
Kojto 90:cb3d968589d8 2652 /*@{*/
Kojto 90:cb3d968589d8 2653 #define BP_DMA_INT_INT12 (12U) /*!< Bit position for DMA_INT_INT12. */
Kojto 90:cb3d968589d8 2654 #define BM_DMA_INT_INT12 (0x00001000U) /*!< Bit mask for DMA_INT_INT12. */
Kojto 90:cb3d968589d8 2655 #define BS_DMA_INT_INT12 (1U) /*!< Bit field size in bits for DMA_INT_INT12. */
Kojto 90:cb3d968589d8 2656
Kojto 90:cb3d968589d8 2657 /*! @brief Read current value of the DMA_INT_INT12 field. */
Kojto 90:cb3d968589d8 2658 #define BR_DMA_INT_INT12(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12))
Kojto 90:cb3d968589d8 2659
Kojto 90:cb3d968589d8 2660 /*! @brief Format value for bitfield DMA_INT_INT12. */
Kojto 90:cb3d968589d8 2661 #define BF_DMA_INT_INT12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT12) & BM_DMA_INT_INT12)
Kojto 90:cb3d968589d8 2662
Kojto 90:cb3d968589d8 2663 /*! @brief Set the INT12 field to a new value. */
Kojto 90:cb3d968589d8 2664 #define BW_DMA_INT_INT12(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12) = (v))
Kojto 90:cb3d968589d8 2665 /*@}*/
Kojto 90:cb3d968589d8 2666
Kojto 90:cb3d968589d8 2667 /*!
Kojto 90:cb3d968589d8 2668 * @name Register DMA_INT, field INT13[13] (W1C)
Kojto 90:cb3d968589d8 2669 *
Kojto 90:cb3d968589d8 2670 * Values:
Kojto 90:cb3d968589d8 2671 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2672 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2673 */
Kojto 90:cb3d968589d8 2674 /*@{*/
Kojto 90:cb3d968589d8 2675 #define BP_DMA_INT_INT13 (13U) /*!< Bit position for DMA_INT_INT13. */
Kojto 90:cb3d968589d8 2676 #define BM_DMA_INT_INT13 (0x00002000U) /*!< Bit mask for DMA_INT_INT13. */
Kojto 90:cb3d968589d8 2677 #define BS_DMA_INT_INT13 (1U) /*!< Bit field size in bits for DMA_INT_INT13. */
Kojto 90:cb3d968589d8 2678
Kojto 90:cb3d968589d8 2679 /*! @brief Read current value of the DMA_INT_INT13 field. */
Kojto 90:cb3d968589d8 2680 #define BR_DMA_INT_INT13(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13))
Kojto 90:cb3d968589d8 2681
Kojto 90:cb3d968589d8 2682 /*! @brief Format value for bitfield DMA_INT_INT13. */
Kojto 90:cb3d968589d8 2683 #define BF_DMA_INT_INT13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT13) & BM_DMA_INT_INT13)
Kojto 90:cb3d968589d8 2684
Kojto 90:cb3d968589d8 2685 /*! @brief Set the INT13 field to a new value. */
Kojto 90:cb3d968589d8 2686 #define BW_DMA_INT_INT13(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13) = (v))
Kojto 90:cb3d968589d8 2687 /*@}*/
Kojto 90:cb3d968589d8 2688
Kojto 90:cb3d968589d8 2689 /*!
Kojto 90:cb3d968589d8 2690 * @name Register DMA_INT, field INT14[14] (W1C)
Kojto 90:cb3d968589d8 2691 *
Kojto 90:cb3d968589d8 2692 * Values:
Kojto 90:cb3d968589d8 2693 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2694 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2695 */
Kojto 90:cb3d968589d8 2696 /*@{*/
Kojto 90:cb3d968589d8 2697 #define BP_DMA_INT_INT14 (14U) /*!< Bit position for DMA_INT_INT14. */
Kojto 90:cb3d968589d8 2698 #define BM_DMA_INT_INT14 (0x00004000U) /*!< Bit mask for DMA_INT_INT14. */
Kojto 90:cb3d968589d8 2699 #define BS_DMA_INT_INT14 (1U) /*!< Bit field size in bits for DMA_INT_INT14. */
Kojto 90:cb3d968589d8 2700
Kojto 90:cb3d968589d8 2701 /*! @brief Read current value of the DMA_INT_INT14 field. */
Kojto 90:cb3d968589d8 2702 #define BR_DMA_INT_INT14(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14))
Kojto 90:cb3d968589d8 2703
Kojto 90:cb3d968589d8 2704 /*! @brief Format value for bitfield DMA_INT_INT14. */
Kojto 90:cb3d968589d8 2705 #define BF_DMA_INT_INT14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT14) & BM_DMA_INT_INT14)
Kojto 90:cb3d968589d8 2706
Kojto 90:cb3d968589d8 2707 /*! @brief Set the INT14 field to a new value. */
Kojto 90:cb3d968589d8 2708 #define BW_DMA_INT_INT14(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14) = (v))
Kojto 90:cb3d968589d8 2709 /*@}*/
Kojto 90:cb3d968589d8 2710
Kojto 90:cb3d968589d8 2711 /*!
Kojto 90:cb3d968589d8 2712 * @name Register DMA_INT, field INT15[15] (W1C)
Kojto 90:cb3d968589d8 2713 *
Kojto 90:cb3d968589d8 2714 * Values:
Kojto 90:cb3d968589d8 2715 * - 0 - The interrupt request for corresponding channel is cleared
Kojto 90:cb3d968589d8 2716 * - 1 - The interrupt request for corresponding channel is active
Kojto 90:cb3d968589d8 2717 */
Kojto 90:cb3d968589d8 2718 /*@{*/
Kojto 90:cb3d968589d8 2719 #define BP_DMA_INT_INT15 (15U) /*!< Bit position for DMA_INT_INT15. */
Kojto 90:cb3d968589d8 2720 #define BM_DMA_INT_INT15 (0x00008000U) /*!< Bit mask for DMA_INT_INT15. */
Kojto 90:cb3d968589d8 2721 #define BS_DMA_INT_INT15 (1U) /*!< Bit field size in bits for DMA_INT_INT15. */
Kojto 90:cb3d968589d8 2722
Kojto 90:cb3d968589d8 2723 /*! @brief Read current value of the DMA_INT_INT15 field. */
Kojto 90:cb3d968589d8 2724 #define BR_DMA_INT_INT15(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15))
Kojto 90:cb3d968589d8 2725
Kojto 90:cb3d968589d8 2726 /*! @brief Format value for bitfield DMA_INT_INT15. */
Kojto 90:cb3d968589d8 2727 #define BF_DMA_INT_INT15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT15) & BM_DMA_INT_INT15)
Kojto 90:cb3d968589d8 2728
Kojto 90:cb3d968589d8 2729 /*! @brief Set the INT15 field to a new value. */
Kojto 90:cb3d968589d8 2730 #define BW_DMA_INT_INT15(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15) = (v))
Kojto 90:cb3d968589d8 2731 /*@}*/
Kojto 90:cb3d968589d8 2732
Kojto 90:cb3d968589d8 2733 /*******************************************************************************
Kojto 90:cb3d968589d8 2734 * HW_DMA_ERR - Error Register
Kojto 90:cb3d968589d8 2735 ******************************************************************************/
Kojto 90:cb3d968589d8 2736
Kojto 90:cb3d968589d8 2737 /*!
Kojto 90:cb3d968589d8 2738 * @brief HW_DMA_ERR - Error Register (RW)
Kojto 90:cb3d968589d8 2739 *
Kojto 90:cb3d968589d8 2740 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 2741 *
Kojto 90:cb3d968589d8 2742 * The ERR provides a bit map for the 16 channels, signaling the presence of an
Kojto 90:cb3d968589d8 2743 * error for each channel. The eDMA engine signals the occurrence of an error
Kojto 90:cb3d968589d8 2744 * condition by setting the appropriate bit in this register. The outputs of this
Kojto 90:cb3d968589d8 2745 * register are enabled by the contents of the EEI, and then routed to the
Kojto 90:cb3d968589d8 2746 * interrupt controller. During the execution of the interrupt-service routine associated
Kojto 90:cb3d968589d8 2747 * with any DMA errors, it is software's responsibility to clear the appropriate
Kojto 90:cb3d968589d8 2748 * bit, negating the error-interrupt request. Typically, a write to the CERR in
Kojto 90:cb3d968589d8 2749 * the interrupt-service routine is used for this purpose. The normal DMA channel
Kojto 90:cb3d968589d8 2750 * completion indicators (setting the transfer control descriptor DONE flag and
Kojto 90:cb3d968589d8 2751 * the possible assertion of an interrupt request) are not affected when an error
Kojto 90:cb3d968589d8 2752 * is detected. The contents of this register can also be polled because a
Kojto 90:cb3d968589d8 2753 * non-zero value indicates the presence of a channel error regardless of the state of
Kojto 90:cb3d968589d8 2754 * the EEI. The state of any given channel's error indicators is affected by
Kojto 90:cb3d968589d8 2755 * writes to this register; it is also affected by writes to the CERR. On writes to
Kojto 90:cb3d968589d8 2756 * the ERR, a one in any bit position clears the corresponding channel's error
Kojto 90:cb3d968589d8 2757 * status. A zero in any bit position has no affect on the corresponding channel's
Kojto 90:cb3d968589d8 2758 * current error status. The CERR is provided so the error indicator for a single
Kojto 90:cb3d968589d8 2759 * channel can easily be cleared.
Kojto 90:cb3d968589d8 2760 */
Kojto 90:cb3d968589d8 2761 typedef union _hw_dma_err
Kojto 90:cb3d968589d8 2762 {
Kojto 90:cb3d968589d8 2763 uint32_t U;
Kojto 90:cb3d968589d8 2764 struct _hw_dma_err_bitfields
Kojto 90:cb3d968589d8 2765 {
Kojto 90:cb3d968589d8 2766 uint32_t ERR0 : 1; /*!< [0] Error In Channel 0 */
Kojto 90:cb3d968589d8 2767 uint32_t ERR1 : 1; /*!< [1] Error In Channel 1 */
Kojto 90:cb3d968589d8 2768 uint32_t ERR2 : 1; /*!< [2] Error In Channel 2 */
Kojto 90:cb3d968589d8 2769 uint32_t ERR3 : 1; /*!< [3] Error In Channel 3 */
Kojto 90:cb3d968589d8 2770 uint32_t ERR4 : 1; /*!< [4] Error In Channel 4 */
Kojto 90:cb3d968589d8 2771 uint32_t ERR5 : 1; /*!< [5] Error In Channel 5 */
Kojto 90:cb3d968589d8 2772 uint32_t ERR6 : 1; /*!< [6] Error In Channel 6 */
Kojto 90:cb3d968589d8 2773 uint32_t ERR7 : 1; /*!< [7] Error In Channel 7 */
Kojto 90:cb3d968589d8 2774 uint32_t ERR8 : 1; /*!< [8] Error In Channel 8 */
Kojto 90:cb3d968589d8 2775 uint32_t ERR9 : 1; /*!< [9] Error In Channel 9 */
Kojto 90:cb3d968589d8 2776 uint32_t ERR10 : 1; /*!< [10] Error In Channel 10 */
Kojto 90:cb3d968589d8 2777 uint32_t ERR11 : 1; /*!< [11] Error In Channel 11 */
Kojto 90:cb3d968589d8 2778 uint32_t ERR12 : 1; /*!< [12] Error In Channel 12 */
Kojto 90:cb3d968589d8 2779 uint32_t ERR13 : 1; /*!< [13] Error In Channel 13 */
Kojto 90:cb3d968589d8 2780 uint32_t ERR14 : 1; /*!< [14] Error In Channel 14 */
Kojto 90:cb3d968589d8 2781 uint32_t ERR15 : 1; /*!< [15] Error In Channel 15 */
Kojto 90:cb3d968589d8 2782 uint32_t RESERVED0 : 16; /*!< [31:16] */
Kojto 90:cb3d968589d8 2783 } B;
Kojto 90:cb3d968589d8 2784 } hw_dma_err_t;
Kojto 90:cb3d968589d8 2785
Kojto 90:cb3d968589d8 2786 /*!
Kojto 90:cb3d968589d8 2787 * @name Constants and macros for entire DMA_ERR register
Kojto 90:cb3d968589d8 2788 */
Kojto 90:cb3d968589d8 2789 /*@{*/
Kojto 90:cb3d968589d8 2790 #define HW_DMA_ERR_ADDR(x) ((x) + 0x2CU)
Kojto 90:cb3d968589d8 2791
Kojto 90:cb3d968589d8 2792 #define HW_DMA_ERR(x) (*(__IO hw_dma_err_t *) HW_DMA_ERR_ADDR(x))
Kojto 90:cb3d968589d8 2793 #define HW_DMA_ERR_RD(x) (HW_DMA_ERR(x).U)
Kojto 90:cb3d968589d8 2794 #define HW_DMA_ERR_WR(x, v) (HW_DMA_ERR(x).U = (v))
Kojto 90:cb3d968589d8 2795 #define HW_DMA_ERR_SET(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) | (v)))
Kojto 90:cb3d968589d8 2796 #define HW_DMA_ERR_CLR(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 2797 #define HW_DMA_ERR_TOG(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 2798 /*@}*/
Kojto 90:cb3d968589d8 2799
Kojto 90:cb3d968589d8 2800 /*
Kojto 90:cb3d968589d8 2801 * Constants & macros for individual DMA_ERR bitfields
Kojto 90:cb3d968589d8 2802 */
Kojto 90:cb3d968589d8 2803
Kojto 90:cb3d968589d8 2804 /*!
Kojto 90:cb3d968589d8 2805 * @name Register DMA_ERR, field ERR0[0] (W1C)
Kojto 90:cb3d968589d8 2806 *
Kojto 90:cb3d968589d8 2807 * Values:
Kojto 90:cb3d968589d8 2808 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 2809 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 2810 */
Kojto 90:cb3d968589d8 2811 /*@{*/
Kojto 90:cb3d968589d8 2812 #define BP_DMA_ERR_ERR0 (0U) /*!< Bit position for DMA_ERR_ERR0. */
Kojto 90:cb3d968589d8 2813 #define BM_DMA_ERR_ERR0 (0x00000001U) /*!< Bit mask for DMA_ERR_ERR0. */
Kojto 90:cb3d968589d8 2814 #define BS_DMA_ERR_ERR0 (1U) /*!< Bit field size in bits for DMA_ERR_ERR0. */
Kojto 90:cb3d968589d8 2815
Kojto 90:cb3d968589d8 2816 /*! @brief Read current value of the DMA_ERR_ERR0 field. */
Kojto 90:cb3d968589d8 2817 #define BR_DMA_ERR_ERR0(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0))
Kojto 90:cb3d968589d8 2818
Kojto 90:cb3d968589d8 2819 /*! @brief Format value for bitfield DMA_ERR_ERR0. */
Kojto 90:cb3d968589d8 2820 #define BF_DMA_ERR_ERR0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR0) & BM_DMA_ERR_ERR0)
Kojto 90:cb3d968589d8 2821
Kojto 90:cb3d968589d8 2822 /*! @brief Set the ERR0 field to a new value. */
Kojto 90:cb3d968589d8 2823 #define BW_DMA_ERR_ERR0(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0) = (v))
Kojto 90:cb3d968589d8 2824 /*@}*/
Kojto 90:cb3d968589d8 2825
Kojto 90:cb3d968589d8 2826 /*!
Kojto 90:cb3d968589d8 2827 * @name Register DMA_ERR, field ERR1[1] (W1C)
Kojto 90:cb3d968589d8 2828 *
Kojto 90:cb3d968589d8 2829 * Values:
Kojto 90:cb3d968589d8 2830 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 2831 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 2832 */
Kojto 90:cb3d968589d8 2833 /*@{*/
Kojto 90:cb3d968589d8 2834 #define BP_DMA_ERR_ERR1 (1U) /*!< Bit position for DMA_ERR_ERR1. */
Kojto 90:cb3d968589d8 2835 #define BM_DMA_ERR_ERR1 (0x00000002U) /*!< Bit mask for DMA_ERR_ERR1. */
Kojto 90:cb3d968589d8 2836 #define BS_DMA_ERR_ERR1 (1U) /*!< Bit field size in bits for DMA_ERR_ERR1. */
Kojto 90:cb3d968589d8 2837
Kojto 90:cb3d968589d8 2838 /*! @brief Read current value of the DMA_ERR_ERR1 field. */
Kojto 90:cb3d968589d8 2839 #define BR_DMA_ERR_ERR1(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1))
Kojto 90:cb3d968589d8 2840
Kojto 90:cb3d968589d8 2841 /*! @brief Format value for bitfield DMA_ERR_ERR1. */
Kojto 90:cb3d968589d8 2842 #define BF_DMA_ERR_ERR1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR1) & BM_DMA_ERR_ERR1)
Kojto 90:cb3d968589d8 2843
Kojto 90:cb3d968589d8 2844 /*! @brief Set the ERR1 field to a new value. */
Kojto 90:cb3d968589d8 2845 #define BW_DMA_ERR_ERR1(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1) = (v))
Kojto 90:cb3d968589d8 2846 /*@}*/
Kojto 90:cb3d968589d8 2847
Kojto 90:cb3d968589d8 2848 /*!
Kojto 90:cb3d968589d8 2849 * @name Register DMA_ERR, field ERR2[2] (W1C)
Kojto 90:cb3d968589d8 2850 *
Kojto 90:cb3d968589d8 2851 * Values:
Kojto 90:cb3d968589d8 2852 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 2853 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 2854 */
Kojto 90:cb3d968589d8 2855 /*@{*/
Kojto 90:cb3d968589d8 2856 #define BP_DMA_ERR_ERR2 (2U) /*!< Bit position for DMA_ERR_ERR2. */
Kojto 90:cb3d968589d8 2857 #define BM_DMA_ERR_ERR2 (0x00000004U) /*!< Bit mask for DMA_ERR_ERR2. */
Kojto 90:cb3d968589d8 2858 #define BS_DMA_ERR_ERR2 (1U) /*!< Bit field size in bits for DMA_ERR_ERR2. */
Kojto 90:cb3d968589d8 2859
Kojto 90:cb3d968589d8 2860 /*! @brief Read current value of the DMA_ERR_ERR2 field. */
Kojto 90:cb3d968589d8 2861 #define BR_DMA_ERR_ERR2(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2))
Kojto 90:cb3d968589d8 2862
Kojto 90:cb3d968589d8 2863 /*! @brief Format value for bitfield DMA_ERR_ERR2. */
Kojto 90:cb3d968589d8 2864 #define BF_DMA_ERR_ERR2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR2) & BM_DMA_ERR_ERR2)
Kojto 90:cb3d968589d8 2865
Kojto 90:cb3d968589d8 2866 /*! @brief Set the ERR2 field to a new value. */
Kojto 90:cb3d968589d8 2867 #define BW_DMA_ERR_ERR2(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2) = (v))
Kojto 90:cb3d968589d8 2868 /*@}*/
Kojto 90:cb3d968589d8 2869
Kojto 90:cb3d968589d8 2870 /*!
Kojto 90:cb3d968589d8 2871 * @name Register DMA_ERR, field ERR3[3] (W1C)
Kojto 90:cb3d968589d8 2872 *
Kojto 90:cb3d968589d8 2873 * Values:
Kojto 90:cb3d968589d8 2874 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 2875 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 2876 */
Kojto 90:cb3d968589d8 2877 /*@{*/
Kojto 90:cb3d968589d8 2878 #define BP_DMA_ERR_ERR3 (3U) /*!< Bit position for DMA_ERR_ERR3. */
Kojto 90:cb3d968589d8 2879 #define BM_DMA_ERR_ERR3 (0x00000008U) /*!< Bit mask for DMA_ERR_ERR3. */
Kojto 90:cb3d968589d8 2880 #define BS_DMA_ERR_ERR3 (1U) /*!< Bit field size in bits for DMA_ERR_ERR3. */
Kojto 90:cb3d968589d8 2881
Kojto 90:cb3d968589d8 2882 /*! @brief Read current value of the DMA_ERR_ERR3 field. */
Kojto 90:cb3d968589d8 2883 #define BR_DMA_ERR_ERR3(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3))
Kojto 90:cb3d968589d8 2884
Kojto 90:cb3d968589d8 2885 /*! @brief Format value for bitfield DMA_ERR_ERR3. */
Kojto 90:cb3d968589d8 2886 #define BF_DMA_ERR_ERR3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR3) & BM_DMA_ERR_ERR3)
Kojto 90:cb3d968589d8 2887
Kojto 90:cb3d968589d8 2888 /*! @brief Set the ERR3 field to a new value. */
Kojto 90:cb3d968589d8 2889 #define BW_DMA_ERR_ERR3(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3) = (v))
Kojto 90:cb3d968589d8 2890 /*@}*/
Kojto 90:cb3d968589d8 2891
Kojto 90:cb3d968589d8 2892 /*!
Kojto 90:cb3d968589d8 2893 * @name Register DMA_ERR, field ERR4[4] (W1C)
Kojto 90:cb3d968589d8 2894 *
Kojto 90:cb3d968589d8 2895 * Values:
Kojto 90:cb3d968589d8 2896 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 2897 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 2898 */
Kojto 90:cb3d968589d8 2899 /*@{*/
Kojto 90:cb3d968589d8 2900 #define BP_DMA_ERR_ERR4 (4U) /*!< Bit position for DMA_ERR_ERR4. */
Kojto 90:cb3d968589d8 2901 #define BM_DMA_ERR_ERR4 (0x00000010U) /*!< Bit mask for DMA_ERR_ERR4. */
Kojto 90:cb3d968589d8 2902 #define BS_DMA_ERR_ERR4 (1U) /*!< Bit field size in bits for DMA_ERR_ERR4. */
Kojto 90:cb3d968589d8 2903
Kojto 90:cb3d968589d8 2904 /*! @brief Read current value of the DMA_ERR_ERR4 field. */
Kojto 90:cb3d968589d8 2905 #define BR_DMA_ERR_ERR4(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4))
Kojto 90:cb3d968589d8 2906
Kojto 90:cb3d968589d8 2907 /*! @brief Format value for bitfield DMA_ERR_ERR4. */
Kojto 90:cb3d968589d8 2908 #define BF_DMA_ERR_ERR4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR4) & BM_DMA_ERR_ERR4)
Kojto 90:cb3d968589d8 2909
Kojto 90:cb3d968589d8 2910 /*! @brief Set the ERR4 field to a new value. */
Kojto 90:cb3d968589d8 2911 #define BW_DMA_ERR_ERR4(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4) = (v))
Kojto 90:cb3d968589d8 2912 /*@}*/
Kojto 90:cb3d968589d8 2913
Kojto 90:cb3d968589d8 2914 /*!
Kojto 90:cb3d968589d8 2915 * @name Register DMA_ERR, field ERR5[5] (W1C)
Kojto 90:cb3d968589d8 2916 *
Kojto 90:cb3d968589d8 2917 * Values:
Kojto 90:cb3d968589d8 2918 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 2919 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 2920 */
Kojto 90:cb3d968589d8 2921 /*@{*/
Kojto 90:cb3d968589d8 2922 #define BP_DMA_ERR_ERR5 (5U) /*!< Bit position for DMA_ERR_ERR5. */
Kojto 90:cb3d968589d8 2923 #define BM_DMA_ERR_ERR5 (0x00000020U) /*!< Bit mask for DMA_ERR_ERR5. */
Kojto 90:cb3d968589d8 2924 #define BS_DMA_ERR_ERR5 (1U) /*!< Bit field size in bits for DMA_ERR_ERR5. */
Kojto 90:cb3d968589d8 2925
Kojto 90:cb3d968589d8 2926 /*! @brief Read current value of the DMA_ERR_ERR5 field. */
Kojto 90:cb3d968589d8 2927 #define BR_DMA_ERR_ERR5(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5))
Kojto 90:cb3d968589d8 2928
Kojto 90:cb3d968589d8 2929 /*! @brief Format value for bitfield DMA_ERR_ERR5. */
Kojto 90:cb3d968589d8 2930 #define BF_DMA_ERR_ERR5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR5) & BM_DMA_ERR_ERR5)
Kojto 90:cb3d968589d8 2931
Kojto 90:cb3d968589d8 2932 /*! @brief Set the ERR5 field to a new value. */
Kojto 90:cb3d968589d8 2933 #define BW_DMA_ERR_ERR5(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5) = (v))
Kojto 90:cb3d968589d8 2934 /*@}*/
Kojto 90:cb3d968589d8 2935
Kojto 90:cb3d968589d8 2936 /*!
Kojto 90:cb3d968589d8 2937 * @name Register DMA_ERR, field ERR6[6] (W1C)
Kojto 90:cb3d968589d8 2938 *
Kojto 90:cb3d968589d8 2939 * Values:
Kojto 90:cb3d968589d8 2940 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 2941 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 2942 */
Kojto 90:cb3d968589d8 2943 /*@{*/
Kojto 90:cb3d968589d8 2944 #define BP_DMA_ERR_ERR6 (6U) /*!< Bit position for DMA_ERR_ERR6. */
Kojto 90:cb3d968589d8 2945 #define BM_DMA_ERR_ERR6 (0x00000040U) /*!< Bit mask for DMA_ERR_ERR6. */
Kojto 90:cb3d968589d8 2946 #define BS_DMA_ERR_ERR6 (1U) /*!< Bit field size in bits for DMA_ERR_ERR6. */
Kojto 90:cb3d968589d8 2947
Kojto 90:cb3d968589d8 2948 /*! @brief Read current value of the DMA_ERR_ERR6 field. */
Kojto 90:cb3d968589d8 2949 #define BR_DMA_ERR_ERR6(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6))
Kojto 90:cb3d968589d8 2950
Kojto 90:cb3d968589d8 2951 /*! @brief Format value for bitfield DMA_ERR_ERR6. */
Kojto 90:cb3d968589d8 2952 #define BF_DMA_ERR_ERR6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR6) & BM_DMA_ERR_ERR6)
Kojto 90:cb3d968589d8 2953
Kojto 90:cb3d968589d8 2954 /*! @brief Set the ERR6 field to a new value. */
Kojto 90:cb3d968589d8 2955 #define BW_DMA_ERR_ERR6(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6) = (v))
Kojto 90:cb3d968589d8 2956 /*@}*/
Kojto 90:cb3d968589d8 2957
Kojto 90:cb3d968589d8 2958 /*!
Kojto 90:cb3d968589d8 2959 * @name Register DMA_ERR, field ERR7[7] (W1C)
Kojto 90:cb3d968589d8 2960 *
Kojto 90:cb3d968589d8 2961 * Values:
Kojto 90:cb3d968589d8 2962 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 2963 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 2964 */
Kojto 90:cb3d968589d8 2965 /*@{*/
Kojto 90:cb3d968589d8 2966 #define BP_DMA_ERR_ERR7 (7U) /*!< Bit position for DMA_ERR_ERR7. */
Kojto 90:cb3d968589d8 2967 #define BM_DMA_ERR_ERR7 (0x00000080U) /*!< Bit mask for DMA_ERR_ERR7. */
Kojto 90:cb3d968589d8 2968 #define BS_DMA_ERR_ERR7 (1U) /*!< Bit field size in bits for DMA_ERR_ERR7. */
Kojto 90:cb3d968589d8 2969
Kojto 90:cb3d968589d8 2970 /*! @brief Read current value of the DMA_ERR_ERR7 field. */
Kojto 90:cb3d968589d8 2971 #define BR_DMA_ERR_ERR7(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7))
Kojto 90:cb3d968589d8 2972
Kojto 90:cb3d968589d8 2973 /*! @brief Format value for bitfield DMA_ERR_ERR7. */
Kojto 90:cb3d968589d8 2974 #define BF_DMA_ERR_ERR7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR7) & BM_DMA_ERR_ERR7)
Kojto 90:cb3d968589d8 2975
Kojto 90:cb3d968589d8 2976 /*! @brief Set the ERR7 field to a new value. */
Kojto 90:cb3d968589d8 2977 #define BW_DMA_ERR_ERR7(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7) = (v))
Kojto 90:cb3d968589d8 2978 /*@}*/
Kojto 90:cb3d968589d8 2979
Kojto 90:cb3d968589d8 2980 /*!
Kojto 90:cb3d968589d8 2981 * @name Register DMA_ERR, field ERR8[8] (W1C)
Kojto 90:cb3d968589d8 2982 *
Kojto 90:cb3d968589d8 2983 * Values:
Kojto 90:cb3d968589d8 2984 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 2985 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 2986 */
Kojto 90:cb3d968589d8 2987 /*@{*/
Kojto 90:cb3d968589d8 2988 #define BP_DMA_ERR_ERR8 (8U) /*!< Bit position for DMA_ERR_ERR8. */
Kojto 90:cb3d968589d8 2989 #define BM_DMA_ERR_ERR8 (0x00000100U) /*!< Bit mask for DMA_ERR_ERR8. */
Kojto 90:cb3d968589d8 2990 #define BS_DMA_ERR_ERR8 (1U) /*!< Bit field size in bits for DMA_ERR_ERR8. */
Kojto 90:cb3d968589d8 2991
Kojto 90:cb3d968589d8 2992 /*! @brief Read current value of the DMA_ERR_ERR8 field. */
Kojto 90:cb3d968589d8 2993 #define BR_DMA_ERR_ERR8(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8))
Kojto 90:cb3d968589d8 2994
Kojto 90:cb3d968589d8 2995 /*! @brief Format value for bitfield DMA_ERR_ERR8. */
Kojto 90:cb3d968589d8 2996 #define BF_DMA_ERR_ERR8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR8) & BM_DMA_ERR_ERR8)
Kojto 90:cb3d968589d8 2997
Kojto 90:cb3d968589d8 2998 /*! @brief Set the ERR8 field to a new value. */
Kojto 90:cb3d968589d8 2999 #define BW_DMA_ERR_ERR8(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8) = (v))
Kojto 90:cb3d968589d8 3000 /*@}*/
Kojto 90:cb3d968589d8 3001
Kojto 90:cb3d968589d8 3002 /*!
Kojto 90:cb3d968589d8 3003 * @name Register DMA_ERR, field ERR9[9] (W1C)
Kojto 90:cb3d968589d8 3004 *
Kojto 90:cb3d968589d8 3005 * Values:
Kojto 90:cb3d968589d8 3006 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 3007 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 3008 */
Kojto 90:cb3d968589d8 3009 /*@{*/
Kojto 90:cb3d968589d8 3010 #define BP_DMA_ERR_ERR9 (9U) /*!< Bit position for DMA_ERR_ERR9. */
Kojto 90:cb3d968589d8 3011 #define BM_DMA_ERR_ERR9 (0x00000200U) /*!< Bit mask for DMA_ERR_ERR9. */
Kojto 90:cb3d968589d8 3012 #define BS_DMA_ERR_ERR9 (1U) /*!< Bit field size in bits for DMA_ERR_ERR9. */
Kojto 90:cb3d968589d8 3013
Kojto 90:cb3d968589d8 3014 /*! @brief Read current value of the DMA_ERR_ERR9 field. */
Kojto 90:cb3d968589d8 3015 #define BR_DMA_ERR_ERR9(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9))
Kojto 90:cb3d968589d8 3016
Kojto 90:cb3d968589d8 3017 /*! @brief Format value for bitfield DMA_ERR_ERR9. */
Kojto 90:cb3d968589d8 3018 #define BF_DMA_ERR_ERR9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR9) & BM_DMA_ERR_ERR9)
Kojto 90:cb3d968589d8 3019
Kojto 90:cb3d968589d8 3020 /*! @brief Set the ERR9 field to a new value. */
Kojto 90:cb3d968589d8 3021 #define BW_DMA_ERR_ERR9(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9) = (v))
Kojto 90:cb3d968589d8 3022 /*@}*/
Kojto 90:cb3d968589d8 3023
Kojto 90:cb3d968589d8 3024 /*!
Kojto 90:cb3d968589d8 3025 * @name Register DMA_ERR, field ERR10[10] (W1C)
Kojto 90:cb3d968589d8 3026 *
Kojto 90:cb3d968589d8 3027 * Values:
Kojto 90:cb3d968589d8 3028 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 3029 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 3030 */
Kojto 90:cb3d968589d8 3031 /*@{*/
Kojto 90:cb3d968589d8 3032 #define BP_DMA_ERR_ERR10 (10U) /*!< Bit position for DMA_ERR_ERR10. */
Kojto 90:cb3d968589d8 3033 #define BM_DMA_ERR_ERR10 (0x00000400U) /*!< Bit mask for DMA_ERR_ERR10. */
Kojto 90:cb3d968589d8 3034 #define BS_DMA_ERR_ERR10 (1U) /*!< Bit field size in bits for DMA_ERR_ERR10. */
Kojto 90:cb3d968589d8 3035
Kojto 90:cb3d968589d8 3036 /*! @brief Read current value of the DMA_ERR_ERR10 field. */
Kojto 90:cb3d968589d8 3037 #define BR_DMA_ERR_ERR10(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10))
Kojto 90:cb3d968589d8 3038
Kojto 90:cb3d968589d8 3039 /*! @brief Format value for bitfield DMA_ERR_ERR10. */
Kojto 90:cb3d968589d8 3040 #define BF_DMA_ERR_ERR10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR10) & BM_DMA_ERR_ERR10)
Kojto 90:cb3d968589d8 3041
Kojto 90:cb3d968589d8 3042 /*! @brief Set the ERR10 field to a new value. */
Kojto 90:cb3d968589d8 3043 #define BW_DMA_ERR_ERR10(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10) = (v))
Kojto 90:cb3d968589d8 3044 /*@}*/
Kojto 90:cb3d968589d8 3045
Kojto 90:cb3d968589d8 3046 /*!
Kojto 90:cb3d968589d8 3047 * @name Register DMA_ERR, field ERR11[11] (W1C)
Kojto 90:cb3d968589d8 3048 *
Kojto 90:cb3d968589d8 3049 * Values:
Kojto 90:cb3d968589d8 3050 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 3051 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 3052 */
Kojto 90:cb3d968589d8 3053 /*@{*/
Kojto 90:cb3d968589d8 3054 #define BP_DMA_ERR_ERR11 (11U) /*!< Bit position for DMA_ERR_ERR11. */
Kojto 90:cb3d968589d8 3055 #define BM_DMA_ERR_ERR11 (0x00000800U) /*!< Bit mask for DMA_ERR_ERR11. */
Kojto 90:cb3d968589d8 3056 #define BS_DMA_ERR_ERR11 (1U) /*!< Bit field size in bits for DMA_ERR_ERR11. */
Kojto 90:cb3d968589d8 3057
Kojto 90:cb3d968589d8 3058 /*! @brief Read current value of the DMA_ERR_ERR11 field. */
Kojto 90:cb3d968589d8 3059 #define BR_DMA_ERR_ERR11(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11))
Kojto 90:cb3d968589d8 3060
Kojto 90:cb3d968589d8 3061 /*! @brief Format value for bitfield DMA_ERR_ERR11. */
Kojto 90:cb3d968589d8 3062 #define BF_DMA_ERR_ERR11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR11) & BM_DMA_ERR_ERR11)
Kojto 90:cb3d968589d8 3063
Kojto 90:cb3d968589d8 3064 /*! @brief Set the ERR11 field to a new value. */
Kojto 90:cb3d968589d8 3065 #define BW_DMA_ERR_ERR11(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11) = (v))
Kojto 90:cb3d968589d8 3066 /*@}*/
Kojto 90:cb3d968589d8 3067
Kojto 90:cb3d968589d8 3068 /*!
Kojto 90:cb3d968589d8 3069 * @name Register DMA_ERR, field ERR12[12] (W1C)
Kojto 90:cb3d968589d8 3070 *
Kojto 90:cb3d968589d8 3071 * Values:
Kojto 90:cb3d968589d8 3072 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 3073 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 3074 */
Kojto 90:cb3d968589d8 3075 /*@{*/
Kojto 90:cb3d968589d8 3076 #define BP_DMA_ERR_ERR12 (12U) /*!< Bit position for DMA_ERR_ERR12. */
Kojto 90:cb3d968589d8 3077 #define BM_DMA_ERR_ERR12 (0x00001000U) /*!< Bit mask for DMA_ERR_ERR12. */
Kojto 90:cb3d968589d8 3078 #define BS_DMA_ERR_ERR12 (1U) /*!< Bit field size in bits for DMA_ERR_ERR12. */
Kojto 90:cb3d968589d8 3079
Kojto 90:cb3d968589d8 3080 /*! @brief Read current value of the DMA_ERR_ERR12 field. */
Kojto 90:cb3d968589d8 3081 #define BR_DMA_ERR_ERR12(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12))
Kojto 90:cb3d968589d8 3082
Kojto 90:cb3d968589d8 3083 /*! @brief Format value for bitfield DMA_ERR_ERR12. */
Kojto 90:cb3d968589d8 3084 #define BF_DMA_ERR_ERR12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR12) & BM_DMA_ERR_ERR12)
Kojto 90:cb3d968589d8 3085
Kojto 90:cb3d968589d8 3086 /*! @brief Set the ERR12 field to a new value. */
Kojto 90:cb3d968589d8 3087 #define BW_DMA_ERR_ERR12(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12) = (v))
Kojto 90:cb3d968589d8 3088 /*@}*/
Kojto 90:cb3d968589d8 3089
Kojto 90:cb3d968589d8 3090 /*!
Kojto 90:cb3d968589d8 3091 * @name Register DMA_ERR, field ERR13[13] (W1C)
Kojto 90:cb3d968589d8 3092 *
Kojto 90:cb3d968589d8 3093 * Values:
Kojto 90:cb3d968589d8 3094 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 3095 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 3096 */
Kojto 90:cb3d968589d8 3097 /*@{*/
Kojto 90:cb3d968589d8 3098 #define BP_DMA_ERR_ERR13 (13U) /*!< Bit position for DMA_ERR_ERR13. */
Kojto 90:cb3d968589d8 3099 #define BM_DMA_ERR_ERR13 (0x00002000U) /*!< Bit mask for DMA_ERR_ERR13. */
Kojto 90:cb3d968589d8 3100 #define BS_DMA_ERR_ERR13 (1U) /*!< Bit field size in bits for DMA_ERR_ERR13. */
Kojto 90:cb3d968589d8 3101
Kojto 90:cb3d968589d8 3102 /*! @brief Read current value of the DMA_ERR_ERR13 field. */
Kojto 90:cb3d968589d8 3103 #define BR_DMA_ERR_ERR13(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13))
Kojto 90:cb3d968589d8 3104
Kojto 90:cb3d968589d8 3105 /*! @brief Format value for bitfield DMA_ERR_ERR13. */
Kojto 90:cb3d968589d8 3106 #define BF_DMA_ERR_ERR13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR13) & BM_DMA_ERR_ERR13)
Kojto 90:cb3d968589d8 3107
Kojto 90:cb3d968589d8 3108 /*! @brief Set the ERR13 field to a new value. */
Kojto 90:cb3d968589d8 3109 #define BW_DMA_ERR_ERR13(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13) = (v))
Kojto 90:cb3d968589d8 3110 /*@}*/
Kojto 90:cb3d968589d8 3111
Kojto 90:cb3d968589d8 3112 /*!
Kojto 90:cb3d968589d8 3113 * @name Register DMA_ERR, field ERR14[14] (W1C)
Kojto 90:cb3d968589d8 3114 *
Kojto 90:cb3d968589d8 3115 * Values:
Kojto 90:cb3d968589d8 3116 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 3117 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 3118 */
Kojto 90:cb3d968589d8 3119 /*@{*/
Kojto 90:cb3d968589d8 3120 #define BP_DMA_ERR_ERR14 (14U) /*!< Bit position for DMA_ERR_ERR14. */
Kojto 90:cb3d968589d8 3121 #define BM_DMA_ERR_ERR14 (0x00004000U) /*!< Bit mask for DMA_ERR_ERR14. */
Kojto 90:cb3d968589d8 3122 #define BS_DMA_ERR_ERR14 (1U) /*!< Bit field size in bits for DMA_ERR_ERR14. */
Kojto 90:cb3d968589d8 3123
Kojto 90:cb3d968589d8 3124 /*! @brief Read current value of the DMA_ERR_ERR14 field. */
Kojto 90:cb3d968589d8 3125 #define BR_DMA_ERR_ERR14(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14))
Kojto 90:cb3d968589d8 3126
Kojto 90:cb3d968589d8 3127 /*! @brief Format value for bitfield DMA_ERR_ERR14. */
Kojto 90:cb3d968589d8 3128 #define BF_DMA_ERR_ERR14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR14) & BM_DMA_ERR_ERR14)
Kojto 90:cb3d968589d8 3129
Kojto 90:cb3d968589d8 3130 /*! @brief Set the ERR14 field to a new value. */
Kojto 90:cb3d968589d8 3131 #define BW_DMA_ERR_ERR14(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14) = (v))
Kojto 90:cb3d968589d8 3132 /*@}*/
Kojto 90:cb3d968589d8 3133
Kojto 90:cb3d968589d8 3134 /*!
Kojto 90:cb3d968589d8 3135 * @name Register DMA_ERR, field ERR15[15] (W1C)
Kojto 90:cb3d968589d8 3136 *
Kojto 90:cb3d968589d8 3137 * Values:
Kojto 90:cb3d968589d8 3138 * - 0 - An error in the corresponding channel has not occurred
Kojto 90:cb3d968589d8 3139 * - 1 - An error in the corresponding channel has occurred
Kojto 90:cb3d968589d8 3140 */
Kojto 90:cb3d968589d8 3141 /*@{*/
Kojto 90:cb3d968589d8 3142 #define BP_DMA_ERR_ERR15 (15U) /*!< Bit position for DMA_ERR_ERR15. */
Kojto 90:cb3d968589d8 3143 #define BM_DMA_ERR_ERR15 (0x00008000U) /*!< Bit mask for DMA_ERR_ERR15. */
Kojto 90:cb3d968589d8 3144 #define BS_DMA_ERR_ERR15 (1U) /*!< Bit field size in bits for DMA_ERR_ERR15. */
Kojto 90:cb3d968589d8 3145
Kojto 90:cb3d968589d8 3146 /*! @brief Read current value of the DMA_ERR_ERR15 field. */
Kojto 90:cb3d968589d8 3147 #define BR_DMA_ERR_ERR15(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15))
Kojto 90:cb3d968589d8 3148
Kojto 90:cb3d968589d8 3149 /*! @brief Format value for bitfield DMA_ERR_ERR15. */
Kojto 90:cb3d968589d8 3150 #define BF_DMA_ERR_ERR15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR15) & BM_DMA_ERR_ERR15)
Kojto 90:cb3d968589d8 3151
Kojto 90:cb3d968589d8 3152 /*! @brief Set the ERR15 field to a new value. */
Kojto 90:cb3d968589d8 3153 #define BW_DMA_ERR_ERR15(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15) = (v))
Kojto 90:cb3d968589d8 3154 /*@}*/
Kojto 90:cb3d968589d8 3155
Kojto 90:cb3d968589d8 3156 /*******************************************************************************
Kojto 90:cb3d968589d8 3157 * HW_DMA_HRS - Hardware Request Status Register
Kojto 90:cb3d968589d8 3158 ******************************************************************************/
Kojto 90:cb3d968589d8 3159
Kojto 90:cb3d968589d8 3160 /*!
Kojto 90:cb3d968589d8 3161 * @brief HW_DMA_HRS - Hardware Request Status Register (RO)
Kojto 90:cb3d968589d8 3162 *
Kojto 90:cb3d968589d8 3163 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 3164 *
Kojto 90:cb3d968589d8 3165 * The HRS register provides a bit map for the DMA channels, signaling the
Kojto 90:cb3d968589d8 3166 * presence of a hardware request for each channel. The hardware request status bits
Kojto 90:cb3d968589d8 3167 * reflect the current state of the register and qualified (via the ERQ fields)
Kojto 90:cb3d968589d8 3168 * DMA request signals as seen by the DMA's arbitration logic. This view into the
Kojto 90:cb3d968589d8 3169 * hardware request signals may be used for debug purposes. These bits reflect the
Kojto 90:cb3d968589d8 3170 * state of the request as seen by the arbitration logic. Therefore, this status
Kojto 90:cb3d968589d8 3171 * is affected by the ERQ bits.
Kojto 90:cb3d968589d8 3172 */
Kojto 90:cb3d968589d8 3173 typedef union _hw_dma_hrs
Kojto 90:cb3d968589d8 3174 {
Kojto 90:cb3d968589d8 3175 uint32_t U;
Kojto 90:cb3d968589d8 3176 struct _hw_dma_hrs_bitfields
Kojto 90:cb3d968589d8 3177 {
Kojto 90:cb3d968589d8 3178 uint32_t HRS0 : 1; /*!< [0] Hardware Request Status Channel 0 */
Kojto 90:cb3d968589d8 3179 uint32_t HRS1 : 1; /*!< [1] Hardware Request Status Channel 1 */
Kojto 90:cb3d968589d8 3180 uint32_t HRS2 : 1; /*!< [2] Hardware Request Status Channel 2 */
Kojto 90:cb3d968589d8 3181 uint32_t HRS3 : 1; /*!< [3] Hardware Request Status Channel 3 */
Kojto 90:cb3d968589d8 3182 uint32_t HRS4 : 1; /*!< [4] Hardware Request Status Channel 4 */
Kojto 90:cb3d968589d8 3183 uint32_t HRS5 : 1; /*!< [5] Hardware Request Status Channel 5 */
Kojto 90:cb3d968589d8 3184 uint32_t HRS6 : 1; /*!< [6] Hardware Request Status Channel 6 */
Kojto 90:cb3d968589d8 3185 uint32_t HRS7 : 1; /*!< [7] Hardware Request Status Channel 7 */
Kojto 90:cb3d968589d8 3186 uint32_t HRS8 : 1; /*!< [8] Hardware Request Status Channel 8 */
Kojto 90:cb3d968589d8 3187 uint32_t HRS9 : 1; /*!< [9] Hardware Request Status Channel 9 */
Kojto 90:cb3d968589d8 3188 uint32_t HRS10 : 1; /*!< [10] Hardware Request Status Channel 10 */
Kojto 90:cb3d968589d8 3189 uint32_t HRS11 : 1; /*!< [11] Hardware Request Status Channel 11 */
Kojto 90:cb3d968589d8 3190 uint32_t HRS12 : 1; /*!< [12] Hardware Request Status Channel 12 */
Kojto 90:cb3d968589d8 3191 uint32_t HRS13 : 1; /*!< [13] Hardware Request Status Channel 13 */
Kojto 90:cb3d968589d8 3192 uint32_t HRS14 : 1; /*!< [14] Hardware Request Status Channel 14 */
Kojto 90:cb3d968589d8 3193 uint32_t HRS15 : 1; /*!< [15] Hardware Request Status Channel 15 */
Kojto 90:cb3d968589d8 3194 uint32_t RESERVED0 : 16; /*!< [31:16] Reserved */
Kojto 90:cb3d968589d8 3195 } B;
Kojto 90:cb3d968589d8 3196 } hw_dma_hrs_t;
Kojto 90:cb3d968589d8 3197
Kojto 90:cb3d968589d8 3198 /*!
Kojto 90:cb3d968589d8 3199 * @name Constants and macros for entire DMA_HRS register
Kojto 90:cb3d968589d8 3200 */
Kojto 90:cb3d968589d8 3201 /*@{*/
Kojto 90:cb3d968589d8 3202 #define HW_DMA_HRS_ADDR(x) ((x) + 0x34U)
Kojto 90:cb3d968589d8 3203
Kojto 90:cb3d968589d8 3204 #define HW_DMA_HRS(x) (*(__I hw_dma_hrs_t *) HW_DMA_HRS_ADDR(x))
Kojto 90:cb3d968589d8 3205 #define HW_DMA_HRS_RD(x) (HW_DMA_HRS(x).U)
Kojto 90:cb3d968589d8 3206 /*@}*/
Kojto 90:cb3d968589d8 3207
Kojto 90:cb3d968589d8 3208 /*
Kojto 90:cb3d968589d8 3209 * Constants & macros for individual DMA_HRS bitfields
Kojto 90:cb3d968589d8 3210 */
Kojto 90:cb3d968589d8 3211
Kojto 90:cb3d968589d8 3212 /*!
Kojto 90:cb3d968589d8 3213 * @name Register DMA_HRS, field HRS0[0] (RO)
Kojto 90:cb3d968589d8 3214 *
Kojto 90:cb3d968589d8 3215 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3216 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3217 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3218 *
Kojto 90:cb3d968589d8 3219 * Values:
Kojto 90:cb3d968589d8 3220 * - 0 - A hardware service request for channel 0 is not present
Kojto 90:cb3d968589d8 3221 * - 1 - A hardware service request for channel 0 is present
Kojto 90:cb3d968589d8 3222 */
Kojto 90:cb3d968589d8 3223 /*@{*/
Kojto 90:cb3d968589d8 3224 #define BP_DMA_HRS_HRS0 (0U) /*!< Bit position for DMA_HRS_HRS0. */
Kojto 90:cb3d968589d8 3225 #define BM_DMA_HRS_HRS0 (0x00000001U) /*!< Bit mask for DMA_HRS_HRS0. */
Kojto 90:cb3d968589d8 3226 #define BS_DMA_HRS_HRS0 (1U) /*!< Bit field size in bits for DMA_HRS_HRS0. */
Kojto 90:cb3d968589d8 3227
Kojto 90:cb3d968589d8 3228 /*! @brief Read current value of the DMA_HRS_HRS0 field. */
Kojto 90:cb3d968589d8 3229 #define BR_DMA_HRS_HRS0(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS0))
Kojto 90:cb3d968589d8 3230 /*@}*/
Kojto 90:cb3d968589d8 3231
Kojto 90:cb3d968589d8 3232 /*!
Kojto 90:cb3d968589d8 3233 * @name Register DMA_HRS, field HRS1[1] (RO)
Kojto 90:cb3d968589d8 3234 *
Kojto 90:cb3d968589d8 3235 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3236 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3237 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3238 *
Kojto 90:cb3d968589d8 3239 * Values:
Kojto 90:cb3d968589d8 3240 * - 0 - A hardware service request for channel 1 is not present
Kojto 90:cb3d968589d8 3241 * - 1 - A hardware service request for channel 1 is present
Kojto 90:cb3d968589d8 3242 */
Kojto 90:cb3d968589d8 3243 /*@{*/
Kojto 90:cb3d968589d8 3244 #define BP_DMA_HRS_HRS1 (1U) /*!< Bit position for DMA_HRS_HRS1. */
Kojto 90:cb3d968589d8 3245 #define BM_DMA_HRS_HRS1 (0x00000002U) /*!< Bit mask for DMA_HRS_HRS1. */
Kojto 90:cb3d968589d8 3246 #define BS_DMA_HRS_HRS1 (1U) /*!< Bit field size in bits for DMA_HRS_HRS1. */
Kojto 90:cb3d968589d8 3247
Kojto 90:cb3d968589d8 3248 /*! @brief Read current value of the DMA_HRS_HRS1 field. */
Kojto 90:cb3d968589d8 3249 #define BR_DMA_HRS_HRS1(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS1))
Kojto 90:cb3d968589d8 3250 /*@}*/
Kojto 90:cb3d968589d8 3251
Kojto 90:cb3d968589d8 3252 /*!
Kojto 90:cb3d968589d8 3253 * @name Register DMA_HRS, field HRS2[2] (RO)
Kojto 90:cb3d968589d8 3254 *
Kojto 90:cb3d968589d8 3255 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3256 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3257 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3258 *
Kojto 90:cb3d968589d8 3259 * Values:
Kojto 90:cb3d968589d8 3260 * - 0 - A hardware service request for channel 2 is not present
Kojto 90:cb3d968589d8 3261 * - 1 - A hardware service request for channel 2 is present
Kojto 90:cb3d968589d8 3262 */
Kojto 90:cb3d968589d8 3263 /*@{*/
Kojto 90:cb3d968589d8 3264 #define BP_DMA_HRS_HRS2 (2U) /*!< Bit position for DMA_HRS_HRS2. */
Kojto 90:cb3d968589d8 3265 #define BM_DMA_HRS_HRS2 (0x00000004U) /*!< Bit mask for DMA_HRS_HRS2. */
Kojto 90:cb3d968589d8 3266 #define BS_DMA_HRS_HRS2 (1U) /*!< Bit field size in bits for DMA_HRS_HRS2. */
Kojto 90:cb3d968589d8 3267
Kojto 90:cb3d968589d8 3268 /*! @brief Read current value of the DMA_HRS_HRS2 field. */
Kojto 90:cb3d968589d8 3269 #define BR_DMA_HRS_HRS2(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS2))
Kojto 90:cb3d968589d8 3270 /*@}*/
Kojto 90:cb3d968589d8 3271
Kojto 90:cb3d968589d8 3272 /*!
Kojto 90:cb3d968589d8 3273 * @name Register DMA_HRS, field HRS3[3] (RO)
Kojto 90:cb3d968589d8 3274 *
Kojto 90:cb3d968589d8 3275 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3276 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3277 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3278 *
Kojto 90:cb3d968589d8 3279 * Values:
Kojto 90:cb3d968589d8 3280 * - 0 - A hardware service request for channel 3 is not present
Kojto 90:cb3d968589d8 3281 * - 1 - A hardware service request for channel 3 is present
Kojto 90:cb3d968589d8 3282 */
Kojto 90:cb3d968589d8 3283 /*@{*/
Kojto 90:cb3d968589d8 3284 #define BP_DMA_HRS_HRS3 (3U) /*!< Bit position for DMA_HRS_HRS3. */
Kojto 90:cb3d968589d8 3285 #define BM_DMA_HRS_HRS3 (0x00000008U) /*!< Bit mask for DMA_HRS_HRS3. */
Kojto 90:cb3d968589d8 3286 #define BS_DMA_HRS_HRS3 (1U) /*!< Bit field size in bits for DMA_HRS_HRS3. */
Kojto 90:cb3d968589d8 3287
Kojto 90:cb3d968589d8 3288 /*! @brief Read current value of the DMA_HRS_HRS3 field. */
Kojto 90:cb3d968589d8 3289 #define BR_DMA_HRS_HRS3(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3))
Kojto 90:cb3d968589d8 3290 /*@}*/
Kojto 90:cb3d968589d8 3291
Kojto 90:cb3d968589d8 3292 /*!
Kojto 90:cb3d968589d8 3293 * @name Register DMA_HRS, field HRS4[4] (RO)
Kojto 90:cb3d968589d8 3294 *
Kojto 90:cb3d968589d8 3295 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3296 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3297 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3298 *
Kojto 90:cb3d968589d8 3299 * Values:
Kojto 90:cb3d968589d8 3300 * - 0 - A hardware service request for channel 4 is not present
Kojto 90:cb3d968589d8 3301 * - 1 - A hardware service request for channel 4 is present
Kojto 90:cb3d968589d8 3302 */
Kojto 90:cb3d968589d8 3303 /*@{*/
Kojto 90:cb3d968589d8 3304 #define BP_DMA_HRS_HRS4 (4U) /*!< Bit position for DMA_HRS_HRS4. */
Kojto 90:cb3d968589d8 3305 #define BM_DMA_HRS_HRS4 (0x00000010U) /*!< Bit mask for DMA_HRS_HRS4. */
Kojto 90:cb3d968589d8 3306 #define BS_DMA_HRS_HRS4 (1U) /*!< Bit field size in bits for DMA_HRS_HRS4. */
Kojto 90:cb3d968589d8 3307
Kojto 90:cb3d968589d8 3308 /*! @brief Read current value of the DMA_HRS_HRS4 field. */
Kojto 90:cb3d968589d8 3309 #define BR_DMA_HRS_HRS4(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4))
Kojto 90:cb3d968589d8 3310 /*@}*/
Kojto 90:cb3d968589d8 3311
Kojto 90:cb3d968589d8 3312 /*!
Kojto 90:cb3d968589d8 3313 * @name Register DMA_HRS, field HRS5[5] (RO)
Kojto 90:cb3d968589d8 3314 *
Kojto 90:cb3d968589d8 3315 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3316 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3317 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3318 *
Kojto 90:cb3d968589d8 3319 * Values:
Kojto 90:cb3d968589d8 3320 * - 0 - A hardware service request for channel 5 is not present
Kojto 90:cb3d968589d8 3321 * - 1 - A hardware service request for channel 5 is present
Kojto 90:cb3d968589d8 3322 */
Kojto 90:cb3d968589d8 3323 /*@{*/
Kojto 90:cb3d968589d8 3324 #define BP_DMA_HRS_HRS5 (5U) /*!< Bit position for DMA_HRS_HRS5. */
Kojto 90:cb3d968589d8 3325 #define BM_DMA_HRS_HRS5 (0x00000020U) /*!< Bit mask for DMA_HRS_HRS5. */
Kojto 90:cb3d968589d8 3326 #define BS_DMA_HRS_HRS5 (1U) /*!< Bit field size in bits for DMA_HRS_HRS5. */
Kojto 90:cb3d968589d8 3327
Kojto 90:cb3d968589d8 3328 /*! @brief Read current value of the DMA_HRS_HRS5 field. */
Kojto 90:cb3d968589d8 3329 #define BR_DMA_HRS_HRS5(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5))
Kojto 90:cb3d968589d8 3330 /*@}*/
Kojto 90:cb3d968589d8 3331
Kojto 90:cb3d968589d8 3332 /*!
Kojto 90:cb3d968589d8 3333 * @name Register DMA_HRS, field HRS6[6] (RO)
Kojto 90:cb3d968589d8 3334 *
Kojto 90:cb3d968589d8 3335 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3336 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3337 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3338 *
Kojto 90:cb3d968589d8 3339 * Values:
Kojto 90:cb3d968589d8 3340 * - 0 - A hardware service request for channel 6 is not present
Kojto 90:cb3d968589d8 3341 * - 1 - A hardware service request for channel 6 is present
Kojto 90:cb3d968589d8 3342 */
Kojto 90:cb3d968589d8 3343 /*@{*/
Kojto 90:cb3d968589d8 3344 #define BP_DMA_HRS_HRS6 (6U) /*!< Bit position for DMA_HRS_HRS6. */
Kojto 90:cb3d968589d8 3345 #define BM_DMA_HRS_HRS6 (0x00000040U) /*!< Bit mask for DMA_HRS_HRS6. */
Kojto 90:cb3d968589d8 3346 #define BS_DMA_HRS_HRS6 (1U) /*!< Bit field size in bits for DMA_HRS_HRS6. */
Kojto 90:cb3d968589d8 3347
Kojto 90:cb3d968589d8 3348 /*! @brief Read current value of the DMA_HRS_HRS6 field. */
Kojto 90:cb3d968589d8 3349 #define BR_DMA_HRS_HRS6(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6))
Kojto 90:cb3d968589d8 3350 /*@}*/
Kojto 90:cb3d968589d8 3351
Kojto 90:cb3d968589d8 3352 /*!
Kojto 90:cb3d968589d8 3353 * @name Register DMA_HRS, field HRS7[7] (RO)
Kojto 90:cb3d968589d8 3354 *
Kojto 90:cb3d968589d8 3355 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3356 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3357 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3358 *
Kojto 90:cb3d968589d8 3359 * Values:
Kojto 90:cb3d968589d8 3360 * - 0 - A hardware service request for channel 7 is not present
Kojto 90:cb3d968589d8 3361 * - 1 - A hardware service request for channel 7 is present
Kojto 90:cb3d968589d8 3362 */
Kojto 90:cb3d968589d8 3363 /*@{*/
Kojto 90:cb3d968589d8 3364 #define BP_DMA_HRS_HRS7 (7U) /*!< Bit position for DMA_HRS_HRS7. */
Kojto 90:cb3d968589d8 3365 #define BM_DMA_HRS_HRS7 (0x00000080U) /*!< Bit mask for DMA_HRS_HRS7. */
Kojto 90:cb3d968589d8 3366 #define BS_DMA_HRS_HRS7 (1U) /*!< Bit field size in bits for DMA_HRS_HRS7. */
Kojto 90:cb3d968589d8 3367
Kojto 90:cb3d968589d8 3368 /*! @brief Read current value of the DMA_HRS_HRS7 field. */
Kojto 90:cb3d968589d8 3369 #define BR_DMA_HRS_HRS7(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7))
Kojto 90:cb3d968589d8 3370 /*@}*/
Kojto 90:cb3d968589d8 3371
Kojto 90:cb3d968589d8 3372 /*!
Kojto 90:cb3d968589d8 3373 * @name Register DMA_HRS, field HRS8[8] (RO)
Kojto 90:cb3d968589d8 3374 *
Kojto 90:cb3d968589d8 3375 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3376 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3377 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3378 *
Kojto 90:cb3d968589d8 3379 * Values:
Kojto 90:cb3d968589d8 3380 * - 0 - A hardware service request for channel 8 is not present
Kojto 90:cb3d968589d8 3381 * - 1 - A hardware service request for channel 8 is present
Kojto 90:cb3d968589d8 3382 */
Kojto 90:cb3d968589d8 3383 /*@{*/
Kojto 90:cb3d968589d8 3384 #define BP_DMA_HRS_HRS8 (8U) /*!< Bit position for DMA_HRS_HRS8. */
Kojto 90:cb3d968589d8 3385 #define BM_DMA_HRS_HRS8 (0x00000100U) /*!< Bit mask for DMA_HRS_HRS8. */
Kojto 90:cb3d968589d8 3386 #define BS_DMA_HRS_HRS8 (1U) /*!< Bit field size in bits for DMA_HRS_HRS8. */
Kojto 90:cb3d968589d8 3387
Kojto 90:cb3d968589d8 3388 /*! @brief Read current value of the DMA_HRS_HRS8 field. */
Kojto 90:cb3d968589d8 3389 #define BR_DMA_HRS_HRS8(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8))
Kojto 90:cb3d968589d8 3390 /*@}*/
Kojto 90:cb3d968589d8 3391
Kojto 90:cb3d968589d8 3392 /*!
Kojto 90:cb3d968589d8 3393 * @name Register DMA_HRS, field HRS9[9] (RO)
Kojto 90:cb3d968589d8 3394 *
Kojto 90:cb3d968589d8 3395 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3396 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3397 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3398 *
Kojto 90:cb3d968589d8 3399 * Values:
Kojto 90:cb3d968589d8 3400 * - 0 - A hardware service request for channel 9 is not present
Kojto 90:cb3d968589d8 3401 * - 1 - A hardware service request for channel 9 is present
Kojto 90:cb3d968589d8 3402 */
Kojto 90:cb3d968589d8 3403 /*@{*/
Kojto 90:cb3d968589d8 3404 #define BP_DMA_HRS_HRS9 (9U) /*!< Bit position for DMA_HRS_HRS9. */
Kojto 90:cb3d968589d8 3405 #define BM_DMA_HRS_HRS9 (0x00000200U) /*!< Bit mask for DMA_HRS_HRS9. */
Kojto 90:cb3d968589d8 3406 #define BS_DMA_HRS_HRS9 (1U) /*!< Bit field size in bits for DMA_HRS_HRS9. */
Kojto 90:cb3d968589d8 3407
Kojto 90:cb3d968589d8 3408 /*! @brief Read current value of the DMA_HRS_HRS9 field. */
Kojto 90:cb3d968589d8 3409 #define BR_DMA_HRS_HRS9(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9))
Kojto 90:cb3d968589d8 3410 /*@}*/
Kojto 90:cb3d968589d8 3411
Kojto 90:cb3d968589d8 3412 /*!
Kojto 90:cb3d968589d8 3413 * @name Register DMA_HRS, field HRS10[10] (RO)
Kojto 90:cb3d968589d8 3414 *
Kojto 90:cb3d968589d8 3415 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3416 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3417 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3418 *
Kojto 90:cb3d968589d8 3419 * Values:
Kojto 90:cb3d968589d8 3420 * - 0 - A hardware service request for channel 10 is not present
Kojto 90:cb3d968589d8 3421 * - 1 - A hardware service request for channel 10 is present
Kojto 90:cb3d968589d8 3422 */
Kojto 90:cb3d968589d8 3423 /*@{*/
Kojto 90:cb3d968589d8 3424 #define BP_DMA_HRS_HRS10 (10U) /*!< Bit position for DMA_HRS_HRS10. */
Kojto 90:cb3d968589d8 3425 #define BM_DMA_HRS_HRS10 (0x00000400U) /*!< Bit mask for DMA_HRS_HRS10. */
Kojto 90:cb3d968589d8 3426 #define BS_DMA_HRS_HRS10 (1U) /*!< Bit field size in bits for DMA_HRS_HRS10. */
Kojto 90:cb3d968589d8 3427
Kojto 90:cb3d968589d8 3428 /*! @brief Read current value of the DMA_HRS_HRS10 field. */
Kojto 90:cb3d968589d8 3429 #define BR_DMA_HRS_HRS10(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10))
Kojto 90:cb3d968589d8 3430 /*@}*/
Kojto 90:cb3d968589d8 3431
Kojto 90:cb3d968589d8 3432 /*!
Kojto 90:cb3d968589d8 3433 * @name Register DMA_HRS, field HRS11[11] (RO)
Kojto 90:cb3d968589d8 3434 *
Kojto 90:cb3d968589d8 3435 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3436 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3437 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3438 *
Kojto 90:cb3d968589d8 3439 * Values:
Kojto 90:cb3d968589d8 3440 * - 0 - A hardware service request for channel 11 is not present
Kojto 90:cb3d968589d8 3441 * - 1 - A hardware service request for channel 11 is present
Kojto 90:cb3d968589d8 3442 */
Kojto 90:cb3d968589d8 3443 /*@{*/
Kojto 90:cb3d968589d8 3444 #define BP_DMA_HRS_HRS11 (11U) /*!< Bit position for DMA_HRS_HRS11. */
Kojto 90:cb3d968589d8 3445 #define BM_DMA_HRS_HRS11 (0x00000800U) /*!< Bit mask for DMA_HRS_HRS11. */
Kojto 90:cb3d968589d8 3446 #define BS_DMA_HRS_HRS11 (1U) /*!< Bit field size in bits for DMA_HRS_HRS11. */
Kojto 90:cb3d968589d8 3447
Kojto 90:cb3d968589d8 3448 /*! @brief Read current value of the DMA_HRS_HRS11 field. */
Kojto 90:cb3d968589d8 3449 #define BR_DMA_HRS_HRS11(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11))
Kojto 90:cb3d968589d8 3450 /*@}*/
Kojto 90:cb3d968589d8 3451
Kojto 90:cb3d968589d8 3452 /*!
Kojto 90:cb3d968589d8 3453 * @name Register DMA_HRS, field HRS12[12] (RO)
Kojto 90:cb3d968589d8 3454 *
Kojto 90:cb3d968589d8 3455 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3456 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3457 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3458 *
Kojto 90:cb3d968589d8 3459 * Values:
Kojto 90:cb3d968589d8 3460 * - 0 - A hardware service request for channel 12 is not present
Kojto 90:cb3d968589d8 3461 * - 1 - A hardware service request for channel 12 is present
Kojto 90:cb3d968589d8 3462 */
Kojto 90:cb3d968589d8 3463 /*@{*/
Kojto 90:cb3d968589d8 3464 #define BP_DMA_HRS_HRS12 (12U) /*!< Bit position for DMA_HRS_HRS12. */
Kojto 90:cb3d968589d8 3465 #define BM_DMA_HRS_HRS12 (0x00001000U) /*!< Bit mask for DMA_HRS_HRS12. */
Kojto 90:cb3d968589d8 3466 #define BS_DMA_HRS_HRS12 (1U) /*!< Bit field size in bits for DMA_HRS_HRS12. */
Kojto 90:cb3d968589d8 3467
Kojto 90:cb3d968589d8 3468 /*! @brief Read current value of the DMA_HRS_HRS12 field. */
Kojto 90:cb3d968589d8 3469 #define BR_DMA_HRS_HRS12(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12))
Kojto 90:cb3d968589d8 3470 /*@}*/
Kojto 90:cb3d968589d8 3471
Kojto 90:cb3d968589d8 3472 /*!
Kojto 90:cb3d968589d8 3473 * @name Register DMA_HRS, field HRS13[13] (RO)
Kojto 90:cb3d968589d8 3474 *
Kojto 90:cb3d968589d8 3475 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3476 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3477 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3478 *
Kojto 90:cb3d968589d8 3479 * Values:
Kojto 90:cb3d968589d8 3480 * - 0 - A hardware service request for channel 13 is not present
Kojto 90:cb3d968589d8 3481 * - 1 - A hardware service request for channel 13 is present
Kojto 90:cb3d968589d8 3482 */
Kojto 90:cb3d968589d8 3483 /*@{*/
Kojto 90:cb3d968589d8 3484 #define BP_DMA_HRS_HRS13 (13U) /*!< Bit position for DMA_HRS_HRS13. */
Kojto 90:cb3d968589d8 3485 #define BM_DMA_HRS_HRS13 (0x00002000U) /*!< Bit mask for DMA_HRS_HRS13. */
Kojto 90:cb3d968589d8 3486 #define BS_DMA_HRS_HRS13 (1U) /*!< Bit field size in bits for DMA_HRS_HRS13. */
Kojto 90:cb3d968589d8 3487
Kojto 90:cb3d968589d8 3488 /*! @brief Read current value of the DMA_HRS_HRS13 field. */
Kojto 90:cb3d968589d8 3489 #define BR_DMA_HRS_HRS13(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13))
Kojto 90:cb3d968589d8 3490 /*@}*/
Kojto 90:cb3d968589d8 3491
Kojto 90:cb3d968589d8 3492 /*!
Kojto 90:cb3d968589d8 3493 * @name Register DMA_HRS, field HRS14[14] (RO)
Kojto 90:cb3d968589d8 3494 *
Kojto 90:cb3d968589d8 3495 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3496 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3497 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3498 *
Kojto 90:cb3d968589d8 3499 * Values:
Kojto 90:cb3d968589d8 3500 * - 0 - A hardware service request for channel 14 is not present
Kojto 90:cb3d968589d8 3501 * - 1 - A hardware service request for channel 14 is present
Kojto 90:cb3d968589d8 3502 */
Kojto 90:cb3d968589d8 3503 /*@{*/
Kojto 90:cb3d968589d8 3504 #define BP_DMA_HRS_HRS14 (14U) /*!< Bit position for DMA_HRS_HRS14. */
Kojto 90:cb3d968589d8 3505 #define BM_DMA_HRS_HRS14 (0x00004000U) /*!< Bit mask for DMA_HRS_HRS14. */
Kojto 90:cb3d968589d8 3506 #define BS_DMA_HRS_HRS14 (1U) /*!< Bit field size in bits for DMA_HRS_HRS14. */
Kojto 90:cb3d968589d8 3507
Kojto 90:cb3d968589d8 3508 /*! @brief Read current value of the DMA_HRS_HRS14 field. */
Kojto 90:cb3d968589d8 3509 #define BR_DMA_HRS_HRS14(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14))
Kojto 90:cb3d968589d8 3510 /*@}*/
Kojto 90:cb3d968589d8 3511
Kojto 90:cb3d968589d8 3512 /*!
Kojto 90:cb3d968589d8 3513 * @name Register DMA_HRS, field HRS15[15] (RO)
Kojto 90:cb3d968589d8 3514 *
Kojto 90:cb3d968589d8 3515 * The HRS bit for its respective channel remains asserted for the period when a
Kojto 90:cb3d968589d8 3516 * Hardware Request is Present on the Channel. After the Request is completed
Kojto 90:cb3d968589d8 3517 * and Channel is free , the HRS bit is automatically cleared by hardware.
Kojto 90:cb3d968589d8 3518 *
Kojto 90:cb3d968589d8 3519 * Values:
Kojto 90:cb3d968589d8 3520 * - 0 - A hardware service request for channel 15 is not present
Kojto 90:cb3d968589d8 3521 * - 1 - A hardware service request for channel 15 is present
Kojto 90:cb3d968589d8 3522 */
Kojto 90:cb3d968589d8 3523 /*@{*/
Kojto 90:cb3d968589d8 3524 #define BP_DMA_HRS_HRS15 (15U) /*!< Bit position for DMA_HRS_HRS15. */
Kojto 90:cb3d968589d8 3525 #define BM_DMA_HRS_HRS15 (0x00008000U) /*!< Bit mask for DMA_HRS_HRS15. */
Kojto 90:cb3d968589d8 3526 #define BS_DMA_HRS_HRS15 (1U) /*!< Bit field size in bits for DMA_HRS_HRS15. */
Kojto 90:cb3d968589d8 3527
Kojto 90:cb3d968589d8 3528 /*! @brief Read current value of the DMA_HRS_HRS15 field. */
Kojto 90:cb3d968589d8 3529 #define BR_DMA_HRS_HRS15(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15))
Kojto 90:cb3d968589d8 3530 /*@}*/
Kojto 90:cb3d968589d8 3531
Kojto 90:cb3d968589d8 3532 /*******************************************************************************
Kojto 90:cb3d968589d8 3533 * HW_DMA_DCHPRIn - Channel n Priority Register
Kojto 90:cb3d968589d8 3534 ******************************************************************************/
Kojto 90:cb3d968589d8 3535
Kojto 90:cb3d968589d8 3536 /*!
Kojto 90:cb3d968589d8 3537 * @brief HW_DMA_DCHPRIn - Channel n Priority Register (RW)
Kojto 90:cb3d968589d8 3538 *
Kojto 90:cb3d968589d8 3539 * Reset value: 0x00U
Kojto 90:cb3d968589d8 3540 *
Kojto 90:cb3d968589d8 3541 * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
Kojto 90:cb3d968589d8 3542 * contents of these registers define the unique priorities associated with each
Kojto 90:cb3d968589d8 3543 * channel . The channel priorities are evaluated by numeric value; for example, 0 is
Kojto 90:cb3d968589d8 3544 * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
Kojto 90:cb3d968589d8 3545 * program the channel priorities with unique values; otherwise, a configuration
Kojto 90:cb3d968589d8 3546 * error is reported. The range of the priority value is limited to the values of 0
Kojto 90:cb3d968589d8 3547 * through 15.
Kojto 90:cb3d968589d8 3548 */
Kojto 90:cb3d968589d8 3549 typedef union _hw_dma_dchprin
Kojto 90:cb3d968589d8 3550 {
Kojto 90:cb3d968589d8 3551 uint8_t U;
Kojto 90:cb3d968589d8 3552 struct _hw_dma_dchprin_bitfields
Kojto 90:cb3d968589d8 3553 {
Kojto 90:cb3d968589d8 3554 uint8_t CHPRI : 4; /*!< [3:0] Channel n Arbitration Priority */
Kojto 90:cb3d968589d8 3555 uint8_t RESERVED0 : 2; /*!< [5:4] */
Kojto 90:cb3d968589d8 3556 uint8_t DPA : 1; /*!< [6] Disable Preempt Ability */
Kojto 90:cb3d968589d8 3557 uint8_t ECP : 1; /*!< [7] Enable Channel Preemption */
Kojto 90:cb3d968589d8 3558 } B;
Kojto 90:cb3d968589d8 3559 } hw_dma_dchprin_t;
Kojto 90:cb3d968589d8 3560
Kojto 90:cb3d968589d8 3561 /*!
Kojto 90:cb3d968589d8 3562 * @name Constants and macros for entire DMA_DCHPRIn register
Kojto 90:cb3d968589d8 3563 */
Kojto 90:cb3d968589d8 3564 /*@{*/
Kojto 90:cb3d968589d8 3565 #define HW_DMA_DCHPRIn_COUNT (16U)
Kojto 90:cb3d968589d8 3566
Kojto 90:cb3d968589d8 3567 #define HW_DMA_DCHPRIn_ADDR(x, n) ((x) + 0x100U + (0x1U * (n)))
Kojto 90:cb3d968589d8 3568
Kojto 90:cb3d968589d8 3569 /* DMA channel index to DMA channel priority register array index conversion macro */
Kojto 90:cb3d968589d8 3570 #define HW_DMA_DCHPRIn_CHANNEL(n) (((n) & ~0x03U) | (3 - ((n) & 0x03U)))
Kojto 90:cb3d968589d8 3571
Kojto 90:cb3d968589d8 3572 #define HW_DMA_DCHPRIn(x, n) (*(__IO hw_dma_dchprin_t *) HW_DMA_DCHPRIn_ADDR(x, n))
Kojto 90:cb3d968589d8 3573 #define HW_DMA_DCHPRIn_RD(x, n) (HW_DMA_DCHPRIn(x, n).U)
Kojto 90:cb3d968589d8 3574 #define HW_DMA_DCHPRIn_WR(x, n, v) (HW_DMA_DCHPRIn(x, n).U = (v))
Kojto 90:cb3d968589d8 3575 #define HW_DMA_DCHPRIn_SET(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 3576 #define HW_DMA_DCHPRIn_CLR(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 3577 #define HW_DMA_DCHPRIn_TOG(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 3578 /*@}*/
Kojto 90:cb3d968589d8 3579
Kojto 90:cb3d968589d8 3580 /*
Kojto 90:cb3d968589d8 3581 * Constants & macros for individual DMA_DCHPRIn bitfields
Kojto 90:cb3d968589d8 3582 */
Kojto 90:cb3d968589d8 3583
Kojto 90:cb3d968589d8 3584 /*!
Kojto 90:cb3d968589d8 3585 * @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW)
Kojto 90:cb3d968589d8 3586 *
Kojto 90:cb3d968589d8 3587 * Channel priority when fixed-priority arbitration is enabled Reset value for
Kojto 90:cb3d968589d8 3588 * the channel priority fields, CHPRI, is equal to the corresponding channel
Kojto 90:cb3d968589d8 3589 * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
Kojto 90:cb3d968589d8 3590 */
Kojto 90:cb3d968589d8 3591 /*@{*/
Kojto 90:cb3d968589d8 3592 #define BP_DMA_DCHPRIn_CHPRI (0U) /*!< Bit position for DMA_DCHPRIn_CHPRI. */
Kojto 90:cb3d968589d8 3593 #define BM_DMA_DCHPRIn_CHPRI (0x0FU) /*!< Bit mask for DMA_DCHPRIn_CHPRI. */
Kojto 90:cb3d968589d8 3594 #define BS_DMA_DCHPRIn_CHPRI (4U) /*!< Bit field size in bits for DMA_DCHPRIn_CHPRI. */
Kojto 90:cb3d968589d8 3595
Kojto 90:cb3d968589d8 3596 /*! @brief Read current value of the DMA_DCHPRIn_CHPRI field. */
Kojto 90:cb3d968589d8 3597 #define BR_DMA_DCHPRIn_CHPRI(x, n) (HW_DMA_DCHPRIn(x, n).B.CHPRI)
Kojto 90:cb3d968589d8 3598
Kojto 90:cb3d968589d8 3599 /*! @brief Format value for bitfield DMA_DCHPRIn_CHPRI. */
Kojto 90:cb3d968589d8 3600 #define BF_DMA_DCHPRIn_CHPRI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_CHPRI) & BM_DMA_DCHPRIn_CHPRI)
Kojto 90:cb3d968589d8 3601
Kojto 90:cb3d968589d8 3602 /*! @brief Set the CHPRI field to a new value. */
Kojto 90:cb3d968589d8 3603 #define BW_DMA_DCHPRIn_CHPRI(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, (HW_DMA_DCHPRIn_RD(x, n) & ~BM_DMA_DCHPRIn_CHPRI) | BF_DMA_DCHPRIn_CHPRI(v)))
Kojto 90:cb3d968589d8 3604 /*@}*/
Kojto 90:cb3d968589d8 3605
Kojto 90:cb3d968589d8 3606 /*!
Kojto 90:cb3d968589d8 3607 * @name Register DMA_DCHPRIn, field DPA[6] (RW)
Kojto 90:cb3d968589d8 3608 *
Kojto 90:cb3d968589d8 3609 * Values:
Kojto 90:cb3d968589d8 3610 * - 0 - Channel n can suspend a lower priority channel
Kojto 90:cb3d968589d8 3611 * - 1 - Channel n cannot suspend any channel, regardless of channel priority
Kojto 90:cb3d968589d8 3612 */
Kojto 90:cb3d968589d8 3613 /*@{*/
Kojto 90:cb3d968589d8 3614 #define BP_DMA_DCHPRIn_DPA (6U) /*!< Bit position for DMA_DCHPRIn_DPA. */
Kojto 90:cb3d968589d8 3615 #define BM_DMA_DCHPRIn_DPA (0x40U) /*!< Bit mask for DMA_DCHPRIn_DPA. */
Kojto 90:cb3d968589d8 3616 #define BS_DMA_DCHPRIn_DPA (1U) /*!< Bit field size in bits for DMA_DCHPRIn_DPA. */
Kojto 90:cb3d968589d8 3617
Kojto 90:cb3d968589d8 3618 /*! @brief Read current value of the DMA_DCHPRIn_DPA field. */
Kojto 90:cb3d968589d8 3619 #define BR_DMA_DCHPRIn_DPA(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA))
Kojto 90:cb3d968589d8 3620
Kojto 90:cb3d968589d8 3621 /*! @brief Format value for bitfield DMA_DCHPRIn_DPA. */
Kojto 90:cb3d968589d8 3622 #define BF_DMA_DCHPRIn_DPA(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_DPA) & BM_DMA_DCHPRIn_DPA)
Kojto 90:cb3d968589d8 3623
Kojto 90:cb3d968589d8 3624 /*! @brief Set the DPA field to a new value. */
Kojto 90:cb3d968589d8 3625 #define BW_DMA_DCHPRIn_DPA(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA) = (v))
Kojto 90:cb3d968589d8 3626 /*@}*/
Kojto 90:cb3d968589d8 3627
Kojto 90:cb3d968589d8 3628 /*!
Kojto 90:cb3d968589d8 3629 * @name Register DMA_DCHPRIn, field ECP[7] (RW)
Kojto 90:cb3d968589d8 3630 *
Kojto 90:cb3d968589d8 3631 * Values:
Kojto 90:cb3d968589d8 3632 * - 0 - Channel n cannot be suspended by a higher priority channel's service
Kojto 90:cb3d968589d8 3633 * request
Kojto 90:cb3d968589d8 3634 * - 1 - Channel n can be temporarily suspended by the service request of a
Kojto 90:cb3d968589d8 3635 * higher priority channel
Kojto 90:cb3d968589d8 3636 */
Kojto 90:cb3d968589d8 3637 /*@{*/
Kojto 90:cb3d968589d8 3638 #define BP_DMA_DCHPRIn_ECP (7U) /*!< Bit position for DMA_DCHPRIn_ECP. */
Kojto 90:cb3d968589d8 3639 #define BM_DMA_DCHPRIn_ECP (0x80U) /*!< Bit mask for DMA_DCHPRIn_ECP. */
Kojto 90:cb3d968589d8 3640 #define BS_DMA_DCHPRIn_ECP (1U) /*!< Bit field size in bits for DMA_DCHPRIn_ECP. */
Kojto 90:cb3d968589d8 3641
Kojto 90:cb3d968589d8 3642 /*! @brief Read current value of the DMA_DCHPRIn_ECP field. */
Kojto 90:cb3d968589d8 3643 #define BR_DMA_DCHPRIn_ECP(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP))
Kojto 90:cb3d968589d8 3644
Kojto 90:cb3d968589d8 3645 /*! @brief Format value for bitfield DMA_DCHPRIn_ECP. */
Kojto 90:cb3d968589d8 3646 #define BF_DMA_DCHPRIn_ECP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_ECP) & BM_DMA_DCHPRIn_ECP)
Kojto 90:cb3d968589d8 3647
Kojto 90:cb3d968589d8 3648 /*! @brief Set the ECP field to a new value. */
Kojto 90:cb3d968589d8 3649 #define BW_DMA_DCHPRIn_ECP(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP) = (v))
Kojto 90:cb3d968589d8 3650 /*@}*/
Kojto 90:cb3d968589d8 3651
Kojto 90:cb3d968589d8 3652 /*******************************************************************************
Kojto 90:cb3d968589d8 3653 * HW_DMA_TCDn_SADDR - TCD Source Address
Kojto 90:cb3d968589d8 3654 ******************************************************************************/
Kojto 90:cb3d968589d8 3655
Kojto 90:cb3d968589d8 3656 /*!
Kojto 90:cb3d968589d8 3657 * @brief HW_DMA_TCDn_SADDR - TCD Source Address (RW)
Kojto 90:cb3d968589d8 3658 *
Kojto 90:cb3d968589d8 3659 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 3660 */
Kojto 90:cb3d968589d8 3661 typedef union _hw_dma_tcdn_saddr
Kojto 90:cb3d968589d8 3662 {
Kojto 90:cb3d968589d8 3663 uint32_t U;
Kojto 90:cb3d968589d8 3664 struct _hw_dma_tcdn_saddr_bitfields
Kojto 90:cb3d968589d8 3665 {
Kojto 90:cb3d968589d8 3666 uint32_t SADDR : 32; /*!< [31:0] Source Address */
Kojto 90:cb3d968589d8 3667 } B;
Kojto 90:cb3d968589d8 3668 } hw_dma_tcdn_saddr_t;
Kojto 90:cb3d968589d8 3669
Kojto 90:cb3d968589d8 3670 /*!
Kojto 90:cb3d968589d8 3671 * @name Constants and macros for entire DMA_TCDn_SADDR register
Kojto 90:cb3d968589d8 3672 */
Kojto 90:cb3d968589d8 3673 /*@{*/
Kojto 90:cb3d968589d8 3674 #define HW_DMA_TCDn_SADDR_COUNT (16U)
Kojto 90:cb3d968589d8 3675
Kojto 90:cb3d968589d8 3676 #define HW_DMA_TCDn_SADDR_ADDR(x, n) ((x) + 0x1000U + (0x20U * (n)))
Kojto 90:cb3d968589d8 3677
Kojto 90:cb3d968589d8 3678 #define HW_DMA_TCDn_SADDR(x, n) (*(__IO hw_dma_tcdn_saddr_t *) HW_DMA_TCDn_SADDR_ADDR(x, n))
Kojto 90:cb3d968589d8 3679 #define HW_DMA_TCDn_SADDR_RD(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
Kojto 90:cb3d968589d8 3680 #define HW_DMA_TCDn_SADDR_WR(x, n, v) (HW_DMA_TCDn_SADDR(x, n).U = (v))
Kojto 90:cb3d968589d8 3681 #define HW_DMA_TCDn_SADDR_SET(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 3682 #define HW_DMA_TCDn_SADDR_CLR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 3683 #define HW_DMA_TCDn_SADDR_TOG(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 3684 /*@}*/
Kojto 90:cb3d968589d8 3685
Kojto 90:cb3d968589d8 3686 /*
Kojto 90:cb3d968589d8 3687 * Constants & macros for individual DMA_TCDn_SADDR bitfields
Kojto 90:cb3d968589d8 3688 */
Kojto 90:cb3d968589d8 3689
Kojto 90:cb3d968589d8 3690 /*!
Kojto 90:cb3d968589d8 3691 * @name Register DMA_TCDn_SADDR, field SADDR[31:0] (RW)
Kojto 90:cb3d968589d8 3692 *
Kojto 90:cb3d968589d8 3693 * Memory address pointing to the source data.
Kojto 90:cb3d968589d8 3694 */
Kojto 90:cb3d968589d8 3695 /*@{*/
Kojto 90:cb3d968589d8 3696 #define BP_DMA_TCDn_SADDR_SADDR (0U) /*!< Bit position for DMA_TCDn_SADDR_SADDR. */
Kojto 90:cb3d968589d8 3697 #define BM_DMA_TCDn_SADDR_SADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SADDR_SADDR. */
Kojto 90:cb3d968589d8 3698 #define BS_DMA_TCDn_SADDR_SADDR (32U) /*!< Bit field size in bits for DMA_TCDn_SADDR_SADDR. */
Kojto 90:cb3d968589d8 3699
Kojto 90:cb3d968589d8 3700 /*! @brief Read current value of the DMA_TCDn_SADDR_SADDR field. */
Kojto 90:cb3d968589d8 3701 #define BR_DMA_TCDn_SADDR_SADDR(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
Kojto 90:cb3d968589d8 3702
Kojto 90:cb3d968589d8 3703 /*! @brief Format value for bitfield DMA_TCDn_SADDR_SADDR. */
Kojto 90:cb3d968589d8 3704 #define BF_DMA_TCDn_SADDR_SADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SADDR_SADDR) & BM_DMA_TCDn_SADDR_SADDR)
Kojto 90:cb3d968589d8 3705
Kojto 90:cb3d968589d8 3706 /*! @brief Set the SADDR field to a new value. */
Kojto 90:cb3d968589d8 3707 #define BW_DMA_TCDn_SADDR_SADDR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, v))
Kojto 90:cb3d968589d8 3708 /*@}*/
Kojto 90:cb3d968589d8 3709 /*******************************************************************************
Kojto 90:cb3d968589d8 3710 * HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
Kojto 90:cb3d968589d8 3711 ******************************************************************************/
Kojto 90:cb3d968589d8 3712
Kojto 90:cb3d968589d8 3713 /*!
Kojto 90:cb3d968589d8 3714 * @brief HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset (RW)
Kojto 90:cb3d968589d8 3715 *
Kojto 90:cb3d968589d8 3716 * Reset value: 0x0000U
Kojto 90:cb3d968589d8 3717 */
Kojto 90:cb3d968589d8 3718 typedef union _hw_dma_tcdn_soff
Kojto 90:cb3d968589d8 3719 {
Kojto 90:cb3d968589d8 3720 uint16_t U;
Kojto 90:cb3d968589d8 3721 struct _hw_dma_tcdn_soff_bitfields
Kojto 90:cb3d968589d8 3722 {
Kojto 90:cb3d968589d8 3723 uint16_t SOFF : 16; /*!< [15:0] Source address signed offset */
Kojto 90:cb3d968589d8 3724 } B;
Kojto 90:cb3d968589d8 3725 } hw_dma_tcdn_soff_t;
Kojto 90:cb3d968589d8 3726
Kojto 90:cb3d968589d8 3727 /*!
Kojto 90:cb3d968589d8 3728 * @name Constants and macros for entire DMA_TCDn_SOFF register
Kojto 90:cb3d968589d8 3729 */
Kojto 90:cb3d968589d8 3730 /*@{*/
Kojto 90:cb3d968589d8 3731 #define HW_DMA_TCDn_SOFF_COUNT (16U)
Kojto 90:cb3d968589d8 3732
Kojto 90:cb3d968589d8 3733 #define HW_DMA_TCDn_SOFF_ADDR(x, n) ((x) + 0x1004U + (0x20U * (n)))
Kojto 90:cb3d968589d8 3734
Kojto 90:cb3d968589d8 3735 #define HW_DMA_TCDn_SOFF(x, n) (*(__IO hw_dma_tcdn_soff_t *) HW_DMA_TCDn_SOFF_ADDR(x, n))
Kojto 90:cb3d968589d8 3736 #define HW_DMA_TCDn_SOFF_RD(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
Kojto 90:cb3d968589d8 3737 #define HW_DMA_TCDn_SOFF_WR(x, n, v) (HW_DMA_TCDn_SOFF(x, n).U = (v))
Kojto 90:cb3d968589d8 3738 #define HW_DMA_TCDn_SOFF_SET(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 3739 #define HW_DMA_TCDn_SOFF_CLR(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 3740 #define HW_DMA_TCDn_SOFF_TOG(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 3741 /*@}*/
Kojto 90:cb3d968589d8 3742
Kojto 90:cb3d968589d8 3743 /*
Kojto 90:cb3d968589d8 3744 * Constants & macros for individual DMA_TCDn_SOFF bitfields
Kojto 90:cb3d968589d8 3745 */
Kojto 90:cb3d968589d8 3746
Kojto 90:cb3d968589d8 3747 /*!
Kojto 90:cb3d968589d8 3748 * @name Register DMA_TCDn_SOFF, field SOFF[15:0] (RW)
Kojto 90:cb3d968589d8 3749 *
Kojto 90:cb3d968589d8 3750 * Sign-extended offset applied to the current source address to form the
Kojto 90:cb3d968589d8 3751 * next-state value as each source read is completed.
Kojto 90:cb3d968589d8 3752 */
Kojto 90:cb3d968589d8 3753 /*@{*/
Kojto 90:cb3d968589d8 3754 #define BP_DMA_TCDn_SOFF_SOFF (0U) /*!< Bit position for DMA_TCDn_SOFF_SOFF. */
Kojto 90:cb3d968589d8 3755 #define BM_DMA_TCDn_SOFF_SOFF (0xFFFFU) /*!< Bit mask for DMA_TCDn_SOFF_SOFF. */
Kojto 90:cb3d968589d8 3756 #define BS_DMA_TCDn_SOFF_SOFF (16U) /*!< Bit field size in bits for DMA_TCDn_SOFF_SOFF. */
Kojto 90:cb3d968589d8 3757
Kojto 90:cb3d968589d8 3758 /*! @brief Read current value of the DMA_TCDn_SOFF_SOFF field. */
Kojto 90:cb3d968589d8 3759 #define BR_DMA_TCDn_SOFF_SOFF(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
Kojto 90:cb3d968589d8 3760
Kojto 90:cb3d968589d8 3761 /*! @brief Format value for bitfield DMA_TCDn_SOFF_SOFF. */
Kojto 90:cb3d968589d8 3762 #define BF_DMA_TCDn_SOFF_SOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_SOFF_SOFF) & BM_DMA_TCDn_SOFF_SOFF)
Kojto 90:cb3d968589d8 3763
Kojto 90:cb3d968589d8 3764 /*! @brief Set the SOFF field to a new value. */
Kojto 90:cb3d968589d8 3765 #define BW_DMA_TCDn_SOFF_SOFF(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, v))
Kojto 90:cb3d968589d8 3766 /*@}*/
Kojto 90:cb3d968589d8 3767 /*******************************************************************************
Kojto 90:cb3d968589d8 3768 * HW_DMA_TCDn_ATTR - TCD Transfer Attributes
Kojto 90:cb3d968589d8 3769 ******************************************************************************/
Kojto 90:cb3d968589d8 3770
Kojto 90:cb3d968589d8 3771 /*!
Kojto 90:cb3d968589d8 3772 * @brief HW_DMA_TCDn_ATTR - TCD Transfer Attributes (RW)
Kojto 90:cb3d968589d8 3773 *
Kojto 90:cb3d968589d8 3774 * Reset value: 0x0000U
Kojto 90:cb3d968589d8 3775 */
Kojto 90:cb3d968589d8 3776 typedef union _hw_dma_tcdn_attr
Kojto 90:cb3d968589d8 3777 {
Kojto 90:cb3d968589d8 3778 uint16_t U;
Kojto 90:cb3d968589d8 3779 struct _hw_dma_tcdn_attr_bitfields
Kojto 90:cb3d968589d8 3780 {
Kojto 90:cb3d968589d8 3781 uint16_t DSIZE : 3; /*!< [2:0] Destination Data Transfer Size */
Kojto 90:cb3d968589d8 3782 uint16_t DMOD : 5; /*!< [7:3] Destination Address Modulo */
Kojto 90:cb3d968589d8 3783 uint16_t SSIZE : 3; /*!< [10:8] Source data transfer size */
Kojto 90:cb3d968589d8 3784 uint16_t SMOD : 5; /*!< [15:11] Source Address Modulo. */
Kojto 90:cb3d968589d8 3785 } B;
Kojto 90:cb3d968589d8 3786 } hw_dma_tcdn_attr_t;
Kojto 90:cb3d968589d8 3787
Kojto 90:cb3d968589d8 3788 /*!
Kojto 90:cb3d968589d8 3789 * @name Constants and macros for entire DMA_TCDn_ATTR register
Kojto 90:cb3d968589d8 3790 */
Kojto 90:cb3d968589d8 3791 /*@{*/
Kojto 90:cb3d968589d8 3792 #define HW_DMA_TCDn_ATTR_COUNT (16U)
Kojto 90:cb3d968589d8 3793
Kojto 90:cb3d968589d8 3794 #define HW_DMA_TCDn_ATTR_ADDR(x, n) ((x) + 0x1006U + (0x20U * (n)))
Kojto 90:cb3d968589d8 3795
Kojto 90:cb3d968589d8 3796 #define HW_DMA_TCDn_ATTR(x, n) (*(__IO hw_dma_tcdn_attr_t *) HW_DMA_TCDn_ATTR_ADDR(x, n))
Kojto 90:cb3d968589d8 3797 #define HW_DMA_TCDn_ATTR_RD(x, n) (HW_DMA_TCDn_ATTR(x, n).U)
Kojto 90:cb3d968589d8 3798 #define HW_DMA_TCDn_ATTR_WR(x, n, v) (HW_DMA_TCDn_ATTR(x, n).U = (v))
Kojto 90:cb3d968589d8 3799 #define HW_DMA_TCDn_ATTR_SET(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 3800 #define HW_DMA_TCDn_ATTR_CLR(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 3801 #define HW_DMA_TCDn_ATTR_TOG(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 3802 /*@}*/
Kojto 90:cb3d968589d8 3803
Kojto 90:cb3d968589d8 3804 /*
Kojto 90:cb3d968589d8 3805 * Constants & macros for individual DMA_TCDn_ATTR bitfields
Kojto 90:cb3d968589d8 3806 */
Kojto 90:cb3d968589d8 3807
Kojto 90:cb3d968589d8 3808 /*!
Kojto 90:cb3d968589d8 3809 * @name Register DMA_TCDn_ATTR, field DSIZE[2:0] (RW)
Kojto 90:cb3d968589d8 3810 *
Kojto 90:cb3d968589d8 3811 * See the SSIZE definition
Kojto 90:cb3d968589d8 3812 */
Kojto 90:cb3d968589d8 3813 /*@{*/
Kojto 90:cb3d968589d8 3814 #define BP_DMA_TCDn_ATTR_DSIZE (0U) /*!< Bit position for DMA_TCDn_ATTR_DSIZE. */
Kojto 90:cb3d968589d8 3815 #define BM_DMA_TCDn_ATTR_DSIZE (0x0007U) /*!< Bit mask for DMA_TCDn_ATTR_DSIZE. */
Kojto 90:cb3d968589d8 3816 #define BS_DMA_TCDn_ATTR_DSIZE (3U) /*!< Bit field size in bits for DMA_TCDn_ATTR_DSIZE. */
Kojto 90:cb3d968589d8 3817
Kojto 90:cb3d968589d8 3818 /*! @brief Read current value of the DMA_TCDn_ATTR_DSIZE field. */
Kojto 90:cb3d968589d8 3819 #define BR_DMA_TCDn_ATTR_DSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DSIZE)
Kojto 90:cb3d968589d8 3820
Kojto 90:cb3d968589d8 3821 /*! @brief Format value for bitfield DMA_TCDn_ATTR_DSIZE. */
Kojto 90:cb3d968589d8 3822 #define BF_DMA_TCDn_ATTR_DSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DSIZE) & BM_DMA_TCDn_ATTR_DSIZE)
Kojto 90:cb3d968589d8 3823
Kojto 90:cb3d968589d8 3824 /*! @brief Set the DSIZE field to a new value. */
Kojto 90:cb3d968589d8 3825 #define BW_DMA_TCDn_ATTR_DSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DSIZE) | BF_DMA_TCDn_ATTR_DSIZE(v)))
Kojto 90:cb3d968589d8 3826 /*@}*/
Kojto 90:cb3d968589d8 3827
Kojto 90:cb3d968589d8 3828 /*!
Kojto 90:cb3d968589d8 3829 * @name Register DMA_TCDn_ATTR, field DMOD[7:3] (RW)
Kojto 90:cb3d968589d8 3830 *
Kojto 90:cb3d968589d8 3831 * See the SMOD definition
Kojto 90:cb3d968589d8 3832 */
Kojto 90:cb3d968589d8 3833 /*@{*/
Kojto 90:cb3d968589d8 3834 #define BP_DMA_TCDn_ATTR_DMOD (3U) /*!< Bit position for DMA_TCDn_ATTR_DMOD. */
Kojto 90:cb3d968589d8 3835 #define BM_DMA_TCDn_ATTR_DMOD (0x00F8U) /*!< Bit mask for DMA_TCDn_ATTR_DMOD. */
Kojto 90:cb3d968589d8 3836 #define BS_DMA_TCDn_ATTR_DMOD (5U) /*!< Bit field size in bits for DMA_TCDn_ATTR_DMOD. */
Kojto 90:cb3d968589d8 3837
Kojto 90:cb3d968589d8 3838 /*! @brief Read current value of the DMA_TCDn_ATTR_DMOD field. */
Kojto 90:cb3d968589d8 3839 #define BR_DMA_TCDn_ATTR_DMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DMOD)
Kojto 90:cb3d968589d8 3840
Kojto 90:cb3d968589d8 3841 /*! @brief Format value for bitfield DMA_TCDn_ATTR_DMOD. */
Kojto 90:cb3d968589d8 3842 #define BF_DMA_TCDn_ATTR_DMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DMOD) & BM_DMA_TCDn_ATTR_DMOD)
Kojto 90:cb3d968589d8 3843
Kojto 90:cb3d968589d8 3844 /*! @brief Set the DMOD field to a new value. */
Kojto 90:cb3d968589d8 3845 #define BW_DMA_TCDn_ATTR_DMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DMOD) | BF_DMA_TCDn_ATTR_DMOD(v)))
Kojto 90:cb3d968589d8 3846 /*@}*/
Kojto 90:cb3d968589d8 3847
Kojto 90:cb3d968589d8 3848 /*!
Kojto 90:cb3d968589d8 3849 * @name Register DMA_TCDn_ATTR, field SSIZE[10:8] (RW)
Kojto 90:cb3d968589d8 3850 *
Kojto 90:cb3d968589d8 3851 * The attempted use of a Reserved encoding causes a configuration error.
Kojto 90:cb3d968589d8 3852 *
Kojto 90:cb3d968589d8 3853 * Values:
Kojto 90:cb3d968589d8 3854 * - 000 - 8-bit
Kojto 90:cb3d968589d8 3855 * - 001 - 16-bit
Kojto 90:cb3d968589d8 3856 * - 010 - 32-bit
Kojto 90:cb3d968589d8 3857 * - 011 - Reserved
Kojto 90:cb3d968589d8 3858 * - 100 - 16-byte
Kojto 90:cb3d968589d8 3859 * - 101 - 32-byte
Kojto 90:cb3d968589d8 3860 * - 110 - Reserved
Kojto 90:cb3d968589d8 3861 * - 111 - Reserved
Kojto 90:cb3d968589d8 3862 */
Kojto 90:cb3d968589d8 3863 /*@{*/
Kojto 90:cb3d968589d8 3864 #define BP_DMA_TCDn_ATTR_SSIZE (8U) /*!< Bit position for DMA_TCDn_ATTR_SSIZE. */
Kojto 90:cb3d968589d8 3865 #define BM_DMA_TCDn_ATTR_SSIZE (0x0700U) /*!< Bit mask for DMA_TCDn_ATTR_SSIZE. */
Kojto 90:cb3d968589d8 3866 #define BS_DMA_TCDn_ATTR_SSIZE (3U) /*!< Bit field size in bits for DMA_TCDn_ATTR_SSIZE. */
Kojto 90:cb3d968589d8 3867
Kojto 90:cb3d968589d8 3868 /*! @brief Read current value of the DMA_TCDn_ATTR_SSIZE field. */
Kojto 90:cb3d968589d8 3869 #define BR_DMA_TCDn_ATTR_SSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SSIZE)
Kojto 90:cb3d968589d8 3870
Kojto 90:cb3d968589d8 3871 /*! @brief Format value for bitfield DMA_TCDn_ATTR_SSIZE. */
Kojto 90:cb3d968589d8 3872 #define BF_DMA_TCDn_ATTR_SSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SSIZE) & BM_DMA_TCDn_ATTR_SSIZE)
Kojto 90:cb3d968589d8 3873
Kojto 90:cb3d968589d8 3874 /*! @brief Set the SSIZE field to a new value. */
Kojto 90:cb3d968589d8 3875 #define BW_DMA_TCDn_ATTR_SSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SSIZE) | BF_DMA_TCDn_ATTR_SSIZE(v)))
Kojto 90:cb3d968589d8 3876 /*@}*/
Kojto 90:cb3d968589d8 3877
Kojto 90:cb3d968589d8 3878 /*!
Kojto 90:cb3d968589d8 3879 * @name Register DMA_TCDn_ATTR, field SMOD[15:11] (RW)
Kojto 90:cb3d968589d8 3880 *
Kojto 90:cb3d968589d8 3881 * Values:
Kojto 90:cb3d968589d8 3882 * - 0 - Source address modulo feature is disabled
Kojto 90:cb3d968589d8 3883 */
Kojto 90:cb3d968589d8 3884 /*@{*/
Kojto 90:cb3d968589d8 3885 #define BP_DMA_TCDn_ATTR_SMOD (11U) /*!< Bit position for DMA_TCDn_ATTR_SMOD. */
Kojto 90:cb3d968589d8 3886 #define BM_DMA_TCDn_ATTR_SMOD (0xF800U) /*!< Bit mask for DMA_TCDn_ATTR_SMOD. */
Kojto 90:cb3d968589d8 3887 #define BS_DMA_TCDn_ATTR_SMOD (5U) /*!< Bit field size in bits for DMA_TCDn_ATTR_SMOD. */
Kojto 90:cb3d968589d8 3888
Kojto 90:cb3d968589d8 3889 /*! @brief Read current value of the DMA_TCDn_ATTR_SMOD field. */
Kojto 90:cb3d968589d8 3890 #define BR_DMA_TCDn_ATTR_SMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SMOD)
Kojto 90:cb3d968589d8 3891
Kojto 90:cb3d968589d8 3892 /*! @brief Format value for bitfield DMA_TCDn_ATTR_SMOD. */
Kojto 90:cb3d968589d8 3893 #define BF_DMA_TCDn_ATTR_SMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SMOD) & BM_DMA_TCDn_ATTR_SMOD)
Kojto 90:cb3d968589d8 3894
Kojto 90:cb3d968589d8 3895 /*! @brief Set the SMOD field to a new value. */
Kojto 90:cb3d968589d8 3896 #define BW_DMA_TCDn_ATTR_SMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SMOD) | BF_DMA_TCDn_ATTR_SMOD(v)))
Kojto 90:cb3d968589d8 3897 /*@}*/
Kojto 90:cb3d968589d8 3898 /*******************************************************************************
Kojto 90:cb3d968589d8 3899 * HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
Kojto 90:cb3d968589d8 3900 ******************************************************************************/
Kojto 90:cb3d968589d8 3901
Kojto 90:cb3d968589d8 3902 /*!
Kojto 90:cb3d968589d8 3903 * @brief HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
Kojto 90:cb3d968589d8 3904 *
Kojto 90:cb3d968589d8 3905 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 3906 *
Kojto 90:cb3d968589d8 3907 * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
Kojto 90:cb3d968589d8 3908 * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
Kojto 90:cb3d968589d8 3909 * register to use depends on whether minor loop mapping is disabled, enabled but not
Kojto 90:cb3d968589d8 3910 * used for this channel, or enabled and used. TCD word 2 is defined as follows
Kojto 90:cb3d968589d8 3911 * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
Kojto 90:cb3d968589d8 3912 * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
Kojto 90:cb3d968589d8 3913 * for TCD word 2's definition.
Kojto 90:cb3d968589d8 3914 */
Kojto 90:cb3d968589d8 3915 typedef union _hw_dma_tcdn_nbytes_mlno
Kojto 90:cb3d968589d8 3916 {
Kojto 90:cb3d968589d8 3917 uint32_t U;
Kojto 90:cb3d968589d8 3918 struct _hw_dma_tcdn_nbytes_mlno_bitfields
Kojto 90:cb3d968589d8 3919 {
Kojto 90:cb3d968589d8 3920 uint32_t NBYTES : 32; /*!< [31:0] Minor Byte Transfer Count */
Kojto 90:cb3d968589d8 3921 } B;
Kojto 90:cb3d968589d8 3922 } hw_dma_tcdn_nbytes_mlno_t;
Kojto 90:cb3d968589d8 3923
Kojto 90:cb3d968589d8 3924 /*!
Kojto 90:cb3d968589d8 3925 * @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register
Kojto 90:cb3d968589d8 3926 */
Kojto 90:cb3d968589d8 3927 /*@{*/
Kojto 90:cb3d968589d8 3928 #define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U)
Kojto 90:cb3d968589d8 3929
Kojto 90:cb3d968589d8 3930 #define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
Kojto 90:cb3d968589d8 3931
Kojto 90:cb3d968589d8 3932 #define HW_DMA_TCDn_NBYTES_MLNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mlno_t *) HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n))
Kojto 90:cb3d968589d8 3933 #define HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
Kojto 90:cb3d968589d8 3934 #define HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U = (v))
Kojto 90:cb3d968589d8 3935 #define HW_DMA_TCDn_NBYTES_MLNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 3936 #define HW_DMA_TCDn_NBYTES_MLNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 3937 #define HW_DMA_TCDn_NBYTES_MLNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 3938 /*@}*/
Kojto 90:cb3d968589d8 3939
Kojto 90:cb3d968589d8 3940 /*
Kojto 90:cb3d968589d8 3941 * Constants & macros for individual DMA_TCDn_NBYTES_MLNO bitfields
Kojto 90:cb3d968589d8 3942 */
Kojto 90:cb3d968589d8 3943
Kojto 90:cb3d968589d8 3944 /*!
Kojto 90:cb3d968589d8 3945 * @name Register DMA_TCDn_NBYTES_MLNO, field NBYTES[31:0] (RW)
Kojto 90:cb3d968589d8 3946 *
Kojto 90:cb3d968589d8 3947 * Number of bytes to be transferred in each service request of the channel. As
Kojto 90:cb3d968589d8 3948 * a channel activates, the appropriate TCD contents load into the eDMA engine,
Kojto 90:cb3d968589d8 3949 * and the appropriate reads and writes perform until the minor byte transfer
Kojto 90:cb3d968589d8 3950 * count has transferred. This is an indivisible operation and cannot be halted.
Kojto 90:cb3d968589d8 3951 * (Although, it may be stalled by using the bandwidth control field, or via
Kojto 90:cb3d968589d8 3952 * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
Kojto 90:cb3d968589d8 3953 * written back into the TCD memory, the major iteration count is decremented and
Kojto 90:cb3d968589d8 3954 * restored to the TCD memory. If the major iteration count is completed, additional
Kojto 90:cb3d968589d8 3955 * processing is performed. An NBYTES value of 0x0000_0000 is interpreted as a 4
Kojto 90:cb3d968589d8 3956 * GB transfer.
Kojto 90:cb3d968589d8 3957 */
Kojto 90:cb3d968589d8 3958 /*@{*/
Kojto 90:cb3d968589d8 3959 #define BP_DMA_TCDn_NBYTES_MLNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLNO_NBYTES. */
Kojto 90:cb3d968589d8 3960 #define BM_DMA_TCDn_NBYTES_MLNO_NBYTES (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLNO_NBYTES. */
Kojto 90:cb3d968589d8 3961 #define BS_DMA_TCDn_NBYTES_MLNO_NBYTES (32U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLNO_NBYTES. */
Kojto 90:cb3d968589d8 3962
Kojto 90:cb3d968589d8 3963 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLNO_NBYTES field. */
Kojto 90:cb3d968589d8 3964 #define BR_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
Kojto 90:cb3d968589d8 3965
Kojto 90:cb3d968589d8 3966 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLNO_NBYTES. */
Kojto 90:cb3d968589d8 3967 #define BF_DMA_TCDn_NBYTES_MLNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLNO_NBYTES)
Kojto 90:cb3d968589d8 3968
Kojto 90:cb3d968589d8 3969 /*! @brief Set the NBYTES field to a new value. */
Kojto 90:cb3d968589d8 3970 #define BW_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v))
Kojto 90:cb3d968589d8 3971 /*@}*/
Kojto 90:cb3d968589d8 3972 /*******************************************************************************
Kojto 90:cb3d968589d8 3973 * HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
Kojto 90:cb3d968589d8 3974 ******************************************************************************/
Kojto 90:cb3d968589d8 3975
Kojto 90:cb3d968589d8 3976 /*!
Kojto 90:cb3d968589d8 3977 * @brief HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
Kojto 90:cb3d968589d8 3978 *
Kojto 90:cb3d968589d8 3979 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 3980 *
Kojto 90:cb3d968589d8 3981 * One of three registers (this register, TCD_NBYTES_MLNO, or
Kojto 90:cb3d968589d8 3982 * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
Kojto 90:cb3d968589d8 3983 * depends on whether minor loop mapping is disabled, enabled but not used for
Kojto 90:cb3d968589d8 3984 * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
Kojto 90:cb3d968589d8 3985 * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
Kojto 90:cb3d968589d8 3986 * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
Kojto 90:cb3d968589d8 3987 * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
Kojto 90:cb3d968589d8 3988 * the TCD_NBYTES_MLNO register description.
Kojto 90:cb3d968589d8 3989 */
Kojto 90:cb3d968589d8 3990 typedef union _hw_dma_tcdn_nbytes_mloffno
Kojto 90:cb3d968589d8 3991 {
Kojto 90:cb3d968589d8 3992 uint32_t U;
Kojto 90:cb3d968589d8 3993 struct _hw_dma_tcdn_nbytes_mloffno_bitfields
Kojto 90:cb3d968589d8 3994 {
Kojto 90:cb3d968589d8 3995 uint32_t NBYTES : 30; /*!< [29:0] Minor Byte Transfer Count */
Kojto 90:cb3d968589d8 3996 uint32_t DMLOE : 1; /*!< [30] Destination Minor Loop Offset enable */
Kojto 90:cb3d968589d8 3997 uint32_t SMLOE : 1; /*!< [31] Source Minor Loop Offset Enable */
Kojto 90:cb3d968589d8 3998 } B;
Kojto 90:cb3d968589d8 3999 } hw_dma_tcdn_nbytes_mloffno_t;
Kojto 90:cb3d968589d8 4000
Kojto 90:cb3d968589d8 4001 /*!
Kojto 90:cb3d968589d8 4002 * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register
Kojto 90:cb3d968589d8 4003 */
Kojto 90:cb3d968589d8 4004 /*@{*/
Kojto 90:cb3d968589d8 4005 #define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U)
Kojto 90:cb3d968589d8 4006
Kojto 90:cb3d968589d8 4007 #define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
Kojto 90:cb3d968589d8 4008
Kojto 90:cb3d968589d8 4009 #define HW_DMA_TCDn_NBYTES_MLOFFNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffno_t *) HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n))
Kojto 90:cb3d968589d8 4010 #define HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U)
Kojto 90:cb3d968589d8 4011 #define HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U = (v))
Kojto 90:cb3d968589d8 4012 #define HW_DMA_TCDn_NBYTES_MLOFFNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 4013 #define HW_DMA_TCDn_NBYTES_MLOFFNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 4014 #define HW_DMA_TCDn_NBYTES_MLOFFNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 4015 /*@}*/
Kojto 90:cb3d968589d8 4016
Kojto 90:cb3d968589d8 4017 /*
Kojto 90:cb3d968589d8 4018 * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFNO bitfields
Kojto 90:cb3d968589d8 4019 */
Kojto 90:cb3d968589d8 4020
Kojto 90:cb3d968589d8 4021 /*!
Kojto 90:cb3d968589d8 4022 * @name Register DMA_TCDn_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
Kojto 90:cb3d968589d8 4023 *
Kojto 90:cb3d968589d8 4024 * Number of bytes to be transferred in each service request of the channel. As
Kojto 90:cb3d968589d8 4025 * a channel activates, the appropriate TCD contents load into the eDMA engine,
Kojto 90:cb3d968589d8 4026 * and the appropriate reads and writes perform until the minor byte transfer
Kojto 90:cb3d968589d8 4027 * count has transferred. This is an indivisible operation and cannot be halted;
Kojto 90:cb3d968589d8 4028 * although, it may be stalled by using the bandwidth control field, or via
Kojto 90:cb3d968589d8 4029 * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
Kojto 90:cb3d968589d8 4030 * back into the TCD memory, the major iteration count is decremented and
Kojto 90:cb3d968589d8 4031 * restored to the TCD memory. If the major iteration count is completed, additional
Kojto 90:cb3d968589d8 4032 * processing is performed.
Kojto 90:cb3d968589d8 4033 */
Kojto 90:cb3d968589d8 4034 /*@{*/
Kojto 90:cb3d968589d8 4035 #define BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
Kojto 90:cb3d968589d8 4036 #define BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0x3FFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
Kojto 90:cb3d968589d8 4037 #define BS_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (30U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
Kojto 90:cb3d968589d8 4038
Kojto 90:cb3d968589d8 4039 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_NBYTES field. */
Kojto 90:cb3d968589d8 4040 #define BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).B.NBYTES)
Kojto 90:cb3d968589d8 4041
Kojto 90:cb3d968589d8 4042 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
Kojto 90:cb3d968589d8 4043 #define BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES)
Kojto 90:cb3d968589d8 4044
Kojto 90:cb3d968589d8 4045 /*! @brief Set the NBYTES field to a new value. */
Kojto 90:cb3d968589d8 4046 #define BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v)))
Kojto 90:cb3d968589d8 4047 /*@}*/
Kojto 90:cb3d968589d8 4048
Kojto 90:cb3d968589d8 4049 /*!
Kojto 90:cb3d968589d8 4050 * @name Register DMA_TCDn_NBYTES_MLOFFNO, field DMLOE[30] (RW)
Kojto 90:cb3d968589d8 4051 *
Kojto 90:cb3d968589d8 4052 * Selects whether the minor loop offset is applied to the destination address
Kojto 90:cb3d968589d8 4053 * upon minor loop completion.
Kojto 90:cb3d968589d8 4054 *
Kojto 90:cb3d968589d8 4055 * Values:
Kojto 90:cb3d968589d8 4056 * - 0 - The minor loop offset is not applied to the DADDR
Kojto 90:cb3d968589d8 4057 * - 1 - The minor loop offset is applied to the DADDR
Kojto 90:cb3d968589d8 4058 */
Kojto 90:cb3d968589d8 4059 /*@{*/
Kojto 90:cb3d968589d8 4060 #define BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
Kojto 90:cb3d968589d8 4061 #define BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
Kojto 90:cb3d968589d8 4062 #define BS_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
Kojto 90:cb3d968589d8 4063
Kojto 90:cb3d968589d8 4064 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_DMLOE field. */
Kojto 90:cb3d968589d8 4065 #define BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE))
Kojto 90:cb3d968589d8 4066
Kojto 90:cb3d968589d8 4067 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
Kojto 90:cb3d968589d8 4068 #define BF_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)
Kojto 90:cb3d968589d8 4069
Kojto 90:cb3d968589d8 4070 /*! @brief Set the DMLOE field to a new value. */
Kojto 90:cb3d968589d8 4071 #define BW_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) = (v))
Kojto 90:cb3d968589d8 4072 /*@}*/
Kojto 90:cb3d968589d8 4073
Kojto 90:cb3d968589d8 4074 /*!
Kojto 90:cb3d968589d8 4075 * @name Register DMA_TCDn_NBYTES_MLOFFNO, field SMLOE[31] (RW)
Kojto 90:cb3d968589d8 4076 *
Kojto 90:cb3d968589d8 4077 * Selects whether the minor loop offset is applied to the source address upon
Kojto 90:cb3d968589d8 4078 * minor loop completion.
Kojto 90:cb3d968589d8 4079 *
Kojto 90:cb3d968589d8 4080 * Values:
Kojto 90:cb3d968589d8 4081 * - 0 - The minor loop offset is not applied to the SADDR
Kojto 90:cb3d968589d8 4082 * - 1 - The minor loop offset is applied to the SADDR
Kojto 90:cb3d968589d8 4083 */
Kojto 90:cb3d968589d8 4084 /*@{*/
Kojto 90:cb3d968589d8 4085 #define BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
Kojto 90:cb3d968589d8 4086 #define BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
Kojto 90:cb3d968589d8 4087 #define BS_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
Kojto 90:cb3d968589d8 4088
Kojto 90:cb3d968589d8 4089 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_SMLOE field. */
Kojto 90:cb3d968589d8 4090 #define BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE))
Kojto 90:cb3d968589d8 4091
Kojto 90:cb3d968589d8 4092 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
Kojto 90:cb3d968589d8 4093 #define BF_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)
Kojto 90:cb3d968589d8 4094
Kojto 90:cb3d968589d8 4095 /*! @brief Set the SMLOE field to a new value. */
Kojto 90:cb3d968589d8 4096 #define BW_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) = (v))
Kojto 90:cb3d968589d8 4097 /*@}*/
Kojto 90:cb3d968589d8 4098 /*******************************************************************************
Kojto 90:cb3d968589d8 4099 * HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
Kojto 90:cb3d968589d8 4100 ******************************************************************************/
Kojto 90:cb3d968589d8 4101
Kojto 90:cb3d968589d8 4102 /*!
Kojto 90:cb3d968589d8 4103 * @brief HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
Kojto 90:cb3d968589d8 4104 *
Kojto 90:cb3d968589d8 4105 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 4106 *
Kojto 90:cb3d968589d8 4107 * One of three registers (this register, TCD_NBYTES_MLNO, or
Kojto 90:cb3d968589d8 4108 * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
Kojto 90:cb3d968589d8 4109 * depends on whether minor loop mapping is disabled, enabled but not used for
Kojto 90:cb3d968589d8 4110 * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
Kojto 90:cb3d968589d8 4111 * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
Kojto 90:cb3d968589d8 4112 * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
Kojto 90:cb3d968589d8 4113 * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
Kojto 90:cb3d968589d8 4114 * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
Kojto 90:cb3d968589d8 4115 */
Kojto 90:cb3d968589d8 4116 typedef union _hw_dma_tcdn_nbytes_mloffyes
Kojto 90:cb3d968589d8 4117 {
Kojto 90:cb3d968589d8 4118 uint32_t U;
Kojto 90:cb3d968589d8 4119 struct _hw_dma_tcdn_nbytes_mloffyes_bitfields
Kojto 90:cb3d968589d8 4120 {
Kojto 90:cb3d968589d8 4121 uint32_t NBYTES : 10; /*!< [9:0] Minor Byte Transfer Count */
Kojto 90:cb3d968589d8 4122 uint32_t MLOFF : 20; /*!< [29:10] If SMLOE or DMLOE is set, this
Kojto 90:cb3d968589d8 4123 * field represents a sign-extended offset applied to the source or destination
Kojto 90:cb3d968589d8 4124 * address to form the next-state value after the minor loop completes. */
Kojto 90:cb3d968589d8 4125 uint32_t DMLOE : 1; /*!< [30] Destination Minor Loop Offset enable */
Kojto 90:cb3d968589d8 4126 uint32_t SMLOE : 1; /*!< [31] Source Minor Loop Offset Enable */
Kojto 90:cb3d968589d8 4127 } B;
Kojto 90:cb3d968589d8 4128 } hw_dma_tcdn_nbytes_mloffyes_t;
Kojto 90:cb3d968589d8 4129
Kojto 90:cb3d968589d8 4130 /*!
Kojto 90:cb3d968589d8 4131 * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register
Kojto 90:cb3d968589d8 4132 */
Kojto 90:cb3d968589d8 4133 /*@{*/
Kojto 90:cb3d968589d8 4134 #define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U)
Kojto 90:cb3d968589d8 4135
Kojto 90:cb3d968589d8 4136 #define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
Kojto 90:cb3d968589d8 4137
Kojto 90:cb3d968589d8 4138 #define HW_DMA_TCDn_NBYTES_MLOFFYES(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffyes_t *) HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n))
Kojto 90:cb3d968589d8 4139 #define HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U)
Kojto 90:cb3d968589d8 4140 #define HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U = (v))
Kojto 90:cb3d968589d8 4141 #define HW_DMA_TCDn_NBYTES_MLOFFYES_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 4142 #define HW_DMA_TCDn_NBYTES_MLOFFYES_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 4143 #define HW_DMA_TCDn_NBYTES_MLOFFYES_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 4144 /*@}*/
Kojto 90:cb3d968589d8 4145
Kojto 90:cb3d968589d8 4146 /*
Kojto 90:cb3d968589d8 4147 * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFYES bitfields
Kojto 90:cb3d968589d8 4148 */
Kojto 90:cb3d968589d8 4149
Kojto 90:cb3d968589d8 4150 /*!
Kojto 90:cb3d968589d8 4151 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
Kojto 90:cb3d968589d8 4152 *
Kojto 90:cb3d968589d8 4153 * Number of bytes to be transferred in each service request of the channel. As
Kojto 90:cb3d968589d8 4154 * a channel activates, the appropriate TCD contents load into the eDMA engine,
Kojto 90:cb3d968589d8 4155 * and the appropriate reads and writes perform until the minor byte transfer
Kojto 90:cb3d968589d8 4156 * count has transferred. This is an indivisible operation and cannot be halted.
Kojto 90:cb3d968589d8 4157 * (Although, it may be stalled by using the bandwidth control field, or via
Kojto 90:cb3d968589d8 4158 * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
Kojto 90:cb3d968589d8 4159 * written back into the TCD memory, the major iteration count is decremented and
Kojto 90:cb3d968589d8 4160 * restored to the TCD memory. If the major iteration count is completed, additional
Kojto 90:cb3d968589d8 4161 * processing is performed.
Kojto 90:cb3d968589d8 4162 */
Kojto 90:cb3d968589d8 4163 /*@{*/
Kojto 90:cb3d968589d8 4164 #define BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
Kojto 90:cb3d968589d8 4165 #define BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0x000003FFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
Kojto 90:cb3d968589d8 4166 #define BS_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (10U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
Kojto 90:cb3d968589d8 4167
Kojto 90:cb3d968589d8 4168 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_NBYTES field. */
Kojto 90:cb3d968589d8 4169 #define BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.NBYTES)
Kojto 90:cb3d968589d8 4170
Kojto 90:cb3d968589d8 4171 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
Kojto 90:cb3d968589d8 4172 #define BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES)
Kojto 90:cb3d968589d8 4173
Kojto 90:cb3d968589d8 4174 /*! @brief Set the NBYTES field to a new value. */
Kojto 90:cb3d968589d8 4175 #define BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v)))
Kojto 90:cb3d968589d8 4176 /*@}*/
Kojto 90:cb3d968589d8 4177
Kojto 90:cb3d968589d8 4178 /*!
Kojto 90:cb3d968589d8 4179 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
Kojto 90:cb3d968589d8 4180 */
Kojto 90:cb3d968589d8 4181 /*@{*/
Kojto 90:cb3d968589d8 4182 #define BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (10U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
Kojto 90:cb3d968589d8 4183 #define BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (0x3FFFFC00U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
Kojto 90:cb3d968589d8 4184 #define BS_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (20U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
Kojto 90:cb3d968589d8 4185
Kojto 90:cb3d968589d8 4186 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_MLOFF field. */
Kojto 90:cb3d968589d8 4187 #define BR_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.MLOFF)
Kojto 90:cb3d968589d8 4188
Kojto 90:cb3d968589d8 4189 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
Kojto 90:cb3d968589d8 4190 #define BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) & BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF)
Kojto 90:cb3d968589d8 4191
Kojto 90:cb3d968589d8 4192 /*! @brief Set the MLOFF field to a new value. */
Kojto 90:cb3d968589d8 4193 #define BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) | BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v)))
Kojto 90:cb3d968589d8 4194 /*@}*/
Kojto 90:cb3d968589d8 4195
Kojto 90:cb3d968589d8 4196 /*!
Kojto 90:cb3d968589d8 4197 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field DMLOE[30] (RW)
Kojto 90:cb3d968589d8 4198 *
Kojto 90:cb3d968589d8 4199 * Selects whether the minor loop offset is applied to the destination address
Kojto 90:cb3d968589d8 4200 * upon minor loop completion.
Kojto 90:cb3d968589d8 4201 *
Kojto 90:cb3d968589d8 4202 * Values:
Kojto 90:cb3d968589d8 4203 * - 0 - The minor loop offset is not applied to the DADDR
Kojto 90:cb3d968589d8 4204 * - 1 - The minor loop offset is applied to the DADDR
Kojto 90:cb3d968589d8 4205 */
Kojto 90:cb3d968589d8 4206 /*@{*/
Kojto 90:cb3d968589d8 4207 #define BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
Kojto 90:cb3d968589d8 4208 #define BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
Kojto 90:cb3d968589d8 4209 #define BS_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
Kojto 90:cb3d968589d8 4210
Kojto 90:cb3d968589d8 4211 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_DMLOE field. */
Kojto 90:cb3d968589d8 4212 #define BR_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE))
Kojto 90:cb3d968589d8 4213
Kojto 90:cb3d968589d8 4214 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
Kojto 90:cb3d968589d8 4215 #define BF_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)
Kojto 90:cb3d968589d8 4216
Kojto 90:cb3d968589d8 4217 /*! @brief Set the DMLOE field to a new value. */
Kojto 90:cb3d968589d8 4218 #define BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) = (v))
Kojto 90:cb3d968589d8 4219 /*@}*/
Kojto 90:cb3d968589d8 4220
Kojto 90:cb3d968589d8 4221 /*!
Kojto 90:cb3d968589d8 4222 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field SMLOE[31] (RW)
Kojto 90:cb3d968589d8 4223 *
Kojto 90:cb3d968589d8 4224 * Selects whether the minor loop offset is applied to the source address upon
Kojto 90:cb3d968589d8 4225 * minor loop completion.
Kojto 90:cb3d968589d8 4226 *
Kojto 90:cb3d968589d8 4227 * Values:
Kojto 90:cb3d968589d8 4228 * - 0 - The minor loop offset is not applied to the SADDR
Kojto 90:cb3d968589d8 4229 * - 1 - The minor loop offset is applied to the SADDR
Kojto 90:cb3d968589d8 4230 */
Kojto 90:cb3d968589d8 4231 /*@{*/
Kojto 90:cb3d968589d8 4232 #define BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
Kojto 90:cb3d968589d8 4233 #define BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
Kojto 90:cb3d968589d8 4234 #define BS_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
Kojto 90:cb3d968589d8 4235
Kojto 90:cb3d968589d8 4236 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_SMLOE field. */
Kojto 90:cb3d968589d8 4237 #define BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE))
Kojto 90:cb3d968589d8 4238
Kojto 90:cb3d968589d8 4239 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
Kojto 90:cb3d968589d8 4240 #define BF_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)
Kojto 90:cb3d968589d8 4241
Kojto 90:cb3d968589d8 4242 /*! @brief Set the SMLOE field to a new value. */
Kojto 90:cb3d968589d8 4243 #define BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) = (v))
Kojto 90:cb3d968589d8 4244 /*@}*/
Kojto 90:cb3d968589d8 4245 /*******************************************************************************
Kojto 90:cb3d968589d8 4246 * HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
Kojto 90:cb3d968589d8 4247 ******************************************************************************/
Kojto 90:cb3d968589d8 4248
Kojto 90:cb3d968589d8 4249 /*!
Kojto 90:cb3d968589d8 4250 * @brief HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment (RW)
Kojto 90:cb3d968589d8 4251 *
Kojto 90:cb3d968589d8 4252 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 4253 */
Kojto 90:cb3d968589d8 4254 typedef union _hw_dma_tcdn_slast
Kojto 90:cb3d968589d8 4255 {
Kojto 90:cb3d968589d8 4256 uint32_t U;
Kojto 90:cb3d968589d8 4257 struct _hw_dma_tcdn_slast_bitfields
Kojto 90:cb3d968589d8 4258 {
Kojto 90:cb3d968589d8 4259 uint32_t SLAST : 32; /*!< [31:0] Last source Address Adjustment */
Kojto 90:cb3d968589d8 4260 } B;
Kojto 90:cb3d968589d8 4261 } hw_dma_tcdn_slast_t;
Kojto 90:cb3d968589d8 4262
Kojto 90:cb3d968589d8 4263 /*!
Kojto 90:cb3d968589d8 4264 * @name Constants and macros for entire DMA_TCDn_SLAST register
Kojto 90:cb3d968589d8 4265 */
Kojto 90:cb3d968589d8 4266 /*@{*/
Kojto 90:cb3d968589d8 4267 #define HW_DMA_TCDn_SLAST_COUNT (16U)
Kojto 90:cb3d968589d8 4268
Kojto 90:cb3d968589d8 4269 #define HW_DMA_TCDn_SLAST_ADDR(x, n) ((x) + 0x100CU + (0x20U * (n)))
Kojto 90:cb3d968589d8 4270
Kojto 90:cb3d968589d8 4271 #define HW_DMA_TCDn_SLAST(x, n) (*(__IO hw_dma_tcdn_slast_t *) HW_DMA_TCDn_SLAST_ADDR(x, n))
Kojto 90:cb3d968589d8 4272 #define HW_DMA_TCDn_SLAST_RD(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
Kojto 90:cb3d968589d8 4273 #define HW_DMA_TCDn_SLAST_WR(x, n, v) (HW_DMA_TCDn_SLAST(x, n).U = (v))
Kojto 90:cb3d968589d8 4274 #define HW_DMA_TCDn_SLAST_SET(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 4275 #define HW_DMA_TCDn_SLAST_CLR(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 4276 #define HW_DMA_TCDn_SLAST_TOG(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 4277 /*@}*/
Kojto 90:cb3d968589d8 4278
Kojto 90:cb3d968589d8 4279 /*
Kojto 90:cb3d968589d8 4280 * Constants & macros for individual DMA_TCDn_SLAST bitfields
Kojto 90:cb3d968589d8 4281 */
Kojto 90:cb3d968589d8 4282
Kojto 90:cb3d968589d8 4283 /*!
Kojto 90:cb3d968589d8 4284 * @name Register DMA_TCDn_SLAST, field SLAST[31:0] (RW)
Kojto 90:cb3d968589d8 4285 *
Kojto 90:cb3d968589d8 4286 * Adjustment value added to the source address at the completion of the major
Kojto 90:cb3d968589d8 4287 * iteration count. This value can be applied to restore the source address to the
Kojto 90:cb3d968589d8 4288 * initial value, or adjust the address to reference the next data structure.
Kojto 90:cb3d968589d8 4289 * This register uses two's complement notation; the overflow bit is discarded.
Kojto 90:cb3d968589d8 4290 */
Kojto 90:cb3d968589d8 4291 /*@{*/
Kojto 90:cb3d968589d8 4292 #define BP_DMA_TCDn_SLAST_SLAST (0U) /*!< Bit position for DMA_TCDn_SLAST_SLAST. */
Kojto 90:cb3d968589d8 4293 #define BM_DMA_TCDn_SLAST_SLAST (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SLAST_SLAST. */
Kojto 90:cb3d968589d8 4294 #define BS_DMA_TCDn_SLAST_SLAST (32U) /*!< Bit field size in bits for DMA_TCDn_SLAST_SLAST. */
Kojto 90:cb3d968589d8 4295
Kojto 90:cb3d968589d8 4296 /*! @brief Read current value of the DMA_TCDn_SLAST_SLAST field. */
Kojto 90:cb3d968589d8 4297 #define BR_DMA_TCDn_SLAST_SLAST(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
Kojto 90:cb3d968589d8 4298
Kojto 90:cb3d968589d8 4299 /*! @brief Format value for bitfield DMA_TCDn_SLAST_SLAST. */
Kojto 90:cb3d968589d8 4300 #define BF_DMA_TCDn_SLAST_SLAST(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SLAST_SLAST) & BM_DMA_TCDn_SLAST_SLAST)
Kojto 90:cb3d968589d8 4301
Kojto 90:cb3d968589d8 4302 /*! @brief Set the SLAST field to a new value. */
Kojto 90:cb3d968589d8 4303 #define BW_DMA_TCDn_SLAST_SLAST(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, v))
Kojto 90:cb3d968589d8 4304 /*@}*/
Kojto 90:cb3d968589d8 4305 /*******************************************************************************
Kojto 90:cb3d968589d8 4306 * HW_DMA_TCDn_DADDR - TCD Destination Address
Kojto 90:cb3d968589d8 4307 ******************************************************************************/
Kojto 90:cb3d968589d8 4308
Kojto 90:cb3d968589d8 4309 /*!
Kojto 90:cb3d968589d8 4310 * @brief HW_DMA_TCDn_DADDR - TCD Destination Address (RW)
Kojto 90:cb3d968589d8 4311 *
Kojto 90:cb3d968589d8 4312 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 4313 */
Kojto 90:cb3d968589d8 4314 typedef union _hw_dma_tcdn_daddr
Kojto 90:cb3d968589d8 4315 {
Kojto 90:cb3d968589d8 4316 uint32_t U;
Kojto 90:cb3d968589d8 4317 struct _hw_dma_tcdn_daddr_bitfields
Kojto 90:cb3d968589d8 4318 {
Kojto 90:cb3d968589d8 4319 uint32_t DADDR : 32; /*!< [31:0] Destination Address */
Kojto 90:cb3d968589d8 4320 } B;
Kojto 90:cb3d968589d8 4321 } hw_dma_tcdn_daddr_t;
Kojto 90:cb3d968589d8 4322
Kojto 90:cb3d968589d8 4323 /*!
Kojto 90:cb3d968589d8 4324 * @name Constants and macros for entire DMA_TCDn_DADDR register
Kojto 90:cb3d968589d8 4325 */
Kojto 90:cb3d968589d8 4326 /*@{*/
Kojto 90:cb3d968589d8 4327 #define HW_DMA_TCDn_DADDR_COUNT (16U)
Kojto 90:cb3d968589d8 4328
Kojto 90:cb3d968589d8 4329 #define HW_DMA_TCDn_DADDR_ADDR(x, n) ((x) + 0x1010U + (0x20U * (n)))
Kojto 90:cb3d968589d8 4330
Kojto 90:cb3d968589d8 4331 #define HW_DMA_TCDn_DADDR(x, n) (*(__IO hw_dma_tcdn_daddr_t *) HW_DMA_TCDn_DADDR_ADDR(x, n))
Kojto 90:cb3d968589d8 4332 #define HW_DMA_TCDn_DADDR_RD(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
Kojto 90:cb3d968589d8 4333 #define HW_DMA_TCDn_DADDR_WR(x, n, v) (HW_DMA_TCDn_DADDR(x, n).U = (v))
Kojto 90:cb3d968589d8 4334 #define HW_DMA_TCDn_DADDR_SET(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 4335 #define HW_DMA_TCDn_DADDR_CLR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 4336 #define HW_DMA_TCDn_DADDR_TOG(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 4337 /*@}*/
Kojto 90:cb3d968589d8 4338
Kojto 90:cb3d968589d8 4339 /*
Kojto 90:cb3d968589d8 4340 * Constants & macros for individual DMA_TCDn_DADDR bitfields
Kojto 90:cb3d968589d8 4341 */
Kojto 90:cb3d968589d8 4342
Kojto 90:cb3d968589d8 4343 /*!
Kojto 90:cb3d968589d8 4344 * @name Register DMA_TCDn_DADDR, field DADDR[31:0] (RW)
Kojto 90:cb3d968589d8 4345 *
Kojto 90:cb3d968589d8 4346 * Memory address pointing to the destination data.
Kojto 90:cb3d968589d8 4347 */
Kojto 90:cb3d968589d8 4348 /*@{*/
Kojto 90:cb3d968589d8 4349 #define BP_DMA_TCDn_DADDR_DADDR (0U) /*!< Bit position for DMA_TCDn_DADDR_DADDR. */
Kojto 90:cb3d968589d8 4350 #define BM_DMA_TCDn_DADDR_DADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DADDR_DADDR. */
Kojto 90:cb3d968589d8 4351 #define BS_DMA_TCDn_DADDR_DADDR (32U) /*!< Bit field size in bits for DMA_TCDn_DADDR_DADDR. */
Kojto 90:cb3d968589d8 4352
Kojto 90:cb3d968589d8 4353 /*! @brief Read current value of the DMA_TCDn_DADDR_DADDR field. */
Kojto 90:cb3d968589d8 4354 #define BR_DMA_TCDn_DADDR_DADDR(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
Kojto 90:cb3d968589d8 4355
Kojto 90:cb3d968589d8 4356 /*! @brief Format value for bitfield DMA_TCDn_DADDR_DADDR. */
Kojto 90:cb3d968589d8 4357 #define BF_DMA_TCDn_DADDR_DADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DADDR_DADDR) & BM_DMA_TCDn_DADDR_DADDR)
Kojto 90:cb3d968589d8 4358
Kojto 90:cb3d968589d8 4359 /*! @brief Set the DADDR field to a new value. */
Kojto 90:cb3d968589d8 4360 #define BW_DMA_TCDn_DADDR_DADDR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, v))
Kojto 90:cb3d968589d8 4361 /*@}*/
Kojto 90:cb3d968589d8 4362 /*******************************************************************************
Kojto 90:cb3d968589d8 4363 * HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
Kojto 90:cb3d968589d8 4364 ******************************************************************************/
Kojto 90:cb3d968589d8 4365
Kojto 90:cb3d968589d8 4366 /*!
Kojto 90:cb3d968589d8 4367 * @brief HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset (RW)
Kojto 90:cb3d968589d8 4368 *
Kojto 90:cb3d968589d8 4369 * Reset value: 0x0000U
Kojto 90:cb3d968589d8 4370 */
Kojto 90:cb3d968589d8 4371 typedef union _hw_dma_tcdn_doff
Kojto 90:cb3d968589d8 4372 {
Kojto 90:cb3d968589d8 4373 uint16_t U;
Kojto 90:cb3d968589d8 4374 struct _hw_dma_tcdn_doff_bitfields
Kojto 90:cb3d968589d8 4375 {
Kojto 90:cb3d968589d8 4376 uint16_t DOFF : 16; /*!< [15:0] Destination Address Signed offset */
Kojto 90:cb3d968589d8 4377 } B;
Kojto 90:cb3d968589d8 4378 } hw_dma_tcdn_doff_t;
Kojto 90:cb3d968589d8 4379
Kojto 90:cb3d968589d8 4380 /*!
Kojto 90:cb3d968589d8 4381 * @name Constants and macros for entire DMA_TCDn_DOFF register
Kojto 90:cb3d968589d8 4382 */
Kojto 90:cb3d968589d8 4383 /*@{*/
Kojto 90:cb3d968589d8 4384 #define HW_DMA_TCDn_DOFF_COUNT (16U)
Kojto 90:cb3d968589d8 4385
Kojto 90:cb3d968589d8 4386 #define HW_DMA_TCDn_DOFF_ADDR(x, n) ((x) + 0x1014U + (0x20U * (n)))
Kojto 90:cb3d968589d8 4387
Kojto 90:cb3d968589d8 4388 #define HW_DMA_TCDn_DOFF(x, n) (*(__IO hw_dma_tcdn_doff_t *) HW_DMA_TCDn_DOFF_ADDR(x, n))
Kojto 90:cb3d968589d8 4389 #define HW_DMA_TCDn_DOFF_RD(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
Kojto 90:cb3d968589d8 4390 #define HW_DMA_TCDn_DOFF_WR(x, n, v) (HW_DMA_TCDn_DOFF(x, n).U = (v))
Kojto 90:cb3d968589d8 4391 #define HW_DMA_TCDn_DOFF_SET(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 4392 #define HW_DMA_TCDn_DOFF_CLR(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 4393 #define HW_DMA_TCDn_DOFF_TOG(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 4394 /*@}*/
Kojto 90:cb3d968589d8 4395
Kojto 90:cb3d968589d8 4396 /*
Kojto 90:cb3d968589d8 4397 * Constants & macros for individual DMA_TCDn_DOFF bitfields
Kojto 90:cb3d968589d8 4398 */
Kojto 90:cb3d968589d8 4399
Kojto 90:cb3d968589d8 4400 /*!
Kojto 90:cb3d968589d8 4401 * @name Register DMA_TCDn_DOFF, field DOFF[15:0] (RW)
Kojto 90:cb3d968589d8 4402 *
Kojto 90:cb3d968589d8 4403 * Sign-extended offset applied to the current destination address to form the
Kojto 90:cb3d968589d8 4404 * next-state value as each destination write is completed.
Kojto 90:cb3d968589d8 4405 */
Kojto 90:cb3d968589d8 4406 /*@{*/
Kojto 90:cb3d968589d8 4407 #define BP_DMA_TCDn_DOFF_DOFF (0U) /*!< Bit position for DMA_TCDn_DOFF_DOFF. */
Kojto 90:cb3d968589d8 4408 #define BM_DMA_TCDn_DOFF_DOFF (0xFFFFU) /*!< Bit mask for DMA_TCDn_DOFF_DOFF. */
Kojto 90:cb3d968589d8 4409 #define BS_DMA_TCDn_DOFF_DOFF (16U) /*!< Bit field size in bits for DMA_TCDn_DOFF_DOFF. */
Kojto 90:cb3d968589d8 4410
Kojto 90:cb3d968589d8 4411 /*! @brief Read current value of the DMA_TCDn_DOFF_DOFF field. */
Kojto 90:cb3d968589d8 4412 #define BR_DMA_TCDn_DOFF_DOFF(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
Kojto 90:cb3d968589d8 4413
Kojto 90:cb3d968589d8 4414 /*! @brief Format value for bitfield DMA_TCDn_DOFF_DOFF. */
Kojto 90:cb3d968589d8 4415 #define BF_DMA_TCDn_DOFF_DOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_DOFF_DOFF) & BM_DMA_TCDn_DOFF_DOFF)
Kojto 90:cb3d968589d8 4416
Kojto 90:cb3d968589d8 4417 /*! @brief Set the DOFF field to a new value. */
Kojto 90:cb3d968589d8 4418 #define BW_DMA_TCDn_DOFF_DOFF(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, v))
Kojto 90:cb3d968589d8 4419 /*@}*/
Kojto 90:cb3d968589d8 4420 /*******************************************************************************
Kojto 90:cb3d968589d8 4421 * HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
Kojto 90:cb3d968589d8 4422 ******************************************************************************/
Kojto 90:cb3d968589d8 4423
Kojto 90:cb3d968589d8 4424 /*!
Kojto 90:cb3d968589d8 4425 * @brief HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
Kojto 90:cb3d968589d8 4426 *
Kojto 90:cb3d968589d8 4427 * Reset value: 0x0000U
Kojto 90:cb3d968589d8 4428 *
Kojto 90:cb3d968589d8 4429 * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
Kojto 90:cb3d968589d8 4430 * follows.
Kojto 90:cb3d968589d8 4431 */
Kojto 90:cb3d968589d8 4432 typedef union _hw_dma_tcdn_citer_elinkno
Kojto 90:cb3d968589d8 4433 {
Kojto 90:cb3d968589d8 4434 uint16_t U;
Kojto 90:cb3d968589d8 4435 struct _hw_dma_tcdn_citer_elinkno_bitfields
Kojto 90:cb3d968589d8 4436 {
Kojto 90:cb3d968589d8 4437 uint16_t CITER : 15; /*!< [14:0] Current Major Iteration Count */
Kojto 90:cb3d968589d8 4438 uint16_t ELINK : 1; /*!< [15] Enable channel-to-channel linking on
Kojto 90:cb3d968589d8 4439 * minor-loop complete */
Kojto 90:cb3d968589d8 4440 } B;
Kojto 90:cb3d968589d8 4441 } hw_dma_tcdn_citer_elinkno_t;
Kojto 90:cb3d968589d8 4442
Kojto 90:cb3d968589d8 4443 /*!
Kojto 90:cb3d968589d8 4444 * @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register
Kojto 90:cb3d968589d8 4445 */
Kojto 90:cb3d968589d8 4446 /*@{*/
Kojto 90:cb3d968589d8 4447 #define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U)
Kojto 90:cb3d968589d8 4448
Kojto 90:cb3d968589d8 4449 #define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n)))
Kojto 90:cb3d968589d8 4450
Kojto 90:cb3d968589d8 4451 #define HW_DMA_TCDn_CITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_citer_elinkno_t *) HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n))
Kojto 90:cb3d968589d8 4452 #define HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U)
Kojto 90:cb3d968589d8 4453 #define HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U = (v))
Kojto 90:cb3d968589d8 4454 #define HW_DMA_TCDn_CITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 4455 #define HW_DMA_TCDn_CITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 4456 #define HW_DMA_TCDn_CITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 4457 /*@}*/
Kojto 90:cb3d968589d8 4458
Kojto 90:cb3d968589d8 4459 /*
Kojto 90:cb3d968589d8 4460 * Constants & macros for individual DMA_TCDn_CITER_ELINKNO bitfields
Kojto 90:cb3d968589d8 4461 */
Kojto 90:cb3d968589d8 4462
Kojto 90:cb3d968589d8 4463 /*!
Kojto 90:cb3d968589d8 4464 * @name Register DMA_TCDn_CITER_ELINKNO, field CITER[14:0] (RW)
Kojto 90:cb3d968589d8 4465 *
Kojto 90:cb3d968589d8 4466 * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
Kojto 90:cb3d968589d8 4467 * major loop count for the channel. It is decremented each time the minor loop is
Kojto 90:cb3d968589d8 4468 * completed and updated in the transfer control descriptor memory. After the
Kojto 90:cb3d968589d8 4469 * major iteration count is exhausted, the channel performs a number of operations
Kojto 90:cb3d968589d8 4470 * (e.g., final source and destination address calculations), optionally generating
Kojto 90:cb3d968589d8 4471 * an interrupt to signal channel completion before reloading the CITER field
Kojto 90:cb3d968589d8 4472 * from the beginning iteration count (BITER) field. When the CITER field is
Kojto 90:cb3d968589d8 4473 * initially loaded by software, it must be set to the same value as that contained in
Kojto 90:cb3d968589d8 4474 * the BITER field. If the channel is configured to execute a single service
Kojto 90:cb3d968589d8 4475 * request, the initial values of BITER and CITER should be 0x0001.
Kojto 90:cb3d968589d8 4476 */
Kojto 90:cb3d968589d8 4477 /*@{*/
Kojto 90:cb3d968589d8 4478 #define BP_DMA_TCDn_CITER_ELINKNO_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_CITER. */
Kojto 90:cb3d968589d8 4479 #define BM_DMA_TCDn_CITER_ELINKNO_CITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_CITER. */
Kojto 90:cb3d968589d8 4480 #define BS_DMA_TCDn_CITER_ELINKNO_CITER (15U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_CITER. */
Kojto 90:cb3d968589d8 4481
Kojto 90:cb3d968589d8 4482 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_CITER field. */
Kojto 90:cb3d968589d8 4483 #define BR_DMA_TCDn_CITER_ELINKNO_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).B.CITER)
Kojto 90:cb3d968589d8 4484
Kojto 90:cb3d968589d8 4485 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_CITER. */
Kojto 90:cb3d968589d8 4486 #define BF_DMA_TCDn_CITER_ELINKNO_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_CITER) & BM_DMA_TCDn_CITER_ELINKNO_CITER)
Kojto 90:cb3d968589d8 4487
Kojto 90:cb3d968589d8 4488 /*! @brief Set the CITER field to a new value. */
Kojto 90:cb3d968589d8 4489 #define BW_DMA_TCDn_CITER_ELINKNO_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKNO_CITER) | BF_DMA_TCDn_CITER_ELINKNO_CITER(v)))
Kojto 90:cb3d968589d8 4490 /*@}*/
Kojto 90:cb3d968589d8 4491
Kojto 90:cb3d968589d8 4492 /*!
Kojto 90:cb3d968589d8 4493 * @name Register DMA_TCDn_CITER_ELINKNO, field ELINK[15] (RW)
Kojto 90:cb3d968589d8 4494 *
Kojto 90:cb3d968589d8 4495 * As the channel completes the minor loop, this flag enables linking to another
Kojto 90:cb3d968589d8 4496 * channel, defined by the LINKCH field. The link target channel initiates a
Kojto 90:cb3d968589d8 4497 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
Kojto 90:cb3d968589d8 4498 * bit of the specified channel. If channel linking is disabled, the CITER value
Kojto 90:cb3d968589d8 4499 * is extended to 15 bits in place of a link channel number. If the major loop is
Kojto 90:cb3d968589d8 4500 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
Kojto 90:cb3d968589d8 4501 * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
Kojto 90:cb3d968589d8 4502 * configuration error is reported.
Kojto 90:cb3d968589d8 4503 *
Kojto 90:cb3d968589d8 4504 * Values:
Kojto 90:cb3d968589d8 4505 * - 0 - The channel-to-channel linking is disabled
Kojto 90:cb3d968589d8 4506 * - 1 - The channel-to-channel linking is enabled
Kojto 90:cb3d968589d8 4507 */
Kojto 90:cb3d968589d8 4508 /*@{*/
Kojto 90:cb3d968589d8 4509 #define BP_DMA_TCDn_CITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_ELINK. */
Kojto 90:cb3d968589d8 4510 #define BM_DMA_TCDn_CITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_ELINK. */
Kojto 90:cb3d968589d8 4511 #define BS_DMA_TCDn_CITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_ELINK. */
Kojto 90:cb3d968589d8 4512
Kojto 90:cb3d968589d8 4513 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_ELINK field. */
Kojto 90:cb3d968589d8 4514 #define BR_DMA_TCDn_CITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK))
Kojto 90:cb3d968589d8 4515
Kojto 90:cb3d968589d8 4516 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_ELINK. */
Kojto 90:cb3d968589d8 4517 #define BF_DMA_TCDn_CITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_ELINK) & BM_DMA_TCDn_CITER_ELINKNO_ELINK)
Kojto 90:cb3d968589d8 4518
Kojto 90:cb3d968589d8 4519 /*! @brief Set the ELINK field to a new value. */
Kojto 90:cb3d968589d8 4520 #define BW_DMA_TCDn_CITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK) = (v))
Kojto 90:cb3d968589d8 4521 /*@}*/
Kojto 90:cb3d968589d8 4522 /*******************************************************************************
Kojto 90:cb3d968589d8 4523 * HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
Kojto 90:cb3d968589d8 4524 ******************************************************************************/
Kojto 90:cb3d968589d8 4525
Kojto 90:cb3d968589d8 4526 /*!
Kojto 90:cb3d968589d8 4527 * @brief HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
Kojto 90:cb3d968589d8 4528 *
Kojto 90:cb3d968589d8 4529 * Reset value: 0x0000U
Kojto 90:cb3d968589d8 4530 *
Kojto 90:cb3d968589d8 4531 * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
Kojto 90:cb3d968589d8 4532 */
Kojto 90:cb3d968589d8 4533 typedef union _hw_dma_tcdn_citer_elinkyes
Kojto 90:cb3d968589d8 4534 {
Kojto 90:cb3d968589d8 4535 uint16_t U;
Kojto 90:cb3d968589d8 4536 struct _hw_dma_tcdn_citer_elinkyes_bitfields
Kojto 90:cb3d968589d8 4537 {
Kojto 90:cb3d968589d8 4538 uint16_t CITER : 9; /*!< [8:0] Current Major Iteration Count */
Kojto 90:cb3d968589d8 4539 uint16_t LINKCH : 4; /*!< [12:9] Link Channel Number */
Kojto 90:cb3d968589d8 4540 uint16_t RESERVED0 : 2; /*!< [14:13] */
Kojto 90:cb3d968589d8 4541 uint16_t ELINK : 1; /*!< [15] Enable channel-to-channel linking on
Kojto 90:cb3d968589d8 4542 * minor-loop complete */
Kojto 90:cb3d968589d8 4543 } B;
Kojto 90:cb3d968589d8 4544 } hw_dma_tcdn_citer_elinkyes_t;
Kojto 90:cb3d968589d8 4545
Kojto 90:cb3d968589d8 4546 /*!
Kojto 90:cb3d968589d8 4547 * @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register
Kojto 90:cb3d968589d8 4548 */
Kojto 90:cb3d968589d8 4549 /*@{*/
Kojto 90:cb3d968589d8 4550 #define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U)
Kojto 90:cb3d968589d8 4551
Kojto 90:cb3d968589d8 4552 #define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n)))
Kojto 90:cb3d968589d8 4553
Kojto 90:cb3d968589d8 4554 #define HW_DMA_TCDn_CITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_citer_elinkyes_t *) HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n))
Kojto 90:cb3d968589d8 4555 #define HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U)
Kojto 90:cb3d968589d8 4556 #define HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U = (v))
Kojto 90:cb3d968589d8 4557 #define HW_DMA_TCDn_CITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 4558 #define HW_DMA_TCDn_CITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 4559 #define HW_DMA_TCDn_CITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 4560 /*@}*/
Kojto 90:cb3d968589d8 4561
Kojto 90:cb3d968589d8 4562 /*
Kojto 90:cb3d968589d8 4563 * Constants & macros for individual DMA_TCDn_CITER_ELINKYES bitfields
Kojto 90:cb3d968589d8 4564 */
Kojto 90:cb3d968589d8 4565
Kojto 90:cb3d968589d8 4566 /*!
Kojto 90:cb3d968589d8 4567 * @name Register DMA_TCDn_CITER_ELINKYES, field CITER[8:0] (RW)
Kojto 90:cb3d968589d8 4568 *
Kojto 90:cb3d968589d8 4569 * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
Kojto 90:cb3d968589d8 4570 * major loop count for the channel. It is decremented each time the minor loop is
Kojto 90:cb3d968589d8 4571 * completed and updated in the transfer control descriptor memory. After the
Kojto 90:cb3d968589d8 4572 * major iteration count is exhausted, the channel performs a number of operations
Kojto 90:cb3d968589d8 4573 * (e.g., final source and destination address calculations), optionally generating
Kojto 90:cb3d968589d8 4574 * an interrupt to signal channel completion before reloading the CITER field
Kojto 90:cb3d968589d8 4575 * from the beginning iteration count (BITER) field. When the CITER field is
Kojto 90:cb3d968589d8 4576 * initially loaded by software, it must be set to the same value as that contained in
Kojto 90:cb3d968589d8 4577 * the BITER field. If the channel is configured to execute a single service
Kojto 90:cb3d968589d8 4578 * request, the initial values of BITER and CITER should be 0x0001.
Kojto 90:cb3d968589d8 4579 */
Kojto 90:cb3d968589d8 4580 /*@{*/
Kojto 90:cb3d968589d8 4581 #define BP_DMA_TCDn_CITER_ELINKYES_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_CITER. */
Kojto 90:cb3d968589d8 4582 #define BM_DMA_TCDn_CITER_ELINKYES_CITER (0x01FFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_CITER. */
Kojto 90:cb3d968589d8 4583 #define BS_DMA_TCDn_CITER_ELINKYES_CITER (9U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_CITER. */
Kojto 90:cb3d968589d8 4584
Kojto 90:cb3d968589d8 4585 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_CITER field. */
Kojto 90:cb3d968589d8 4586 #define BR_DMA_TCDn_CITER_ELINKYES_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.CITER)
Kojto 90:cb3d968589d8 4587
Kojto 90:cb3d968589d8 4588 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_CITER. */
Kojto 90:cb3d968589d8 4589 #define BF_DMA_TCDn_CITER_ELINKYES_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_CITER) & BM_DMA_TCDn_CITER_ELINKYES_CITER)
Kojto 90:cb3d968589d8 4590
Kojto 90:cb3d968589d8 4591 /*! @brief Set the CITER field to a new value. */
Kojto 90:cb3d968589d8 4592 #define BW_DMA_TCDn_CITER_ELINKYES_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_CITER) | BF_DMA_TCDn_CITER_ELINKYES_CITER(v)))
Kojto 90:cb3d968589d8 4593 /*@}*/
Kojto 90:cb3d968589d8 4594
Kojto 90:cb3d968589d8 4595 /*!
Kojto 90:cb3d968589d8 4596 * @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW)
Kojto 90:cb3d968589d8 4597 *
Kojto 90:cb3d968589d8 4598 * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
Kojto 90:cb3d968589d8 4599 * loop is exhausted, the eDMA engine initiates a channel service request to the
Kojto 90:cb3d968589d8 4600 * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
Kojto 90:cb3d968589d8 4601 */
Kojto 90:cb3d968589d8 4602 /*@{*/
Kojto 90:cb3d968589d8 4603 #define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH. */
Kojto 90:cb3d968589d8 4604 #define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH. */
Kojto 90:cb3d968589d8 4605 #define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH. */
Kojto 90:cb3d968589d8 4606
Kojto 90:cb3d968589d8 4607 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field. */
Kojto 90:cb3d968589d8 4608 #define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.LINKCH)
Kojto 90:cb3d968589d8 4609
Kojto 90:cb3d968589d8 4610 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_LINKCH. */
Kojto 90:cb3d968589d8 4611 #define BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_LINKCH) & BM_DMA_TCDn_CITER_ELINKYES_LINKCH)
Kojto 90:cb3d968589d8 4612
Kojto 90:cb3d968589d8 4613 /*! @brief Set the LINKCH field to a new value. */
Kojto 90:cb3d968589d8 4614 #define BW_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_LINKCH) | BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v)))
Kojto 90:cb3d968589d8 4615 /*@}*/
Kojto 90:cb3d968589d8 4616
Kojto 90:cb3d968589d8 4617 /*!
Kojto 90:cb3d968589d8 4618 * @name Register DMA_TCDn_CITER_ELINKYES, field ELINK[15] (RW)
Kojto 90:cb3d968589d8 4619 *
Kojto 90:cb3d968589d8 4620 * As the channel completes the minor loop, this flag enables linking to another
Kojto 90:cb3d968589d8 4621 * channel, defined by the LINKCH field. The link target channel initiates a
Kojto 90:cb3d968589d8 4622 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
Kojto 90:cb3d968589d8 4623 * bit of the specified channel. If channel linking is disabled, the CITER value
Kojto 90:cb3d968589d8 4624 * is extended to 15 bits in place of a link channel number. If the major loop is
Kojto 90:cb3d968589d8 4625 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
Kojto 90:cb3d968589d8 4626 * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
Kojto 90:cb3d968589d8 4627 * configuration error is reported.
Kojto 90:cb3d968589d8 4628 *
Kojto 90:cb3d968589d8 4629 * Values:
Kojto 90:cb3d968589d8 4630 * - 0 - The channel-to-channel linking is disabled
Kojto 90:cb3d968589d8 4631 * - 1 - The channel-to-channel linking is enabled
Kojto 90:cb3d968589d8 4632 */
Kojto 90:cb3d968589d8 4633 /*@{*/
Kojto 90:cb3d968589d8 4634 #define BP_DMA_TCDn_CITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_ELINK. */
Kojto 90:cb3d968589d8 4635 #define BM_DMA_TCDn_CITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_ELINK. */
Kojto 90:cb3d968589d8 4636 #define BS_DMA_TCDn_CITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_ELINK. */
Kojto 90:cb3d968589d8 4637
Kojto 90:cb3d968589d8 4638 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_ELINK field. */
Kojto 90:cb3d968589d8 4639 #define BR_DMA_TCDn_CITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK))
Kojto 90:cb3d968589d8 4640
Kojto 90:cb3d968589d8 4641 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_ELINK. */
Kojto 90:cb3d968589d8 4642 #define BF_DMA_TCDn_CITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_ELINK) & BM_DMA_TCDn_CITER_ELINKYES_ELINK)
Kojto 90:cb3d968589d8 4643
Kojto 90:cb3d968589d8 4644 /*! @brief Set the ELINK field to a new value. */
Kojto 90:cb3d968589d8 4645 #define BW_DMA_TCDn_CITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK) = (v))
Kojto 90:cb3d968589d8 4646 /*@}*/
Kojto 90:cb3d968589d8 4647 /*******************************************************************************
Kojto 90:cb3d968589d8 4648 * HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
Kojto 90:cb3d968589d8 4649 ******************************************************************************/
Kojto 90:cb3d968589d8 4650
Kojto 90:cb3d968589d8 4651 /*!
Kojto 90:cb3d968589d8 4652 * @brief HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
Kojto 90:cb3d968589d8 4653 *
Kojto 90:cb3d968589d8 4654 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 4655 */
Kojto 90:cb3d968589d8 4656 typedef union _hw_dma_tcdn_dlastsga
Kojto 90:cb3d968589d8 4657 {
Kojto 90:cb3d968589d8 4658 uint32_t U;
Kojto 90:cb3d968589d8 4659 struct _hw_dma_tcdn_dlastsga_bitfields
Kojto 90:cb3d968589d8 4660 {
Kojto 90:cb3d968589d8 4661 uint32_t DLASTSGA : 32; /*!< [31:0] */
Kojto 90:cb3d968589d8 4662 } B;
Kojto 90:cb3d968589d8 4663 } hw_dma_tcdn_dlastsga_t;
Kojto 90:cb3d968589d8 4664
Kojto 90:cb3d968589d8 4665 /*!
Kojto 90:cb3d968589d8 4666 * @name Constants and macros for entire DMA_TCDn_DLASTSGA register
Kojto 90:cb3d968589d8 4667 */
Kojto 90:cb3d968589d8 4668 /*@{*/
Kojto 90:cb3d968589d8 4669 #define HW_DMA_TCDn_DLASTSGA_COUNT (16U)
Kojto 90:cb3d968589d8 4670
Kojto 90:cb3d968589d8 4671 #define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) ((x) + 0x1018U + (0x20U * (n)))
Kojto 90:cb3d968589d8 4672
Kojto 90:cb3d968589d8 4673 #define HW_DMA_TCDn_DLASTSGA(x, n) (*(__IO hw_dma_tcdn_dlastsga_t *) HW_DMA_TCDn_DLASTSGA_ADDR(x, n))
Kojto 90:cb3d968589d8 4674 #define HW_DMA_TCDn_DLASTSGA_RD(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
Kojto 90:cb3d968589d8 4675 #define HW_DMA_TCDn_DLASTSGA_WR(x, n, v) (HW_DMA_TCDn_DLASTSGA(x, n).U = (v))
Kojto 90:cb3d968589d8 4676 #define HW_DMA_TCDn_DLASTSGA_SET(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 4677 #define HW_DMA_TCDn_DLASTSGA_CLR(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 4678 #define HW_DMA_TCDn_DLASTSGA_TOG(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 4679 /*@}*/
Kojto 90:cb3d968589d8 4680
Kojto 90:cb3d968589d8 4681 /*
Kojto 90:cb3d968589d8 4682 * Constants & macros for individual DMA_TCDn_DLASTSGA bitfields
Kojto 90:cb3d968589d8 4683 */
Kojto 90:cb3d968589d8 4684
Kojto 90:cb3d968589d8 4685 /*!
Kojto 90:cb3d968589d8 4686 * @name Register DMA_TCDn_DLASTSGA, field DLASTSGA[31:0] (RW)
Kojto 90:cb3d968589d8 4687 *
Kojto 90:cb3d968589d8 4688 * Destination last address adjustment or the memory address for the next
Kojto 90:cb3d968589d8 4689 * transfer control descriptor to be loaded into this channel (scatter/gather). If
Kojto 90:cb3d968589d8 4690 * (TCDn_CSR[ESG] = 0), then: Adjustment value added to the destination address at
Kojto 90:cb3d968589d8 4691 * the completion of the major iteration count. This value can apply to restore the
Kojto 90:cb3d968589d8 4692 * destination address to the initial value or adjust the address to reference
Kojto 90:cb3d968589d8 4693 * the next data structure. This field uses two's complement notation for the
Kojto 90:cb3d968589d8 4694 * final destination address adjustment. Otherwise: This address points to the
Kojto 90:cb3d968589d8 4695 * beginning of a 0-modulo-32-byte region containing the next transfer control
Kojto 90:cb3d968589d8 4696 * descriptor to be loaded into this channel. This channel reload is performed as the
Kojto 90:cb3d968589d8 4697 * major iteration count completes. The scatter/gather address must be
Kojto 90:cb3d968589d8 4698 * 0-modulo-32-byte, else a configuration error is reported.
Kojto 90:cb3d968589d8 4699 */
Kojto 90:cb3d968589d8 4700 /*@{*/
Kojto 90:cb3d968589d8 4701 #define BP_DMA_TCDn_DLASTSGA_DLASTSGA (0U) /*!< Bit position for DMA_TCDn_DLASTSGA_DLASTSGA. */
Kojto 90:cb3d968589d8 4702 #define BM_DMA_TCDn_DLASTSGA_DLASTSGA (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DLASTSGA_DLASTSGA. */
Kojto 90:cb3d968589d8 4703 #define BS_DMA_TCDn_DLASTSGA_DLASTSGA (32U) /*!< Bit field size in bits for DMA_TCDn_DLASTSGA_DLASTSGA. */
Kojto 90:cb3d968589d8 4704
Kojto 90:cb3d968589d8 4705 /*! @brief Read current value of the DMA_TCDn_DLASTSGA_DLASTSGA field. */
Kojto 90:cb3d968589d8 4706 #define BR_DMA_TCDn_DLASTSGA_DLASTSGA(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
Kojto 90:cb3d968589d8 4707
Kojto 90:cb3d968589d8 4708 /*! @brief Format value for bitfield DMA_TCDn_DLASTSGA_DLASTSGA. */
Kojto 90:cb3d968589d8 4709 #define BF_DMA_TCDn_DLASTSGA_DLASTSGA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DLASTSGA_DLASTSGA) & BM_DMA_TCDn_DLASTSGA_DLASTSGA)
Kojto 90:cb3d968589d8 4710
Kojto 90:cb3d968589d8 4711 /*! @brief Set the DLASTSGA field to a new value. */
Kojto 90:cb3d968589d8 4712 #define BW_DMA_TCDn_DLASTSGA_DLASTSGA(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, v))
Kojto 90:cb3d968589d8 4713 /*@}*/
Kojto 90:cb3d968589d8 4714 /*******************************************************************************
Kojto 90:cb3d968589d8 4715 * HW_DMA_TCDn_CSR - TCD Control and Status
Kojto 90:cb3d968589d8 4716 ******************************************************************************/
Kojto 90:cb3d968589d8 4717
Kojto 90:cb3d968589d8 4718 /*!
Kojto 90:cb3d968589d8 4719 * @brief HW_DMA_TCDn_CSR - TCD Control and Status (RW)
Kojto 90:cb3d968589d8 4720 *
Kojto 90:cb3d968589d8 4721 * Reset value: 0x0000U
Kojto 90:cb3d968589d8 4722 */
Kojto 90:cb3d968589d8 4723 typedef union _hw_dma_tcdn_csr
Kojto 90:cb3d968589d8 4724 {
Kojto 90:cb3d968589d8 4725 uint16_t U;
Kojto 90:cb3d968589d8 4726 struct _hw_dma_tcdn_csr_bitfields
Kojto 90:cb3d968589d8 4727 {
Kojto 90:cb3d968589d8 4728 uint16_t START : 1; /*!< [0] Channel Start */
Kojto 90:cb3d968589d8 4729 uint16_t INTMAJOR : 1; /*!< [1] Enable an interrupt when major
Kojto 90:cb3d968589d8 4730 * iteration count completes */
Kojto 90:cb3d968589d8 4731 uint16_t INTHALF : 1; /*!< [2] Enable an interrupt when major counter
Kojto 90:cb3d968589d8 4732 * is half complete. */
Kojto 90:cb3d968589d8 4733 uint16_t DREQ : 1; /*!< [3] Disable Request */
Kojto 90:cb3d968589d8 4734 uint16_t ESG : 1; /*!< [4] Enable Scatter/Gather Processing */
Kojto 90:cb3d968589d8 4735 uint16_t MAJORELINK : 1; /*!< [5] Enable channel-to-channel linking
Kojto 90:cb3d968589d8 4736 * on major loop complete */
Kojto 90:cb3d968589d8 4737 uint16_t ACTIVE : 1; /*!< [6] Channel Active */
Kojto 90:cb3d968589d8 4738 uint16_t DONE : 1; /*!< [7] Channel Done */
Kojto 90:cb3d968589d8 4739 uint16_t MAJORLINKCH : 4; /*!< [11:8] Link Channel Number */
Kojto 90:cb3d968589d8 4740 uint16_t RESERVED0 : 2; /*!< [13:12] */
Kojto 90:cb3d968589d8 4741 uint16_t BWC : 2; /*!< [15:14] Bandwidth Control */
Kojto 90:cb3d968589d8 4742 } B;
Kojto 90:cb3d968589d8 4743 } hw_dma_tcdn_csr_t;
Kojto 90:cb3d968589d8 4744
Kojto 90:cb3d968589d8 4745 /*!
Kojto 90:cb3d968589d8 4746 * @name Constants and macros for entire DMA_TCDn_CSR register
Kojto 90:cb3d968589d8 4747 */
Kojto 90:cb3d968589d8 4748 /*@{*/
Kojto 90:cb3d968589d8 4749 #define HW_DMA_TCDn_CSR_COUNT (16U)
Kojto 90:cb3d968589d8 4750
Kojto 90:cb3d968589d8 4751 #define HW_DMA_TCDn_CSR_ADDR(x, n) ((x) + 0x101CU + (0x20U * (n)))
Kojto 90:cb3d968589d8 4752
Kojto 90:cb3d968589d8 4753 #define HW_DMA_TCDn_CSR(x, n) (*(__IO hw_dma_tcdn_csr_t *) HW_DMA_TCDn_CSR_ADDR(x, n))
Kojto 90:cb3d968589d8 4754 #define HW_DMA_TCDn_CSR_RD(x, n) (HW_DMA_TCDn_CSR(x, n).U)
Kojto 90:cb3d968589d8 4755 #define HW_DMA_TCDn_CSR_WR(x, n, v) (HW_DMA_TCDn_CSR(x, n).U = (v))
Kojto 90:cb3d968589d8 4756 #define HW_DMA_TCDn_CSR_SET(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 4757 #define HW_DMA_TCDn_CSR_CLR(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 4758 #define HW_DMA_TCDn_CSR_TOG(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 4759 /*@}*/
Kojto 90:cb3d968589d8 4760
Kojto 90:cb3d968589d8 4761 /*
Kojto 90:cb3d968589d8 4762 * Constants & macros for individual DMA_TCDn_CSR bitfields
Kojto 90:cb3d968589d8 4763 */
Kojto 90:cb3d968589d8 4764
Kojto 90:cb3d968589d8 4765 /*!
Kojto 90:cb3d968589d8 4766 * @name Register DMA_TCDn_CSR, field START[0] (RW)
Kojto 90:cb3d968589d8 4767 *
Kojto 90:cb3d968589d8 4768 * If this flag is set, the channel is requesting service. The eDMA hardware
Kojto 90:cb3d968589d8 4769 * automatically clears this flag after the channel begins execution.
Kojto 90:cb3d968589d8 4770 *
Kojto 90:cb3d968589d8 4771 * Values:
Kojto 90:cb3d968589d8 4772 * - 0 - The channel is not explicitly started
Kojto 90:cb3d968589d8 4773 * - 1 - The channel is explicitly started via a software initiated service
Kojto 90:cb3d968589d8 4774 * request
Kojto 90:cb3d968589d8 4775 */
Kojto 90:cb3d968589d8 4776 /*@{*/
Kojto 90:cb3d968589d8 4777 #define BP_DMA_TCDn_CSR_START (0U) /*!< Bit position for DMA_TCDn_CSR_START. */
Kojto 90:cb3d968589d8 4778 #define BM_DMA_TCDn_CSR_START (0x0001U) /*!< Bit mask for DMA_TCDn_CSR_START. */
Kojto 90:cb3d968589d8 4779 #define BS_DMA_TCDn_CSR_START (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_START. */
Kojto 90:cb3d968589d8 4780
Kojto 90:cb3d968589d8 4781 /*! @brief Read current value of the DMA_TCDn_CSR_START field. */
Kojto 90:cb3d968589d8 4782 #define BR_DMA_TCDn_CSR_START(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START))
Kojto 90:cb3d968589d8 4783
Kojto 90:cb3d968589d8 4784 /*! @brief Format value for bitfield DMA_TCDn_CSR_START. */
Kojto 90:cb3d968589d8 4785 #define BF_DMA_TCDn_CSR_START(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_START) & BM_DMA_TCDn_CSR_START)
Kojto 90:cb3d968589d8 4786
Kojto 90:cb3d968589d8 4787 /*! @brief Set the START field to a new value. */
Kojto 90:cb3d968589d8 4788 #define BW_DMA_TCDn_CSR_START(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START) = (v))
Kojto 90:cb3d968589d8 4789 /*@}*/
Kojto 90:cb3d968589d8 4790
Kojto 90:cb3d968589d8 4791 /*!
Kojto 90:cb3d968589d8 4792 * @name Register DMA_TCDn_CSR, field INTMAJOR[1] (RW)
Kojto 90:cb3d968589d8 4793 *
Kojto 90:cb3d968589d8 4794 * If this flag is set, the channel generates an interrupt request by setting
Kojto 90:cb3d968589d8 4795 * the appropriate bit in the INT when the current major iteration count reaches
Kojto 90:cb3d968589d8 4796 * zero.
Kojto 90:cb3d968589d8 4797 *
Kojto 90:cb3d968589d8 4798 * Values:
Kojto 90:cb3d968589d8 4799 * - 0 - The end-of-major loop interrupt is disabled
Kojto 90:cb3d968589d8 4800 * - 1 - The end-of-major loop interrupt is enabled
Kojto 90:cb3d968589d8 4801 */
Kojto 90:cb3d968589d8 4802 /*@{*/
Kojto 90:cb3d968589d8 4803 #define BP_DMA_TCDn_CSR_INTMAJOR (1U) /*!< Bit position for DMA_TCDn_CSR_INTMAJOR. */
Kojto 90:cb3d968589d8 4804 #define BM_DMA_TCDn_CSR_INTMAJOR (0x0002U) /*!< Bit mask for DMA_TCDn_CSR_INTMAJOR. */
Kojto 90:cb3d968589d8 4805 #define BS_DMA_TCDn_CSR_INTMAJOR (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_INTMAJOR. */
Kojto 90:cb3d968589d8 4806
Kojto 90:cb3d968589d8 4807 /*! @brief Read current value of the DMA_TCDn_CSR_INTMAJOR field. */
Kojto 90:cb3d968589d8 4808 #define BR_DMA_TCDn_CSR_INTMAJOR(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR))
Kojto 90:cb3d968589d8 4809
Kojto 90:cb3d968589d8 4810 /*! @brief Format value for bitfield DMA_TCDn_CSR_INTMAJOR. */
Kojto 90:cb3d968589d8 4811 #define BF_DMA_TCDn_CSR_INTMAJOR(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTMAJOR) & BM_DMA_TCDn_CSR_INTMAJOR)
Kojto 90:cb3d968589d8 4812
Kojto 90:cb3d968589d8 4813 /*! @brief Set the INTMAJOR field to a new value. */
Kojto 90:cb3d968589d8 4814 #define BW_DMA_TCDn_CSR_INTMAJOR(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR) = (v))
Kojto 90:cb3d968589d8 4815 /*@}*/
Kojto 90:cb3d968589d8 4816
Kojto 90:cb3d968589d8 4817 /*!
Kojto 90:cb3d968589d8 4818 * @name Register DMA_TCDn_CSR, field INTHALF[2] (RW)
Kojto 90:cb3d968589d8 4819 *
Kojto 90:cb3d968589d8 4820 * If this flag is set, the channel generates an interrupt request by setting
Kojto 90:cb3d968589d8 4821 * the appropriate bit in the INT register when the current major iteration count
Kojto 90:cb3d968589d8 4822 * reaches the halfway point. Specifically, the comparison performed by the eDMA
Kojto 90:cb3d968589d8 4823 * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
Kojto 90:cb3d968589d8 4824 * provided to support double-buffered (aka ping-pong) schemes or other types of data
Kojto 90:cb3d968589d8 4825 * movement where the processor needs an early indication of the transfer's
Kojto 90:cb3d968589d8 4826 * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
Kojto 90:cb3d968589d8 4827 *
Kojto 90:cb3d968589d8 4828 * Values:
Kojto 90:cb3d968589d8 4829 * - 0 - The half-point interrupt is disabled
Kojto 90:cb3d968589d8 4830 * - 1 - The half-point interrupt is enabled
Kojto 90:cb3d968589d8 4831 */
Kojto 90:cb3d968589d8 4832 /*@{*/
Kojto 90:cb3d968589d8 4833 #define BP_DMA_TCDn_CSR_INTHALF (2U) /*!< Bit position for DMA_TCDn_CSR_INTHALF. */
Kojto 90:cb3d968589d8 4834 #define BM_DMA_TCDn_CSR_INTHALF (0x0004U) /*!< Bit mask for DMA_TCDn_CSR_INTHALF. */
Kojto 90:cb3d968589d8 4835 #define BS_DMA_TCDn_CSR_INTHALF (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_INTHALF. */
Kojto 90:cb3d968589d8 4836
Kojto 90:cb3d968589d8 4837 /*! @brief Read current value of the DMA_TCDn_CSR_INTHALF field. */
Kojto 90:cb3d968589d8 4838 #define BR_DMA_TCDn_CSR_INTHALF(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF))
Kojto 90:cb3d968589d8 4839
Kojto 90:cb3d968589d8 4840 /*! @brief Format value for bitfield DMA_TCDn_CSR_INTHALF. */
Kojto 90:cb3d968589d8 4841 #define BF_DMA_TCDn_CSR_INTHALF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTHALF) & BM_DMA_TCDn_CSR_INTHALF)
Kojto 90:cb3d968589d8 4842
Kojto 90:cb3d968589d8 4843 /*! @brief Set the INTHALF field to a new value. */
Kojto 90:cb3d968589d8 4844 #define BW_DMA_TCDn_CSR_INTHALF(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF) = (v))
Kojto 90:cb3d968589d8 4845 /*@}*/
Kojto 90:cb3d968589d8 4846
Kojto 90:cb3d968589d8 4847 /*!
Kojto 90:cb3d968589d8 4848 * @name Register DMA_TCDn_CSR, field DREQ[3] (RW)
Kojto 90:cb3d968589d8 4849 *
Kojto 90:cb3d968589d8 4850 * If this flag is set, the eDMA hardware automatically clears the corresponding
Kojto 90:cb3d968589d8 4851 * ERQ bit when the current major iteration count reaches zero.
Kojto 90:cb3d968589d8 4852 *
Kojto 90:cb3d968589d8 4853 * Values:
Kojto 90:cb3d968589d8 4854 * - 0 - The channel's ERQ bit is not affected
Kojto 90:cb3d968589d8 4855 * - 1 - The channel's ERQ bit is cleared when the major loop is complete
Kojto 90:cb3d968589d8 4856 */
Kojto 90:cb3d968589d8 4857 /*@{*/
Kojto 90:cb3d968589d8 4858 #define BP_DMA_TCDn_CSR_DREQ (3U) /*!< Bit position for DMA_TCDn_CSR_DREQ. */
Kojto 90:cb3d968589d8 4859 #define BM_DMA_TCDn_CSR_DREQ (0x0008U) /*!< Bit mask for DMA_TCDn_CSR_DREQ. */
Kojto 90:cb3d968589d8 4860 #define BS_DMA_TCDn_CSR_DREQ (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_DREQ. */
Kojto 90:cb3d968589d8 4861
Kojto 90:cb3d968589d8 4862 /*! @brief Read current value of the DMA_TCDn_CSR_DREQ field. */
Kojto 90:cb3d968589d8 4863 #define BR_DMA_TCDn_CSR_DREQ(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ))
Kojto 90:cb3d968589d8 4864
Kojto 90:cb3d968589d8 4865 /*! @brief Format value for bitfield DMA_TCDn_CSR_DREQ. */
Kojto 90:cb3d968589d8 4866 #define BF_DMA_TCDn_CSR_DREQ(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DREQ) & BM_DMA_TCDn_CSR_DREQ)
Kojto 90:cb3d968589d8 4867
Kojto 90:cb3d968589d8 4868 /*! @brief Set the DREQ field to a new value. */
Kojto 90:cb3d968589d8 4869 #define BW_DMA_TCDn_CSR_DREQ(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ) = (v))
Kojto 90:cb3d968589d8 4870 /*@}*/
Kojto 90:cb3d968589d8 4871
Kojto 90:cb3d968589d8 4872 /*!
Kojto 90:cb3d968589d8 4873 * @name Register DMA_TCDn_CSR, field ESG[4] (RW)
Kojto 90:cb3d968589d8 4874 *
Kojto 90:cb3d968589d8 4875 * As the channel completes the major loop, this flag enables scatter/gather
Kojto 90:cb3d968589d8 4876 * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
Kojto 90:cb3d968589d8 4877 * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
Kojto 90:cb3d968589d8 4878 * loaded as the transfer control descriptor into the local memory. To support the
Kojto 90:cb3d968589d8 4879 * dynamic scatter/gather coherency model, this field is forced to zero when
Kojto 90:cb3d968589d8 4880 * written to while the TCDn_CSR[DONE] bit is set.
Kojto 90:cb3d968589d8 4881 *
Kojto 90:cb3d968589d8 4882 * Values:
Kojto 90:cb3d968589d8 4883 * - 0 - The current channel's TCD is normal format.
Kojto 90:cb3d968589d8 4884 * - 1 - The current channel's TCD specifies a scatter gather format. The
Kojto 90:cb3d968589d8 4885 * DLASTSGA field provides a memory pointer to the next TCD to be loaded into this
Kojto 90:cb3d968589d8 4886 * channel after the major loop completes its execution.
Kojto 90:cb3d968589d8 4887 */
Kojto 90:cb3d968589d8 4888 /*@{*/
Kojto 90:cb3d968589d8 4889 #define BP_DMA_TCDn_CSR_ESG (4U) /*!< Bit position for DMA_TCDn_CSR_ESG. */
Kojto 90:cb3d968589d8 4890 #define BM_DMA_TCDn_CSR_ESG (0x0010U) /*!< Bit mask for DMA_TCDn_CSR_ESG. */
Kojto 90:cb3d968589d8 4891 #define BS_DMA_TCDn_CSR_ESG (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_ESG. */
Kojto 90:cb3d968589d8 4892
Kojto 90:cb3d968589d8 4893 /*! @brief Read current value of the DMA_TCDn_CSR_ESG field. */
Kojto 90:cb3d968589d8 4894 #define BR_DMA_TCDn_CSR_ESG(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG))
Kojto 90:cb3d968589d8 4895
Kojto 90:cb3d968589d8 4896 /*! @brief Format value for bitfield DMA_TCDn_CSR_ESG. */
Kojto 90:cb3d968589d8 4897 #define BF_DMA_TCDn_CSR_ESG(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ESG) & BM_DMA_TCDn_CSR_ESG)
Kojto 90:cb3d968589d8 4898
Kojto 90:cb3d968589d8 4899 /*! @brief Set the ESG field to a new value. */
Kojto 90:cb3d968589d8 4900 #define BW_DMA_TCDn_CSR_ESG(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG) = (v))
Kojto 90:cb3d968589d8 4901 /*@}*/
Kojto 90:cb3d968589d8 4902
Kojto 90:cb3d968589d8 4903 /*!
Kojto 90:cb3d968589d8 4904 * @name Register DMA_TCDn_CSR, field MAJORELINK[5] (RW)
Kojto 90:cb3d968589d8 4905 *
Kojto 90:cb3d968589d8 4906 * As the channel completes the major loop, this flag enables the linking to
Kojto 90:cb3d968589d8 4907 * another channel, defined by MAJORLINKCH. The link target channel initiates a
Kojto 90:cb3d968589d8 4908 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
Kojto 90:cb3d968589d8 4909 * bit of the specified channel. To support the dynamic linking coherency model,
Kojto 90:cb3d968589d8 4910 * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
Kojto 90:cb3d968589d8 4911 *
Kojto 90:cb3d968589d8 4912 * Values:
Kojto 90:cb3d968589d8 4913 * - 0 - The channel-to-channel linking is disabled
Kojto 90:cb3d968589d8 4914 * - 1 - The channel-to-channel linking is enabled
Kojto 90:cb3d968589d8 4915 */
Kojto 90:cb3d968589d8 4916 /*@{*/
Kojto 90:cb3d968589d8 4917 #define BP_DMA_TCDn_CSR_MAJORELINK (5U) /*!< Bit position for DMA_TCDn_CSR_MAJORELINK. */
Kojto 90:cb3d968589d8 4918 #define BM_DMA_TCDn_CSR_MAJORELINK (0x0020U) /*!< Bit mask for DMA_TCDn_CSR_MAJORELINK. */
Kojto 90:cb3d968589d8 4919 #define BS_DMA_TCDn_CSR_MAJORELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORELINK. */
Kojto 90:cb3d968589d8 4920
Kojto 90:cb3d968589d8 4921 /*! @brief Read current value of the DMA_TCDn_CSR_MAJORELINK field. */
Kojto 90:cb3d968589d8 4922 #define BR_DMA_TCDn_CSR_MAJORELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK))
Kojto 90:cb3d968589d8 4923
Kojto 90:cb3d968589d8 4924 /*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORELINK. */
Kojto 90:cb3d968589d8 4925 #define BF_DMA_TCDn_CSR_MAJORELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORELINK) & BM_DMA_TCDn_CSR_MAJORELINK)
Kojto 90:cb3d968589d8 4926
Kojto 90:cb3d968589d8 4927 /*! @brief Set the MAJORELINK field to a new value. */
Kojto 90:cb3d968589d8 4928 #define BW_DMA_TCDn_CSR_MAJORELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK) = (v))
Kojto 90:cb3d968589d8 4929 /*@}*/
Kojto 90:cb3d968589d8 4930
Kojto 90:cb3d968589d8 4931 /*!
Kojto 90:cb3d968589d8 4932 * @name Register DMA_TCDn_CSR, field ACTIVE[6] (RW)
Kojto 90:cb3d968589d8 4933 *
Kojto 90:cb3d968589d8 4934 * This flag signals the channel is currently in execution. It is set when
Kojto 90:cb3d968589d8 4935 * channel service begins, and the eDMA clears it as the minor loop completes or if
Kojto 90:cb3d968589d8 4936 * any error condition is detected. This bit resets to zero.
Kojto 90:cb3d968589d8 4937 */
Kojto 90:cb3d968589d8 4938 /*@{*/
Kojto 90:cb3d968589d8 4939 #define BP_DMA_TCDn_CSR_ACTIVE (6U) /*!< Bit position for DMA_TCDn_CSR_ACTIVE. */
Kojto 90:cb3d968589d8 4940 #define BM_DMA_TCDn_CSR_ACTIVE (0x0040U) /*!< Bit mask for DMA_TCDn_CSR_ACTIVE. */
Kojto 90:cb3d968589d8 4941 #define BS_DMA_TCDn_CSR_ACTIVE (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_ACTIVE. */
Kojto 90:cb3d968589d8 4942
Kojto 90:cb3d968589d8 4943 /*! @brief Read current value of the DMA_TCDn_CSR_ACTIVE field. */
Kojto 90:cb3d968589d8 4944 #define BR_DMA_TCDn_CSR_ACTIVE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE))
Kojto 90:cb3d968589d8 4945
Kojto 90:cb3d968589d8 4946 /*! @brief Format value for bitfield DMA_TCDn_CSR_ACTIVE. */
Kojto 90:cb3d968589d8 4947 #define BF_DMA_TCDn_CSR_ACTIVE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ACTIVE) & BM_DMA_TCDn_CSR_ACTIVE)
Kojto 90:cb3d968589d8 4948
Kojto 90:cb3d968589d8 4949 /*! @brief Set the ACTIVE field to a new value. */
Kojto 90:cb3d968589d8 4950 #define BW_DMA_TCDn_CSR_ACTIVE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE) = (v))
Kojto 90:cb3d968589d8 4951 /*@}*/
Kojto 90:cb3d968589d8 4952
Kojto 90:cb3d968589d8 4953 /*!
Kojto 90:cb3d968589d8 4954 * @name Register DMA_TCDn_CSR, field DONE[7] (RW)
Kojto 90:cb3d968589d8 4955 *
Kojto 90:cb3d968589d8 4956 * This flag indicates the eDMA has completed the major loop. The eDMA engine
Kojto 90:cb3d968589d8 4957 * sets it as the CITER count reaches zero; The software clears it, or the hardware
Kojto 90:cb3d968589d8 4958 * when the channel is activated. This bit must be cleared to write the
Kojto 90:cb3d968589d8 4959 * MAJORELINK or ESG bits.
Kojto 90:cb3d968589d8 4960 */
Kojto 90:cb3d968589d8 4961 /*@{*/
Kojto 90:cb3d968589d8 4962 #define BP_DMA_TCDn_CSR_DONE (7U) /*!< Bit position for DMA_TCDn_CSR_DONE. */
Kojto 90:cb3d968589d8 4963 #define BM_DMA_TCDn_CSR_DONE (0x0080U) /*!< Bit mask for DMA_TCDn_CSR_DONE. */
Kojto 90:cb3d968589d8 4964 #define BS_DMA_TCDn_CSR_DONE (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_DONE. */
Kojto 90:cb3d968589d8 4965
Kojto 90:cb3d968589d8 4966 /*! @brief Read current value of the DMA_TCDn_CSR_DONE field. */
Kojto 90:cb3d968589d8 4967 #define BR_DMA_TCDn_CSR_DONE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE))
Kojto 90:cb3d968589d8 4968
Kojto 90:cb3d968589d8 4969 /*! @brief Format value for bitfield DMA_TCDn_CSR_DONE. */
Kojto 90:cb3d968589d8 4970 #define BF_DMA_TCDn_CSR_DONE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DONE) & BM_DMA_TCDn_CSR_DONE)
Kojto 90:cb3d968589d8 4971
Kojto 90:cb3d968589d8 4972 /*! @brief Set the DONE field to a new value. */
Kojto 90:cb3d968589d8 4973 #define BW_DMA_TCDn_CSR_DONE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE) = (v))
Kojto 90:cb3d968589d8 4974 /*@}*/
Kojto 90:cb3d968589d8 4975
Kojto 90:cb3d968589d8 4976 /*!
Kojto 90:cb3d968589d8 4977 * @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW)
Kojto 90:cb3d968589d8 4978 *
Kojto 90:cb3d968589d8 4979 * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
Kojto 90:cb3d968589d8 4980 * performed after the major loop counter is exhausted. else After the major loop
Kojto 90:cb3d968589d8 4981 * counter is exhausted, the eDMA engine initiates a channel service request at the
Kojto 90:cb3d968589d8 4982 * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
Kojto 90:cb3d968589d8 4983 */
Kojto 90:cb3d968589d8 4984 /*@{*/
Kojto 90:cb3d968589d8 4985 #define BP_DMA_TCDn_CSR_MAJORLINKCH (8U) /*!< Bit position for DMA_TCDn_CSR_MAJORLINKCH. */
Kojto 90:cb3d968589d8 4986 #define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) /*!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH. */
Kojto 90:cb3d968589d8 4987 #define BS_DMA_TCDn_CSR_MAJORLINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH. */
Kojto 90:cb3d968589d8 4988
Kojto 90:cb3d968589d8 4989 /*! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field. */
Kojto 90:cb3d968589d8 4990 #define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (HW_DMA_TCDn_CSR(x, n).B.MAJORLINKCH)
Kojto 90:cb3d968589d8 4991
Kojto 90:cb3d968589d8 4992 /*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORLINKCH. */
Kojto 90:cb3d968589d8 4993 #define BF_DMA_TCDn_CSR_MAJORLINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORLINKCH) & BM_DMA_TCDn_CSR_MAJORLINKCH)
Kojto 90:cb3d968589d8 4994
Kojto 90:cb3d968589d8 4995 /*! @brief Set the MAJORLINKCH field to a new value. */
Kojto 90:cb3d968589d8 4996 #define BW_DMA_TCDn_CSR_MAJORLINKCH(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_MAJORLINKCH) | BF_DMA_TCDn_CSR_MAJORLINKCH(v)))
Kojto 90:cb3d968589d8 4997 /*@}*/
Kojto 90:cb3d968589d8 4998
Kojto 90:cb3d968589d8 4999 /*!
Kojto 90:cb3d968589d8 5000 * @name Register DMA_TCDn_CSR, field BWC[15:14] (RW)
Kojto 90:cb3d968589d8 5001 *
Kojto 90:cb3d968589d8 5002 * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
Kojto 90:cb3d968589d8 5003 * the eDMA processes the minor loop, it continuously generates read/write
Kojto 90:cb3d968589d8 5004 * sequences until the minor count is exhausted. This field forces the eDMA to stall
Kojto 90:cb3d968589d8 5005 * after the completion of each read/write access to control the bus request
Kojto 90:cb3d968589d8 5006 * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
Kojto 90:cb3d968589d8 5007 * this field is ignored between the first and second transfers and after the
Kojto 90:cb3d968589d8 5008 * last write of each minor loop. This behavior is a side effect of reducing
Kojto 90:cb3d968589d8 5009 * start-up latency.
Kojto 90:cb3d968589d8 5010 *
Kojto 90:cb3d968589d8 5011 * Values:
Kojto 90:cb3d968589d8 5012 * - 00 - No eDMA engine stalls
Kojto 90:cb3d968589d8 5013 * - 01 - Reserved
Kojto 90:cb3d968589d8 5014 * - 10 - eDMA engine stalls for 4 cycles after each r/w
Kojto 90:cb3d968589d8 5015 * - 11 - eDMA engine stalls for 8 cycles after each r/w
Kojto 90:cb3d968589d8 5016 */
Kojto 90:cb3d968589d8 5017 /*@{*/
Kojto 90:cb3d968589d8 5018 #define BP_DMA_TCDn_CSR_BWC (14U) /*!< Bit position for DMA_TCDn_CSR_BWC. */
Kojto 90:cb3d968589d8 5019 #define BM_DMA_TCDn_CSR_BWC (0xC000U) /*!< Bit mask for DMA_TCDn_CSR_BWC. */
Kojto 90:cb3d968589d8 5020 #define BS_DMA_TCDn_CSR_BWC (2U) /*!< Bit field size in bits for DMA_TCDn_CSR_BWC. */
Kojto 90:cb3d968589d8 5021
Kojto 90:cb3d968589d8 5022 /*! @brief Read current value of the DMA_TCDn_CSR_BWC field. */
Kojto 90:cb3d968589d8 5023 #define BR_DMA_TCDn_CSR_BWC(x, n) (HW_DMA_TCDn_CSR(x, n).B.BWC)
Kojto 90:cb3d968589d8 5024
Kojto 90:cb3d968589d8 5025 /*! @brief Format value for bitfield DMA_TCDn_CSR_BWC. */
Kojto 90:cb3d968589d8 5026 #define BF_DMA_TCDn_CSR_BWC(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_BWC) & BM_DMA_TCDn_CSR_BWC)
Kojto 90:cb3d968589d8 5027
Kojto 90:cb3d968589d8 5028 /*! @brief Set the BWC field to a new value. */
Kojto 90:cb3d968589d8 5029 #define BW_DMA_TCDn_CSR_BWC(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_BWC) | BF_DMA_TCDn_CSR_BWC(v)))
Kojto 90:cb3d968589d8 5030 /*@}*/
Kojto 90:cb3d968589d8 5031 /*******************************************************************************
Kojto 90:cb3d968589d8 5032 * HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
Kojto 90:cb3d968589d8 5033 ******************************************************************************/
Kojto 90:cb3d968589d8 5034
Kojto 90:cb3d968589d8 5035 /*!
Kojto 90:cb3d968589d8 5036 * @brief HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
Kojto 90:cb3d968589d8 5037 *
Kojto 90:cb3d968589d8 5038 * Reset value: 0x0000U
Kojto 90:cb3d968589d8 5039 *
Kojto 90:cb3d968589d8 5040 * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
Kojto 90:cb3d968589d8 5041 * as follows.
Kojto 90:cb3d968589d8 5042 */
Kojto 90:cb3d968589d8 5043 typedef union _hw_dma_tcdn_biter_elinkno
Kojto 90:cb3d968589d8 5044 {
Kojto 90:cb3d968589d8 5045 uint16_t U;
Kojto 90:cb3d968589d8 5046 struct _hw_dma_tcdn_biter_elinkno_bitfields
Kojto 90:cb3d968589d8 5047 {
Kojto 90:cb3d968589d8 5048 uint16_t BITER : 15; /*!< [14:0] Starting Major Iteration Count */
Kojto 90:cb3d968589d8 5049 uint16_t ELINK : 1; /*!< [15] Enables channel-to-channel linking on
Kojto 90:cb3d968589d8 5050 * minor loop complete */
Kojto 90:cb3d968589d8 5051 } B;
Kojto 90:cb3d968589d8 5052 } hw_dma_tcdn_biter_elinkno_t;
Kojto 90:cb3d968589d8 5053
Kojto 90:cb3d968589d8 5054 /*!
Kojto 90:cb3d968589d8 5055 * @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register
Kojto 90:cb3d968589d8 5056 */
Kojto 90:cb3d968589d8 5057 /*@{*/
Kojto 90:cb3d968589d8 5058 #define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U)
Kojto 90:cb3d968589d8 5059
Kojto 90:cb3d968589d8 5060 #define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n)))
Kojto 90:cb3d968589d8 5061
Kojto 90:cb3d968589d8 5062 #define HW_DMA_TCDn_BITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_biter_elinkno_t *) HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n))
Kojto 90:cb3d968589d8 5063 #define HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U)
Kojto 90:cb3d968589d8 5064 #define HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U = (v))
Kojto 90:cb3d968589d8 5065 #define HW_DMA_TCDn_BITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 5066 #define HW_DMA_TCDn_BITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 5067 #define HW_DMA_TCDn_BITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 5068 /*@}*/
Kojto 90:cb3d968589d8 5069
Kojto 90:cb3d968589d8 5070 /*
Kojto 90:cb3d968589d8 5071 * Constants & macros for individual DMA_TCDn_BITER_ELINKNO bitfields
Kojto 90:cb3d968589d8 5072 */
Kojto 90:cb3d968589d8 5073
Kojto 90:cb3d968589d8 5074 /*!
Kojto 90:cb3d968589d8 5075 * @name Register DMA_TCDn_BITER_ELINKNO, field BITER[14:0] (RW)
Kojto 90:cb3d968589d8 5076 *
Kojto 90:cb3d968589d8 5077 * As the transfer control descriptor is first loaded by software, this 9-bit
Kojto 90:cb3d968589d8 5078 * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
Kojto 90:cb3d968589d8 5079 * field. As the major iteration count is exhausted, the contents of this field
Kojto 90:cb3d968589d8 5080 * are reloaded into the CITER field. When the software loads the TCD, this field
Kojto 90:cb3d968589d8 5081 * must be set equal to the corresponding CITER field; otherwise, a configuration
Kojto 90:cb3d968589d8 5082 * error is reported. As the major iteration count is exhausted, the contents of
Kojto 90:cb3d968589d8 5083 * this field is reloaded into the CITER field. If the channel is configured to
Kojto 90:cb3d968589d8 5084 * execute a single service request, the initial values of BITER and CITER should
Kojto 90:cb3d968589d8 5085 * be 0x0001.
Kojto 90:cb3d968589d8 5086 */
Kojto 90:cb3d968589d8 5087 /*@{*/
Kojto 90:cb3d968589d8 5088 #define BP_DMA_TCDn_BITER_ELINKNO_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_BITER. */
Kojto 90:cb3d968589d8 5089 #define BM_DMA_TCDn_BITER_ELINKNO_BITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_BITER. */
Kojto 90:cb3d968589d8 5090 #define BS_DMA_TCDn_BITER_ELINKNO_BITER (15U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_BITER. */
Kojto 90:cb3d968589d8 5091
Kojto 90:cb3d968589d8 5092 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_BITER field. */
Kojto 90:cb3d968589d8 5093 #define BR_DMA_TCDn_BITER_ELINKNO_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).B.BITER)
Kojto 90:cb3d968589d8 5094
Kojto 90:cb3d968589d8 5095 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_BITER. */
Kojto 90:cb3d968589d8 5096 #define BF_DMA_TCDn_BITER_ELINKNO_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_BITER) & BM_DMA_TCDn_BITER_ELINKNO_BITER)
Kojto 90:cb3d968589d8 5097
Kojto 90:cb3d968589d8 5098 /*! @brief Set the BITER field to a new value. */
Kojto 90:cb3d968589d8 5099 #define BW_DMA_TCDn_BITER_ELINKNO_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKNO_BITER) | BF_DMA_TCDn_BITER_ELINKNO_BITER(v)))
Kojto 90:cb3d968589d8 5100 /*@}*/
Kojto 90:cb3d968589d8 5101
Kojto 90:cb3d968589d8 5102 /*!
Kojto 90:cb3d968589d8 5103 * @name Register DMA_TCDn_BITER_ELINKNO, field ELINK[15] (RW)
Kojto 90:cb3d968589d8 5104 *
Kojto 90:cb3d968589d8 5105 * As the channel completes the minor loop, this flag enables the linking to
Kojto 90:cb3d968589d8 5106 * another channel, defined by BITER[LINKCH]. The link target channel initiates a
Kojto 90:cb3d968589d8 5107 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
Kojto 90:cb3d968589d8 5108 * bit of the specified channel. If channel linking is disabled, the BITER value
Kojto 90:cb3d968589d8 5109 * extends to 15 bits in place of a link channel number. If the major loop is
Kojto 90:cb3d968589d8 5110 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
Kojto 90:cb3d968589d8 5111 * linking. When the software loads the TCD, this field must be set equal to the
Kojto 90:cb3d968589d8 5112 * corresponding CITER field; otherwise, a configuration error is reported. As the
Kojto 90:cb3d968589d8 5113 * major iteration count is exhausted, the contents of this field is reloaded
Kojto 90:cb3d968589d8 5114 * into the CITER field.
Kojto 90:cb3d968589d8 5115 *
Kojto 90:cb3d968589d8 5116 * Values:
Kojto 90:cb3d968589d8 5117 * - 0 - The channel-to-channel linking is disabled
Kojto 90:cb3d968589d8 5118 * - 1 - The channel-to-channel linking is enabled
Kojto 90:cb3d968589d8 5119 */
Kojto 90:cb3d968589d8 5120 /*@{*/
Kojto 90:cb3d968589d8 5121 #define BP_DMA_TCDn_BITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_ELINK. */
Kojto 90:cb3d968589d8 5122 #define BM_DMA_TCDn_BITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_ELINK. */
Kojto 90:cb3d968589d8 5123 #define BS_DMA_TCDn_BITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_ELINK. */
Kojto 90:cb3d968589d8 5124
Kojto 90:cb3d968589d8 5125 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_ELINK field. */
Kojto 90:cb3d968589d8 5126 #define BR_DMA_TCDn_BITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK))
Kojto 90:cb3d968589d8 5127
Kojto 90:cb3d968589d8 5128 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_ELINK. */
Kojto 90:cb3d968589d8 5129 #define BF_DMA_TCDn_BITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_ELINK) & BM_DMA_TCDn_BITER_ELINKNO_ELINK)
Kojto 90:cb3d968589d8 5130
Kojto 90:cb3d968589d8 5131 /*! @brief Set the ELINK field to a new value. */
Kojto 90:cb3d968589d8 5132 #define BW_DMA_TCDn_BITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK) = (v))
Kojto 90:cb3d968589d8 5133 /*@}*/
Kojto 90:cb3d968589d8 5134 /*******************************************************************************
Kojto 90:cb3d968589d8 5135 * HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
Kojto 90:cb3d968589d8 5136 ******************************************************************************/
Kojto 90:cb3d968589d8 5137
Kojto 90:cb3d968589d8 5138 /*!
Kojto 90:cb3d968589d8 5139 * @brief HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
Kojto 90:cb3d968589d8 5140 *
Kojto 90:cb3d968589d8 5141 * Reset value: 0x0000U
Kojto 90:cb3d968589d8 5142 *
Kojto 90:cb3d968589d8 5143 * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
Kojto 90:cb3d968589d8 5144 * follows.
Kojto 90:cb3d968589d8 5145 */
Kojto 90:cb3d968589d8 5146 typedef union _hw_dma_tcdn_biter_elinkyes
Kojto 90:cb3d968589d8 5147 {
Kojto 90:cb3d968589d8 5148 uint16_t U;
Kojto 90:cb3d968589d8 5149 struct _hw_dma_tcdn_biter_elinkyes_bitfields
Kojto 90:cb3d968589d8 5150 {
Kojto 90:cb3d968589d8 5151 uint16_t BITER : 9; /*!< [8:0] Starting Major Iteration Count */
Kojto 90:cb3d968589d8 5152 uint16_t LINKCH : 4; /*!< [12:9] Link Channel Number */
Kojto 90:cb3d968589d8 5153 uint16_t RESERVED0 : 2; /*!< [14:13] */
Kojto 90:cb3d968589d8 5154 uint16_t ELINK : 1; /*!< [15] Enables channel-to-channel linking on
Kojto 90:cb3d968589d8 5155 * minor loop complete */
Kojto 90:cb3d968589d8 5156 } B;
Kojto 90:cb3d968589d8 5157 } hw_dma_tcdn_biter_elinkyes_t;
Kojto 90:cb3d968589d8 5158
Kojto 90:cb3d968589d8 5159 /*!
Kojto 90:cb3d968589d8 5160 * @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register
Kojto 90:cb3d968589d8 5161 */
Kojto 90:cb3d968589d8 5162 /*@{*/
Kojto 90:cb3d968589d8 5163 #define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U)
Kojto 90:cb3d968589d8 5164
Kojto 90:cb3d968589d8 5165 #define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n)))
Kojto 90:cb3d968589d8 5166
Kojto 90:cb3d968589d8 5167 #define HW_DMA_TCDn_BITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_biter_elinkyes_t *) HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n))
Kojto 90:cb3d968589d8 5168 #define HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U)
Kojto 90:cb3d968589d8 5169 #define HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U = (v))
Kojto 90:cb3d968589d8 5170 #define HW_DMA_TCDn_BITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 5171 #define HW_DMA_TCDn_BITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 5172 #define HW_DMA_TCDn_BITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 5173 /*@}*/
Kojto 90:cb3d968589d8 5174
Kojto 90:cb3d968589d8 5175 /*
Kojto 90:cb3d968589d8 5176 * Constants & macros for individual DMA_TCDn_BITER_ELINKYES bitfields
Kojto 90:cb3d968589d8 5177 */
Kojto 90:cb3d968589d8 5178
Kojto 90:cb3d968589d8 5179 /*!
Kojto 90:cb3d968589d8 5180 * @name Register DMA_TCDn_BITER_ELINKYES, field BITER[8:0] (RW)
Kojto 90:cb3d968589d8 5181 *
Kojto 90:cb3d968589d8 5182 * As the transfer control descriptor is first loaded by software, this 9-bit
Kojto 90:cb3d968589d8 5183 * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
Kojto 90:cb3d968589d8 5184 * field. As the major iteration count is exhausted, the contents of this field
Kojto 90:cb3d968589d8 5185 * are reloaded into the CITER field. When the software loads the TCD, this field
Kojto 90:cb3d968589d8 5186 * must be set equal to the corresponding CITER field; otherwise, a configuration
Kojto 90:cb3d968589d8 5187 * error is reported. As the major iteration count is exhausted, the contents of
Kojto 90:cb3d968589d8 5188 * this field is reloaded into the CITER field. If the channel is configured to
Kojto 90:cb3d968589d8 5189 * execute a single service request, the initial values of BITER and CITER should
Kojto 90:cb3d968589d8 5190 * be 0x0001.
Kojto 90:cb3d968589d8 5191 */
Kojto 90:cb3d968589d8 5192 /*@{*/
Kojto 90:cb3d968589d8 5193 #define BP_DMA_TCDn_BITER_ELINKYES_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_BITER. */
Kojto 90:cb3d968589d8 5194 #define BM_DMA_TCDn_BITER_ELINKYES_BITER (0x01FFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_BITER. */
Kojto 90:cb3d968589d8 5195 #define BS_DMA_TCDn_BITER_ELINKYES_BITER (9U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_BITER. */
Kojto 90:cb3d968589d8 5196
Kojto 90:cb3d968589d8 5197 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_BITER field. */
Kojto 90:cb3d968589d8 5198 #define BR_DMA_TCDn_BITER_ELINKYES_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.BITER)
Kojto 90:cb3d968589d8 5199
Kojto 90:cb3d968589d8 5200 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_BITER. */
Kojto 90:cb3d968589d8 5201 #define BF_DMA_TCDn_BITER_ELINKYES_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_BITER) & BM_DMA_TCDn_BITER_ELINKYES_BITER)
Kojto 90:cb3d968589d8 5202
Kojto 90:cb3d968589d8 5203 /*! @brief Set the BITER field to a new value. */
Kojto 90:cb3d968589d8 5204 #define BW_DMA_TCDn_BITER_ELINKYES_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_BITER) | BF_DMA_TCDn_BITER_ELINKYES_BITER(v)))
Kojto 90:cb3d968589d8 5205 /*@}*/
Kojto 90:cb3d968589d8 5206
Kojto 90:cb3d968589d8 5207 /*!
Kojto 90:cb3d968589d8 5208 * @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW)
Kojto 90:cb3d968589d8 5209 *
Kojto 90:cb3d968589d8 5210 * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
Kojto 90:cb3d968589d8 5211 * loop is exhausted, the eDMA engine initiates a channel service request at the
Kojto 90:cb3d968589d8 5212 * channel defined by these four bits by setting that channel's TCDn_CSR[START]
Kojto 90:cb3d968589d8 5213 * bit. When the software loads the TCD, this field must be set equal to the
Kojto 90:cb3d968589d8 5214 * corresponding CITER field; otherwise, a configuration error is reported. As the major
Kojto 90:cb3d968589d8 5215 * iteration count is exhausted, the contents of this field is reloaded into the
Kojto 90:cb3d968589d8 5216 * CITER field.
Kojto 90:cb3d968589d8 5217 */
Kojto 90:cb3d968589d8 5218 /*@{*/
Kojto 90:cb3d968589d8 5219 #define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH. */
Kojto 90:cb3d968589d8 5220 #define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH. */
Kojto 90:cb3d968589d8 5221 #define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH. */
Kojto 90:cb3d968589d8 5222
Kojto 90:cb3d968589d8 5223 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field. */
Kojto 90:cb3d968589d8 5224 #define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.LINKCH)
Kojto 90:cb3d968589d8 5225
Kojto 90:cb3d968589d8 5226 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_LINKCH. */
Kojto 90:cb3d968589d8 5227 #define BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_LINKCH) & BM_DMA_TCDn_BITER_ELINKYES_LINKCH)
Kojto 90:cb3d968589d8 5228
Kojto 90:cb3d968589d8 5229 /*! @brief Set the LINKCH field to a new value. */
Kojto 90:cb3d968589d8 5230 #define BW_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_LINKCH) | BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v)))
Kojto 90:cb3d968589d8 5231 /*@}*/
Kojto 90:cb3d968589d8 5232
Kojto 90:cb3d968589d8 5233 /*!
Kojto 90:cb3d968589d8 5234 * @name Register DMA_TCDn_BITER_ELINKYES, field ELINK[15] (RW)
Kojto 90:cb3d968589d8 5235 *
Kojto 90:cb3d968589d8 5236 * As the channel completes the minor loop, this flag enables the linking to
Kojto 90:cb3d968589d8 5237 * another channel, defined by BITER[LINKCH]. The link target channel initiates a
Kojto 90:cb3d968589d8 5238 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
Kojto 90:cb3d968589d8 5239 * bit of the specified channel. If channel linking disables, the BITER value
Kojto 90:cb3d968589d8 5240 * extends to 15 bits in place of a link channel number. If the major loop is
Kojto 90:cb3d968589d8 5241 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
Kojto 90:cb3d968589d8 5242 * linking. When the software loads the TCD, this field must be set equal to the
Kojto 90:cb3d968589d8 5243 * corresponding CITER field; otherwise, a configuration error is reported. As the
Kojto 90:cb3d968589d8 5244 * major iteration count is exhausted, the contents of this field is reloaded into
Kojto 90:cb3d968589d8 5245 * the CITER field.
Kojto 90:cb3d968589d8 5246 *
Kojto 90:cb3d968589d8 5247 * Values:
Kojto 90:cb3d968589d8 5248 * - 0 - The channel-to-channel linking is disabled
Kojto 90:cb3d968589d8 5249 * - 1 - The channel-to-channel linking is enabled
Kojto 90:cb3d968589d8 5250 */
Kojto 90:cb3d968589d8 5251 /*@{*/
Kojto 90:cb3d968589d8 5252 #define BP_DMA_TCDn_BITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_ELINK. */
Kojto 90:cb3d968589d8 5253 #define BM_DMA_TCDn_BITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_ELINK. */
Kojto 90:cb3d968589d8 5254 #define BS_DMA_TCDn_BITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_ELINK. */
Kojto 90:cb3d968589d8 5255
Kojto 90:cb3d968589d8 5256 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_ELINK field. */
Kojto 90:cb3d968589d8 5257 #define BR_DMA_TCDn_BITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK))
Kojto 90:cb3d968589d8 5258
Kojto 90:cb3d968589d8 5259 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_ELINK. */
Kojto 90:cb3d968589d8 5260 #define BF_DMA_TCDn_BITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_ELINK) & BM_DMA_TCDn_BITER_ELINKYES_ELINK)
Kojto 90:cb3d968589d8 5261
Kojto 90:cb3d968589d8 5262 /*! @brief Set the ELINK field to a new value. */
Kojto 90:cb3d968589d8 5263 #define BW_DMA_TCDn_BITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK) = (v))
Kojto 90:cb3d968589d8 5264 /*@}*/
Kojto 90:cb3d968589d8 5265
Kojto 90:cb3d968589d8 5266 /*
Kojto 90:cb3d968589d8 5267 ** Start of section using anonymous unions
Kojto 90:cb3d968589d8 5268 */
Kojto 90:cb3d968589d8 5269
Kojto 90:cb3d968589d8 5270 #if defined(__ARMCC_VERSION)
Kojto 90:cb3d968589d8 5271 #pragma push
Kojto 90:cb3d968589d8 5272 #pragma anon_unions
Kojto 90:cb3d968589d8 5273 #elif defined(__CWCC__)
Kojto 90:cb3d968589d8 5274 #pragma push
Kojto 90:cb3d968589d8 5275 #pragma cpp_extensions on
Kojto 90:cb3d968589d8 5276 #elif defined(__GNUC__)
Kojto 90:cb3d968589d8 5277 /* anonymous unions are enabled by default */
Kojto 90:cb3d968589d8 5278 #elif defined(__IAR_SYSTEMS_ICC__)
Kojto 90:cb3d968589d8 5279 #pragma language=extended
Kojto 90:cb3d968589d8 5280 #else
Kojto 90:cb3d968589d8 5281 #error Not supported compiler type
Kojto 90:cb3d968589d8 5282 #endif
Kojto 90:cb3d968589d8 5283
Kojto 90:cb3d968589d8 5284 /*******************************************************************************
Kojto 90:cb3d968589d8 5285 * hw_dma_t - module struct
Kojto 90:cb3d968589d8 5286 ******************************************************************************/
Kojto 90:cb3d968589d8 5287 /*!
Kojto 90:cb3d968589d8 5288 * @brief All DMA module registers.
Kojto 90:cb3d968589d8 5289 */
Kojto 90:cb3d968589d8 5290 #pragma pack(1)
Kojto 90:cb3d968589d8 5291 typedef struct _hw_dma
Kojto 90:cb3d968589d8 5292 {
Kojto 90:cb3d968589d8 5293 __IO hw_dma_cr_t CR; /*!< [0x0] Control Register */
Kojto 90:cb3d968589d8 5294 __I hw_dma_es_t ES; /*!< [0x4] Error Status Register */
Kojto 90:cb3d968589d8 5295 uint8_t _reserved0[4];
Kojto 90:cb3d968589d8 5296 __IO hw_dma_erq_t ERQ; /*!< [0xC] Enable Request Register */
Kojto 90:cb3d968589d8 5297 uint8_t _reserved1[4];
Kojto 90:cb3d968589d8 5298 __IO hw_dma_eei_t EEI; /*!< [0x14] Enable Error Interrupt Register */
Kojto 90:cb3d968589d8 5299 __O hw_dma_ceei_t CEEI; /*!< [0x18] Clear Enable Error Interrupt Register */
Kojto 90:cb3d968589d8 5300 __O hw_dma_seei_t SEEI; /*!< [0x19] Set Enable Error Interrupt Register */
Kojto 90:cb3d968589d8 5301 __O hw_dma_cerq_t CERQ; /*!< [0x1A] Clear Enable Request Register */
Kojto 90:cb3d968589d8 5302 __O hw_dma_serq_t SERQ; /*!< [0x1B] Set Enable Request Register */
Kojto 90:cb3d968589d8 5303 __O hw_dma_cdne_t CDNE; /*!< [0x1C] Clear DONE Status Bit Register */
Kojto 90:cb3d968589d8 5304 __O hw_dma_ssrt_t SSRT; /*!< [0x1D] Set START Bit Register */
Kojto 90:cb3d968589d8 5305 __O hw_dma_cerr_t CERR; /*!< [0x1E] Clear Error Register */
Kojto 90:cb3d968589d8 5306 __O hw_dma_cint_t CINT; /*!< [0x1F] Clear Interrupt Request Register */
Kojto 90:cb3d968589d8 5307 uint8_t _reserved2[4];
Kojto 90:cb3d968589d8 5308 __IO hw_dma_int_t INT; /*!< [0x24] Interrupt Request Register */
Kojto 90:cb3d968589d8 5309 uint8_t _reserved3[4];
Kojto 90:cb3d968589d8 5310 __IO hw_dma_err_t ERR; /*!< [0x2C] Error Register */
Kojto 90:cb3d968589d8 5311 uint8_t _reserved4[4];
Kojto 90:cb3d968589d8 5312 __I hw_dma_hrs_t HRS; /*!< [0x34] Hardware Request Status Register */
Kojto 90:cb3d968589d8 5313 uint8_t _reserved5[200];
Kojto 90:cb3d968589d8 5314 __IO hw_dma_dchprin_t DCHPRIn[16]; /*!< [0x100] Channel n Priority Register */
Kojto 90:cb3d968589d8 5315 uint8_t _reserved6[3824];
Kojto 90:cb3d968589d8 5316 struct {
Kojto 90:cb3d968589d8 5317 __IO hw_dma_tcdn_saddr_t TCDn_SADDR; /*!< [0x1000] TCD Source Address */
Kojto 90:cb3d968589d8 5318 __IO hw_dma_tcdn_soff_t TCDn_SOFF; /*!< [0x1004] TCD Signed Source Address Offset */
Kojto 90:cb3d968589d8 5319 __IO hw_dma_tcdn_attr_t TCDn_ATTR; /*!< [0x1006] TCD Transfer Attributes */
Kojto 90:cb3d968589d8 5320 union {
Kojto 90:cb3d968589d8 5321 __IO hw_dma_tcdn_nbytes_mlno_t TCDn_NBYTES_MLNO; /*!< [0x1008] TCD Minor Byte Count (Minor Loop Disabled) */
Kojto 90:cb3d968589d8 5322 __IO hw_dma_tcdn_nbytes_mloffno_t TCDn_NBYTES_MLOFFNO; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
Kojto 90:cb3d968589d8 5323 __IO hw_dma_tcdn_nbytes_mloffyes_t TCDn_NBYTES_MLOFFYES; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
Kojto 90:cb3d968589d8 5324 };
Kojto 90:cb3d968589d8 5325 __IO hw_dma_tcdn_slast_t TCDn_SLAST; /*!< [0x100C] TCD Last Source Address Adjustment */
Kojto 90:cb3d968589d8 5326 __IO hw_dma_tcdn_daddr_t TCDn_DADDR; /*!< [0x1010] TCD Destination Address */
Kojto 90:cb3d968589d8 5327 __IO hw_dma_tcdn_doff_t TCDn_DOFF; /*!< [0x1014] TCD Signed Destination Address Offset */
Kojto 90:cb3d968589d8 5328 union {
Kojto 90:cb3d968589d8 5329 __IO hw_dma_tcdn_citer_elinkno_t TCDn_CITER_ELINKNO; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
Kojto 90:cb3d968589d8 5330 __IO hw_dma_tcdn_citer_elinkyes_t TCDn_CITER_ELINKYES; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
Kojto 90:cb3d968589d8 5331 };
Kojto 90:cb3d968589d8 5332 __IO hw_dma_tcdn_dlastsga_t TCDn_DLASTSGA; /*!< [0x1018] TCD Last Destination Address Adjustment/Scatter Gather Address */
Kojto 90:cb3d968589d8 5333 __IO hw_dma_tcdn_csr_t TCDn_CSR; /*!< [0x101C] TCD Control and Status */
Kojto 90:cb3d968589d8 5334 union {
Kojto 90:cb3d968589d8 5335 __IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
Kojto 90:cb3d968589d8 5336 __IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
Kojto 90:cb3d968589d8 5337 };
Kojto 90:cb3d968589d8 5338 } TCD[16];
Kojto 90:cb3d968589d8 5339 } hw_dma_t;
Kojto 90:cb3d968589d8 5340 #pragma pack()
Kojto 90:cb3d968589d8 5341
Kojto 90:cb3d968589d8 5342 /*! @brief Macro to access all DMA registers. */
Kojto 90:cb3d968589d8 5343 /*! @param x DMA module instance base address. */
Kojto 90:cb3d968589d8 5344 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 5345 * use the '&' operator, like <code>&HW_DMA(DMA_BASE)</code>. */
Kojto 90:cb3d968589d8 5346 #define HW_DMA(x) (*(hw_dma_t *)(x))
Kojto 90:cb3d968589d8 5347
Kojto 90:cb3d968589d8 5348 /*
Kojto 90:cb3d968589d8 5349 ** End of section using anonymous unions
Kojto 90:cb3d968589d8 5350 */
Kojto 90:cb3d968589d8 5351
Kojto 90:cb3d968589d8 5352 #if defined(__ARMCC_VERSION)
Kojto 90:cb3d968589d8 5353 #pragma pop
Kojto 90:cb3d968589d8 5354 #elif defined(__CWCC__)
Kojto 90:cb3d968589d8 5355 #pragma pop
Kojto 90:cb3d968589d8 5356 #elif defined(__GNUC__)
Kojto 90:cb3d968589d8 5357 /* leave anonymous unions enabled */
Kojto 90:cb3d968589d8 5358 #elif defined(__IAR_SYSTEMS_ICC__)
Kojto 90:cb3d968589d8 5359 #pragma language=default
Kojto 90:cb3d968589d8 5360 #else
Kojto 90:cb3d968589d8 5361 #error Not supported compiler type
Kojto 90:cb3d968589d8 5362 #endif
Kojto 90:cb3d968589d8 5363
Kojto 90:cb3d968589d8 5364 #endif /* __HW_DMA_REGISTERS_H__ */
Kojto 90:cb3d968589d8 5365 /* EOF */