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TARGET_NUCLEO_F334R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dac.h@168:b9e159c1930a, 2018-05-24 (annotated)

Committer:
AnnaBridge
Date:
Thu May 24 15:35:55 2018 +0100
Revision:
168:b9e159c1930a
Parent:
135:176b8275d35d 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 135:176b8275d35d 1 /**
<> 135:176b8275d35d 2 ******************************************************************************
<> 135:176b8275d35d 3 * @file stm32f3xx_ll_dac.h
<> 135:176b8275d35d 4 * @author MCD Application Team
<> 135:176b8275d35d 5 * @brief Header file of DAC LL module.
<> 135:176b8275d35d 6 ******************************************************************************
<> 135:176b8275d35d 7 * @attention
<> 135:176b8275d35d 8 *
<> 135:176b8275d35d 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 135:176b8275d35d 10 *
<> 135:176b8275d35d 11 * Redistribution and use in source and binary forms, with or without modification,
<> 135:176b8275d35d 12 * are permitted provided that the following conditions are met:
<> 135:176b8275d35d 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 135:176b8275d35d 14 * this list of conditions and the following disclaimer.
<> 135:176b8275d35d 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 135:176b8275d35d 16 * this list of conditions and the following disclaimer in the documentation
<> 135:176b8275d35d 17 * and/or other materials provided with the distribution.
<> 135:176b8275d35d 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 135:176b8275d35d 19 * may be used to endorse or promote products derived from this software
<> 135:176b8275d35d 20 * without specific prior written permission.
<> 135:176b8275d35d 21 *
<> 135:176b8275d35d 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 135:176b8275d35d 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 135:176b8275d35d 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 135:176b8275d35d 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 135:176b8275d35d 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 135:176b8275d35d 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 135:176b8275d35d 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 135:176b8275d35d 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 135:176b8275d35d 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 135:176b8275d35d 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 135:176b8275d35d 32 *
<> 135:176b8275d35d 33 ******************************************************************************
<> 135:176b8275d35d 34 */
<> 135:176b8275d35d 35
<> 135:176b8275d35d 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 135:176b8275d35d 37 #ifndef __STM32F3xx_LL_DAC_H
<> 135:176b8275d35d 38 #define __STM32F3xx_LL_DAC_H
<> 135:176b8275d35d 39
<> 135:176b8275d35d 40 #ifdef __cplusplus
<> 135:176b8275d35d 41 extern "C" {
<> 135:176b8275d35d 42 #endif
<> 135:176b8275d35d 43
<> 135:176b8275d35d 44 /* Includes ------------------------------------------------------------------*/
<> 135:176b8275d35d 45 #include "stm32f3xx.h"
<> 135:176b8275d35d 46
<> 135:176b8275d35d 47 /** @addtogroup STM32F3xx_LL_Driver
<> 135:176b8275d35d 48 * @{
<> 135:176b8275d35d 49 */
<> 135:176b8275d35d 50
<> 135:176b8275d35d 51 #if defined (DAC1) || defined (DAC2)
<> 135:176b8275d35d 52
<> 135:176b8275d35d 53 /** @defgroup DAC_LL DAC
<> 135:176b8275d35d 54 * @{
<> 135:176b8275d35d 55 */
<> 135:176b8275d35d 56
<> 135:176b8275d35d 57 /* Private types -------------------------------------------------------------*/
<> 135:176b8275d35d 58 /* Private variables ---------------------------------------------------------*/
<> 135:176b8275d35d 59
<> 135:176b8275d35d 60 /* Private constants ---------------------------------------------------------*/
<> 135:176b8275d35d 61 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
<> 135:176b8275d35d 62 * @{
<> 135:176b8275d35d 63 */
<> 135:176b8275d35d 64
<> 135:176b8275d35d 65 /* Internal masks for DAC channels definition */
<> 135:176b8275d35d 66 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
<> 135:176b8275d35d 67 /* - channel bits position into register CR */
<> 135:176b8275d35d 68 /* - channel bits position into register SWTRIG */
<> 135:176b8275d35d 69 /* - channel register offset of data holding register DHRx */
<> 135:176b8275d35d 70 /* - channel register offset of data output register DORx */
<> 135:176b8275d35d 71 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
<> 135:176b8275d35d 72 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
<> 135:176b8275d35d 73 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
<> 135:176b8275d35d 74
<> 135:176b8275d35d 75 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
<> 135:176b8275d35d 76 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 77 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
<> 135:176b8275d35d 78 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
<> 135:176b8275d35d 79 #else
<> 135:176b8275d35d 80 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
<> 135:176b8275d35d 81 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 82
<> 135:176b8275d35d 83 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
<> 135:176b8275d35d 84 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
<> 135:176b8275d35d 85 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
<> 135:176b8275d35d 86 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 87 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
<> 135:176b8275d35d 88 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
<> 135:176b8275d35d 89 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
<> 135:176b8275d35d 90 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 91 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
<> 135:176b8275d35d 92 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
<> 135:176b8275d35d 93 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
<> 135:176b8275d35d 94 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
<> 135:176b8275d35d 95
<> 135:176b8275d35d 96 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
<> 135:176b8275d35d 97 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 98 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
<> 135:176b8275d35d 99 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
<> 135:176b8275d35d 100 #else
<> 135:176b8275d35d 101 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
<> 135:176b8275d35d 102 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 103
<> 135:176b8275d35d 104 /* DAC registers bits positions */
<> 135:176b8275d35d 105 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 106 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
<> 135:176b8275d35d 107 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
<> 135:176b8275d35d 108 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
<> 135:176b8275d35d 109 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 110
<> 135:176b8275d35d 111 /* Miscellaneous data */
<> 135:176b8275d35d 112 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
<> 135:176b8275d35d 113
<> 135:176b8275d35d 114 /**
<> 135:176b8275d35d 115 * @}
<> 135:176b8275d35d 116 */
<> 135:176b8275d35d 117
<> 135:176b8275d35d 118
<> 135:176b8275d35d 119 /* Private macros ------------------------------------------------------------*/
<> 135:176b8275d35d 120 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
<> 135:176b8275d35d 121 * @{
<> 135:176b8275d35d 122 */
<> 135:176b8275d35d 123
<> 135:176b8275d35d 124 /**
<> 135:176b8275d35d 125 * @brief Driver macro reserved for internal use: isolate bits with the
<> 135:176b8275d35d 126 * selected mask and shift them to the register LSB
<> 135:176b8275d35d 127 * (shift mask on register position bit 0).
<> 135:176b8275d35d 128 * @param __BITS__ Bits in register 32 bits
<> 135:176b8275d35d 129 * @param __MASK__ Mask in register 32 bits
<> 135:176b8275d35d 130 * @retval Bits in register 32 bits
<> 135:176b8275d35d 131 */
<> 135:176b8275d35d 132 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
<> 135:176b8275d35d 133 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
<> 135:176b8275d35d 134
<> 135:176b8275d35d 135 /**
<> 135:176b8275d35d 136 * @brief Driver macro reserved for internal use: set a pointer to
<> 135:176b8275d35d 137 * a register from a register basis from which an offset
<> 135:176b8275d35d 138 * is applied.
<> 135:176b8275d35d 139 * @param __REG__ Register basis from which the offset is applied.
<> 135:176b8275d35d 140 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
<> 135:176b8275d35d 141 * @retval Pointer to register address
<> 135:176b8275d35d 142 */
<> 135:176b8275d35d 143 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
<> 135:176b8275d35d 144 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
<> 135:176b8275d35d 145
<> 135:176b8275d35d 146 /**
<> 135:176b8275d35d 147 * @}
<> 135:176b8275d35d 148 */
<> 135:176b8275d35d 149
<> 135:176b8275d35d 150
<> 135:176b8275d35d 151 /* Exported types ------------------------------------------------------------*/
<> 135:176b8275d35d 152 #if defined(USE_FULL_LL_DRIVER)
<> 135:176b8275d35d 153 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
<> 135:176b8275d35d 154 * @{
<> 135:176b8275d35d 155 */
<> 135:176b8275d35d 156
<> 135:176b8275d35d 157 /**
<> 135:176b8275d35d 158 * @brief Structure definition of some features of DAC instance.
<> 135:176b8275d35d 159 */
<> 135:176b8275d35d 160 typedef struct
<> 135:176b8275d35d 161 {
<> 135:176b8275d35d 162 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
<> 135:176b8275d35d 163 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
<> 135:176b8275d35d 164
<> 135:176b8275d35d 165 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
<> 135:176b8275d35d 166
<> 135:176b8275d35d 167 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
<> 135:176b8275d35d 168 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
<> 135:176b8275d35d 169
<> 135:176b8275d35d 170 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
<> 135:176b8275d35d 171
<> 135:176b8275d35d 172 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
<> 135:176b8275d35d 173 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
<> 135:176b8275d35d 174 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
<> 135:176b8275d35d 175 @note If waveform automatic generation mode is disabled, this parameter is discarded.
<> 135:176b8275d35d 176
<> 135:176b8275d35d 177 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
<> 135:176b8275d35d 178
<> 135:176b8275d35d 179 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
<> 135:176b8275d35d 180 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
<> 135:176b8275d35d 181
<> 135:176b8275d35d 182 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
<> 135:176b8275d35d 183
<> 135:176b8275d35d 184 } LL_DAC_InitTypeDef;
<> 135:176b8275d35d 185
<> 135:176b8275d35d 186 /**
<> 135:176b8275d35d 187 * @}
<> 135:176b8275d35d 188 */
<> 135:176b8275d35d 189 #endif /* USE_FULL_LL_DRIVER */
<> 135:176b8275d35d 190
<> 135:176b8275d35d 191 /* Exported constants --------------------------------------------------------*/
<> 135:176b8275d35d 192 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
<> 135:176b8275d35d 193 * @{
<> 135:176b8275d35d 194 */
<> 135:176b8275d35d 195
<> 135:176b8275d35d 196 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
<> 135:176b8275d35d 197 * @brief Flags defines which can be used with LL_DAC_ReadReg function
<> 135:176b8275d35d 198 * @{
<> 135:176b8275d35d 199 */
<> 135:176b8275d35d 200 /* DAC channel 1 flags */
<> 135:176b8275d35d 201 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
<> 135:176b8275d35d 202
<> 135:176b8275d35d 203 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 204 /* DAC channel 2 flags */
<> 135:176b8275d35d 205 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
<> 135:176b8275d35d 206 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 207 /**
<> 135:176b8275d35d 208 * @}
<> 135:176b8275d35d 209 */
<> 135:176b8275d35d 210
<> 135:176b8275d35d 211 /** @defgroup DAC_LL_EC_IT DAC interruptions
<> 135:176b8275d35d 212 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
<> 135:176b8275d35d 213 * @{
<> 135:176b8275d35d 214 */
<> 135:176b8275d35d 215 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
<> 135:176b8275d35d 216 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 217 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
<> 135:176b8275d35d 218 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 219 /**
<> 135:176b8275d35d 220 * @}
<> 135:176b8275d35d 221 */
<> 135:176b8275d35d 222
<> 135:176b8275d35d 223 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
<> 135:176b8275d35d 224 * @{
<> 135:176b8275d35d 225 */
<> 135:176b8275d35d 226 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
<> 135:176b8275d35d 227 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 228 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
<> 135:176b8275d35d 229 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 230 /**
<> 135:176b8275d35d 231 * @}
<> 135:176b8275d35d 232 */
<> 135:176b8275d35d 233
<> 135:176b8275d35d 234 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
<> 135:176b8275d35d 235 * @{
<> 135:176b8275d35d 236 */
<> 135:176b8275d35d 237 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
<> 135:176b8275d35d 238 #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
<> 135:176b8275d35d 239 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
<> 135:176b8275d35d 240 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
<> 135:176b8275d35d 241 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
<> 135:176b8275d35d 242 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
<> 135:176b8275d35d 243 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
<> 135:176b8275d35d 244 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
<> 135:176b8275d35d 245 #define LL_DAC_TRIG_EXT_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM3_TRGO) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM8_TRGO for TIM8 selection. */
<> 135:176b8275d35d 246 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
<> 135:176b8275d35d 247
<> 135:176b8275d35d 248 #elif defined(STM32F303x8) || defined(STM32F328xx)
<> 135:176b8275d35d 249 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
<> 135:176b8275d35d 250 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
<> 135:176b8275d35d 251 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
<> 135:176b8275d35d 252 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
<> 135:176b8275d35d 253 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
<> 135:176b8275d35d 254 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
<> 135:176b8275d35d 255
<> 135:176b8275d35d 256 #elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8)
<> 135:176b8275d35d 257 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
<> 135:176b8275d35d 258 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
<> 135:176b8275d35d 259 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
<> 135:176b8275d35d 260 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
<> 135:176b8275d35d 261 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
<> 135:176b8275d35d 262 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
<> 135:176b8275d35d 263
<> 135:176b8275d35d 264 #elif defined(STM32F301x8) || defined(STM32F318xx)
<> 135:176b8275d35d 265 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
<> 135:176b8275d35d 266 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
<> 135:176b8275d35d 267 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
<> 135:176b8275d35d 268 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
<> 135:176b8275d35d 269
<> 135:176b8275d35d 270 #elif defined(STM32F373xC) || defined(STM32F378xx)
<> 135:176b8275d35d 271 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
<> 135:176b8275d35d 272 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
<> 135:176b8275d35d 273 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
<> 135:176b8275d35d 274 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
<> 135:176b8275d35d 275 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
<> 135:176b8275d35d 276 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
<> 135:176b8275d35d 277 #define LL_DAC_TRIG_EXT_TIM18_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO) /*!< DAC channel conversion trigger from external IP: TIM18 TRGO. */
<> 135:176b8275d35d 278 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
<> 135:176b8275d35d 279
<> 135:176b8275d35d 280 #elif defined(STM32F334x8)
<> 135:176b8275d35d 281 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
<> 135:176b8275d35d 282 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
<> 135:176b8275d35d 283 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
<> 135:176b8275d35d 284 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
<> 135:176b8275d35d 285 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_TIM15_TRGO for TIM15 selection. */
<> 135:176b8275d35d 286 #define LL_DAC_TRIGGER_HRTIM1_DACTRG1 (LL_DAC_TRIG_EXT_TIM15_TRGO) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG1. Available only on DAC instance: DAC1. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_HRTIM1_DAC1_TRIG1 for HRTIM1 TRIG1 selection. */
<> 135:176b8275d35d 287 #define LL_DAC_TRIGGER_HRTIM1_DACTRG2 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG2. Available only on DAC instance: DAC2. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG5_REMAP_HRTIM1_DAC1_TRIG2 for HRTIM1 TRIG2 selection. */
<> 135:176b8275d35d 288 #define LL_DAC_TRIGGER_HRTIM1_DACTRG3 (LL_DAC_TRIGGER_HRTIM1_DACTRG2) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG3. */
<> 135:176b8275d35d 289 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
<> 135:176b8275d35d 290
<> 135:176b8275d35d 291 #endif
<> 135:176b8275d35d 292 /**
<> 135:176b8275d35d 293 * @}
<> 135:176b8275d35d 294 */
<> 135:176b8275d35d 295
<> 135:176b8275d35d 296 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
<> 135:176b8275d35d 297 * @{
<> 135:176b8275d35d 298 */
<> 135:176b8275d35d 299 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
<> 135:176b8275d35d 300 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
<> 135:176b8275d35d 301 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
<> 135:176b8275d35d 302 /**
<> 135:176b8275d35d 303 * @}
<> 135:176b8275d35d 304 */
<> 135:176b8275d35d 305
<> 135:176b8275d35d 306 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
<> 135:176b8275d35d 307 * @{
<> 135:176b8275d35d 308 */
<> 135:176b8275d35d 309 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
<> 135:176b8275d35d 310 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
<> 135:176b8275d35d 311 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
<> 135:176b8275d35d 312 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
<> 135:176b8275d35d 313 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
<> 135:176b8275d35d 314 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
<> 135:176b8275d35d 315 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
<> 135:176b8275d35d 316 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
<> 135:176b8275d35d 317 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
<> 135:176b8275d35d 318 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
<> 135:176b8275d35d 319 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
<> 135:176b8275d35d 320 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
<> 135:176b8275d35d 321 /**
<> 135:176b8275d35d 322 * @}
<> 135:176b8275d35d 323 */
<> 135:176b8275d35d 324
<> 135:176b8275d35d 325 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
<> 135:176b8275d35d 326 * @{
<> 135:176b8275d35d 327 */
<> 135:176b8275d35d 328 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
<> 135:176b8275d35d 329 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
<> 135:176b8275d35d 330 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
<> 135:176b8275d35d 331 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
<> 135:176b8275d35d 332 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
<> 135:176b8275d35d 333 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
<> 135:176b8275d35d 334 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
<> 135:176b8275d35d 335 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
<> 135:176b8275d35d 336 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
<> 135:176b8275d35d 337 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
<> 135:176b8275d35d 338 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
<> 135:176b8275d35d 339 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
<> 135:176b8275d35d 340 /**
<> 135:176b8275d35d 341 * @}
<> 135:176b8275d35d 342 */
<> 135:176b8275d35d 343
<> 135:176b8275d35d 344 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
<> 135:176b8275d35d 345 * @{
<> 135:176b8275d35d 346 */
<> 135:176b8275d35d 347 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
<> 135:176b8275d35d 348 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
<> 135:176b8275d35d 349
<> 135:176b8275d35d 350 #if defined(DAC_CR_OUTEN1) || defined(DAC_CR_OUTEN2)
<> 135:176b8275d35d 351 #define LL_DAC_OUTPUT_SWITCH_DISABLE (LL_DAC_OUTPUT_BUFFER_ENABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. Selection of switch disabled: DAC channel output not connected to GPIO. */
<> 135:176b8275d35d 352 #define LL_DAC_OUTPUT_SWITCH_ENABLE (LL_DAC_OUTPUT_BUFFER_DISABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. */
<> 135:176b8275d35d 353 #endif
<> 135:176b8275d35d 354 /**
<> 135:176b8275d35d 355 * @}
<> 135:176b8275d35d 356 */
<> 135:176b8275d35d 357
<> 135:176b8275d35d 358
<> 135:176b8275d35d 359 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
<> 135:176b8275d35d 360 * @{
<> 135:176b8275d35d 361 */
<> 135:176b8275d35d 362 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
<> 135:176b8275d35d 363 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
<> 135:176b8275d35d 364 /**
<> 135:176b8275d35d 365 * @}
<> 135:176b8275d35d 366 */
<> 135:176b8275d35d 367
<> 135:176b8275d35d 368 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
<> 135:176b8275d35d 369 * @{
<> 135:176b8275d35d 370 */
<> 135:176b8275d35d 371 /* List of DAC registers intended to be used (most commonly) with */
<> 135:176b8275d35d 372 /* DMA transfer. */
<> 135:176b8275d35d 373 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
<> 135:176b8275d35d 374 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
<> 135:176b8275d35d 375 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
<> 135:176b8275d35d 376 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
<> 135:176b8275d35d 377 /**
<> 135:176b8275d35d 378 * @}
<> 135:176b8275d35d 379 */
<> 135:176b8275d35d 380
<> 135:176b8275d35d 381 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
<> 135:176b8275d35d 382 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
<> 135:176b8275d35d 383 * not timeout values.
<> 135:176b8275d35d 384 * For details on delays values, refer to descriptions in source code
<> 135:176b8275d35d 385 * above each literal definition.
<> 135:176b8275d35d 386 * @{
<> 135:176b8275d35d 387 */
<> 135:176b8275d35d 388
<> 135:176b8275d35d 389 /* Delay for DAC channel voltage settling time from DAC channel startup */
<> 135:176b8275d35d 390 /* (transition from disable to enable). */
<> 135:176b8275d35d 391 /* Note: DAC channel startup time depends on board application environment: */
<> 135:176b8275d35d 392 /* impedance connected to DAC channel output. */
<> 135:176b8275d35d 393 /* The delay below is specified under conditions: */
<> 135:176b8275d35d 394 /* - voltage maximum transition (lowest to highest value) */
<> 135:176b8275d35d 395 /* - until voltage reaches final value +-1LSB */
<> 135:176b8275d35d 396 /* - DAC channel output buffer enabled */
<> 135:176b8275d35d 397 /* - load impedance of 5kOhm (min), 50pF (max) */
<> 135:176b8275d35d 398 /* Literal set to maximum value (refer to device datasheet, */
<> 135:176b8275d35d 399 /* parameter "tWAKEUP"). */
<> 135:176b8275d35d 400 /* Unit: us */
<> 135:176b8275d35d 401 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
<> 135:176b8275d35d 402
<> 135:176b8275d35d 403 /* Delay for DAC channel voltage settling time. */
<> 135:176b8275d35d 404 /* Note: DAC channel startup time depends on board application environment: */
<> 135:176b8275d35d 405 /* impedance connected to DAC channel output. */
<> 135:176b8275d35d 406 /* The delay below is specified under conditions: */
<> 135:176b8275d35d 407 /* - voltage maximum transition (lowest to highest value) */
<> 135:176b8275d35d 408 /* - until voltage reaches final value +-1LSB */
<> 135:176b8275d35d 409 /* - DAC channel output buffer enabled */
<> 135:176b8275d35d 410 /* - load impedance of 5kOhm min, 50pF max */
<> 135:176b8275d35d 411 /* Literal set to maximum value (refer to device datasheet, */
<> 135:176b8275d35d 412 /* parameter "tSETTLING"). */
<> 135:176b8275d35d 413 /* Unit: us */
<> 135:176b8275d35d 414 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
<> 135:176b8275d35d 415 /**
<> 135:176b8275d35d 416 * @}
<> 135:176b8275d35d 417 */
<> 135:176b8275d35d 418
<> 135:176b8275d35d 419 /**
<> 135:176b8275d35d 420 * @}
<> 135:176b8275d35d 421 */
<> 135:176b8275d35d 422
<> 135:176b8275d35d 423 /* Exported macro ------------------------------------------------------------*/
<> 135:176b8275d35d 424 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
<> 135:176b8275d35d 425 * @{
<> 135:176b8275d35d 426 */
<> 135:176b8275d35d 427
<> 135:176b8275d35d 428 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
<> 135:176b8275d35d 429 * @{
<> 135:176b8275d35d 430 */
<> 135:176b8275d35d 431
<> 135:176b8275d35d 432 /**
<> 135:176b8275d35d 433 * @brief Write a value in DAC register
<> 135:176b8275d35d 434 * @param __INSTANCE__ DAC Instance
<> 135:176b8275d35d 435 * @param __REG__ Register to be written
<> 135:176b8275d35d 436 * @param __VALUE__ Value to be written in the register
<> 135:176b8275d35d 437 * @retval None
<> 135:176b8275d35d 438 */
<> 135:176b8275d35d 439 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 135:176b8275d35d 440
<> 135:176b8275d35d 441 /**
<> 135:176b8275d35d 442 * @brief Read a value in DAC register
<> 135:176b8275d35d 443 * @param __INSTANCE__ DAC Instance
<> 135:176b8275d35d 444 * @param __REG__ Register to be read
<> 135:176b8275d35d 445 * @retval Register value
<> 135:176b8275d35d 446 */
<> 135:176b8275d35d 447 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 135:176b8275d35d 448
<> 135:176b8275d35d 449 /**
<> 135:176b8275d35d 450 * @}
<> 135:176b8275d35d 451 */
<> 135:176b8275d35d 452
<> 135:176b8275d35d 453 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
<> 135:176b8275d35d 454 * @{
<> 135:176b8275d35d 455 */
<> 135:176b8275d35d 456
<> 135:176b8275d35d 457 /**
<> 135:176b8275d35d 458 * @brief Helper macro to get DAC channel number in decimal format
<> 135:176b8275d35d 459 * from literals LL_DAC_CHANNEL_x.
<> 135:176b8275d35d 460 * Example:
<> 135:176b8275d35d 461 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
<> 135:176b8275d35d 462 * will return decimal number "1".
<> 135:176b8275d35d 463 * @note The input can be a value from functions where a channel
<> 135:176b8275d35d 464 * number is returned.
<> 135:176b8275d35d 465 * @param __CHANNEL__ This parameter can be one of the following values:
<> 135:176b8275d35d 466 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 467 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 468 *
<> 135:176b8275d35d 469 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 470 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 471 * @retval 1...2 (value "2" depending on DAC channel 2 availability)
<> 135:176b8275d35d 472 */
<> 135:176b8275d35d 473 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
<> 135:176b8275d35d 474 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
<> 135:176b8275d35d 475
<> 135:176b8275d35d 476 /**
<> 135:176b8275d35d 477 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
<> 135:176b8275d35d 478 * from number in decimal format.
<> 135:176b8275d35d 479 * Example:
<> 135:176b8275d35d 480 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
<> 135:176b8275d35d 481 * will return a data equivalent to "LL_DAC_CHANNEL_1".
<> 135:176b8275d35d 482 * @note If the input parameter does not correspond to a DAC channel,
<> 135:176b8275d35d 483 * this macro returns value '0'.
<> 135:176b8275d35d 484 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
<> 135:176b8275d35d 485 * @retval Returned value can be one of the following values:
<> 135:176b8275d35d 486 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 487 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 488 *
<> 135:176b8275d35d 489 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 490 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 491 */
<> 135:176b8275d35d 492 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 493 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<> 135:176b8275d35d 494 (((__DECIMAL_NB__) == 1U) \
<> 135:176b8275d35d 495 ? ( \
<> 135:176b8275d35d 496 LL_DAC_CHANNEL_1 \
<> 135:176b8275d35d 497 ) \
<> 135:176b8275d35d 498 : \
<> 135:176b8275d35d 499 (((__DECIMAL_NB__) == 2U) \
<> 135:176b8275d35d 500 ? ( \
<> 135:176b8275d35d 501 LL_DAC_CHANNEL_2 \
<> 135:176b8275d35d 502 ) \
<> 135:176b8275d35d 503 : \
<> 135:176b8275d35d 504 ( \
<> 135:176b8275d35d 505 0 \
<> 135:176b8275d35d 506 ) \
<> 135:176b8275d35d 507 ) \
<> 135:176b8275d35d 508 )
<> 135:176b8275d35d 509 #else
<> 135:176b8275d35d 510 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<> 135:176b8275d35d 511 (((__DECIMAL_NB__) == 1U) \
<> 135:176b8275d35d 512 ? ( \
<> 135:176b8275d35d 513 LL_DAC_CHANNEL_1 \
<> 135:176b8275d35d 514 ) \
<> 135:176b8275d35d 515 : \
<> 135:176b8275d35d 516 ( \
<> 135:176b8275d35d 517 0 \
<> 135:176b8275d35d 518 ) \
<> 135:176b8275d35d 519 )
<> 135:176b8275d35d 520 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 521
<> 135:176b8275d35d 522 /**
<> 135:176b8275d35d 523 * @brief Helper macro to define the DAC conversion data full-scale digital
<> 135:176b8275d35d 524 * value corresponding to the selected DAC resolution.
<> 135:176b8275d35d 525 * @note DAC conversion data full-scale corresponds to voltage range
<> 135:176b8275d35d 526 * determined by analog voltage references Vref+ and Vref-
<> 135:176b8275d35d 527 * (refer to reference manual).
<> 135:176b8275d35d 528 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
<> 135:176b8275d35d 529 * @arg @ref LL_DAC_RESOLUTION_12B
<> 135:176b8275d35d 530 * @arg @ref LL_DAC_RESOLUTION_8B
<> 135:176b8275d35d 531 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
<> 135:176b8275d35d 532 */
<> 135:176b8275d35d 533 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
<> 135:176b8275d35d 534 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
<> 135:176b8275d35d 535
<> 135:176b8275d35d 536 /**
<> 135:176b8275d35d 537 * @brief Helper macro to calculate the DAC conversion data (unit: digital
<> 135:176b8275d35d 538 * value) corresponding to a voltage (unit: mVolt).
<> 135:176b8275d35d 539 * @note This helper macro is intended to provide input data in voltage
<> 135:176b8275d35d 540 * rather than digital value,
<> 135:176b8275d35d 541 * to be used with LL DAC functions such as
<> 135:176b8275d35d 542 * @ref LL_DAC_ConvertData12RightAligned().
<> 135:176b8275d35d 543 * @note Analog reference voltage (Vref+) must be either known from
<> 135:176b8275d35d 544 * user board environment or can be calculated using ADC measurement
<> 135:176b8275d35d 545 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<> 135:176b8275d35d 546 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<> 135:176b8275d35d 547 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
<> 135:176b8275d35d 548 * (unit: mVolt).
<> 135:176b8275d35d 549 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
<> 135:176b8275d35d 550 * @arg @ref LL_DAC_RESOLUTION_12B
<> 135:176b8275d35d 551 * @arg @ref LL_DAC_RESOLUTION_8B
<> 135:176b8275d35d 552 * @retval DAC conversion data (unit: digital value)
<> 135:176b8275d35d 553 */
<> 135:176b8275d35d 554 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
<> 135:176b8275d35d 555 __DAC_VOLTAGE__,\
<> 135:176b8275d35d 556 __DAC_RESOLUTION__) \
<> 135:176b8275d35d 557 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
<> 135:176b8275d35d 558 / (__VREFANALOG_VOLTAGE__) \
<> 135:176b8275d35d 559 )
<> 135:176b8275d35d 560
<> 135:176b8275d35d 561 /**
<> 135:176b8275d35d 562 * @}
<> 135:176b8275d35d 563 */
<> 135:176b8275d35d 564
<> 135:176b8275d35d 565 /**
<> 135:176b8275d35d 566 * @}
<> 135:176b8275d35d 567 */
<> 135:176b8275d35d 568
<> 135:176b8275d35d 569
<> 135:176b8275d35d 570 /* Exported functions --------------------------------------------------------*/
<> 135:176b8275d35d 571 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
<> 135:176b8275d35d 572 * @{
<> 135:176b8275d35d 573 */
<> 135:176b8275d35d 574 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
<> 135:176b8275d35d 575 * @{
<> 135:176b8275d35d 576 */
<> 135:176b8275d35d 577
<> 135:176b8275d35d 578 /**
<> 135:176b8275d35d 579 * @brief Set the conversion trigger source for the selected DAC channel.
<> 135:176b8275d35d 580 * @note For conversion trigger source to be effective, DAC trigger
<> 135:176b8275d35d 581 * must be enabled using function @ref LL_DAC_EnableTrigger().
<> 135:176b8275d35d 582 * @note To set conversion trigger source, DAC channel must be disabled.
<> 135:176b8275d35d 583 * Otherwise, the setting is discarded.
<> 135:176b8275d35d 584 * @note Availability of parameters of trigger sources from timer
<> 135:176b8275d35d 585 * depends on timers availability on the selected device.
<> 135:176b8275d35d 586 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
<> 135:176b8275d35d 587 * CR TSEL2 LL_DAC_SetTriggerSource
<> 135:176b8275d35d 588 * @param DACx DAC instance
<> 135:176b8275d35d 589 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 590 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 591 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 592 *
<> 135:176b8275d35d 593 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 594 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 595 * @param TriggerSource This parameter can be one of the following values:
<> 135:176b8275d35d 596 * @arg @ref LL_DAC_TRIG_SOFTWARE
<> 135:176b8275d35d 597 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
<> 135:176b8275d35d 598 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
<> 135:176b8275d35d 599 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1)
<> 135:176b8275d35d 600 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1)
<> 135:176b8275d35d 601 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
<> 135:176b8275d35d 602 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1)
<> 135:176b8275d35d 603 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1)
<> 135:176b8275d35d 604 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1)
<> 135:176b8275d35d 605 * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1)
<> 135:176b8275d35d 606 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
<> 135:176b8275d35d 607 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
<> 135:176b8275d35d 608 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
<> 135:176b8275d35d 609 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
<> 135:176b8275d35d 610 *
<> 135:176b8275d35d 611 * (1) On STM32F3, parameter not available on all devices
<> 135:176b8275d35d 612 * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
<> 135:176b8275d35d 613 * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
<> 135:176b8275d35d 614 * @retval None
<> 135:176b8275d35d 615 */
<> 135:176b8275d35d 616 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
<> 135:176b8275d35d 617 {
<> 135:176b8275d35d 618 MODIFY_REG(DACx->CR,
<> 135:176b8275d35d 619 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<> 135:176b8275d35d 620 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 135:176b8275d35d 621 }
<> 135:176b8275d35d 622
<> 135:176b8275d35d 623 /**
<> 135:176b8275d35d 624 * @brief Get the conversion trigger source for the selected DAC channel.
<> 135:176b8275d35d 625 * @note For conversion trigger source to be effective, DAC trigger
<> 135:176b8275d35d 626 * must be enabled using function @ref LL_DAC_EnableTrigger().
<> 135:176b8275d35d 627 * @note Availability of parameters of trigger sources from timer
<> 135:176b8275d35d 628 * depends on timers availability on the selected device.
<> 135:176b8275d35d 629 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
<> 135:176b8275d35d 630 * CR TSEL2 LL_DAC_GetTriggerSource
<> 135:176b8275d35d 631 * @param DACx DAC instance
<> 135:176b8275d35d 632 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 633 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 634 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 635 *
<> 135:176b8275d35d 636 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 637 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 638 * @retval Returned value can be one of the following values:
<> 135:176b8275d35d 639 * @arg @ref LL_DAC_TRIG_SOFTWARE
<> 135:176b8275d35d 640 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
<> 135:176b8275d35d 641 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
<> 135:176b8275d35d 642 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1)
<> 135:176b8275d35d 643 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1)
<> 135:176b8275d35d 644 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
<> 135:176b8275d35d 645 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1)
<> 135:176b8275d35d 646 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1)
<> 135:176b8275d35d 647 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1)
<> 135:176b8275d35d 648 * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1)
<> 135:176b8275d35d 649 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
<> 135:176b8275d35d 650 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
<> 135:176b8275d35d 651 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
<> 135:176b8275d35d 652 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
<> 135:176b8275d35d 653 *
<> 135:176b8275d35d 654 * (1) On STM32F3, parameter not available on all devices
<> 135:176b8275d35d 655 * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
<> 135:176b8275d35d 656 * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
<> 135:176b8275d35d 657 */
<> 135:176b8275d35d 658 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 659 {
<> 135:176b8275d35d 660 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 135:176b8275d35d 661 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 135:176b8275d35d 662 );
<> 135:176b8275d35d 663 }
<> 135:176b8275d35d 664
<> 135:176b8275d35d 665 /**
<> 135:176b8275d35d 666 * @brief Set the waveform automatic generation mode
<> 135:176b8275d35d 667 * for the selected DAC channel.
<> 135:176b8275d35d 668 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
<> 135:176b8275d35d 669 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
<> 135:176b8275d35d 670 * @param DACx DAC instance
<> 135:176b8275d35d 671 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 672 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 673 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 674 *
<> 135:176b8275d35d 675 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 676 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 677 * @param WaveAutoGeneration This parameter can be one of the following values:
<> 135:176b8275d35d 678 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
<> 135:176b8275d35d 679 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
<> 135:176b8275d35d 680 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
<> 135:176b8275d35d 681 * @retval None
<> 135:176b8275d35d 682 */
<> 135:176b8275d35d 683 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
<> 135:176b8275d35d 684 {
<> 135:176b8275d35d 685 MODIFY_REG(DACx->CR,
<> 135:176b8275d35d 686 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<> 135:176b8275d35d 687 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 135:176b8275d35d 688 }
<> 135:176b8275d35d 689
<> 135:176b8275d35d 690 /**
<> 135:176b8275d35d 691 * @brief Get the waveform automatic generation mode
<> 135:176b8275d35d 692 * for the selected DAC channel.
<> 135:176b8275d35d 693 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
<> 135:176b8275d35d 694 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
<> 135:176b8275d35d 695 * @param DACx DAC instance
<> 135:176b8275d35d 696 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 697 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 698 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 699 *
<> 135:176b8275d35d 700 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 701 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 702 * @retval Returned value can be one of the following values:
<> 135:176b8275d35d 703 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
<> 135:176b8275d35d 704 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
<> 135:176b8275d35d 705 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
<> 135:176b8275d35d 706 */
<> 135:176b8275d35d 707 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 708 {
<> 135:176b8275d35d 709 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 135:176b8275d35d 710 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 135:176b8275d35d 711 );
<> 135:176b8275d35d 712 }
<> 135:176b8275d35d 713
<> 135:176b8275d35d 714 /**
<> 135:176b8275d35d 715 * @brief Set the noise waveform generation for the selected DAC channel:
<> 135:176b8275d35d 716 * Noise mode and parameters LFSR (linear feedback shift register).
<> 135:176b8275d35d 717 * @note For wave generation to be effective, DAC channel
<> 135:176b8275d35d 718 * wave generation mode must be enabled using
<> 135:176b8275d35d 719 * function @ref LL_DAC_SetWaveAutoGeneration().
<> 135:176b8275d35d 720 * @note This setting can be set when the selected DAC channel is disabled
<> 135:176b8275d35d 721 * (otherwise, the setting operation is ignored).
<> 135:176b8275d35d 722 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
<> 135:176b8275d35d 723 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
<> 135:176b8275d35d 724 * @param DACx DAC instance
<> 135:176b8275d35d 725 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 726 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 727 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 728 *
<> 135:176b8275d35d 729 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 730 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 731 * @param NoiseLFSRMask This parameter can be one of the following values:
<> 135:176b8275d35d 732 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
<> 135:176b8275d35d 733 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
<> 135:176b8275d35d 734 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
<> 135:176b8275d35d 735 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
<> 135:176b8275d35d 736 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
<> 135:176b8275d35d 737 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
<> 135:176b8275d35d 738 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
<> 135:176b8275d35d 739 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
<> 135:176b8275d35d 740 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
<> 135:176b8275d35d 741 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
<> 135:176b8275d35d 742 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
<> 135:176b8275d35d 743 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
<> 135:176b8275d35d 744 * @retval None
<> 135:176b8275d35d 745 */
<> 135:176b8275d35d 746 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
<> 135:176b8275d35d 747 {
<> 135:176b8275d35d 748 MODIFY_REG(DACx->CR,
<> 135:176b8275d35d 749 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<> 135:176b8275d35d 750 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 135:176b8275d35d 751 }
<> 135:176b8275d35d 752
<> 135:176b8275d35d 753 /**
<> 135:176b8275d35d 754 * @brief Set the noise waveform generation for the selected DAC channel:
<> 135:176b8275d35d 755 * Noise mode and parameters LFSR (linear feedback shift register).
<> 135:176b8275d35d 756 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
<> 135:176b8275d35d 757 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
<> 135:176b8275d35d 758 * @param DACx DAC instance
<> 135:176b8275d35d 759 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 760 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 761 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 762 *
<> 135:176b8275d35d 763 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 764 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 765 * @retval Returned value can be one of the following values:
<> 135:176b8275d35d 766 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
<> 135:176b8275d35d 767 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
<> 135:176b8275d35d 768 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
<> 135:176b8275d35d 769 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
<> 135:176b8275d35d 770 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
<> 135:176b8275d35d 771 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
<> 135:176b8275d35d 772 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
<> 135:176b8275d35d 773 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
<> 135:176b8275d35d 774 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
<> 135:176b8275d35d 775 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
<> 135:176b8275d35d 776 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
<> 135:176b8275d35d 777 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
<> 135:176b8275d35d 778 */
<> 135:176b8275d35d 779 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 780 {
<> 135:176b8275d35d 781 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 135:176b8275d35d 782 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 135:176b8275d35d 783 );
<> 135:176b8275d35d 784 }
<> 135:176b8275d35d 785
<> 135:176b8275d35d 786 /**
<> 135:176b8275d35d 787 * @brief Set the triangle waveform generation for the selected DAC channel:
<> 135:176b8275d35d 788 * triangle mode and amplitude.
<> 135:176b8275d35d 789 * @note For wave generation to be effective, DAC channel
<> 135:176b8275d35d 790 * wave generation mode must be enabled using
<> 135:176b8275d35d 791 * function @ref LL_DAC_SetWaveAutoGeneration().
<> 135:176b8275d35d 792 * @note This setting can be set when the selected DAC channel is disabled
<> 135:176b8275d35d 793 * (otherwise, the setting operation is ignored).
<> 135:176b8275d35d 794 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
<> 135:176b8275d35d 795 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
<> 135:176b8275d35d 796 * @param DACx DAC instance
<> 135:176b8275d35d 797 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 798 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 799 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 800 *
<> 135:176b8275d35d 801 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 802 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 803 * @param TriangleAmplitude This parameter can be one of the following values:
<> 135:176b8275d35d 804 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
<> 135:176b8275d35d 805 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
<> 135:176b8275d35d 806 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
<> 135:176b8275d35d 807 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
<> 135:176b8275d35d 808 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
<> 135:176b8275d35d 809 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
<> 135:176b8275d35d 810 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
<> 135:176b8275d35d 811 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
<> 135:176b8275d35d 812 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
<> 135:176b8275d35d 813 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
<> 135:176b8275d35d 814 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
<> 135:176b8275d35d 815 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
<> 135:176b8275d35d 816 * @retval None
<> 135:176b8275d35d 817 */
<> 135:176b8275d35d 818 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
<> 135:176b8275d35d 819 {
<> 135:176b8275d35d 820 MODIFY_REG(DACx->CR,
<> 135:176b8275d35d 821 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<> 135:176b8275d35d 822 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 135:176b8275d35d 823 }
<> 135:176b8275d35d 824
<> 135:176b8275d35d 825 /**
<> 135:176b8275d35d 826 * @brief Set the triangle waveform generation for the selected DAC channel:
<> 135:176b8275d35d 827 * triangle mode and amplitude.
<> 135:176b8275d35d 828 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
<> 135:176b8275d35d 829 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
<> 135:176b8275d35d 830 * @param DACx DAC instance
<> 135:176b8275d35d 831 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 832 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 833 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 834 *
<> 135:176b8275d35d 835 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 836 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 837 * @retval Returned value can be one of the following values:
<> 135:176b8275d35d 838 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
<> 135:176b8275d35d 839 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
<> 135:176b8275d35d 840 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
<> 135:176b8275d35d 841 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
<> 135:176b8275d35d 842 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
<> 135:176b8275d35d 843 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
<> 135:176b8275d35d 844 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
<> 135:176b8275d35d 845 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
<> 135:176b8275d35d 846 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
<> 135:176b8275d35d 847 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
<> 135:176b8275d35d 848 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
<> 135:176b8275d35d 849 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
<> 135:176b8275d35d 850 */
<> 135:176b8275d35d 851 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 852 {
<> 135:176b8275d35d 853 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 135:176b8275d35d 854 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 135:176b8275d35d 855 );
<> 135:176b8275d35d 856 }
<> 135:176b8275d35d 857
<> 135:176b8275d35d 858 /**
<> 135:176b8275d35d 859 * @brief Set the output buffer for the selected DAC channel.
<> 135:176b8275d35d 860 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
<> 135:176b8275d35d 861 * CR BOFF2 LL_DAC_SetOutputBuffer
<> 135:176b8275d35d 862 * @param DACx DAC instance
<> 135:176b8275d35d 863 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 864 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 865 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 866 *
<> 135:176b8275d35d 867 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 868 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 869 * @param OutputBuffer This parameter can be one of the following values:
<> 135:176b8275d35d 870 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
<> 135:176b8275d35d 871 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
<> 135:176b8275d35d 872 * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
<> 135:176b8275d35d 873 * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1)
<> 135:176b8275d35d 874 *
<> 135:176b8275d35d 875 * (1) Feature specific to STM32F303x6/8 and STM32F328:
<> 135:176b8275d35d 876 * On DAC1 channel 2, output buffer is replaced by a switch
<> 135:176b8275d35d 877 * to connect DAC channel output to pin PA5.
<> 135:176b8275d35d 878 * On DAC2 channel 1, output buffer is replaced by a switch
<> 135:176b8275d35d 879 * to connect DAC channel output to pin PA6.
<> 135:176b8275d35d 880 * @retval None
<> 135:176b8275d35d 881 */
<> 135:176b8275d35d 882 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
<> 135:176b8275d35d 883 {
<> 135:176b8275d35d 884 MODIFY_REG(DACx->CR,
<> 135:176b8275d35d 885 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<> 135:176b8275d35d 886 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 135:176b8275d35d 887 }
<> 135:176b8275d35d 888
<> 135:176b8275d35d 889 /**
<> 135:176b8275d35d 890 * @brief Get the output buffer state for the selected DAC channel.
<> 135:176b8275d35d 891 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
<> 135:176b8275d35d 892 * CR BOFF2 LL_DAC_GetOutputBuffer
<> 135:176b8275d35d 893 * @param DACx DAC instance
<> 135:176b8275d35d 894 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 895 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 896 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 897 *
<> 135:176b8275d35d 898 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 899 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 900 * @retval Returned value can be one of the following values:
<> 135:176b8275d35d 901 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
<> 135:176b8275d35d 902 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
<> 135:176b8275d35d 903 * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
<> 135:176b8275d35d 904 * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1)
<> 135:176b8275d35d 905 *
<> 135:176b8275d35d 906 * (1) Feature specific to STM32F303x6/8 and STM32F328:
<> 135:176b8275d35d 907 * On DAC1 channel 2, output buffer is replaced by a switch
<> 135:176b8275d35d 908 * to connect DAC channel output to pin PA5.
<> 135:176b8275d35d 909 * On DAC2 channel 1, output buffer is replaced by a switch
<> 135:176b8275d35d 910 * to connect DAC channel output to pin PA6.
<> 135:176b8275d35d 911 */
<> 135:176b8275d35d 912 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 913 {
<> 135:176b8275d35d 914 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 135:176b8275d35d 915 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<> 135:176b8275d35d 916 );
<> 135:176b8275d35d 917 }
<> 135:176b8275d35d 918
<> 135:176b8275d35d 919 /**
<> 135:176b8275d35d 920 * @}
<> 135:176b8275d35d 921 */
<> 135:176b8275d35d 922
<> 135:176b8275d35d 923 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
<> 135:176b8275d35d 924 * @{
<> 135:176b8275d35d 925 */
<> 135:176b8275d35d 926
<> 135:176b8275d35d 927 /**
<> 135:176b8275d35d 928 * @brief Enable DAC DMA transfer request of the selected channel.
<> 135:176b8275d35d 929 * @note To configure DMA source address (peripheral address),
<> 135:176b8275d35d 930 * use function @ref LL_DAC_DMA_GetRegAddr().
<> 135:176b8275d35d 931 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
<> 135:176b8275d35d 932 * CR DMAEN2 LL_DAC_EnableDMAReq
<> 135:176b8275d35d 933 * @param DACx DAC instance
<> 135:176b8275d35d 934 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 935 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 936 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 937 *
<> 135:176b8275d35d 938 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 939 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 940 * @retval None
<> 135:176b8275d35d 941 */
<> 135:176b8275d35d 942 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 943 {
<> 135:176b8275d35d 944 SET_BIT(DACx->CR,
<> 135:176b8275d35d 945 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 135:176b8275d35d 946 }
<> 135:176b8275d35d 947
<> 135:176b8275d35d 948 /**
<> 135:176b8275d35d 949 * @brief Disable DAC DMA transfer request of the selected channel.
<> 135:176b8275d35d 950 * @note To configure DMA source address (peripheral address),
<> 135:176b8275d35d 951 * use function @ref LL_DAC_DMA_GetRegAddr().
<> 135:176b8275d35d 952 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
<> 135:176b8275d35d 953 * CR DMAEN2 LL_DAC_DisableDMAReq
<> 135:176b8275d35d 954 * @param DACx DAC instance
<> 135:176b8275d35d 955 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 956 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 957 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 958 *
<> 135:176b8275d35d 959 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 960 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 961 * @retval None
<> 135:176b8275d35d 962 */
<> 135:176b8275d35d 963 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 964 {
<> 135:176b8275d35d 965 CLEAR_BIT(DACx->CR,
<> 135:176b8275d35d 966 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 135:176b8275d35d 967 }
<> 135:176b8275d35d 968
<> 135:176b8275d35d 969 /**
<> 135:176b8275d35d 970 * @brief Get DAC DMA transfer request state of the selected channel.
<> 135:176b8275d35d 971 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
<> 135:176b8275d35d 972 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
<> 135:176b8275d35d 973 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
<> 135:176b8275d35d 974 * @param DACx DAC instance
<> 135:176b8275d35d 975 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 976 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 977 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 978 *
<> 135:176b8275d35d 979 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 980 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 981 * @retval State of bit (1 or 0).
<> 135:176b8275d35d 982 */
<> 135:176b8275d35d 983 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 984 {
<> 135:176b8275d35d 985 return (READ_BIT(DACx->CR,
<> 135:176b8275d35d 986 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 135:176b8275d35d 987 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<> 135:176b8275d35d 988 }
<> 135:176b8275d35d 989
<> 135:176b8275d35d 990 /**
<> 135:176b8275d35d 991 * @brief Function to help to configure DMA transfer to DAC: retrieve the
<> 135:176b8275d35d 992 * DAC register address from DAC instance and a list of DAC registers
<> 135:176b8275d35d 993 * intended to be used (most commonly) with DMA transfer.
<> 135:176b8275d35d 994 * @note These DAC registers are data holding registers:
<> 135:176b8275d35d 995 * when DAC conversion is requested, DAC generates a DMA transfer
<> 135:176b8275d35d 996 * request to have data available in DAC data holding registers.
<> 135:176b8275d35d 997 * @note This macro is intended to be used with LL DMA driver, refer to
<> 135:176b8275d35d 998 * function "LL_DMA_ConfigAddresses()".
<> 135:176b8275d35d 999 * Example:
<> 135:176b8275d35d 1000 * LL_DMA_ConfigAddresses(DMA1,
<> 135:176b8275d35d 1001 * LL_DMA_CHANNEL_1,
<> 135:176b8275d35d 1002 * (uint32_t)&< array or variable >,
<> 135:176b8275d35d 1003 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
<> 135:176b8275d35d 1004 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
<> 135:176b8275d35d 1005 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<> 135:176b8275d35d 1006 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<> 135:176b8275d35d 1007 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<> 135:176b8275d35d 1008 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
<> 135:176b8275d35d 1009 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
<> 135:176b8275d35d 1010 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
<> 135:176b8275d35d 1011 * @param DACx DAC instance
<> 135:176b8275d35d 1012 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 1013 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 1014 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 1015 *
<> 135:176b8275d35d 1016 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 1017 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 1018 * @param Register This parameter can be one of the following values:
<> 135:176b8275d35d 1019 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
<> 135:176b8275d35d 1020 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
<> 135:176b8275d35d 1021 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
<> 135:176b8275d35d 1022 * @retval DAC register address
<> 135:176b8275d35d 1023 */
<> 135:176b8275d35d 1024 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
<> 135:176b8275d35d 1025 {
<> 135:176b8275d35d 1026 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
<> 135:176b8275d35d 1027 /* DAC channel selected. */
<> 135:176b8275d35d 1028 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
<> 135:176b8275d35d 1029 }
<> 135:176b8275d35d 1030 /**
<> 135:176b8275d35d 1031 * @}
<> 135:176b8275d35d 1032 */
<> 135:176b8275d35d 1033
<> 135:176b8275d35d 1034 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
<> 135:176b8275d35d 1035 * @{
<> 135:176b8275d35d 1036 */
<> 135:176b8275d35d 1037
<> 135:176b8275d35d 1038 /**
<> 135:176b8275d35d 1039 * @brief Enable DAC selected channel.
<> 135:176b8275d35d 1040 * @rmtoll CR EN1 LL_DAC_Enable\n
<> 135:176b8275d35d 1041 * CR EN2 LL_DAC_Enable
<> 135:176b8275d35d 1042 * @note After enable from off state, DAC channel requires a delay
<> 135:176b8275d35d 1043 * for output voltage to reach accuracy +/- 1 LSB.
<> 135:176b8275d35d 1044 * Refer to device datasheet, parameter "tWAKEUP".
<> 135:176b8275d35d 1045 * @param DACx DAC instance
<> 135:176b8275d35d 1046 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 1047 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 1048 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 1049 *
<> 135:176b8275d35d 1050 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 1051 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 1052 * @retval None
<> 135:176b8275d35d 1053 */
<> 135:176b8275d35d 1054 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 1055 {
<> 135:176b8275d35d 1056 SET_BIT(DACx->CR,
<> 135:176b8275d35d 1057 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 135:176b8275d35d 1058 }
<> 135:176b8275d35d 1059
<> 135:176b8275d35d 1060 /**
<> 135:176b8275d35d 1061 * @brief Disable DAC selected channel.
<> 135:176b8275d35d 1062 * @rmtoll CR EN1 LL_DAC_Disable\n
<> 135:176b8275d35d 1063 * CR EN2 LL_DAC_Disable
<> 135:176b8275d35d 1064 * @param DACx DAC instance
<> 135:176b8275d35d 1065 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 1066 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 1067 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 1068 *
<> 135:176b8275d35d 1069 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 1070 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 1071 * @retval None
<> 135:176b8275d35d 1072 */
<> 135:176b8275d35d 1073 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 1074 {
<> 135:176b8275d35d 1075 CLEAR_BIT(DACx->CR,
<> 135:176b8275d35d 1076 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 135:176b8275d35d 1077 }
<> 135:176b8275d35d 1078
<> 135:176b8275d35d 1079 /**
<> 135:176b8275d35d 1080 * @brief Get DAC enable state of the selected channel.
<> 135:176b8275d35d 1081 * (0: DAC channel is disabled, 1: DAC channel is enabled)
<> 135:176b8275d35d 1082 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
<> 135:176b8275d35d 1083 * CR EN2 LL_DAC_IsEnabled
<> 135:176b8275d35d 1084 * @param DACx DAC instance
<> 135:176b8275d35d 1085 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 1086 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 1087 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 1088 *
<> 135:176b8275d35d 1089 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 1090 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 1091 * @retval State of bit (1 or 0).
<> 135:176b8275d35d 1092 */
<> 135:176b8275d35d 1093 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 1094 {
<> 135:176b8275d35d 1095 return (READ_BIT(DACx->CR,
<> 135:176b8275d35d 1096 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 135:176b8275d35d 1097 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<> 135:176b8275d35d 1098 }
<> 135:176b8275d35d 1099
<> 135:176b8275d35d 1100 /**
<> 135:176b8275d35d 1101 * @brief Enable DAC trigger of the selected channel.
<> 135:176b8275d35d 1102 * @note - If DAC trigger is disabled, DAC conversion is performed
<> 135:176b8275d35d 1103 * automatically once the data holding register is updated,
<> 135:176b8275d35d 1104 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
<> 135:176b8275d35d 1105 * @ref LL_DAC_ConvertData12RightAligned(), ...
<> 135:176b8275d35d 1106 * - If DAC trigger is enabled, DAC conversion is performed
<> 135:176b8275d35d 1107 * only when a hardware of software trigger event is occurring.
<> 135:176b8275d35d 1108 * Select trigger source using
<> 135:176b8275d35d 1109 * function @ref LL_DAC_SetTriggerSource().
<> 135:176b8275d35d 1110 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
<> 135:176b8275d35d 1111 * CR TEN2 LL_DAC_EnableTrigger
<> 135:176b8275d35d 1112 * @param DACx DAC instance
<> 135:176b8275d35d 1113 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 1114 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 1115 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 1116 *
<> 135:176b8275d35d 1117 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 1118 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 1119 * @retval None
<> 135:176b8275d35d 1120 */
<> 135:176b8275d35d 1121 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 1122 {
<> 135:176b8275d35d 1123 SET_BIT(DACx->CR,
<> 135:176b8275d35d 1124 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 135:176b8275d35d 1125 }
<> 135:176b8275d35d 1126
<> 135:176b8275d35d 1127 /**
<> 135:176b8275d35d 1128 * @brief Disable DAC trigger of the selected channel.
<> 135:176b8275d35d 1129 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
<> 135:176b8275d35d 1130 * CR TEN2 LL_DAC_DisableTrigger
<> 135:176b8275d35d 1131 * @param DACx DAC instance
<> 135:176b8275d35d 1132 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 1133 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 1134 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 1135 *
<> 135:176b8275d35d 1136 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 1137 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 1138 * @retval None
<> 135:176b8275d35d 1139 */
<> 135:176b8275d35d 1140 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 1141 {
<> 135:176b8275d35d 1142 CLEAR_BIT(DACx->CR,
<> 135:176b8275d35d 1143 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<> 135:176b8275d35d 1144 }
<> 135:176b8275d35d 1145
<> 135:176b8275d35d 1146 /**
<> 135:176b8275d35d 1147 * @brief Get DAC trigger state of the selected channel.
<> 135:176b8275d35d 1148 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
<> 135:176b8275d35d 1149 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
<> 135:176b8275d35d 1150 * CR TEN2 LL_DAC_IsTriggerEnabled
<> 135:176b8275d35d 1151 * @param DACx DAC instance
<> 135:176b8275d35d 1152 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 1153 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 1154 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 1155 *
<> 135:176b8275d35d 1156 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 1157 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 1158 * @retval State of bit (1 or 0).
<> 135:176b8275d35d 1159 */
<> 135:176b8275d35d 1160 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 1161 {
<> 135:176b8275d35d 1162 return (READ_BIT(DACx->CR,
<> 135:176b8275d35d 1163 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<> 135:176b8275d35d 1164 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<> 135:176b8275d35d 1165 }
<> 135:176b8275d35d 1166
<> 135:176b8275d35d 1167 /**
<> 135:176b8275d35d 1168 * @brief Trig DAC conversion by software for the selected DAC channel.
<> 135:176b8275d35d 1169 * @note Preliminarily, DAC trigger must be set to software trigger
<> 135:176b8275d35d 1170 * using function @ref LL_DAC_SetTriggerSource()
<> 135:176b8275d35d 1171 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
<> 135:176b8275d35d 1172 * and DAC trigger must be enabled using
<> 135:176b8275d35d 1173 * function @ref LL_DAC_EnableTrigger().
<> 135:176b8275d35d 1174 * @note For devices featuring DAC with 2 channels: this function
<> 135:176b8275d35d 1175 * can perform a SW start of both DAC channels simultaneously.
<> 135:176b8275d35d 1176 * Two channels can be selected as parameter.
<> 135:176b8275d35d 1177 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
<> 135:176b8275d35d 1178 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
<> 135:176b8275d35d 1179 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
<> 135:176b8275d35d 1180 * @param DACx DAC instance
<> 135:176b8275d35d 1181 * @param DAC_Channel This parameter can a combination of the following values:
<> 135:176b8275d35d 1182 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 1183 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 1184 *
<> 135:176b8275d35d 1185 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 1186 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 1187 * @retval None
<> 135:176b8275d35d 1188 */
<> 135:176b8275d35d 1189 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 1190 {
<> 135:176b8275d35d 1191 SET_BIT(DACx->SWTRIGR,
<> 135:176b8275d35d 1192 (DAC_Channel & DAC_SWTR_CHX_MASK));
<> 135:176b8275d35d 1193 }
<> 135:176b8275d35d 1194
<> 135:176b8275d35d 1195 /**
<> 135:176b8275d35d 1196 * @brief Set the data to be loaded in the data holding register
<> 135:176b8275d35d 1197 * in format 12 bits left alignment (LSB aligned on bit 0),
<> 135:176b8275d35d 1198 * for the selected DAC channel.
<> 135:176b8275d35d 1199 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
<> 135:176b8275d35d 1200 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
<> 135:176b8275d35d 1201 * @param DACx DAC instance
<> 135:176b8275d35d 1202 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 1203 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 1204 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 1205 *
<> 135:176b8275d35d 1206 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 1207 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 1208 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
<> 135:176b8275d35d 1209 * @retval None
<> 135:176b8275d35d 1210 */
<> 135:176b8275d35d 1211 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<> 135:176b8275d35d 1212 {
<> 135:176b8275d35d 1213 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
<> 135:176b8275d35d 1214
<> 135:176b8275d35d 1215 MODIFY_REG(*preg,
<> 135:176b8275d35d 1216 DAC_DHR12R1_DACC1DHR,
<> 135:176b8275d35d 1217 Data);
<> 135:176b8275d35d 1218 }
<> 135:176b8275d35d 1219
<> 135:176b8275d35d 1220 /**
<> 135:176b8275d35d 1221 * @brief Set the data to be loaded in the data holding register
<> 135:176b8275d35d 1222 * in format 12 bits left alignment (MSB aligned on bit 15),
<> 135:176b8275d35d 1223 * for the selected DAC channel.
<> 135:176b8275d35d 1224 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
<> 135:176b8275d35d 1225 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
<> 135:176b8275d35d 1226 * @param DACx DAC instance
<> 135:176b8275d35d 1227 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 1228 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 1229 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 1230 *
<> 135:176b8275d35d 1231 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 1232 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 1233 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
<> 135:176b8275d35d 1234 * @retval None
<> 135:176b8275d35d 1235 */
<> 135:176b8275d35d 1236 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<> 135:176b8275d35d 1237 {
<> 135:176b8275d35d 1238 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
<> 135:176b8275d35d 1239
<> 135:176b8275d35d 1240 MODIFY_REG(*preg,
<> 135:176b8275d35d 1241 DAC_DHR12L1_DACC1DHR,
<> 135:176b8275d35d 1242 Data);
<> 135:176b8275d35d 1243 }
<> 135:176b8275d35d 1244
<> 135:176b8275d35d 1245 /**
<> 135:176b8275d35d 1246 * @brief Set the data to be loaded in the data holding register
<> 135:176b8275d35d 1247 * in format 8 bits left alignment (LSB aligned on bit 0),
<> 135:176b8275d35d 1248 * for the selected DAC channel.
<> 135:176b8275d35d 1249 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
<> 135:176b8275d35d 1250 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
<> 135:176b8275d35d 1251 * @param DACx DAC instance
<> 135:176b8275d35d 1252 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 1253 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 1254 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 1255 *
<> 135:176b8275d35d 1256 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 1257 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 1258 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
<> 135:176b8275d35d 1259 * @retval None
<> 135:176b8275d35d 1260 */
<> 135:176b8275d35d 1261 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<> 135:176b8275d35d 1262 {
<> 135:176b8275d35d 1263 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
<> 135:176b8275d35d 1264
<> 135:176b8275d35d 1265 MODIFY_REG(*preg,
<> 135:176b8275d35d 1266 DAC_DHR8R1_DACC1DHR,
<> 135:176b8275d35d 1267 Data);
<> 135:176b8275d35d 1268 }
<> 135:176b8275d35d 1269
<> 135:176b8275d35d 1270 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 1271 /**
<> 135:176b8275d35d 1272 * @brief Set the data to be loaded in the data holding register
<> 135:176b8275d35d 1273 * in format 12 bits left alignment (LSB aligned on bit 0),
<> 135:176b8275d35d 1274 * for both DAC channels.
<> 135:176b8275d35d 1275 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
<> 135:176b8275d35d 1276 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
<> 135:176b8275d35d 1277 * @param DACx DAC instance
<> 135:176b8275d35d 1278 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
<> 135:176b8275d35d 1279 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
<> 135:176b8275d35d 1280 * @retval None
<> 135:176b8275d35d 1281 */
<> 135:176b8275d35d 1282 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<> 135:176b8275d35d 1283 {
<> 135:176b8275d35d 1284 MODIFY_REG(DACx->DHR12RD,
<> 135:176b8275d35d 1285 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
<> 135:176b8275d35d 1286 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
<> 135:176b8275d35d 1287 }
<> 135:176b8275d35d 1288
<> 135:176b8275d35d 1289 /**
<> 135:176b8275d35d 1290 * @brief Set the data to be loaded in the data holding register
<> 135:176b8275d35d 1291 * in format 12 bits left alignment (MSB aligned on bit 15),
<> 135:176b8275d35d 1292 * for both DAC channels.
<> 135:176b8275d35d 1293 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
<> 135:176b8275d35d 1294 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
<> 135:176b8275d35d 1295 * @param DACx DAC instance
<> 135:176b8275d35d 1296 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
<> 135:176b8275d35d 1297 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
<> 135:176b8275d35d 1298 * @retval None
<> 135:176b8275d35d 1299 */
<> 135:176b8275d35d 1300 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<> 135:176b8275d35d 1301 {
<> 135:176b8275d35d 1302 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
<> 135:176b8275d35d 1303 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
<> 135:176b8275d35d 1304 /* the 4 LSB must be taken into account for the shift value. */
<> 135:176b8275d35d 1305 MODIFY_REG(DACx->DHR12LD,
<> 135:176b8275d35d 1306 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
<> 135:176b8275d35d 1307 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
<> 135:176b8275d35d 1308 }
<> 135:176b8275d35d 1309
<> 135:176b8275d35d 1310 /**
<> 135:176b8275d35d 1311 * @brief Set the data to be loaded in the data holding register
<> 135:176b8275d35d 1312 * in format 8 bits left alignment (LSB aligned on bit 0),
<> 135:176b8275d35d 1313 * for both DAC channels.
<> 135:176b8275d35d 1314 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
<> 135:176b8275d35d 1315 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
<> 135:176b8275d35d 1316 * @param DACx DAC instance
<> 135:176b8275d35d 1317 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
<> 135:176b8275d35d 1318 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
<> 135:176b8275d35d 1319 * @retval None
<> 135:176b8275d35d 1320 */
<> 135:176b8275d35d 1321 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<> 135:176b8275d35d 1322 {
<> 135:176b8275d35d 1323 MODIFY_REG(DACx->DHR8RD,
<> 135:176b8275d35d 1324 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
<> 135:176b8275d35d 1325 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
<> 135:176b8275d35d 1326 }
<> 135:176b8275d35d 1327
<> 135:176b8275d35d 1328 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 1329 /**
<> 135:176b8275d35d 1330 * @brief Retrieve output data currently generated for the selected DAC channel.
<> 135:176b8275d35d 1331 * @note Whatever alignment and resolution settings
<> 135:176b8275d35d 1332 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
<> 135:176b8275d35d 1333 * @ref LL_DAC_ConvertData12RightAligned(), ...),
<> 135:176b8275d35d 1334 * output data format is 12 bits right aligned (LSB aligned on bit 0).
<> 135:176b8275d35d 1335 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
<> 135:176b8275d35d 1336 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
<> 135:176b8275d35d 1337 * @param DACx DAC instance
<> 135:176b8275d35d 1338 * @param DAC_Channel This parameter can be one of the following values:
<> 135:176b8275d35d 1339 * @arg @ref LL_DAC_CHANNEL_1
<> 135:176b8275d35d 1340 * @arg @ref LL_DAC_CHANNEL_2 (1)
<> 135:176b8275d35d 1341 *
<> 135:176b8275d35d 1342 * (1) On this STM32 serie, parameter not available on all devices.
<> 135:176b8275d35d 1343 * Refer to device datasheet for channels availability.
<> 135:176b8275d35d 1344 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<> 135:176b8275d35d 1345 */
<> 135:176b8275d35d 1346 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<> 135:176b8275d35d 1347 {
<> 135:176b8275d35d 1348 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
<> 135:176b8275d35d 1349
<> 135:176b8275d35d 1350 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
<> 135:176b8275d35d 1351 }
<> 135:176b8275d35d 1352
<> 135:176b8275d35d 1353 /**
<> 135:176b8275d35d 1354 * @}
<> 135:176b8275d35d 1355 */
<> 135:176b8275d35d 1356
<> 135:176b8275d35d 1357 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
<> 135:176b8275d35d 1358 * @{
<> 135:176b8275d35d 1359 */
<> 135:176b8275d35d 1360 /**
<> 135:176b8275d35d 1361 * @brief Get DAC underrun flag for DAC channel 1
<> 135:176b8275d35d 1362 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
<> 135:176b8275d35d 1363 * @param DACx DAC instance
<> 135:176b8275d35d 1364 * @retval State of bit (1 or 0).
<> 135:176b8275d35d 1365 */
<> 135:176b8275d35d 1366 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
<> 135:176b8275d35d 1367 {
<> 135:176b8275d35d 1368 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
<> 135:176b8275d35d 1369 }
<> 135:176b8275d35d 1370
<> 135:176b8275d35d 1371 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 1372 /**
<> 135:176b8275d35d 1373 * @brief Get DAC underrun flag for DAC channel 2
<> 135:176b8275d35d 1374 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
<> 135:176b8275d35d 1375 * @param DACx DAC instance
<> 135:176b8275d35d 1376 * @retval State of bit (1 or 0).
<> 135:176b8275d35d 1377 */
<> 135:176b8275d35d 1378 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
<> 135:176b8275d35d 1379 {
<> 135:176b8275d35d 1380 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
<> 135:176b8275d35d 1381 }
<> 135:176b8275d35d 1382 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 1383
<> 135:176b8275d35d 1384 /**
<> 135:176b8275d35d 1385 * @brief Clear DAC underrun flag for DAC channel 1
<> 135:176b8275d35d 1386 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
<> 135:176b8275d35d 1387 * @param DACx DAC instance
<> 135:176b8275d35d 1388 * @retval None
<> 135:176b8275d35d 1389 */
<> 135:176b8275d35d 1390 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
<> 135:176b8275d35d 1391 {
<> 135:176b8275d35d 1392 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
<> 135:176b8275d35d 1393 }
<> 135:176b8275d35d 1394
<> 135:176b8275d35d 1395 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 1396 /**
<> 135:176b8275d35d 1397 * @brief Clear DAC underrun flag for DAC channel 2
<> 135:176b8275d35d 1398 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
<> 135:176b8275d35d 1399 * @param DACx DAC instance
<> 135:176b8275d35d 1400 * @retval None
<> 135:176b8275d35d 1401 */
<> 135:176b8275d35d 1402 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
<> 135:176b8275d35d 1403 {
<> 135:176b8275d35d 1404 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
<> 135:176b8275d35d 1405 }
<> 135:176b8275d35d 1406 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 1407
<> 135:176b8275d35d 1408 /**
<> 135:176b8275d35d 1409 * @}
<> 135:176b8275d35d 1410 */
<> 135:176b8275d35d 1411
<> 135:176b8275d35d 1412 /** @defgroup DAC_LL_EF_IT_Management IT management
<> 135:176b8275d35d 1413 * @{
<> 135:176b8275d35d 1414 */
<> 135:176b8275d35d 1415
<> 135:176b8275d35d 1416 /**
<> 135:176b8275d35d 1417 * @brief Enable DMA underrun interrupt for DAC channel 1
<> 135:176b8275d35d 1418 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
<> 135:176b8275d35d 1419 * @param DACx DAC instance
<> 135:176b8275d35d 1420 * @retval None
<> 135:176b8275d35d 1421 */
<> 135:176b8275d35d 1422 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
<> 135:176b8275d35d 1423 {
<> 135:176b8275d35d 1424 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
<> 135:176b8275d35d 1425 }
<> 135:176b8275d35d 1426
<> 135:176b8275d35d 1427 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 1428 /**
<> 135:176b8275d35d 1429 * @brief Enable DMA underrun interrupt for DAC channel 2
<> 135:176b8275d35d 1430 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
<> 135:176b8275d35d 1431 * @param DACx DAC instance
<> 135:176b8275d35d 1432 * @retval None
<> 135:176b8275d35d 1433 */
<> 135:176b8275d35d 1434 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
<> 135:176b8275d35d 1435 {
<> 135:176b8275d35d 1436 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
<> 135:176b8275d35d 1437 }
<> 135:176b8275d35d 1438 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 1439
<> 135:176b8275d35d 1440 /**
<> 135:176b8275d35d 1441 * @brief Disable DMA underrun interrupt for DAC channel 1
<> 135:176b8275d35d 1442 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
<> 135:176b8275d35d 1443 * @param DACx DAC instance
<> 135:176b8275d35d 1444 * @retval None
<> 135:176b8275d35d 1445 */
<> 135:176b8275d35d 1446 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
<> 135:176b8275d35d 1447 {
<> 135:176b8275d35d 1448 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
<> 135:176b8275d35d 1449 }
<> 135:176b8275d35d 1450
<> 135:176b8275d35d 1451 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 1452 /**
<> 135:176b8275d35d 1453 * @brief Disable DMA underrun interrupt for DAC channel 2
<> 135:176b8275d35d 1454 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
<> 135:176b8275d35d 1455 * @param DACx DAC instance
<> 135:176b8275d35d 1456 * @retval None
<> 135:176b8275d35d 1457 */
<> 135:176b8275d35d 1458 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
<> 135:176b8275d35d 1459 {
<> 135:176b8275d35d 1460 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
<> 135:176b8275d35d 1461 }
<> 135:176b8275d35d 1462 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 1463
<> 135:176b8275d35d 1464 /**
<> 135:176b8275d35d 1465 * @brief Get DMA underrun interrupt for DAC channel 1
<> 135:176b8275d35d 1466 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
<> 135:176b8275d35d 1467 * @param DACx DAC instance
<> 135:176b8275d35d 1468 * @retval State of bit (1 or 0).
<> 135:176b8275d35d 1469 */
<> 135:176b8275d35d 1470 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
<> 135:176b8275d35d 1471 {
<> 135:176b8275d35d 1472 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
<> 135:176b8275d35d 1473 }
<> 135:176b8275d35d 1474
<> 135:176b8275d35d 1475 #if defined(DAC_CHANNEL2_SUPPORT)
<> 135:176b8275d35d 1476 /**
<> 135:176b8275d35d 1477 * @brief Get DMA underrun interrupt for DAC channel 2
<> 135:176b8275d35d 1478 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
<> 135:176b8275d35d 1479 * @param DACx DAC instance
<> 135:176b8275d35d 1480 * @retval State of bit (1 or 0).
<> 135:176b8275d35d 1481 */
<> 135:176b8275d35d 1482 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
<> 135:176b8275d35d 1483 {
<> 135:176b8275d35d 1484 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
<> 135:176b8275d35d 1485 }
<> 135:176b8275d35d 1486 #endif /* DAC_CHANNEL2_SUPPORT */
<> 135:176b8275d35d 1487
<> 135:176b8275d35d 1488 /**
<> 135:176b8275d35d 1489 * @}
<> 135:176b8275d35d 1490 */
<> 135:176b8275d35d 1491
<> 135:176b8275d35d 1492 #if defined(USE_FULL_LL_DRIVER)
<> 135:176b8275d35d 1493 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
<> 135:176b8275d35d 1494 * @{
<> 135:176b8275d35d 1495 */
<> 135:176b8275d35d 1496
<> 135:176b8275d35d 1497 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
<> 135:176b8275d35d 1498 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
<> 135:176b8275d35d 1499 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
<> 135:176b8275d35d 1500
<> 135:176b8275d35d 1501 /**
<> 135:176b8275d35d 1502 * @}
<> 135:176b8275d35d 1503 */
<> 135:176b8275d35d 1504 #endif /* USE_FULL_LL_DRIVER */
<> 135:176b8275d35d 1505
<> 135:176b8275d35d 1506 /**
<> 135:176b8275d35d 1507 * @}
<> 135:176b8275d35d 1508 */
<> 135:176b8275d35d 1509
<> 135:176b8275d35d 1510 /**
<> 135:176b8275d35d 1511 * @}
<> 135:176b8275d35d 1512 */
<> 135:176b8275d35d 1513
<> 135:176b8275d35d 1514 #endif /* DAC1 || DAC2 */
<> 135:176b8275d35d 1515
<> 135:176b8275d35d 1516 /**
<> 135:176b8275d35d 1517 * @}
<> 135:176b8275d35d 1518 */
<> 135:176b8275d35d 1519
<> 135:176b8275d35d 1520 #ifdef __cplusplus
<> 135:176b8275d35d 1521 }
<> 135:176b8275d35d 1522 #endif
<> 135:176b8275d35d 1523
<> 135:176b8275d35d 1524 #endif /* __STM32F3xx_LL_DAC_H */
<> 135:176b8275d35d 1525
<> 135:176b8275d35d 1526 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/