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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_port.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_PORT_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_PORT_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 PORT
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * Pin Control and Interrupts
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_PORT_PCRn - Pin Control Register n
Kojto 90:cb3d968589d8 93 * - HW_PORT_GPCLR - Global Pin Control Low Register
Kojto 90:cb3d968589d8 94 * - HW_PORT_GPCHR - Global Pin Control High Register
Kojto 90:cb3d968589d8 95 * - HW_PORT_ISFR - Interrupt Status Flag Register
Kojto 90:cb3d968589d8 96 * - HW_PORT_DFER - Digital Filter Enable Register
Kojto 90:cb3d968589d8 97 * - HW_PORT_DFCR - Digital Filter Clock Register
Kojto 90:cb3d968589d8 98 * - HW_PORT_DFWR - Digital Filter Width Register
Kojto 90:cb3d968589d8 99 *
Kojto 90:cb3d968589d8 100 * - hw_port_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 101 */
Kojto 90:cb3d968589d8 102
Kojto 90:cb3d968589d8 103 #define HW_PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
Kojto 90:cb3d968589d8 104 #define HW_PORTA (0U) /*!< Instance number for PORTA. */
Kojto 90:cb3d968589d8 105 #define HW_PORTB (1U) /*!< Instance number for PORTB. */
Kojto 90:cb3d968589d8 106 #define HW_PORTC (2U) /*!< Instance number for PORTC. */
Kojto 90:cb3d968589d8 107 #define HW_PORTD (3U) /*!< Instance number for PORTD. */
Kojto 90:cb3d968589d8 108 #define HW_PORTE (4U) /*!< Instance number for PORTE. */
Kojto 90:cb3d968589d8 109
Kojto 90:cb3d968589d8 110 /*******************************************************************************
Kojto 90:cb3d968589d8 111 * HW_PORT_PCRn - Pin Control Register n
Kojto 90:cb3d968589d8 112 ******************************************************************************/
Kojto 90:cb3d968589d8 113
Kojto 90:cb3d968589d8 114 /*!
Kojto 90:cb3d968589d8 115 * @brief HW_PORT_PCRn - Pin Control Register n (RW)
Kojto 90:cb3d968589d8 116 *
Kojto 90:cb3d968589d8 117 * Reset value: 0x00000742U
Kojto 90:cb3d968589d8 118 *
Kojto 90:cb3d968589d8 119 * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
Kojto 90:cb3d968589d8 120 * this device. See the GPIO Configuration section for details on the available
Kojto 90:cb3d968589d8 121 * functions for each pin. Do not modify pin configuration registers associated
Kojto 90:cb3d968589d8 122 * with pins not available in your selected package. All unbonded pins not
Kojto 90:cb3d968589d8 123 * available in your package will default to DISABLE state for lowest power consumption.
Kojto 90:cb3d968589d8 124 */
Kojto 90:cb3d968589d8 125 typedef union _hw_port_pcrn
Kojto 90:cb3d968589d8 126 {
Kojto 90:cb3d968589d8 127 uint32_t U;
Kojto 90:cb3d968589d8 128 struct _hw_port_pcrn_bitfields
Kojto 90:cb3d968589d8 129 {
Kojto 90:cb3d968589d8 130 uint32_t PS : 1; /*!< [0] Pull Select */
Kojto 90:cb3d968589d8 131 uint32_t PE : 1; /*!< [1] Pull Enable */
Kojto 90:cb3d968589d8 132 uint32_t SRE : 1; /*!< [2] Slew Rate Enable */
Kojto 90:cb3d968589d8 133 uint32_t RESERVED0 : 1; /*!< [3] */
Kojto 90:cb3d968589d8 134 uint32_t PFE : 1; /*!< [4] Passive Filter Enable */
Kojto 90:cb3d968589d8 135 uint32_t ODE : 1; /*!< [5] Open Drain Enable */
Kojto 90:cb3d968589d8 136 uint32_t DSE : 1; /*!< [6] Drive Strength Enable */
Kojto 90:cb3d968589d8 137 uint32_t RESERVED1 : 1; /*!< [7] */
Kojto 90:cb3d968589d8 138 uint32_t MUX : 3; /*!< [10:8] Pin Mux Control */
Kojto 90:cb3d968589d8 139 uint32_t RESERVED2 : 4; /*!< [14:11] */
Kojto 90:cb3d968589d8 140 uint32_t LK : 1; /*!< [15] Lock Register */
Kojto 90:cb3d968589d8 141 uint32_t IRQC : 4; /*!< [19:16] Interrupt Configuration */
Kojto 90:cb3d968589d8 142 uint32_t RESERVED3 : 4; /*!< [23:20] */
Kojto 90:cb3d968589d8 143 uint32_t ISF : 1; /*!< [24] Interrupt Status Flag */
Kojto 90:cb3d968589d8 144 uint32_t RESERVED4 : 7; /*!< [31:25] */
Kojto 90:cb3d968589d8 145 } B;
Kojto 90:cb3d968589d8 146 } hw_port_pcrn_t;
Kojto 90:cb3d968589d8 147
Kojto 90:cb3d968589d8 148 /*!
Kojto 90:cb3d968589d8 149 * @name Constants and macros for entire PORT_PCRn register
Kojto 90:cb3d968589d8 150 */
Kojto 90:cb3d968589d8 151 /*@{*/
Kojto 90:cb3d968589d8 152 #define HW_PORT_PCRn_COUNT (32U)
Kojto 90:cb3d968589d8 153
Kojto 90:cb3d968589d8 154 #define HW_PORT_PCRn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
Kojto 90:cb3d968589d8 155
Kojto 90:cb3d968589d8 156 #define HW_PORT_PCRn(x, n) (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
Kojto 90:cb3d968589d8 157 #define HW_PORT_PCRn_RD(x, n) (HW_PORT_PCRn(x, n).U)
Kojto 90:cb3d968589d8 158 #define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
Kojto 90:cb3d968589d8 159 #define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 160 #define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 161 #define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 162 /*@}*/
Kojto 90:cb3d968589d8 163
Kojto 90:cb3d968589d8 164 /*
Kojto 90:cb3d968589d8 165 * Constants & macros for individual PORT_PCRn bitfields
Kojto 90:cb3d968589d8 166 */
Kojto 90:cb3d968589d8 167
Kojto 90:cb3d968589d8 168 /*!
Kojto 90:cb3d968589d8 169 * @name Register PORT_PCRn, field PS[0] (RW)
Kojto 90:cb3d968589d8 170 *
Kojto 90:cb3d968589d8 171 * Pull configuration is valid in all digital pin muxing modes.
Kojto 90:cb3d968589d8 172 *
Kojto 90:cb3d968589d8 173 * Values:
Kojto 90:cb3d968589d8 174 * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
Kojto 90:cb3d968589d8 175 * corresponding PE field is set.
Kojto 90:cb3d968589d8 176 * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
Kojto 90:cb3d968589d8 177 * corresponding PE field is set.
Kojto 90:cb3d968589d8 178 */
Kojto 90:cb3d968589d8 179 /*@{*/
Kojto 90:cb3d968589d8 180 #define BP_PORT_PCRn_PS (0U) /*!< Bit position for PORT_PCRn_PS. */
Kojto 90:cb3d968589d8 181 #define BM_PORT_PCRn_PS (0x00000001U) /*!< Bit mask for PORT_PCRn_PS. */
Kojto 90:cb3d968589d8 182 #define BS_PORT_PCRn_PS (1U) /*!< Bit field size in bits for PORT_PCRn_PS. */
Kojto 90:cb3d968589d8 183
Kojto 90:cb3d968589d8 184 /*! @brief Read current value of the PORT_PCRn_PS field. */
Kojto 90:cb3d968589d8 185 #define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
Kojto 90:cb3d968589d8 186
Kojto 90:cb3d968589d8 187 /*! @brief Format value for bitfield PORT_PCRn_PS. */
Kojto 90:cb3d968589d8 188 #define BF_PORT_PCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PS) & BM_PORT_PCRn_PS)
Kojto 90:cb3d968589d8 189
Kojto 90:cb3d968589d8 190 /*! @brief Set the PS field to a new value. */
Kojto 90:cb3d968589d8 191 #define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
Kojto 90:cb3d968589d8 192 /*@}*/
Kojto 90:cb3d968589d8 193
Kojto 90:cb3d968589d8 194 /*!
Kojto 90:cb3d968589d8 195 * @name Register PORT_PCRn, field PE[1] (RW)
Kojto 90:cb3d968589d8 196 *
Kojto 90:cb3d968589d8 197 * Pull configuration is valid in all digital pin muxing modes.
Kojto 90:cb3d968589d8 198 *
Kojto 90:cb3d968589d8 199 * Values:
Kojto 90:cb3d968589d8 200 * - 0 - Internal pullup or pulldown resistor is not enabled on the
Kojto 90:cb3d968589d8 201 * corresponding pin.
Kojto 90:cb3d968589d8 202 * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
Kojto 90:cb3d968589d8 203 * pin, if the pin is configured as a digital input.
Kojto 90:cb3d968589d8 204 */
Kojto 90:cb3d968589d8 205 /*@{*/
Kojto 90:cb3d968589d8 206 #define BP_PORT_PCRn_PE (1U) /*!< Bit position for PORT_PCRn_PE. */
Kojto 90:cb3d968589d8 207 #define BM_PORT_PCRn_PE (0x00000002U) /*!< Bit mask for PORT_PCRn_PE. */
Kojto 90:cb3d968589d8 208 #define BS_PORT_PCRn_PE (1U) /*!< Bit field size in bits for PORT_PCRn_PE. */
Kojto 90:cb3d968589d8 209
Kojto 90:cb3d968589d8 210 /*! @brief Read current value of the PORT_PCRn_PE field. */
Kojto 90:cb3d968589d8 211 #define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
Kojto 90:cb3d968589d8 212
Kojto 90:cb3d968589d8 213 /*! @brief Format value for bitfield PORT_PCRn_PE. */
Kojto 90:cb3d968589d8 214 #define BF_PORT_PCRn_PE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PE) & BM_PORT_PCRn_PE)
Kojto 90:cb3d968589d8 215
Kojto 90:cb3d968589d8 216 /*! @brief Set the PE field to a new value. */
Kojto 90:cb3d968589d8 217 #define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
Kojto 90:cb3d968589d8 218 /*@}*/
Kojto 90:cb3d968589d8 219
Kojto 90:cb3d968589d8 220 /*!
Kojto 90:cb3d968589d8 221 * @name Register PORT_PCRn, field SRE[2] (RW)
Kojto 90:cb3d968589d8 222 *
Kojto 90:cb3d968589d8 223 * Slew rate configuration is valid in all digital pin muxing modes.
Kojto 90:cb3d968589d8 224 *
Kojto 90:cb3d968589d8 225 * Values:
Kojto 90:cb3d968589d8 226 * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
Kojto 90:cb3d968589d8 227 * configured as a digital output.
Kojto 90:cb3d968589d8 228 * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
Kojto 90:cb3d968589d8 229 * configured as a digital output.
Kojto 90:cb3d968589d8 230 */
Kojto 90:cb3d968589d8 231 /*@{*/
Kojto 90:cb3d968589d8 232 #define BP_PORT_PCRn_SRE (2U) /*!< Bit position for PORT_PCRn_SRE. */
Kojto 90:cb3d968589d8 233 #define BM_PORT_PCRn_SRE (0x00000004U) /*!< Bit mask for PORT_PCRn_SRE. */
Kojto 90:cb3d968589d8 234 #define BS_PORT_PCRn_SRE (1U) /*!< Bit field size in bits for PORT_PCRn_SRE. */
Kojto 90:cb3d968589d8 235
Kojto 90:cb3d968589d8 236 /*! @brief Read current value of the PORT_PCRn_SRE field. */
Kojto 90:cb3d968589d8 237 #define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
Kojto 90:cb3d968589d8 238
Kojto 90:cb3d968589d8 239 /*! @brief Format value for bitfield PORT_PCRn_SRE. */
Kojto 90:cb3d968589d8 240 #define BF_PORT_PCRn_SRE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_SRE) & BM_PORT_PCRn_SRE)
Kojto 90:cb3d968589d8 241
Kojto 90:cb3d968589d8 242 /*! @brief Set the SRE field to a new value. */
Kojto 90:cb3d968589d8 243 #define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
Kojto 90:cb3d968589d8 244 /*@}*/
Kojto 90:cb3d968589d8 245
Kojto 90:cb3d968589d8 246 /*!
Kojto 90:cb3d968589d8 247 * @name Register PORT_PCRn, field PFE[4] (RW)
Kojto 90:cb3d968589d8 248 *
Kojto 90:cb3d968589d8 249 * Passive filter configuration is valid in all digital pin muxing modes.
Kojto 90:cb3d968589d8 250 *
Kojto 90:cb3d968589d8 251 * Values:
Kojto 90:cb3d968589d8 252 * - 0 - Passive input filter is disabled on the corresponding pin.
Kojto 90:cb3d968589d8 253 * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
Kojto 90:cb3d968589d8 254 * configured as a digital input. Refer to the device data sheet for filter
Kojto 90:cb3d968589d8 255 * characteristics.
Kojto 90:cb3d968589d8 256 */
Kojto 90:cb3d968589d8 257 /*@{*/
Kojto 90:cb3d968589d8 258 #define BP_PORT_PCRn_PFE (4U) /*!< Bit position for PORT_PCRn_PFE. */
Kojto 90:cb3d968589d8 259 #define BM_PORT_PCRn_PFE (0x00000010U) /*!< Bit mask for PORT_PCRn_PFE. */
Kojto 90:cb3d968589d8 260 #define BS_PORT_PCRn_PFE (1U) /*!< Bit field size in bits for PORT_PCRn_PFE. */
Kojto 90:cb3d968589d8 261
Kojto 90:cb3d968589d8 262 /*! @brief Read current value of the PORT_PCRn_PFE field. */
Kojto 90:cb3d968589d8 263 #define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
Kojto 90:cb3d968589d8 264
Kojto 90:cb3d968589d8 265 /*! @brief Format value for bitfield PORT_PCRn_PFE. */
Kojto 90:cb3d968589d8 266 #define BF_PORT_PCRn_PFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PFE) & BM_PORT_PCRn_PFE)
Kojto 90:cb3d968589d8 267
Kojto 90:cb3d968589d8 268 /*! @brief Set the PFE field to a new value. */
Kojto 90:cb3d968589d8 269 #define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
Kojto 90:cb3d968589d8 270 /*@}*/
Kojto 90:cb3d968589d8 271
Kojto 90:cb3d968589d8 272 /*!
Kojto 90:cb3d968589d8 273 * @name Register PORT_PCRn, field ODE[5] (RW)
Kojto 90:cb3d968589d8 274 *
Kojto 90:cb3d968589d8 275 * Open drain configuration is valid in all digital pin muxing modes.
Kojto 90:cb3d968589d8 276 *
Kojto 90:cb3d968589d8 277 * Values:
Kojto 90:cb3d968589d8 278 * - 0 - Open drain output is disabled on the corresponding pin.
Kojto 90:cb3d968589d8 279 * - 1 - Open drain output is enabled on the corresponding pin, if the pin is
Kojto 90:cb3d968589d8 280 * configured as a digital output.
Kojto 90:cb3d968589d8 281 */
Kojto 90:cb3d968589d8 282 /*@{*/
Kojto 90:cb3d968589d8 283 #define BP_PORT_PCRn_ODE (5U) /*!< Bit position for PORT_PCRn_ODE. */
Kojto 90:cb3d968589d8 284 #define BM_PORT_PCRn_ODE (0x00000020U) /*!< Bit mask for PORT_PCRn_ODE. */
Kojto 90:cb3d968589d8 285 #define BS_PORT_PCRn_ODE (1U) /*!< Bit field size in bits for PORT_PCRn_ODE. */
Kojto 90:cb3d968589d8 286
Kojto 90:cb3d968589d8 287 /*! @brief Read current value of the PORT_PCRn_ODE field. */
Kojto 90:cb3d968589d8 288 #define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
Kojto 90:cb3d968589d8 289
Kojto 90:cb3d968589d8 290 /*! @brief Format value for bitfield PORT_PCRn_ODE. */
Kojto 90:cb3d968589d8 291 #define BF_PORT_PCRn_ODE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ODE) & BM_PORT_PCRn_ODE)
Kojto 90:cb3d968589d8 292
Kojto 90:cb3d968589d8 293 /*! @brief Set the ODE field to a new value. */
Kojto 90:cb3d968589d8 294 #define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
Kojto 90:cb3d968589d8 295 /*@}*/
Kojto 90:cb3d968589d8 296
Kojto 90:cb3d968589d8 297 /*!
Kojto 90:cb3d968589d8 298 * @name Register PORT_PCRn, field DSE[6] (RW)
Kojto 90:cb3d968589d8 299 *
Kojto 90:cb3d968589d8 300 * Drive strength configuration is valid in all digital pin muxing modes.
Kojto 90:cb3d968589d8 301 *
Kojto 90:cb3d968589d8 302 * Values:
Kojto 90:cb3d968589d8 303 * - 0 - Low drive strength is configured on the corresponding pin, if pin is
Kojto 90:cb3d968589d8 304 * configured as a digital output.
Kojto 90:cb3d968589d8 305 * - 1 - High drive strength is configured on the corresponding pin, if pin is
Kojto 90:cb3d968589d8 306 * configured as a digital output.
Kojto 90:cb3d968589d8 307 */
Kojto 90:cb3d968589d8 308 /*@{*/
Kojto 90:cb3d968589d8 309 #define BP_PORT_PCRn_DSE (6U) /*!< Bit position for PORT_PCRn_DSE. */
Kojto 90:cb3d968589d8 310 #define BM_PORT_PCRn_DSE (0x00000040U) /*!< Bit mask for PORT_PCRn_DSE. */
Kojto 90:cb3d968589d8 311 #define BS_PORT_PCRn_DSE (1U) /*!< Bit field size in bits for PORT_PCRn_DSE. */
Kojto 90:cb3d968589d8 312
Kojto 90:cb3d968589d8 313 /*! @brief Read current value of the PORT_PCRn_DSE field. */
Kojto 90:cb3d968589d8 314 #define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
Kojto 90:cb3d968589d8 315
Kojto 90:cb3d968589d8 316 /*! @brief Format value for bitfield PORT_PCRn_DSE. */
Kojto 90:cb3d968589d8 317 #define BF_PORT_PCRn_DSE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_DSE) & BM_PORT_PCRn_DSE)
Kojto 90:cb3d968589d8 318
Kojto 90:cb3d968589d8 319 /*! @brief Set the DSE field to a new value. */
Kojto 90:cb3d968589d8 320 #define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
Kojto 90:cb3d968589d8 321 /*@}*/
Kojto 90:cb3d968589d8 322
Kojto 90:cb3d968589d8 323 /*!
Kojto 90:cb3d968589d8 324 * @name Register PORT_PCRn, field MUX[10:8] (RW)
Kojto 90:cb3d968589d8 325 *
Kojto 90:cb3d968589d8 326 * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
Kojto 90:cb3d968589d8 327 * reserved and may result in configuring the pin for a different pin muxing
Kojto 90:cb3d968589d8 328 * slot. The corresponding pin is configured in the following pin muxing slot as
Kojto 90:cb3d968589d8 329 * follows:
Kojto 90:cb3d968589d8 330 *
Kojto 90:cb3d968589d8 331 * Values:
Kojto 90:cb3d968589d8 332 * - 000 - Pin disabled (analog).
Kojto 90:cb3d968589d8 333 * - 001 - Alternative 1 (GPIO).
Kojto 90:cb3d968589d8 334 * - 010 - Alternative 2 (chip-specific).
Kojto 90:cb3d968589d8 335 * - 011 - Alternative 3 (chip-specific).
Kojto 90:cb3d968589d8 336 * - 100 - Alternative 4 (chip-specific).
Kojto 90:cb3d968589d8 337 * - 101 - Alternative 5 (chip-specific).
Kojto 90:cb3d968589d8 338 * - 110 - Alternative 6 (chip-specific).
Kojto 90:cb3d968589d8 339 * - 111 - Alternative 7 (chip-specific).
Kojto 90:cb3d968589d8 340 */
Kojto 90:cb3d968589d8 341 /*@{*/
Kojto 90:cb3d968589d8 342 #define BP_PORT_PCRn_MUX (8U) /*!< Bit position for PORT_PCRn_MUX. */
Kojto 90:cb3d968589d8 343 #define BM_PORT_PCRn_MUX (0x00000700U) /*!< Bit mask for PORT_PCRn_MUX. */
Kojto 90:cb3d968589d8 344 #define BS_PORT_PCRn_MUX (3U) /*!< Bit field size in bits for PORT_PCRn_MUX. */
Kojto 90:cb3d968589d8 345
Kojto 90:cb3d968589d8 346 /*! @brief Read current value of the PORT_PCRn_MUX field. */
Kojto 90:cb3d968589d8 347 #define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
Kojto 90:cb3d968589d8 348
Kojto 90:cb3d968589d8 349 /*! @brief Format value for bitfield PORT_PCRn_MUX. */
Kojto 90:cb3d968589d8 350 #define BF_PORT_PCRn_MUX(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_MUX) & BM_PORT_PCRn_MUX)
Kojto 90:cb3d968589d8 351
Kojto 90:cb3d968589d8 352 /*! @brief Set the MUX field to a new value. */
Kojto 90:cb3d968589d8 353 #define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
Kojto 90:cb3d968589d8 354 /*@}*/
Kojto 90:cb3d968589d8 355
Kojto 90:cb3d968589d8 356 /*!
Kojto 90:cb3d968589d8 357 * @name Register PORT_PCRn, field LK[15] (RW)
Kojto 90:cb3d968589d8 358 *
Kojto 90:cb3d968589d8 359 * Values:
Kojto 90:cb3d968589d8 360 * - 0 - Pin Control Register fields [15:0] are not locked.
Kojto 90:cb3d968589d8 361 * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
Kojto 90:cb3d968589d8 362 * until the next system reset.
Kojto 90:cb3d968589d8 363 */
Kojto 90:cb3d968589d8 364 /*@{*/
Kojto 90:cb3d968589d8 365 #define BP_PORT_PCRn_LK (15U) /*!< Bit position for PORT_PCRn_LK. */
Kojto 90:cb3d968589d8 366 #define BM_PORT_PCRn_LK (0x00008000U) /*!< Bit mask for PORT_PCRn_LK. */
Kojto 90:cb3d968589d8 367 #define BS_PORT_PCRn_LK (1U) /*!< Bit field size in bits for PORT_PCRn_LK. */
Kojto 90:cb3d968589d8 368
Kojto 90:cb3d968589d8 369 /*! @brief Read current value of the PORT_PCRn_LK field. */
Kojto 90:cb3d968589d8 370 #define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
Kojto 90:cb3d968589d8 371
Kojto 90:cb3d968589d8 372 /*! @brief Format value for bitfield PORT_PCRn_LK. */
Kojto 90:cb3d968589d8 373 #define BF_PORT_PCRn_LK(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_LK) & BM_PORT_PCRn_LK)
Kojto 90:cb3d968589d8 374
Kojto 90:cb3d968589d8 375 /*! @brief Set the LK field to a new value. */
Kojto 90:cb3d968589d8 376 #define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
Kojto 90:cb3d968589d8 377 /*@}*/
Kojto 90:cb3d968589d8 378
Kojto 90:cb3d968589d8 379 /*!
Kojto 90:cb3d968589d8 380 * @name Register PORT_PCRn, field IRQC[19:16] (RW)
Kojto 90:cb3d968589d8 381 *
Kojto 90:cb3d968589d8 382 * The pin interrupt configuration is valid in all digital pin muxing modes. The
Kojto 90:cb3d968589d8 383 * corresponding pin is configured to generate interrupt/DMA request as follows:
Kojto 90:cb3d968589d8 384 *
Kojto 90:cb3d968589d8 385 * Values:
Kojto 90:cb3d968589d8 386 * - 0000 - Interrupt/DMA request disabled.
Kojto 90:cb3d968589d8 387 * - 0001 - DMA request on rising edge.
Kojto 90:cb3d968589d8 388 * - 0010 - DMA request on falling edge.
Kojto 90:cb3d968589d8 389 * - 0011 - DMA request on either edge.
Kojto 90:cb3d968589d8 390 * - 1000 - Interrupt when logic 0.
Kojto 90:cb3d968589d8 391 * - 1001 - Interrupt on rising-edge.
Kojto 90:cb3d968589d8 392 * - 1010 - Interrupt on falling-edge.
Kojto 90:cb3d968589d8 393 * - 1011 - Interrupt on either edge.
Kojto 90:cb3d968589d8 394 * - 1100 - Interrupt when logic 1.
Kojto 90:cb3d968589d8 395 */
Kojto 90:cb3d968589d8 396 /*@{*/
Kojto 90:cb3d968589d8 397 #define BP_PORT_PCRn_IRQC (16U) /*!< Bit position for PORT_PCRn_IRQC. */
Kojto 90:cb3d968589d8 398 #define BM_PORT_PCRn_IRQC (0x000F0000U) /*!< Bit mask for PORT_PCRn_IRQC. */
Kojto 90:cb3d968589d8 399 #define BS_PORT_PCRn_IRQC (4U) /*!< Bit field size in bits for PORT_PCRn_IRQC. */
Kojto 90:cb3d968589d8 400
Kojto 90:cb3d968589d8 401 /*! @brief Read current value of the PORT_PCRn_IRQC field. */
Kojto 90:cb3d968589d8 402 #define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
Kojto 90:cb3d968589d8 403
Kojto 90:cb3d968589d8 404 /*! @brief Format value for bitfield PORT_PCRn_IRQC. */
Kojto 90:cb3d968589d8 405 #define BF_PORT_PCRn_IRQC(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_IRQC) & BM_PORT_PCRn_IRQC)
Kojto 90:cb3d968589d8 406
Kojto 90:cb3d968589d8 407 /*! @brief Set the IRQC field to a new value. */
Kojto 90:cb3d968589d8 408 #define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
Kojto 90:cb3d968589d8 409 /*@}*/
Kojto 90:cb3d968589d8 410
Kojto 90:cb3d968589d8 411 /*!
Kojto 90:cb3d968589d8 412 * @name Register PORT_PCRn, field ISF[24] (W1C)
Kojto 90:cb3d968589d8 413 *
Kojto 90:cb3d968589d8 414 * The pin interrupt configuration is valid in all digital pin muxing modes.
Kojto 90:cb3d968589d8 415 *
Kojto 90:cb3d968589d8 416 * Values:
Kojto 90:cb3d968589d8 417 * - 0 - Configured interrupt is not detected.
Kojto 90:cb3d968589d8 418 * - 1 - Configured interrupt is detected. If the pin is configured to generate
Kojto 90:cb3d968589d8 419 * a DMA request, then the corresponding flag will be cleared automatically
Kojto 90:cb3d968589d8 420 * at the completion of the requested DMA transfer. Otherwise, the flag
Kojto 90:cb3d968589d8 421 * remains set until a logic 1 is written to the flag. If the pin is configured for
Kojto 90:cb3d968589d8 422 * a level sensitive interrupt and the pin remains asserted, then the flag
Kojto 90:cb3d968589d8 423 * is set again immediately after it is cleared.
Kojto 90:cb3d968589d8 424 */
Kojto 90:cb3d968589d8 425 /*@{*/
Kojto 90:cb3d968589d8 426 #define BP_PORT_PCRn_ISF (24U) /*!< Bit position for PORT_PCRn_ISF. */
Kojto 90:cb3d968589d8 427 #define BM_PORT_PCRn_ISF (0x01000000U) /*!< Bit mask for PORT_PCRn_ISF. */
Kojto 90:cb3d968589d8 428 #define BS_PORT_PCRn_ISF (1U) /*!< Bit field size in bits for PORT_PCRn_ISF. */
Kojto 90:cb3d968589d8 429
Kojto 90:cb3d968589d8 430 /*! @brief Read current value of the PORT_PCRn_ISF field. */
Kojto 90:cb3d968589d8 431 #define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
Kojto 90:cb3d968589d8 432
Kojto 90:cb3d968589d8 433 /*! @brief Format value for bitfield PORT_PCRn_ISF. */
Kojto 90:cb3d968589d8 434 #define BF_PORT_PCRn_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ISF) & BM_PORT_PCRn_ISF)
Kojto 90:cb3d968589d8 435
Kojto 90:cb3d968589d8 436 /*! @brief Set the ISF field to a new value. */
Kojto 90:cb3d968589d8 437 #define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
Kojto 90:cb3d968589d8 438 /*@}*/
Kojto 90:cb3d968589d8 439
Kojto 90:cb3d968589d8 440 /*******************************************************************************
Kojto 90:cb3d968589d8 441 * HW_PORT_GPCLR - Global Pin Control Low Register
Kojto 90:cb3d968589d8 442 ******************************************************************************/
Kojto 90:cb3d968589d8 443
Kojto 90:cb3d968589d8 444 /*!
Kojto 90:cb3d968589d8 445 * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
Kojto 90:cb3d968589d8 446 *
Kojto 90:cb3d968589d8 447 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 448 *
Kojto 90:cb3d968589d8 449 * Only 32-bit writes are supported to this register.
Kojto 90:cb3d968589d8 450 */
Kojto 90:cb3d968589d8 451 typedef union _hw_port_gpclr
Kojto 90:cb3d968589d8 452 {
Kojto 90:cb3d968589d8 453 uint32_t U;
Kojto 90:cb3d968589d8 454 struct _hw_port_gpclr_bitfields
Kojto 90:cb3d968589d8 455 {
Kojto 90:cb3d968589d8 456 uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */
Kojto 90:cb3d968589d8 457 uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */
Kojto 90:cb3d968589d8 458 } B;
Kojto 90:cb3d968589d8 459 } hw_port_gpclr_t;
Kojto 90:cb3d968589d8 460
Kojto 90:cb3d968589d8 461 /*!
Kojto 90:cb3d968589d8 462 * @name Constants and macros for entire PORT_GPCLR register
Kojto 90:cb3d968589d8 463 */
Kojto 90:cb3d968589d8 464 /*@{*/
Kojto 90:cb3d968589d8 465 #define HW_PORT_GPCLR_ADDR(x) ((x) + 0x80U)
Kojto 90:cb3d968589d8 466
Kojto 90:cb3d968589d8 467 #define HW_PORT_GPCLR(x) (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
Kojto 90:cb3d968589d8 468 #define HW_PORT_GPCLR_RD(x) (HW_PORT_GPCLR(x).U)
Kojto 90:cb3d968589d8 469 #define HW_PORT_GPCLR_WR(x, v) (HW_PORT_GPCLR(x).U = (v))
Kojto 90:cb3d968589d8 470 /*@}*/
Kojto 90:cb3d968589d8 471
Kojto 90:cb3d968589d8 472 /*
Kojto 90:cb3d968589d8 473 * Constants & macros for individual PORT_GPCLR bitfields
Kojto 90:cb3d968589d8 474 */
Kojto 90:cb3d968589d8 475
Kojto 90:cb3d968589d8 476 /*!
Kojto 90:cb3d968589d8 477 * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
Kojto 90:cb3d968589d8 478 *
Kojto 90:cb3d968589d8 479 * Write value that is written to all Pin Control Registers bits [15:0] that are
Kojto 90:cb3d968589d8 480 * selected by GPWE.
Kojto 90:cb3d968589d8 481 */
Kojto 90:cb3d968589d8 482 /*@{*/
Kojto 90:cb3d968589d8 483 #define BP_PORT_GPCLR_GPWD (0U) /*!< Bit position for PORT_GPCLR_GPWD. */
Kojto 90:cb3d968589d8 484 #define BM_PORT_GPCLR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCLR_GPWD. */
Kojto 90:cb3d968589d8 485 #define BS_PORT_GPCLR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWD. */
Kojto 90:cb3d968589d8 486
Kojto 90:cb3d968589d8 487 /*! @brief Format value for bitfield PORT_GPCLR_GPWD. */
Kojto 90:cb3d968589d8 488 #define BF_PORT_GPCLR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWD) & BM_PORT_GPCLR_GPWD)
Kojto 90:cb3d968589d8 489
Kojto 90:cb3d968589d8 490 /*! @brief Set the GPWD field to a new value. */
Kojto 90:cb3d968589d8 491 #define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
Kojto 90:cb3d968589d8 492 /*@}*/
Kojto 90:cb3d968589d8 493
Kojto 90:cb3d968589d8 494 /*!
Kojto 90:cb3d968589d8 495 * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
Kojto 90:cb3d968589d8 496 *
Kojto 90:cb3d968589d8 497 * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
Kojto 90:cb3d968589d8 498 * the value in GPWD. If a selected Pin Control Register is locked then the write
Kojto 90:cb3d968589d8 499 * to that register is ignored.
Kojto 90:cb3d968589d8 500 *
Kojto 90:cb3d968589d8 501 * Values:
Kojto 90:cb3d968589d8 502 * - 0 - Corresponding Pin Control Register is not updated with the value in
Kojto 90:cb3d968589d8 503 * GPWD.
Kojto 90:cb3d968589d8 504 * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
Kojto 90:cb3d968589d8 505 */
Kojto 90:cb3d968589d8 506 /*@{*/
Kojto 90:cb3d968589d8 507 #define BP_PORT_GPCLR_GPWE (16U) /*!< Bit position for PORT_GPCLR_GPWE. */
Kojto 90:cb3d968589d8 508 #define BM_PORT_GPCLR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCLR_GPWE. */
Kojto 90:cb3d968589d8 509 #define BS_PORT_GPCLR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWE. */
Kojto 90:cb3d968589d8 510
Kojto 90:cb3d968589d8 511 /*! @brief Format value for bitfield PORT_GPCLR_GPWE. */
Kojto 90:cb3d968589d8 512 #define BF_PORT_GPCLR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWE) & BM_PORT_GPCLR_GPWE)
Kojto 90:cb3d968589d8 513
Kojto 90:cb3d968589d8 514 /*! @brief Set the GPWE field to a new value. */
Kojto 90:cb3d968589d8 515 #define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
Kojto 90:cb3d968589d8 516 /*@}*/
Kojto 90:cb3d968589d8 517
Kojto 90:cb3d968589d8 518 /*******************************************************************************
Kojto 90:cb3d968589d8 519 * HW_PORT_GPCHR - Global Pin Control High Register
Kojto 90:cb3d968589d8 520 ******************************************************************************/
Kojto 90:cb3d968589d8 521
Kojto 90:cb3d968589d8 522 /*!
Kojto 90:cb3d968589d8 523 * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
Kojto 90:cb3d968589d8 524 *
Kojto 90:cb3d968589d8 525 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 526 *
Kojto 90:cb3d968589d8 527 * Only 32-bit writes are supported to this register.
Kojto 90:cb3d968589d8 528 */
Kojto 90:cb3d968589d8 529 typedef union _hw_port_gpchr
Kojto 90:cb3d968589d8 530 {
Kojto 90:cb3d968589d8 531 uint32_t U;
Kojto 90:cb3d968589d8 532 struct _hw_port_gpchr_bitfields
Kojto 90:cb3d968589d8 533 {
Kojto 90:cb3d968589d8 534 uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */
Kojto 90:cb3d968589d8 535 uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */
Kojto 90:cb3d968589d8 536 } B;
Kojto 90:cb3d968589d8 537 } hw_port_gpchr_t;
Kojto 90:cb3d968589d8 538
Kojto 90:cb3d968589d8 539 /*!
Kojto 90:cb3d968589d8 540 * @name Constants and macros for entire PORT_GPCHR register
Kojto 90:cb3d968589d8 541 */
Kojto 90:cb3d968589d8 542 /*@{*/
Kojto 90:cb3d968589d8 543 #define HW_PORT_GPCHR_ADDR(x) ((x) + 0x84U)
Kojto 90:cb3d968589d8 544
Kojto 90:cb3d968589d8 545 #define HW_PORT_GPCHR(x) (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
Kojto 90:cb3d968589d8 546 #define HW_PORT_GPCHR_RD(x) (HW_PORT_GPCHR(x).U)
Kojto 90:cb3d968589d8 547 #define HW_PORT_GPCHR_WR(x, v) (HW_PORT_GPCHR(x).U = (v))
Kojto 90:cb3d968589d8 548 /*@}*/
Kojto 90:cb3d968589d8 549
Kojto 90:cb3d968589d8 550 /*
Kojto 90:cb3d968589d8 551 * Constants & macros for individual PORT_GPCHR bitfields
Kojto 90:cb3d968589d8 552 */
Kojto 90:cb3d968589d8 553
Kojto 90:cb3d968589d8 554 /*!
Kojto 90:cb3d968589d8 555 * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
Kojto 90:cb3d968589d8 556 *
Kojto 90:cb3d968589d8 557 * Write value that is written to all Pin Control Registers bits [15:0] that are
Kojto 90:cb3d968589d8 558 * selected by GPWE.
Kojto 90:cb3d968589d8 559 */
Kojto 90:cb3d968589d8 560 /*@{*/
Kojto 90:cb3d968589d8 561 #define BP_PORT_GPCHR_GPWD (0U) /*!< Bit position for PORT_GPCHR_GPWD. */
Kojto 90:cb3d968589d8 562 #define BM_PORT_GPCHR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCHR_GPWD. */
Kojto 90:cb3d968589d8 563 #define BS_PORT_GPCHR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWD. */
Kojto 90:cb3d968589d8 564
Kojto 90:cb3d968589d8 565 /*! @brief Format value for bitfield PORT_GPCHR_GPWD. */
Kojto 90:cb3d968589d8 566 #define BF_PORT_GPCHR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWD) & BM_PORT_GPCHR_GPWD)
Kojto 90:cb3d968589d8 567
Kojto 90:cb3d968589d8 568 /*! @brief Set the GPWD field to a new value. */
Kojto 90:cb3d968589d8 569 #define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
Kojto 90:cb3d968589d8 570 /*@}*/
Kojto 90:cb3d968589d8 571
Kojto 90:cb3d968589d8 572 /*!
Kojto 90:cb3d968589d8 573 * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
Kojto 90:cb3d968589d8 574 *
Kojto 90:cb3d968589d8 575 * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
Kojto 90:cb3d968589d8 576 * the value in GPWD. If a selected Pin Control Register is locked then the write
Kojto 90:cb3d968589d8 577 * to that register is ignored.
Kojto 90:cb3d968589d8 578 *
Kojto 90:cb3d968589d8 579 * Values:
Kojto 90:cb3d968589d8 580 * - 0 - Corresponding Pin Control Register is not updated with the value in
Kojto 90:cb3d968589d8 581 * GPWD.
Kojto 90:cb3d968589d8 582 * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
Kojto 90:cb3d968589d8 583 */
Kojto 90:cb3d968589d8 584 /*@{*/
Kojto 90:cb3d968589d8 585 #define BP_PORT_GPCHR_GPWE (16U) /*!< Bit position for PORT_GPCHR_GPWE. */
Kojto 90:cb3d968589d8 586 #define BM_PORT_GPCHR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCHR_GPWE. */
Kojto 90:cb3d968589d8 587 #define BS_PORT_GPCHR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWE. */
Kojto 90:cb3d968589d8 588
Kojto 90:cb3d968589d8 589 /*! @brief Format value for bitfield PORT_GPCHR_GPWE. */
Kojto 90:cb3d968589d8 590 #define BF_PORT_GPCHR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWE) & BM_PORT_GPCHR_GPWE)
Kojto 90:cb3d968589d8 591
Kojto 90:cb3d968589d8 592 /*! @brief Set the GPWE field to a new value. */
Kojto 90:cb3d968589d8 593 #define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
Kojto 90:cb3d968589d8 594 /*@}*/
Kojto 90:cb3d968589d8 595
Kojto 90:cb3d968589d8 596 /*******************************************************************************
Kojto 90:cb3d968589d8 597 * HW_PORT_ISFR - Interrupt Status Flag Register
Kojto 90:cb3d968589d8 598 ******************************************************************************/
Kojto 90:cb3d968589d8 599
Kojto 90:cb3d968589d8 600 /*!
Kojto 90:cb3d968589d8 601 * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
Kojto 90:cb3d968589d8 602 *
Kojto 90:cb3d968589d8 603 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 604 *
Kojto 90:cb3d968589d8 605 * The pin interrupt configuration is valid in all digital pin muxing modes. The
Kojto 90:cb3d968589d8 606 * Interrupt Status Flag for each pin is also visible in the corresponding Pin
Kojto 90:cb3d968589d8 607 * Control Register, and each flag can be cleared in either location.
Kojto 90:cb3d968589d8 608 */
Kojto 90:cb3d968589d8 609 typedef union _hw_port_isfr
Kojto 90:cb3d968589d8 610 {
Kojto 90:cb3d968589d8 611 uint32_t U;
Kojto 90:cb3d968589d8 612 struct _hw_port_isfr_bitfields
Kojto 90:cb3d968589d8 613 {
Kojto 90:cb3d968589d8 614 uint32_t ISF : 32; /*!< [31:0] Interrupt Status Flag */
Kojto 90:cb3d968589d8 615 } B;
Kojto 90:cb3d968589d8 616 } hw_port_isfr_t;
Kojto 90:cb3d968589d8 617
Kojto 90:cb3d968589d8 618 /*!
Kojto 90:cb3d968589d8 619 * @name Constants and macros for entire PORT_ISFR register
Kojto 90:cb3d968589d8 620 */
Kojto 90:cb3d968589d8 621 /*@{*/
Kojto 90:cb3d968589d8 622 #define HW_PORT_ISFR_ADDR(x) ((x) + 0xA0U)
Kojto 90:cb3d968589d8 623
Kojto 90:cb3d968589d8 624 #define HW_PORT_ISFR(x) (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
Kojto 90:cb3d968589d8 625 #define HW_PORT_ISFR_RD(x) (HW_PORT_ISFR(x).U)
Kojto 90:cb3d968589d8 626 #define HW_PORT_ISFR_WR(x, v) (HW_PORT_ISFR(x).U = (v))
Kojto 90:cb3d968589d8 627 #define HW_PORT_ISFR_SET(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) | (v)))
Kojto 90:cb3d968589d8 628 #define HW_PORT_ISFR_CLR(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 629 #define HW_PORT_ISFR_TOG(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 630 /*@}*/
Kojto 90:cb3d968589d8 631
Kojto 90:cb3d968589d8 632 /*
Kojto 90:cb3d968589d8 633 * Constants & macros for individual PORT_ISFR bitfields
Kojto 90:cb3d968589d8 634 */
Kojto 90:cb3d968589d8 635
Kojto 90:cb3d968589d8 636 /*!
Kojto 90:cb3d968589d8 637 * @name Register PORT_ISFR, field ISF[31:0] (W1C)
Kojto 90:cb3d968589d8 638 *
Kojto 90:cb3d968589d8 639 * Each bit in the field indicates the detection of the configured interrupt of
Kojto 90:cb3d968589d8 640 * the same number as the field.
Kojto 90:cb3d968589d8 641 *
Kojto 90:cb3d968589d8 642 * Values:
Kojto 90:cb3d968589d8 643 * - 0 - Configured interrupt is not detected.
Kojto 90:cb3d968589d8 644 * - 1 - Configured interrupt is detected. If the pin is configured to generate
Kojto 90:cb3d968589d8 645 * a DMA request, then the corresponding flag will be cleared automatically
Kojto 90:cb3d968589d8 646 * at the completion of the requested DMA transfer. Otherwise, the flag
Kojto 90:cb3d968589d8 647 * remains set until a logic 1 is written to the flag. If the pin is configured for
Kojto 90:cb3d968589d8 648 * a level sensitive interrupt and the pin remains asserted, then the flag
Kojto 90:cb3d968589d8 649 * is set again immediately after it is cleared.
Kojto 90:cb3d968589d8 650 */
Kojto 90:cb3d968589d8 651 /*@{*/
Kojto 90:cb3d968589d8 652 #define BP_PORT_ISFR_ISF (0U) /*!< Bit position for PORT_ISFR_ISF. */
Kojto 90:cb3d968589d8 653 #define BM_PORT_ISFR_ISF (0xFFFFFFFFU) /*!< Bit mask for PORT_ISFR_ISF. */
Kojto 90:cb3d968589d8 654 #define BS_PORT_ISFR_ISF (32U) /*!< Bit field size in bits for PORT_ISFR_ISF. */
Kojto 90:cb3d968589d8 655
Kojto 90:cb3d968589d8 656 /*! @brief Read current value of the PORT_ISFR_ISF field. */
Kojto 90:cb3d968589d8 657 #define BR_PORT_ISFR_ISF(x) (HW_PORT_ISFR(x).U)
Kojto 90:cb3d968589d8 658
Kojto 90:cb3d968589d8 659 /*! @brief Format value for bitfield PORT_ISFR_ISF. */
Kojto 90:cb3d968589d8 660 #define BF_PORT_ISFR_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_ISFR_ISF) & BM_PORT_ISFR_ISF)
Kojto 90:cb3d968589d8 661
Kojto 90:cb3d968589d8 662 /*! @brief Set the ISF field to a new value. */
Kojto 90:cb3d968589d8 663 #define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
Kojto 90:cb3d968589d8 664 /*@}*/
Kojto 90:cb3d968589d8 665
Kojto 90:cb3d968589d8 666 /*******************************************************************************
Kojto 90:cb3d968589d8 667 * HW_PORT_DFER - Digital Filter Enable Register
Kojto 90:cb3d968589d8 668 ******************************************************************************/
Kojto 90:cb3d968589d8 669
Kojto 90:cb3d968589d8 670 /*!
Kojto 90:cb3d968589d8 671 * @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
Kojto 90:cb3d968589d8 672 *
Kojto 90:cb3d968589d8 673 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 674 *
Kojto 90:cb3d968589d8 675 * The corresponding bit is read only for pins that do not support a digital
Kojto 90:cb3d968589d8 676 * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
Kojto 90:cb3d968589d8 677 * the pins that support digital filter. The digital filter configuration is valid
Kojto 90:cb3d968589d8 678 * in all digital pin muxing modes.
Kojto 90:cb3d968589d8 679 */
Kojto 90:cb3d968589d8 680 typedef union _hw_port_dfer
Kojto 90:cb3d968589d8 681 {
Kojto 90:cb3d968589d8 682 uint32_t U;
Kojto 90:cb3d968589d8 683 struct _hw_port_dfer_bitfields
Kojto 90:cb3d968589d8 684 {
Kojto 90:cb3d968589d8 685 uint32_t DFE : 32; /*!< [31:0] Digital Filter Enable */
Kojto 90:cb3d968589d8 686 } B;
Kojto 90:cb3d968589d8 687 } hw_port_dfer_t;
Kojto 90:cb3d968589d8 688
Kojto 90:cb3d968589d8 689 /*!
Kojto 90:cb3d968589d8 690 * @name Constants and macros for entire PORT_DFER register
Kojto 90:cb3d968589d8 691 */
Kojto 90:cb3d968589d8 692 /*@{*/
Kojto 90:cb3d968589d8 693 #define HW_PORT_DFER_ADDR(x) ((x) + 0xC0U)
Kojto 90:cb3d968589d8 694
Kojto 90:cb3d968589d8 695 #define HW_PORT_DFER(x) (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
Kojto 90:cb3d968589d8 696 #define HW_PORT_DFER_RD(x) (HW_PORT_DFER(x).U)
Kojto 90:cb3d968589d8 697 #define HW_PORT_DFER_WR(x, v) (HW_PORT_DFER(x).U = (v))
Kojto 90:cb3d968589d8 698 #define HW_PORT_DFER_SET(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) | (v)))
Kojto 90:cb3d968589d8 699 #define HW_PORT_DFER_CLR(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 700 #define HW_PORT_DFER_TOG(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 701 /*@}*/
Kojto 90:cb3d968589d8 702
Kojto 90:cb3d968589d8 703 /*
Kojto 90:cb3d968589d8 704 * Constants & macros for individual PORT_DFER bitfields
Kojto 90:cb3d968589d8 705 */
Kojto 90:cb3d968589d8 706
Kojto 90:cb3d968589d8 707 /*!
Kojto 90:cb3d968589d8 708 * @name Register PORT_DFER, field DFE[31:0] (RW)
Kojto 90:cb3d968589d8 709 *
Kojto 90:cb3d968589d8 710 * The digital filter configuration is valid in all digital pin muxing modes.
Kojto 90:cb3d968589d8 711 * The output of each digital filter is reset to zero at system reset and whenever
Kojto 90:cb3d968589d8 712 * the digital filter is disabled. Each bit in the field enables the digital
Kojto 90:cb3d968589d8 713 * filter of the same number as the field.
Kojto 90:cb3d968589d8 714 *
Kojto 90:cb3d968589d8 715 * Values:
Kojto 90:cb3d968589d8 716 * - 0 - Digital filter is disabled on the corresponding pin and output of the
Kojto 90:cb3d968589d8 717 * digital filter is reset to zero.
Kojto 90:cb3d968589d8 718 * - 1 - Digital filter is enabled on the corresponding pin, if the pin is
Kojto 90:cb3d968589d8 719 * configured as a digital input.
Kojto 90:cb3d968589d8 720 */
Kojto 90:cb3d968589d8 721 /*@{*/
Kojto 90:cb3d968589d8 722 #define BP_PORT_DFER_DFE (0U) /*!< Bit position for PORT_DFER_DFE. */
Kojto 90:cb3d968589d8 723 #define BM_PORT_DFER_DFE (0xFFFFFFFFU) /*!< Bit mask for PORT_DFER_DFE. */
Kojto 90:cb3d968589d8 724 #define BS_PORT_DFER_DFE (32U) /*!< Bit field size in bits for PORT_DFER_DFE. */
Kojto 90:cb3d968589d8 725
Kojto 90:cb3d968589d8 726 /*! @brief Read current value of the PORT_DFER_DFE field. */
Kojto 90:cb3d968589d8 727 #define BR_PORT_DFER_DFE(x) (HW_PORT_DFER(x).U)
Kojto 90:cb3d968589d8 728
Kojto 90:cb3d968589d8 729 /*! @brief Format value for bitfield PORT_DFER_DFE. */
Kojto 90:cb3d968589d8 730 #define BF_PORT_DFER_DFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFER_DFE) & BM_PORT_DFER_DFE)
Kojto 90:cb3d968589d8 731
Kojto 90:cb3d968589d8 732 /*! @brief Set the DFE field to a new value. */
Kojto 90:cb3d968589d8 733 #define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
Kojto 90:cb3d968589d8 734 /*@}*/
Kojto 90:cb3d968589d8 735
Kojto 90:cb3d968589d8 736 /*******************************************************************************
Kojto 90:cb3d968589d8 737 * HW_PORT_DFCR - Digital Filter Clock Register
Kojto 90:cb3d968589d8 738 ******************************************************************************/
Kojto 90:cb3d968589d8 739
Kojto 90:cb3d968589d8 740 /*!
Kojto 90:cb3d968589d8 741 * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
Kojto 90:cb3d968589d8 742 *
Kojto 90:cb3d968589d8 743 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 744 *
Kojto 90:cb3d968589d8 745 * This register is read only for ports that do not support a digital filter.
Kojto 90:cb3d968589d8 746 * The digital filter configuration is valid in all digital pin muxing modes.
Kojto 90:cb3d968589d8 747 */
Kojto 90:cb3d968589d8 748 typedef union _hw_port_dfcr
Kojto 90:cb3d968589d8 749 {
Kojto 90:cb3d968589d8 750 uint32_t U;
Kojto 90:cb3d968589d8 751 struct _hw_port_dfcr_bitfields
Kojto 90:cb3d968589d8 752 {
Kojto 90:cb3d968589d8 753 uint32_t CS : 1; /*!< [0] Clock Source */
Kojto 90:cb3d968589d8 754 uint32_t RESERVED0 : 31; /*!< [31:1] */
Kojto 90:cb3d968589d8 755 } B;
Kojto 90:cb3d968589d8 756 } hw_port_dfcr_t;
Kojto 90:cb3d968589d8 757
Kojto 90:cb3d968589d8 758 /*!
Kojto 90:cb3d968589d8 759 * @name Constants and macros for entire PORT_DFCR register
Kojto 90:cb3d968589d8 760 */
Kojto 90:cb3d968589d8 761 /*@{*/
Kojto 90:cb3d968589d8 762 #define HW_PORT_DFCR_ADDR(x) ((x) + 0xC4U)
Kojto 90:cb3d968589d8 763
Kojto 90:cb3d968589d8 764 #define HW_PORT_DFCR(x) (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
Kojto 90:cb3d968589d8 765 #define HW_PORT_DFCR_RD(x) (HW_PORT_DFCR(x).U)
Kojto 90:cb3d968589d8 766 #define HW_PORT_DFCR_WR(x, v) (HW_PORT_DFCR(x).U = (v))
Kojto 90:cb3d968589d8 767 #define HW_PORT_DFCR_SET(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) | (v)))
Kojto 90:cb3d968589d8 768 #define HW_PORT_DFCR_CLR(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 769 #define HW_PORT_DFCR_TOG(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 770 /*@}*/
Kojto 90:cb3d968589d8 771
Kojto 90:cb3d968589d8 772 /*
Kojto 90:cb3d968589d8 773 * Constants & macros for individual PORT_DFCR bitfields
Kojto 90:cb3d968589d8 774 */
Kojto 90:cb3d968589d8 775
Kojto 90:cb3d968589d8 776 /*!
Kojto 90:cb3d968589d8 777 * @name Register PORT_DFCR, field CS[0] (RW)
Kojto 90:cb3d968589d8 778 *
Kojto 90:cb3d968589d8 779 * The digital filter configuration is valid in all digital pin muxing modes.
Kojto 90:cb3d968589d8 780 * Configures the clock source for the digital input filters. Changing the filter
Kojto 90:cb3d968589d8 781 * clock source must be done only when all digital filters are disabled.
Kojto 90:cb3d968589d8 782 *
Kojto 90:cb3d968589d8 783 * Values:
Kojto 90:cb3d968589d8 784 * - 0 - Digital filters are clocked by the bus clock.
Kojto 90:cb3d968589d8 785 * - 1 - Digital filters are clocked by the 1 kHz LPO clock.
Kojto 90:cb3d968589d8 786 */
Kojto 90:cb3d968589d8 787 /*@{*/
Kojto 90:cb3d968589d8 788 #define BP_PORT_DFCR_CS (0U) /*!< Bit position for PORT_DFCR_CS. */
Kojto 90:cb3d968589d8 789 #define BM_PORT_DFCR_CS (0x00000001U) /*!< Bit mask for PORT_DFCR_CS. */
Kojto 90:cb3d968589d8 790 #define BS_PORT_DFCR_CS (1U) /*!< Bit field size in bits for PORT_DFCR_CS. */
Kojto 90:cb3d968589d8 791
Kojto 90:cb3d968589d8 792 /*! @brief Read current value of the PORT_DFCR_CS field. */
Kojto 90:cb3d968589d8 793 #define BR_PORT_DFCR_CS(x) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
Kojto 90:cb3d968589d8 794
Kojto 90:cb3d968589d8 795 /*! @brief Format value for bitfield PORT_DFCR_CS. */
Kojto 90:cb3d968589d8 796 #define BF_PORT_DFCR_CS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFCR_CS) & BM_PORT_DFCR_CS)
Kojto 90:cb3d968589d8 797
Kojto 90:cb3d968589d8 798 /*! @brief Set the CS field to a new value. */
Kojto 90:cb3d968589d8 799 #define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
Kojto 90:cb3d968589d8 800 /*@}*/
Kojto 90:cb3d968589d8 801
Kojto 90:cb3d968589d8 802 /*******************************************************************************
Kojto 90:cb3d968589d8 803 * HW_PORT_DFWR - Digital Filter Width Register
Kojto 90:cb3d968589d8 804 ******************************************************************************/
Kojto 90:cb3d968589d8 805
Kojto 90:cb3d968589d8 806 /*!
Kojto 90:cb3d968589d8 807 * @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
Kojto 90:cb3d968589d8 808 *
Kojto 90:cb3d968589d8 809 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 810 *
Kojto 90:cb3d968589d8 811 * This register is read only for ports that do not support a digital filter.
Kojto 90:cb3d968589d8 812 * The digital filter configuration is valid in all digital pin muxing modes.
Kojto 90:cb3d968589d8 813 */
Kojto 90:cb3d968589d8 814 typedef union _hw_port_dfwr
Kojto 90:cb3d968589d8 815 {
Kojto 90:cb3d968589d8 816 uint32_t U;
Kojto 90:cb3d968589d8 817 struct _hw_port_dfwr_bitfields
Kojto 90:cb3d968589d8 818 {
Kojto 90:cb3d968589d8 819 uint32_t FILT : 5; /*!< [4:0] Filter Length */
Kojto 90:cb3d968589d8 820 uint32_t RESERVED0 : 27; /*!< [31:5] */
Kojto 90:cb3d968589d8 821 } B;
Kojto 90:cb3d968589d8 822 } hw_port_dfwr_t;
Kojto 90:cb3d968589d8 823
Kojto 90:cb3d968589d8 824 /*!
Kojto 90:cb3d968589d8 825 * @name Constants and macros for entire PORT_DFWR register
Kojto 90:cb3d968589d8 826 */
Kojto 90:cb3d968589d8 827 /*@{*/
Kojto 90:cb3d968589d8 828 #define HW_PORT_DFWR_ADDR(x) ((x) + 0xC8U)
Kojto 90:cb3d968589d8 829
Kojto 90:cb3d968589d8 830 #define HW_PORT_DFWR(x) (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
Kojto 90:cb3d968589d8 831 #define HW_PORT_DFWR_RD(x) (HW_PORT_DFWR(x).U)
Kojto 90:cb3d968589d8 832 #define HW_PORT_DFWR_WR(x, v) (HW_PORT_DFWR(x).U = (v))
Kojto 90:cb3d968589d8 833 #define HW_PORT_DFWR_SET(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) | (v)))
Kojto 90:cb3d968589d8 834 #define HW_PORT_DFWR_CLR(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 835 #define HW_PORT_DFWR_TOG(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 836 /*@}*/
Kojto 90:cb3d968589d8 837
Kojto 90:cb3d968589d8 838 /*
Kojto 90:cb3d968589d8 839 * Constants & macros for individual PORT_DFWR bitfields
Kojto 90:cb3d968589d8 840 */
Kojto 90:cb3d968589d8 841
Kojto 90:cb3d968589d8 842 /*!
Kojto 90:cb3d968589d8 843 * @name Register PORT_DFWR, field FILT[4:0] (RW)
Kojto 90:cb3d968589d8 844 *
Kojto 90:cb3d968589d8 845 * The digital filter configuration is valid in all digital pin muxing modes.
Kojto 90:cb3d968589d8 846 * Configures the maximum size of the glitches, in clock cycles, that the digital
Kojto 90:cb3d968589d8 847 * filter absorbs for the enabled digital filters. Glitches that are longer than
Kojto 90:cb3d968589d8 848 * this register setting will pass through the digital filter, and glitches that
Kojto 90:cb3d968589d8 849 * are equal to or less than this register setting are filtered. Changing the
Kojto 90:cb3d968589d8 850 * filter length must be done only after all filters are disabled.
Kojto 90:cb3d968589d8 851 */
Kojto 90:cb3d968589d8 852 /*@{*/
Kojto 90:cb3d968589d8 853 #define BP_PORT_DFWR_FILT (0U) /*!< Bit position for PORT_DFWR_FILT. */
Kojto 90:cb3d968589d8 854 #define BM_PORT_DFWR_FILT (0x0000001FU) /*!< Bit mask for PORT_DFWR_FILT. */
Kojto 90:cb3d968589d8 855 #define BS_PORT_DFWR_FILT (5U) /*!< Bit field size in bits for PORT_DFWR_FILT. */
Kojto 90:cb3d968589d8 856
Kojto 90:cb3d968589d8 857 /*! @brief Read current value of the PORT_DFWR_FILT field. */
Kojto 90:cb3d968589d8 858 #define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
Kojto 90:cb3d968589d8 859
Kojto 90:cb3d968589d8 860 /*! @brief Format value for bitfield PORT_DFWR_FILT. */
Kojto 90:cb3d968589d8 861 #define BF_PORT_DFWR_FILT(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFWR_FILT) & BM_PORT_DFWR_FILT)
Kojto 90:cb3d968589d8 862
Kojto 90:cb3d968589d8 863 /*! @brief Set the FILT field to a new value. */
Kojto 90:cb3d968589d8 864 #define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
Kojto 90:cb3d968589d8 865 /*@}*/
Kojto 90:cb3d968589d8 866
Kojto 90:cb3d968589d8 867 /*******************************************************************************
Kojto 90:cb3d968589d8 868 * hw_port_t - module struct
Kojto 90:cb3d968589d8 869 ******************************************************************************/
Kojto 90:cb3d968589d8 870 /*!
Kojto 90:cb3d968589d8 871 * @brief All PORT module registers.
Kojto 90:cb3d968589d8 872 */
Kojto 90:cb3d968589d8 873 #pragma pack(1)
Kojto 90:cb3d968589d8 874 typedef struct _hw_port
Kojto 90:cb3d968589d8 875 {
Kojto 90:cb3d968589d8 876 __IO hw_port_pcrn_t PCRn[32]; /*!< [0x0] Pin Control Register n */
Kojto 90:cb3d968589d8 877 __O hw_port_gpclr_t GPCLR; /*!< [0x80] Global Pin Control Low Register */
Kojto 90:cb3d968589d8 878 __O hw_port_gpchr_t GPCHR; /*!< [0x84] Global Pin Control High Register */
Kojto 90:cb3d968589d8 879 uint8_t _reserved0[24];
Kojto 90:cb3d968589d8 880 __IO hw_port_isfr_t ISFR; /*!< [0xA0] Interrupt Status Flag Register */
Kojto 90:cb3d968589d8 881 uint8_t _reserved1[28];
Kojto 90:cb3d968589d8 882 __IO hw_port_dfer_t DFER; /*!< [0xC0] Digital Filter Enable Register */
Kojto 90:cb3d968589d8 883 __IO hw_port_dfcr_t DFCR; /*!< [0xC4] Digital Filter Clock Register */
Kojto 90:cb3d968589d8 884 __IO hw_port_dfwr_t DFWR; /*!< [0xC8] Digital Filter Width Register */
Kojto 90:cb3d968589d8 885 } hw_port_t;
Kojto 90:cb3d968589d8 886 #pragma pack()
Kojto 90:cb3d968589d8 887
Kojto 90:cb3d968589d8 888 /*! @brief Macro to access all PORT registers. */
Kojto 90:cb3d968589d8 889 /*! @param x PORT module instance base address. */
Kojto 90:cb3d968589d8 890 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 891 * use the '&' operator, like <code>&HW_PORT(PORTA_BASE)</code>. */
Kojto 90:cb3d968589d8 892 #define HW_PORT(x) (*(hw_port_t *)(x))
Kojto 90:cb3d968589d8 893
Kojto 90:cb3d968589d8 894 #endif /* __HW_PORT_REGISTERS_H__ */
Kojto 90:cb3d968589d8 895 /* EOF */