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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pdb.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:: Kojto
Date:: Wed Aug 05 13:16:35 2015 +0100
Revision:: 104:b9ad9a133dc7
Parent:: 90:cb3d968589d8

Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/*
Kojto	90:cb3d968589d8	2	** ###################################################################
Kojto	90:cb3d968589d8	3	** Compilers: Keil ARM C/C++ Compiler
Kojto	90:cb3d968589d8	4	** Freescale C/C++ for Embedded ARM
Kojto	90:cb3d968589d8	5	** GNU C Compiler
Kojto	90:cb3d968589d8	6	** IAR ANSI C/C++ Compiler for ARM
Kojto	90:cb3d968589d8	7	**
Kojto	90:cb3d968589d8	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto	90:cb3d968589d8	9	** Version: rev. 2.5, 2014-02-10
Kojto	90:cb3d968589d8	10	** Build: b140604
Kojto	90:cb3d968589d8	11	**
Kojto	90:cb3d968589d8	12	** Abstract:
Kojto	90:cb3d968589d8	13	** Extension to the CMSIS register access layer header.
Kojto	90:cb3d968589d8	14	**
Kojto	90:cb3d968589d8	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto	90:cb3d968589d8	16	** All rights reserved.
Kojto	90:cb3d968589d8	17	**
Kojto	90:cb3d968589d8	18	** Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	19	** are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	20	**
Kojto	90:cb3d968589d8	21	** o Redistributions of source code must retain the above copyright notice, this list
Kojto	90:cb3d968589d8	22	** of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	**
Kojto	90:cb3d968589d8	24	** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto	90:cb3d968589d8	25	** list of conditions and the following disclaimer in the documentation and/or
Kojto	90:cb3d968589d8	26	** other materials provided with the distribution.
Kojto	90:cb3d968589d8	27	**
Kojto	90:cb3d968589d8	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto	90:cb3d968589d8	29	** contributors may be used to endorse or promote products derived from this
Kojto	90:cb3d968589d8	30	** software without specific prior written permission.
Kojto	90:cb3d968589d8	31	**
Kojto	90:cb3d968589d8	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	90:cb3d968589d8	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	90:cb3d968589d8	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	90:cb3d968589d8	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	90:cb3d968589d8	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	90:cb3d968589d8	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	90:cb3d968589d8	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	90:cb3d968589d8	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	90:cb3d968589d8	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	42	**
Kojto	90:cb3d968589d8	43	** http: www.freescale.com
Kojto	90:cb3d968589d8	44	** mail: support@freescale.com
Kojto	90:cb3d968589d8	45	**
Kojto	90:cb3d968589d8	46	** Revisions:
Kojto	90:cb3d968589d8	47	** - rev. 1.0 (2013-08-12)
Kojto	90:cb3d968589d8	48	** Initial version.
Kojto	90:cb3d968589d8	49	** - rev. 2.0 (2013-10-29)
Kojto	90:cb3d968589d8	50	** Register accessor macros added to the memory map.
Kojto	90:cb3d968589d8	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto	90:cb3d968589d8	52	** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto	90:cb3d968589d8	53	** System initialization updated.
Kojto	90:cb3d968589d8	54	** MCG - registers updated.
Kojto	90:cb3d968589d8	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto	90:cb3d968589d8	56	** - rev. 2.1 (2013-10-30)
Kojto	90:cb3d968589d8	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto	90:cb3d968589d8	58	** - rev. 2.2 (2013-12-09)
Kojto	90:cb3d968589d8	59	** DMA - EARS register removed.
Kojto	90:cb3d968589d8	60	** AIPS0, AIPS1 - MPRA register updated.
Kojto	90:cb3d968589d8	61	** - rev. 2.3 (2014-01-24)
Kojto	90:cb3d968589d8	62	** Update according to reference manual rev. 2
Kojto	90:cb3d968589d8	63	** ENET, MCG, MCM, SIM, USB - registers updated
Kojto	90:cb3d968589d8	64	** - rev. 2.4 (2014-02-10)
Kojto	90:cb3d968589d8	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	67	** - rev. 2.5 (2014-02-10)
Kojto	90:cb3d968589d8	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto	90:cb3d968589d8	71	**
Kojto	90:cb3d968589d8	72	** ###################################################################
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/*
Kojto	90:cb3d968589d8	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto	90:cb3d968589d8	77	*
Kojto	90:cb3d968589d8	78	* This file was generated automatically and any changes may be lost.
Kojto	90:cb3d968589d8	79	*/
Kojto	90:cb3d968589d8	80	#ifndef __HW_PDB_REGISTERS_H__
Kojto	90:cb3d968589d8	81	#define __HW_PDB_REGISTERS_H__
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	#include "MK64F12.h"
Kojto	90:cb3d968589d8	84	#include "fsl_bitaccess.h"
Kojto	90:cb3d968589d8	85
Kojto	90:cb3d968589d8	86	/*
Kojto	90:cb3d968589d8	87	* MK64F12 PDB
Kojto	90:cb3d968589d8	88	*
Kojto	90:cb3d968589d8	89	* Programmable Delay Block
Kojto	90:cb3d968589d8	90	*
Kojto	90:cb3d968589d8	91	* Registers defined in this header file:
Kojto	90:cb3d968589d8	92	* - HW_PDB_SC - Status and Control register
Kojto	90:cb3d968589d8	93	* - HW_PDB_MOD - Modulus register
Kojto	90:cb3d968589d8	94	* - HW_PDB_CNT - Counter register
Kojto	90:cb3d968589d8	95	* - HW_PDB_IDLY - Interrupt Delay register
Kojto	90:cb3d968589d8	96	* - HW_PDB_CHnC1 - Channel n Control register 1
Kojto	90:cb3d968589d8	97	* - HW_PDB_CHnS - Channel n Status register
Kojto	90:cb3d968589d8	98	* - HW_PDB_CHnDLY0 - Channel n Delay 0 register
Kojto	90:cb3d968589d8	99	* - HW_PDB_CHnDLY1 - Channel n Delay 1 register
Kojto	90:cb3d968589d8	100	* - HW_PDB_DACINTCn - DAC Interval Trigger n Control register
Kojto	90:cb3d968589d8	101	* - HW_PDB_DACINTn - DAC Interval n register
Kojto	90:cb3d968589d8	102	* - HW_PDB_POEN - Pulse-Out n Enable register
Kojto	90:cb3d968589d8	103	* - HW_PDB_POnDLY - Pulse-Out n Delay register
Kojto	90:cb3d968589d8	104	*
Kojto	90:cb3d968589d8	105	* - hw_pdb_t - Struct containing all module registers.
Kojto	90:cb3d968589d8	106	*/
Kojto	90:cb3d968589d8	107
Kojto	90:cb3d968589d8	108	#define HW_PDB_INSTANCE_COUNT (1U) /!< Number of instances of the PDB module. /
Kojto	90:cb3d968589d8	109
Kojto	90:cb3d968589d8	110	/*******************************************************************************
Kojto	90:cb3d968589d8	111	* HW_PDB_SC - Status and Control register
Kojto	90:cb3d968589d8	112	******************************************************************************/
Kojto	90:cb3d968589d8	113
Kojto	90:cb3d968589d8	114	/*!
Kojto	90:cb3d968589d8	115	* @brief HW_PDB_SC - Status and Control register (RW)
Kojto	90:cb3d968589d8	116	*
Kojto	90:cb3d968589d8	117	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	118	*/
Kojto	90:cb3d968589d8	119	typedef union _hw_pdb_sc
Kojto	90:cb3d968589d8	120	{
Kojto	90:cb3d968589d8	121	uint32_t U;
Kojto	90:cb3d968589d8	122	struct _hw_pdb_sc_bitfields
Kojto	90:cb3d968589d8	123	{
Kojto	90:cb3d968589d8	124	uint32_t LDOK : 1; /!< [0] Load OK /
Kojto	90:cb3d968589d8	125	uint32_t CONT : 1; /!< [1] Continuous Mode Enable /
Kojto	90:cb3d968589d8	126	uint32_t MULT : 2; /*!< [3:2] Multiplication Factor Select for
Kojto	90:cb3d968589d8	127	* Prescaler */
Kojto	90:cb3d968589d8	128	uint32_t RESERVED0 : 1; /!< [4] /
Kojto	90:cb3d968589d8	129	uint32_t PDBIE : 1; /!< [5] PDB Interrupt Enable /
Kojto	90:cb3d968589d8	130	uint32_t PDBIF : 1; /!< [6] PDB Interrupt Flag /
Kojto	90:cb3d968589d8	131	uint32_t PDBEN : 1; /!< [7] PDB Enable /
Kojto	90:cb3d968589d8	132	uint32_t TRGSEL : 4; /!< [11:8] Trigger Input Source Select /
Kojto	90:cb3d968589d8	133	uint32_t PRESCALER : 3; /!< [14:12] Prescaler Divider Select /
Kojto	90:cb3d968589d8	134	uint32_t DMAEN : 1; /!< [15] DMA Enable /
Kojto	90:cb3d968589d8	135	uint32_t SWTRIG : 1; /!< [16] Software Trigger /
Kojto	90:cb3d968589d8	136	uint32_t PDBEIE : 1; /!< [17] PDB Sequence Error Interrupt Enable /
Kojto	90:cb3d968589d8	137	uint32_t LDMOD : 2; /!< [19:18] Load Mode Select /
Kojto	90:cb3d968589d8	138	uint32_t RESERVED1 : 12; /!< [31:20] /
Kojto	90:cb3d968589d8	139	} B;
Kojto	90:cb3d968589d8	140	} hw_pdb_sc_t;
Kojto	90:cb3d968589d8	141
Kojto	90:cb3d968589d8	142	/*!
Kojto	90:cb3d968589d8	143	* @name Constants and macros for entire PDB_SC register
Kojto	90:cb3d968589d8	144	*/
Kojto	90:cb3d968589d8	145	/@{/
Kojto	90:cb3d968589d8	146	#define HW_PDB_SC_ADDR(x) ((x) + 0x0U)
Kojto	90:cb3d968589d8	147
Kojto	90:cb3d968589d8	148	#define HW_PDB_SC(x) ((__IO hw_pdb_sc_t ) HW_PDB_SC_ADDR(x))
Kojto	90:cb3d968589d8	149	#define HW_PDB_SC_RD(x) (HW_PDB_SC(x).U)
Kojto	90:cb3d968589d8	150	#define HW_PDB_SC_WR(x, v) (HW_PDB_SC(x).U = (v))
Kojto	90:cb3d968589d8	151	#define HW_PDB_SC_SET(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) \| (v)))
Kojto	90:cb3d968589d8	152	#define HW_PDB_SC_CLR(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	153	#define HW_PDB_SC_TOG(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	154	/@}/
Kojto	90:cb3d968589d8	155
Kojto	90:cb3d968589d8	156	/*
Kojto	90:cb3d968589d8	157	* Constants & macros for individual PDB_SC bitfields
Kojto	90:cb3d968589d8	158	*/
Kojto	90:cb3d968589d8	159
Kojto	90:cb3d968589d8	160	/*!
Kojto	90:cb3d968589d8	161	* @name Register PDB_SC, field LDOK[0] (RW)
Kojto	90:cb3d968589d8	162	*
Kojto	90:cb3d968589d8	163	* Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
Kojto	90:cb3d968589d8	164	* DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
Kojto	90:cb3d968589d8	165	* CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
Kojto	90:cb3d968589d8	166	* written to the LDOK field, the values in the buffers of above registers are
Kojto	90:cb3d968589d8	167	* not effective and the buffers cannot be written until the values in buffers are
Kojto	90:cb3d968589d8	168	* loaded into their internal registers. LDOK can be written only when PDBEN is
Kojto	90:cb3d968589d8	169	* set or it can be written at the same time with PDBEN being written to 1. It is
Kojto	90:cb3d968589d8	170	* automatically cleared when the values in buffers are loaded into the internal
Kojto	90:cb3d968589d8	171	* registers or the PDBEN is cleared. Writing 0 to it has no effect.
Kojto	90:cb3d968589d8	172	*/
Kojto	90:cb3d968589d8	173	/@{/
Kojto	90:cb3d968589d8	174	#define BP_PDB_SC_LDOK (0U) /!< Bit position for PDB_SC_LDOK. /
Kojto	90:cb3d968589d8	175	#define BM_PDB_SC_LDOK (0x00000001U) /!< Bit mask for PDB_SC_LDOK. /
Kojto	90:cb3d968589d8	176	#define BS_PDB_SC_LDOK (1U) /!< Bit field size in bits for PDB_SC_LDOK. /
Kojto	90:cb3d968589d8	177
Kojto	90:cb3d968589d8	178	/! @brief Read current value of the PDB_SC_LDOK field. /
Kojto	90:cb3d968589d8	179	#define BR_PDB_SC_LDOK(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK))
Kojto	90:cb3d968589d8	180
Kojto	90:cb3d968589d8	181	/! @brief Format value for bitfield PDB_SC_LDOK. /
Kojto	90:cb3d968589d8	182	#define BF_PDB_SC_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDOK) & BM_PDB_SC_LDOK)
Kojto	90:cb3d968589d8	183
Kojto	90:cb3d968589d8	184	/! @brief Set the LDOK field to a new value. /
Kojto	90:cb3d968589d8	185	#define BW_PDB_SC_LDOK(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK) = (v))
Kojto	90:cb3d968589d8	186	/@}/
Kojto	90:cb3d968589d8	187
Kojto	90:cb3d968589d8	188	/*!
Kojto	90:cb3d968589d8	189	* @name Register PDB_SC, field CONT[1] (RW)
Kojto	90:cb3d968589d8	190	*
Kojto	90:cb3d968589d8	191	* Enables the PDB operation in Continuous mode.
Kojto	90:cb3d968589d8	192	*
Kojto	90:cb3d968589d8	193	* Values:
Kojto	90:cb3d968589d8	194	* - 0 - PDB operation in One-Shot mode
Kojto	90:cb3d968589d8	195	* - 1 - PDB operation in Continuous mode
Kojto	90:cb3d968589d8	196	*/
Kojto	90:cb3d968589d8	197	/@{/
Kojto	90:cb3d968589d8	198	#define BP_PDB_SC_CONT (1U) /!< Bit position for PDB_SC_CONT. /
Kojto	90:cb3d968589d8	199	#define BM_PDB_SC_CONT (0x00000002U) /!< Bit mask for PDB_SC_CONT. /
Kojto	90:cb3d968589d8	200	#define BS_PDB_SC_CONT (1U) /!< Bit field size in bits for PDB_SC_CONT. /
Kojto	90:cb3d968589d8	201
Kojto	90:cb3d968589d8	202	/! @brief Read current value of the PDB_SC_CONT field. /
Kojto	90:cb3d968589d8	203	#define BR_PDB_SC_CONT(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT))
Kojto	90:cb3d968589d8	204
Kojto	90:cb3d968589d8	205	/! @brief Format value for bitfield PDB_SC_CONT. /
Kojto	90:cb3d968589d8	206	#define BF_PDB_SC_CONT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_CONT) & BM_PDB_SC_CONT)
Kojto	90:cb3d968589d8	207
Kojto	90:cb3d968589d8	208	/! @brief Set the CONT field to a new value. /
Kojto	90:cb3d968589d8	209	#define BW_PDB_SC_CONT(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT) = (v))
Kojto	90:cb3d968589d8	210	/@}/
Kojto	90:cb3d968589d8	211
Kojto	90:cb3d968589d8	212	/*!
Kojto	90:cb3d968589d8	213	* @name Register PDB_SC, field MULT[3:2] (RW)
Kojto	90:cb3d968589d8	214	*
Kojto	90:cb3d968589d8	215	* Selects the multiplication factor of the prescaler divider for the counter
Kojto	90:cb3d968589d8	216	* clock.
Kojto	90:cb3d968589d8	217	*
Kojto	90:cb3d968589d8	218	* Values:
Kojto	90:cb3d968589d8	219	* - 00 - Multiplication factor is 1.
Kojto	90:cb3d968589d8	220	* - 01 - Multiplication factor is 10.
Kojto	90:cb3d968589d8	221	* - 10 - Multiplication factor is 20.
Kojto	90:cb3d968589d8	222	* - 11 - Multiplication factor is 40.
Kojto	90:cb3d968589d8	223	*/
Kojto	90:cb3d968589d8	224	/@{/
Kojto	90:cb3d968589d8	225	#define BP_PDB_SC_MULT (2U) /!< Bit position for PDB_SC_MULT. /
Kojto	90:cb3d968589d8	226	#define BM_PDB_SC_MULT (0x0000000CU) /!< Bit mask for PDB_SC_MULT. /
Kojto	90:cb3d968589d8	227	#define BS_PDB_SC_MULT (2U) /!< Bit field size in bits for PDB_SC_MULT. /
Kojto	90:cb3d968589d8	228
Kojto	90:cb3d968589d8	229	/! @brief Read current value of the PDB_SC_MULT field. /
Kojto	90:cb3d968589d8	230	#define BR_PDB_SC_MULT(x) (HW_PDB_SC(x).B.MULT)
Kojto	90:cb3d968589d8	231
Kojto	90:cb3d968589d8	232	/! @brief Format value for bitfield PDB_SC_MULT. /
Kojto	90:cb3d968589d8	233	#define BF_PDB_SC_MULT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_MULT) & BM_PDB_SC_MULT)
Kojto	90:cb3d968589d8	234
Kojto	90:cb3d968589d8	235	/! @brief Set the MULT field to a new value. /
Kojto	90:cb3d968589d8	236	#define BW_PDB_SC_MULT(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_MULT) \| BF_PDB_SC_MULT(v)))
Kojto	90:cb3d968589d8	237	/@}/
Kojto	90:cb3d968589d8	238
Kojto	90:cb3d968589d8	239	/*!
Kojto	90:cb3d968589d8	240	* @name Register PDB_SC, field PDBIE[5] (RW)
Kojto	90:cb3d968589d8	241	*
Kojto	90:cb3d968589d8	242	* Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
Kojto	90:cb3d968589d8	243	* generates a PDB interrupt.
Kojto	90:cb3d968589d8	244	*
Kojto	90:cb3d968589d8	245	* Values:
Kojto	90:cb3d968589d8	246	* - 0 - PDB interrupt disabled.
Kojto	90:cb3d968589d8	247	* - 1 - PDB interrupt enabled.
Kojto	90:cb3d968589d8	248	*/
Kojto	90:cb3d968589d8	249	/@{/
Kojto	90:cb3d968589d8	250	#define BP_PDB_SC_PDBIE (5U) /!< Bit position for PDB_SC_PDBIE. /
Kojto	90:cb3d968589d8	251	#define BM_PDB_SC_PDBIE (0x00000020U) /!< Bit mask for PDB_SC_PDBIE. /
Kojto	90:cb3d968589d8	252	#define BS_PDB_SC_PDBIE (1U) /!< Bit field size in bits for PDB_SC_PDBIE. /
Kojto	90:cb3d968589d8	253
Kojto	90:cb3d968589d8	254	/! @brief Read current value of the PDB_SC_PDBIE field. /
Kojto	90:cb3d968589d8	255	#define BR_PDB_SC_PDBIE(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE))
Kojto	90:cb3d968589d8	256
Kojto	90:cb3d968589d8	257	/! @brief Format value for bitfield PDB_SC_PDBIE. /
Kojto	90:cb3d968589d8	258	#define BF_PDB_SC_PDBIE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIE) & BM_PDB_SC_PDBIE)
Kojto	90:cb3d968589d8	259
Kojto	90:cb3d968589d8	260	/! @brief Set the PDBIE field to a new value. /
Kojto	90:cb3d968589d8	261	#define BW_PDB_SC_PDBIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE) = (v))
Kojto	90:cb3d968589d8	262	/@}/
Kojto	90:cb3d968589d8	263
Kojto	90:cb3d968589d8	264	/*!
Kojto	90:cb3d968589d8	265	* @name Register PDB_SC, field PDBIF[6] (RW)
Kojto	90:cb3d968589d8	266	*
Kojto	90:cb3d968589d8	267	* This field is set when the counter value is equal to the IDLY register.
Kojto	90:cb3d968589d8	268	* Writing zero clears this field.
Kojto	90:cb3d968589d8	269	*/
Kojto	90:cb3d968589d8	270	/@{/
Kojto	90:cb3d968589d8	271	#define BP_PDB_SC_PDBIF (6U) /!< Bit position for PDB_SC_PDBIF. /
Kojto	90:cb3d968589d8	272	#define BM_PDB_SC_PDBIF (0x00000040U) /!< Bit mask for PDB_SC_PDBIF. /
Kojto	90:cb3d968589d8	273	#define BS_PDB_SC_PDBIF (1U) /!< Bit field size in bits for PDB_SC_PDBIF. /
Kojto	90:cb3d968589d8	274
Kojto	90:cb3d968589d8	275	/! @brief Read current value of the PDB_SC_PDBIF field. /
Kojto	90:cb3d968589d8	276	#define BR_PDB_SC_PDBIF(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF))
Kojto	90:cb3d968589d8	277
Kojto	90:cb3d968589d8	278	/! @brief Format value for bitfield PDB_SC_PDBIF. /
Kojto	90:cb3d968589d8	279	#define BF_PDB_SC_PDBIF(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIF) & BM_PDB_SC_PDBIF)
Kojto	90:cb3d968589d8	280
Kojto	90:cb3d968589d8	281	/! @brief Set the PDBIF field to a new value. /
Kojto	90:cb3d968589d8	282	#define BW_PDB_SC_PDBIF(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF) = (v))
Kojto	90:cb3d968589d8	283	/@}/
Kojto	90:cb3d968589d8	284
Kojto	90:cb3d968589d8	285	/*!
Kojto	90:cb3d968589d8	286	* @name Register PDB_SC, field PDBEN[7] (RW)
Kojto	90:cb3d968589d8	287	*
Kojto	90:cb3d968589d8	288	* Values:
Kojto	90:cb3d968589d8	289	* - 0 - PDB disabled. Counter is off.
Kojto	90:cb3d968589d8	290	* - 1 - PDB enabled.
Kojto	90:cb3d968589d8	291	*/
Kojto	90:cb3d968589d8	292	/@{/
Kojto	90:cb3d968589d8	293	#define BP_PDB_SC_PDBEN (7U) /!< Bit position for PDB_SC_PDBEN. /
Kojto	90:cb3d968589d8	294	#define BM_PDB_SC_PDBEN (0x00000080U) /!< Bit mask for PDB_SC_PDBEN. /
Kojto	90:cb3d968589d8	295	#define BS_PDB_SC_PDBEN (1U) /!< Bit field size in bits for PDB_SC_PDBEN. /
Kojto	90:cb3d968589d8	296
Kojto	90:cb3d968589d8	297	/! @brief Read current value of the PDB_SC_PDBEN field. /
Kojto	90:cb3d968589d8	298	#define BR_PDB_SC_PDBEN(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN))
Kojto	90:cb3d968589d8	299
Kojto	90:cb3d968589d8	300	/! @brief Format value for bitfield PDB_SC_PDBEN. /
Kojto	90:cb3d968589d8	301	#define BF_PDB_SC_PDBEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEN) & BM_PDB_SC_PDBEN)
Kojto	90:cb3d968589d8	302
Kojto	90:cb3d968589d8	303	/! @brief Set the PDBEN field to a new value. /
Kojto	90:cb3d968589d8	304	#define BW_PDB_SC_PDBEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN) = (v))
Kojto	90:cb3d968589d8	305	/@}/
Kojto	90:cb3d968589d8	306
Kojto	90:cb3d968589d8	307	/*!
Kojto	90:cb3d968589d8	308	* @name Register PDB_SC, field TRGSEL[11:8] (RW)
Kojto	90:cb3d968589d8	309	*
Kojto	90:cb3d968589d8	310	* Selects the trigger input source for the PDB. The trigger input source can be
Kojto	90:cb3d968589d8	311	* internal or external (EXTRG pin), or the software trigger. Refer to chip
Kojto	90:cb3d968589d8	312	* configuration details for the actual PDB input trigger connections.
Kojto	90:cb3d968589d8	313	*
Kojto	90:cb3d968589d8	314	* Values:
Kojto	90:cb3d968589d8	315	* - 0000 - Trigger-In 0 is selected.
Kojto	90:cb3d968589d8	316	* - 0001 - Trigger-In 1 is selected.
Kojto	90:cb3d968589d8	317	* - 0010 - Trigger-In 2 is selected.
Kojto	90:cb3d968589d8	318	* - 0011 - Trigger-In 3 is selected.
Kojto	90:cb3d968589d8	319	* - 0100 - Trigger-In 4 is selected.
Kojto	90:cb3d968589d8	320	* - 0101 - Trigger-In 5 is selected.
Kojto	90:cb3d968589d8	321	* - 0110 - Trigger-In 6 is selected.
Kojto	90:cb3d968589d8	322	* - 0111 - Trigger-In 7 is selected.
Kojto	90:cb3d968589d8	323	* - 1000 - Trigger-In 8 is selected.
Kojto	90:cb3d968589d8	324	* - 1001 - Trigger-In 9 is selected.
Kojto	90:cb3d968589d8	325	* - 1010 - Trigger-In 10 is selected.
Kojto	90:cb3d968589d8	326	* - 1011 - Trigger-In 11 is selected.
Kojto	90:cb3d968589d8	327	* - 1100 - Trigger-In 12 is selected.
Kojto	90:cb3d968589d8	328	* - 1101 - Trigger-In 13 is selected.
Kojto	90:cb3d968589d8	329	* - 1110 - Trigger-In 14 is selected.
Kojto	90:cb3d968589d8	330	* - 1111 - Software trigger is selected.
Kojto	90:cb3d968589d8	331	*/
Kojto	90:cb3d968589d8	332	/@{/
Kojto	90:cb3d968589d8	333	#define BP_PDB_SC_TRGSEL (8U) /!< Bit position for PDB_SC_TRGSEL. /
Kojto	90:cb3d968589d8	334	#define BM_PDB_SC_TRGSEL (0x00000F00U) /!< Bit mask for PDB_SC_TRGSEL. /
Kojto	90:cb3d968589d8	335	#define BS_PDB_SC_TRGSEL (4U) /!< Bit field size in bits for PDB_SC_TRGSEL. /
Kojto	90:cb3d968589d8	336
Kojto	90:cb3d968589d8	337	/! @brief Read current value of the PDB_SC_TRGSEL field. /
Kojto	90:cb3d968589d8	338	#define BR_PDB_SC_TRGSEL(x) (HW_PDB_SC(x).B.TRGSEL)
Kojto	90:cb3d968589d8	339
Kojto	90:cb3d968589d8	340	/! @brief Format value for bitfield PDB_SC_TRGSEL. /
Kojto	90:cb3d968589d8	341	#define BF_PDB_SC_TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_TRGSEL) & BM_PDB_SC_TRGSEL)
Kojto	90:cb3d968589d8	342
Kojto	90:cb3d968589d8	343	/! @brief Set the TRGSEL field to a new value. /
Kojto	90:cb3d968589d8	344	#define BW_PDB_SC_TRGSEL(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_TRGSEL) \| BF_PDB_SC_TRGSEL(v)))
Kojto	90:cb3d968589d8	345	/@}/
Kojto	90:cb3d968589d8	346
Kojto	90:cb3d968589d8	347	/*!
Kojto	90:cb3d968589d8	348	* @name Register PDB_SC, field PRESCALER[14:12] (RW)
Kojto	90:cb3d968589d8	349	*
Kojto	90:cb3d968589d8	350	* Values:
Kojto	90:cb3d968589d8	351	* - 000 - Counting uses the peripheral clock divided by multiplication factor
Kojto	90:cb3d968589d8	352	* selected by MULT.
Kojto	90:cb3d968589d8	353	* - 001 - Counting uses the peripheral clock divided by twice of the
Kojto	90:cb3d968589d8	354	* multiplication factor selected by MULT.
Kojto	90:cb3d968589d8	355	* - 010 - Counting uses the peripheral clock divided by four times of the
Kojto	90:cb3d968589d8	356	* multiplication factor selected by MULT.
Kojto	90:cb3d968589d8	357	* - 011 - Counting uses the peripheral clock divided by eight times of the
Kojto	90:cb3d968589d8	358	* multiplication factor selected by MULT.
Kojto	90:cb3d968589d8	359	* - 100 - Counting uses the peripheral clock divided by 16 times of the
Kojto	90:cb3d968589d8	360	* multiplication factor selected by MULT.
Kojto	90:cb3d968589d8	361	* - 101 - Counting uses the peripheral clock divided by 32 times of the
Kojto	90:cb3d968589d8	362	* multiplication factor selected by MULT.
Kojto	90:cb3d968589d8	363	* - 110 - Counting uses the peripheral clock divided by 64 times of the
Kojto	90:cb3d968589d8	364	* multiplication factor selected by MULT.
Kojto	90:cb3d968589d8	365	* - 111 - Counting uses the peripheral clock divided by 128 times of the
Kojto	90:cb3d968589d8	366	* multiplication factor selected by MULT.
Kojto	90:cb3d968589d8	367	*/
Kojto	90:cb3d968589d8	368	/@{/
Kojto	90:cb3d968589d8	369	#define BP_PDB_SC_PRESCALER (12U) /!< Bit position for PDB_SC_PRESCALER. /
Kojto	90:cb3d968589d8	370	#define BM_PDB_SC_PRESCALER (0x00007000U) /!< Bit mask for PDB_SC_PRESCALER. /
Kojto	90:cb3d968589d8	371	#define BS_PDB_SC_PRESCALER (3U) /!< Bit field size in bits for PDB_SC_PRESCALER. /
Kojto	90:cb3d968589d8	372
Kojto	90:cb3d968589d8	373	/! @brief Read current value of the PDB_SC_PRESCALER field. /
Kojto	90:cb3d968589d8	374	#define BR_PDB_SC_PRESCALER(x) (HW_PDB_SC(x).B.PRESCALER)
Kojto	90:cb3d968589d8	375
Kojto	90:cb3d968589d8	376	/! @brief Format value for bitfield PDB_SC_PRESCALER. /
Kojto	90:cb3d968589d8	377	#define BF_PDB_SC_PRESCALER(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PRESCALER) & BM_PDB_SC_PRESCALER)
Kojto	90:cb3d968589d8	378
Kojto	90:cb3d968589d8	379	/! @brief Set the PRESCALER field to a new value. /
Kojto	90:cb3d968589d8	380	#define BW_PDB_SC_PRESCALER(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_PRESCALER) \| BF_PDB_SC_PRESCALER(v)))
Kojto	90:cb3d968589d8	381	/@}/
Kojto	90:cb3d968589d8	382
Kojto	90:cb3d968589d8	383	/*!
Kojto	90:cb3d968589d8	384	* @name Register PDB_SC, field DMAEN[15] (RW)
Kojto	90:cb3d968589d8	385	*
Kojto	90:cb3d968589d8	386	* When DMA is enabled, the PDBIF flag generates a DMA request instead of an
Kojto	90:cb3d968589d8	387	* interrupt.
Kojto	90:cb3d968589d8	388	*
Kojto	90:cb3d968589d8	389	* Values:
Kojto	90:cb3d968589d8	390	* - 0 - DMA disabled.
Kojto	90:cb3d968589d8	391	* - 1 - DMA enabled.
Kojto	90:cb3d968589d8	392	*/
Kojto	90:cb3d968589d8	393	/@{/
Kojto	90:cb3d968589d8	394	#define BP_PDB_SC_DMAEN (15U) /!< Bit position for PDB_SC_DMAEN. /
Kojto	90:cb3d968589d8	395	#define BM_PDB_SC_DMAEN (0x00008000U) /!< Bit mask for PDB_SC_DMAEN. /
Kojto	90:cb3d968589d8	396	#define BS_PDB_SC_DMAEN (1U) /!< Bit field size in bits for PDB_SC_DMAEN. /
Kojto	90:cb3d968589d8	397
Kojto	90:cb3d968589d8	398	/! @brief Read current value of the PDB_SC_DMAEN field. /
Kojto	90:cb3d968589d8	399	#define BR_PDB_SC_DMAEN(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN))
Kojto	90:cb3d968589d8	400
Kojto	90:cb3d968589d8	401	/! @brief Format value for bitfield PDB_SC_DMAEN. /
Kojto	90:cb3d968589d8	402	#define BF_PDB_SC_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_DMAEN) & BM_PDB_SC_DMAEN)
Kojto	90:cb3d968589d8	403
Kojto	90:cb3d968589d8	404	/! @brief Set the DMAEN field to a new value. /
Kojto	90:cb3d968589d8	405	#define BW_PDB_SC_DMAEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN) = (v))
Kojto	90:cb3d968589d8	406	/@}/
Kojto	90:cb3d968589d8	407
Kojto	90:cb3d968589d8	408	/*!
Kojto	90:cb3d968589d8	409	* @name Register PDB_SC, field SWTRIG[16] (WORZ)
Kojto	90:cb3d968589d8	410	*
Kojto	90:cb3d968589d8	411	* When PDB is enabled and the software trigger is selected as the trigger input
Kojto	90:cb3d968589d8	412	* source, writing 1 to this field resets and restarts the counter. Writing 0 to
Kojto	90:cb3d968589d8	413	* this field has no effect. Reading this field results 0.
Kojto	90:cb3d968589d8	414	*/
Kojto	90:cb3d968589d8	415	/@{/
Kojto	90:cb3d968589d8	416	#define BP_PDB_SC_SWTRIG (16U) /!< Bit position for PDB_SC_SWTRIG. /
Kojto	90:cb3d968589d8	417	#define BM_PDB_SC_SWTRIG (0x00010000U) /!< Bit mask for PDB_SC_SWTRIG. /
Kojto	90:cb3d968589d8	418	#define BS_PDB_SC_SWTRIG (1U) /!< Bit field size in bits for PDB_SC_SWTRIG. /
Kojto	90:cb3d968589d8	419
Kojto	90:cb3d968589d8	420	/! @brief Format value for bitfield PDB_SC_SWTRIG. /
Kojto	90:cb3d968589d8	421	#define BF_PDB_SC_SWTRIG(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_SWTRIG) & BM_PDB_SC_SWTRIG)
Kojto	90:cb3d968589d8	422
Kojto	90:cb3d968589d8	423	/! @brief Set the SWTRIG field to a new value. /
Kojto	90:cb3d968589d8	424	#define BW_PDB_SC_SWTRIG(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_SWTRIG) = (v))
Kojto	90:cb3d968589d8	425	/@}/
Kojto	90:cb3d968589d8	426
Kojto	90:cb3d968589d8	427	/*!
Kojto	90:cb3d968589d8	428	* @name Register PDB_SC, field PDBEIE[17] (RW)
Kojto	90:cb3d968589d8	429	*
Kojto	90:cb3d968589d8	430	* Enables the PDB sequence error interrupt. When this field is set, any of the
Kojto	90:cb3d968589d8	431	* PDB channel sequence error flags generates a PDB sequence error interrupt.
Kojto	90:cb3d968589d8	432	*
Kojto	90:cb3d968589d8	433	* Values:
Kojto	90:cb3d968589d8	434	* - 0 - PDB sequence error interrupt disabled.
Kojto	90:cb3d968589d8	435	* - 1 - PDB sequence error interrupt enabled.
Kojto	90:cb3d968589d8	436	*/
Kojto	90:cb3d968589d8	437	/@{/
Kojto	90:cb3d968589d8	438	#define BP_PDB_SC_PDBEIE (17U) /!< Bit position for PDB_SC_PDBEIE. /
Kojto	90:cb3d968589d8	439	#define BM_PDB_SC_PDBEIE (0x00020000U) /!< Bit mask for PDB_SC_PDBEIE. /
Kojto	90:cb3d968589d8	440	#define BS_PDB_SC_PDBEIE (1U) /!< Bit field size in bits for PDB_SC_PDBEIE. /
Kojto	90:cb3d968589d8	441
Kojto	90:cb3d968589d8	442	/! @brief Read current value of the PDB_SC_PDBEIE field. /
Kojto	90:cb3d968589d8	443	#define BR_PDB_SC_PDBEIE(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE))
Kojto	90:cb3d968589d8	444
Kojto	90:cb3d968589d8	445	/! @brief Format value for bitfield PDB_SC_PDBEIE. /
Kojto	90:cb3d968589d8	446	#define BF_PDB_SC_PDBEIE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEIE) & BM_PDB_SC_PDBEIE)
Kojto	90:cb3d968589d8	447
Kojto	90:cb3d968589d8	448	/! @brief Set the PDBEIE field to a new value. /
Kojto	90:cb3d968589d8	449	#define BW_PDB_SC_PDBEIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE) = (v))
Kojto	90:cb3d968589d8	450	/@}/
Kojto	90:cb3d968589d8	451
Kojto	90:cb3d968589d8	452	/*!
Kojto	90:cb3d968589d8	453	* @name Register PDB_SC, field LDMOD[19:18] (RW)
Kojto	90:cb3d968589d8	454	*
Kojto	90:cb3d968589d8	455	* Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
Kojto	90:cb3d968589d8	456	* after 1 is written to LDOK.
Kojto	90:cb3d968589d8	457	*
Kojto	90:cb3d968589d8	458	* Values:
Kojto	90:cb3d968589d8	459	* - 00 - The internal registers are loaded with the values from their buffers
Kojto	90:cb3d968589d8	460	* immediately after 1 is written to LDOK.
Kojto	90:cb3d968589d8	461	* - 01 - The internal registers are loaded with the values from their buffers
Kojto	90:cb3d968589d8	462	* when the PDB counter reaches the MOD register value after 1 is written to
Kojto	90:cb3d968589d8	463	* LDOK.
Kojto	90:cb3d968589d8	464	* - 10 - The internal registers are loaded with the values from their buffers
Kojto	90:cb3d968589d8	465	* when a trigger input event is detected after 1 is written to LDOK.
Kojto	90:cb3d968589d8	466	* - 11 - The internal registers are loaded with the values from their buffers
Kojto	90:cb3d968589d8	467	* when either the PDB counter reaches the MOD register value or a trigger
Kojto	90:cb3d968589d8	468	* input event is detected, after 1 is written to LDOK.
Kojto	90:cb3d968589d8	469	*/
Kojto	90:cb3d968589d8	470	/@{/
Kojto	90:cb3d968589d8	471	#define BP_PDB_SC_LDMOD (18U) /!< Bit position for PDB_SC_LDMOD. /
Kojto	90:cb3d968589d8	472	#define BM_PDB_SC_LDMOD (0x000C0000U) /!< Bit mask for PDB_SC_LDMOD. /
Kojto	90:cb3d968589d8	473	#define BS_PDB_SC_LDMOD (2U) /!< Bit field size in bits for PDB_SC_LDMOD. /
Kojto	90:cb3d968589d8	474
Kojto	90:cb3d968589d8	475	/! @brief Read current value of the PDB_SC_LDMOD field. /
Kojto	90:cb3d968589d8	476	#define BR_PDB_SC_LDMOD(x) (HW_PDB_SC(x).B.LDMOD)
Kojto	90:cb3d968589d8	477
Kojto	90:cb3d968589d8	478	/! @brief Format value for bitfield PDB_SC_LDMOD. /
Kojto	90:cb3d968589d8	479	#define BF_PDB_SC_LDMOD(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDMOD) & BM_PDB_SC_LDMOD)
Kojto	90:cb3d968589d8	480
Kojto	90:cb3d968589d8	481	/! @brief Set the LDMOD field to a new value. /
Kojto	90:cb3d968589d8	482	#define BW_PDB_SC_LDMOD(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_LDMOD) \| BF_PDB_SC_LDMOD(v)))
Kojto	90:cb3d968589d8	483	/@}/
Kojto	90:cb3d968589d8	484
Kojto	90:cb3d968589d8	485	/*******************************************************************************
Kojto	90:cb3d968589d8	486	* HW_PDB_MOD - Modulus register
Kojto	90:cb3d968589d8	487	******************************************************************************/
Kojto	90:cb3d968589d8	488
Kojto	90:cb3d968589d8	489	/*!
Kojto	90:cb3d968589d8	490	* @brief HW_PDB_MOD - Modulus register (RW)
Kojto	90:cb3d968589d8	491	*
Kojto	90:cb3d968589d8	492	* Reset value: 0x0000FFFFU
Kojto	90:cb3d968589d8	493	*/
Kojto	90:cb3d968589d8	494	typedef union _hw_pdb_mod
Kojto	90:cb3d968589d8	495	{
Kojto	90:cb3d968589d8	496	uint32_t U;
Kojto	90:cb3d968589d8	497	struct _hw_pdb_mod_bitfields
Kojto	90:cb3d968589d8	498	{
Kojto	90:cb3d968589d8	499	uint32_t MOD : 16; /!< [15:0] PDB Modulus /
Kojto	90:cb3d968589d8	500	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	501	} B;
Kojto	90:cb3d968589d8	502	} hw_pdb_mod_t;
Kojto	90:cb3d968589d8	503
Kojto	90:cb3d968589d8	504	/*!
Kojto	90:cb3d968589d8	505	* @name Constants and macros for entire PDB_MOD register
Kojto	90:cb3d968589d8	506	*/
Kojto	90:cb3d968589d8	507	/@{/
Kojto	90:cb3d968589d8	508	#define HW_PDB_MOD_ADDR(x) ((x) + 0x4U)
Kojto	90:cb3d968589d8	509
Kojto	90:cb3d968589d8	510	#define HW_PDB_MOD(x) ((__IO hw_pdb_mod_t ) HW_PDB_MOD_ADDR(x))
Kojto	90:cb3d968589d8	511	#define HW_PDB_MOD_RD(x) (HW_PDB_MOD(x).U)
Kojto	90:cb3d968589d8	512	#define HW_PDB_MOD_WR(x, v) (HW_PDB_MOD(x).U = (v))
Kojto	90:cb3d968589d8	513	#define HW_PDB_MOD_SET(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) \| (v)))
Kojto	90:cb3d968589d8	514	#define HW_PDB_MOD_CLR(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	515	#define HW_PDB_MOD_TOG(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	516	/@}/
Kojto	90:cb3d968589d8	517
Kojto	90:cb3d968589d8	518	/*
Kojto	90:cb3d968589d8	519	* Constants & macros for individual PDB_MOD bitfields
Kojto	90:cb3d968589d8	520	*/
Kojto	90:cb3d968589d8	521
Kojto	90:cb3d968589d8	522	/*!
Kojto	90:cb3d968589d8	523	* @name Register PDB_MOD, field MOD[15:0] (RW)
Kojto	90:cb3d968589d8	524	*
Kojto	90:cb3d968589d8	525	* Specifies the period of the counter. When the counter reaches this value, it
Kojto	90:cb3d968589d8	526	* will be reset back to zero. If the PDB is in Continuous mode, the count begins
Kojto	90:cb3d968589d8	527	* anew. Reading this field returns the value of the internal register that is
Kojto	90:cb3d968589d8	528	* effective for the current cycle of PDB.
Kojto	90:cb3d968589d8	529	*/
Kojto	90:cb3d968589d8	530	/@{/
Kojto	90:cb3d968589d8	531	#define BP_PDB_MOD_MOD (0U) /!< Bit position for PDB_MOD_MOD. /
Kojto	90:cb3d968589d8	532	#define BM_PDB_MOD_MOD (0x0000FFFFU) /!< Bit mask for PDB_MOD_MOD. /
Kojto	90:cb3d968589d8	533	#define BS_PDB_MOD_MOD (16U) /!< Bit field size in bits for PDB_MOD_MOD. /
Kojto	90:cb3d968589d8	534
Kojto	90:cb3d968589d8	535	/! @brief Read current value of the PDB_MOD_MOD field. /
Kojto	90:cb3d968589d8	536	#define BR_PDB_MOD_MOD(x) (HW_PDB_MOD(x).B.MOD)
Kojto	90:cb3d968589d8	537
Kojto	90:cb3d968589d8	538	/! @brief Format value for bitfield PDB_MOD_MOD. /
Kojto	90:cb3d968589d8	539	#define BF_PDB_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_PDB_MOD_MOD) & BM_PDB_MOD_MOD)
Kojto	90:cb3d968589d8	540
Kojto	90:cb3d968589d8	541	/! @brief Set the MOD field to a new value. /
Kojto	90:cb3d968589d8	542	#define BW_PDB_MOD_MOD(x, v) (HW_PDB_MOD_WR(x, (HW_PDB_MOD_RD(x) & ~BM_PDB_MOD_MOD) \| BF_PDB_MOD_MOD(v)))
Kojto	90:cb3d968589d8	543	/@}/
Kojto	90:cb3d968589d8	544
Kojto	90:cb3d968589d8	545	/*******************************************************************************
Kojto	90:cb3d968589d8	546	* HW_PDB_CNT - Counter register
Kojto	90:cb3d968589d8	547	******************************************************************************/
Kojto	90:cb3d968589d8	548
Kojto	90:cb3d968589d8	549	/*!
Kojto	90:cb3d968589d8	550	* @brief HW_PDB_CNT - Counter register (RO)
Kojto	90:cb3d968589d8	551	*
Kojto	90:cb3d968589d8	552	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	553	*/
Kojto	90:cb3d968589d8	554	typedef union _hw_pdb_cnt
Kojto	90:cb3d968589d8	555	{
Kojto	90:cb3d968589d8	556	uint32_t U;
Kojto	90:cb3d968589d8	557	struct _hw_pdb_cnt_bitfields
Kojto	90:cb3d968589d8	558	{
Kojto	90:cb3d968589d8	559	uint32_t CNT : 16; /!< [15:0] PDB Counter /
Kojto	90:cb3d968589d8	560	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	561	} B;
Kojto	90:cb3d968589d8	562	} hw_pdb_cnt_t;
Kojto	90:cb3d968589d8	563
Kojto	90:cb3d968589d8	564	/*!
Kojto	90:cb3d968589d8	565	* @name Constants and macros for entire PDB_CNT register
Kojto	90:cb3d968589d8	566	*/
Kojto	90:cb3d968589d8	567	/@{/
Kojto	90:cb3d968589d8	568	#define HW_PDB_CNT_ADDR(x) ((x) + 0x8U)
Kojto	90:cb3d968589d8	569
Kojto	90:cb3d968589d8	570	#define HW_PDB_CNT(x) ((__I hw_pdb_cnt_t ) HW_PDB_CNT_ADDR(x))
Kojto	90:cb3d968589d8	571	#define HW_PDB_CNT_RD(x) (HW_PDB_CNT(x).U)
Kojto	90:cb3d968589d8	572	/@}/
Kojto	90:cb3d968589d8	573
Kojto	90:cb3d968589d8	574	/*
Kojto	90:cb3d968589d8	575	* Constants & macros for individual PDB_CNT bitfields
Kojto	90:cb3d968589d8	576	*/
Kojto	90:cb3d968589d8	577
Kojto	90:cb3d968589d8	578	/*!
Kojto	90:cb3d968589d8	579	* @name Register PDB_CNT, field CNT[15:0] (RO)
Kojto	90:cb3d968589d8	580	*
Kojto	90:cb3d968589d8	581	* Contains the current value of the counter.
Kojto	90:cb3d968589d8	582	*/
Kojto	90:cb3d968589d8	583	/@{/
Kojto	90:cb3d968589d8	584	#define BP_PDB_CNT_CNT (0U) /!< Bit position for PDB_CNT_CNT. /
Kojto	90:cb3d968589d8	585	#define BM_PDB_CNT_CNT (0x0000FFFFU) /!< Bit mask for PDB_CNT_CNT. /
Kojto	90:cb3d968589d8	586	#define BS_PDB_CNT_CNT (16U) /!< Bit field size in bits for PDB_CNT_CNT. /
Kojto	90:cb3d968589d8	587
Kojto	90:cb3d968589d8	588	/! @brief Read current value of the PDB_CNT_CNT field. /
Kojto	90:cb3d968589d8	589	#define BR_PDB_CNT_CNT(x) (HW_PDB_CNT(x).B.CNT)
Kojto	90:cb3d968589d8	590	/@}/
Kojto	90:cb3d968589d8	591
Kojto	90:cb3d968589d8	592	/*******************************************************************************
Kojto	90:cb3d968589d8	593	* HW_PDB_IDLY - Interrupt Delay register
Kojto	90:cb3d968589d8	594	******************************************************************************/
Kojto	90:cb3d968589d8	595
Kojto	90:cb3d968589d8	596	/*!
Kojto	90:cb3d968589d8	597	* @brief HW_PDB_IDLY - Interrupt Delay register (RW)
Kojto	90:cb3d968589d8	598	*
Kojto	90:cb3d968589d8	599	* Reset value: 0x0000FFFFU
Kojto	90:cb3d968589d8	600	*/
Kojto	90:cb3d968589d8	601	typedef union _hw_pdb_idly
Kojto	90:cb3d968589d8	602	{
Kojto	90:cb3d968589d8	603	uint32_t U;
Kojto	90:cb3d968589d8	604	struct _hw_pdb_idly_bitfields
Kojto	90:cb3d968589d8	605	{
Kojto	90:cb3d968589d8	606	uint32_t IDLY : 16; /!< [15:0] PDB Interrupt Delay /
Kojto	90:cb3d968589d8	607	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	608	} B;
Kojto	90:cb3d968589d8	609	} hw_pdb_idly_t;
Kojto	90:cb3d968589d8	610
Kojto	90:cb3d968589d8	611	/*!
Kojto	90:cb3d968589d8	612	* @name Constants and macros for entire PDB_IDLY register
Kojto	90:cb3d968589d8	613	*/
Kojto	90:cb3d968589d8	614	/@{/
Kojto	90:cb3d968589d8	615	#define HW_PDB_IDLY_ADDR(x) ((x) + 0xCU)
Kojto	90:cb3d968589d8	616
Kojto	90:cb3d968589d8	617	#define HW_PDB_IDLY(x) ((__IO hw_pdb_idly_t ) HW_PDB_IDLY_ADDR(x))
Kojto	90:cb3d968589d8	618	#define HW_PDB_IDLY_RD(x) (HW_PDB_IDLY(x).U)
Kojto	90:cb3d968589d8	619	#define HW_PDB_IDLY_WR(x, v) (HW_PDB_IDLY(x).U = (v))
Kojto	90:cb3d968589d8	620	#define HW_PDB_IDLY_SET(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) \| (v)))
Kojto	90:cb3d968589d8	621	#define HW_PDB_IDLY_CLR(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	622	#define HW_PDB_IDLY_TOG(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	623	/@}/
Kojto	90:cb3d968589d8	624
Kojto	90:cb3d968589d8	625	/*
Kojto	90:cb3d968589d8	626	* Constants & macros for individual PDB_IDLY bitfields
Kojto	90:cb3d968589d8	627	*/
Kojto	90:cb3d968589d8	628
Kojto	90:cb3d968589d8	629	/*!
Kojto	90:cb3d968589d8	630	* @name Register PDB_IDLY, field IDLY[15:0] (RW)
Kojto	90:cb3d968589d8	631	*
Kojto	90:cb3d968589d8	632	* Specifies the delay value to schedule the PDB interrupt. It can be used to
Kojto	90:cb3d968589d8	633	* schedule an independent interrupt at some point in the PDB cycle. If enabled, a
Kojto	90:cb3d968589d8	634	* PDB interrupt is generated, when the counter is equal to the IDLY. Reading
Kojto	90:cb3d968589d8	635	* this field returns the value of internal register that is effective for the
Kojto	90:cb3d968589d8	636	* current cycle of the PDB.
Kojto	90:cb3d968589d8	637	*/
Kojto	90:cb3d968589d8	638	/@{/
Kojto	90:cb3d968589d8	639	#define BP_PDB_IDLY_IDLY (0U) /!< Bit position for PDB_IDLY_IDLY. /
Kojto	90:cb3d968589d8	640	#define BM_PDB_IDLY_IDLY (0x0000FFFFU) /!< Bit mask for PDB_IDLY_IDLY. /
Kojto	90:cb3d968589d8	641	#define BS_PDB_IDLY_IDLY (16U) /!< Bit field size in bits for PDB_IDLY_IDLY. /
Kojto	90:cb3d968589d8	642
Kojto	90:cb3d968589d8	643	/! @brief Read current value of the PDB_IDLY_IDLY field. /
Kojto	90:cb3d968589d8	644	#define BR_PDB_IDLY_IDLY(x) (HW_PDB_IDLY(x).B.IDLY)
Kojto	90:cb3d968589d8	645
Kojto	90:cb3d968589d8	646	/! @brief Format value for bitfield PDB_IDLY_IDLY. /
Kojto	90:cb3d968589d8	647	#define BF_PDB_IDLY_IDLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_IDLY_IDLY) & BM_PDB_IDLY_IDLY)
Kojto	90:cb3d968589d8	648
Kojto	90:cb3d968589d8	649	/! @brief Set the IDLY field to a new value. /
Kojto	90:cb3d968589d8	650	#define BW_PDB_IDLY_IDLY(x, v) (HW_PDB_IDLY_WR(x, (HW_PDB_IDLY_RD(x) & ~BM_PDB_IDLY_IDLY) \| BF_PDB_IDLY_IDLY(v)))
Kojto	90:cb3d968589d8	651	/@}/
Kojto	90:cb3d968589d8	652
Kojto	90:cb3d968589d8	653	/*******************************************************************************
Kojto	90:cb3d968589d8	654	* HW_PDB_CHnC1 - Channel n Control register 1
Kojto	90:cb3d968589d8	655	******************************************************************************/
Kojto	90:cb3d968589d8	656
Kojto	90:cb3d968589d8	657	/*!
Kojto	90:cb3d968589d8	658	* @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW)
Kojto	90:cb3d968589d8	659	*
Kojto	90:cb3d968589d8	660	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	661	*
Kojto	90:cb3d968589d8	662	* Each PDB channel has one control register, CHnC1. The bits in this register
Kojto	90:cb3d968589d8	663	* control the functionality of each PDB channel operation.
Kojto	90:cb3d968589d8	664	*/
Kojto	90:cb3d968589d8	665	typedef union _hw_pdb_chnc1
Kojto	90:cb3d968589d8	666	{
Kojto	90:cb3d968589d8	667	uint32_t U;
Kojto	90:cb3d968589d8	668	struct _hw_pdb_chnc1_bitfields
Kojto	90:cb3d968589d8	669	{
Kojto	90:cb3d968589d8	670	uint32_t EN : 8; /!< [7:0] PDB Channel Pre-Trigger Enable /
Kojto	90:cb3d968589d8	671	uint32_t TOS : 8; /!< [15:8] PDB Channel Pre-Trigger Output Select /
Kojto	90:cb3d968589d8	672	uint32_t BB : 8; /*!< [23:16] PDB Channel Pre-Trigger Back-to-Back
Kojto	90:cb3d968589d8	673	* Operation Enable */
Kojto	90:cb3d968589d8	674	uint32_t RESERVED0 : 8; /!< [31:24] /
Kojto	90:cb3d968589d8	675	} B;
Kojto	90:cb3d968589d8	676	} hw_pdb_chnc1_t;
Kojto	90:cb3d968589d8	677
Kojto	90:cb3d968589d8	678	/*!
Kojto	90:cb3d968589d8	679	* @name Constants and macros for entire PDB_CHnC1 register
Kojto	90:cb3d968589d8	680	*/
Kojto	90:cb3d968589d8	681	/@{/
Kojto	90:cb3d968589d8	682	#define HW_PDB_CHnC1_COUNT (2U)
Kojto	90:cb3d968589d8	683
Kojto	90:cb3d968589d8	684	#define HW_PDB_CHnC1_ADDR(x, n) ((x) + 0x10U + (0x28U * (n)))
Kojto	90:cb3d968589d8	685
Kojto	90:cb3d968589d8	686	#define HW_PDB_CHnC1(x, n) ((__IO hw_pdb_chnc1_t ) HW_PDB_CHnC1_ADDR(x, n))
Kojto	90:cb3d968589d8	687	#define HW_PDB_CHnC1_RD(x, n) (HW_PDB_CHnC1(x, n).U)
Kojto	90:cb3d968589d8	688	#define HW_PDB_CHnC1_WR(x, n, v) (HW_PDB_CHnC1(x, n).U = (v))
Kojto	90:cb3d968589d8	689	#define HW_PDB_CHnC1_SET(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	690	#define HW_PDB_CHnC1_CLR(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	691	#define HW_PDB_CHnC1_TOG(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	692	/@}/
Kojto	90:cb3d968589d8	693
Kojto	90:cb3d968589d8	694	/*
Kojto	90:cb3d968589d8	695	* Constants & macros for individual PDB_CHnC1 bitfields
Kojto	90:cb3d968589d8	696	*/
Kojto	90:cb3d968589d8	697
Kojto	90:cb3d968589d8	698	/*!
Kojto	90:cb3d968589d8	699	* @name Register PDB_CHnC1, field EN[7:0] (RW)
Kojto	90:cb3d968589d8	700	*
Kojto	90:cb3d968589d8	701	* These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
Kojto	90:cb3d968589d8	702	* bits are implemented in this MCU.
Kojto	90:cb3d968589d8	703	*
Kojto	90:cb3d968589d8	704	* Values:
Kojto	90:cb3d968589d8	705	* - 0 - PDB channel's corresponding pre-trigger disabled.
Kojto	90:cb3d968589d8	706	* - 1 - PDB channel's corresponding pre-trigger enabled.
Kojto	90:cb3d968589d8	707	*/
Kojto	90:cb3d968589d8	708	/@{/
Kojto	90:cb3d968589d8	709	#define BP_PDB_CHnC1_EN (0U) /!< Bit position for PDB_CHnC1_EN. /
Kojto	90:cb3d968589d8	710	#define BM_PDB_CHnC1_EN (0x000000FFU) /!< Bit mask for PDB_CHnC1_EN. /
Kojto	90:cb3d968589d8	711	#define BS_PDB_CHnC1_EN (8U) /!< Bit field size in bits for PDB_CHnC1_EN. /
Kojto	90:cb3d968589d8	712
Kojto	90:cb3d968589d8	713	/! @brief Read current value of the PDB_CHnC1_EN field. /
Kojto	90:cb3d968589d8	714	#define BR_PDB_CHnC1_EN(x, n) (HW_PDB_CHnC1(x, n).B.EN)
Kojto	90:cb3d968589d8	715
Kojto	90:cb3d968589d8	716	/! @brief Format value for bitfield PDB_CHnC1_EN. /
Kojto	90:cb3d968589d8	717	#define BF_PDB_CHnC1_EN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_EN) & BM_PDB_CHnC1_EN)
Kojto	90:cb3d968589d8	718
Kojto	90:cb3d968589d8	719	/! @brief Set the EN field to a new value. /
Kojto	90:cb3d968589d8	720	#define BW_PDB_CHnC1_EN(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_EN) \| BF_PDB_CHnC1_EN(v)))
Kojto	90:cb3d968589d8	721	/@}/
Kojto	90:cb3d968589d8	722
Kojto	90:cb3d968589d8	723	/*!
Kojto	90:cb3d968589d8	724	* @name Register PDB_CHnC1, field TOS[15:8] (RW)
Kojto	90:cb3d968589d8	725	*
Kojto	90:cb3d968589d8	726	* Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
Kojto	90:cb3d968589d8	727	* implemented in this MCU.
Kojto	90:cb3d968589d8	728	*
Kojto	90:cb3d968589d8	729	* Values:
Kojto	90:cb3d968589d8	730	* - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The
Kojto	90:cb3d968589d8	731	* pre-trigger asserts one peripheral clock cycle after a rising edge is detected
Kojto	90:cb3d968589d8	732	* on selected trigger input source or software trigger is selected and SWTRIG
Kojto	90:cb3d968589d8	733	* is written with 1.
Kojto	90:cb3d968589d8	734	* - 1 - PDB channel's corresponding pre-trigger asserts when the counter
Kojto	90:cb3d968589d8	735	* reaches the channel delay register and one peripheral clock cycle after a rising
Kojto	90:cb3d968589d8	736	* edge is detected on selected trigger input source or software trigger is
Kojto	90:cb3d968589d8	737	* selected and SETRIG is written with 1.
Kojto	90:cb3d968589d8	738	*/
Kojto	90:cb3d968589d8	739	/@{/
Kojto	90:cb3d968589d8	740	#define BP_PDB_CHnC1_TOS (8U) /!< Bit position for PDB_CHnC1_TOS. /
Kojto	90:cb3d968589d8	741	#define BM_PDB_CHnC1_TOS (0x0000FF00U) /!< Bit mask for PDB_CHnC1_TOS. /
Kojto	90:cb3d968589d8	742	#define BS_PDB_CHnC1_TOS (8U) /!< Bit field size in bits for PDB_CHnC1_TOS. /
Kojto	90:cb3d968589d8	743
Kojto	90:cb3d968589d8	744	/! @brief Read current value of the PDB_CHnC1_TOS field. /
Kojto	90:cb3d968589d8	745	#define BR_PDB_CHnC1_TOS(x, n) (HW_PDB_CHnC1(x, n).B.TOS)
Kojto	90:cb3d968589d8	746
Kojto	90:cb3d968589d8	747	/! @brief Format value for bitfield PDB_CHnC1_TOS. /
Kojto	90:cb3d968589d8	748	#define BF_PDB_CHnC1_TOS(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_TOS) & BM_PDB_CHnC1_TOS)
Kojto	90:cb3d968589d8	749
Kojto	90:cb3d968589d8	750	/! @brief Set the TOS field to a new value. /
Kojto	90:cb3d968589d8	751	#define BW_PDB_CHnC1_TOS(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_TOS) \| BF_PDB_CHnC1_TOS(v)))
Kojto	90:cb3d968589d8	752	/@}/
Kojto	90:cb3d968589d8	753
Kojto	90:cb3d968589d8	754	/*!
Kojto	90:cb3d968589d8	755	* @name Register PDB_CHnC1, field BB[23:16] (RW)
Kojto	90:cb3d968589d8	756	*
Kojto	90:cb3d968589d8	757	* These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
Kojto	90:cb3d968589d8	758	* Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
Kojto	90:cb3d968589d8	759	* enables the ADC conversions complete to trigger the next PDB channel
Kojto	90:cb3d968589d8	760	* pre-trigger and trigger output, so that the ADC conversions can be triggered on next
Kojto	90:cb3d968589d8	761	* set of configuration and results registers. Application code must only enable
Kojto	90:cb3d968589d8	762	* the back-to-back operation of the PDB pre-triggers at the leading of the
Kojto	90:cb3d968589d8	763	* back-to-back connection chain.
Kojto	90:cb3d968589d8	764	*
Kojto	90:cb3d968589d8	765	* Values:
Kojto	90:cb3d968589d8	766	* - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled.
Kojto	90:cb3d968589d8	767	* - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled.
Kojto	90:cb3d968589d8	768	*/
Kojto	90:cb3d968589d8	769	/@{/
Kojto	90:cb3d968589d8	770	#define BP_PDB_CHnC1_BB (16U) /!< Bit position for PDB_CHnC1_BB. /
Kojto	90:cb3d968589d8	771	#define BM_PDB_CHnC1_BB (0x00FF0000U) /!< Bit mask for PDB_CHnC1_BB. /
Kojto	90:cb3d968589d8	772	#define BS_PDB_CHnC1_BB (8U) /!< Bit field size in bits for PDB_CHnC1_BB. /
Kojto	90:cb3d968589d8	773
Kojto	90:cb3d968589d8	774	/! @brief Read current value of the PDB_CHnC1_BB field. /
Kojto	90:cb3d968589d8	775	#define BR_PDB_CHnC1_BB(x, n) (HW_PDB_CHnC1(x, n).B.BB)
Kojto	90:cb3d968589d8	776
Kojto	90:cb3d968589d8	777	/! @brief Format value for bitfield PDB_CHnC1_BB. /
Kojto	90:cb3d968589d8	778	#define BF_PDB_CHnC1_BB(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_BB) & BM_PDB_CHnC1_BB)
Kojto	90:cb3d968589d8	779
Kojto	90:cb3d968589d8	780	/! @brief Set the BB field to a new value. /
Kojto	90:cb3d968589d8	781	#define BW_PDB_CHnC1_BB(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_BB) \| BF_PDB_CHnC1_BB(v)))
Kojto	90:cb3d968589d8	782	/@}/
Kojto	90:cb3d968589d8	783	/*******************************************************************************
Kojto	90:cb3d968589d8	784	* HW_PDB_CHnS - Channel n Status register
Kojto	90:cb3d968589d8	785	******************************************************************************/
Kojto	90:cb3d968589d8	786
Kojto	90:cb3d968589d8	787	/*!
Kojto	90:cb3d968589d8	788	* @brief HW_PDB_CHnS - Channel n Status register (RW)
Kojto	90:cb3d968589d8	789	*
Kojto	90:cb3d968589d8	790	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	791	*/
Kojto	90:cb3d968589d8	792	typedef union _hw_pdb_chns
Kojto	90:cb3d968589d8	793	{
Kojto	90:cb3d968589d8	794	uint32_t U;
Kojto	90:cb3d968589d8	795	struct _hw_pdb_chns_bitfields
Kojto	90:cb3d968589d8	796	{
Kojto	90:cb3d968589d8	797	uint32_t ERR : 8; /!< [7:0] PDB Channel Sequence Error Flags /
Kojto	90:cb3d968589d8	798	uint32_t RESERVED0 : 8; /!< [15:8] /
Kojto	90:cb3d968589d8	799	uint32_t CF : 8; /!< [23:16] PDB Channel Flags /
Kojto	90:cb3d968589d8	800	uint32_t RESERVED1 : 8; /!< [31:24] /
Kojto	90:cb3d968589d8	801	} B;
Kojto	90:cb3d968589d8	802	} hw_pdb_chns_t;
Kojto	90:cb3d968589d8	803
Kojto	90:cb3d968589d8	804	/*!
Kojto	90:cb3d968589d8	805	* @name Constants and macros for entire PDB_CHnS register
Kojto	90:cb3d968589d8	806	*/
Kojto	90:cb3d968589d8	807	/@{/
Kojto	90:cb3d968589d8	808	#define HW_PDB_CHnS_COUNT (2U)
Kojto	90:cb3d968589d8	809
Kojto	90:cb3d968589d8	810	#define HW_PDB_CHnS_ADDR(x, n) ((x) + 0x14U + (0x28U * (n)))
Kojto	90:cb3d968589d8	811
Kojto	90:cb3d968589d8	812	#define HW_PDB_CHnS(x, n) ((__IO hw_pdb_chns_t ) HW_PDB_CHnS_ADDR(x, n))
Kojto	90:cb3d968589d8	813	#define HW_PDB_CHnS_RD(x, n) (HW_PDB_CHnS(x, n).U)
Kojto	90:cb3d968589d8	814	#define HW_PDB_CHnS_WR(x, n, v) (HW_PDB_CHnS(x, n).U = (v))
Kojto	90:cb3d968589d8	815	#define HW_PDB_CHnS_SET(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	816	#define HW_PDB_CHnS_CLR(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	817	#define HW_PDB_CHnS_TOG(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	818	/@}/
Kojto	90:cb3d968589d8	819
Kojto	90:cb3d968589d8	820	/*
Kojto	90:cb3d968589d8	821	* Constants & macros for individual PDB_CHnS bitfields
Kojto	90:cb3d968589d8	822	*/
Kojto	90:cb3d968589d8	823
Kojto	90:cb3d968589d8	824	/*!
Kojto	90:cb3d968589d8	825	* @name Register PDB_CHnS, field ERR[7:0] (RW)
Kojto	90:cb3d968589d8	826	*
Kojto	90:cb3d968589d8	827	* Only the lower M bits are implemented in this MCU.
Kojto	90:cb3d968589d8	828	*
Kojto	90:cb3d968589d8	829	* Values:
Kojto	90:cb3d968589d8	830	* - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger.
Kojto	90:cb3d968589d8	831	* - 1 - Sequence error detected on PDB channel's corresponding pre-trigger.
Kojto	90:cb3d968589d8	832	* ADCn block can be triggered for a conversion by one pre-trigger from PDB
Kojto	90:cb3d968589d8	833	* channel n. When one conversion, which is triggered by one of the pre-triggers
Kojto	90:cb3d968589d8	834	* from PDB channel n, is in progress, new trigger from PDB channel's
Kojto	90:cb3d968589d8	835	* corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set.
Kojto	90:cb3d968589d8	836	* Writing 0's to clear the sequence error flags.
Kojto	90:cb3d968589d8	837	*/
Kojto	90:cb3d968589d8	838	/@{/
Kojto	90:cb3d968589d8	839	#define BP_PDB_CHnS_ERR (0U) /!< Bit position for PDB_CHnS_ERR. /
Kojto	90:cb3d968589d8	840	#define BM_PDB_CHnS_ERR (0x000000FFU) /!< Bit mask for PDB_CHnS_ERR. /
Kojto	90:cb3d968589d8	841	#define BS_PDB_CHnS_ERR (8U) /!< Bit field size in bits for PDB_CHnS_ERR. /
Kojto	90:cb3d968589d8	842
Kojto	90:cb3d968589d8	843	/! @brief Read current value of the PDB_CHnS_ERR field. /
Kojto	90:cb3d968589d8	844	#define BR_PDB_CHnS_ERR(x, n) (HW_PDB_CHnS(x, n).B.ERR)
Kojto	90:cb3d968589d8	845
Kojto	90:cb3d968589d8	846	/! @brief Format value for bitfield PDB_CHnS_ERR. /
Kojto	90:cb3d968589d8	847	#define BF_PDB_CHnS_ERR(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_ERR) & BM_PDB_CHnS_ERR)
Kojto	90:cb3d968589d8	848
Kojto	90:cb3d968589d8	849	/! @brief Set the ERR field to a new value. /
Kojto	90:cb3d968589d8	850	#define BW_PDB_CHnS_ERR(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_ERR) \| BF_PDB_CHnS_ERR(v)))
Kojto	90:cb3d968589d8	851	/@}/
Kojto	90:cb3d968589d8	852
Kojto	90:cb3d968589d8	853	/*!
Kojto	90:cb3d968589d8	854	* @name Register PDB_CHnS, field CF[23:16] (RW)
Kojto	90:cb3d968589d8	855	*
Kojto	90:cb3d968589d8	856	* The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
Kojto	90:cb3d968589d8	857	* clear these bits.
Kojto	90:cb3d968589d8	858	*/
Kojto	90:cb3d968589d8	859	/@{/
Kojto	90:cb3d968589d8	860	#define BP_PDB_CHnS_CF (16U) /!< Bit position for PDB_CHnS_CF. /
Kojto	90:cb3d968589d8	861	#define BM_PDB_CHnS_CF (0x00FF0000U) /!< Bit mask for PDB_CHnS_CF. /
Kojto	90:cb3d968589d8	862	#define BS_PDB_CHnS_CF (8U) /!< Bit field size in bits for PDB_CHnS_CF. /
Kojto	90:cb3d968589d8	863
Kojto	90:cb3d968589d8	864	/! @brief Read current value of the PDB_CHnS_CF field. /
Kojto	90:cb3d968589d8	865	#define BR_PDB_CHnS_CF(x, n) (HW_PDB_CHnS(x, n).B.CF)
Kojto	90:cb3d968589d8	866
Kojto	90:cb3d968589d8	867	/! @brief Format value for bitfield PDB_CHnS_CF. /
Kojto	90:cb3d968589d8	868	#define BF_PDB_CHnS_CF(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_CF) & BM_PDB_CHnS_CF)
Kojto	90:cb3d968589d8	869
Kojto	90:cb3d968589d8	870	/! @brief Set the CF field to a new value. /
Kojto	90:cb3d968589d8	871	#define BW_PDB_CHnS_CF(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_CF) \| BF_PDB_CHnS_CF(v)))
Kojto	90:cb3d968589d8	872	/@}/
Kojto	90:cb3d968589d8	873	/*******************************************************************************
Kojto	90:cb3d968589d8	874	* HW_PDB_CHnDLY0 - Channel n Delay 0 register
Kojto	90:cb3d968589d8	875	******************************************************************************/
Kojto	90:cb3d968589d8	876
Kojto	90:cb3d968589d8	877	/*!
Kojto	90:cb3d968589d8	878	* @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW)
Kojto	90:cb3d968589d8	879	*
Kojto	90:cb3d968589d8	880	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	881	*/
Kojto	90:cb3d968589d8	882	typedef union _hw_pdb_chndly0
Kojto	90:cb3d968589d8	883	{
Kojto	90:cb3d968589d8	884	uint32_t U;
Kojto	90:cb3d968589d8	885	struct _hw_pdb_chndly0_bitfields
Kojto	90:cb3d968589d8	886	{
Kojto	90:cb3d968589d8	887	uint32_t DLY : 16; /!< [15:0] PDB Channel Delay /
Kojto	90:cb3d968589d8	888	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	889	} B;
Kojto	90:cb3d968589d8	890	} hw_pdb_chndly0_t;
Kojto	90:cb3d968589d8	891
Kojto	90:cb3d968589d8	892	/*!
Kojto	90:cb3d968589d8	893	* @name Constants and macros for entire PDB_CHnDLY0 register
Kojto	90:cb3d968589d8	894	*/
Kojto	90:cb3d968589d8	895	/@{/
Kojto	90:cb3d968589d8	896	#define HW_PDB_CHnDLY0_COUNT (2U)
Kojto	90:cb3d968589d8	897
Kojto	90:cb3d968589d8	898	#define HW_PDB_CHnDLY0_ADDR(x, n) ((x) + 0x18U + (0x28U * (n)))
Kojto	90:cb3d968589d8	899
Kojto	90:cb3d968589d8	900	#define HW_PDB_CHnDLY0(x, n) ((__IO hw_pdb_chndly0_t ) HW_PDB_CHnDLY0_ADDR(x, n))
Kojto	90:cb3d968589d8	901	#define HW_PDB_CHnDLY0_RD(x, n) (HW_PDB_CHnDLY0(x, n).U)
Kojto	90:cb3d968589d8	902	#define HW_PDB_CHnDLY0_WR(x, n, v) (HW_PDB_CHnDLY0(x, n).U = (v))
Kojto	90:cb3d968589d8	903	#define HW_PDB_CHnDLY0_SET(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	904	#define HW_PDB_CHnDLY0_CLR(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	905	#define HW_PDB_CHnDLY0_TOG(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	906	/@}/
Kojto	90:cb3d968589d8	907
Kojto	90:cb3d968589d8	908	/*
Kojto	90:cb3d968589d8	909	* Constants & macros for individual PDB_CHnDLY0 bitfields
Kojto	90:cb3d968589d8	910	*/
Kojto	90:cb3d968589d8	911
Kojto	90:cb3d968589d8	912	/*!
Kojto	90:cb3d968589d8	913	* @name Register PDB_CHnDLY0, field DLY[15:0] (RW)
Kojto	90:cb3d968589d8	914	*
Kojto	90:cb3d968589d8	915	* Specifies the delay value for the channel's corresponding pre-trigger. The
Kojto	90:cb3d968589d8	916	* pre-trigger asserts when the counter is equal to DLY. Reading this field returns
Kojto	90:cb3d968589d8	917	* the value of internal register that is effective for the current PDB cycle.
Kojto	90:cb3d968589d8	918	*/
Kojto	90:cb3d968589d8	919	/@{/
Kojto	90:cb3d968589d8	920	#define BP_PDB_CHnDLY0_DLY (0U) /!< Bit position for PDB_CHnDLY0_DLY. /
Kojto	90:cb3d968589d8	921	#define BM_PDB_CHnDLY0_DLY (0x0000FFFFU) /!< Bit mask for PDB_CHnDLY0_DLY. /
Kojto	90:cb3d968589d8	922	#define BS_PDB_CHnDLY0_DLY (16U) /!< Bit field size in bits for PDB_CHnDLY0_DLY. /
Kojto	90:cb3d968589d8	923
Kojto	90:cb3d968589d8	924	/! @brief Read current value of the PDB_CHnDLY0_DLY field. /
Kojto	90:cb3d968589d8	925	#define BR_PDB_CHnDLY0_DLY(x, n) (HW_PDB_CHnDLY0(x, n).B.DLY)
Kojto	90:cb3d968589d8	926
Kojto	90:cb3d968589d8	927	/! @brief Format value for bitfield PDB_CHnDLY0_DLY. /
Kojto	90:cb3d968589d8	928	#define BF_PDB_CHnDLY0_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY0_DLY) & BM_PDB_CHnDLY0_DLY)
Kojto	90:cb3d968589d8	929
Kojto	90:cb3d968589d8	930	/! @brief Set the DLY field to a new value. /
Kojto	90:cb3d968589d8	931	#define BW_PDB_CHnDLY0_DLY(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, (HW_PDB_CHnDLY0_RD(x, n) & ~BM_PDB_CHnDLY0_DLY) \| BF_PDB_CHnDLY0_DLY(v)))
Kojto	90:cb3d968589d8	932	/@}/
Kojto	90:cb3d968589d8	933	/*******************************************************************************
Kojto	90:cb3d968589d8	934	* HW_PDB_CHnDLY1 - Channel n Delay 1 register
Kojto	90:cb3d968589d8	935	******************************************************************************/
Kojto	90:cb3d968589d8	936
Kojto	90:cb3d968589d8	937	/*!
Kojto	90:cb3d968589d8	938	* @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW)
Kojto	90:cb3d968589d8	939	*
Kojto	90:cb3d968589d8	940	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	941	*/
Kojto	90:cb3d968589d8	942	typedef union _hw_pdb_chndly1
Kojto	90:cb3d968589d8	943	{
Kojto	90:cb3d968589d8	944	uint32_t U;
Kojto	90:cb3d968589d8	945	struct _hw_pdb_chndly1_bitfields
Kojto	90:cb3d968589d8	946	{
Kojto	90:cb3d968589d8	947	uint32_t DLY : 16; /!< [15:0] PDB Channel Delay /
Kojto	90:cb3d968589d8	948	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	949	} B;
Kojto	90:cb3d968589d8	950	} hw_pdb_chndly1_t;
Kojto	90:cb3d968589d8	951
Kojto	90:cb3d968589d8	952	/*!
Kojto	90:cb3d968589d8	953	* @name Constants and macros for entire PDB_CHnDLY1 register
Kojto	90:cb3d968589d8	954	*/
Kojto	90:cb3d968589d8	955	/@{/
Kojto	90:cb3d968589d8	956	#define HW_PDB_CHnDLY1_COUNT (2U)
Kojto	90:cb3d968589d8	957
Kojto	90:cb3d968589d8	958	#define HW_PDB_CHnDLY1_ADDR(x, n) ((x) + 0x1CU + (0x28U * (n)))
Kojto	90:cb3d968589d8	959
Kojto	90:cb3d968589d8	960	#define HW_PDB_CHnDLY1(x, n) ((__IO hw_pdb_chndly1_t ) HW_PDB_CHnDLY1_ADDR(x, n))
Kojto	90:cb3d968589d8	961	#define HW_PDB_CHnDLY1_RD(x, n) (HW_PDB_CHnDLY1(x, n).U)
Kojto	90:cb3d968589d8	962	#define HW_PDB_CHnDLY1_WR(x, n, v) (HW_PDB_CHnDLY1(x, n).U = (v))
Kojto	90:cb3d968589d8	963	#define HW_PDB_CHnDLY1_SET(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	964	#define HW_PDB_CHnDLY1_CLR(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	965	#define HW_PDB_CHnDLY1_TOG(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	966	/@}/
Kojto	90:cb3d968589d8	967
Kojto	90:cb3d968589d8	968	/*
Kojto	90:cb3d968589d8	969	* Constants & macros for individual PDB_CHnDLY1 bitfields
Kojto	90:cb3d968589d8	970	*/
Kojto	90:cb3d968589d8	971
Kojto	90:cb3d968589d8	972	/*!
Kojto	90:cb3d968589d8	973	* @name Register PDB_CHnDLY1, field DLY[15:0] (RW)
Kojto	90:cb3d968589d8	974	*
Kojto	90:cb3d968589d8	975	* These bits specify the delay value for the channel's corresponding
Kojto	90:cb3d968589d8	976	* pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these
Kojto	90:cb3d968589d8	977	* bits returns the value of internal register that is effective for the current PDB
Kojto	90:cb3d968589d8	978	* cycle.
Kojto	90:cb3d968589d8	979	*/
Kojto	90:cb3d968589d8	980	/@{/
Kojto	90:cb3d968589d8	981	#define BP_PDB_CHnDLY1_DLY (0U) /!< Bit position for PDB_CHnDLY1_DLY. /
Kojto	90:cb3d968589d8	982	#define BM_PDB_CHnDLY1_DLY (0x0000FFFFU) /!< Bit mask for PDB_CHnDLY1_DLY. /
Kojto	90:cb3d968589d8	983	#define BS_PDB_CHnDLY1_DLY (16U) /!< Bit field size in bits for PDB_CHnDLY1_DLY. /
Kojto	90:cb3d968589d8	984
Kojto	90:cb3d968589d8	985	/! @brief Read current value of the PDB_CHnDLY1_DLY field. /
Kojto	90:cb3d968589d8	986	#define BR_PDB_CHnDLY1_DLY(x, n) (HW_PDB_CHnDLY1(x, n).B.DLY)
Kojto	90:cb3d968589d8	987
Kojto	90:cb3d968589d8	988	/! @brief Format value for bitfield PDB_CHnDLY1_DLY. /
Kojto	90:cb3d968589d8	989	#define BF_PDB_CHnDLY1_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY1_DLY) & BM_PDB_CHnDLY1_DLY)
Kojto	90:cb3d968589d8	990
Kojto	90:cb3d968589d8	991	/! @brief Set the DLY field to a new value. /
Kojto	90:cb3d968589d8	992	#define BW_PDB_CHnDLY1_DLY(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, (HW_PDB_CHnDLY1_RD(x, n) & ~BM_PDB_CHnDLY1_DLY) \| BF_PDB_CHnDLY1_DLY(v)))
Kojto	90:cb3d968589d8	993	/@}/
Kojto	90:cb3d968589d8	994
Kojto	90:cb3d968589d8	995	/*******************************************************************************
Kojto	90:cb3d968589d8	996	* HW_PDB_DACINTCn - DAC Interval Trigger n Control register
Kojto	90:cb3d968589d8	997	******************************************************************************/
Kojto	90:cb3d968589d8	998
Kojto	90:cb3d968589d8	999	/*!
Kojto	90:cb3d968589d8	1000	* @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW)
Kojto	90:cb3d968589d8	1001	*
Kojto	90:cb3d968589d8	1002	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1003	*/
Kojto	90:cb3d968589d8	1004	typedef union _hw_pdb_dacintcn
Kojto	90:cb3d968589d8	1005	{
Kojto	90:cb3d968589d8	1006	uint32_t U;
Kojto	90:cb3d968589d8	1007	struct _hw_pdb_dacintcn_bitfields
Kojto	90:cb3d968589d8	1008	{
Kojto	90:cb3d968589d8	1009	uint32_t TOE : 1; /!< [0] DAC Interval Trigger Enable /
Kojto	90:cb3d968589d8	1010	uint32_t EXT : 1; /!< [1] DAC External Trigger Input Enable /
Kojto	90:cb3d968589d8	1011	uint32_t RESERVED0 : 30; /!< [31:2] /
Kojto	90:cb3d968589d8	1012	} B;
Kojto	90:cb3d968589d8	1013	} hw_pdb_dacintcn_t;
Kojto	90:cb3d968589d8	1014
Kojto	90:cb3d968589d8	1015	/*!
Kojto	90:cb3d968589d8	1016	* @name Constants and macros for entire PDB_DACINTCn register
Kojto	90:cb3d968589d8	1017	*/
Kojto	90:cb3d968589d8	1018	/@{/
Kojto	90:cb3d968589d8	1019	#define HW_PDB_DACINTCn_COUNT (2U)
Kojto	90:cb3d968589d8	1020
Kojto	90:cb3d968589d8	1021	#define HW_PDB_DACINTCn_ADDR(x, n) ((x) + 0x150U + (0x8U * (n)))
Kojto	90:cb3d968589d8	1022
Kojto	90:cb3d968589d8	1023	#define HW_PDB_DACINTCn(x, n) ((__IO hw_pdb_dacintcn_t ) HW_PDB_DACINTCn_ADDR(x, n))
Kojto	90:cb3d968589d8	1024	#define HW_PDB_DACINTCn_RD(x, n) (HW_PDB_DACINTCn(x, n).U)
Kojto	90:cb3d968589d8	1025	#define HW_PDB_DACINTCn_WR(x, n, v) (HW_PDB_DACINTCn(x, n).U = (v))
Kojto	90:cb3d968589d8	1026	#define HW_PDB_DACINTCn_SET(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	1027	#define HW_PDB_DACINTCn_CLR(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	1028	#define HW_PDB_DACINTCn_TOG(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	1029	/@}/
Kojto	90:cb3d968589d8	1030
Kojto	90:cb3d968589d8	1031	/*
Kojto	90:cb3d968589d8	1032	* Constants & macros for individual PDB_DACINTCn bitfields
Kojto	90:cb3d968589d8	1033	*/
Kojto	90:cb3d968589d8	1034
Kojto	90:cb3d968589d8	1035	/*!
Kojto	90:cb3d968589d8	1036	* @name Register PDB_DACINTCn, field TOE[0] (RW)
Kojto	90:cb3d968589d8	1037	*
Kojto	90:cb3d968589d8	1038	* This bit enables the DAC interval trigger.
Kojto	90:cb3d968589d8	1039	*
Kojto	90:cb3d968589d8	1040	* Values:
Kojto	90:cb3d968589d8	1041	* - 0 - DAC interval trigger disabled.
Kojto	90:cb3d968589d8	1042	* - 1 - DAC interval trigger enabled.
Kojto	90:cb3d968589d8	1043	*/
Kojto	90:cb3d968589d8	1044	/@{/
Kojto	90:cb3d968589d8	1045	#define BP_PDB_DACINTCn_TOE (0U) /!< Bit position for PDB_DACINTCn_TOE. /
Kojto	90:cb3d968589d8	1046	#define BM_PDB_DACINTCn_TOE (0x00000001U) /!< Bit mask for PDB_DACINTCn_TOE. /
Kojto	90:cb3d968589d8	1047	#define BS_PDB_DACINTCn_TOE (1U) /!< Bit field size in bits for PDB_DACINTCn_TOE. /
Kojto	90:cb3d968589d8	1048
Kojto	90:cb3d968589d8	1049	/! @brief Read current value of the PDB_DACINTCn_TOE field. /
Kojto	90:cb3d968589d8	1050	#define BR_PDB_DACINTCn_TOE(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE))
Kojto	90:cb3d968589d8	1051
Kojto	90:cb3d968589d8	1052	/! @brief Format value for bitfield PDB_DACINTCn_TOE. /
Kojto	90:cb3d968589d8	1053	#define BF_PDB_DACINTCn_TOE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_TOE) & BM_PDB_DACINTCn_TOE)
Kojto	90:cb3d968589d8	1054
Kojto	90:cb3d968589d8	1055	/! @brief Set the TOE field to a new value. /
Kojto	90:cb3d968589d8	1056	#define BW_PDB_DACINTCn_TOE(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE) = (v))
Kojto	90:cb3d968589d8	1057	/@}/
Kojto	90:cb3d968589d8	1058
Kojto	90:cb3d968589d8	1059	/*!
Kojto	90:cb3d968589d8	1060	* @name Register PDB_DACINTCn, field EXT[1] (RW)
Kojto	90:cb3d968589d8	1061	*
Kojto	90:cb3d968589d8	1062	* Enables the external trigger for DAC interval counter.
Kojto	90:cb3d968589d8	1063	*
Kojto	90:cb3d968589d8	1064	* Values:
Kojto	90:cb3d968589d8	1065	* - 0 - DAC external trigger input disabled. DAC interval counter is reset and
Kojto	90:cb3d968589d8	1066	* counting starts when a rising edge is detected on selected trigger input
Kojto	90:cb3d968589d8	1067	* source or software trigger is selected and SWTRIG is written with 1.
Kojto	90:cb3d968589d8	1068	* - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
Kojto	90:cb3d968589d8	1069	* and DAC external trigger input triggers the DAC interval trigger.
Kojto	90:cb3d968589d8	1070	*/
Kojto	90:cb3d968589d8	1071	/@{/
Kojto	90:cb3d968589d8	1072	#define BP_PDB_DACINTCn_EXT (1U) /!< Bit position for PDB_DACINTCn_EXT. /
Kojto	90:cb3d968589d8	1073	#define BM_PDB_DACINTCn_EXT (0x00000002U) /!< Bit mask for PDB_DACINTCn_EXT. /
Kojto	90:cb3d968589d8	1074	#define BS_PDB_DACINTCn_EXT (1U) /!< Bit field size in bits for PDB_DACINTCn_EXT. /
Kojto	90:cb3d968589d8	1075
Kojto	90:cb3d968589d8	1076	/! @brief Read current value of the PDB_DACINTCn_EXT field. /
Kojto	90:cb3d968589d8	1077	#define BR_PDB_DACINTCn_EXT(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT))
Kojto	90:cb3d968589d8	1078
Kojto	90:cb3d968589d8	1079	/! @brief Format value for bitfield PDB_DACINTCn_EXT. /
Kojto	90:cb3d968589d8	1080	#define BF_PDB_DACINTCn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_EXT) & BM_PDB_DACINTCn_EXT)
Kojto	90:cb3d968589d8	1081
Kojto	90:cb3d968589d8	1082	/! @brief Set the EXT field to a new value. /
Kojto	90:cb3d968589d8	1083	#define BW_PDB_DACINTCn_EXT(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT) = (v))
Kojto	90:cb3d968589d8	1084	/@}/
Kojto	90:cb3d968589d8	1085	/*******************************************************************************
Kojto	90:cb3d968589d8	1086	* HW_PDB_DACINTn - DAC Interval n register
Kojto	90:cb3d968589d8	1087	******************************************************************************/
Kojto	90:cb3d968589d8	1088
Kojto	90:cb3d968589d8	1089	/*!
Kojto	90:cb3d968589d8	1090	* @brief HW_PDB_DACINTn - DAC Interval n register (RW)
Kojto	90:cb3d968589d8	1091	*
Kojto	90:cb3d968589d8	1092	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1093	*/
Kojto	90:cb3d968589d8	1094	typedef union _hw_pdb_dacintn
Kojto	90:cb3d968589d8	1095	{
Kojto	90:cb3d968589d8	1096	uint32_t U;
Kojto	90:cb3d968589d8	1097	struct _hw_pdb_dacintn_bitfields
Kojto	90:cb3d968589d8	1098	{
Kojto	90:cb3d968589d8	1099	uint32_t INT : 16; /!< [15:0] DAC Interval /
Kojto	90:cb3d968589d8	1100	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	1101	} B;
Kojto	90:cb3d968589d8	1102	} hw_pdb_dacintn_t;
Kojto	90:cb3d968589d8	1103
Kojto	90:cb3d968589d8	1104	/*!
Kojto	90:cb3d968589d8	1105	* @name Constants and macros for entire PDB_DACINTn register
Kojto	90:cb3d968589d8	1106	*/
Kojto	90:cb3d968589d8	1107	/@{/
Kojto	90:cb3d968589d8	1108	#define HW_PDB_DACINTn_COUNT (2U)
Kojto	90:cb3d968589d8	1109
Kojto	90:cb3d968589d8	1110	#define HW_PDB_DACINTn_ADDR(x, n) ((x) + 0x154U + (0x8U * (n)))
Kojto	90:cb3d968589d8	1111
Kojto	90:cb3d968589d8	1112	#define HW_PDB_DACINTn(x, n) ((__IO hw_pdb_dacintn_t ) HW_PDB_DACINTn_ADDR(x, n))
Kojto	90:cb3d968589d8	1113	#define HW_PDB_DACINTn_RD(x, n) (HW_PDB_DACINTn(x, n).U)
Kojto	90:cb3d968589d8	1114	#define HW_PDB_DACINTn_WR(x, n, v) (HW_PDB_DACINTn(x, n).U = (v))
Kojto	90:cb3d968589d8	1115	#define HW_PDB_DACINTn_SET(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	1116	#define HW_PDB_DACINTn_CLR(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	1117	#define HW_PDB_DACINTn_TOG(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	1118	/@}/
Kojto	90:cb3d968589d8	1119
Kojto	90:cb3d968589d8	1120	/*
Kojto	90:cb3d968589d8	1121	* Constants & macros for individual PDB_DACINTn bitfields
Kojto	90:cb3d968589d8	1122	*/
Kojto	90:cb3d968589d8	1123
Kojto	90:cb3d968589d8	1124	/*!
Kojto	90:cb3d968589d8	1125	* @name Register PDB_DACINTn, field INT[15:0] (RW)
Kojto	90:cb3d968589d8	1126	*
Kojto	90:cb3d968589d8	1127	* Specifies the interval value for DAC interval trigger. DAC interval trigger
Kojto	90:cb3d968589d8	1128	* triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
Kojto	90:cb3d968589d8	1129	* Reading this field returns the value of internal register that is effective
Kojto	90:cb3d968589d8	1130	* for the current PDB cycle.
Kojto	90:cb3d968589d8	1131	*/
Kojto	90:cb3d968589d8	1132	/@{/
Kojto	90:cb3d968589d8	1133	#define BP_PDB_DACINTn_INT (0U) /!< Bit position for PDB_DACINTn_INT. /
Kojto	90:cb3d968589d8	1134	#define BM_PDB_DACINTn_INT (0x0000FFFFU) /!< Bit mask for PDB_DACINTn_INT. /
Kojto	90:cb3d968589d8	1135	#define BS_PDB_DACINTn_INT (16U) /!< Bit field size in bits for PDB_DACINTn_INT. /
Kojto	90:cb3d968589d8	1136
Kojto	90:cb3d968589d8	1137	/! @brief Read current value of the PDB_DACINTn_INT field. /
Kojto	90:cb3d968589d8	1138	#define BR_PDB_DACINTn_INT(x, n) (HW_PDB_DACINTn(x, n).B.INT)
Kojto	90:cb3d968589d8	1139
Kojto	90:cb3d968589d8	1140	/! @brief Format value for bitfield PDB_DACINTn_INT. /
Kojto	90:cb3d968589d8	1141	#define BF_PDB_DACINTn_INT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTn_INT) & BM_PDB_DACINTn_INT)
Kojto	90:cb3d968589d8	1142
Kojto	90:cb3d968589d8	1143	/! @brief Set the INT field to a new value. /
Kojto	90:cb3d968589d8	1144	#define BW_PDB_DACINTn_INT(x, n, v) (HW_PDB_DACINTn_WR(x, n, (HW_PDB_DACINTn_RD(x, n) & ~BM_PDB_DACINTn_INT) \| BF_PDB_DACINTn_INT(v)))
Kojto	90:cb3d968589d8	1145	/@}/
Kojto	90:cb3d968589d8	1146
Kojto	90:cb3d968589d8	1147	/*******************************************************************************
Kojto	90:cb3d968589d8	1148	* HW_PDB_POEN - Pulse-Out n Enable register
Kojto	90:cb3d968589d8	1149	******************************************************************************/
Kojto	90:cb3d968589d8	1150
Kojto	90:cb3d968589d8	1151	/*!
Kojto	90:cb3d968589d8	1152	* @brief HW_PDB_POEN - Pulse-Out n Enable register (RW)
Kojto	90:cb3d968589d8	1153	*
Kojto	90:cb3d968589d8	1154	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1155	*/
Kojto	90:cb3d968589d8	1156	typedef union _hw_pdb_poen
Kojto	90:cb3d968589d8	1157	{
Kojto	90:cb3d968589d8	1158	uint32_t U;
Kojto	90:cb3d968589d8	1159	struct _hw_pdb_poen_bitfields
Kojto	90:cb3d968589d8	1160	{
Kojto	90:cb3d968589d8	1161	uint32_t POEN : 8; /!< [7:0] PDB Pulse-Out Enable /
Kojto	90:cb3d968589d8	1162	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	1163	} B;
Kojto	90:cb3d968589d8	1164	} hw_pdb_poen_t;
Kojto	90:cb3d968589d8	1165
Kojto	90:cb3d968589d8	1166	/*!
Kojto	90:cb3d968589d8	1167	* @name Constants and macros for entire PDB_POEN register
Kojto	90:cb3d968589d8	1168	*/
Kojto	90:cb3d968589d8	1169	/@{/
Kojto	90:cb3d968589d8	1170	#define HW_PDB_POEN_ADDR(x) ((x) + 0x190U)
Kojto	90:cb3d968589d8	1171
Kojto	90:cb3d968589d8	1172	#define HW_PDB_POEN(x) ((__IO hw_pdb_poen_t ) HW_PDB_POEN_ADDR(x))
Kojto	90:cb3d968589d8	1173	#define HW_PDB_POEN_RD(x) (HW_PDB_POEN(x).U)
Kojto	90:cb3d968589d8	1174	#define HW_PDB_POEN_WR(x, v) (HW_PDB_POEN(x).U = (v))
Kojto	90:cb3d968589d8	1175	#define HW_PDB_POEN_SET(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1176	#define HW_PDB_POEN_CLR(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1177	#define HW_PDB_POEN_TOG(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1178	/@}/
Kojto	90:cb3d968589d8	1179
Kojto	90:cb3d968589d8	1180	/*
Kojto	90:cb3d968589d8	1181	* Constants & macros for individual PDB_POEN bitfields
Kojto	90:cb3d968589d8	1182	*/
Kojto	90:cb3d968589d8	1183
Kojto	90:cb3d968589d8	1184	/*!
Kojto	90:cb3d968589d8	1185	* @name Register PDB_POEN, field POEN[7:0] (RW)
Kojto	90:cb3d968589d8	1186	*
Kojto	90:cb3d968589d8	1187	* Enables the pulse output. Only lower Y bits are implemented in this MCU.
Kojto	90:cb3d968589d8	1188	*
Kojto	90:cb3d968589d8	1189	* Values:
Kojto	90:cb3d968589d8	1190	* - 0 - PDB Pulse-Out disabled
Kojto	90:cb3d968589d8	1191	* - 1 - PDB Pulse-Out enabled
Kojto	90:cb3d968589d8	1192	*/
Kojto	90:cb3d968589d8	1193	/@{/
Kojto	90:cb3d968589d8	1194	#define BP_PDB_POEN_POEN (0U) /!< Bit position for PDB_POEN_POEN. /
Kojto	90:cb3d968589d8	1195	#define BM_PDB_POEN_POEN (0x000000FFU) /!< Bit mask for PDB_POEN_POEN. /
Kojto	90:cb3d968589d8	1196	#define BS_PDB_POEN_POEN (8U) /!< Bit field size in bits for PDB_POEN_POEN. /
Kojto	90:cb3d968589d8	1197
Kojto	90:cb3d968589d8	1198	/! @brief Read current value of the PDB_POEN_POEN field. /
Kojto	90:cb3d968589d8	1199	#define BR_PDB_POEN_POEN(x) (HW_PDB_POEN(x).B.POEN)
Kojto	90:cb3d968589d8	1200
Kojto	90:cb3d968589d8	1201	/! @brief Format value for bitfield PDB_POEN_POEN. /
Kojto	90:cb3d968589d8	1202	#define BF_PDB_POEN_POEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POEN_POEN) & BM_PDB_POEN_POEN)
Kojto	90:cb3d968589d8	1203
Kojto	90:cb3d968589d8	1204	/! @brief Set the POEN field to a new value. /
Kojto	90:cb3d968589d8	1205	#define BW_PDB_POEN_POEN(x, v) (HW_PDB_POEN_WR(x, (HW_PDB_POEN_RD(x) & ~BM_PDB_POEN_POEN) \| BF_PDB_POEN_POEN(v)))
Kojto	90:cb3d968589d8	1206	/@}/
Kojto	90:cb3d968589d8	1207
Kojto	90:cb3d968589d8	1208	/*******************************************************************************
Kojto	90:cb3d968589d8	1209	* HW_PDB_POnDLY - Pulse-Out n Delay register
Kojto	90:cb3d968589d8	1210	******************************************************************************/
Kojto	90:cb3d968589d8	1211
Kojto	90:cb3d968589d8	1212	/*!
Kojto	90:cb3d968589d8	1213	* @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW)
Kojto	90:cb3d968589d8	1214	*
Kojto	90:cb3d968589d8	1215	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1216	*/
Kojto	90:cb3d968589d8	1217	typedef union _hw_pdb_pondly
Kojto	90:cb3d968589d8	1218	{
Kojto	90:cb3d968589d8	1219	uint32_t U;
Kojto	90:cb3d968589d8	1220	struct _hw_pdb_pondly_bitfields
Kojto	90:cb3d968589d8	1221	{
Kojto	90:cb3d968589d8	1222	uint32_t DLY2 : 16; /!< [15:0] PDB Pulse-Out Delay 2 /
Kojto	90:cb3d968589d8	1223	uint32_t DLY1 : 16; /!< [31:16] PDB Pulse-Out Delay 1 /
Kojto	90:cb3d968589d8	1224	} B;
Kojto	90:cb3d968589d8	1225	} hw_pdb_pondly_t;
Kojto	90:cb3d968589d8	1226
Kojto	90:cb3d968589d8	1227	/*!
Kojto	90:cb3d968589d8	1228	* @name Constants and macros for entire PDB_POnDLY register
Kojto	90:cb3d968589d8	1229	*/
Kojto	90:cb3d968589d8	1230	/@{/
Kojto	90:cb3d968589d8	1231	#define HW_PDB_POnDLY_COUNT (3U)
Kojto	90:cb3d968589d8	1232
Kojto	90:cb3d968589d8	1233	#define HW_PDB_POnDLY_ADDR(x, n) ((x) + 0x194U + (0x4U * (n)))
Kojto	90:cb3d968589d8	1234
Kojto	90:cb3d968589d8	1235	#define HW_PDB_POnDLY(x, n) ((__IO hw_pdb_pondly_t ) HW_PDB_POnDLY_ADDR(x, n))
Kojto	90:cb3d968589d8	1236	#define HW_PDB_POnDLY_RD(x, n) (HW_PDB_POnDLY(x, n).U)
Kojto	90:cb3d968589d8	1237	#define HW_PDB_POnDLY_WR(x, n, v) (HW_PDB_POnDLY(x, n).U = (v))
Kojto	90:cb3d968589d8	1238	#define HW_PDB_POnDLY_SET(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	1239	#define HW_PDB_POnDLY_CLR(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	1240	#define HW_PDB_POnDLY_TOG(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	1241	/@}/
Kojto	90:cb3d968589d8	1242
Kojto	90:cb3d968589d8	1243	/*
Kojto	90:cb3d968589d8	1244	* Constants & macros for individual PDB_POnDLY bitfields
Kojto	90:cb3d968589d8	1245	*/
Kojto	90:cb3d968589d8	1246
Kojto	90:cb3d968589d8	1247	/*!
Kojto	90:cb3d968589d8	1248	* @name Register PDB_POnDLY, field DLY2[15:0] (RW)
Kojto	90:cb3d968589d8	1249	*
Kojto	90:cb3d968589d8	1250	* These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
Kojto	90:cb3d968589d8	1251	* low when the PDB counter is equal to the DLY2. Reading these bits returns the
Kojto	90:cb3d968589d8	1252	* value of internal register that is effective for the current PDB cycle.
Kojto	90:cb3d968589d8	1253	*/
Kojto	90:cb3d968589d8	1254	/@{/
Kojto	90:cb3d968589d8	1255	#define BP_PDB_POnDLY_DLY2 (0U) /!< Bit position for PDB_POnDLY_DLY2. /
Kojto	90:cb3d968589d8	1256	#define BM_PDB_POnDLY_DLY2 (0x0000FFFFU) /!< Bit mask for PDB_POnDLY_DLY2. /
Kojto	90:cb3d968589d8	1257	#define BS_PDB_POnDLY_DLY2 (16U) /!< Bit field size in bits for PDB_POnDLY_DLY2. /
Kojto	90:cb3d968589d8	1258
Kojto	90:cb3d968589d8	1259	/! @brief Read current value of the PDB_POnDLY_DLY2 field. /
Kojto	90:cb3d968589d8	1260	#define BR_PDB_POnDLY_DLY2(x, n) (HW_PDB_POnDLY(x, n).B.DLY2)
Kojto	90:cb3d968589d8	1261
Kojto	90:cb3d968589d8	1262	/! @brief Format value for bitfield PDB_POnDLY_DLY2. /
Kojto	90:cb3d968589d8	1263	#define BF_PDB_POnDLY_DLY2(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY2) & BM_PDB_POnDLY_DLY2)
Kojto	90:cb3d968589d8	1264
Kojto	90:cb3d968589d8	1265	/! @brief Set the DLY2 field to a new value. /
Kojto	90:cb3d968589d8	1266	#define BW_PDB_POnDLY_DLY2(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY2) \| BF_PDB_POnDLY_DLY2(v)))
Kojto	90:cb3d968589d8	1267	/@}/
Kojto	90:cb3d968589d8	1268
Kojto	90:cb3d968589d8	1269	/*!
Kojto	90:cb3d968589d8	1270	* @name Register PDB_POnDLY, field DLY1[31:16] (RW)
Kojto	90:cb3d968589d8	1271	*
Kojto	90:cb3d968589d8	1272	* These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
Kojto	90:cb3d968589d8	1273	* high when the PDB counter is equal to the DLY1. Reading these bits returns the
Kojto	90:cb3d968589d8	1274	* value of internal register that is effective for the current PDB cycle.
Kojto	90:cb3d968589d8	1275	*/
Kojto	90:cb3d968589d8	1276	/@{/
Kojto	90:cb3d968589d8	1277	#define BP_PDB_POnDLY_DLY1 (16U) /!< Bit position for PDB_POnDLY_DLY1. /
Kojto	90:cb3d968589d8	1278	#define BM_PDB_POnDLY_DLY1 (0xFFFF0000U) /!< Bit mask for PDB_POnDLY_DLY1. /
Kojto	90:cb3d968589d8	1279	#define BS_PDB_POnDLY_DLY1 (16U) /!< Bit field size in bits for PDB_POnDLY_DLY1. /
Kojto	90:cb3d968589d8	1280
Kojto	90:cb3d968589d8	1281	/! @brief Read current value of the PDB_POnDLY_DLY1 field. /
Kojto	90:cb3d968589d8	1282	#define BR_PDB_POnDLY_DLY1(x, n) (HW_PDB_POnDLY(x, n).B.DLY1)
Kojto	90:cb3d968589d8	1283
Kojto	90:cb3d968589d8	1284	/! @brief Format value for bitfield PDB_POnDLY_DLY1. /
Kojto	90:cb3d968589d8	1285	#define BF_PDB_POnDLY_DLY1(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY1) & BM_PDB_POnDLY_DLY1)
Kojto	90:cb3d968589d8	1286
Kojto	90:cb3d968589d8	1287	/! @brief Set the DLY1 field to a new value. /
Kojto	90:cb3d968589d8	1288	#define BW_PDB_POnDLY_DLY1(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY1) \| BF_PDB_POnDLY_DLY1(v)))
Kojto	90:cb3d968589d8	1289	/@}/
Kojto	90:cb3d968589d8	1290
Kojto	90:cb3d968589d8	1291	/*******************************************************************************
Kojto	90:cb3d968589d8	1292	* hw_pdb_t - module struct
Kojto	90:cb3d968589d8	1293	******************************************************************************/
Kojto	90:cb3d968589d8	1294	/*!
Kojto	90:cb3d968589d8	1295	* @brief All PDB module registers.
Kojto	90:cb3d968589d8	1296	*/
Kojto	90:cb3d968589d8	1297	#pragma pack(1)
Kojto	90:cb3d968589d8	1298	typedef struct _hw_pdb
Kojto	90:cb3d968589d8	1299	{
Kojto	90:cb3d968589d8	1300	__IO hw_pdb_sc_t SC; /!< [0x0] Status and Control register /
Kojto	90:cb3d968589d8	1301	__IO hw_pdb_mod_t MOD; /!< [0x4] Modulus register /
Kojto	90:cb3d968589d8	1302	__I hw_pdb_cnt_t CNT; /!< [0x8] Counter register /
Kojto	90:cb3d968589d8	1303	__IO hw_pdb_idly_t IDLY; /!< [0xC] Interrupt Delay register /
Kojto	90:cb3d968589d8	1304	struct {
Kojto	90:cb3d968589d8	1305	__IO hw_pdb_chnc1_t CHnC1; /!< [0x10] Channel n Control register 1 /
Kojto	90:cb3d968589d8	1306	__IO hw_pdb_chns_t CHnS; /!< [0x14] Channel n Status register /
Kojto	90:cb3d968589d8	1307	__IO hw_pdb_chndly0_t CHnDLY0; /!< [0x18] Channel n Delay 0 register /
Kojto	90:cb3d968589d8	1308	__IO hw_pdb_chndly1_t CHnDLY1; /!< [0x1C] Channel n Delay 1 register /
Kojto	90:cb3d968589d8	1309	uint8_t _reserved0[24];
Kojto	90:cb3d968589d8	1310	} CH[2];
Kojto	90:cb3d968589d8	1311	uint8_t _reserved0[240];
Kojto	90:cb3d968589d8	1312	struct {
Kojto	90:cb3d968589d8	1313	__IO hw_pdb_dacintcn_t DACINTCn; /!< [0x150] DAC Interval Trigger n Control register /
Kojto	90:cb3d968589d8	1314	__IO hw_pdb_dacintn_t DACINTn; /!< [0x154] DAC Interval n register /
Kojto	90:cb3d968589d8	1315	} DAC[2];
Kojto	90:cb3d968589d8	1316	uint8_t _reserved1[48];
Kojto	90:cb3d968589d8	1317	__IO hw_pdb_poen_t POEN; /!< [0x190] Pulse-Out n Enable register /
Kojto	90:cb3d968589d8	1318	__IO hw_pdb_pondly_t POnDLY[3]; /!< [0x194] Pulse-Out n Delay register /
Kojto	90:cb3d968589d8	1319	} hw_pdb_t;
Kojto	90:cb3d968589d8	1320	#pragma pack()
Kojto	90:cb3d968589d8	1321
Kojto	90:cb3d968589d8	1322	/! @brief Macro to access all PDB registers. /
Kojto	90:cb3d968589d8	1323	/! @param x PDB module instance base address. /
Kojto	90:cb3d968589d8	1324	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto	90:cb3d968589d8	1325	* use the '&' operator, like <code>&HW_PDB(PDB0_BASE)</code>. */
Kojto	90:cb3d968589d8	1326	#define HW_PDB(x) ((hw_pdb_t )(x))
Kojto	90:cb3d968589d8	1327
Kojto	90:cb3d968589d8	1328	#endif /* __HW_PDB_REGISTERS_H__ */
Kojto	90:cb3d968589d8	1329	/* EOF */