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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mcg.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:: Kojto
Date:: Wed Aug 05 13:16:35 2015 +0100
Revision:: 104:b9ad9a133dc7
Parent:: 90:cb3d968589d8

Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/*
Kojto	90:cb3d968589d8	2	** ###################################################################
Kojto	90:cb3d968589d8	3	** Compilers: Keil ARM C/C++ Compiler
Kojto	90:cb3d968589d8	4	** Freescale C/C++ for Embedded ARM
Kojto	90:cb3d968589d8	5	** GNU C Compiler
Kojto	90:cb3d968589d8	6	** IAR ANSI C/C++ Compiler for ARM
Kojto	90:cb3d968589d8	7	**
Kojto	90:cb3d968589d8	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto	90:cb3d968589d8	9	** Version: rev. 2.5, 2014-02-10
Kojto	90:cb3d968589d8	10	** Build: b140604
Kojto	90:cb3d968589d8	11	**
Kojto	90:cb3d968589d8	12	** Abstract:
Kojto	90:cb3d968589d8	13	** Extension to the CMSIS register access layer header.
Kojto	90:cb3d968589d8	14	**
Kojto	90:cb3d968589d8	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto	90:cb3d968589d8	16	** All rights reserved.
Kojto	90:cb3d968589d8	17	**
Kojto	90:cb3d968589d8	18	** Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	19	** are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	20	**
Kojto	90:cb3d968589d8	21	** o Redistributions of source code must retain the above copyright notice, this list
Kojto	90:cb3d968589d8	22	** of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	**
Kojto	90:cb3d968589d8	24	** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto	90:cb3d968589d8	25	** list of conditions and the following disclaimer in the documentation and/or
Kojto	90:cb3d968589d8	26	** other materials provided with the distribution.
Kojto	90:cb3d968589d8	27	**
Kojto	90:cb3d968589d8	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto	90:cb3d968589d8	29	** contributors may be used to endorse or promote products derived from this
Kojto	90:cb3d968589d8	30	** software without specific prior written permission.
Kojto	90:cb3d968589d8	31	**
Kojto	90:cb3d968589d8	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	90:cb3d968589d8	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	90:cb3d968589d8	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	90:cb3d968589d8	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	90:cb3d968589d8	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	90:cb3d968589d8	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	90:cb3d968589d8	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	90:cb3d968589d8	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	90:cb3d968589d8	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	42	**
Kojto	90:cb3d968589d8	43	** http: www.freescale.com
Kojto	90:cb3d968589d8	44	** mail: support@freescale.com
Kojto	90:cb3d968589d8	45	**
Kojto	90:cb3d968589d8	46	** Revisions:
Kojto	90:cb3d968589d8	47	** - rev. 1.0 (2013-08-12)
Kojto	90:cb3d968589d8	48	** Initial version.
Kojto	90:cb3d968589d8	49	** - rev. 2.0 (2013-10-29)
Kojto	90:cb3d968589d8	50	** Register accessor macros added to the memory map.
Kojto	90:cb3d968589d8	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto	90:cb3d968589d8	52	** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto	90:cb3d968589d8	53	** System initialization updated.
Kojto	90:cb3d968589d8	54	** MCG - registers updated.
Kojto	90:cb3d968589d8	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto	90:cb3d968589d8	56	** - rev. 2.1 (2013-10-30)
Kojto	90:cb3d968589d8	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto	90:cb3d968589d8	58	** - rev. 2.2 (2013-12-09)
Kojto	90:cb3d968589d8	59	** DMA - EARS register removed.
Kojto	90:cb3d968589d8	60	** AIPS0, AIPS1 - MPRA register updated.
Kojto	90:cb3d968589d8	61	** - rev. 2.3 (2014-01-24)
Kojto	90:cb3d968589d8	62	** Update according to reference manual rev. 2
Kojto	90:cb3d968589d8	63	** ENET, MCG, MCM, SIM, USB - registers updated
Kojto	90:cb3d968589d8	64	** - rev. 2.4 (2014-02-10)
Kojto	90:cb3d968589d8	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	67	** - rev. 2.5 (2014-02-10)
Kojto	90:cb3d968589d8	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto	90:cb3d968589d8	71	**
Kojto	90:cb3d968589d8	72	** ###################################################################
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/*
Kojto	90:cb3d968589d8	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto	90:cb3d968589d8	77	*
Kojto	90:cb3d968589d8	78	* This file was generated automatically and any changes may be lost.
Kojto	90:cb3d968589d8	79	*/
Kojto	90:cb3d968589d8	80	#ifndef __HW_MCG_REGISTERS_H__
Kojto	90:cb3d968589d8	81	#define __HW_MCG_REGISTERS_H__
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	#include "MK64F12.h"
Kojto	90:cb3d968589d8	84	#include "fsl_bitaccess.h"
Kojto	90:cb3d968589d8	85
Kojto	90:cb3d968589d8	86	/*
Kojto	90:cb3d968589d8	87	* MK64F12 MCG
Kojto	90:cb3d968589d8	88	*
Kojto	90:cb3d968589d8	89	* Multipurpose Clock Generator module
Kojto	90:cb3d968589d8	90	*
Kojto	90:cb3d968589d8	91	* Registers defined in this header file:
Kojto	90:cb3d968589d8	92	* - HW_MCG_C1 - MCG Control 1 Register
Kojto	90:cb3d968589d8	93	* - HW_MCG_C2 - MCG Control 2 Register
Kojto	90:cb3d968589d8	94	* - HW_MCG_C3 - MCG Control 3 Register
Kojto	90:cb3d968589d8	95	* - HW_MCG_C4 - MCG Control 4 Register
Kojto	90:cb3d968589d8	96	* - HW_MCG_C5 - MCG Control 5 Register
Kojto	90:cb3d968589d8	97	* - HW_MCG_C6 - MCG Control 6 Register
Kojto	90:cb3d968589d8	98	* - HW_MCG_S - MCG Status Register
Kojto	90:cb3d968589d8	99	* - HW_MCG_SC - MCG Status and Control Register
Kojto	90:cb3d968589d8	100	* - HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
Kojto	90:cb3d968589d8	101	* - HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
Kojto	90:cb3d968589d8	102	* - HW_MCG_C7 - MCG Control 7 Register
Kojto	90:cb3d968589d8	103	* - HW_MCG_C8 - MCG Control 8 Register
Kojto	90:cb3d968589d8	104	*
Kojto	90:cb3d968589d8	105	* - hw_mcg_t - Struct containing all module registers.
Kojto	90:cb3d968589d8	106	*/
Kojto	90:cb3d968589d8	107
Kojto	90:cb3d968589d8	108	#define HW_MCG_INSTANCE_COUNT (1U) /!< Number of instances of the MCG module. /
Kojto	90:cb3d968589d8	109
Kojto	90:cb3d968589d8	110	/*******************************************************************************
Kojto	90:cb3d968589d8	111	* HW_MCG_C1 - MCG Control 1 Register
Kojto	90:cb3d968589d8	112	******************************************************************************/
Kojto	90:cb3d968589d8	113
Kojto	90:cb3d968589d8	114	/*!
Kojto	90:cb3d968589d8	115	* @brief HW_MCG_C1 - MCG Control 1 Register (RW)
Kojto	90:cb3d968589d8	116	*
Kojto	90:cb3d968589d8	117	* Reset value: 0x04U
Kojto	90:cb3d968589d8	118	*/
Kojto	90:cb3d968589d8	119	typedef union _hw_mcg_c1
Kojto	90:cb3d968589d8	120	{
Kojto	90:cb3d968589d8	121	uint8_t U;
Kojto	90:cb3d968589d8	122	struct _hw_mcg_c1_bitfields
Kojto	90:cb3d968589d8	123	{
Kojto	90:cb3d968589d8	124	uint8_t IREFSTEN : 1; /!< [0] Internal Reference Stop Enable /
Kojto	90:cb3d968589d8	125	uint8_t IRCLKEN : 1; /!< [1] Internal Reference Clock Enable /
Kojto	90:cb3d968589d8	126	uint8_t IREFS : 1; /!< [2] Internal Reference Select /
Kojto	90:cb3d968589d8	127	uint8_t FRDIV : 3; /!< [5:3] FLL External Reference Divider /
Kojto	90:cb3d968589d8	128	uint8_t CLKS : 2; /!< [7:6] Clock Source Select /
Kojto	90:cb3d968589d8	129	} B;
Kojto	90:cb3d968589d8	130	} hw_mcg_c1_t;
Kojto	90:cb3d968589d8	131
Kojto	90:cb3d968589d8	132	/*!
Kojto	90:cb3d968589d8	133	* @name Constants and macros for entire MCG_C1 register
Kojto	90:cb3d968589d8	134	*/
Kojto	90:cb3d968589d8	135	/@{/
Kojto	90:cb3d968589d8	136	#define HW_MCG_C1_ADDR(x) ((x) + 0x0U)
Kojto	90:cb3d968589d8	137
Kojto	90:cb3d968589d8	138	#define HW_MCG_C1(x) ((__IO hw_mcg_c1_t ) HW_MCG_C1_ADDR(x))
Kojto	90:cb3d968589d8	139	#define HW_MCG_C1_RD(x) (HW_MCG_C1(x).U)
Kojto	90:cb3d968589d8	140	#define HW_MCG_C1_WR(x, v) (HW_MCG_C1(x).U = (v))
Kojto	90:cb3d968589d8	141	#define HW_MCG_C1_SET(x, v) (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	142	#define HW_MCG_C1_CLR(x, v) (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	143	#define HW_MCG_C1_TOG(x, v) (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	144	/@}/
Kojto	90:cb3d968589d8	145
Kojto	90:cb3d968589d8	146	/*
Kojto	90:cb3d968589d8	147	* Constants & macros for individual MCG_C1 bitfields
Kojto	90:cb3d968589d8	148	*/
Kojto	90:cb3d968589d8	149
Kojto	90:cb3d968589d8	150	/*!
Kojto	90:cb3d968589d8	151	* @name Register MCG_C1, field IREFSTEN[0] (RW)
Kojto	90:cb3d968589d8	152	*
Kojto	90:cb3d968589d8	153	* Controls whether or not the internal reference clock remains enabled when the
Kojto	90:cb3d968589d8	154	* MCG enters Stop mode.
Kojto	90:cb3d968589d8	155	*
Kojto	90:cb3d968589d8	156	* Values:
Kojto	90:cb3d968589d8	157	* - 0 - Internal reference clock is disabled in Stop mode.
Kojto	90:cb3d968589d8	158	* - 1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
Kojto	90:cb3d968589d8	159	* if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
Kojto	90:cb3d968589d8	160	*/
Kojto	90:cb3d968589d8	161	/@{/
Kojto	90:cb3d968589d8	162	#define BP_MCG_C1_IREFSTEN (0U) /!< Bit position for MCG_C1_IREFSTEN. /
Kojto	90:cb3d968589d8	163	#define BM_MCG_C1_IREFSTEN (0x01U) /!< Bit mask for MCG_C1_IREFSTEN. /
Kojto	90:cb3d968589d8	164	#define BS_MCG_C1_IREFSTEN (1U) /!< Bit field size in bits for MCG_C1_IREFSTEN. /
Kojto	90:cb3d968589d8	165
Kojto	90:cb3d968589d8	166	/! @brief Read current value of the MCG_C1_IREFSTEN field. /
Kojto	90:cb3d968589d8	167	#define BR_MCG_C1_IREFSTEN(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFSTEN))
Kojto	90:cb3d968589d8	168
Kojto	90:cb3d968589d8	169	/! @brief Format value for bitfield MCG_C1_IREFSTEN. /
Kojto	90:cb3d968589d8	170	#define BF_MCG_C1_IREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IREFSTEN) & BM_MCG_C1_IREFSTEN)
Kojto	90:cb3d968589d8	171
Kojto	90:cb3d968589d8	172	/! @brief Set the IREFSTEN field to a new value. /
Kojto	90:cb3d968589d8	173	#define BW_MCG_C1_IREFSTEN(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFSTEN) = (v))
Kojto	90:cb3d968589d8	174	/@}/
Kojto	90:cb3d968589d8	175
Kojto	90:cb3d968589d8	176	/*!
Kojto	90:cb3d968589d8	177	* @name Register MCG_C1, field IRCLKEN[1] (RW)
Kojto	90:cb3d968589d8	178	*
Kojto	90:cb3d968589d8	179	* Enables the internal reference clock for use as MCGIRCLK.
Kojto	90:cb3d968589d8	180	*
Kojto	90:cb3d968589d8	181	* Values:
Kojto	90:cb3d968589d8	182	* - 0 - MCGIRCLK inactive.
Kojto	90:cb3d968589d8	183	* - 1 - MCGIRCLK active.
Kojto	90:cb3d968589d8	184	*/
Kojto	90:cb3d968589d8	185	/@{/
Kojto	90:cb3d968589d8	186	#define BP_MCG_C1_IRCLKEN (1U) /!< Bit position for MCG_C1_IRCLKEN. /
Kojto	90:cb3d968589d8	187	#define BM_MCG_C1_IRCLKEN (0x02U) /!< Bit mask for MCG_C1_IRCLKEN. /
Kojto	90:cb3d968589d8	188	#define BS_MCG_C1_IRCLKEN (1U) /!< Bit field size in bits for MCG_C1_IRCLKEN. /
Kojto	90:cb3d968589d8	189
Kojto	90:cb3d968589d8	190	/! @brief Read current value of the MCG_C1_IRCLKEN field. /
Kojto	90:cb3d968589d8	191	#define BR_MCG_C1_IRCLKEN(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IRCLKEN))
Kojto	90:cb3d968589d8	192
Kojto	90:cb3d968589d8	193	/! @brief Format value for bitfield MCG_C1_IRCLKEN. /
Kojto	90:cb3d968589d8	194	#define BF_MCG_C1_IRCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IRCLKEN) & BM_MCG_C1_IRCLKEN)
Kojto	90:cb3d968589d8	195
Kojto	90:cb3d968589d8	196	/! @brief Set the IRCLKEN field to a new value. /
Kojto	90:cb3d968589d8	197	#define BW_MCG_C1_IRCLKEN(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IRCLKEN) = (v))
Kojto	90:cb3d968589d8	198	/@}/
Kojto	90:cb3d968589d8	199
Kojto	90:cb3d968589d8	200	/*!
Kojto	90:cb3d968589d8	201	* @name Register MCG_C1, field IREFS[2] (RW)
Kojto	90:cb3d968589d8	202	*
Kojto	90:cb3d968589d8	203	* Selects the reference clock source for the FLL.
Kojto	90:cb3d968589d8	204	*
Kojto	90:cb3d968589d8	205	* Values:
Kojto	90:cb3d968589d8	206	* - 0 - External reference clock is selected.
Kojto	90:cb3d968589d8	207	* - 1 - The slow internal reference clock is selected.
Kojto	90:cb3d968589d8	208	*/
Kojto	90:cb3d968589d8	209	/@{/
Kojto	90:cb3d968589d8	210	#define BP_MCG_C1_IREFS (2U) /!< Bit position for MCG_C1_IREFS. /
Kojto	90:cb3d968589d8	211	#define BM_MCG_C1_IREFS (0x04U) /!< Bit mask for MCG_C1_IREFS. /
Kojto	90:cb3d968589d8	212	#define BS_MCG_C1_IREFS (1U) /!< Bit field size in bits for MCG_C1_IREFS. /
Kojto	90:cb3d968589d8	213
Kojto	90:cb3d968589d8	214	/! @brief Read current value of the MCG_C1_IREFS field. /
Kojto	90:cb3d968589d8	215	#define BR_MCG_C1_IREFS(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFS))
Kojto	90:cb3d968589d8	216
Kojto	90:cb3d968589d8	217	/! @brief Format value for bitfield MCG_C1_IREFS. /
Kojto	90:cb3d968589d8	218	#define BF_MCG_C1_IREFS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IREFS) & BM_MCG_C1_IREFS)
Kojto	90:cb3d968589d8	219
Kojto	90:cb3d968589d8	220	/! @brief Set the IREFS field to a new value. /
Kojto	90:cb3d968589d8	221	#define BW_MCG_C1_IREFS(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFS) = (v))
Kojto	90:cb3d968589d8	222	/@}/
Kojto	90:cb3d968589d8	223
Kojto	90:cb3d968589d8	224	/*!
Kojto	90:cb3d968589d8	225	* @name Register MCG_C1, field FRDIV[5:3] (RW)
Kojto	90:cb3d968589d8	226	*
Kojto	90:cb3d968589d8	227	* Selects the amount to divide down the external reference clock for the FLL.
Kojto	90:cb3d968589d8	228	* The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
Kojto	90:cb3d968589d8	229	* required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
Kojto	90:cb3d968589d8	230	* not required to meet this range, but it is recommended in the cases when trying
Kojto	90:cb3d968589d8	231	* to enter a FLL mode from FBE).
Kojto	90:cb3d968589d8	232	*
Kojto	90:cb3d968589d8	233	* Values:
Kojto	90:cb3d968589d8	234	* - 000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
Kojto	90:cb3d968589d8	235	* values, Divide Factor is 32.
Kojto	90:cb3d968589d8	236	* - 001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
Kojto	90:cb3d968589d8	237	* values, Divide Factor is 64.
Kojto	90:cb3d968589d8	238	* - 010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
Kojto	90:cb3d968589d8	239	* values, Divide Factor is 128.
Kojto	90:cb3d968589d8	240	* - 011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
Kojto	90:cb3d968589d8	241	* values, Divide Factor is 256.
Kojto	90:cb3d968589d8	242	* - 100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
Kojto	90:cb3d968589d8	243	* values, Divide Factor is 512.
Kojto	90:cb3d968589d8	244	* - 101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
Kojto	90:cb3d968589d8	245	* values, Divide Factor is 1024.
Kojto	90:cb3d968589d8	246	* - 110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
Kojto	90:cb3d968589d8	247	* values, Divide Factor is 1280 .
Kojto	90:cb3d968589d8	248	* - 111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE
Kojto	90:cb3d968589d8	249	* values, Divide Factor is 1536 .
Kojto	90:cb3d968589d8	250	*/
Kojto	90:cb3d968589d8	251	/@{/
Kojto	90:cb3d968589d8	252	#define BP_MCG_C1_FRDIV (3U) /!< Bit position for MCG_C1_FRDIV. /
Kojto	90:cb3d968589d8	253	#define BM_MCG_C1_FRDIV (0x38U) /!< Bit mask for MCG_C1_FRDIV. /
Kojto	90:cb3d968589d8	254	#define BS_MCG_C1_FRDIV (3U) /!< Bit field size in bits for MCG_C1_FRDIV. /
Kojto	90:cb3d968589d8	255
Kojto	90:cb3d968589d8	256	/! @brief Read current value of the MCG_C1_FRDIV field. /
Kojto	90:cb3d968589d8	257	#define BR_MCG_C1_FRDIV(x) (HW_MCG_C1(x).B.FRDIV)
Kojto	90:cb3d968589d8	258
Kojto	90:cb3d968589d8	259	/! @brief Format value for bitfield MCG_C1_FRDIV. /
Kojto	90:cb3d968589d8	260	#define BF_MCG_C1_FRDIV(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_FRDIV) & BM_MCG_C1_FRDIV)
Kojto	90:cb3d968589d8	261
Kojto	90:cb3d968589d8	262	/! @brief Set the FRDIV field to a new value. /
Kojto	90:cb3d968589d8	263	#define BW_MCG_C1_FRDIV(x, v) (HW_MCG_C1_WR(x, (HW_MCG_C1_RD(x) & ~BM_MCG_C1_FRDIV) \| BF_MCG_C1_FRDIV(v)))
Kojto	90:cb3d968589d8	264	/@}/
Kojto	90:cb3d968589d8	265
Kojto	90:cb3d968589d8	266	/*!
Kojto	90:cb3d968589d8	267	* @name Register MCG_C1, field CLKS[7:6] (RW)
Kojto	90:cb3d968589d8	268	*
Kojto	90:cb3d968589d8	269	* Selects the clock source for MCGOUTCLK .
Kojto	90:cb3d968589d8	270	*
Kojto	90:cb3d968589d8	271	* Values:
Kojto	90:cb3d968589d8	272	* - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control
Kojto	90:cb3d968589d8	273	* bit).
Kojto	90:cb3d968589d8	274	* - 01 - Encoding 1 - Internal reference clock is selected.
Kojto	90:cb3d968589d8	275	* - 10 - Encoding 2 - External reference clock is selected.
Kojto	90:cb3d968589d8	276	* - 11 - Encoding 3 - Reserved.
Kojto	90:cb3d968589d8	277	*/
Kojto	90:cb3d968589d8	278	/@{/
Kojto	90:cb3d968589d8	279	#define BP_MCG_C1_CLKS (6U) /!< Bit position for MCG_C1_CLKS. /
Kojto	90:cb3d968589d8	280	#define BM_MCG_C1_CLKS (0xC0U) /!< Bit mask for MCG_C1_CLKS. /
Kojto	90:cb3d968589d8	281	#define BS_MCG_C1_CLKS (2U) /!< Bit field size in bits for MCG_C1_CLKS. /
Kojto	90:cb3d968589d8	282
Kojto	90:cb3d968589d8	283	/! @brief Read current value of the MCG_C1_CLKS field. /
Kojto	90:cb3d968589d8	284	#define BR_MCG_C1_CLKS(x) (HW_MCG_C1(x).B.CLKS)
Kojto	90:cb3d968589d8	285
Kojto	90:cb3d968589d8	286	/! @brief Format value for bitfield MCG_C1_CLKS. /
Kojto	90:cb3d968589d8	287	#define BF_MCG_C1_CLKS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_CLKS) & BM_MCG_C1_CLKS)
Kojto	90:cb3d968589d8	288
Kojto	90:cb3d968589d8	289	/! @brief Set the CLKS field to a new value. /
Kojto	90:cb3d968589d8	290	#define BW_MCG_C1_CLKS(x, v) (HW_MCG_C1_WR(x, (HW_MCG_C1_RD(x) & ~BM_MCG_C1_CLKS) \| BF_MCG_C1_CLKS(v)))
Kojto	90:cb3d968589d8	291	/@}/
Kojto	90:cb3d968589d8	292
Kojto	90:cb3d968589d8	293	/*******************************************************************************
Kojto	90:cb3d968589d8	294	* HW_MCG_C2 - MCG Control 2 Register
Kojto	90:cb3d968589d8	295	******************************************************************************/
Kojto	90:cb3d968589d8	296
Kojto	90:cb3d968589d8	297	/*!
Kojto	90:cb3d968589d8	298	* @brief HW_MCG_C2 - MCG Control 2 Register (RW)
Kojto	90:cb3d968589d8	299	*
Kojto	90:cb3d968589d8	300	* Reset value: 0x80U
Kojto	90:cb3d968589d8	301	*/
Kojto	90:cb3d968589d8	302	typedef union _hw_mcg_c2
Kojto	90:cb3d968589d8	303	{
Kojto	90:cb3d968589d8	304	uint8_t U;
Kojto	90:cb3d968589d8	305	struct _hw_mcg_c2_bitfields
Kojto	90:cb3d968589d8	306	{
Kojto	90:cb3d968589d8	307	uint8_t IRCS : 1; /!< [0] Internal Reference Clock Select /
Kojto	90:cb3d968589d8	308	uint8_t LP : 1; /!< [1] Low Power Select /
Kojto	90:cb3d968589d8	309	uint8_t EREFS : 1; /!< [2] External Reference Select /
Kojto	90:cb3d968589d8	310	uint8_t HGO : 1; /!< [3] High Gain Oscillator Select /
Kojto	90:cb3d968589d8	311	uint8_t RANGE : 2; /!< [5:4] Frequency Range Select /
Kojto	90:cb3d968589d8	312	uint8_t FCFTRIM : 1; /*!< [6] Fast Internal Reference Clock Fine Trim
Kojto	90:cb3d968589d8	313	* */
Kojto	90:cb3d968589d8	314	uint8_t LOCRE0 : 1; /!< [7] Loss of Clock Reset Enable /
Kojto	90:cb3d968589d8	315	} B;
Kojto	90:cb3d968589d8	316	} hw_mcg_c2_t;
Kojto	90:cb3d968589d8	317
Kojto	90:cb3d968589d8	318	/*!
Kojto	90:cb3d968589d8	319	* @name Constants and macros for entire MCG_C2 register
Kojto	90:cb3d968589d8	320	*/
Kojto	90:cb3d968589d8	321	/@{/
Kojto	90:cb3d968589d8	322	#define HW_MCG_C2_ADDR(x) ((x) + 0x1U)
Kojto	90:cb3d968589d8	323
Kojto	90:cb3d968589d8	324	#define HW_MCG_C2(x) ((__IO hw_mcg_c2_t ) HW_MCG_C2_ADDR(x))
Kojto	90:cb3d968589d8	325	#define HW_MCG_C2_RD(x) (HW_MCG_C2(x).U)
Kojto	90:cb3d968589d8	326	#define HW_MCG_C2_WR(x, v) (HW_MCG_C2(x).U = (v))
Kojto	90:cb3d968589d8	327	#define HW_MCG_C2_SET(x, v) (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	328	#define HW_MCG_C2_CLR(x, v) (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	329	#define HW_MCG_C2_TOG(x, v) (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	330	/@}/
Kojto	90:cb3d968589d8	331
Kojto	90:cb3d968589d8	332	/*
Kojto	90:cb3d968589d8	333	* Constants & macros for individual MCG_C2 bitfields
Kojto	90:cb3d968589d8	334	*/
Kojto	90:cb3d968589d8	335
Kojto	90:cb3d968589d8	336	/*!
Kojto	90:cb3d968589d8	337	* @name Register MCG_C2, field IRCS[0] (RW)
Kojto	90:cb3d968589d8	338	*
Kojto	90:cb3d968589d8	339	* Selects between the fast or slow internal reference clock source.
Kojto	90:cb3d968589d8	340	*
Kojto	90:cb3d968589d8	341	* Values:
Kojto	90:cb3d968589d8	342	* - 0 - Slow internal reference clock selected.
Kojto	90:cb3d968589d8	343	* - 1 - Fast internal reference clock selected.
Kojto	90:cb3d968589d8	344	*/
Kojto	90:cb3d968589d8	345	/@{/
Kojto	90:cb3d968589d8	346	#define BP_MCG_C2_IRCS (0U) /!< Bit position for MCG_C2_IRCS. /
Kojto	90:cb3d968589d8	347	#define BM_MCG_C2_IRCS (0x01U) /!< Bit mask for MCG_C2_IRCS. /
Kojto	90:cb3d968589d8	348	#define BS_MCG_C2_IRCS (1U) /!< Bit field size in bits for MCG_C2_IRCS. /
Kojto	90:cb3d968589d8	349
Kojto	90:cb3d968589d8	350	/! @brief Read current value of the MCG_C2_IRCS field. /
Kojto	90:cb3d968589d8	351	#define BR_MCG_C2_IRCS(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_IRCS))
Kojto	90:cb3d968589d8	352
Kojto	90:cb3d968589d8	353	/! @brief Format value for bitfield MCG_C2_IRCS. /
Kojto	90:cb3d968589d8	354	#define BF_MCG_C2_IRCS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_IRCS) & BM_MCG_C2_IRCS)
Kojto	90:cb3d968589d8	355
Kojto	90:cb3d968589d8	356	/! @brief Set the IRCS field to a new value. /
Kojto	90:cb3d968589d8	357	#define BW_MCG_C2_IRCS(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_IRCS) = (v))
Kojto	90:cb3d968589d8	358	/@}/
Kojto	90:cb3d968589d8	359
Kojto	90:cb3d968589d8	360	/*!
Kojto	90:cb3d968589d8	361	* @name Register MCG_C2, field LP[1] (RW)
Kojto	90:cb3d968589d8	362	*
Kojto	90:cb3d968589d8	363	* Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
Kojto	90:cb3d968589d8	364	* PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
Kojto	90:cb3d968589d8	365	* FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
Kojto	90:cb3d968589d8	366	* other MCG mode, LP bit has no affect.
Kojto	90:cb3d968589d8	367	*
Kojto	90:cb3d968589d8	368	* Values:
Kojto	90:cb3d968589d8	369	* - 0 - FLL or PLL is not disabled in bypass modes.
Kojto	90:cb3d968589d8	370	* - 1 - FLL or PLL is disabled in bypass modes (lower power)
Kojto	90:cb3d968589d8	371	*/
Kojto	90:cb3d968589d8	372	/@{/
Kojto	90:cb3d968589d8	373	#define BP_MCG_C2_LP (1U) /!< Bit position for MCG_C2_LP. /
Kojto	90:cb3d968589d8	374	#define BM_MCG_C2_LP (0x02U) /!< Bit mask for MCG_C2_LP. /
Kojto	90:cb3d968589d8	375	#define BS_MCG_C2_LP (1U) /!< Bit field size in bits for MCG_C2_LP. /
Kojto	90:cb3d968589d8	376
Kojto	90:cb3d968589d8	377	/! @brief Read current value of the MCG_C2_LP field. /
Kojto	90:cb3d968589d8	378	#define BR_MCG_C2_LP(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LP))
Kojto	90:cb3d968589d8	379
Kojto	90:cb3d968589d8	380	/! @brief Format value for bitfield MCG_C2_LP. /
Kojto	90:cb3d968589d8	381	#define BF_MCG_C2_LP(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_LP) & BM_MCG_C2_LP)
Kojto	90:cb3d968589d8	382
Kojto	90:cb3d968589d8	383	/! @brief Set the LP field to a new value. /
Kojto	90:cb3d968589d8	384	#define BW_MCG_C2_LP(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LP) = (v))
Kojto	90:cb3d968589d8	385	/@}/
Kojto	90:cb3d968589d8	386
Kojto	90:cb3d968589d8	387	/*!
Kojto	90:cb3d968589d8	388	* @name Register MCG_C2, field EREFS[2] (RW)
Kojto	90:cb3d968589d8	389	*
Kojto	90:cb3d968589d8	390	* Selects the source for the external reference clock. See the Oscillator (OSC)
Kojto	90:cb3d968589d8	391	* chapter for more details.
Kojto	90:cb3d968589d8	392	*
Kojto	90:cb3d968589d8	393	* Values:
Kojto	90:cb3d968589d8	394	* - 0 - External reference clock requested.
Kojto	90:cb3d968589d8	395	* - 1 - Oscillator requested.
Kojto	90:cb3d968589d8	396	*/
Kojto	90:cb3d968589d8	397	/@{/
Kojto	90:cb3d968589d8	398	#define BP_MCG_C2_EREFS (2U) /!< Bit position for MCG_C2_EREFS. /
Kojto	90:cb3d968589d8	399	#define BM_MCG_C2_EREFS (0x04U) /!< Bit mask for MCG_C2_EREFS. /
Kojto	90:cb3d968589d8	400	#define BS_MCG_C2_EREFS (1U) /!< Bit field size in bits for MCG_C2_EREFS. /
Kojto	90:cb3d968589d8	401
Kojto	90:cb3d968589d8	402	/! @brief Read current value of the MCG_C2_EREFS field. /
Kojto	90:cb3d968589d8	403	#define BR_MCG_C2_EREFS(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_EREFS))
Kojto	90:cb3d968589d8	404
Kojto	90:cb3d968589d8	405	/! @brief Format value for bitfield MCG_C2_EREFS. /
Kojto	90:cb3d968589d8	406	#define BF_MCG_C2_EREFS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_EREFS) & BM_MCG_C2_EREFS)
Kojto	90:cb3d968589d8	407
Kojto	90:cb3d968589d8	408	/! @brief Set the EREFS field to a new value. /
Kojto	90:cb3d968589d8	409	#define BW_MCG_C2_EREFS(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_EREFS) = (v))
Kojto	90:cb3d968589d8	410	/@}/
Kojto	90:cb3d968589d8	411
Kojto	90:cb3d968589d8	412	/*!
Kojto	90:cb3d968589d8	413	* @name Register MCG_C2, field HGO[3] (RW)
Kojto	90:cb3d968589d8	414	*
Kojto	90:cb3d968589d8	415	* Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
Kojto	90:cb3d968589d8	416	* chapter for more details.
Kojto	90:cb3d968589d8	417	*
Kojto	90:cb3d968589d8	418	* Values:
Kojto	90:cb3d968589d8	419	* - 0 - Configure crystal oscillator for low-power operation.
Kojto	90:cb3d968589d8	420	* - 1 - Configure crystal oscillator for high-gain operation.
Kojto	90:cb3d968589d8	421	*/
Kojto	90:cb3d968589d8	422	/@{/
Kojto	90:cb3d968589d8	423	#define BP_MCG_C2_HGO (3U) /!< Bit position for MCG_C2_HGO. /
Kojto	90:cb3d968589d8	424	#define BM_MCG_C2_HGO (0x08U) /!< Bit mask for MCG_C2_HGO. /
Kojto	90:cb3d968589d8	425	#define BS_MCG_C2_HGO (1U) /!< Bit field size in bits for MCG_C2_HGO. /
Kojto	90:cb3d968589d8	426
Kojto	90:cb3d968589d8	427	/! @brief Read current value of the MCG_C2_HGO field. /
Kojto	90:cb3d968589d8	428	#define BR_MCG_C2_HGO(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_HGO))
Kojto	90:cb3d968589d8	429
Kojto	90:cb3d968589d8	430	/! @brief Format value for bitfield MCG_C2_HGO. /
Kojto	90:cb3d968589d8	431	#define BF_MCG_C2_HGO(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_HGO) & BM_MCG_C2_HGO)
Kojto	90:cb3d968589d8	432
Kojto	90:cb3d968589d8	433	/! @brief Set the HGO field to a new value. /
Kojto	90:cb3d968589d8	434	#define BW_MCG_C2_HGO(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_HGO) = (v))
Kojto	90:cb3d968589d8	435	/@}/
Kojto	90:cb3d968589d8	436
Kojto	90:cb3d968589d8	437	/*!
Kojto	90:cb3d968589d8	438	* @name Register MCG_C2, field RANGE[5:4] (RW)
Kojto	90:cb3d968589d8	439	*
Kojto	90:cb3d968589d8	440	* Selects the frequency range for the crystal oscillator or external clock
Kojto	90:cb3d968589d8	441	* source. See the Oscillator (OSC) chapter for more details and the device data
Kojto	90:cb3d968589d8	442	* sheet for the frequency ranges used.
Kojto	90:cb3d968589d8	443	*
Kojto	90:cb3d968589d8	444	* Values:
Kojto	90:cb3d968589d8	445	* - 00 - Encoding 0 - Low frequency range selected for the crystal oscillator .
Kojto	90:cb3d968589d8	446	* - 01 - Encoding 1 - High frequency range selected for the crystal oscillator .
Kojto	90:cb3d968589d8	447	*/
Kojto	90:cb3d968589d8	448	/@{/
Kojto	90:cb3d968589d8	449	#define BP_MCG_C2_RANGE (4U) /!< Bit position for MCG_C2_RANGE. /
Kojto	90:cb3d968589d8	450	#define BM_MCG_C2_RANGE (0x30U) /!< Bit mask for MCG_C2_RANGE. /
Kojto	90:cb3d968589d8	451	#define BS_MCG_C2_RANGE (2U) /!< Bit field size in bits for MCG_C2_RANGE. /
Kojto	90:cb3d968589d8	452
Kojto	90:cb3d968589d8	453	/! @brief Read current value of the MCG_C2_RANGE field. /
Kojto	90:cb3d968589d8	454	#define BR_MCG_C2_RANGE(x) (HW_MCG_C2(x).B.RANGE)
Kojto	90:cb3d968589d8	455
Kojto	90:cb3d968589d8	456	/! @brief Format value for bitfield MCG_C2_RANGE. /
Kojto	90:cb3d968589d8	457	#define BF_MCG_C2_RANGE(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_RANGE) & BM_MCG_C2_RANGE)
Kojto	90:cb3d968589d8	458
Kojto	90:cb3d968589d8	459	/! @brief Set the RANGE field to a new value. /
Kojto	90:cb3d968589d8	460	#define BW_MCG_C2_RANGE(x, v) (HW_MCG_C2_WR(x, (HW_MCG_C2_RD(x) & ~BM_MCG_C2_RANGE) \| BF_MCG_C2_RANGE(v)))
Kojto	90:cb3d968589d8	461	/@}/
Kojto	90:cb3d968589d8	462
Kojto	90:cb3d968589d8	463	/*!
Kojto	90:cb3d968589d8	464	* @name Register MCG_C2, field FCFTRIM[6] (RW)
Kojto	90:cb3d968589d8	465	*
Kojto	90:cb3d968589d8	466	* FCFTRIM controls the smallest adjustment of the fast internal reference clock
Kojto	90:cb3d968589d8	467	* frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
Kojto	90:cb3d968589d8	468	* decreases the period by the smallest amount possible. If an FCFTRIM value stored in
Kojto	90:cb3d968589d8	469	* nonvolatile memory is to be used, it is your responsibility to copy that value
Kojto	90:cb3d968589d8	470	* from the nonvolatile memory location to this bit.
Kojto	90:cb3d968589d8	471	*/
Kojto	90:cb3d968589d8	472	/@{/
Kojto	90:cb3d968589d8	473	#define BP_MCG_C2_FCFTRIM (6U) /!< Bit position for MCG_C2_FCFTRIM. /
Kojto	90:cb3d968589d8	474	#define BM_MCG_C2_FCFTRIM (0x40U) /!< Bit mask for MCG_C2_FCFTRIM. /
Kojto	90:cb3d968589d8	475	#define BS_MCG_C2_FCFTRIM (1U) /!< Bit field size in bits for MCG_C2_FCFTRIM. /
Kojto	90:cb3d968589d8	476
Kojto	90:cb3d968589d8	477	/! @brief Read current value of the MCG_C2_FCFTRIM field. /
Kojto	90:cb3d968589d8	478	#define BR_MCG_C2_FCFTRIM(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_FCFTRIM))
Kojto	90:cb3d968589d8	479
Kojto	90:cb3d968589d8	480	/! @brief Format value for bitfield MCG_C2_FCFTRIM. /
Kojto	90:cb3d968589d8	481	#define BF_MCG_C2_FCFTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_FCFTRIM) & BM_MCG_C2_FCFTRIM)
Kojto	90:cb3d968589d8	482
Kojto	90:cb3d968589d8	483	/! @brief Set the FCFTRIM field to a new value. /
Kojto	90:cb3d968589d8	484	#define BW_MCG_C2_FCFTRIM(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_FCFTRIM) = (v))
Kojto	90:cb3d968589d8	485	/@}/
Kojto	90:cb3d968589d8	486
Kojto	90:cb3d968589d8	487	/*!
Kojto	90:cb3d968589d8	488	* @name Register MCG_C2, field LOCRE0[7] (RW)
Kojto	90:cb3d968589d8	489	*
Kojto	90:cb3d968589d8	490	* Determines whether an interrupt or a reset request is made following a loss
Kojto	90:cb3d968589d8	491	* of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
Kojto	90:cb3d968589d8	492	* set.
Kojto	90:cb3d968589d8	493	*
Kojto	90:cb3d968589d8	494	* Values:
Kojto	90:cb3d968589d8	495	* - 0 - Interrupt request is generated on a loss of OSC0 external reference
Kojto	90:cb3d968589d8	496	* clock.
Kojto	90:cb3d968589d8	497	* - 1 - Generate a reset request on a loss of OSC0 external reference clock.
Kojto	90:cb3d968589d8	498	*/
Kojto	90:cb3d968589d8	499	/@{/
Kojto	90:cb3d968589d8	500	#define BP_MCG_C2_LOCRE0 (7U) /!< Bit position for MCG_C2_LOCRE0. /
Kojto	90:cb3d968589d8	501	#define BM_MCG_C2_LOCRE0 (0x80U) /!< Bit mask for MCG_C2_LOCRE0. /
Kojto	90:cb3d968589d8	502	#define BS_MCG_C2_LOCRE0 (1U) /!< Bit field size in bits for MCG_C2_LOCRE0. /
Kojto	90:cb3d968589d8	503
Kojto	90:cb3d968589d8	504	/! @brief Read current value of the MCG_C2_LOCRE0 field. /
Kojto	90:cb3d968589d8	505	#define BR_MCG_C2_LOCRE0(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LOCRE0))
Kojto	90:cb3d968589d8	506
Kojto	90:cb3d968589d8	507	/! @brief Format value for bitfield MCG_C2_LOCRE0. /
Kojto	90:cb3d968589d8	508	#define BF_MCG_C2_LOCRE0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_LOCRE0) & BM_MCG_C2_LOCRE0)
Kojto	90:cb3d968589d8	509
Kojto	90:cb3d968589d8	510	/! @brief Set the LOCRE0 field to a new value. /
Kojto	90:cb3d968589d8	511	#define BW_MCG_C2_LOCRE0(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LOCRE0) = (v))
Kojto	90:cb3d968589d8	512	/@}/
Kojto	90:cb3d968589d8	513
Kojto	90:cb3d968589d8	514	/*******************************************************************************
Kojto	90:cb3d968589d8	515	* HW_MCG_C3 - MCG Control 3 Register
Kojto	90:cb3d968589d8	516	******************************************************************************/
Kojto	90:cb3d968589d8	517
Kojto	90:cb3d968589d8	518	/*!
Kojto	90:cb3d968589d8	519	* @brief HW_MCG_C3 - MCG Control 3 Register (RW)
Kojto	90:cb3d968589d8	520	*
Kojto	90:cb3d968589d8	521	* Reset value: 0x00U
Kojto	90:cb3d968589d8	522	*/
Kojto	90:cb3d968589d8	523	typedef union _hw_mcg_c3
Kojto	90:cb3d968589d8	524	{
Kojto	90:cb3d968589d8	525	uint8_t U;
Kojto	90:cb3d968589d8	526	struct _hw_mcg_c3_bitfields
Kojto	90:cb3d968589d8	527	{
Kojto	90:cb3d968589d8	528	uint8_t SCTRIM : 8; /*!< [7:0] Slow Internal Reference Clock Trim
Kojto	90:cb3d968589d8	529	* Setting */
Kojto	90:cb3d968589d8	530	} B;
Kojto	90:cb3d968589d8	531	} hw_mcg_c3_t;
Kojto	90:cb3d968589d8	532
Kojto	90:cb3d968589d8	533	/*!
Kojto	90:cb3d968589d8	534	* @name Constants and macros for entire MCG_C3 register
Kojto	90:cb3d968589d8	535	*/
Kojto	90:cb3d968589d8	536	/@{/
Kojto	90:cb3d968589d8	537	#define HW_MCG_C3_ADDR(x) ((x) + 0x2U)
Kojto	90:cb3d968589d8	538
Kojto	90:cb3d968589d8	539	#define HW_MCG_C3(x) ((__IO hw_mcg_c3_t ) HW_MCG_C3_ADDR(x))
Kojto	90:cb3d968589d8	540	#define HW_MCG_C3_RD(x) (HW_MCG_C3(x).U)
Kojto	90:cb3d968589d8	541	#define HW_MCG_C3_WR(x, v) (HW_MCG_C3(x).U = (v))
Kojto	90:cb3d968589d8	542	#define HW_MCG_C3_SET(x, v) (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) \| (v)))
Kojto	90:cb3d968589d8	543	#define HW_MCG_C3_CLR(x, v) (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	544	#define HW_MCG_C3_TOG(x, v) (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	545	/@}/
Kojto	90:cb3d968589d8	546
Kojto	90:cb3d968589d8	547	/*
Kojto	90:cb3d968589d8	548	* Constants & macros for individual MCG_C3 bitfields
Kojto	90:cb3d968589d8	549	*/
Kojto	90:cb3d968589d8	550
Kojto	90:cb3d968589d8	551	/*!
Kojto	90:cb3d968589d8	552	* @name Register MCG_C3, field SCTRIM[7:0] (RW)
Kojto	90:cb3d968589d8	553	*
Kojto	90:cb3d968589d8	554	* SCTRIM A value for SCTRIM is loaded during reset from a factory programmed
Kojto	90:cb3d968589d8	555	* location. controls the slow internal reference clock frequency by controlling
Kojto	90:cb3d968589d8	556	* the slow internal reference clock period. The SCTRIM bits are binary weighted,
Kojto	90:cb3d968589d8	557	* that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
Kojto	90:cb3d968589d8	558	* increases the period, and decreasing the value decreases the period. An additional
Kojto	90:cb3d968589d8	559	* fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset,
Kojto	90:cb3d968589d8	560	* this value is loaded with a factory trim value. If an SCTRIM value stored in
Kojto	90:cb3d968589d8	561	* nonvolatile memory is to be used, it is your responsibility to copy that value
Kojto	90:cb3d968589d8	562	* from the nonvolatile memory location to this register.
Kojto	90:cb3d968589d8	563	*/
Kojto	90:cb3d968589d8	564	/@{/
Kojto	90:cb3d968589d8	565	#define BP_MCG_C3_SCTRIM (0U) /!< Bit position for MCG_C3_SCTRIM. /
Kojto	90:cb3d968589d8	566	#define BM_MCG_C3_SCTRIM (0xFFU) /!< Bit mask for MCG_C3_SCTRIM. /
Kojto	90:cb3d968589d8	567	#define BS_MCG_C3_SCTRIM (8U) /!< Bit field size in bits for MCG_C3_SCTRIM. /
Kojto	90:cb3d968589d8	568
Kojto	90:cb3d968589d8	569	/! @brief Read current value of the MCG_C3_SCTRIM field. /
Kojto	90:cb3d968589d8	570	#define BR_MCG_C3_SCTRIM(x) (HW_MCG_C3(x).U)
Kojto	90:cb3d968589d8	571
Kojto	90:cb3d968589d8	572	/! @brief Format value for bitfield MCG_C3_SCTRIM. /
Kojto	90:cb3d968589d8	573	#define BF_MCG_C3_SCTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C3_SCTRIM) & BM_MCG_C3_SCTRIM)
Kojto	90:cb3d968589d8	574
Kojto	90:cb3d968589d8	575	/! @brief Set the SCTRIM field to a new value. /
Kojto	90:cb3d968589d8	576	#define BW_MCG_C3_SCTRIM(x, v) (HW_MCG_C3_WR(x, v))
Kojto	90:cb3d968589d8	577	/@}/
Kojto	90:cb3d968589d8	578
Kojto	90:cb3d968589d8	579	/*******************************************************************************
Kojto	90:cb3d968589d8	580	* HW_MCG_C4 - MCG Control 4 Register
Kojto	90:cb3d968589d8	581	******************************************************************************/
Kojto	90:cb3d968589d8	582
Kojto	90:cb3d968589d8	583	/*!
Kojto	90:cb3d968589d8	584	* @brief HW_MCG_C4 - MCG Control 4 Register (RW)
Kojto	90:cb3d968589d8	585	*
Kojto	90:cb3d968589d8	586	* Reset value: 0x00U
Kojto	90:cb3d968589d8	587	*
Kojto	90:cb3d968589d8	588	* Reset values for DRST and DMX32 bits are 0.
Kojto	90:cb3d968589d8	589	*/
Kojto	90:cb3d968589d8	590	typedef union _hw_mcg_c4
Kojto	90:cb3d968589d8	591	{
Kojto	90:cb3d968589d8	592	uint8_t U;
Kojto	90:cb3d968589d8	593	struct _hw_mcg_c4_bitfields
Kojto	90:cb3d968589d8	594	{
Kojto	90:cb3d968589d8	595	uint8_t SCFTRIM : 1; /*!< [0] Slow Internal Reference Clock Fine Trim
Kojto	90:cb3d968589d8	596	* */
Kojto	90:cb3d968589d8	597	uint8_t FCTRIM : 4; /*!< [4:1] Fast Internal Reference Clock Trim
Kojto	90:cb3d968589d8	598	* Setting */
Kojto	90:cb3d968589d8	599	uint8_t DRST_DRS : 2; /!< [6:5] DCO Range Select /
Kojto	90:cb3d968589d8	600	uint8_t DMX32 : 1; /*!< [7] DCO Maximum Frequency with 32.768 kHz
Kojto	90:cb3d968589d8	601	* Reference */
Kojto	90:cb3d968589d8	602	} B;
Kojto	90:cb3d968589d8	603	} hw_mcg_c4_t;
Kojto	90:cb3d968589d8	604
Kojto	90:cb3d968589d8	605	/*!
Kojto	90:cb3d968589d8	606	* @name Constants and macros for entire MCG_C4 register
Kojto	90:cb3d968589d8	607	*/
Kojto	90:cb3d968589d8	608	/@{/
Kojto	90:cb3d968589d8	609	#define HW_MCG_C4_ADDR(x) ((x) + 0x3U)
Kojto	90:cb3d968589d8	610
Kojto	90:cb3d968589d8	611	#define HW_MCG_C4(x) ((__IO hw_mcg_c4_t ) HW_MCG_C4_ADDR(x))
Kojto	90:cb3d968589d8	612	#define HW_MCG_C4_RD(x) (HW_MCG_C4(x).U)
Kojto	90:cb3d968589d8	613	#define HW_MCG_C4_WR(x, v) (HW_MCG_C4(x).U = (v))
Kojto	90:cb3d968589d8	614	#define HW_MCG_C4_SET(x, v) (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) \| (v)))
Kojto	90:cb3d968589d8	615	#define HW_MCG_C4_CLR(x, v) (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	616	#define HW_MCG_C4_TOG(x, v) (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	617	/@}/
Kojto	90:cb3d968589d8	618
Kojto	90:cb3d968589d8	619	/*
Kojto	90:cb3d968589d8	620	* Constants & macros for individual MCG_C4 bitfields
Kojto	90:cb3d968589d8	621	*/
Kojto	90:cb3d968589d8	622
Kojto	90:cb3d968589d8	623	/*!
Kojto	90:cb3d968589d8	624	* @name Register MCG_C4, field SCFTRIM[0] (RW)
Kojto	90:cb3d968589d8	625	*
Kojto	90:cb3d968589d8	626	* SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
Kojto	90:cb3d968589d8	627	* location . controls the smallest adjustment of the slow internal reference
Kojto	90:cb3d968589d8	628	* clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
Kojto	90:cb3d968589d8	629	* decreases the period by the smallest amount possible. If an SCFTRIM value stored in
Kojto	90:cb3d968589d8	630	* nonvolatile memory is to be used, it is your responsibility to copy that value
Kojto	90:cb3d968589d8	631	* from the nonvolatile memory location to this bit.
Kojto	90:cb3d968589d8	632	*/
Kojto	90:cb3d968589d8	633	/@{/
Kojto	90:cb3d968589d8	634	#define BP_MCG_C4_SCFTRIM (0U) /!< Bit position for MCG_C4_SCFTRIM. /
Kojto	90:cb3d968589d8	635	#define BM_MCG_C4_SCFTRIM (0x01U) /!< Bit mask for MCG_C4_SCFTRIM. /
Kojto	90:cb3d968589d8	636	#define BS_MCG_C4_SCFTRIM (1U) /!< Bit field size in bits for MCG_C4_SCFTRIM. /
Kojto	90:cb3d968589d8	637
Kojto	90:cb3d968589d8	638	/! @brief Read current value of the MCG_C4_SCFTRIM field. /
Kojto	90:cb3d968589d8	639	#define BR_MCG_C4_SCFTRIM(x) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_SCFTRIM))
Kojto	90:cb3d968589d8	640
Kojto	90:cb3d968589d8	641	/! @brief Format value for bitfield MCG_C4_SCFTRIM. /
Kojto	90:cb3d968589d8	642	#define BF_MCG_C4_SCFTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_SCFTRIM) & BM_MCG_C4_SCFTRIM)
Kojto	90:cb3d968589d8	643
Kojto	90:cb3d968589d8	644	/! @brief Set the SCFTRIM field to a new value. /
Kojto	90:cb3d968589d8	645	#define BW_MCG_C4_SCFTRIM(x, v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_SCFTRIM) = (v))
Kojto	90:cb3d968589d8	646	/@}/
Kojto	90:cb3d968589d8	647
Kojto	90:cb3d968589d8	648	/*!
Kojto	90:cb3d968589d8	649	* @name Register MCG_C4, field FCTRIM[4:1] (RW)
Kojto	90:cb3d968589d8	650	*
Kojto	90:cb3d968589d8	651	* FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
Kojto	90:cb3d968589d8	652	* location. controls the fast internal reference clock frequency by controlling
Kojto	90:cb3d968589d8	653	* the fast internal reference clock period. The FCTRIM bits are binary weighted,
Kojto	90:cb3d968589d8	654	* that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
Kojto	90:cb3d968589d8	655	* increases the period, and decreasing the value decreases the period. If an
Kojto	90:cb3d968589d8	656	* FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
Kojto	90:cb3d968589d8	657	* responsibility to copy that value from the nonvolatile memory location to this register.
Kojto	90:cb3d968589d8	658	*/
Kojto	90:cb3d968589d8	659	/@{/
Kojto	90:cb3d968589d8	660	#define BP_MCG_C4_FCTRIM (1U) /!< Bit position for MCG_C4_FCTRIM. /
Kojto	90:cb3d968589d8	661	#define BM_MCG_C4_FCTRIM (0x1EU) /!< Bit mask for MCG_C4_FCTRIM. /
Kojto	90:cb3d968589d8	662	#define BS_MCG_C4_FCTRIM (4U) /!< Bit field size in bits for MCG_C4_FCTRIM. /
Kojto	90:cb3d968589d8	663
Kojto	90:cb3d968589d8	664	/! @brief Read current value of the MCG_C4_FCTRIM field. /
Kojto	90:cb3d968589d8	665	#define BR_MCG_C4_FCTRIM(x) (HW_MCG_C4(x).B.FCTRIM)
Kojto	90:cb3d968589d8	666
Kojto	90:cb3d968589d8	667	/! @brief Format value for bitfield MCG_C4_FCTRIM. /
Kojto	90:cb3d968589d8	668	#define BF_MCG_C4_FCTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_FCTRIM) & BM_MCG_C4_FCTRIM)
Kojto	90:cb3d968589d8	669
Kojto	90:cb3d968589d8	670	/! @brief Set the FCTRIM field to a new value. /
Kojto	90:cb3d968589d8	671	#define BW_MCG_C4_FCTRIM(x, v) (HW_MCG_C4_WR(x, (HW_MCG_C4_RD(x) & ~BM_MCG_C4_FCTRIM) \| BF_MCG_C4_FCTRIM(v)))
Kojto	90:cb3d968589d8	672	/@}/
Kojto	90:cb3d968589d8	673
Kojto	90:cb3d968589d8	674	/*!
Kojto	90:cb3d968589d8	675	* @name Register MCG_C4, field DRST_DRS[6:5] (RW)
Kojto	90:cb3d968589d8	676	*
Kojto	90:cb3d968589d8	677	* The DRS bits select the frequency range for the FLL output, DCOOUT. When the
Kojto	90:cb3d968589d8	678	* LP bit is set, writes to the DRS bits are ignored. The DRST read field
Kojto	90:cb3d968589d8	679	* indicates the current frequency range for DCOOUT. The DRST field does not update
Kojto	90:cb3d968589d8	680	* immediately after a write to the DRS field due to internal synchronization between
Kojto	90:cb3d968589d8	681	* clock domains. See the DCO Frequency Range table for more details.
Kojto	90:cb3d968589d8	682	*
Kojto	90:cb3d968589d8	683	* Values:
Kojto	90:cb3d968589d8	684	* - 00 - Encoding 0 - Low range (reset default).
Kojto	90:cb3d968589d8	685	* - 01 - Encoding 1 - Mid range.
Kojto	90:cb3d968589d8	686	* - 10 - Encoding 2 - Mid-high range.
Kojto	90:cb3d968589d8	687	* - 11 - Encoding 3 - High range.
Kojto	90:cb3d968589d8	688	*/
Kojto	90:cb3d968589d8	689	/@{/
Kojto	90:cb3d968589d8	690	#define BP_MCG_C4_DRST_DRS (5U) /!< Bit position for MCG_C4_DRST_DRS. /
Kojto	90:cb3d968589d8	691	#define BM_MCG_C4_DRST_DRS (0x60U) /!< Bit mask for MCG_C4_DRST_DRS. /
Kojto	90:cb3d968589d8	692	#define BS_MCG_C4_DRST_DRS (2U) /!< Bit field size in bits for MCG_C4_DRST_DRS. /
Kojto	90:cb3d968589d8	693
Kojto	90:cb3d968589d8	694	/! @brief Read current value of the MCG_C4_DRST_DRS field. /
Kojto	90:cb3d968589d8	695	#define BR_MCG_C4_DRST_DRS(x) (HW_MCG_C4(x).B.DRST_DRS)
Kojto	90:cb3d968589d8	696
Kojto	90:cb3d968589d8	697	/! @brief Format value for bitfield MCG_C4_DRST_DRS. /
Kojto	90:cb3d968589d8	698	#define BF_MCG_C4_DRST_DRS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_DRST_DRS) & BM_MCG_C4_DRST_DRS)
Kojto	90:cb3d968589d8	699
Kojto	90:cb3d968589d8	700	/! @brief Set the DRST_DRS field to a new value. /
Kojto	90:cb3d968589d8	701	#define BW_MCG_C4_DRST_DRS(x, v) (HW_MCG_C4_WR(x, (HW_MCG_C4_RD(x) & ~BM_MCG_C4_DRST_DRS) \| BF_MCG_C4_DRST_DRS(v)))
Kojto	90:cb3d968589d8	702	/@}/
Kojto	90:cb3d968589d8	703
Kojto	90:cb3d968589d8	704	/*!
Kojto	90:cb3d968589d8	705	* @name Register MCG_C4, field DMX32[7] (RW)
Kojto	90:cb3d968589d8	706	*
Kojto	90:cb3d968589d8	707	* The DMX32 bit controls whether the DCO frequency range is narrowed to its
Kojto	90:cb3d968589d8	708	* maximum frequency with a 32.768 kHz reference. The following table identifies
Kojto	90:cb3d968589d8	709	* settings for the DCO frequency range. The system clocks derived from this source
Kojto	90:cb3d968589d8	710	* should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
Kojto	90:cb3d968589d8	711	* Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
Kojto	90:cb3d968589d8	712	* 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
Kojto	90:cb3d968589d8	713	* 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
Kojto	90:cb3d968589d8	714	* 80-100 MHz 1 32.768 kHz 2929 96 MHz
Kojto	90:cb3d968589d8	715	*
Kojto	90:cb3d968589d8	716	* Values:
Kojto	90:cb3d968589d8	717	* - 0 - DCO has a default range of 25%.
Kojto	90:cb3d968589d8	718	* - 1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
Kojto	90:cb3d968589d8	719	*/
Kojto	90:cb3d968589d8	720	/@{/
Kojto	90:cb3d968589d8	721	#define BP_MCG_C4_DMX32 (7U) /!< Bit position for MCG_C4_DMX32. /
Kojto	90:cb3d968589d8	722	#define BM_MCG_C4_DMX32 (0x80U) /!< Bit mask for MCG_C4_DMX32. /
Kojto	90:cb3d968589d8	723	#define BS_MCG_C4_DMX32 (1U) /!< Bit field size in bits for MCG_C4_DMX32. /
Kojto	90:cb3d968589d8	724
Kojto	90:cb3d968589d8	725	/! @brief Read current value of the MCG_C4_DMX32 field. /
Kojto	90:cb3d968589d8	726	#define BR_MCG_C4_DMX32(x) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_DMX32))
Kojto	90:cb3d968589d8	727
Kojto	90:cb3d968589d8	728	/! @brief Format value for bitfield MCG_C4_DMX32. /
Kojto	90:cb3d968589d8	729	#define BF_MCG_C4_DMX32(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_DMX32) & BM_MCG_C4_DMX32)
Kojto	90:cb3d968589d8	730
Kojto	90:cb3d968589d8	731	/! @brief Set the DMX32 field to a new value. /
Kojto	90:cb3d968589d8	732	#define BW_MCG_C4_DMX32(x, v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_DMX32) = (v))
Kojto	90:cb3d968589d8	733	/@}/
Kojto	90:cb3d968589d8	734
Kojto	90:cb3d968589d8	735	/*******************************************************************************
Kojto	90:cb3d968589d8	736	* HW_MCG_C5 - MCG Control 5 Register
Kojto	90:cb3d968589d8	737	******************************************************************************/
Kojto	90:cb3d968589d8	738
Kojto	90:cb3d968589d8	739	/*!
Kojto	90:cb3d968589d8	740	* @brief HW_MCG_C5 - MCG Control 5 Register (RW)
Kojto	90:cb3d968589d8	741	*
Kojto	90:cb3d968589d8	742	* Reset value: 0x00U
Kojto	90:cb3d968589d8	743	*/
Kojto	90:cb3d968589d8	744	typedef union _hw_mcg_c5
Kojto	90:cb3d968589d8	745	{
Kojto	90:cb3d968589d8	746	uint8_t U;
Kojto	90:cb3d968589d8	747	struct _hw_mcg_c5_bitfields
Kojto	90:cb3d968589d8	748	{
Kojto	90:cb3d968589d8	749	uint8_t PRDIV0 : 5; /!< [4:0] PLL External Reference Divider /
Kojto	90:cb3d968589d8	750	uint8_t PLLSTEN0 : 1; /!< [5] PLL Stop Enable /
Kojto	90:cb3d968589d8	751	uint8_t PLLCLKEN0 : 1; /!< [6] PLL Clock Enable /
Kojto	90:cb3d968589d8	752	uint8_t RESERVED0 : 1; /!< [7] /
Kojto	90:cb3d968589d8	753	} B;
Kojto	90:cb3d968589d8	754	} hw_mcg_c5_t;
Kojto	90:cb3d968589d8	755
Kojto	90:cb3d968589d8	756	/*!
Kojto	90:cb3d968589d8	757	* @name Constants and macros for entire MCG_C5 register
Kojto	90:cb3d968589d8	758	*/
Kojto	90:cb3d968589d8	759	/@{/
Kojto	90:cb3d968589d8	760	#define HW_MCG_C5_ADDR(x) ((x) + 0x4U)
Kojto	90:cb3d968589d8	761
Kojto	90:cb3d968589d8	762	#define HW_MCG_C5(x) ((__IO hw_mcg_c5_t ) HW_MCG_C5_ADDR(x))
Kojto	90:cb3d968589d8	763	#define HW_MCG_C5_RD(x) (HW_MCG_C5(x).U)
Kojto	90:cb3d968589d8	764	#define HW_MCG_C5_WR(x, v) (HW_MCG_C5(x).U = (v))
Kojto	90:cb3d968589d8	765	#define HW_MCG_C5_SET(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) \| (v)))
Kojto	90:cb3d968589d8	766	#define HW_MCG_C5_CLR(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	767	#define HW_MCG_C5_TOG(x, v) (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	768	/@}/
Kojto	90:cb3d968589d8	769
Kojto	90:cb3d968589d8	770	/*
Kojto	90:cb3d968589d8	771	* Constants & macros for individual MCG_C5 bitfields
Kojto	90:cb3d968589d8	772	*/
Kojto	90:cb3d968589d8	773
Kojto	90:cb3d968589d8	774	/*!
Kojto	90:cb3d968589d8	775	* @name Register MCG_C5, field PRDIV0[4:0] (RW)
Kojto	90:cb3d968589d8	776	*
Kojto	90:cb3d968589d8	777	* Selects the amount to divide down the external reference clock for the PLL.
Kojto	90:cb3d968589d8	778	* The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
Kojto	90:cb3d968589d8	779	* is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
Kojto	90:cb3d968589d8	780	* be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
Kojto	90:cb3d968589d8	781	* Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
Kojto	90:cb3d968589d8	782	* 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
Kojto	90:cb3d968589d8	783	* 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
Kojto	90:cb3d968589d8	784	* 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
Kojto	90:cb3d968589d8	785	* Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
Kojto	90:cb3d968589d8	786	* Reserved
Kojto	90:cb3d968589d8	787	*/
Kojto	90:cb3d968589d8	788	/@{/
Kojto	90:cb3d968589d8	789	#define BP_MCG_C5_PRDIV0 (0U) /!< Bit position for MCG_C5_PRDIV0. /
Kojto	90:cb3d968589d8	790	#define BM_MCG_C5_PRDIV0 (0x1FU) /!< Bit mask for MCG_C5_PRDIV0. /
Kojto	90:cb3d968589d8	791	#define BS_MCG_C5_PRDIV0 (5U) /!< Bit field size in bits for MCG_C5_PRDIV0. /
Kojto	90:cb3d968589d8	792
Kojto	90:cb3d968589d8	793	/! @brief Read current value of the MCG_C5_PRDIV0 field. /
Kojto	90:cb3d968589d8	794	#define BR_MCG_C5_PRDIV0(x) (HW_MCG_C5(x).B.PRDIV0)
Kojto	90:cb3d968589d8	795
Kojto	90:cb3d968589d8	796	/! @brief Format value for bitfield MCG_C5_PRDIV0. /
Kojto	90:cb3d968589d8	797	#define BF_MCG_C5_PRDIV0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PRDIV0) & BM_MCG_C5_PRDIV0)
Kojto	90:cb3d968589d8	798
Kojto	90:cb3d968589d8	799	/! @brief Set the PRDIV0 field to a new value. /
Kojto	90:cb3d968589d8	800	#define BW_MCG_C5_PRDIV0(x, v) (HW_MCG_C5_WR(x, (HW_MCG_C5_RD(x) & ~BM_MCG_C5_PRDIV0) \| BF_MCG_C5_PRDIV0(v)))
Kojto	90:cb3d968589d8	801	/@}/
Kojto	90:cb3d968589d8	802
Kojto	90:cb3d968589d8	803	/*!
Kojto	90:cb3d968589d8	804	* @name Register MCG_C5, field PLLSTEN0[5] (RW)
Kojto	90:cb3d968589d8	805	*
Kojto	90:cb3d968589d8	806	* Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
Kojto	90:cb3d968589d8	807	* clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
Kojto	90:cb3d968589d8	808	* has no affect and does not enable the PLL Clock to run if it is written to 1.
Kojto	90:cb3d968589d8	809	*
Kojto	90:cb3d968589d8	810	* Values:
Kojto	90:cb3d968589d8	811	* - 0 - MCGPLLCLK is disabled in any of the Stop modes.
Kojto	90:cb3d968589d8	812	* - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
Kojto	90:cb3d968589d8	813	*/
Kojto	90:cb3d968589d8	814	/@{/
Kojto	90:cb3d968589d8	815	#define BP_MCG_C5_PLLSTEN0 (5U) /!< Bit position for MCG_C5_PLLSTEN0. /
Kojto	90:cb3d968589d8	816	#define BM_MCG_C5_PLLSTEN0 (0x20U) /!< Bit mask for MCG_C5_PLLSTEN0. /
Kojto	90:cb3d968589d8	817	#define BS_MCG_C5_PLLSTEN0 (1U) /!< Bit field size in bits for MCG_C5_PLLSTEN0. /
Kojto	90:cb3d968589d8	818
Kojto	90:cb3d968589d8	819	/! @brief Read current value of the MCG_C5_PLLSTEN0 field. /
Kojto	90:cb3d968589d8	820	#define BR_MCG_C5_PLLSTEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0))
Kojto	90:cb3d968589d8	821
Kojto	90:cb3d968589d8	822	/! @brief Format value for bitfield MCG_C5_PLLSTEN0. /
Kojto	90:cb3d968589d8	823	#define BF_MCG_C5_PLLSTEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLSTEN0) & BM_MCG_C5_PLLSTEN0)
Kojto	90:cb3d968589d8	824
Kojto	90:cb3d968589d8	825	/! @brief Set the PLLSTEN0 field to a new value. /
Kojto	90:cb3d968589d8	826	#define BW_MCG_C5_PLLSTEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0) = (v))
Kojto	90:cb3d968589d8	827	/@}/
Kojto	90:cb3d968589d8	828
Kojto	90:cb3d968589d8	829	/*!
Kojto	90:cb3d968589d8	830	* @name Register MCG_C5, field PLLCLKEN0[6] (RW)
Kojto	90:cb3d968589d8	831	*
Kojto	90:cb3d968589d8	832	* Enables the PLL independent of PLLS and enables the PLL clock for use as
Kojto	90:cb3d968589d8	833	* MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
Kojto	90:cb3d968589d8	834	* PLL reference clock in the range of 2 - 4 MHz range prior to setting the
Kojto	90:cb3d968589d8	835	* PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
Kojto	90:cb3d968589d8	836	* already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
Kojto	90:cb3d968589d8	837	* and the external oscillator is being used as the reference clock, the OSCINIT 0
Kojto	90:cb3d968589d8	838	* bit should be checked to make sure it is set.
Kojto	90:cb3d968589d8	839	*
Kojto	90:cb3d968589d8	840	* Values:
Kojto	90:cb3d968589d8	841	* - 0 - MCGPLLCLK is inactive.
Kojto	90:cb3d968589d8	842	* - 1 - MCGPLLCLK is active.
Kojto	90:cb3d968589d8	843	*/
Kojto	90:cb3d968589d8	844	/@{/
Kojto	90:cb3d968589d8	845	#define BP_MCG_C5_PLLCLKEN0 (6U) /!< Bit position for MCG_C5_PLLCLKEN0. /
Kojto	90:cb3d968589d8	846	#define BM_MCG_C5_PLLCLKEN0 (0x40U) /!< Bit mask for MCG_C5_PLLCLKEN0. /
Kojto	90:cb3d968589d8	847	#define BS_MCG_C5_PLLCLKEN0 (1U) /!< Bit field size in bits for MCG_C5_PLLCLKEN0. /
Kojto	90:cb3d968589d8	848
Kojto	90:cb3d968589d8	849	/! @brief Read current value of the MCG_C5_PLLCLKEN0 field. /
Kojto	90:cb3d968589d8	850	#define BR_MCG_C5_PLLCLKEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0))
Kojto	90:cb3d968589d8	851
Kojto	90:cb3d968589d8	852	/! @brief Format value for bitfield MCG_C5_PLLCLKEN0. /
Kojto	90:cb3d968589d8	853	#define BF_MCG_C5_PLLCLKEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLCLKEN0) & BM_MCG_C5_PLLCLKEN0)
Kojto	90:cb3d968589d8	854
Kojto	90:cb3d968589d8	855	/! @brief Set the PLLCLKEN0 field to a new value. /
Kojto	90:cb3d968589d8	856	#define BW_MCG_C5_PLLCLKEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0) = (v))
Kojto	90:cb3d968589d8	857	/@}/
Kojto	90:cb3d968589d8	858
Kojto	90:cb3d968589d8	859	/*******************************************************************************
Kojto	90:cb3d968589d8	860	* HW_MCG_C6 - MCG Control 6 Register
Kojto	90:cb3d968589d8	861	******************************************************************************/
Kojto	90:cb3d968589d8	862
Kojto	90:cb3d968589d8	863	/*!
Kojto	90:cb3d968589d8	864	* @brief HW_MCG_C6 - MCG Control 6 Register (RW)
Kojto	90:cb3d968589d8	865	*
Kojto	90:cb3d968589d8	866	* Reset value: 0x00U
Kojto	90:cb3d968589d8	867	*/
Kojto	90:cb3d968589d8	868	typedef union _hw_mcg_c6
Kojto	90:cb3d968589d8	869	{
Kojto	90:cb3d968589d8	870	uint8_t U;
Kojto	90:cb3d968589d8	871	struct _hw_mcg_c6_bitfields
Kojto	90:cb3d968589d8	872	{
Kojto	90:cb3d968589d8	873	uint8_t VDIV0 : 5; /!< [4:0] VCO 0 Divider /
Kojto	90:cb3d968589d8	874	uint8_t CME0 : 1; /!< [5] Clock Monitor Enable /
Kojto	90:cb3d968589d8	875	uint8_t PLLS : 1; /!< [6] PLL Select /
Kojto	90:cb3d968589d8	876	uint8_t LOLIE0 : 1; /!< [7] Loss of Lock Interrrupt Enable /
Kojto	90:cb3d968589d8	877	} B;
Kojto	90:cb3d968589d8	878	} hw_mcg_c6_t;
Kojto	90:cb3d968589d8	879
Kojto	90:cb3d968589d8	880	/*!
Kojto	90:cb3d968589d8	881	* @name Constants and macros for entire MCG_C6 register
Kojto	90:cb3d968589d8	882	*/
Kojto	90:cb3d968589d8	883	/@{/
Kojto	90:cb3d968589d8	884	#define HW_MCG_C6_ADDR(x) ((x) + 0x5U)
Kojto	90:cb3d968589d8	885
Kojto	90:cb3d968589d8	886	#define HW_MCG_C6(x) ((__IO hw_mcg_c6_t ) HW_MCG_C6_ADDR(x))
Kojto	90:cb3d968589d8	887	#define HW_MCG_C6_RD(x) (HW_MCG_C6(x).U)
Kojto	90:cb3d968589d8	888	#define HW_MCG_C6_WR(x, v) (HW_MCG_C6(x).U = (v))
Kojto	90:cb3d968589d8	889	#define HW_MCG_C6_SET(x, v) (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) \| (v)))
Kojto	90:cb3d968589d8	890	#define HW_MCG_C6_CLR(x, v) (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	891	#define HW_MCG_C6_TOG(x, v) (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	892	/@}/
Kojto	90:cb3d968589d8	893
Kojto	90:cb3d968589d8	894	/*
Kojto	90:cb3d968589d8	895	* Constants & macros for individual MCG_C6 bitfields
Kojto	90:cb3d968589d8	896	*/
Kojto	90:cb3d968589d8	897
Kojto	90:cb3d968589d8	898	/*!
Kojto	90:cb3d968589d8	899	* @name Register MCG_C6, field VDIV0[4:0] (RW)
Kojto	90:cb3d968589d8	900	*
Kojto	90:cb3d968589d8	901	* Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
Kojto	90:cb3d968589d8	902	* establish the multiplication factor (M) applied to the reference clock frequency.
Kojto	90:cb3d968589d8	903	* After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
Kojto	90:cb3d968589d8	904	* value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
Kojto	90:cb3d968589d8	905	* Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
Kojto	90:cb3d968589d8	906	* Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
Kojto	90:cb3d968589d8	907	* 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
Kojto	90:cb3d968589d8	908	* 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
Kojto	90:cb3d968589d8	909	* 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
Kojto	90:cb3d968589d8	910	*/
Kojto	90:cb3d968589d8	911	/@{/
Kojto	90:cb3d968589d8	912	#define BP_MCG_C6_VDIV0 (0U) /!< Bit position for MCG_C6_VDIV0. /
Kojto	90:cb3d968589d8	913	#define BM_MCG_C6_VDIV0 (0x1FU) /!< Bit mask for MCG_C6_VDIV0. /
Kojto	90:cb3d968589d8	914	#define BS_MCG_C6_VDIV0 (5U) /!< Bit field size in bits for MCG_C6_VDIV0. /
Kojto	90:cb3d968589d8	915
Kojto	90:cb3d968589d8	916	/! @brief Read current value of the MCG_C6_VDIV0 field. /
Kojto	90:cb3d968589d8	917	#define BR_MCG_C6_VDIV0(x) (HW_MCG_C6(x).B.VDIV0)
Kojto	90:cb3d968589d8	918
Kojto	90:cb3d968589d8	919	/! @brief Format value for bitfield MCG_C6_VDIV0. /
Kojto	90:cb3d968589d8	920	#define BF_MCG_C6_VDIV0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_VDIV0) & BM_MCG_C6_VDIV0)
Kojto	90:cb3d968589d8	921
Kojto	90:cb3d968589d8	922	/! @brief Set the VDIV0 field to a new value. /
Kojto	90:cb3d968589d8	923	#define BW_MCG_C6_VDIV0(x, v) (HW_MCG_C6_WR(x, (HW_MCG_C6_RD(x) & ~BM_MCG_C6_VDIV0) \| BF_MCG_C6_VDIV0(v)))
Kojto	90:cb3d968589d8	924	/@}/
Kojto	90:cb3d968589d8	925
Kojto	90:cb3d968589d8	926	/*!
Kojto	90:cb3d968589d8	927	* @name Register MCG_C6, field CME0[5] (RW)
Kojto	90:cb3d968589d8	928	*
Kojto	90:cb3d968589d8	929	* Enables the loss of clock monitoring circuit for the OSC0 external reference
Kojto	90:cb3d968589d8	930	* mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
Kojto	90:cb3d968589d8	931	* generated following a loss of OSC0 indication. The CME0 bit must only be set
Kojto	90:cb3d968589d8	932	* to a logic 1 when the MCG is in an operational mode that uses the external
Kojto	90:cb3d968589d8	933	* clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
Kojto	90:cb3d968589d8	934	* the value of the RANGE0 bits in the C2 register should not be changed. CME0
Kojto	90:cb3d968589d8	935	* bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
Kojto	90:cb3d968589d8	936	* reset request may occur while in Stop mode. CME0 should also be set to a
Kojto	90:cb3d968589d8	937	* logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
Kojto	90:cb3d968589d8	938	*
Kojto	90:cb3d968589d8	939	* Values:
Kojto	90:cb3d968589d8	940	* - 0 - External clock monitor is disabled for OSC0.
Kojto	90:cb3d968589d8	941	* - 1 - External clock monitor is enabled for OSC0.
Kojto	90:cb3d968589d8	942	*/
Kojto	90:cb3d968589d8	943	/@{/
Kojto	90:cb3d968589d8	944	#define BP_MCG_C6_CME0 (5U) /!< Bit position for MCG_C6_CME0. /
Kojto	90:cb3d968589d8	945	#define BM_MCG_C6_CME0 (0x20U) /!< Bit mask for MCG_C6_CME0. /
Kojto	90:cb3d968589d8	946	#define BS_MCG_C6_CME0 (1U) /!< Bit field size in bits for MCG_C6_CME0. /
Kojto	90:cb3d968589d8	947
Kojto	90:cb3d968589d8	948	/! @brief Read current value of the MCG_C6_CME0 field. /
Kojto	90:cb3d968589d8	949	#define BR_MCG_C6_CME0(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0))
Kojto	90:cb3d968589d8	950
Kojto	90:cb3d968589d8	951	/! @brief Format value for bitfield MCG_C6_CME0. /
Kojto	90:cb3d968589d8	952	#define BF_MCG_C6_CME0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_CME0) & BM_MCG_C6_CME0)
Kojto	90:cb3d968589d8	953
Kojto	90:cb3d968589d8	954	/! @brief Set the CME0 field to a new value. /
Kojto	90:cb3d968589d8	955	#define BW_MCG_C6_CME0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0) = (v))
Kojto	90:cb3d968589d8	956	/@}/
Kojto	90:cb3d968589d8	957
Kojto	90:cb3d968589d8	958	/*!
Kojto	90:cb3d968589d8	959	* @name Register MCG_C6, field PLLS[6] (RW)
Kojto	90:cb3d968589d8	960	*
Kojto	90:cb3d968589d8	961	* Controls whether the PLL or FLL output is selected as the MCG source when
Kojto	90:cb3d968589d8	962	* CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
Kojto	90:cb3d968589d8	963	* disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
Kojto	90:cb3d968589d8	964	*
Kojto	90:cb3d968589d8	965	* Values:
Kojto	90:cb3d968589d8	966	* - 0 - FLL is selected.
Kojto	90:cb3d968589d8	967	* - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
Kojto	90:cb3d968589d8	968	* to generate a PLL reference clock in the range of 2-4 MHz prior to setting
Kojto	90:cb3d968589d8	969	* the PLLS bit).
Kojto	90:cb3d968589d8	970	*/
Kojto	90:cb3d968589d8	971	/@{/
Kojto	90:cb3d968589d8	972	#define BP_MCG_C6_PLLS (6U) /!< Bit position for MCG_C6_PLLS. /
Kojto	90:cb3d968589d8	973	#define BM_MCG_C6_PLLS (0x40U) /!< Bit mask for MCG_C6_PLLS. /
Kojto	90:cb3d968589d8	974	#define BS_MCG_C6_PLLS (1U) /!< Bit field size in bits for MCG_C6_PLLS. /
Kojto	90:cb3d968589d8	975
Kojto	90:cb3d968589d8	976	/! @brief Read current value of the MCG_C6_PLLS field. /
Kojto	90:cb3d968589d8	977	#define BR_MCG_C6_PLLS(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS))
Kojto	90:cb3d968589d8	978
Kojto	90:cb3d968589d8	979	/! @brief Format value for bitfield MCG_C6_PLLS. /
Kojto	90:cb3d968589d8	980	#define BF_MCG_C6_PLLS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_PLLS) & BM_MCG_C6_PLLS)
Kojto	90:cb3d968589d8	981
Kojto	90:cb3d968589d8	982	/! @brief Set the PLLS field to a new value. /
Kojto	90:cb3d968589d8	983	#define BW_MCG_C6_PLLS(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS) = (v))
Kojto	90:cb3d968589d8	984	/@}/
Kojto	90:cb3d968589d8	985
Kojto	90:cb3d968589d8	986	/*!
Kojto	90:cb3d968589d8	987	* @name Register MCG_C6, field LOLIE0[7] (RW)
Kojto	90:cb3d968589d8	988	*
Kojto	90:cb3d968589d8	989	* Determines if an interrupt request is made following a loss of lock
Kojto	90:cb3d968589d8	990	* indication. This bit only has an effect when LOLS 0 is set.
Kojto	90:cb3d968589d8	991	*
Kojto	90:cb3d968589d8	992	* Values:
Kojto	90:cb3d968589d8	993	* - 0 - No interrupt request is generated on loss of lock.
Kojto	90:cb3d968589d8	994	* - 1 - Generate an interrupt request on loss of lock.
Kojto	90:cb3d968589d8	995	*/
Kojto	90:cb3d968589d8	996	/@{/
Kojto	90:cb3d968589d8	997	#define BP_MCG_C6_LOLIE0 (7U) /!< Bit position for MCG_C6_LOLIE0. /
Kojto	90:cb3d968589d8	998	#define BM_MCG_C6_LOLIE0 (0x80U) /!< Bit mask for MCG_C6_LOLIE0. /
Kojto	90:cb3d968589d8	999	#define BS_MCG_C6_LOLIE0 (1U) /!< Bit field size in bits for MCG_C6_LOLIE0. /
Kojto	90:cb3d968589d8	1000
Kojto	90:cb3d968589d8	1001	/! @brief Read current value of the MCG_C6_LOLIE0 field. /
Kojto	90:cb3d968589d8	1002	#define BR_MCG_C6_LOLIE0(x) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0))
Kojto	90:cb3d968589d8	1003
Kojto	90:cb3d968589d8	1004	/! @brief Format value for bitfield MCG_C6_LOLIE0. /
Kojto	90:cb3d968589d8	1005	#define BF_MCG_C6_LOLIE0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C6_LOLIE0) & BM_MCG_C6_LOLIE0)
Kojto	90:cb3d968589d8	1006
Kojto	90:cb3d968589d8	1007	/! @brief Set the LOLIE0 field to a new value. /
Kojto	90:cb3d968589d8	1008	#define BW_MCG_C6_LOLIE0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0) = (v))
Kojto	90:cb3d968589d8	1009	/@}/
Kojto	90:cb3d968589d8	1010
Kojto	90:cb3d968589d8	1011	/*******************************************************************************
Kojto	90:cb3d968589d8	1012	* HW_MCG_S - MCG Status Register
Kojto	90:cb3d968589d8	1013	******************************************************************************/
Kojto	90:cb3d968589d8	1014
Kojto	90:cb3d968589d8	1015	/*!
Kojto	90:cb3d968589d8	1016	* @brief HW_MCG_S - MCG Status Register (RW)
Kojto	90:cb3d968589d8	1017	*
Kojto	90:cb3d968589d8	1018	* Reset value: 0x10U
Kojto	90:cb3d968589d8	1019	*/
Kojto	90:cb3d968589d8	1020	typedef union _hw_mcg_s
Kojto	90:cb3d968589d8	1021	{
Kojto	90:cb3d968589d8	1022	uint8_t U;
Kojto	90:cb3d968589d8	1023	struct _hw_mcg_s_bitfields
Kojto	90:cb3d968589d8	1024	{
Kojto	90:cb3d968589d8	1025	uint8_t IRCST : 1; /!< [0] Internal Reference Clock Status /
Kojto	90:cb3d968589d8	1026	uint8_t OSCINIT0 : 1; /!< [1] OSC Initialization /
Kojto	90:cb3d968589d8	1027	uint8_t CLKST : 2; /!< [3:2] Clock Mode Status /
Kojto	90:cb3d968589d8	1028	uint8_t IREFST : 1; /!< [4] Internal Reference Status /
Kojto	90:cb3d968589d8	1029	uint8_t PLLST : 1; /!< [5] PLL Select Status /
Kojto	90:cb3d968589d8	1030	uint8_t LOCK0 : 1; /!< [6] Lock Status /
Kojto	90:cb3d968589d8	1031	uint8_t LOLS0 : 1; /!< [7] Loss of Lock Status /
Kojto	90:cb3d968589d8	1032	} B;
Kojto	90:cb3d968589d8	1033	} hw_mcg_s_t;
Kojto	90:cb3d968589d8	1034
Kojto	90:cb3d968589d8	1035	/*!
Kojto	90:cb3d968589d8	1036	* @name Constants and macros for entire MCG_S register
Kojto	90:cb3d968589d8	1037	*/
Kojto	90:cb3d968589d8	1038	/@{/
Kojto	90:cb3d968589d8	1039	#define HW_MCG_S_ADDR(x) ((x) + 0x6U)
Kojto	90:cb3d968589d8	1040
Kojto	90:cb3d968589d8	1041	#define HW_MCG_S(x) ((__IO hw_mcg_s_t ) HW_MCG_S_ADDR(x))
Kojto	90:cb3d968589d8	1042	#define HW_MCG_S_RD(x) (HW_MCG_S(x).U)
Kojto	90:cb3d968589d8	1043	#define HW_MCG_S_WR(x, v) (HW_MCG_S(x).U = (v))
Kojto	90:cb3d968589d8	1044	#define HW_MCG_S_SET(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1045	#define HW_MCG_S_CLR(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1046	#define HW_MCG_S_TOG(x, v) (HW_MCG_S_WR(x, HW_MCG_S_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1047	/@}/
Kojto	90:cb3d968589d8	1048
Kojto	90:cb3d968589d8	1049	/*
Kojto	90:cb3d968589d8	1050	* Constants & macros for individual MCG_S bitfields
Kojto	90:cb3d968589d8	1051	*/
Kojto	90:cb3d968589d8	1052
Kojto	90:cb3d968589d8	1053	/*!
Kojto	90:cb3d968589d8	1054	* @name Register MCG_S, field IRCST[0] (RO)
Kojto	90:cb3d968589d8	1055	*
Kojto	90:cb3d968589d8	1056	* The IRCST bit indicates the current source for the internal reference clock
Kojto	90:cb3d968589d8	1057	* select clock (IRCSCLK). The IRCST bit does not update immediately after a write
Kojto	90:cb3d968589d8	1058	* to the IRCS bit due to internal synchronization between clock domains. The
Kojto	90:cb3d968589d8	1059	* IRCST bit will only be updated if the internal reference clock is enabled,
Kojto	90:cb3d968589d8	1060	* either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
Kojto	90:cb3d968589d8	1061	* bit .
Kojto	90:cb3d968589d8	1062	*
Kojto	90:cb3d968589d8	1063	* Values:
Kojto	90:cb3d968589d8	1064	* - 0 - Source of internal reference clock is the slow clock (32 kHz IRC).
Kojto	90:cb3d968589d8	1065	* - 1 - Source of internal reference clock is the fast clock (4 MHz IRC).
Kojto	90:cb3d968589d8	1066	*/
Kojto	90:cb3d968589d8	1067	/@{/
Kojto	90:cb3d968589d8	1068	#define BP_MCG_S_IRCST (0U) /!< Bit position for MCG_S_IRCST. /
Kojto	90:cb3d968589d8	1069	#define BM_MCG_S_IRCST (0x01U) /!< Bit mask for MCG_S_IRCST. /
Kojto	90:cb3d968589d8	1070	#define BS_MCG_S_IRCST (1U) /!< Bit field size in bits for MCG_S_IRCST. /
Kojto	90:cb3d968589d8	1071
Kojto	90:cb3d968589d8	1072	/! @brief Read current value of the MCG_S_IRCST field. /
Kojto	90:cb3d968589d8	1073	#define BR_MCG_S_IRCST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IRCST))
Kojto	90:cb3d968589d8	1074	/@}/
Kojto	90:cb3d968589d8	1075
Kojto	90:cb3d968589d8	1076	/*!
Kojto	90:cb3d968589d8	1077	* @name Register MCG_S, field OSCINIT0[1] (RO)
Kojto	90:cb3d968589d8	1078	*
Kojto	90:cb3d968589d8	1079	* This bit, which resets to 0, is set to 1 after the initialization cycles of
Kojto	90:cb3d968589d8	1080	* the crystal oscillator clock have completed. After being set, the bit is
Kojto	90:cb3d968589d8	1081	* cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
Kojto	90:cb3d968589d8	1082	* description for more information.
Kojto	90:cb3d968589d8	1083	*/
Kojto	90:cb3d968589d8	1084	/@{/
Kojto	90:cb3d968589d8	1085	#define BP_MCG_S_OSCINIT0 (1U) /!< Bit position for MCG_S_OSCINIT0. /
Kojto	90:cb3d968589d8	1086	#define BM_MCG_S_OSCINIT0 (0x02U) /!< Bit mask for MCG_S_OSCINIT0. /
Kojto	90:cb3d968589d8	1087	#define BS_MCG_S_OSCINIT0 (1U) /!< Bit field size in bits for MCG_S_OSCINIT0. /
Kojto	90:cb3d968589d8	1088
Kojto	90:cb3d968589d8	1089	/! @brief Read current value of the MCG_S_OSCINIT0 field. /
Kojto	90:cb3d968589d8	1090	#define BR_MCG_S_OSCINIT0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_OSCINIT0))
Kojto	90:cb3d968589d8	1091	/@}/
Kojto	90:cb3d968589d8	1092
Kojto	90:cb3d968589d8	1093	/*!
Kojto	90:cb3d968589d8	1094	* @name Register MCG_S, field CLKST[3:2] (RO)
Kojto	90:cb3d968589d8	1095	*
Kojto	90:cb3d968589d8	1096	* These bits indicate the current clock mode. The CLKST bits do not update
Kojto	90:cb3d968589d8	1097	* immediately after a write to the CLKS bits due to internal synchronization between
Kojto	90:cb3d968589d8	1098	* clock domains.
Kojto	90:cb3d968589d8	1099	*
Kojto	90:cb3d968589d8	1100	* Values:
Kojto	90:cb3d968589d8	1101	* - 00 - Encoding 0 - Output of the FLL is selected (reset default).
Kojto	90:cb3d968589d8	1102	* - 01 - Encoding 1 - Internal reference clock is selected.
Kojto	90:cb3d968589d8	1103	* - 10 - Encoding 2 - External reference clock is selected.
Kojto	90:cb3d968589d8	1104	* - 11 - Encoding 3 - Output of the PLL is selected.
Kojto	90:cb3d968589d8	1105	*/
Kojto	90:cb3d968589d8	1106	/@{/
Kojto	90:cb3d968589d8	1107	#define BP_MCG_S_CLKST (2U) /!< Bit position for MCG_S_CLKST. /
Kojto	90:cb3d968589d8	1108	#define BM_MCG_S_CLKST (0x0CU) /!< Bit mask for MCG_S_CLKST. /
Kojto	90:cb3d968589d8	1109	#define BS_MCG_S_CLKST (2U) /!< Bit field size in bits for MCG_S_CLKST. /
Kojto	90:cb3d968589d8	1110
Kojto	90:cb3d968589d8	1111	/! @brief Read current value of the MCG_S_CLKST field. /
Kojto	90:cb3d968589d8	1112	#define BR_MCG_S_CLKST(x) (HW_MCG_S(x).B.CLKST)
Kojto	90:cb3d968589d8	1113	/@}/
Kojto	90:cb3d968589d8	1114
Kojto	90:cb3d968589d8	1115	/*!
Kojto	90:cb3d968589d8	1116	* @name Register MCG_S, field IREFST[4] (RO)
Kojto	90:cb3d968589d8	1117	*
Kojto	90:cb3d968589d8	1118	* This bit indicates the current source for the FLL reference clock. The IREFST
Kojto	90:cb3d968589d8	1119	* bit does not update immediately after a write to the IREFS bit due to
Kojto	90:cb3d968589d8	1120	* internal synchronization between clock domains.
Kojto	90:cb3d968589d8	1121	*
Kojto	90:cb3d968589d8	1122	* Values:
Kojto	90:cb3d968589d8	1123	* - 0 - Source of FLL reference clock is the external reference clock.
Kojto	90:cb3d968589d8	1124	* - 1 - Source of FLL reference clock is the internal reference clock.
Kojto	90:cb3d968589d8	1125	*/
Kojto	90:cb3d968589d8	1126	/@{/
Kojto	90:cb3d968589d8	1127	#define BP_MCG_S_IREFST (4U) /!< Bit position for MCG_S_IREFST. /
Kojto	90:cb3d968589d8	1128	#define BM_MCG_S_IREFST (0x10U) /!< Bit mask for MCG_S_IREFST. /
Kojto	90:cb3d968589d8	1129	#define BS_MCG_S_IREFST (1U) /!< Bit field size in bits for MCG_S_IREFST. /
Kojto	90:cb3d968589d8	1130
Kojto	90:cb3d968589d8	1131	/! @brief Read current value of the MCG_S_IREFST field. /
Kojto	90:cb3d968589d8	1132	#define BR_MCG_S_IREFST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IREFST))
Kojto	90:cb3d968589d8	1133	/@}/
Kojto	90:cb3d968589d8	1134
Kojto	90:cb3d968589d8	1135	/*!
Kojto	90:cb3d968589d8	1136	* @name Register MCG_S, field PLLST[5] (RO)
Kojto	90:cb3d968589d8	1137	*
Kojto	90:cb3d968589d8	1138	* This bit indicates the clock source selected by PLLS . The PLLST bit does not
Kojto	90:cb3d968589d8	1139	* update immediately after a write to the PLLS bit due to internal
Kojto	90:cb3d968589d8	1140	* synchronization between clock domains.
Kojto	90:cb3d968589d8	1141	*
Kojto	90:cb3d968589d8	1142	* Values:
Kojto	90:cb3d968589d8	1143	* - 0 - Source of PLLS clock is FLL clock.
Kojto	90:cb3d968589d8	1144	* - 1 - Source of PLLS clock is PLL output clock.
Kojto	90:cb3d968589d8	1145	*/
Kojto	90:cb3d968589d8	1146	/@{/
Kojto	90:cb3d968589d8	1147	#define BP_MCG_S_PLLST (5U) /!< Bit position for MCG_S_PLLST. /
Kojto	90:cb3d968589d8	1148	#define BM_MCG_S_PLLST (0x20U) /!< Bit mask for MCG_S_PLLST. /
Kojto	90:cb3d968589d8	1149	#define BS_MCG_S_PLLST (1U) /!< Bit field size in bits for MCG_S_PLLST. /
Kojto	90:cb3d968589d8	1150
Kojto	90:cb3d968589d8	1151	/! @brief Read current value of the MCG_S_PLLST field. /
Kojto	90:cb3d968589d8	1152	#define BR_MCG_S_PLLST(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_PLLST))
Kojto	90:cb3d968589d8	1153	/@}/
Kojto	90:cb3d968589d8	1154
Kojto	90:cb3d968589d8	1155	/*!
Kojto	90:cb3d968589d8	1156	* @name Register MCG_S, field LOCK0[6] (RO)
Kojto	90:cb3d968589d8	1157	*
Kojto	90:cb3d968589d8	1158	* This bit indicates whether the PLL has acquired lock. Lock detection is only
Kojto	90:cb3d968589d8	1159	* enabled when the PLL is enabled (either through clock mode selection or
Kojto	90:cb3d968589d8	1160	* PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
Kojto	90:cb3d968589d8	1161	* MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
Kojto	90:cb3d968589d8	1162	* If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
Kojto	90:cb3d968589d8	1163	* the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
Kojto	90:cb3d968589d8	1164	* status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
Kojto	90:cb3d968589d8	1165	* reference clock will also cause the LOCK0 bit to clear until the PLL has
Kojto	90:cb3d968589d8	1166	* reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
Kojto	90:cb3d968589d8	1167	* the lock status bit to clear and stay cleared until the Stop mode is exited
Kojto	90:cb3d968589d8	1168	* and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
Kojto	90:cb3d968589d8	1169	* is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
Kojto	90:cb3d968589d8	1170	* again.
Kojto	90:cb3d968589d8	1171	*
Kojto	90:cb3d968589d8	1172	* Values:
Kojto	90:cb3d968589d8	1173	* - 0 - PLL is currently unlocked.
Kojto	90:cb3d968589d8	1174	* - 1 - PLL is currently locked.
Kojto	90:cb3d968589d8	1175	*/
Kojto	90:cb3d968589d8	1176	/@{/
Kojto	90:cb3d968589d8	1177	#define BP_MCG_S_LOCK0 (6U) /!< Bit position for MCG_S_LOCK0. /
Kojto	90:cb3d968589d8	1178	#define BM_MCG_S_LOCK0 (0x40U) /!< Bit mask for MCG_S_LOCK0. /
Kojto	90:cb3d968589d8	1179	#define BS_MCG_S_LOCK0 (1U) /!< Bit field size in bits for MCG_S_LOCK0. /
Kojto	90:cb3d968589d8	1180
Kojto	90:cb3d968589d8	1181	/! @brief Read current value of the MCG_S_LOCK0 field. /
Kojto	90:cb3d968589d8	1182	#define BR_MCG_S_LOCK0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOCK0))
Kojto	90:cb3d968589d8	1183	/@}/
Kojto	90:cb3d968589d8	1184
Kojto	90:cb3d968589d8	1185	/*!
Kojto	90:cb3d968589d8	1186	* @name Register MCG_S, field LOLS0[7] (W1C)
Kojto	90:cb3d968589d8	1187	*
Kojto	90:cb3d968589d8	1188	* This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
Kojto	90:cb3d968589d8	1189	* if after acquiring lock, the PLL output frequency has fallen outside the lock
Kojto	90:cb3d968589d8	1190	* exit frequency tolerance, D unl . LOLIE determines whether an interrupt
Kojto	90:cb3d968589d8	1191	* request is made when LOLS is set. LOLRE determines whether a reset request is made
Kojto	90:cb3d968589d8	1192	* when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
Kojto	90:cb3d968589d8	1193	* when set. Writing a logic 0 to this bit has no effect.
Kojto	90:cb3d968589d8	1194	*
Kojto	90:cb3d968589d8	1195	* Values:
Kojto	90:cb3d968589d8	1196	* - 0 - PLL has not lost lock since LOLS 0 was last cleared.
Kojto	90:cb3d968589d8	1197	* - 1 - PLL has lost lock since LOLS 0 was last cleared.
Kojto	90:cb3d968589d8	1198	*/
Kojto	90:cb3d968589d8	1199	/@{/
Kojto	90:cb3d968589d8	1200	#define BP_MCG_S_LOLS0 (7U) /!< Bit position for MCG_S_LOLS0. /
Kojto	90:cb3d968589d8	1201	#define BM_MCG_S_LOLS0 (0x80U) /!< Bit mask for MCG_S_LOLS0. /
Kojto	90:cb3d968589d8	1202	#define BS_MCG_S_LOLS0 (1U) /!< Bit field size in bits for MCG_S_LOLS0. /
Kojto	90:cb3d968589d8	1203
Kojto	90:cb3d968589d8	1204	/! @brief Read current value of the MCG_S_LOLS0 field. /
Kojto	90:cb3d968589d8	1205	#define BR_MCG_S_LOLS0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0))
Kojto	90:cb3d968589d8	1206
Kojto	90:cb3d968589d8	1207	/! @brief Format value for bitfield MCG_S_LOLS0. /
Kojto	90:cb3d968589d8	1208	#define BF_MCG_S_LOLS0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_S_LOLS0) & BM_MCG_S_LOLS0)
Kojto	90:cb3d968589d8	1209
Kojto	90:cb3d968589d8	1210	/! @brief Set the LOLS0 field to a new value. /
Kojto	90:cb3d968589d8	1211	#define BW_MCG_S_LOLS0(x, v) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0) = (v))
Kojto	90:cb3d968589d8	1212	/@}/
Kojto	90:cb3d968589d8	1213
Kojto	90:cb3d968589d8	1214	/*******************************************************************************
Kojto	90:cb3d968589d8	1215	* HW_MCG_SC - MCG Status and Control Register
Kojto	90:cb3d968589d8	1216	******************************************************************************/
Kojto	90:cb3d968589d8	1217
Kojto	90:cb3d968589d8	1218	/*!
Kojto	90:cb3d968589d8	1219	* @brief HW_MCG_SC - MCG Status and Control Register (RW)
Kojto	90:cb3d968589d8	1220	*
Kojto	90:cb3d968589d8	1221	* Reset value: 0x02U
Kojto	90:cb3d968589d8	1222	*/
Kojto	90:cb3d968589d8	1223	typedef union _hw_mcg_sc
Kojto	90:cb3d968589d8	1224	{
Kojto	90:cb3d968589d8	1225	uint8_t U;
Kojto	90:cb3d968589d8	1226	struct _hw_mcg_sc_bitfields
Kojto	90:cb3d968589d8	1227	{
Kojto	90:cb3d968589d8	1228	uint8_t LOCS0 : 1; /!< [0] OSC0 Loss of Clock Status /
Kojto	90:cb3d968589d8	1229	uint8_t FCRDIV : 3; /*!< [3:1] Fast Clock Internal Reference Divider
Kojto	90:cb3d968589d8	1230	* */
Kojto	90:cb3d968589d8	1231	uint8_t FLTPRSRV : 1; /!< [4] FLL Filter Preserve Enable /
Kojto	90:cb3d968589d8	1232	uint8_t ATMF : 1; /!< [5] Automatic Trim Machine Fail Flag /
Kojto	90:cb3d968589d8	1233	uint8_t ATMS : 1; /!< [6] Automatic Trim Machine Select /
Kojto	90:cb3d968589d8	1234	uint8_t ATME : 1; /!< [7] Automatic Trim Machine Enable /
Kojto	90:cb3d968589d8	1235	} B;
Kojto	90:cb3d968589d8	1236	} hw_mcg_sc_t;
Kojto	90:cb3d968589d8	1237
Kojto	90:cb3d968589d8	1238	/*!
Kojto	90:cb3d968589d8	1239	* @name Constants and macros for entire MCG_SC register
Kojto	90:cb3d968589d8	1240	*/
Kojto	90:cb3d968589d8	1241	/@{/
Kojto	90:cb3d968589d8	1242	#define HW_MCG_SC_ADDR(x) ((x) + 0x8U)
Kojto	90:cb3d968589d8	1243
Kojto	90:cb3d968589d8	1244	#define HW_MCG_SC(x) ((__IO hw_mcg_sc_t ) HW_MCG_SC_ADDR(x))
Kojto	90:cb3d968589d8	1245	#define HW_MCG_SC_RD(x) (HW_MCG_SC(x).U)
Kojto	90:cb3d968589d8	1246	#define HW_MCG_SC_WR(x, v) (HW_MCG_SC(x).U = (v))
Kojto	90:cb3d968589d8	1247	#define HW_MCG_SC_SET(x, v) (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1248	#define HW_MCG_SC_CLR(x, v) (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1249	#define HW_MCG_SC_TOG(x, v) (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1250	/@}/
Kojto	90:cb3d968589d8	1251
Kojto	90:cb3d968589d8	1252	/*
Kojto	90:cb3d968589d8	1253	* Constants & macros for individual MCG_SC bitfields
Kojto	90:cb3d968589d8	1254	*/
Kojto	90:cb3d968589d8	1255
Kojto	90:cb3d968589d8	1256	/*!
Kojto	90:cb3d968589d8	1257	* @name Register MCG_SC, field LOCS0[0] (W1C)
Kojto	90:cb3d968589d8	1258	*
Kojto	90:cb3d968589d8	1259	* The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
Kojto	90:cb3d968589d8	1260	* LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
Kojto	90:cb3d968589d8	1261	* logic 1 to it when set.
Kojto	90:cb3d968589d8	1262	*
Kojto	90:cb3d968589d8	1263	* Values:
Kojto	90:cb3d968589d8	1264	* - 0 - Loss of OSC0 has not occurred.
Kojto	90:cb3d968589d8	1265	* - 1 - Loss of OSC0 has occurred.
Kojto	90:cb3d968589d8	1266	*/
Kojto	90:cb3d968589d8	1267	/@{/
Kojto	90:cb3d968589d8	1268	#define BP_MCG_SC_LOCS0 (0U) /!< Bit position for MCG_SC_LOCS0. /
Kojto	90:cb3d968589d8	1269	#define BM_MCG_SC_LOCS0 (0x01U) /!< Bit mask for MCG_SC_LOCS0. /
Kojto	90:cb3d968589d8	1270	#define BS_MCG_SC_LOCS0 (1U) /!< Bit field size in bits for MCG_SC_LOCS0. /
Kojto	90:cb3d968589d8	1271
Kojto	90:cb3d968589d8	1272	/! @brief Read current value of the MCG_SC_LOCS0 field. /
Kojto	90:cb3d968589d8	1273	#define BR_MCG_SC_LOCS0(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_LOCS0))
Kojto	90:cb3d968589d8	1274
Kojto	90:cb3d968589d8	1275	/! @brief Format value for bitfield MCG_SC_LOCS0. /
Kojto	90:cb3d968589d8	1276	#define BF_MCG_SC_LOCS0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_LOCS0) & BM_MCG_SC_LOCS0)
Kojto	90:cb3d968589d8	1277
Kojto	90:cb3d968589d8	1278	/! @brief Set the LOCS0 field to a new value. /
Kojto	90:cb3d968589d8	1279	#define BW_MCG_SC_LOCS0(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_LOCS0) = (v))
Kojto	90:cb3d968589d8	1280	/@}/
Kojto	90:cb3d968589d8	1281
Kojto	90:cb3d968589d8	1282	/*!
Kojto	90:cb3d968589d8	1283	* @name Register MCG_SC, field FCRDIV[3:1] (RW)
Kojto	90:cb3d968589d8	1284	*
Kojto	90:cb3d968589d8	1285	* Selects the amount to divide down the fast internal reference clock. The
Kojto	90:cb3d968589d8	1286	* resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
Kojto	90:cb3d968589d8	1287	* divider when the Fast IRC is enabled is not supported).
Kojto	90:cb3d968589d8	1288	*
Kojto	90:cb3d968589d8	1289	* Values:
Kojto	90:cb3d968589d8	1290	* - 000 - Divide Factor is 1
Kojto	90:cb3d968589d8	1291	* - 001 - Divide Factor is 2.
Kojto	90:cb3d968589d8	1292	* - 010 - Divide Factor is 4.
Kojto	90:cb3d968589d8	1293	* - 011 - Divide Factor is 8.
Kojto	90:cb3d968589d8	1294	* - 100 - Divide Factor is 16
Kojto	90:cb3d968589d8	1295	* - 101 - Divide Factor is 32
Kojto	90:cb3d968589d8	1296	* - 110 - Divide Factor is 64
Kojto	90:cb3d968589d8	1297	* - 111 - Divide Factor is 128.
Kojto	90:cb3d968589d8	1298	*/
Kojto	90:cb3d968589d8	1299	/@{/
Kojto	90:cb3d968589d8	1300	#define BP_MCG_SC_FCRDIV (1U) /!< Bit position for MCG_SC_FCRDIV. /
Kojto	90:cb3d968589d8	1301	#define BM_MCG_SC_FCRDIV (0x0EU) /!< Bit mask for MCG_SC_FCRDIV. /
Kojto	90:cb3d968589d8	1302	#define BS_MCG_SC_FCRDIV (3U) /!< Bit field size in bits for MCG_SC_FCRDIV. /
Kojto	90:cb3d968589d8	1303
Kojto	90:cb3d968589d8	1304	/! @brief Read current value of the MCG_SC_FCRDIV field. /
Kojto	90:cb3d968589d8	1305	#define BR_MCG_SC_FCRDIV(x) (HW_MCG_SC(x).B.FCRDIV)
Kojto	90:cb3d968589d8	1306
Kojto	90:cb3d968589d8	1307	/! @brief Format value for bitfield MCG_SC_FCRDIV. /
Kojto	90:cb3d968589d8	1308	#define BF_MCG_SC_FCRDIV(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_FCRDIV) & BM_MCG_SC_FCRDIV)
Kojto	90:cb3d968589d8	1309
Kojto	90:cb3d968589d8	1310	/! @brief Set the FCRDIV field to a new value. /
Kojto	90:cb3d968589d8	1311	#define BW_MCG_SC_FCRDIV(x, v) (HW_MCG_SC_WR(x, (HW_MCG_SC_RD(x) & ~BM_MCG_SC_FCRDIV) \| BF_MCG_SC_FCRDIV(v)))
Kojto	90:cb3d968589d8	1312	/@}/
Kojto	90:cb3d968589d8	1313
Kojto	90:cb3d968589d8	1314	/*!
Kojto	90:cb3d968589d8	1315	* @name Register MCG_SC, field FLTPRSRV[4] (RW)
Kojto	90:cb3d968589d8	1316	*
Kojto	90:cb3d968589d8	1317	* This bit will prevent the FLL filter values from resetting allowing the FLL
Kojto	90:cb3d968589d8	1318	* output frequency to remain the same during clock mode changes where the FLL/DCO
Kojto	90:cb3d968589d8	1319	* output is still valid. (Note: This requires that the FLL reference frequency
Kojto	90:cb3d968589d8	1320	* to remain the same as what it was prior to the new clock mode switch.
Kojto	90:cb3d968589d8	1321	* Otherwise FLL filter and frequency values will change.)
Kojto	90:cb3d968589d8	1322	*
Kojto	90:cb3d968589d8	1323	* Values:
Kojto	90:cb3d968589d8	1324	* - 0 - FLL filter and FLL frequency will reset on changes to currect clock
Kojto	90:cb3d968589d8	1325	* mode.
Kojto	90:cb3d968589d8	1326	* - 1 - Fll filter and FLL frequency retain their previous values during new
Kojto	90:cb3d968589d8	1327	* clock mode change.
Kojto	90:cb3d968589d8	1328	*/
Kojto	90:cb3d968589d8	1329	/@{/
Kojto	90:cb3d968589d8	1330	#define BP_MCG_SC_FLTPRSRV (4U) /!< Bit position for MCG_SC_FLTPRSRV. /
Kojto	90:cb3d968589d8	1331	#define BM_MCG_SC_FLTPRSRV (0x10U) /!< Bit mask for MCG_SC_FLTPRSRV. /
Kojto	90:cb3d968589d8	1332	#define BS_MCG_SC_FLTPRSRV (1U) /!< Bit field size in bits for MCG_SC_FLTPRSRV. /
Kojto	90:cb3d968589d8	1333
Kojto	90:cb3d968589d8	1334	/! @brief Read current value of the MCG_SC_FLTPRSRV field. /
Kojto	90:cb3d968589d8	1335	#define BR_MCG_SC_FLTPRSRV(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_FLTPRSRV))
Kojto	90:cb3d968589d8	1336
Kojto	90:cb3d968589d8	1337	/! @brief Format value for bitfield MCG_SC_FLTPRSRV. /
Kojto	90:cb3d968589d8	1338	#define BF_MCG_SC_FLTPRSRV(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_FLTPRSRV) & BM_MCG_SC_FLTPRSRV)
Kojto	90:cb3d968589d8	1339
Kojto	90:cb3d968589d8	1340	/! @brief Set the FLTPRSRV field to a new value. /
Kojto	90:cb3d968589d8	1341	#define BW_MCG_SC_FLTPRSRV(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_FLTPRSRV) = (v))
Kojto	90:cb3d968589d8	1342	/@}/
Kojto	90:cb3d968589d8	1343
Kojto	90:cb3d968589d8	1344	/*!
Kojto	90:cb3d968589d8	1345	* @name Register MCG_SC, field ATMF[5] (RW)
Kojto	90:cb3d968589d8	1346	*
Kojto	90:cb3d968589d8	1347	* Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
Kojto	90:cb3d968589d8	1348	* Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
Kojto	90:cb3d968589d8	1349	* registers is detected or the MCG enters into any Stop mode. A write to ATMF
Kojto	90:cb3d968589d8	1350	* clears the flag.
Kojto	90:cb3d968589d8	1351	*
Kojto	90:cb3d968589d8	1352	* Values:
Kojto	90:cb3d968589d8	1353	* - 0 - Automatic Trim Machine completed normally.
Kojto	90:cb3d968589d8	1354	* - 1 - Automatic Trim Machine failed.
Kojto	90:cb3d968589d8	1355	*/
Kojto	90:cb3d968589d8	1356	/@{/
Kojto	90:cb3d968589d8	1357	#define BP_MCG_SC_ATMF (5U) /!< Bit position for MCG_SC_ATMF. /
Kojto	90:cb3d968589d8	1358	#define BM_MCG_SC_ATMF (0x20U) /!< Bit mask for MCG_SC_ATMF. /
Kojto	90:cb3d968589d8	1359	#define BS_MCG_SC_ATMF (1U) /!< Bit field size in bits for MCG_SC_ATMF. /
Kojto	90:cb3d968589d8	1360
Kojto	90:cb3d968589d8	1361	/! @brief Read current value of the MCG_SC_ATMF field. /
Kojto	90:cb3d968589d8	1362	#define BR_MCG_SC_ATMF(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMF))
Kojto	90:cb3d968589d8	1363
Kojto	90:cb3d968589d8	1364	/! @brief Format value for bitfield MCG_SC_ATMF. /
Kojto	90:cb3d968589d8	1365	#define BF_MCG_SC_ATMF(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATMF) & BM_MCG_SC_ATMF)
Kojto	90:cb3d968589d8	1366
Kojto	90:cb3d968589d8	1367	/! @brief Set the ATMF field to a new value. /
Kojto	90:cb3d968589d8	1368	#define BW_MCG_SC_ATMF(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMF) = (v))
Kojto	90:cb3d968589d8	1369	/@}/
Kojto	90:cb3d968589d8	1370
Kojto	90:cb3d968589d8	1371	/*!
Kojto	90:cb3d968589d8	1372	* @name Register MCG_SC, field ATMS[6] (RW)
Kojto	90:cb3d968589d8	1373	*
Kojto	90:cb3d968589d8	1374	* Selects the IRCS clock for Auto Trim Test.
Kojto	90:cb3d968589d8	1375	*
Kojto	90:cb3d968589d8	1376	* Values:
Kojto	90:cb3d968589d8	1377	* - 0 - 32 kHz Internal Reference Clock selected.
Kojto	90:cb3d968589d8	1378	* - 1 - 4 MHz Internal Reference Clock selected.
Kojto	90:cb3d968589d8	1379	*/
Kojto	90:cb3d968589d8	1380	/@{/
Kojto	90:cb3d968589d8	1381	#define BP_MCG_SC_ATMS (6U) /!< Bit position for MCG_SC_ATMS. /
Kojto	90:cb3d968589d8	1382	#define BM_MCG_SC_ATMS (0x40U) /!< Bit mask for MCG_SC_ATMS. /
Kojto	90:cb3d968589d8	1383	#define BS_MCG_SC_ATMS (1U) /!< Bit field size in bits for MCG_SC_ATMS. /
Kojto	90:cb3d968589d8	1384
Kojto	90:cb3d968589d8	1385	/! @brief Read current value of the MCG_SC_ATMS field. /
Kojto	90:cb3d968589d8	1386	#define BR_MCG_SC_ATMS(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMS))
Kojto	90:cb3d968589d8	1387
Kojto	90:cb3d968589d8	1388	/! @brief Format value for bitfield MCG_SC_ATMS. /
Kojto	90:cb3d968589d8	1389	#define BF_MCG_SC_ATMS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATMS) & BM_MCG_SC_ATMS)
Kojto	90:cb3d968589d8	1390
Kojto	90:cb3d968589d8	1391	/! @brief Set the ATMS field to a new value. /
Kojto	90:cb3d968589d8	1392	#define BW_MCG_SC_ATMS(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMS) = (v))
Kojto	90:cb3d968589d8	1393	/@}/
Kojto	90:cb3d968589d8	1394
Kojto	90:cb3d968589d8	1395	/*!
Kojto	90:cb3d968589d8	1396	* @name Register MCG_SC, field ATME[7] (RW)
Kojto	90:cb3d968589d8	1397	*
Kojto	90:cb3d968589d8	1398	* Enables the Auto Trim Machine to start automatically trimming the selected
Kojto	90:cb3d968589d8	1399	* Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
Kojto	90:cb3d968589d8	1400	* completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
Kojto	90:cb3d968589d8	1401	* to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
Kojto	90:cb3d968589d8	1402	* operation and clears this bit.
Kojto	90:cb3d968589d8	1403	*
Kojto	90:cb3d968589d8	1404	* Values:
Kojto	90:cb3d968589d8	1405	* - 0 - Auto Trim Machine disabled.
Kojto	90:cb3d968589d8	1406	* - 1 - Auto Trim Machine enabled.
Kojto	90:cb3d968589d8	1407	*/
Kojto	90:cb3d968589d8	1408	/@{/
Kojto	90:cb3d968589d8	1409	#define BP_MCG_SC_ATME (7U) /!< Bit position for MCG_SC_ATME. /
Kojto	90:cb3d968589d8	1410	#define BM_MCG_SC_ATME (0x80U) /!< Bit mask for MCG_SC_ATME. /
Kojto	90:cb3d968589d8	1411	#define BS_MCG_SC_ATME (1U) /!< Bit field size in bits for MCG_SC_ATME. /
Kojto	90:cb3d968589d8	1412
Kojto	90:cb3d968589d8	1413	/! @brief Read current value of the MCG_SC_ATME field. /
Kojto	90:cb3d968589d8	1414	#define BR_MCG_SC_ATME(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATME))
Kojto	90:cb3d968589d8	1415
Kojto	90:cb3d968589d8	1416	/! @brief Format value for bitfield MCG_SC_ATME. /
Kojto	90:cb3d968589d8	1417	#define BF_MCG_SC_ATME(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATME) & BM_MCG_SC_ATME)
Kojto	90:cb3d968589d8	1418
Kojto	90:cb3d968589d8	1419	/! @brief Set the ATME field to a new value. /
Kojto	90:cb3d968589d8	1420	#define BW_MCG_SC_ATME(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATME) = (v))
Kojto	90:cb3d968589d8	1421	/@}/
Kojto	90:cb3d968589d8	1422
Kojto	90:cb3d968589d8	1423	/*******************************************************************************
Kojto	90:cb3d968589d8	1424	* HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
Kojto	90:cb3d968589d8	1425	******************************************************************************/
Kojto	90:cb3d968589d8	1426
Kojto	90:cb3d968589d8	1427	/*!
Kojto	90:cb3d968589d8	1428	* @brief HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
Kojto	90:cb3d968589d8	1429	*
Kojto	90:cb3d968589d8	1430	* Reset value: 0x00U
Kojto	90:cb3d968589d8	1431	*/
Kojto	90:cb3d968589d8	1432	typedef union _hw_mcg_atcvh
Kojto	90:cb3d968589d8	1433	{
Kojto	90:cb3d968589d8	1434	uint8_t U;
Kojto	90:cb3d968589d8	1435	struct _hw_mcg_atcvh_bitfields
Kojto	90:cb3d968589d8	1436	{
Kojto	90:cb3d968589d8	1437	uint8_t ATCVH : 8; /!< [7:0] ATM Compare Value High /
Kojto	90:cb3d968589d8	1438	} B;
Kojto	90:cb3d968589d8	1439	} hw_mcg_atcvh_t;
Kojto	90:cb3d968589d8	1440
Kojto	90:cb3d968589d8	1441	/*!
Kojto	90:cb3d968589d8	1442	* @name Constants and macros for entire MCG_ATCVH register
Kojto	90:cb3d968589d8	1443	*/
Kojto	90:cb3d968589d8	1444	/@{/
Kojto	90:cb3d968589d8	1445	#define HW_MCG_ATCVH_ADDR(x) ((x) + 0xAU)
Kojto	90:cb3d968589d8	1446
Kojto	90:cb3d968589d8	1447	#define HW_MCG_ATCVH(x) ((__IO hw_mcg_atcvh_t ) HW_MCG_ATCVH_ADDR(x))
Kojto	90:cb3d968589d8	1448	#define HW_MCG_ATCVH_RD(x) (HW_MCG_ATCVH(x).U)
Kojto	90:cb3d968589d8	1449	#define HW_MCG_ATCVH_WR(x, v) (HW_MCG_ATCVH(x).U = (v))
Kojto	90:cb3d968589d8	1450	#define HW_MCG_ATCVH_SET(x, v) (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1451	#define HW_MCG_ATCVH_CLR(x, v) (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1452	#define HW_MCG_ATCVH_TOG(x, v) (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1453	/@}/
Kojto	90:cb3d968589d8	1454
Kojto	90:cb3d968589d8	1455	/*
Kojto	90:cb3d968589d8	1456	* Constants & macros for individual MCG_ATCVH bitfields
Kojto	90:cb3d968589d8	1457	*/
Kojto	90:cb3d968589d8	1458
Kojto	90:cb3d968589d8	1459	/*!
Kojto	90:cb3d968589d8	1460	* @name Register MCG_ATCVH, field ATCVH[7:0] (RW)
Kojto	90:cb3d968589d8	1461	*
Kojto	90:cb3d968589d8	1462	* Values are used by Auto Trim Machine to compare and adjust Internal Reference
Kojto	90:cb3d968589d8	1463	* trim values during ATM SAR conversion.
Kojto	90:cb3d968589d8	1464	*/
Kojto	90:cb3d968589d8	1465	/@{/
Kojto	90:cb3d968589d8	1466	#define BP_MCG_ATCVH_ATCVH (0U) /!< Bit position for MCG_ATCVH_ATCVH. /
Kojto	90:cb3d968589d8	1467	#define BM_MCG_ATCVH_ATCVH (0xFFU) /!< Bit mask for MCG_ATCVH_ATCVH. /
Kojto	90:cb3d968589d8	1468	#define BS_MCG_ATCVH_ATCVH (8U) /!< Bit field size in bits for MCG_ATCVH_ATCVH. /
Kojto	90:cb3d968589d8	1469
Kojto	90:cb3d968589d8	1470	/! @brief Read current value of the MCG_ATCVH_ATCVH field. /
Kojto	90:cb3d968589d8	1471	#define BR_MCG_ATCVH_ATCVH(x) (HW_MCG_ATCVH(x).U)
Kojto	90:cb3d968589d8	1472
Kojto	90:cb3d968589d8	1473	/! @brief Format value for bitfield MCG_ATCVH_ATCVH. /
Kojto	90:cb3d968589d8	1474	#define BF_MCG_ATCVH_ATCVH(v) ((uint8_t)((uint8_t)(v) << BP_MCG_ATCVH_ATCVH) & BM_MCG_ATCVH_ATCVH)
Kojto	90:cb3d968589d8	1475
Kojto	90:cb3d968589d8	1476	/! @brief Set the ATCVH field to a new value. /
Kojto	90:cb3d968589d8	1477	#define BW_MCG_ATCVH_ATCVH(x, v) (HW_MCG_ATCVH_WR(x, v))
Kojto	90:cb3d968589d8	1478	/@}/
Kojto	90:cb3d968589d8	1479
Kojto	90:cb3d968589d8	1480	/*******************************************************************************
Kojto	90:cb3d968589d8	1481	* HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
Kojto	90:cb3d968589d8	1482	******************************************************************************/
Kojto	90:cb3d968589d8	1483
Kojto	90:cb3d968589d8	1484	/*!
Kojto	90:cb3d968589d8	1485	* @brief HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
Kojto	90:cb3d968589d8	1486	*
Kojto	90:cb3d968589d8	1487	* Reset value: 0x00U
Kojto	90:cb3d968589d8	1488	*/
Kojto	90:cb3d968589d8	1489	typedef union _hw_mcg_atcvl
Kojto	90:cb3d968589d8	1490	{
Kojto	90:cb3d968589d8	1491	uint8_t U;
Kojto	90:cb3d968589d8	1492	struct _hw_mcg_atcvl_bitfields
Kojto	90:cb3d968589d8	1493	{
Kojto	90:cb3d968589d8	1494	uint8_t ATCVL : 8; /!< [7:0] ATM Compare Value Low /
Kojto	90:cb3d968589d8	1495	} B;
Kojto	90:cb3d968589d8	1496	} hw_mcg_atcvl_t;
Kojto	90:cb3d968589d8	1497
Kojto	90:cb3d968589d8	1498	/*!
Kojto	90:cb3d968589d8	1499	* @name Constants and macros for entire MCG_ATCVL register
Kojto	90:cb3d968589d8	1500	*/
Kojto	90:cb3d968589d8	1501	/@{/
Kojto	90:cb3d968589d8	1502	#define HW_MCG_ATCVL_ADDR(x) ((x) + 0xBU)
Kojto	90:cb3d968589d8	1503
Kojto	90:cb3d968589d8	1504	#define HW_MCG_ATCVL(x) ((__IO hw_mcg_atcvl_t ) HW_MCG_ATCVL_ADDR(x))
Kojto	90:cb3d968589d8	1505	#define HW_MCG_ATCVL_RD(x) (HW_MCG_ATCVL(x).U)
Kojto	90:cb3d968589d8	1506	#define HW_MCG_ATCVL_WR(x, v) (HW_MCG_ATCVL(x).U = (v))
Kojto	90:cb3d968589d8	1507	#define HW_MCG_ATCVL_SET(x, v) (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1508	#define HW_MCG_ATCVL_CLR(x, v) (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1509	#define HW_MCG_ATCVL_TOG(x, v) (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1510	/@}/
Kojto	90:cb3d968589d8	1511
Kojto	90:cb3d968589d8	1512	/*
Kojto	90:cb3d968589d8	1513	* Constants & macros for individual MCG_ATCVL bitfields
Kojto	90:cb3d968589d8	1514	*/
Kojto	90:cb3d968589d8	1515
Kojto	90:cb3d968589d8	1516	/*!
Kojto	90:cb3d968589d8	1517	* @name Register MCG_ATCVL, field ATCVL[7:0] (RW)
Kojto	90:cb3d968589d8	1518	*
Kojto	90:cb3d968589d8	1519	* Values are used by Auto Trim Machine to compare and adjust Internal Reference
Kojto	90:cb3d968589d8	1520	* trim values during ATM SAR conversion.
Kojto	90:cb3d968589d8	1521	*/
Kojto	90:cb3d968589d8	1522	/@{/
Kojto	90:cb3d968589d8	1523	#define BP_MCG_ATCVL_ATCVL (0U) /!< Bit position for MCG_ATCVL_ATCVL. /
Kojto	90:cb3d968589d8	1524	#define BM_MCG_ATCVL_ATCVL (0xFFU) /!< Bit mask for MCG_ATCVL_ATCVL. /
Kojto	90:cb3d968589d8	1525	#define BS_MCG_ATCVL_ATCVL (8U) /!< Bit field size in bits for MCG_ATCVL_ATCVL. /
Kojto	90:cb3d968589d8	1526
Kojto	90:cb3d968589d8	1527	/! @brief Read current value of the MCG_ATCVL_ATCVL field. /
Kojto	90:cb3d968589d8	1528	#define BR_MCG_ATCVL_ATCVL(x) (HW_MCG_ATCVL(x).U)
Kojto	90:cb3d968589d8	1529
Kojto	90:cb3d968589d8	1530	/! @brief Format value for bitfield MCG_ATCVL_ATCVL. /
Kojto	90:cb3d968589d8	1531	#define BF_MCG_ATCVL_ATCVL(v) ((uint8_t)((uint8_t)(v) << BP_MCG_ATCVL_ATCVL) & BM_MCG_ATCVL_ATCVL)
Kojto	90:cb3d968589d8	1532
Kojto	90:cb3d968589d8	1533	/! @brief Set the ATCVL field to a new value. /
Kojto	90:cb3d968589d8	1534	#define BW_MCG_ATCVL_ATCVL(x, v) (HW_MCG_ATCVL_WR(x, v))
Kojto	90:cb3d968589d8	1535	/@}/
Kojto	90:cb3d968589d8	1536
Kojto	90:cb3d968589d8	1537	/*******************************************************************************
Kojto	90:cb3d968589d8	1538	* HW_MCG_C7 - MCG Control 7 Register
Kojto	90:cb3d968589d8	1539	******************************************************************************/
Kojto	90:cb3d968589d8	1540
Kojto	90:cb3d968589d8	1541	/*!
Kojto	90:cb3d968589d8	1542	* @brief HW_MCG_C7 - MCG Control 7 Register (RW)
Kojto	90:cb3d968589d8	1543	*
Kojto	90:cb3d968589d8	1544	* Reset value: 0x00U
Kojto	90:cb3d968589d8	1545	*/
Kojto	90:cb3d968589d8	1546	typedef union _hw_mcg_c7
Kojto	90:cb3d968589d8	1547	{
Kojto	90:cb3d968589d8	1548	uint8_t U;
Kojto	90:cb3d968589d8	1549	struct _hw_mcg_c7_bitfields
Kojto	90:cb3d968589d8	1550	{
Kojto	90:cb3d968589d8	1551	uint8_t OSCSEL : 2; /!< [1:0] MCG OSC Clock Select /
Kojto	90:cb3d968589d8	1552	uint8_t RESERVED0 : 6; /!< [7:2] /
Kojto	90:cb3d968589d8	1553	} B;
Kojto	90:cb3d968589d8	1554	} hw_mcg_c7_t;
Kojto	90:cb3d968589d8	1555
Kojto	90:cb3d968589d8	1556	/*!
Kojto	90:cb3d968589d8	1557	* @name Constants and macros for entire MCG_C7 register
Kojto	90:cb3d968589d8	1558	*/
Kojto	90:cb3d968589d8	1559	/@{/
Kojto	90:cb3d968589d8	1560	#define HW_MCG_C7_ADDR(x) ((x) + 0xCU)
Kojto	90:cb3d968589d8	1561
Kojto	90:cb3d968589d8	1562	#define HW_MCG_C7(x) ((__IO hw_mcg_c7_t ) HW_MCG_C7_ADDR(x))
Kojto	90:cb3d968589d8	1563	#define HW_MCG_C7_RD(x) (HW_MCG_C7(x).U)
Kojto	90:cb3d968589d8	1564	#define HW_MCG_C7_WR(x, v) (HW_MCG_C7(x).U = (v))
Kojto	90:cb3d968589d8	1565	#define HW_MCG_C7_SET(x, v) (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1566	#define HW_MCG_C7_CLR(x, v) (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1567	#define HW_MCG_C7_TOG(x, v) (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1568	/@}/
Kojto	90:cb3d968589d8	1569
Kojto	90:cb3d968589d8	1570	/*
Kojto	90:cb3d968589d8	1571	* Constants & macros for individual MCG_C7 bitfields
Kojto	90:cb3d968589d8	1572	*/
Kojto	90:cb3d968589d8	1573
Kojto	90:cb3d968589d8	1574	/*!
Kojto	90:cb3d968589d8	1575	* @name Register MCG_C7, field OSCSEL[1:0] (RW)
Kojto	90:cb3d968589d8	1576	*
Kojto	90:cb3d968589d8	1577	* Selects the MCG FLL external reference clock
Kojto	90:cb3d968589d8	1578	*
Kojto	90:cb3d968589d8	1579	* Values:
Kojto	90:cb3d968589d8	1580	* - 00 - Selects Oscillator (OSCCLK0).
Kojto	90:cb3d968589d8	1581	* - 01 - Selects 32 kHz RTC Oscillator.
Kojto	90:cb3d968589d8	1582	* - 10 - Selects Oscillator (OSCCLK1).
Kojto	90:cb3d968589d8	1583	* - 11 - RESERVED
Kojto	90:cb3d968589d8	1584	*/
Kojto	90:cb3d968589d8	1585	/@{/
Kojto	90:cb3d968589d8	1586	#define BP_MCG_C7_OSCSEL (0U) /!< Bit position for MCG_C7_OSCSEL. /
Kojto	90:cb3d968589d8	1587	#define BM_MCG_C7_OSCSEL (0x03U) /!< Bit mask for MCG_C7_OSCSEL. /
Kojto	90:cb3d968589d8	1588	#define BS_MCG_C7_OSCSEL (2U) /!< Bit field size in bits for MCG_C7_OSCSEL. /
Kojto	90:cb3d968589d8	1589
Kojto	90:cb3d968589d8	1590	/! @brief Read current value of the MCG_C7_OSCSEL field. /
Kojto	90:cb3d968589d8	1591	#define BR_MCG_C7_OSCSEL(x) (HW_MCG_C7(x).B.OSCSEL)
Kojto	90:cb3d968589d8	1592
Kojto	90:cb3d968589d8	1593	/! @brief Format value for bitfield MCG_C7_OSCSEL. /
Kojto	90:cb3d968589d8	1594	#define BF_MCG_C7_OSCSEL(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C7_OSCSEL) & BM_MCG_C7_OSCSEL)
Kojto	90:cb3d968589d8	1595
Kojto	90:cb3d968589d8	1596	/! @brief Set the OSCSEL field to a new value. /
Kojto	90:cb3d968589d8	1597	#define BW_MCG_C7_OSCSEL(x, v) (HW_MCG_C7_WR(x, (HW_MCG_C7_RD(x) & ~BM_MCG_C7_OSCSEL) \| BF_MCG_C7_OSCSEL(v)))
Kojto	90:cb3d968589d8	1598	/@}/
Kojto	90:cb3d968589d8	1599
Kojto	90:cb3d968589d8	1600	/*******************************************************************************
Kojto	90:cb3d968589d8	1601	* HW_MCG_C8 - MCG Control 8 Register
Kojto	90:cb3d968589d8	1602	******************************************************************************/
Kojto	90:cb3d968589d8	1603
Kojto	90:cb3d968589d8	1604	/*!
Kojto	90:cb3d968589d8	1605	* @brief HW_MCG_C8 - MCG Control 8 Register (RW)
Kojto	90:cb3d968589d8	1606	*
Kojto	90:cb3d968589d8	1607	* Reset value: 0x80U
Kojto	90:cb3d968589d8	1608	*/
Kojto	90:cb3d968589d8	1609	typedef union _hw_mcg_c8
Kojto	90:cb3d968589d8	1610	{
Kojto	90:cb3d968589d8	1611	uint8_t U;
Kojto	90:cb3d968589d8	1612	struct _hw_mcg_c8_bitfields
Kojto	90:cb3d968589d8	1613	{
Kojto	90:cb3d968589d8	1614	uint8_t LOCS1 : 1; /!< [0] RTC Loss of Clock Status /
Kojto	90:cb3d968589d8	1615	uint8_t RESERVED0 : 4; /!< [4:1] /
Kojto	90:cb3d968589d8	1616	uint8_t CME1 : 1; /!< [5] Clock Monitor Enable1 /
Kojto	90:cb3d968589d8	1617	uint8_t LOLRE : 1; /!< [6] PLL Loss of Lock Reset Enable /
Kojto	90:cb3d968589d8	1618	uint8_t LOCRE1 : 1; /!< [7] Loss of Clock Reset Enable /
Kojto	90:cb3d968589d8	1619	} B;
Kojto	90:cb3d968589d8	1620	} hw_mcg_c8_t;
Kojto	90:cb3d968589d8	1621
Kojto	90:cb3d968589d8	1622	/*!
Kojto	90:cb3d968589d8	1623	* @name Constants and macros for entire MCG_C8 register
Kojto	90:cb3d968589d8	1624	*/
Kojto	90:cb3d968589d8	1625	/@{/
Kojto	90:cb3d968589d8	1626	#define HW_MCG_C8_ADDR(x) ((x) + 0xDU)
Kojto	90:cb3d968589d8	1627
Kojto	90:cb3d968589d8	1628	#define HW_MCG_C8(x) ((__IO hw_mcg_c8_t ) HW_MCG_C8_ADDR(x))
Kojto	90:cb3d968589d8	1629	#define HW_MCG_C8_RD(x) (HW_MCG_C8(x).U)
Kojto	90:cb3d968589d8	1630	#define HW_MCG_C8_WR(x, v) (HW_MCG_C8(x).U = (v))
Kojto	90:cb3d968589d8	1631	#define HW_MCG_C8_SET(x, v) (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1632	#define HW_MCG_C8_CLR(x, v) (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1633	#define HW_MCG_C8_TOG(x, v) (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1634	/@}/
Kojto	90:cb3d968589d8	1635
Kojto	90:cb3d968589d8	1636	/*
Kojto	90:cb3d968589d8	1637	* Constants & macros for individual MCG_C8 bitfields
Kojto	90:cb3d968589d8	1638	*/
Kojto	90:cb3d968589d8	1639
Kojto	90:cb3d968589d8	1640	/*!
Kojto	90:cb3d968589d8	1641	* @name Register MCG_C8, field LOCS1[0] (W1C)
Kojto	90:cb3d968589d8	1642	*
Kojto	90:cb3d968589d8	1643	* This bit indicates when a loss of clock has occurred. This bit is cleared by
Kojto	90:cb3d968589d8	1644	* writing a logic 1 to it when set.
Kojto	90:cb3d968589d8	1645	*
Kojto	90:cb3d968589d8	1646	* Values:
Kojto	90:cb3d968589d8	1647	* - 0 - Loss of RTC has not occur.
Kojto	90:cb3d968589d8	1648	* - 1 - Loss of RTC has occur
Kojto	90:cb3d968589d8	1649	*/
Kojto	90:cb3d968589d8	1650	/@{/
Kojto	90:cb3d968589d8	1651	#define BP_MCG_C8_LOCS1 (0U) /!< Bit position for MCG_C8_LOCS1. /
Kojto	90:cb3d968589d8	1652	#define BM_MCG_C8_LOCS1 (0x01U) /!< Bit mask for MCG_C8_LOCS1. /
Kojto	90:cb3d968589d8	1653	#define BS_MCG_C8_LOCS1 (1U) /!< Bit field size in bits for MCG_C8_LOCS1. /
Kojto	90:cb3d968589d8	1654
Kojto	90:cb3d968589d8	1655	/! @brief Read current value of the MCG_C8_LOCS1 field. /
Kojto	90:cb3d968589d8	1656	#define BR_MCG_C8_LOCS1(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCS1))
Kojto	90:cb3d968589d8	1657
Kojto	90:cb3d968589d8	1658	/! @brief Format value for bitfield MCG_C8_LOCS1. /
Kojto	90:cb3d968589d8	1659	#define BF_MCG_C8_LOCS1(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOCS1) & BM_MCG_C8_LOCS1)
Kojto	90:cb3d968589d8	1660
Kojto	90:cb3d968589d8	1661	/! @brief Set the LOCS1 field to a new value. /
Kojto	90:cb3d968589d8	1662	#define BW_MCG_C8_LOCS1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCS1) = (v))
Kojto	90:cb3d968589d8	1663	/@}/
Kojto	90:cb3d968589d8	1664
Kojto	90:cb3d968589d8	1665	/*!
Kojto	90:cb3d968589d8	1666	* @name Register MCG_C8, field CME1[5] (RW)
Kojto	90:cb3d968589d8	1667	*
Kojto	90:cb3d968589d8	1668	* Enables the loss of clock monitoring circuit for the output of the RTC
Kojto	90:cb3d968589d8	1669	* external reference clock. The LOCRE1 bit will determine whether an interrupt or a
Kojto	90:cb3d968589d8	1670	* reset request is generated following a loss of RTC clock indication. The CME1
Kojto	90:cb3d968589d8	1671	* bit should be set to a logic 1 when the MCG is in an operational mode that uses
Kojto	90:cb3d968589d8	1672	* the RTC as its external reference clock or if the RTC is operational. CME1 bit
Kojto	90:cb3d968589d8	1673	* must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
Kojto	90:cb3d968589d8	1674	* reset request may occur when in Stop mode. CME1 should also be set to a logic 0
Kojto	90:cb3d968589d8	1675	* before entering VLPR or VLPW power modes.
Kojto	90:cb3d968589d8	1676	*
Kojto	90:cb3d968589d8	1677	* Values:
Kojto	90:cb3d968589d8	1678	* - 0 - External clock monitor is disabled for RTC clock.
Kojto	90:cb3d968589d8	1679	* - 1 - External clock monitor is enabled for RTC clock.
Kojto	90:cb3d968589d8	1680	*/
Kojto	90:cb3d968589d8	1681	/@{/
Kojto	90:cb3d968589d8	1682	#define BP_MCG_C8_CME1 (5U) /!< Bit position for MCG_C8_CME1. /
Kojto	90:cb3d968589d8	1683	#define BM_MCG_C8_CME1 (0x20U) /!< Bit mask for MCG_C8_CME1. /
Kojto	90:cb3d968589d8	1684	#define BS_MCG_C8_CME1 (1U) /!< Bit field size in bits for MCG_C8_CME1. /
Kojto	90:cb3d968589d8	1685
Kojto	90:cb3d968589d8	1686	/! @brief Read current value of the MCG_C8_CME1 field. /
Kojto	90:cb3d968589d8	1687	#define BR_MCG_C8_CME1(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1))
Kojto	90:cb3d968589d8	1688
Kojto	90:cb3d968589d8	1689	/! @brief Format value for bitfield MCG_C8_CME1. /
Kojto	90:cb3d968589d8	1690	#define BF_MCG_C8_CME1(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_CME1) & BM_MCG_C8_CME1)
Kojto	90:cb3d968589d8	1691
Kojto	90:cb3d968589d8	1692	/! @brief Set the CME1 field to a new value. /
Kojto	90:cb3d968589d8	1693	#define BW_MCG_C8_CME1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1) = (v))
Kojto	90:cb3d968589d8	1694	/@}/
Kojto	90:cb3d968589d8	1695
Kojto	90:cb3d968589d8	1696	/*!
Kojto	90:cb3d968589d8	1697	* @name Register MCG_C8, field LOLRE[6] (RW)
Kojto	90:cb3d968589d8	1698	*
Kojto	90:cb3d968589d8	1699	* Determines if an interrupt or a reset request is made following a PLL loss of
Kojto	90:cb3d968589d8	1700	* lock.
Kojto	90:cb3d968589d8	1701	*
Kojto	90:cb3d968589d8	1702	* Values:
Kojto	90:cb3d968589d8	1703	* - 0 - Interrupt request is generated on a PLL loss of lock indication. The
Kojto	90:cb3d968589d8	1704	* PLL loss of lock interrupt enable bit must also be set to generate the
Kojto	90:cb3d968589d8	1705	* interrupt request.
Kojto	90:cb3d968589d8	1706	* - 1 - Generate a reset request on a PLL loss of lock indication.
Kojto	90:cb3d968589d8	1707	*/
Kojto	90:cb3d968589d8	1708	/@{/
Kojto	90:cb3d968589d8	1709	#define BP_MCG_C8_LOLRE (6U) /!< Bit position for MCG_C8_LOLRE. /
Kojto	90:cb3d968589d8	1710	#define BM_MCG_C8_LOLRE (0x40U) /!< Bit mask for MCG_C8_LOLRE. /
Kojto	90:cb3d968589d8	1711	#define BS_MCG_C8_LOLRE (1U) /!< Bit field size in bits for MCG_C8_LOLRE. /
Kojto	90:cb3d968589d8	1712
Kojto	90:cb3d968589d8	1713	/! @brief Read current value of the MCG_C8_LOLRE field. /
Kojto	90:cb3d968589d8	1714	#define BR_MCG_C8_LOLRE(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE))
Kojto	90:cb3d968589d8	1715
Kojto	90:cb3d968589d8	1716	/! @brief Format value for bitfield MCG_C8_LOLRE. /
Kojto	90:cb3d968589d8	1717	#define BF_MCG_C8_LOLRE(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOLRE) & BM_MCG_C8_LOLRE)
Kojto	90:cb3d968589d8	1718
Kojto	90:cb3d968589d8	1719	/! @brief Set the LOLRE field to a new value. /
Kojto	90:cb3d968589d8	1720	#define BW_MCG_C8_LOLRE(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE) = (v))
Kojto	90:cb3d968589d8	1721	/@}/
Kojto	90:cb3d968589d8	1722
Kojto	90:cb3d968589d8	1723	/*!
Kojto	90:cb3d968589d8	1724	* @name Register MCG_C8, field LOCRE1[7] (RW)
Kojto	90:cb3d968589d8	1725	*
Kojto	90:cb3d968589d8	1726	* Determines if a interrupt or a reset request is made following a loss of RTC
Kojto	90:cb3d968589d8	1727	* external reference clock. The LOCRE1 only has an affect when CME1 is set.
Kojto	90:cb3d968589d8	1728	*
Kojto	90:cb3d968589d8	1729	* Values:
Kojto	90:cb3d968589d8	1730	* - 0 - Interrupt request is generated on a loss of RTC external reference
Kojto	90:cb3d968589d8	1731	* clock.
Kojto	90:cb3d968589d8	1732	* - 1 - Generate a reset request on a loss of RTC external reference clock
Kojto	90:cb3d968589d8	1733	*/
Kojto	90:cb3d968589d8	1734	/@{/
Kojto	90:cb3d968589d8	1735	#define BP_MCG_C8_LOCRE1 (7U) /!< Bit position for MCG_C8_LOCRE1. /
Kojto	90:cb3d968589d8	1736	#define BM_MCG_C8_LOCRE1 (0x80U) /!< Bit mask for MCG_C8_LOCRE1. /
Kojto	90:cb3d968589d8	1737	#define BS_MCG_C8_LOCRE1 (1U) /!< Bit field size in bits for MCG_C8_LOCRE1. /
Kojto	90:cb3d968589d8	1738
Kojto	90:cb3d968589d8	1739	/! @brief Read current value of the MCG_C8_LOCRE1 field. /
Kojto	90:cb3d968589d8	1740	#define BR_MCG_C8_LOCRE1(x) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCRE1))
Kojto	90:cb3d968589d8	1741
Kojto	90:cb3d968589d8	1742	/! @brief Format value for bitfield MCG_C8_LOCRE1. /
Kojto	90:cb3d968589d8	1743	#define BF_MCG_C8_LOCRE1(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOCRE1) & BM_MCG_C8_LOCRE1)
Kojto	90:cb3d968589d8	1744
Kojto	90:cb3d968589d8	1745	/! @brief Set the LOCRE1 field to a new value. /
Kojto	90:cb3d968589d8	1746	#define BW_MCG_C8_LOCRE1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCRE1) = (v))
Kojto	90:cb3d968589d8	1747	/@}/
Kojto	90:cb3d968589d8	1748
Kojto	90:cb3d968589d8	1749	/*******************************************************************************
Kojto	90:cb3d968589d8	1750	* hw_mcg_t - module struct
Kojto	90:cb3d968589d8	1751	******************************************************************************/
Kojto	90:cb3d968589d8	1752	/*!
Kojto	90:cb3d968589d8	1753	* @brief All MCG module registers.
Kojto	90:cb3d968589d8	1754	*/
Kojto	90:cb3d968589d8	1755	#pragma pack(1)
Kojto	90:cb3d968589d8	1756	typedef struct _hw_mcg
Kojto	90:cb3d968589d8	1757	{
Kojto	90:cb3d968589d8	1758	__IO hw_mcg_c1_t C1; /!< [0x0] MCG Control 1 Register /
Kojto	90:cb3d968589d8	1759	__IO hw_mcg_c2_t C2; /!< [0x1] MCG Control 2 Register /
Kojto	90:cb3d968589d8	1760	__IO hw_mcg_c3_t C3; /!< [0x2] MCG Control 3 Register /
Kojto	90:cb3d968589d8	1761	__IO hw_mcg_c4_t C4; /!< [0x3] MCG Control 4 Register /
Kojto	90:cb3d968589d8	1762	__IO hw_mcg_c5_t C5; /!< [0x4] MCG Control 5 Register /
Kojto	90:cb3d968589d8	1763	__IO hw_mcg_c6_t C6; /!< [0x5] MCG Control 6 Register /
Kojto	90:cb3d968589d8	1764	__IO hw_mcg_s_t S; /!< [0x6] MCG Status Register /
Kojto	90:cb3d968589d8	1765	uint8_t _reserved0[1];
Kojto	90:cb3d968589d8	1766	__IO hw_mcg_sc_t SC; /!< [0x8] MCG Status and Control Register /
Kojto	90:cb3d968589d8	1767	uint8_t _reserved1[1];
Kojto	90:cb3d968589d8	1768	__IO hw_mcg_atcvh_t ATCVH; /!< [0xA] MCG Auto Trim Compare Value High Register /
Kojto	90:cb3d968589d8	1769	__IO hw_mcg_atcvl_t ATCVL; /!< [0xB] MCG Auto Trim Compare Value Low Register /
Kojto	90:cb3d968589d8	1770	__IO hw_mcg_c7_t C7; /!< [0xC] MCG Control 7 Register /
Kojto	90:cb3d968589d8	1771	__IO hw_mcg_c8_t C8; /!< [0xD] MCG Control 8 Register /
Kojto	90:cb3d968589d8	1772	} hw_mcg_t;
Kojto	90:cb3d968589d8	1773	#pragma pack()
Kojto	90:cb3d968589d8	1774
Kojto	90:cb3d968589d8	1775	/! @brief Macro to access all MCG registers. /
Kojto	90:cb3d968589d8	1776	/! @param x MCG module instance base address. /
Kojto	90:cb3d968589d8	1777	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto	90:cb3d968589d8	1778	* use the '&' operator, like <code>&HW_MCG(MCG_BASE)</code>. */
Kojto	90:cb3d968589d8	1779	#define HW_MCG(x) ((hw_mcg_t )(x))
Kojto	90:cb3d968589d8	1780
Kojto	90:cb3d968589d8	1781	#endif /* __HW_MCG_REGISTERS_H__ */
Kojto	90:cb3d968589d8	1782	/* EOF */