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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_enet.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:: Kojto
Date:: Wed Aug 05 13:16:35 2015 +0100
Revision:: 104:b9ad9a133dc7
Parent:: 90:cb3d968589d8

Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/*
Kojto	90:cb3d968589d8	2	** ###################################################################
Kojto	90:cb3d968589d8	3	** Compilers: Keil ARM C/C++ Compiler
Kojto	90:cb3d968589d8	4	** Freescale C/C++ for Embedded ARM
Kojto	90:cb3d968589d8	5	** GNU C Compiler
Kojto	90:cb3d968589d8	6	** IAR ANSI C/C++ Compiler for ARM
Kojto	90:cb3d968589d8	7	**
Kojto	90:cb3d968589d8	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto	90:cb3d968589d8	9	** Version: rev. 2.5, 2014-02-10
Kojto	90:cb3d968589d8	10	** Build: b140604
Kojto	90:cb3d968589d8	11	**
Kojto	90:cb3d968589d8	12	** Abstract:
Kojto	90:cb3d968589d8	13	** Extension to the CMSIS register access layer header.
Kojto	90:cb3d968589d8	14	**
Kojto	90:cb3d968589d8	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto	90:cb3d968589d8	16	** All rights reserved.
Kojto	90:cb3d968589d8	17	**
Kojto	90:cb3d968589d8	18	** Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	19	** are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	20	**
Kojto	90:cb3d968589d8	21	** o Redistributions of source code must retain the above copyright notice, this list
Kojto	90:cb3d968589d8	22	** of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	**
Kojto	90:cb3d968589d8	24	** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto	90:cb3d968589d8	25	** list of conditions and the following disclaimer in the documentation and/or
Kojto	90:cb3d968589d8	26	** other materials provided with the distribution.
Kojto	90:cb3d968589d8	27	**
Kojto	90:cb3d968589d8	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto	90:cb3d968589d8	29	** contributors may be used to endorse or promote products derived from this
Kojto	90:cb3d968589d8	30	** software without specific prior written permission.
Kojto	90:cb3d968589d8	31	**
Kojto	90:cb3d968589d8	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	90:cb3d968589d8	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	90:cb3d968589d8	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	90:cb3d968589d8	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	90:cb3d968589d8	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	90:cb3d968589d8	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	90:cb3d968589d8	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	90:cb3d968589d8	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	90:cb3d968589d8	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	42	**
Kojto	90:cb3d968589d8	43	** http: www.freescale.com
Kojto	90:cb3d968589d8	44	** mail: support@freescale.com
Kojto	90:cb3d968589d8	45	**
Kojto	90:cb3d968589d8	46	** Revisions:
Kojto	90:cb3d968589d8	47	** - rev. 1.0 (2013-08-12)
Kojto	90:cb3d968589d8	48	** Initial version.
Kojto	90:cb3d968589d8	49	** - rev. 2.0 (2013-10-29)
Kojto	90:cb3d968589d8	50	** Register accessor macros added to the memory map.
Kojto	90:cb3d968589d8	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto	90:cb3d968589d8	52	** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto	90:cb3d968589d8	53	** System initialization updated.
Kojto	90:cb3d968589d8	54	** MCG - registers updated.
Kojto	90:cb3d968589d8	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto	90:cb3d968589d8	56	** - rev. 2.1 (2013-10-30)
Kojto	90:cb3d968589d8	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto	90:cb3d968589d8	58	** - rev. 2.2 (2013-12-09)
Kojto	90:cb3d968589d8	59	** DMA - EARS register removed.
Kojto	90:cb3d968589d8	60	** AIPS0, AIPS1 - MPRA register updated.
Kojto	90:cb3d968589d8	61	** - rev. 2.3 (2014-01-24)
Kojto	90:cb3d968589d8	62	** Update according to reference manual rev. 2
Kojto	90:cb3d968589d8	63	** ENET, MCG, MCM, SIM, USB - registers updated
Kojto	90:cb3d968589d8	64	** - rev. 2.4 (2014-02-10)
Kojto	90:cb3d968589d8	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	67	** - rev. 2.5 (2014-02-10)
Kojto	90:cb3d968589d8	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto	90:cb3d968589d8	71	**
Kojto	90:cb3d968589d8	72	** ###################################################################
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/*
Kojto	90:cb3d968589d8	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto	90:cb3d968589d8	77	*
Kojto	90:cb3d968589d8	78	* This file was generated automatically and any changes may be lost.
Kojto	90:cb3d968589d8	79	*/
Kojto	90:cb3d968589d8	80	#ifndef __HW_ENET_REGISTERS_H__
Kojto	90:cb3d968589d8	81	#define __HW_ENET_REGISTERS_H__
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	#include "MK64F12.h"
Kojto	90:cb3d968589d8	84	#include "fsl_bitaccess.h"
Kojto	90:cb3d968589d8	85
Kojto	90:cb3d968589d8	86	/*
Kojto	90:cb3d968589d8	87	* MK64F12 ENET
Kojto	90:cb3d968589d8	88	*
Kojto	90:cb3d968589d8	89	* Ethernet MAC-NET Core
Kojto	90:cb3d968589d8	90	*
Kojto	90:cb3d968589d8	91	* Registers defined in this header file:
Kojto	90:cb3d968589d8	92	* - HW_ENET_EIR - Interrupt Event Register
Kojto	90:cb3d968589d8	93	* - HW_ENET_EIMR - Interrupt Mask Register
Kojto	90:cb3d968589d8	94	* - HW_ENET_RDAR - Receive Descriptor Active Register
Kojto	90:cb3d968589d8	95	* - HW_ENET_TDAR - Transmit Descriptor Active Register
Kojto	90:cb3d968589d8	96	* - HW_ENET_ECR - Ethernet Control Register
Kojto	90:cb3d968589d8	97	* - HW_ENET_MMFR - MII Management Frame Register
Kojto	90:cb3d968589d8	98	* - HW_ENET_MSCR - MII Speed Control Register
Kojto	90:cb3d968589d8	99	* - HW_ENET_MIBC - MIB Control Register
Kojto	90:cb3d968589d8	100	* - HW_ENET_RCR - Receive Control Register
Kojto	90:cb3d968589d8	101	* - HW_ENET_TCR - Transmit Control Register
Kojto	90:cb3d968589d8	102	* - HW_ENET_PALR - Physical Address Lower Register
Kojto	90:cb3d968589d8	103	* - HW_ENET_PAUR - Physical Address Upper Register
Kojto	90:cb3d968589d8	104	* - HW_ENET_OPD - Opcode/Pause Duration Register
Kojto	90:cb3d968589d8	105	* - HW_ENET_IAUR - Descriptor Individual Upper Address Register
Kojto	90:cb3d968589d8	106	* - HW_ENET_IALR - Descriptor Individual Lower Address Register
Kojto	90:cb3d968589d8	107	* - HW_ENET_GAUR - Descriptor Group Upper Address Register
Kojto	90:cb3d968589d8	108	* - HW_ENET_GALR - Descriptor Group Lower Address Register
Kojto	90:cb3d968589d8	109	* - HW_ENET_TFWR - Transmit FIFO Watermark Register
Kojto	90:cb3d968589d8	110	* - HW_ENET_RDSR - Receive Descriptor Ring Start Register
Kojto	90:cb3d968589d8	111	* - HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
Kojto	90:cb3d968589d8	112	* - HW_ENET_MRBR - Maximum Receive Buffer Size Register
Kojto	90:cb3d968589d8	113	* - HW_ENET_RSFL - Receive FIFO Section Full Threshold
Kojto	90:cb3d968589d8	114	* - HW_ENET_RSEM - Receive FIFO Section Empty Threshold
Kojto	90:cb3d968589d8	115	* - HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
Kojto	90:cb3d968589d8	116	* - HW_ENET_RAFL - Receive FIFO Almost Full Threshold
Kojto	90:cb3d968589d8	117	* - HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
Kojto	90:cb3d968589d8	118	* - HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
Kojto	90:cb3d968589d8	119	* - HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
Kojto	90:cb3d968589d8	120	* - HW_ENET_TIPG - Transmit Inter-Packet Gap
Kojto	90:cb3d968589d8	121	* - HW_ENET_FTRL - Frame Truncation Length
Kojto	90:cb3d968589d8	122	* - HW_ENET_TACC - Transmit Accelerator Function Configuration
Kojto	90:cb3d968589d8	123	* - HW_ENET_RACC - Receive Accelerator Function Configuration
Kojto	90:cb3d968589d8	124	* - HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
Kojto	90:cb3d968589d8	125	* - HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
Kojto	90:cb3d968589d8	126	* - HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
Kojto	90:cb3d968589d8	127	* - HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
Kojto	90:cb3d968589d8	128	* - HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
Kojto	90:cb3d968589d8	129	* - HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
Kojto	90:cb3d968589d8	130	* - HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
Kojto	90:cb3d968589d8	131	* - HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
Kojto	90:cb3d968589d8	132	* - HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
Kojto	90:cb3d968589d8	133	* - HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	134	* - HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
Kojto	90:cb3d968589d8	135	* - HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
Kojto	90:cb3d968589d8	136	* - HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
Kojto	90:cb3d968589d8	137	* - HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
Kojto	90:cb3d968589d8	138	* - HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
Kojto	90:cb3d968589d8	139	* - HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
Kojto	90:cb3d968589d8	140	* - HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
Kojto	90:cb3d968589d8	141	* - HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
Kojto	90:cb3d968589d8	142	* - HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
Kojto	90:cb3d968589d8	143	* - HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
Kojto	90:cb3d968589d8	144	* - HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
Kojto	90:cb3d968589d8	145	* - HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
Kojto	90:cb3d968589d8	146	* - HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
Kojto	90:cb3d968589d8	147	* - HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
Kojto	90:cb3d968589d8	148	* - HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
Kojto	90:cb3d968589d8	149	* - HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
Kojto	90:cb3d968589d8	150	* - HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
Kojto	90:cb3d968589d8	151	* - HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
Kojto	90:cb3d968589d8	152	* - HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
Kojto	90:cb3d968589d8	153	* - HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
Kojto	90:cb3d968589d8	154	* - HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
Kojto	90:cb3d968589d8	155	* - HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
Kojto	90:cb3d968589d8	156	* - HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
Kojto	90:cb3d968589d8	157	* - HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
Kojto	90:cb3d968589d8	158	* - HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
Kojto	90:cb3d968589d8	159	* - HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	160	* - HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	161	* - HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	162	* - HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	163	* - HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	164	* - HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	165	* - HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
Kojto	90:cb3d968589d8	166	* - HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
Kojto	90:cb3d968589d8	167	* - HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
Kojto	90:cb3d968589d8	168	* - HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
Kojto	90:cb3d968589d8	169	* - HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
Kojto	90:cb3d968589d8	170	* - HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
Kojto	90:cb3d968589d8	171	* - HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
Kojto	90:cb3d968589d8	172	* - HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
Kojto	90:cb3d968589d8	173	* - HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
Kojto	90:cb3d968589d8	174	* - HW_ENET_ATCR - Adjustable Timer Control Register
Kojto	90:cb3d968589d8	175	* - HW_ENET_ATVR - Timer Value Register
Kojto	90:cb3d968589d8	176	* - HW_ENET_ATOFF - Timer Offset Register
Kojto	90:cb3d968589d8	177	* - HW_ENET_ATPER - Timer Period Register
Kojto	90:cb3d968589d8	178	* - HW_ENET_ATCOR - Timer Correction Register
Kojto	90:cb3d968589d8	179	* - HW_ENET_ATINC - Time-Stamping Clock Period Register
Kojto	90:cb3d968589d8	180	* - HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
Kojto	90:cb3d968589d8	181	* - HW_ENET_TGSR - Timer Global Status Register
Kojto	90:cb3d968589d8	182	* - HW_ENET_TCSRn - Timer Control Status Register
Kojto	90:cb3d968589d8	183	* - HW_ENET_TCCRn - Timer Compare Capture Register
Kojto	90:cb3d968589d8	184	*
Kojto	90:cb3d968589d8	185	* - hw_enet_t - Struct containing all module registers.
Kojto	90:cb3d968589d8	186	*/
Kojto	90:cb3d968589d8	187
Kojto	90:cb3d968589d8	188	#define HW_ENET_INSTANCE_COUNT (1U) /!< Number of instances of the ENET module. /
Kojto	90:cb3d968589d8	189
Kojto	90:cb3d968589d8	190	/*******************************************************************************
Kojto	90:cb3d968589d8	191	* HW_ENET_EIR - Interrupt Event Register
Kojto	90:cb3d968589d8	192	******************************************************************************/
Kojto	90:cb3d968589d8	193
Kojto	90:cb3d968589d8	194	/*!
Kojto	90:cb3d968589d8	195	* @brief HW_ENET_EIR - Interrupt Event Register (RW)
Kojto	90:cb3d968589d8	196	*
Kojto	90:cb3d968589d8	197	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	198	*
Kojto	90:cb3d968589d8	199	* When an event occurs that sets a bit in EIR, an interrupt occurs if the
Kojto	90:cb3d968589d8	200	* corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
Kojto	90:cb3d968589d8	201	* an EIR bit clears it; writing 0 has no effect. This register is cleared upon
Kojto	90:cb3d968589d8	202	* hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
Kojto	90:cb3d968589d8	203	* corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
Kojto	90:cb3d968589d8	204	* Legacy mode does not require these flags to be enabled.
Kojto	90:cb3d968589d8	205	*/
Kojto	90:cb3d968589d8	206	typedef union _hw_enet_eir
Kojto	90:cb3d968589d8	207	{
Kojto	90:cb3d968589d8	208	uint32_t U;
Kojto	90:cb3d968589d8	209	struct _hw_enet_eir_bitfields
Kojto	90:cb3d968589d8	210	{
Kojto	90:cb3d968589d8	211	uint32_t RESERVED0 : 15; /!< [14:0] /
Kojto	90:cb3d968589d8	212	uint32_t TS_TIMER : 1; /!< [15] Timestamp Timer /
Kojto	90:cb3d968589d8	213	uint32_t TS_AVAIL : 1; /!< [16] Transmit Timestamp Available /
Kojto	90:cb3d968589d8	214	uint32_t WAKEUP : 1; /!< [17] Node Wakeup Request Indication /
Kojto	90:cb3d968589d8	215	uint32_t PLR : 1; /!< [18] Payload Receive Error /
Kojto	90:cb3d968589d8	216	uint32_t UN : 1; /!< [19] Transmit FIFO Underrun /
Kojto	90:cb3d968589d8	217	uint32_t RL : 1; /!< [20] Collision Retry Limit /
Kojto	90:cb3d968589d8	218	uint32_t LC : 1; /!< [21] Late Collision /
Kojto	90:cb3d968589d8	219	uint32_t EBERR : 1; /!< [22] Ethernet Bus Error /
Kojto	90:cb3d968589d8	220	uint32_t MII : 1; /!< [23] MII Interrupt. /
Kojto	90:cb3d968589d8	221	uint32_t RXB : 1; /!< [24] Receive Buffer Interrupt /
Kojto	90:cb3d968589d8	222	uint32_t RXF : 1; /!< [25] Receive Frame Interrupt /
Kojto	90:cb3d968589d8	223	uint32_t TXB : 1; /!< [26] Transmit Buffer Interrupt /
Kojto	90:cb3d968589d8	224	uint32_t TXF : 1; /!< [27] Transmit Frame Interrupt /
Kojto	90:cb3d968589d8	225	uint32_t GRA : 1; /!< [28] Graceful Stop Complete /
Kojto	90:cb3d968589d8	226	uint32_t BABT : 1; /!< [29] Babbling Transmit Error /
Kojto	90:cb3d968589d8	227	uint32_t BABR : 1; /!< [30] Babbling Receive Error /
Kojto	90:cb3d968589d8	228	uint32_t RESERVED1 : 1; /!< [31] /
Kojto	90:cb3d968589d8	229	} B;
Kojto	90:cb3d968589d8	230	} hw_enet_eir_t;
Kojto	90:cb3d968589d8	231
Kojto	90:cb3d968589d8	232	/*!
Kojto	90:cb3d968589d8	233	* @name Constants and macros for entire ENET_EIR register
Kojto	90:cb3d968589d8	234	*/
Kojto	90:cb3d968589d8	235	/@{/
Kojto	90:cb3d968589d8	236	#define HW_ENET_EIR_ADDR(x) ((x) + 0x4U)
Kojto	90:cb3d968589d8	237
Kojto	90:cb3d968589d8	238	#define HW_ENET_EIR(x) ((__IO hw_enet_eir_t ) HW_ENET_EIR_ADDR(x))
Kojto	90:cb3d968589d8	239	#define HW_ENET_EIR_RD(x) (HW_ENET_EIR(x).U)
Kojto	90:cb3d968589d8	240	#define HW_ENET_EIR_WR(x, v) (HW_ENET_EIR(x).U = (v))
Kojto	90:cb3d968589d8	241	#define HW_ENET_EIR_SET(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	242	#define HW_ENET_EIR_CLR(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	243	#define HW_ENET_EIR_TOG(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	244	/@}/
Kojto	90:cb3d968589d8	245
Kojto	90:cb3d968589d8	246	/*
Kojto	90:cb3d968589d8	247	* Constants & macros for individual ENET_EIR bitfields
Kojto	90:cb3d968589d8	248	*/
Kojto	90:cb3d968589d8	249
Kojto	90:cb3d968589d8	250	/*!
Kojto	90:cb3d968589d8	251	* @name Register ENET_EIR, field TS_TIMER[15] (W1C)
Kojto	90:cb3d968589d8	252	*
Kojto	90:cb3d968589d8	253	* The adjustable timer reached the period event. A period event interrupt can
Kojto	90:cb3d968589d8	254	* be generated if ATCR[PEREN] is set and the timer wraps according to the
Kojto	90:cb3d968589d8	255	* periodic setting in the ATPER register. Set the timer period value before setting
Kojto	90:cb3d968589d8	256	* ATCR[PEREN].
Kojto	90:cb3d968589d8	257	*/
Kojto	90:cb3d968589d8	258	/@{/
Kojto	90:cb3d968589d8	259	#define BP_ENET_EIR_TS_TIMER (15U) /!< Bit position for ENET_EIR_TS_TIMER. /
Kojto	90:cb3d968589d8	260	#define BM_ENET_EIR_TS_TIMER (0x00008000U) /!< Bit mask for ENET_EIR_TS_TIMER. /
Kojto	90:cb3d968589d8	261	#define BS_ENET_EIR_TS_TIMER (1U) /!< Bit field size in bits for ENET_EIR_TS_TIMER. /
Kojto	90:cb3d968589d8	262
Kojto	90:cb3d968589d8	263	/! @brief Read current value of the ENET_EIR_TS_TIMER field. /
Kojto	90:cb3d968589d8	264	#define BR_ENET_EIR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER))
Kojto	90:cb3d968589d8	265
Kojto	90:cb3d968589d8	266	/! @brief Format value for bitfield ENET_EIR_TS_TIMER. /
Kojto	90:cb3d968589d8	267	#define BF_ENET_EIR_TS_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TS_TIMER) & BM_ENET_EIR_TS_TIMER)
Kojto	90:cb3d968589d8	268
Kojto	90:cb3d968589d8	269	/! @brief Set the TS_TIMER field to a new value. /
Kojto	90:cb3d968589d8	270	#define BW_ENET_EIR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER) = (v))
Kojto	90:cb3d968589d8	271	/@}/
Kojto	90:cb3d968589d8	272
Kojto	90:cb3d968589d8	273	/*!
Kojto	90:cb3d968589d8	274	* @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
Kojto	90:cb3d968589d8	275	*
Kojto	90:cb3d968589d8	276	* Indicates that the timestamp of the last transmitted timing frame is
Kojto	90:cb3d968589d8	277	* available in the ATSTMP register.
Kojto	90:cb3d968589d8	278	*/
Kojto	90:cb3d968589d8	279	/@{/
Kojto	90:cb3d968589d8	280	#define BP_ENET_EIR_TS_AVAIL (16U) /!< Bit position for ENET_EIR_TS_AVAIL. /
Kojto	90:cb3d968589d8	281	#define BM_ENET_EIR_TS_AVAIL (0x00010000U) /!< Bit mask for ENET_EIR_TS_AVAIL. /
Kojto	90:cb3d968589d8	282	#define BS_ENET_EIR_TS_AVAIL (1U) /!< Bit field size in bits for ENET_EIR_TS_AVAIL. /
Kojto	90:cb3d968589d8	283
Kojto	90:cb3d968589d8	284	/! @brief Read current value of the ENET_EIR_TS_AVAIL field. /
Kojto	90:cb3d968589d8	285	#define BR_ENET_EIR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL))
Kojto	90:cb3d968589d8	286
Kojto	90:cb3d968589d8	287	/! @brief Format value for bitfield ENET_EIR_TS_AVAIL. /
Kojto	90:cb3d968589d8	288	#define BF_ENET_EIR_TS_AVAIL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TS_AVAIL) & BM_ENET_EIR_TS_AVAIL)
Kojto	90:cb3d968589d8	289
Kojto	90:cb3d968589d8	290	/! @brief Set the TS_AVAIL field to a new value. /
Kojto	90:cb3d968589d8	291	#define BW_ENET_EIR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL) = (v))
Kojto	90:cb3d968589d8	292	/@}/
Kojto	90:cb3d968589d8	293
Kojto	90:cb3d968589d8	294	/*!
Kojto	90:cb3d968589d8	295	* @name Register ENET_EIR, field WAKEUP[17] (W1C)
Kojto	90:cb3d968589d8	296	*
Kojto	90:cb3d968589d8	297	* Read-only status bit to indicate that a magic packet has been detected. Will
Kojto	90:cb3d968589d8	298	* act only if ECR[MAGICEN] is set.
Kojto	90:cb3d968589d8	299	*/
Kojto	90:cb3d968589d8	300	/@{/
Kojto	90:cb3d968589d8	301	#define BP_ENET_EIR_WAKEUP (17U) /!< Bit position for ENET_EIR_WAKEUP. /
Kojto	90:cb3d968589d8	302	#define BM_ENET_EIR_WAKEUP (0x00020000U) /!< Bit mask for ENET_EIR_WAKEUP. /
Kojto	90:cb3d968589d8	303	#define BS_ENET_EIR_WAKEUP (1U) /!< Bit field size in bits for ENET_EIR_WAKEUP. /
Kojto	90:cb3d968589d8	304
Kojto	90:cb3d968589d8	305	/! @brief Read current value of the ENET_EIR_WAKEUP field. /
Kojto	90:cb3d968589d8	306	#define BR_ENET_EIR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP))
Kojto	90:cb3d968589d8	307
Kojto	90:cb3d968589d8	308	/! @brief Format value for bitfield ENET_EIR_WAKEUP. /
Kojto	90:cb3d968589d8	309	#define BF_ENET_EIR_WAKEUP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_WAKEUP) & BM_ENET_EIR_WAKEUP)
Kojto	90:cb3d968589d8	310
Kojto	90:cb3d968589d8	311	/! @brief Set the WAKEUP field to a new value. /
Kojto	90:cb3d968589d8	312	#define BW_ENET_EIR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP) = (v))
Kojto	90:cb3d968589d8	313	/@}/
Kojto	90:cb3d968589d8	314
Kojto	90:cb3d968589d8	315	/*!
Kojto	90:cb3d968589d8	316	* @name Register ENET_EIR, field PLR[18] (W1C)
Kojto	90:cb3d968589d8	317	*
Kojto	90:cb3d968589d8	318	* Indicates a frame was received with a payload length error. See Frame
Kojto	90:cb3d968589d8	319	* Length/Type Verification: Payload Length Check for more information.
Kojto	90:cb3d968589d8	320	*/
Kojto	90:cb3d968589d8	321	/@{/
Kojto	90:cb3d968589d8	322	#define BP_ENET_EIR_PLR (18U) /!< Bit position for ENET_EIR_PLR. /
Kojto	90:cb3d968589d8	323	#define BM_ENET_EIR_PLR (0x00040000U) /!< Bit mask for ENET_EIR_PLR. /
Kojto	90:cb3d968589d8	324	#define BS_ENET_EIR_PLR (1U) /!< Bit field size in bits for ENET_EIR_PLR. /
Kojto	90:cb3d968589d8	325
Kojto	90:cb3d968589d8	326	/! @brief Read current value of the ENET_EIR_PLR field. /
Kojto	90:cb3d968589d8	327	#define BR_ENET_EIR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR))
Kojto	90:cb3d968589d8	328
Kojto	90:cb3d968589d8	329	/! @brief Format value for bitfield ENET_EIR_PLR. /
Kojto	90:cb3d968589d8	330	#define BF_ENET_EIR_PLR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_PLR) & BM_ENET_EIR_PLR)
Kojto	90:cb3d968589d8	331
Kojto	90:cb3d968589d8	332	/! @brief Set the PLR field to a new value. /
Kojto	90:cb3d968589d8	333	#define BW_ENET_EIR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR) = (v))
Kojto	90:cb3d968589d8	334	/@}/
Kojto	90:cb3d968589d8	335
Kojto	90:cb3d968589d8	336	/*!
Kojto	90:cb3d968589d8	337	* @name Register ENET_EIR, field UN[19] (W1C)
Kojto	90:cb3d968589d8	338	*
Kojto	90:cb3d968589d8	339	* Indicates the transmit FIFO became empty before the complete frame was
Kojto	90:cb3d968589d8	340	* transmitted. A bad CRC is appended to the frame fragment and the remainder of the
Kojto	90:cb3d968589d8	341	* frame is discarded.
Kojto	90:cb3d968589d8	342	*/
Kojto	90:cb3d968589d8	343	/@{/
Kojto	90:cb3d968589d8	344	#define BP_ENET_EIR_UN (19U) /!< Bit position for ENET_EIR_UN. /
Kojto	90:cb3d968589d8	345	#define BM_ENET_EIR_UN (0x00080000U) /!< Bit mask for ENET_EIR_UN. /
Kojto	90:cb3d968589d8	346	#define BS_ENET_EIR_UN (1U) /!< Bit field size in bits for ENET_EIR_UN. /
Kojto	90:cb3d968589d8	347
Kojto	90:cb3d968589d8	348	/! @brief Read current value of the ENET_EIR_UN field. /
Kojto	90:cb3d968589d8	349	#define BR_ENET_EIR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN))
Kojto	90:cb3d968589d8	350
Kojto	90:cb3d968589d8	351	/! @brief Format value for bitfield ENET_EIR_UN. /
Kojto	90:cb3d968589d8	352	#define BF_ENET_EIR_UN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_UN) & BM_ENET_EIR_UN)
Kojto	90:cb3d968589d8	353
Kojto	90:cb3d968589d8	354	/! @brief Set the UN field to a new value. /
Kojto	90:cb3d968589d8	355	#define BW_ENET_EIR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN) = (v))
Kojto	90:cb3d968589d8	356	/@}/
Kojto	90:cb3d968589d8	357
Kojto	90:cb3d968589d8	358	/*!
Kojto	90:cb3d968589d8	359	* @name Register ENET_EIR, field RL[20] (W1C)
Kojto	90:cb3d968589d8	360	*
Kojto	90:cb3d968589d8	361	* Indicates a collision occurred on each of 16 successive attempts to transmit
Kojto	90:cb3d968589d8	362	* the frame. The frame is discarded without being transmitted and transmission
Kojto	90:cb3d968589d8	363	* of the next frame commences. This error can only occur in half-duplex mode.
Kojto	90:cb3d968589d8	364	*/
Kojto	90:cb3d968589d8	365	/@{/
Kojto	90:cb3d968589d8	366	#define BP_ENET_EIR_RL (20U) /!< Bit position for ENET_EIR_RL. /
Kojto	90:cb3d968589d8	367	#define BM_ENET_EIR_RL (0x00100000U) /!< Bit mask for ENET_EIR_RL. /
Kojto	90:cb3d968589d8	368	#define BS_ENET_EIR_RL (1U) /!< Bit field size in bits for ENET_EIR_RL. /
Kojto	90:cb3d968589d8	369
Kojto	90:cb3d968589d8	370	/! @brief Read current value of the ENET_EIR_RL field. /
Kojto	90:cb3d968589d8	371	#define BR_ENET_EIR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL))
Kojto	90:cb3d968589d8	372
Kojto	90:cb3d968589d8	373	/! @brief Format value for bitfield ENET_EIR_RL. /
Kojto	90:cb3d968589d8	374	#define BF_ENET_EIR_RL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RL) & BM_ENET_EIR_RL)
Kojto	90:cb3d968589d8	375
Kojto	90:cb3d968589d8	376	/! @brief Set the RL field to a new value. /
Kojto	90:cb3d968589d8	377	#define BW_ENET_EIR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL) = (v))
Kojto	90:cb3d968589d8	378	/@}/
Kojto	90:cb3d968589d8	379
Kojto	90:cb3d968589d8	380	/*!
Kojto	90:cb3d968589d8	381	* @name Register ENET_EIR, field LC[21] (W1C)
Kojto	90:cb3d968589d8	382	*
Kojto	90:cb3d968589d8	383	* Indicates a collision occurred beyond the collision window (slot time) in
Kojto	90:cb3d968589d8	384	* half-duplex mode. The frame truncates with a bad CRC and the remainder of the
Kojto	90:cb3d968589d8	385	* frame is discarded.
Kojto	90:cb3d968589d8	386	*/
Kojto	90:cb3d968589d8	387	/@{/
Kojto	90:cb3d968589d8	388	#define BP_ENET_EIR_LC (21U) /!< Bit position for ENET_EIR_LC. /
Kojto	90:cb3d968589d8	389	#define BM_ENET_EIR_LC (0x00200000U) /!< Bit mask for ENET_EIR_LC. /
Kojto	90:cb3d968589d8	390	#define BS_ENET_EIR_LC (1U) /!< Bit field size in bits for ENET_EIR_LC. /
Kojto	90:cb3d968589d8	391
Kojto	90:cb3d968589d8	392	/! @brief Read current value of the ENET_EIR_LC field. /
Kojto	90:cb3d968589d8	393	#define BR_ENET_EIR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC))
Kojto	90:cb3d968589d8	394
Kojto	90:cb3d968589d8	395	/! @brief Format value for bitfield ENET_EIR_LC. /
Kojto	90:cb3d968589d8	396	#define BF_ENET_EIR_LC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_LC) & BM_ENET_EIR_LC)
Kojto	90:cb3d968589d8	397
Kojto	90:cb3d968589d8	398	/! @brief Set the LC field to a new value. /
Kojto	90:cb3d968589d8	399	#define BW_ENET_EIR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC) = (v))
Kojto	90:cb3d968589d8	400	/@}/
Kojto	90:cb3d968589d8	401
Kojto	90:cb3d968589d8	402	/*!
Kojto	90:cb3d968589d8	403	* @name Register ENET_EIR, field EBERR[22] (W1C)
Kojto	90:cb3d968589d8	404	*
Kojto	90:cb3d968589d8	405	* Indicates a system bus error occurred when a uDMA transaction is underway.
Kojto	90:cb3d968589d8	406	* When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
Kojto	90:cb3d968589d8	407	* MAC. When this occurs, software must ensure proper actions, possibly resetting
Kojto	90:cb3d968589d8	408	* the system, to resume normal operation.
Kojto	90:cb3d968589d8	409	*/
Kojto	90:cb3d968589d8	410	/@{/
Kojto	90:cb3d968589d8	411	#define BP_ENET_EIR_EBERR (22U) /!< Bit position for ENET_EIR_EBERR. /
Kojto	90:cb3d968589d8	412	#define BM_ENET_EIR_EBERR (0x00400000U) /!< Bit mask for ENET_EIR_EBERR. /
Kojto	90:cb3d968589d8	413	#define BS_ENET_EIR_EBERR (1U) /!< Bit field size in bits for ENET_EIR_EBERR. /
Kojto	90:cb3d968589d8	414
Kojto	90:cb3d968589d8	415	/! @brief Read current value of the ENET_EIR_EBERR field. /
Kojto	90:cb3d968589d8	416	#define BR_ENET_EIR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR))
Kojto	90:cb3d968589d8	417
Kojto	90:cb3d968589d8	418	/! @brief Format value for bitfield ENET_EIR_EBERR. /
Kojto	90:cb3d968589d8	419	#define BF_ENET_EIR_EBERR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_EBERR) & BM_ENET_EIR_EBERR)
Kojto	90:cb3d968589d8	420
Kojto	90:cb3d968589d8	421	/! @brief Set the EBERR field to a new value. /
Kojto	90:cb3d968589d8	422	#define BW_ENET_EIR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR) = (v))
Kojto	90:cb3d968589d8	423	/@}/
Kojto	90:cb3d968589d8	424
Kojto	90:cb3d968589d8	425	/*!
Kojto	90:cb3d968589d8	426	* @name Register ENET_EIR, field MII[23] (W1C)
Kojto	90:cb3d968589d8	427	*
Kojto	90:cb3d968589d8	428	* Indicates that the MII has completed the data transfer requested.
Kojto	90:cb3d968589d8	429	*/
Kojto	90:cb3d968589d8	430	/@{/
Kojto	90:cb3d968589d8	431	#define BP_ENET_EIR_MII (23U) /!< Bit position for ENET_EIR_MII. /
Kojto	90:cb3d968589d8	432	#define BM_ENET_EIR_MII (0x00800000U) /!< Bit mask for ENET_EIR_MII. /
Kojto	90:cb3d968589d8	433	#define BS_ENET_EIR_MII (1U) /!< Bit field size in bits for ENET_EIR_MII. /
Kojto	90:cb3d968589d8	434
Kojto	90:cb3d968589d8	435	/! @brief Read current value of the ENET_EIR_MII field. /
Kojto	90:cb3d968589d8	436	#define BR_ENET_EIR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII))
Kojto	90:cb3d968589d8	437
Kojto	90:cb3d968589d8	438	/! @brief Format value for bitfield ENET_EIR_MII. /
Kojto	90:cb3d968589d8	439	#define BF_ENET_EIR_MII(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_MII) & BM_ENET_EIR_MII)
Kojto	90:cb3d968589d8	440
Kojto	90:cb3d968589d8	441	/! @brief Set the MII field to a new value. /
Kojto	90:cb3d968589d8	442	#define BW_ENET_EIR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII) = (v))
Kojto	90:cb3d968589d8	443	/@}/
Kojto	90:cb3d968589d8	444
Kojto	90:cb3d968589d8	445	/*!
Kojto	90:cb3d968589d8	446	* @name Register ENET_EIR, field RXB[24] (W1C)
Kojto	90:cb3d968589d8	447	*
Kojto	90:cb3d968589d8	448	* Indicates a receive buffer descriptor is not the last in the frame has been
Kojto	90:cb3d968589d8	449	* updated.
Kojto	90:cb3d968589d8	450	*/
Kojto	90:cb3d968589d8	451	/@{/
Kojto	90:cb3d968589d8	452	#define BP_ENET_EIR_RXB (24U) /!< Bit position for ENET_EIR_RXB. /
Kojto	90:cb3d968589d8	453	#define BM_ENET_EIR_RXB (0x01000000U) /!< Bit mask for ENET_EIR_RXB. /
Kojto	90:cb3d968589d8	454	#define BS_ENET_EIR_RXB (1U) /!< Bit field size in bits for ENET_EIR_RXB. /
Kojto	90:cb3d968589d8	455
Kojto	90:cb3d968589d8	456	/! @brief Read current value of the ENET_EIR_RXB field. /
Kojto	90:cb3d968589d8	457	#define BR_ENET_EIR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB))
Kojto	90:cb3d968589d8	458
Kojto	90:cb3d968589d8	459	/! @brief Format value for bitfield ENET_EIR_RXB. /
Kojto	90:cb3d968589d8	460	#define BF_ENET_EIR_RXB(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RXB) & BM_ENET_EIR_RXB)
Kojto	90:cb3d968589d8	461
Kojto	90:cb3d968589d8	462	/! @brief Set the RXB field to a new value. /
Kojto	90:cb3d968589d8	463	#define BW_ENET_EIR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB) = (v))
Kojto	90:cb3d968589d8	464	/@}/
Kojto	90:cb3d968589d8	465
Kojto	90:cb3d968589d8	466	/*!
Kojto	90:cb3d968589d8	467	* @name Register ENET_EIR, field RXF[25] (W1C)
Kojto	90:cb3d968589d8	468	*
Kojto	90:cb3d968589d8	469	* Indicates a frame has been received and the last corresponding buffer
Kojto	90:cb3d968589d8	470	* descriptor has been updated.
Kojto	90:cb3d968589d8	471	*/
Kojto	90:cb3d968589d8	472	/@{/
Kojto	90:cb3d968589d8	473	#define BP_ENET_EIR_RXF (25U) /!< Bit position for ENET_EIR_RXF. /
Kojto	90:cb3d968589d8	474	#define BM_ENET_EIR_RXF (0x02000000U) /!< Bit mask for ENET_EIR_RXF. /
Kojto	90:cb3d968589d8	475	#define BS_ENET_EIR_RXF (1U) /!< Bit field size in bits for ENET_EIR_RXF. /
Kojto	90:cb3d968589d8	476
Kojto	90:cb3d968589d8	477	/! @brief Read current value of the ENET_EIR_RXF field. /
Kojto	90:cb3d968589d8	478	#define BR_ENET_EIR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF))
Kojto	90:cb3d968589d8	479
Kojto	90:cb3d968589d8	480	/! @brief Format value for bitfield ENET_EIR_RXF. /
Kojto	90:cb3d968589d8	481	#define BF_ENET_EIR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RXF) & BM_ENET_EIR_RXF)
Kojto	90:cb3d968589d8	482
Kojto	90:cb3d968589d8	483	/! @brief Set the RXF field to a new value. /
Kojto	90:cb3d968589d8	484	#define BW_ENET_EIR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF) = (v))
Kojto	90:cb3d968589d8	485	/@}/
Kojto	90:cb3d968589d8	486
Kojto	90:cb3d968589d8	487	/*!
Kojto	90:cb3d968589d8	488	* @name Register ENET_EIR, field TXB[26] (W1C)
Kojto	90:cb3d968589d8	489	*
Kojto	90:cb3d968589d8	490	* Indicates a transmit buffer descriptor has been updated.
Kojto	90:cb3d968589d8	491	*/
Kojto	90:cb3d968589d8	492	/@{/
Kojto	90:cb3d968589d8	493	#define BP_ENET_EIR_TXB (26U) /!< Bit position for ENET_EIR_TXB. /
Kojto	90:cb3d968589d8	494	#define BM_ENET_EIR_TXB (0x04000000U) /!< Bit mask for ENET_EIR_TXB. /
Kojto	90:cb3d968589d8	495	#define BS_ENET_EIR_TXB (1U) /!< Bit field size in bits for ENET_EIR_TXB. /
Kojto	90:cb3d968589d8	496
Kojto	90:cb3d968589d8	497	/! @brief Read current value of the ENET_EIR_TXB field. /
Kojto	90:cb3d968589d8	498	#define BR_ENET_EIR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB))
Kojto	90:cb3d968589d8	499
Kojto	90:cb3d968589d8	500	/! @brief Format value for bitfield ENET_EIR_TXB. /
Kojto	90:cb3d968589d8	501	#define BF_ENET_EIR_TXB(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TXB) & BM_ENET_EIR_TXB)
Kojto	90:cb3d968589d8	502
Kojto	90:cb3d968589d8	503	/! @brief Set the TXB field to a new value. /
Kojto	90:cb3d968589d8	504	#define BW_ENET_EIR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB) = (v))
Kojto	90:cb3d968589d8	505	/@}/
Kojto	90:cb3d968589d8	506
Kojto	90:cb3d968589d8	507	/*!
Kojto	90:cb3d968589d8	508	* @name Register ENET_EIR, field TXF[27] (W1C)
Kojto	90:cb3d968589d8	509	*
Kojto	90:cb3d968589d8	510	* Indicates a frame has been transmitted and the last corresponding buffer
Kojto	90:cb3d968589d8	511	* descriptor has been updated.
Kojto	90:cb3d968589d8	512	*/
Kojto	90:cb3d968589d8	513	/@{/
Kojto	90:cb3d968589d8	514	#define BP_ENET_EIR_TXF (27U) /!< Bit position for ENET_EIR_TXF. /
Kojto	90:cb3d968589d8	515	#define BM_ENET_EIR_TXF (0x08000000U) /!< Bit mask for ENET_EIR_TXF. /
Kojto	90:cb3d968589d8	516	#define BS_ENET_EIR_TXF (1U) /!< Bit field size in bits for ENET_EIR_TXF. /
Kojto	90:cb3d968589d8	517
Kojto	90:cb3d968589d8	518	/! @brief Read current value of the ENET_EIR_TXF field. /
Kojto	90:cb3d968589d8	519	#define BR_ENET_EIR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF))
Kojto	90:cb3d968589d8	520
Kojto	90:cb3d968589d8	521	/! @brief Format value for bitfield ENET_EIR_TXF. /
Kojto	90:cb3d968589d8	522	#define BF_ENET_EIR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TXF) & BM_ENET_EIR_TXF)
Kojto	90:cb3d968589d8	523
Kojto	90:cb3d968589d8	524	/! @brief Set the TXF field to a new value. /
Kojto	90:cb3d968589d8	525	#define BW_ENET_EIR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF) = (v))
Kojto	90:cb3d968589d8	526	/@}/
Kojto	90:cb3d968589d8	527
Kojto	90:cb3d968589d8	528	/*!
Kojto	90:cb3d968589d8	529	* @name Register ENET_EIR, field GRA[28] (W1C)
Kojto	90:cb3d968589d8	530	*
Kojto	90:cb3d968589d8	531	* This interrupt is asserted after the transmitter is put into a pause state
Kojto	90:cb3d968589d8	532	* after completion of the frame currently being transmitted. See Graceful Transmit
Kojto	90:cb3d968589d8	533	* Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
Kojto	90:cb3d968589d8	534	* asserted only when the TX transitions into the stopped state. If this bit is
Kojto	90:cb3d968589d8	535	* cleared by writing 1 and the TX is still stopped, the bit is not set again.
Kojto	90:cb3d968589d8	536	*/
Kojto	90:cb3d968589d8	537	/@{/
Kojto	90:cb3d968589d8	538	#define BP_ENET_EIR_GRA (28U) /!< Bit position for ENET_EIR_GRA. /
Kojto	90:cb3d968589d8	539	#define BM_ENET_EIR_GRA (0x10000000U) /!< Bit mask for ENET_EIR_GRA. /
Kojto	90:cb3d968589d8	540	#define BS_ENET_EIR_GRA (1U) /!< Bit field size in bits for ENET_EIR_GRA. /
Kojto	90:cb3d968589d8	541
Kojto	90:cb3d968589d8	542	/! @brief Read current value of the ENET_EIR_GRA field. /
Kojto	90:cb3d968589d8	543	#define BR_ENET_EIR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA))
Kojto	90:cb3d968589d8	544
Kojto	90:cb3d968589d8	545	/! @brief Format value for bitfield ENET_EIR_GRA. /
Kojto	90:cb3d968589d8	546	#define BF_ENET_EIR_GRA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_GRA) & BM_ENET_EIR_GRA)
Kojto	90:cb3d968589d8	547
Kojto	90:cb3d968589d8	548	/! @brief Set the GRA field to a new value. /
Kojto	90:cb3d968589d8	549	#define BW_ENET_EIR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA) = (v))
Kojto	90:cb3d968589d8	550	/@}/
Kojto	90:cb3d968589d8	551
Kojto	90:cb3d968589d8	552	/*!
Kojto	90:cb3d968589d8	553	* @name Register ENET_EIR, field BABT[29] (W1C)
Kojto	90:cb3d968589d8	554	*
Kojto	90:cb3d968589d8	555	* Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
Kojto	90:cb3d968589d8	556	* this condition is caused when a frame that is too long is placed into the
Kojto	90:cb3d968589d8	557	* transmit data buffer(s). Truncation does not occur.
Kojto	90:cb3d968589d8	558	*/
Kojto	90:cb3d968589d8	559	/@{/
Kojto	90:cb3d968589d8	560	#define BP_ENET_EIR_BABT (29U) /!< Bit position for ENET_EIR_BABT. /
Kojto	90:cb3d968589d8	561	#define BM_ENET_EIR_BABT (0x20000000U) /!< Bit mask for ENET_EIR_BABT. /
Kojto	90:cb3d968589d8	562	#define BS_ENET_EIR_BABT (1U) /!< Bit field size in bits for ENET_EIR_BABT. /
Kojto	90:cb3d968589d8	563
Kojto	90:cb3d968589d8	564	/! @brief Read current value of the ENET_EIR_BABT field. /
Kojto	90:cb3d968589d8	565	#define BR_ENET_EIR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT))
Kojto	90:cb3d968589d8	566
Kojto	90:cb3d968589d8	567	/! @brief Format value for bitfield ENET_EIR_BABT. /
Kojto	90:cb3d968589d8	568	#define BF_ENET_EIR_BABT(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_BABT) & BM_ENET_EIR_BABT)
Kojto	90:cb3d968589d8	569
Kojto	90:cb3d968589d8	570	/! @brief Set the BABT field to a new value. /
Kojto	90:cb3d968589d8	571	#define BW_ENET_EIR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT) = (v))
Kojto	90:cb3d968589d8	572	/@}/
Kojto	90:cb3d968589d8	573
Kojto	90:cb3d968589d8	574	/*!
Kojto	90:cb3d968589d8	575	* @name Register ENET_EIR, field BABR[30] (W1C)
Kojto	90:cb3d968589d8	576	*
Kojto	90:cb3d968589d8	577	* Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
Kojto	90:cb3d968589d8	578	*/
Kojto	90:cb3d968589d8	579	/@{/
Kojto	90:cb3d968589d8	580	#define BP_ENET_EIR_BABR (30U) /!< Bit position for ENET_EIR_BABR. /
Kojto	90:cb3d968589d8	581	#define BM_ENET_EIR_BABR (0x40000000U) /!< Bit mask for ENET_EIR_BABR. /
Kojto	90:cb3d968589d8	582	#define BS_ENET_EIR_BABR (1U) /!< Bit field size in bits for ENET_EIR_BABR. /
Kojto	90:cb3d968589d8	583
Kojto	90:cb3d968589d8	584	/! @brief Read current value of the ENET_EIR_BABR field. /
Kojto	90:cb3d968589d8	585	#define BR_ENET_EIR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR))
Kojto	90:cb3d968589d8	586
Kojto	90:cb3d968589d8	587	/! @brief Format value for bitfield ENET_EIR_BABR. /
Kojto	90:cb3d968589d8	588	#define BF_ENET_EIR_BABR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_BABR) & BM_ENET_EIR_BABR)
Kojto	90:cb3d968589d8	589
Kojto	90:cb3d968589d8	590	/! @brief Set the BABR field to a new value. /
Kojto	90:cb3d968589d8	591	#define BW_ENET_EIR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR) = (v))
Kojto	90:cb3d968589d8	592	/@}/
Kojto	90:cb3d968589d8	593
Kojto	90:cb3d968589d8	594	/*******************************************************************************
Kojto	90:cb3d968589d8	595	* HW_ENET_EIMR - Interrupt Mask Register
Kojto	90:cb3d968589d8	596	******************************************************************************/
Kojto	90:cb3d968589d8	597
Kojto	90:cb3d968589d8	598	/*!
Kojto	90:cb3d968589d8	599	* @brief HW_ENET_EIMR - Interrupt Mask Register (RW)
Kojto	90:cb3d968589d8	600	*
Kojto	90:cb3d968589d8	601	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	602	*
Kojto	90:cb3d968589d8	603	* EIMR controls which interrupt events are allowed to generate actual
Kojto	90:cb3d968589d8	604	* interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
Kojto	90:cb3d968589d8	605	* and EIMR registers are set, an interrupt is generated. The interrupt signal
Kojto	90:cb3d968589d8	606	* remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
Kojto	90:cb3d968589d8	607	* 0 is written to the EIMR field.
Kojto	90:cb3d968589d8	608	*/
Kojto	90:cb3d968589d8	609	typedef union _hw_enet_eimr
Kojto	90:cb3d968589d8	610	{
Kojto	90:cb3d968589d8	611	uint32_t U;
Kojto	90:cb3d968589d8	612	struct _hw_enet_eimr_bitfields
Kojto	90:cb3d968589d8	613	{
Kojto	90:cb3d968589d8	614	uint32_t RESERVED0 : 15; /!< [14:0] /
Kojto	90:cb3d968589d8	615	uint32_t TS_TIMER : 1; /!< [15] TS_TIMER Interrupt Mask /
Kojto	90:cb3d968589d8	616	uint32_t TS_AVAIL : 1; /!< [16] TS_AVAIL Interrupt Mask /
Kojto	90:cb3d968589d8	617	uint32_t WAKEUP : 1; /!< [17] WAKEUP Interrupt Mask /
Kojto	90:cb3d968589d8	618	uint32_t PLR : 1; /!< [18] PLR Interrupt Mask /
Kojto	90:cb3d968589d8	619	uint32_t UN : 1; /!< [19] UN Interrupt Mask /
Kojto	90:cb3d968589d8	620	uint32_t RL : 1; /!< [20] RL Interrupt Mask /
Kojto	90:cb3d968589d8	621	uint32_t LC : 1; /!< [21] LC Interrupt Mask /
Kojto	90:cb3d968589d8	622	uint32_t EBERR : 1; /!< [22] EBERR Interrupt Mask /
Kojto	90:cb3d968589d8	623	uint32_t MII : 1; /!< [23] MII Interrupt Mask /
Kojto	90:cb3d968589d8	624	uint32_t RXB : 1; /!< [24] RXB Interrupt Mask /
Kojto	90:cb3d968589d8	625	uint32_t RXF : 1; /!< [25] RXF Interrupt Mask /
Kojto	90:cb3d968589d8	626	uint32_t TXB : 1; /!< [26] TXB Interrupt Mask /
Kojto	90:cb3d968589d8	627	uint32_t TXF : 1; /!< [27] TXF Interrupt Mask /
Kojto	90:cb3d968589d8	628	uint32_t GRA : 1; /!< [28] GRA Interrupt Mask /
Kojto	90:cb3d968589d8	629	uint32_t BABT : 1; /!< [29] BABT Interrupt Mask /
Kojto	90:cb3d968589d8	630	uint32_t BABR : 1; /!< [30] BABR Interrupt Mask /
Kojto	90:cb3d968589d8	631	uint32_t RESERVED1 : 1; /!< [31] /
Kojto	90:cb3d968589d8	632	} B;
Kojto	90:cb3d968589d8	633	} hw_enet_eimr_t;
Kojto	90:cb3d968589d8	634
Kojto	90:cb3d968589d8	635	/*!
Kojto	90:cb3d968589d8	636	* @name Constants and macros for entire ENET_EIMR register
Kojto	90:cb3d968589d8	637	*/
Kojto	90:cb3d968589d8	638	/@{/
Kojto	90:cb3d968589d8	639	#define HW_ENET_EIMR_ADDR(x) ((x) + 0x8U)
Kojto	90:cb3d968589d8	640
Kojto	90:cb3d968589d8	641	#define HW_ENET_EIMR(x) ((__IO hw_enet_eimr_t ) HW_ENET_EIMR_ADDR(x))
Kojto	90:cb3d968589d8	642	#define HW_ENET_EIMR_RD(x) (HW_ENET_EIMR(x).U)
Kojto	90:cb3d968589d8	643	#define HW_ENET_EIMR_WR(x, v) (HW_ENET_EIMR(x).U = (v))
Kojto	90:cb3d968589d8	644	#define HW_ENET_EIMR_SET(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	645	#define HW_ENET_EIMR_CLR(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	646	#define HW_ENET_EIMR_TOG(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	647	/@}/
Kojto	90:cb3d968589d8	648
Kojto	90:cb3d968589d8	649	/*
Kojto	90:cb3d968589d8	650	* Constants & macros for individual ENET_EIMR bitfields
Kojto	90:cb3d968589d8	651	*/
Kojto	90:cb3d968589d8	652
Kojto	90:cb3d968589d8	653	/*!
Kojto	90:cb3d968589d8	654	* @name Register ENET_EIMR, field TS_TIMER[15] (RW)
Kojto	90:cb3d968589d8	655	*
Kojto	90:cb3d968589d8	656	* Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
Kojto	90:cb3d968589d8	657	* an interrupt condition can generate an interrupt. At every module clock, the
Kojto	90:cb3d968589d8	658	* EIR samples the signal generated by the interrupting source. The corresponding
Kojto	90:cb3d968589d8	659	* EIR TS_TIMER field reflects the state of the interrupt signal even if the
Kojto	90:cb3d968589d8	660	* corresponding EIMR field is cleared.
Kojto	90:cb3d968589d8	661	*/
Kojto	90:cb3d968589d8	662	/@{/
Kojto	90:cb3d968589d8	663	#define BP_ENET_EIMR_TS_TIMER (15U) /!< Bit position for ENET_EIMR_TS_TIMER. /
Kojto	90:cb3d968589d8	664	#define BM_ENET_EIMR_TS_TIMER (0x00008000U) /!< Bit mask for ENET_EIMR_TS_TIMER. /
Kojto	90:cb3d968589d8	665	#define BS_ENET_EIMR_TS_TIMER (1U) /!< Bit field size in bits for ENET_EIMR_TS_TIMER. /
Kojto	90:cb3d968589d8	666
Kojto	90:cb3d968589d8	667	/! @brief Read current value of the ENET_EIMR_TS_TIMER field. /
Kojto	90:cb3d968589d8	668	#define BR_ENET_EIMR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER))
Kojto	90:cb3d968589d8	669
Kojto	90:cb3d968589d8	670	/! @brief Format value for bitfield ENET_EIMR_TS_TIMER. /
Kojto	90:cb3d968589d8	671	#define BF_ENET_EIMR_TS_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TS_TIMER) & BM_ENET_EIMR_TS_TIMER)
Kojto	90:cb3d968589d8	672
Kojto	90:cb3d968589d8	673	/! @brief Set the TS_TIMER field to a new value. /
Kojto	90:cb3d968589d8	674	#define BW_ENET_EIMR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER) = (v))
Kojto	90:cb3d968589d8	675	/@}/
Kojto	90:cb3d968589d8	676
Kojto	90:cb3d968589d8	677	/*!
Kojto	90:cb3d968589d8	678	* @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
Kojto	90:cb3d968589d8	679	*
Kojto	90:cb3d968589d8	680	* Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
Kojto	90:cb3d968589d8	681	* an interrupt condition can generate an interrupt. At every module clock, the
Kojto	90:cb3d968589d8	682	* EIR samples the signal generated by the interrupting source. The corresponding
Kojto	90:cb3d968589d8	683	* EIR TS_AVAIL field reflects the state of the interrupt signal even if the
Kojto	90:cb3d968589d8	684	* corresponding EIMR field is cleared.
Kojto	90:cb3d968589d8	685	*/
Kojto	90:cb3d968589d8	686	/@{/
Kojto	90:cb3d968589d8	687	#define BP_ENET_EIMR_TS_AVAIL (16U) /!< Bit position for ENET_EIMR_TS_AVAIL. /
Kojto	90:cb3d968589d8	688	#define BM_ENET_EIMR_TS_AVAIL (0x00010000U) /!< Bit mask for ENET_EIMR_TS_AVAIL. /
Kojto	90:cb3d968589d8	689	#define BS_ENET_EIMR_TS_AVAIL (1U) /!< Bit field size in bits for ENET_EIMR_TS_AVAIL. /
Kojto	90:cb3d968589d8	690
Kojto	90:cb3d968589d8	691	/! @brief Read current value of the ENET_EIMR_TS_AVAIL field. /
Kojto	90:cb3d968589d8	692	#define BR_ENET_EIMR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL))
Kojto	90:cb3d968589d8	693
Kojto	90:cb3d968589d8	694	/! @brief Format value for bitfield ENET_EIMR_TS_AVAIL. /
Kojto	90:cb3d968589d8	695	#define BF_ENET_EIMR_TS_AVAIL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TS_AVAIL) & BM_ENET_EIMR_TS_AVAIL)
Kojto	90:cb3d968589d8	696
Kojto	90:cb3d968589d8	697	/! @brief Set the TS_AVAIL field to a new value. /
Kojto	90:cb3d968589d8	698	#define BW_ENET_EIMR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL) = (v))
Kojto	90:cb3d968589d8	699	/@}/
Kojto	90:cb3d968589d8	700
Kojto	90:cb3d968589d8	701	/*!
Kojto	90:cb3d968589d8	702	* @name Register ENET_EIMR, field WAKEUP[17] (RW)
Kojto	90:cb3d968589d8	703	*
Kojto	90:cb3d968589d8	704	* Corresponds to interrupt source EIR[WAKEUP] register and determines whether
Kojto	90:cb3d968589d8	705	* an interrupt condition can generate an interrupt. At every module clock, the
Kojto	90:cb3d968589d8	706	* EIR samples the signal generated by the interrupting source. The corresponding
Kojto	90:cb3d968589d8	707	* EIR WAKEUP field reflects the state of the interrupt signal even if the
Kojto	90:cb3d968589d8	708	* corresponding EIMR field is cleared.
Kojto	90:cb3d968589d8	709	*/
Kojto	90:cb3d968589d8	710	/@{/
Kojto	90:cb3d968589d8	711	#define BP_ENET_EIMR_WAKEUP (17U) /!< Bit position for ENET_EIMR_WAKEUP. /
Kojto	90:cb3d968589d8	712	#define BM_ENET_EIMR_WAKEUP (0x00020000U) /!< Bit mask for ENET_EIMR_WAKEUP. /
Kojto	90:cb3d968589d8	713	#define BS_ENET_EIMR_WAKEUP (1U) /!< Bit field size in bits for ENET_EIMR_WAKEUP. /
Kojto	90:cb3d968589d8	714
Kojto	90:cb3d968589d8	715	/! @brief Read current value of the ENET_EIMR_WAKEUP field. /
Kojto	90:cb3d968589d8	716	#define BR_ENET_EIMR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP))
Kojto	90:cb3d968589d8	717
Kojto	90:cb3d968589d8	718	/! @brief Format value for bitfield ENET_EIMR_WAKEUP. /
Kojto	90:cb3d968589d8	719	#define BF_ENET_EIMR_WAKEUP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_WAKEUP) & BM_ENET_EIMR_WAKEUP)
Kojto	90:cb3d968589d8	720
Kojto	90:cb3d968589d8	721	/! @brief Set the WAKEUP field to a new value. /
Kojto	90:cb3d968589d8	722	#define BW_ENET_EIMR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP) = (v))
Kojto	90:cb3d968589d8	723	/@}/
Kojto	90:cb3d968589d8	724
Kojto	90:cb3d968589d8	725	/*!
Kojto	90:cb3d968589d8	726	* @name Register ENET_EIMR, field PLR[18] (RW)
Kojto	90:cb3d968589d8	727	*
Kojto	90:cb3d968589d8	728	* Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
Kojto	90:cb3d968589d8	729	* condition can generate an interrupt. At every module clock, the EIR samples
Kojto	90:cb3d968589d8	730	* the signal generated by the interrupting source. The corresponding EIR PLR field
Kojto	90:cb3d968589d8	731	* reflects the state of the interrupt signal even if the corresponding EIMR
Kojto	90:cb3d968589d8	732	* field is cleared.
Kojto	90:cb3d968589d8	733	*/
Kojto	90:cb3d968589d8	734	/@{/
Kojto	90:cb3d968589d8	735	#define BP_ENET_EIMR_PLR (18U) /!< Bit position for ENET_EIMR_PLR. /
Kojto	90:cb3d968589d8	736	#define BM_ENET_EIMR_PLR (0x00040000U) /!< Bit mask for ENET_EIMR_PLR. /
Kojto	90:cb3d968589d8	737	#define BS_ENET_EIMR_PLR (1U) /!< Bit field size in bits for ENET_EIMR_PLR. /
Kojto	90:cb3d968589d8	738
Kojto	90:cb3d968589d8	739	/! @brief Read current value of the ENET_EIMR_PLR field. /
Kojto	90:cb3d968589d8	740	#define BR_ENET_EIMR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR))
Kojto	90:cb3d968589d8	741
Kojto	90:cb3d968589d8	742	/! @brief Format value for bitfield ENET_EIMR_PLR. /
Kojto	90:cb3d968589d8	743	#define BF_ENET_EIMR_PLR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_PLR) & BM_ENET_EIMR_PLR)
Kojto	90:cb3d968589d8	744
Kojto	90:cb3d968589d8	745	/! @brief Set the PLR field to a new value. /
Kojto	90:cb3d968589d8	746	#define BW_ENET_EIMR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR) = (v))
Kojto	90:cb3d968589d8	747	/@}/
Kojto	90:cb3d968589d8	748
Kojto	90:cb3d968589d8	749	/*!
Kojto	90:cb3d968589d8	750	* @name Register ENET_EIMR, field UN[19] (RW)
Kojto	90:cb3d968589d8	751	*
Kojto	90:cb3d968589d8	752	* Corresponds to interrupt source EIR[UN] and determines whether an interrupt
Kojto	90:cb3d968589d8	753	* condition can generate an interrupt. At every module clock, the EIR samples the
Kojto	90:cb3d968589d8	754	* signal generated by the interrupting source. The corresponding EIR UN field
Kojto	90:cb3d968589d8	755	* reflects the state of the interrupt signal even if the corresponding EIMR field
Kojto	90:cb3d968589d8	756	* is cleared.
Kojto	90:cb3d968589d8	757	*/
Kojto	90:cb3d968589d8	758	/@{/
Kojto	90:cb3d968589d8	759	#define BP_ENET_EIMR_UN (19U) /!< Bit position for ENET_EIMR_UN. /
Kojto	90:cb3d968589d8	760	#define BM_ENET_EIMR_UN (0x00080000U) /!< Bit mask for ENET_EIMR_UN. /
Kojto	90:cb3d968589d8	761	#define BS_ENET_EIMR_UN (1U) /!< Bit field size in bits for ENET_EIMR_UN. /
Kojto	90:cb3d968589d8	762
Kojto	90:cb3d968589d8	763	/! @brief Read current value of the ENET_EIMR_UN field. /
Kojto	90:cb3d968589d8	764	#define BR_ENET_EIMR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN))
Kojto	90:cb3d968589d8	765
Kojto	90:cb3d968589d8	766	/! @brief Format value for bitfield ENET_EIMR_UN. /
Kojto	90:cb3d968589d8	767	#define BF_ENET_EIMR_UN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_UN) & BM_ENET_EIMR_UN)
Kojto	90:cb3d968589d8	768
Kojto	90:cb3d968589d8	769	/! @brief Set the UN field to a new value. /
Kojto	90:cb3d968589d8	770	#define BW_ENET_EIMR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN) = (v))
Kojto	90:cb3d968589d8	771	/@}/
Kojto	90:cb3d968589d8	772
Kojto	90:cb3d968589d8	773	/*!
Kojto	90:cb3d968589d8	774	* @name Register ENET_EIMR, field RL[20] (RW)
Kojto	90:cb3d968589d8	775	*
Kojto	90:cb3d968589d8	776	* Corresponds to interrupt source EIR[RL] and determines whether an interrupt
Kojto	90:cb3d968589d8	777	* condition can generate an interrupt. At every module clock, the EIR samples the
Kojto	90:cb3d968589d8	778	* signal generated by the interrupting source. The corresponding EIR RL field
Kojto	90:cb3d968589d8	779	* reflects the state of the interrupt signal even if the corresponding EIMR field
Kojto	90:cb3d968589d8	780	* is cleared.
Kojto	90:cb3d968589d8	781	*/
Kojto	90:cb3d968589d8	782	/@{/
Kojto	90:cb3d968589d8	783	#define BP_ENET_EIMR_RL (20U) /!< Bit position for ENET_EIMR_RL. /
Kojto	90:cb3d968589d8	784	#define BM_ENET_EIMR_RL (0x00100000U) /!< Bit mask for ENET_EIMR_RL. /
Kojto	90:cb3d968589d8	785	#define BS_ENET_EIMR_RL (1U) /!< Bit field size in bits for ENET_EIMR_RL. /
Kojto	90:cb3d968589d8	786
Kojto	90:cb3d968589d8	787	/! @brief Read current value of the ENET_EIMR_RL field. /
Kojto	90:cb3d968589d8	788	#define BR_ENET_EIMR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL))
Kojto	90:cb3d968589d8	789
Kojto	90:cb3d968589d8	790	/! @brief Format value for bitfield ENET_EIMR_RL. /
Kojto	90:cb3d968589d8	791	#define BF_ENET_EIMR_RL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RL) & BM_ENET_EIMR_RL)
Kojto	90:cb3d968589d8	792
Kojto	90:cb3d968589d8	793	/! @brief Set the RL field to a new value. /
Kojto	90:cb3d968589d8	794	#define BW_ENET_EIMR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL) = (v))
Kojto	90:cb3d968589d8	795	/@}/
Kojto	90:cb3d968589d8	796
Kojto	90:cb3d968589d8	797	/*!
Kojto	90:cb3d968589d8	798	* @name Register ENET_EIMR, field LC[21] (RW)
Kojto	90:cb3d968589d8	799	*
Kojto	90:cb3d968589d8	800	* Corresponds to interrupt source EIR[LC] and determines whether an interrupt
Kojto	90:cb3d968589d8	801	* condition can generate an interrupt. At every module clock, the EIR samples the
Kojto	90:cb3d968589d8	802	* signal generated by the interrupting source. The corresponding EIR LC field
Kojto	90:cb3d968589d8	803	* reflects the state of the interrupt signal even if the corresponding EIMR field
Kojto	90:cb3d968589d8	804	* is cleared.
Kojto	90:cb3d968589d8	805	*/
Kojto	90:cb3d968589d8	806	/@{/
Kojto	90:cb3d968589d8	807	#define BP_ENET_EIMR_LC (21U) /!< Bit position for ENET_EIMR_LC. /
Kojto	90:cb3d968589d8	808	#define BM_ENET_EIMR_LC (0x00200000U) /!< Bit mask for ENET_EIMR_LC. /
Kojto	90:cb3d968589d8	809	#define BS_ENET_EIMR_LC (1U) /!< Bit field size in bits for ENET_EIMR_LC. /
Kojto	90:cb3d968589d8	810
Kojto	90:cb3d968589d8	811	/! @brief Read current value of the ENET_EIMR_LC field. /
Kojto	90:cb3d968589d8	812	#define BR_ENET_EIMR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC))
Kojto	90:cb3d968589d8	813
Kojto	90:cb3d968589d8	814	/! @brief Format value for bitfield ENET_EIMR_LC. /
Kojto	90:cb3d968589d8	815	#define BF_ENET_EIMR_LC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_LC) & BM_ENET_EIMR_LC)
Kojto	90:cb3d968589d8	816
Kojto	90:cb3d968589d8	817	/! @brief Set the LC field to a new value. /
Kojto	90:cb3d968589d8	818	#define BW_ENET_EIMR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC) = (v))
Kojto	90:cb3d968589d8	819	/@}/
Kojto	90:cb3d968589d8	820
Kojto	90:cb3d968589d8	821	/*!
Kojto	90:cb3d968589d8	822	* @name Register ENET_EIMR, field EBERR[22] (RW)
Kojto	90:cb3d968589d8	823	*
Kojto	90:cb3d968589d8	824	* Corresponds to interrupt source EIR[EBERR] and determines whether an
Kojto	90:cb3d968589d8	825	* interrupt condition can generate an interrupt. At every module clock, the EIR samples
Kojto	90:cb3d968589d8	826	* the signal generated by the interrupting source. The corresponding EIR EBERR
Kojto	90:cb3d968589d8	827	* field reflects the state of the interrupt signal even if the corresponding EIMR
Kojto	90:cb3d968589d8	828	* field is cleared.
Kojto	90:cb3d968589d8	829	*/
Kojto	90:cb3d968589d8	830	/@{/
Kojto	90:cb3d968589d8	831	#define BP_ENET_EIMR_EBERR (22U) /!< Bit position for ENET_EIMR_EBERR. /
Kojto	90:cb3d968589d8	832	#define BM_ENET_EIMR_EBERR (0x00400000U) /!< Bit mask for ENET_EIMR_EBERR. /
Kojto	90:cb3d968589d8	833	#define BS_ENET_EIMR_EBERR (1U) /!< Bit field size in bits for ENET_EIMR_EBERR. /
Kojto	90:cb3d968589d8	834
Kojto	90:cb3d968589d8	835	/! @brief Read current value of the ENET_EIMR_EBERR field. /
Kojto	90:cb3d968589d8	836	#define BR_ENET_EIMR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR))
Kojto	90:cb3d968589d8	837
Kojto	90:cb3d968589d8	838	/! @brief Format value for bitfield ENET_EIMR_EBERR. /
Kojto	90:cb3d968589d8	839	#define BF_ENET_EIMR_EBERR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_EBERR) & BM_ENET_EIMR_EBERR)
Kojto	90:cb3d968589d8	840
Kojto	90:cb3d968589d8	841	/! @brief Set the EBERR field to a new value. /
Kojto	90:cb3d968589d8	842	#define BW_ENET_EIMR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR) = (v))
Kojto	90:cb3d968589d8	843	/@}/
Kojto	90:cb3d968589d8	844
Kojto	90:cb3d968589d8	845	/*!
Kojto	90:cb3d968589d8	846	* @name Register ENET_EIMR, field MII[23] (RW)
Kojto	90:cb3d968589d8	847	*
Kojto	90:cb3d968589d8	848	* Corresponds to interrupt source EIR[MII] and determines whether an interrupt
Kojto	90:cb3d968589d8	849	* condition can generate an interrupt. At every module clock, the EIR samples
Kojto	90:cb3d968589d8	850	* the signal generated by the interrupting source. The corresponding EIR MII field
Kojto	90:cb3d968589d8	851	* reflects the state of the interrupt signal even if the corresponding EIMR
Kojto	90:cb3d968589d8	852	* field is cleared.
Kojto	90:cb3d968589d8	853	*/
Kojto	90:cb3d968589d8	854	/@{/
Kojto	90:cb3d968589d8	855	#define BP_ENET_EIMR_MII (23U) /!< Bit position for ENET_EIMR_MII. /
Kojto	90:cb3d968589d8	856	#define BM_ENET_EIMR_MII (0x00800000U) /!< Bit mask for ENET_EIMR_MII. /
Kojto	90:cb3d968589d8	857	#define BS_ENET_EIMR_MII (1U) /!< Bit field size in bits for ENET_EIMR_MII. /
Kojto	90:cb3d968589d8	858
Kojto	90:cb3d968589d8	859	/! @brief Read current value of the ENET_EIMR_MII field. /
Kojto	90:cb3d968589d8	860	#define BR_ENET_EIMR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII))
Kojto	90:cb3d968589d8	861
Kojto	90:cb3d968589d8	862	/! @brief Format value for bitfield ENET_EIMR_MII. /
Kojto	90:cb3d968589d8	863	#define BF_ENET_EIMR_MII(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_MII) & BM_ENET_EIMR_MII)
Kojto	90:cb3d968589d8	864
Kojto	90:cb3d968589d8	865	/! @brief Set the MII field to a new value. /
Kojto	90:cb3d968589d8	866	#define BW_ENET_EIMR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII) = (v))
Kojto	90:cb3d968589d8	867	/@}/
Kojto	90:cb3d968589d8	868
Kojto	90:cb3d968589d8	869	/*!
Kojto	90:cb3d968589d8	870	* @name Register ENET_EIMR, field RXB[24] (RW)
Kojto	90:cb3d968589d8	871	*
Kojto	90:cb3d968589d8	872	* Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
Kojto	90:cb3d968589d8	873	* condition can generate an interrupt. At every module clock, the EIR samples
Kojto	90:cb3d968589d8	874	* the signal generated by the interrupting source. The corresponding EIR RXB field
Kojto	90:cb3d968589d8	875	* reflects the state of the interrupt signal even if the corresponding EIMR
Kojto	90:cb3d968589d8	876	* field is cleared.
Kojto	90:cb3d968589d8	877	*/
Kojto	90:cb3d968589d8	878	/@{/
Kojto	90:cb3d968589d8	879	#define BP_ENET_EIMR_RXB (24U) /!< Bit position for ENET_EIMR_RXB. /
Kojto	90:cb3d968589d8	880	#define BM_ENET_EIMR_RXB (0x01000000U) /!< Bit mask for ENET_EIMR_RXB. /
Kojto	90:cb3d968589d8	881	#define BS_ENET_EIMR_RXB (1U) /!< Bit field size in bits for ENET_EIMR_RXB. /
Kojto	90:cb3d968589d8	882
Kojto	90:cb3d968589d8	883	/! @brief Read current value of the ENET_EIMR_RXB field. /
Kojto	90:cb3d968589d8	884	#define BR_ENET_EIMR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB))
Kojto	90:cb3d968589d8	885
Kojto	90:cb3d968589d8	886	/! @brief Format value for bitfield ENET_EIMR_RXB. /
Kojto	90:cb3d968589d8	887	#define BF_ENET_EIMR_RXB(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RXB) & BM_ENET_EIMR_RXB)
Kojto	90:cb3d968589d8	888
Kojto	90:cb3d968589d8	889	/! @brief Set the RXB field to a new value. /
Kojto	90:cb3d968589d8	890	#define BW_ENET_EIMR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB) = (v))
Kojto	90:cb3d968589d8	891	/@}/
Kojto	90:cb3d968589d8	892
Kojto	90:cb3d968589d8	893	/*!
Kojto	90:cb3d968589d8	894	* @name Register ENET_EIMR, field RXF[25] (RW)
Kojto	90:cb3d968589d8	895	*
Kojto	90:cb3d968589d8	896	* Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
Kojto	90:cb3d968589d8	897	* condition can generate an interrupt. At every module clock, the EIR samples
Kojto	90:cb3d968589d8	898	* the signal generated by the interrupting source. The corresponding EIR RXF field
Kojto	90:cb3d968589d8	899	* reflects the state of the interrupt signal even if the corresponding EIMR
Kojto	90:cb3d968589d8	900	* field is cleared.
Kojto	90:cb3d968589d8	901	*/
Kojto	90:cb3d968589d8	902	/@{/
Kojto	90:cb3d968589d8	903	#define BP_ENET_EIMR_RXF (25U) /!< Bit position for ENET_EIMR_RXF. /
Kojto	90:cb3d968589d8	904	#define BM_ENET_EIMR_RXF (0x02000000U) /!< Bit mask for ENET_EIMR_RXF. /
Kojto	90:cb3d968589d8	905	#define BS_ENET_EIMR_RXF (1U) /!< Bit field size in bits for ENET_EIMR_RXF. /
Kojto	90:cb3d968589d8	906
Kojto	90:cb3d968589d8	907	/! @brief Read current value of the ENET_EIMR_RXF field. /
Kojto	90:cb3d968589d8	908	#define BR_ENET_EIMR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF))
Kojto	90:cb3d968589d8	909
Kojto	90:cb3d968589d8	910	/! @brief Format value for bitfield ENET_EIMR_RXF. /
Kojto	90:cb3d968589d8	911	#define BF_ENET_EIMR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RXF) & BM_ENET_EIMR_RXF)
Kojto	90:cb3d968589d8	912
Kojto	90:cb3d968589d8	913	/! @brief Set the RXF field to a new value. /
Kojto	90:cb3d968589d8	914	#define BW_ENET_EIMR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF) = (v))
Kojto	90:cb3d968589d8	915	/@}/
Kojto	90:cb3d968589d8	916
Kojto	90:cb3d968589d8	917	/*!
Kojto	90:cb3d968589d8	918	* @name Register ENET_EIMR, field TXB[26] (RW)
Kojto	90:cb3d968589d8	919	*
Kojto	90:cb3d968589d8	920	* Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
Kojto	90:cb3d968589d8	921	* condition can generate an interrupt. At every module clock, the EIR samples
Kojto	90:cb3d968589d8	922	* the signal generated by the interrupting source. The corresponding EIR TXF field
Kojto	90:cb3d968589d8	923	* reflects the state of the interrupt signal even if the corresponding EIMR
Kojto	90:cb3d968589d8	924	* field is cleared.
Kojto	90:cb3d968589d8	925	*
Kojto	90:cb3d968589d8	926	* Values:
Kojto	90:cb3d968589d8	927	* - 0 - The corresponding interrupt source is masked.
Kojto	90:cb3d968589d8	928	* - 1 - The corresponding interrupt source is not masked.
Kojto	90:cb3d968589d8	929	*/
Kojto	90:cb3d968589d8	930	/@{/
Kojto	90:cb3d968589d8	931	#define BP_ENET_EIMR_TXB (26U) /!< Bit position for ENET_EIMR_TXB. /
Kojto	90:cb3d968589d8	932	#define BM_ENET_EIMR_TXB (0x04000000U) /!< Bit mask for ENET_EIMR_TXB. /
Kojto	90:cb3d968589d8	933	#define BS_ENET_EIMR_TXB (1U) /!< Bit field size in bits for ENET_EIMR_TXB. /
Kojto	90:cb3d968589d8	934
Kojto	90:cb3d968589d8	935	/! @brief Read current value of the ENET_EIMR_TXB field. /
Kojto	90:cb3d968589d8	936	#define BR_ENET_EIMR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB))
Kojto	90:cb3d968589d8	937
Kojto	90:cb3d968589d8	938	/! @brief Format value for bitfield ENET_EIMR_TXB. /
Kojto	90:cb3d968589d8	939	#define BF_ENET_EIMR_TXB(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TXB) & BM_ENET_EIMR_TXB)
Kojto	90:cb3d968589d8	940
Kojto	90:cb3d968589d8	941	/! @brief Set the TXB field to a new value. /
Kojto	90:cb3d968589d8	942	#define BW_ENET_EIMR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB) = (v))
Kojto	90:cb3d968589d8	943	/@}/
Kojto	90:cb3d968589d8	944
Kojto	90:cb3d968589d8	945	/*!
Kojto	90:cb3d968589d8	946	* @name Register ENET_EIMR, field TXF[27] (RW)
Kojto	90:cb3d968589d8	947	*
Kojto	90:cb3d968589d8	948	* Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
Kojto	90:cb3d968589d8	949	* condition can generate an interrupt. At every module clock, the EIR samples
Kojto	90:cb3d968589d8	950	* the signal generated by the interrupting source. The corresponding EIR TXF field
Kojto	90:cb3d968589d8	951	* reflects the state of the interrupt signal even if the corresponding EIMR
Kojto	90:cb3d968589d8	952	* field is cleared.
Kojto	90:cb3d968589d8	953	*
Kojto	90:cb3d968589d8	954	* Values:
Kojto	90:cb3d968589d8	955	* - 0 - The corresponding interrupt source is masked.
Kojto	90:cb3d968589d8	956	* - 1 - The corresponding interrupt source is not masked.
Kojto	90:cb3d968589d8	957	*/
Kojto	90:cb3d968589d8	958	/@{/
Kojto	90:cb3d968589d8	959	#define BP_ENET_EIMR_TXF (27U) /!< Bit position for ENET_EIMR_TXF. /
Kojto	90:cb3d968589d8	960	#define BM_ENET_EIMR_TXF (0x08000000U) /!< Bit mask for ENET_EIMR_TXF. /
Kojto	90:cb3d968589d8	961	#define BS_ENET_EIMR_TXF (1U) /!< Bit field size in bits for ENET_EIMR_TXF. /
Kojto	90:cb3d968589d8	962
Kojto	90:cb3d968589d8	963	/! @brief Read current value of the ENET_EIMR_TXF field. /
Kojto	90:cb3d968589d8	964	#define BR_ENET_EIMR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF))
Kojto	90:cb3d968589d8	965
Kojto	90:cb3d968589d8	966	/! @brief Format value for bitfield ENET_EIMR_TXF. /
Kojto	90:cb3d968589d8	967	#define BF_ENET_EIMR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TXF) & BM_ENET_EIMR_TXF)
Kojto	90:cb3d968589d8	968
Kojto	90:cb3d968589d8	969	/! @brief Set the TXF field to a new value. /
Kojto	90:cb3d968589d8	970	#define BW_ENET_EIMR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF) = (v))
Kojto	90:cb3d968589d8	971	/@}/
Kojto	90:cb3d968589d8	972
Kojto	90:cb3d968589d8	973	/*!
Kojto	90:cb3d968589d8	974	* @name Register ENET_EIMR, field GRA[28] (RW)
Kojto	90:cb3d968589d8	975	*
Kojto	90:cb3d968589d8	976	* Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
Kojto	90:cb3d968589d8	977	* condition can generate an interrupt. At every module clock, the EIR samples
Kojto	90:cb3d968589d8	978	* the signal generated by the interrupting source. The corresponding EIR GRA field
Kojto	90:cb3d968589d8	979	* reflects the state of the interrupt signal even if the corresponding EIMR
Kojto	90:cb3d968589d8	980	* field is cleared.
Kojto	90:cb3d968589d8	981	*
Kojto	90:cb3d968589d8	982	* Values:
Kojto	90:cb3d968589d8	983	* - 0 - The corresponding interrupt source is masked.
Kojto	90:cb3d968589d8	984	* - 1 - The corresponding interrupt source is not masked.
Kojto	90:cb3d968589d8	985	*/
Kojto	90:cb3d968589d8	986	/@{/
Kojto	90:cb3d968589d8	987	#define BP_ENET_EIMR_GRA (28U) /!< Bit position for ENET_EIMR_GRA. /
Kojto	90:cb3d968589d8	988	#define BM_ENET_EIMR_GRA (0x10000000U) /!< Bit mask for ENET_EIMR_GRA. /
Kojto	90:cb3d968589d8	989	#define BS_ENET_EIMR_GRA (1U) /!< Bit field size in bits for ENET_EIMR_GRA. /
Kojto	90:cb3d968589d8	990
Kojto	90:cb3d968589d8	991	/! @brief Read current value of the ENET_EIMR_GRA field. /
Kojto	90:cb3d968589d8	992	#define BR_ENET_EIMR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA))
Kojto	90:cb3d968589d8	993
Kojto	90:cb3d968589d8	994	/! @brief Format value for bitfield ENET_EIMR_GRA. /
Kojto	90:cb3d968589d8	995	#define BF_ENET_EIMR_GRA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_GRA) & BM_ENET_EIMR_GRA)
Kojto	90:cb3d968589d8	996
Kojto	90:cb3d968589d8	997	/! @brief Set the GRA field to a new value. /
Kojto	90:cb3d968589d8	998	#define BW_ENET_EIMR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA) = (v))
Kojto	90:cb3d968589d8	999	/@}/
Kojto	90:cb3d968589d8	1000
Kojto	90:cb3d968589d8	1001	/*!
Kojto	90:cb3d968589d8	1002	* @name Register ENET_EIMR, field BABT[29] (RW)
Kojto	90:cb3d968589d8	1003	*
Kojto	90:cb3d968589d8	1004	* Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
Kojto	90:cb3d968589d8	1005	* condition can generate an interrupt. At every module clock, the EIR samples
Kojto	90:cb3d968589d8	1006	* the signal generated by the interrupting source. The corresponding EIR BABT
Kojto	90:cb3d968589d8	1007	* field reflects the state of the interrupt signal even if the corresponding EIMR
Kojto	90:cb3d968589d8	1008	* field is cleared.
Kojto	90:cb3d968589d8	1009	*
Kojto	90:cb3d968589d8	1010	* Values:
Kojto	90:cb3d968589d8	1011	* - 0 - The corresponding interrupt source is masked.
Kojto	90:cb3d968589d8	1012	* - 1 - The corresponding interrupt source is not masked.
Kojto	90:cb3d968589d8	1013	*/
Kojto	90:cb3d968589d8	1014	/@{/
Kojto	90:cb3d968589d8	1015	#define BP_ENET_EIMR_BABT (29U) /!< Bit position for ENET_EIMR_BABT. /
Kojto	90:cb3d968589d8	1016	#define BM_ENET_EIMR_BABT (0x20000000U) /!< Bit mask for ENET_EIMR_BABT. /
Kojto	90:cb3d968589d8	1017	#define BS_ENET_EIMR_BABT (1U) /!< Bit field size in bits for ENET_EIMR_BABT. /
Kojto	90:cb3d968589d8	1018
Kojto	90:cb3d968589d8	1019	/! @brief Read current value of the ENET_EIMR_BABT field. /
Kojto	90:cb3d968589d8	1020	#define BR_ENET_EIMR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT))
Kojto	90:cb3d968589d8	1021
Kojto	90:cb3d968589d8	1022	/! @brief Format value for bitfield ENET_EIMR_BABT. /
Kojto	90:cb3d968589d8	1023	#define BF_ENET_EIMR_BABT(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_BABT) & BM_ENET_EIMR_BABT)
Kojto	90:cb3d968589d8	1024
Kojto	90:cb3d968589d8	1025	/! @brief Set the BABT field to a new value. /
Kojto	90:cb3d968589d8	1026	#define BW_ENET_EIMR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT) = (v))
Kojto	90:cb3d968589d8	1027	/@}/
Kojto	90:cb3d968589d8	1028
Kojto	90:cb3d968589d8	1029	/*!
Kojto	90:cb3d968589d8	1030	* @name Register ENET_EIMR, field BABR[30] (RW)
Kojto	90:cb3d968589d8	1031	*
Kojto	90:cb3d968589d8	1032	* Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
Kojto	90:cb3d968589d8	1033	* condition can generate an interrupt. At every module clock, the EIR samples
Kojto	90:cb3d968589d8	1034	* the signal generated by the interrupting source. The corresponding EIR BABR
Kojto	90:cb3d968589d8	1035	* field reflects the state of the interrupt signal even if the corresponding EIMR
Kojto	90:cb3d968589d8	1036	* field is cleared.
Kojto	90:cb3d968589d8	1037	*
Kojto	90:cb3d968589d8	1038	* Values:
Kojto	90:cb3d968589d8	1039	* - 0 - The corresponding interrupt source is masked.
Kojto	90:cb3d968589d8	1040	* - 1 - The corresponding interrupt source is not masked.
Kojto	90:cb3d968589d8	1041	*/
Kojto	90:cb3d968589d8	1042	/@{/
Kojto	90:cb3d968589d8	1043	#define BP_ENET_EIMR_BABR (30U) /!< Bit position for ENET_EIMR_BABR. /
Kojto	90:cb3d968589d8	1044	#define BM_ENET_EIMR_BABR (0x40000000U) /!< Bit mask for ENET_EIMR_BABR. /
Kojto	90:cb3d968589d8	1045	#define BS_ENET_EIMR_BABR (1U) /!< Bit field size in bits for ENET_EIMR_BABR. /
Kojto	90:cb3d968589d8	1046
Kojto	90:cb3d968589d8	1047	/! @brief Read current value of the ENET_EIMR_BABR field. /
Kojto	90:cb3d968589d8	1048	#define BR_ENET_EIMR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR))
Kojto	90:cb3d968589d8	1049
Kojto	90:cb3d968589d8	1050	/! @brief Format value for bitfield ENET_EIMR_BABR. /
Kojto	90:cb3d968589d8	1051	#define BF_ENET_EIMR_BABR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_BABR) & BM_ENET_EIMR_BABR)
Kojto	90:cb3d968589d8	1052
Kojto	90:cb3d968589d8	1053	/! @brief Set the BABR field to a new value. /
Kojto	90:cb3d968589d8	1054	#define BW_ENET_EIMR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR) = (v))
Kojto	90:cb3d968589d8	1055	/@}/
Kojto	90:cb3d968589d8	1056
Kojto	90:cb3d968589d8	1057	/*******************************************************************************
Kojto	90:cb3d968589d8	1058	* HW_ENET_RDAR - Receive Descriptor Active Register
Kojto	90:cb3d968589d8	1059	******************************************************************************/
Kojto	90:cb3d968589d8	1060
Kojto	90:cb3d968589d8	1061	/*!
Kojto	90:cb3d968589d8	1062	* @brief HW_ENET_RDAR - Receive Descriptor Active Register (RW)
Kojto	90:cb3d968589d8	1063	*
Kojto	90:cb3d968589d8	1064	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1065	*
Kojto	90:cb3d968589d8	1066	* RDAR is a command register, written by the user, to indicate that the receive
Kojto	90:cb3d968589d8	1067	* descriptor ring has been updated, that is, that the driver produced empty
Kojto	90:cb3d968589d8	1068	* receive buffers with the empty bit set.
Kojto	90:cb3d968589d8	1069	*/
Kojto	90:cb3d968589d8	1070	typedef union _hw_enet_rdar
Kojto	90:cb3d968589d8	1071	{
Kojto	90:cb3d968589d8	1072	uint32_t U;
Kojto	90:cb3d968589d8	1073	struct _hw_enet_rdar_bitfields
Kojto	90:cb3d968589d8	1074	{
Kojto	90:cb3d968589d8	1075	uint32_t RESERVED0 : 24; /!< [23:0] /
Kojto	90:cb3d968589d8	1076	uint32_t RDAR : 1; /!< [24] Receive Descriptor Active /
Kojto	90:cb3d968589d8	1077	uint32_t RESERVED1 : 7; /!< [31:25] /
Kojto	90:cb3d968589d8	1078	} B;
Kojto	90:cb3d968589d8	1079	} hw_enet_rdar_t;
Kojto	90:cb3d968589d8	1080
Kojto	90:cb3d968589d8	1081	/*!
Kojto	90:cb3d968589d8	1082	* @name Constants and macros for entire ENET_RDAR register
Kojto	90:cb3d968589d8	1083	*/
Kojto	90:cb3d968589d8	1084	/@{/
Kojto	90:cb3d968589d8	1085	#define HW_ENET_RDAR_ADDR(x) ((x) + 0x10U)
Kojto	90:cb3d968589d8	1086
Kojto	90:cb3d968589d8	1087	#define HW_ENET_RDAR(x) ((__IO hw_enet_rdar_t ) HW_ENET_RDAR_ADDR(x))
Kojto	90:cb3d968589d8	1088	#define HW_ENET_RDAR_RD(x) (HW_ENET_RDAR(x).U)
Kojto	90:cb3d968589d8	1089	#define HW_ENET_RDAR_WR(x, v) (HW_ENET_RDAR(x).U = (v))
Kojto	90:cb3d968589d8	1090	#define HW_ENET_RDAR_SET(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1091	#define HW_ENET_RDAR_CLR(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1092	#define HW_ENET_RDAR_TOG(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1093	/@}/
Kojto	90:cb3d968589d8	1094
Kojto	90:cb3d968589d8	1095	/*
Kojto	90:cb3d968589d8	1096	* Constants & macros for individual ENET_RDAR bitfields
Kojto	90:cb3d968589d8	1097	*/
Kojto	90:cb3d968589d8	1098
Kojto	90:cb3d968589d8	1099	/*!
Kojto	90:cb3d968589d8	1100	* @name Register ENET_RDAR, field RDAR[24] (RW)
Kojto	90:cb3d968589d8	1101	*
Kojto	90:cb3d968589d8	1102	* Always set to 1 when this register is written, regardless of the value
Kojto	90:cb3d968589d8	1103	* written. This field is cleared by the MAC device when no additional empty
Kojto	90:cb3d968589d8	1104	* descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
Kojto	90:cb3d968589d8	1105	* from set to cleared or when ECR[RESET] is set.
Kojto	90:cb3d968589d8	1106	*/
Kojto	90:cb3d968589d8	1107	/@{/
Kojto	90:cb3d968589d8	1108	#define BP_ENET_RDAR_RDAR (24U) /!< Bit position for ENET_RDAR_RDAR. /
Kojto	90:cb3d968589d8	1109	#define BM_ENET_RDAR_RDAR (0x01000000U) /!< Bit mask for ENET_RDAR_RDAR. /
Kojto	90:cb3d968589d8	1110	#define BS_ENET_RDAR_RDAR (1U) /!< Bit field size in bits for ENET_RDAR_RDAR. /
Kojto	90:cb3d968589d8	1111
Kojto	90:cb3d968589d8	1112	/! @brief Read current value of the ENET_RDAR_RDAR field. /
Kojto	90:cb3d968589d8	1113	#define BR_ENET_RDAR_RDAR(x) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR))
Kojto	90:cb3d968589d8	1114
Kojto	90:cb3d968589d8	1115	/! @brief Format value for bitfield ENET_RDAR_RDAR. /
Kojto	90:cb3d968589d8	1116	#define BF_ENET_RDAR_RDAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RDAR_RDAR) & BM_ENET_RDAR_RDAR)
Kojto	90:cb3d968589d8	1117
Kojto	90:cb3d968589d8	1118	/! @brief Set the RDAR field to a new value. /
Kojto	90:cb3d968589d8	1119	#define BW_ENET_RDAR_RDAR(x, v) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR) = (v))
Kojto	90:cb3d968589d8	1120	/@}/
Kojto	90:cb3d968589d8	1121
Kojto	90:cb3d968589d8	1122	/*******************************************************************************
Kojto	90:cb3d968589d8	1123	* HW_ENET_TDAR - Transmit Descriptor Active Register
Kojto	90:cb3d968589d8	1124	******************************************************************************/
Kojto	90:cb3d968589d8	1125
Kojto	90:cb3d968589d8	1126	/*!
Kojto	90:cb3d968589d8	1127	* @brief HW_ENET_TDAR - Transmit Descriptor Active Register (RW)
Kojto	90:cb3d968589d8	1128	*
Kojto	90:cb3d968589d8	1129	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1130	*
Kojto	90:cb3d968589d8	1131	* The TDAR is a command register that the user writes to indicate that the
Kojto	90:cb3d968589d8	1132	* transmit descriptor ring has been updated, that is, that transmit buffers have
Kojto	90:cb3d968589d8	1133	* been produced by the driver with the ready bit set in the buffer descriptor. The
Kojto	90:cb3d968589d8	1134	* TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
Kojto	90:cb3d968589d8	1135	* cleared, or when ECR[RESET] is set.
Kojto	90:cb3d968589d8	1136	*/
Kojto	90:cb3d968589d8	1137	typedef union _hw_enet_tdar
Kojto	90:cb3d968589d8	1138	{
Kojto	90:cb3d968589d8	1139	uint32_t U;
Kojto	90:cb3d968589d8	1140	struct _hw_enet_tdar_bitfields
Kojto	90:cb3d968589d8	1141	{
Kojto	90:cb3d968589d8	1142	uint32_t RESERVED0 : 24; /!< [23:0] /
Kojto	90:cb3d968589d8	1143	uint32_t TDAR : 1; /!< [24] Transmit Descriptor Active /
Kojto	90:cb3d968589d8	1144	uint32_t RESERVED1 : 7; /!< [31:25] /
Kojto	90:cb3d968589d8	1145	} B;
Kojto	90:cb3d968589d8	1146	} hw_enet_tdar_t;
Kojto	90:cb3d968589d8	1147
Kojto	90:cb3d968589d8	1148	/*!
Kojto	90:cb3d968589d8	1149	* @name Constants and macros for entire ENET_TDAR register
Kojto	90:cb3d968589d8	1150	*/
Kojto	90:cb3d968589d8	1151	/@{/
Kojto	90:cb3d968589d8	1152	#define HW_ENET_TDAR_ADDR(x) ((x) + 0x14U)
Kojto	90:cb3d968589d8	1153
Kojto	90:cb3d968589d8	1154	#define HW_ENET_TDAR(x) ((__IO hw_enet_tdar_t ) HW_ENET_TDAR_ADDR(x))
Kojto	90:cb3d968589d8	1155	#define HW_ENET_TDAR_RD(x) (HW_ENET_TDAR(x).U)
Kojto	90:cb3d968589d8	1156	#define HW_ENET_TDAR_WR(x, v) (HW_ENET_TDAR(x).U = (v))
Kojto	90:cb3d968589d8	1157	#define HW_ENET_TDAR_SET(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1158	#define HW_ENET_TDAR_CLR(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1159	#define HW_ENET_TDAR_TOG(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1160	/@}/
Kojto	90:cb3d968589d8	1161
Kojto	90:cb3d968589d8	1162	/*
Kojto	90:cb3d968589d8	1163	* Constants & macros for individual ENET_TDAR bitfields
Kojto	90:cb3d968589d8	1164	*/
Kojto	90:cb3d968589d8	1165
Kojto	90:cb3d968589d8	1166	/*!
Kojto	90:cb3d968589d8	1167	* @name Register ENET_TDAR, field TDAR[24] (RW)
Kojto	90:cb3d968589d8	1168	*
Kojto	90:cb3d968589d8	1169	* Always set to 1 when this register is written, regardless of the value
Kojto	90:cb3d968589d8	1170	* written. This bit is cleared by the MAC device when no additional ready descriptors
Kojto	90:cb3d968589d8	1171	* remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
Kojto	90:cb3d968589d8	1172	* set to cleared or when ECR[RESET] is set.
Kojto	90:cb3d968589d8	1173	*/
Kojto	90:cb3d968589d8	1174	/@{/
Kojto	90:cb3d968589d8	1175	#define BP_ENET_TDAR_TDAR (24U) /!< Bit position for ENET_TDAR_TDAR. /
Kojto	90:cb3d968589d8	1176	#define BM_ENET_TDAR_TDAR (0x01000000U) /!< Bit mask for ENET_TDAR_TDAR. /
Kojto	90:cb3d968589d8	1177	#define BS_ENET_TDAR_TDAR (1U) /!< Bit field size in bits for ENET_TDAR_TDAR. /
Kojto	90:cb3d968589d8	1178
Kojto	90:cb3d968589d8	1179	/! @brief Read current value of the ENET_TDAR_TDAR field. /
Kojto	90:cb3d968589d8	1180	#define BR_ENET_TDAR_TDAR(x) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR))
Kojto	90:cb3d968589d8	1181
Kojto	90:cb3d968589d8	1182	/! @brief Format value for bitfield ENET_TDAR_TDAR. /
Kojto	90:cb3d968589d8	1183	#define BF_ENET_TDAR_TDAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TDAR_TDAR) & BM_ENET_TDAR_TDAR)
Kojto	90:cb3d968589d8	1184
Kojto	90:cb3d968589d8	1185	/! @brief Set the TDAR field to a new value. /
Kojto	90:cb3d968589d8	1186	#define BW_ENET_TDAR_TDAR(x, v) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR) = (v))
Kojto	90:cb3d968589d8	1187	/@}/
Kojto	90:cb3d968589d8	1188
Kojto	90:cb3d968589d8	1189	/*******************************************************************************
Kojto	90:cb3d968589d8	1190	* HW_ENET_ECR - Ethernet Control Register
Kojto	90:cb3d968589d8	1191	******************************************************************************/
Kojto	90:cb3d968589d8	1192
Kojto	90:cb3d968589d8	1193	/*!
Kojto	90:cb3d968589d8	1194	* @brief HW_ENET_ECR - Ethernet Control Register (RW)
Kojto	90:cb3d968589d8	1195	*
Kojto	90:cb3d968589d8	1196	* Reset value: 0xF0000000U
Kojto	90:cb3d968589d8	1197	*
Kojto	90:cb3d968589d8	1198	* ECR is a read/write user register, though hardware may also alter fields in
Kojto	90:cb3d968589d8	1199	* this register. It controls many of the high level features of the Ethernet MAC,
Kojto	90:cb3d968589d8	1200	* including legacy FEC support through the EN1588 field.
Kojto	90:cb3d968589d8	1201	*/
Kojto	90:cb3d968589d8	1202	typedef union _hw_enet_ecr
Kojto	90:cb3d968589d8	1203	{
Kojto	90:cb3d968589d8	1204	uint32_t U;
Kojto	90:cb3d968589d8	1205	struct _hw_enet_ecr_bitfields
Kojto	90:cb3d968589d8	1206	{
Kojto	90:cb3d968589d8	1207	uint32_t RESET : 1; /!< [0] Ethernet MAC Reset /
Kojto	90:cb3d968589d8	1208	uint32_t ETHEREN : 1; /!< [1] Ethernet Enable /
Kojto	90:cb3d968589d8	1209	uint32_t MAGICEN : 1; /!< [2] Magic Packet Detection Enable /
Kojto	90:cb3d968589d8	1210	uint32_t SLEEP : 1; /!< [3] Sleep Mode Enable /
Kojto	90:cb3d968589d8	1211	uint32_t EN1588 : 1; /!< [4] EN1588 Enable /
Kojto	90:cb3d968589d8	1212	uint32_t RESERVED0 : 1; /!< [5] /
Kojto	90:cb3d968589d8	1213	uint32_t DBGEN : 1; /!< [6] Debug Enable /
Kojto	90:cb3d968589d8	1214	uint32_t STOPEN : 1; /!< [7] STOPEN Signal Control /
Kojto	90:cb3d968589d8	1215	uint32_t DBSWP : 1; /!< [8] Descriptor Byte Swapping Enable /
Kojto	90:cb3d968589d8	1216	uint32_t RESERVED1 : 23; /!< [31:9] /
Kojto	90:cb3d968589d8	1217	} B;
Kojto	90:cb3d968589d8	1218	} hw_enet_ecr_t;
Kojto	90:cb3d968589d8	1219
Kojto	90:cb3d968589d8	1220	/*!
Kojto	90:cb3d968589d8	1221	* @name Constants and macros for entire ENET_ECR register
Kojto	90:cb3d968589d8	1222	*/
Kojto	90:cb3d968589d8	1223	/@{/
Kojto	90:cb3d968589d8	1224	#define HW_ENET_ECR_ADDR(x) ((x) + 0x24U)
Kojto	90:cb3d968589d8	1225
Kojto	90:cb3d968589d8	1226	#define HW_ENET_ECR(x) ((__IO hw_enet_ecr_t ) HW_ENET_ECR_ADDR(x))
Kojto	90:cb3d968589d8	1227	#define HW_ENET_ECR_RD(x) (HW_ENET_ECR(x).U)
Kojto	90:cb3d968589d8	1228	#define HW_ENET_ECR_WR(x, v) (HW_ENET_ECR(x).U = (v))
Kojto	90:cb3d968589d8	1229	#define HW_ENET_ECR_SET(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1230	#define HW_ENET_ECR_CLR(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1231	#define HW_ENET_ECR_TOG(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1232	/@}/
Kojto	90:cb3d968589d8	1233
Kojto	90:cb3d968589d8	1234	/*
Kojto	90:cb3d968589d8	1235	* Constants & macros for individual ENET_ECR bitfields
Kojto	90:cb3d968589d8	1236	*/
Kojto	90:cb3d968589d8	1237
Kojto	90:cb3d968589d8	1238	/*!
Kojto	90:cb3d968589d8	1239	* @name Register ENET_ECR, field RESET[0] (RW)
Kojto	90:cb3d968589d8	1240	*
Kojto	90:cb3d968589d8	1241	* When this field is set, it clears the ETHEREN field.
Kojto	90:cb3d968589d8	1242	*/
Kojto	90:cb3d968589d8	1243	/@{/
Kojto	90:cb3d968589d8	1244	#define BP_ENET_ECR_RESET (0U) /!< Bit position for ENET_ECR_RESET. /
Kojto	90:cb3d968589d8	1245	#define BM_ENET_ECR_RESET (0x00000001U) /!< Bit mask for ENET_ECR_RESET. /
Kojto	90:cb3d968589d8	1246	#define BS_ENET_ECR_RESET (1U) /!< Bit field size in bits for ENET_ECR_RESET. /
Kojto	90:cb3d968589d8	1247
Kojto	90:cb3d968589d8	1248	/! @brief Read current value of the ENET_ECR_RESET field. /
Kojto	90:cb3d968589d8	1249	#define BR_ENET_ECR_RESET(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET))
Kojto	90:cb3d968589d8	1250
Kojto	90:cb3d968589d8	1251	/! @brief Format value for bitfield ENET_ECR_RESET. /
Kojto	90:cb3d968589d8	1252	#define BF_ENET_ECR_RESET(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_RESET) & BM_ENET_ECR_RESET)
Kojto	90:cb3d968589d8	1253
Kojto	90:cb3d968589d8	1254	/! @brief Set the RESET field to a new value. /
Kojto	90:cb3d968589d8	1255	#define BW_ENET_ECR_RESET(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET) = (v))
Kojto	90:cb3d968589d8	1256	/@}/
Kojto	90:cb3d968589d8	1257
Kojto	90:cb3d968589d8	1258	/*!
Kojto	90:cb3d968589d8	1259	* @name Register ENET_ECR, field ETHEREN[1] (RW)
Kojto	90:cb3d968589d8	1260	*
Kojto	90:cb3d968589d8	1261	* Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
Kojto	90:cb3d968589d8	1262	* descriptors for an aborted transmit frame are not updated. The uDMA, buffer
Kojto	90:cb3d968589d8	1263	* descriptor, and FIFO control logic are reset, including the buffer descriptor and
Kojto	90:cb3d968589d8	1264	* FIFO pointers. Hardware clears this field under the following conditions: RESET
Kojto	90:cb3d968589d8	1265	* is set by software An error condition causes the EBERR field to set. ETHEREN
Kojto	90:cb3d968589d8	1266	* must be set at the very last step during ENET
Kojto	90:cb3d968589d8	1267	* configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
Kojto	90:cb3d968589d8	1268	* is cleared to 0 by software then then next time ETHEREN is set, the EIR
Kojto	90:cb3d968589d8	1269	* interrupts must cleared to 0 due to previous pending interrupts.
Kojto	90:cb3d968589d8	1270	*
Kojto	90:cb3d968589d8	1271	* Values:
Kojto	90:cb3d968589d8	1272	* - 0 - Reception immediately stops and transmission stops after a bad CRC is
Kojto	90:cb3d968589d8	1273	* appended to any currently transmitted frame.
Kojto	90:cb3d968589d8	1274	* - 1 - MAC is enabled, and reception and transmission are possible.
Kojto	90:cb3d968589d8	1275	*/
Kojto	90:cb3d968589d8	1276	/@{/
Kojto	90:cb3d968589d8	1277	#define BP_ENET_ECR_ETHEREN (1U) /!< Bit position for ENET_ECR_ETHEREN. /
Kojto	90:cb3d968589d8	1278	#define BM_ENET_ECR_ETHEREN (0x00000002U) /!< Bit mask for ENET_ECR_ETHEREN. /
Kojto	90:cb3d968589d8	1279	#define BS_ENET_ECR_ETHEREN (1U) /!< Bit field size in bits for ENET_ECR_ETHEREN. /
Kojto	90:cb3d968589d8	1280
Kojto	90:cb3d968589d8	1281	/! @brief Read current value of the ENET_ECR_ETHEREN field. /
Kojto	90:cb3d968589d8	1282	#define BR_ENET_ECR_ETHEREN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN))
Kojto	90:cb3d968589d8	1283
Kojto	90:cb3d968589d8	1284	/! @brief Format value for bitfield ENET_ECR_ETHEREN. /
Kojto	90:cb3d968589d8	1285	#define BF_ENET_ECR_ETHEREN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_ETHEREN) & BM_ENET_ECR_ETHEREN)
Kojto	90:cb3d968589d8	1286
Kojto	90:cb3d968589d8	1287	/! @brief Set the ETHEREN field to a new value. /
Kojto	90:cb3d968589d8	1288	#define BW_ENET_ECR_ETHEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN) = (v))
Kojto	90:cb3d968589d8	1289	/@}/
Kojto	90:cb3d968589d8	1290
Kojto	90:cb3d968589d8	1291	/*!
Kojto	90:cb3d968589d8	1292	* @name Register ENET_ECR, field MAGICEN[2] (RW)
Kojto	90:cb3d968589d8	1293	*
Kojto	90:cb3d968589d8	1294	* Enables/disables magic packet detection. MAGICEN is relevant only if the
Kojto	90:cb3d968589d8	1295	* SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
Kojto	90:cb3d968589d8	1296	* sleep mode and magic packet detection.
Kojto	90:cb3d968589d8	1297	*
Kojto	90:cb3d968589d8	1298	* Values:
Kojto	90:cb3d968589d8	1299	* - 0 - Magic detection logic disabled.
Kojto	90:cb3d968589d8	1300	* - 1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame
Kojto	90:cb3d968589d8	1301	* is detected.
Kojto	90:cb3d968589d8	1302	*/
Kojto	90:cb3d968589d8	1303	/@{/
Kojto	90:cb3d968589d8	1304	#define BP_ENET_ECR_MAGICEN (2U) /!< Bit position for ENET_ECR_MAGICEN. /
Kojto	90:cb3d968589d8	1305	#define BM_ENET_ECR_MAGICEN (0x00000004U) /!< Bit mask for ENET_ECR_MAGICEN. /
Kojto	90:cb3d968589d8	1306	#define BS_ENET_ECR_MAGICEN (1U) /!< Bit field size in bits for ENET_ECR_MAGICEN. /
Kojto	90:cb3d968589d8	1307
Kojto	90:cb3d968589d8	1308	/! @brief Read current value of the ENET_ECR_MAGICEN field. /
Kojto	90:cb3d968589d8	1309	#define BR_ENET_ECR_MAGICEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN))
Kojto	90:cb3d968589d8	1310
Kojto	90:cb3d968589d8	1311	/! @brief Format value for bitfield ENET_ECR_MAGICEN. /
Kojto	90:cb3d968589d8	1312	#define BF_ENET_ECR_MAGICEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_MAGICEN) & BM_ENET_ECR_MAGICEN)
Kojto	90:cb3d968589d8	1313
Kojto	90:cb3d968589d8	1314	/! @brief Set the MAGICEN field to a new value. /
Kojto	90:cb3d968589d8	1315	#define BW_ENET_ECR_MAGICEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN) = (v))
Kojto	90:cb3d968589d8	1316	/@}/
Kojto	90:cb3d968589d8	1317
Kojto	90:cb3d968589d8	1318	/*!
Kojto	90:cb3d968589d8	1319	* @name Register ENET_ECR, field SLEEP[3] (RW)
Kojto	90:cb3d968589d8	1320	*
Kojto	90:cb3d968589d8	1321	* Values:
Kojto	90:cb3d968589d8	1322	* - 0 - Normal operating mode.
Kojto	90:cb3d968589d8	1323	* - 1 - Sleep mode.
Kojto	90:cb3d968589d8	1324	*/
Kojto	90:cb3d968589d8	1325	/@{/
Kojto	90:cb3d968589d8	1326	#define BP_ENET_ECR_SLEEP (3U) /!< Bit position for ENET_ECR_SLEEP. /
Kojto	90:cb3d968589d8	1327	#define BM_ENET_ECR_SLEEP (0x00000008U) /!< Bit mask for ENET_ECR_SLEEP. /
Kojto	90:cb3d968589d8	1328	#define BS_ENET_ECR_SLEEP (1U) /!< Bit field size in bits for ENET_ECR_SLEEP. /
Kojto	90:cb3d968589d8	1329
Kojto	90:cb3d968589d8	1330	/! @brief Read current value of the ENET_ECR_SLEEP field. /
Kojto	90:cb3d968589d8	1331	#define BR_ENET_ECR_SLEEP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP))
Kojto	90:cb3d968589d8	1332
Kojto	90:cb3d968589d8	1333	/! @brief Format value for bitfield ENET_ECR_SLEEP. /
Kojto	90:cb3d968589d8	1334	#define BF_ENET_ECR_SLEEP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_SLEEP) & BM_ENET_ECR_SLEEP)
Kojto	90:cb3d968589d8	1335
Kojto	90:cb3d968589d8	1336	/! @brief Set the SLEEP field to a new value. /
Kojto	90:cb3d968589d8	1337	#define BW_ENET_ECR_SLEEP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP) = (v))
Kojto	90:cb3d968589d8	1338	/@}/
Kojto	90:cb3d968589d8	1339
Kojto	90:cb3d968589d8	1340	/*!
Kojto	90:cb3d968589d8	1341	* @name Register ENET_ECR, field EN1588[4] (RW)
Kojto	90:cb3d968589d8	1342	*
Kojto	90:cb3d968589d8	1343	* Enables enhanced functionality of the MAC.
Kojto	90:cb3d968589d8	1344	*
Kojto	90:cb3d968589d8	1345	* Values:
Kojto	90:cb3d968589d8	1346	* - 0 - Legacy FEC buffer descriptors and functions enabled.
Kojto	90:cb3d968589d8	1347	* - 1 - Enhanced frame time-stamping functions enabled.
Kojto	90:cb3d968589d8	1348	*/
Kojto	90:cb3d968589d8	1349	/@{/
Kojto	90:cb3d968589d8	1350	#define BP_ENET_ECR_EN1588 (4U) /!< Bit position for ENET_ECR_EN1588. /
Kojto	90:cb3d968589d8	1351	#define BM_ENET_ECR_EN1588 (0x00000010U) /!< Bit mask for ENET_ECR_EN1588. /
Kojto	90:cb3d968589d8	1352	#define BS_ENET_ECR_EN1588 (1U) /!< Bit field size in bits for ENET_ECR_EN1588. /
Kojto	90:cb3d968589d8	1353
Kojto	90:cb3d968589d8	1354	/! @brief Read current value of the ENET_ECR_EN1588 field. /
Kojto	90:cb3d968589d8	1355	#define BR_ENET_ECR_EN1588(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588))
Kojto	90:cb3d968589d8	1356
Kojto	90:cb3d968589d8	1357	/! @brief Format value for bitfield ENET_ECR_EN1588. /
Kojto	90:cb3d968589d8	1358	#define BF_ENET_ECR_EN1588(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_EN1588) & BM_ENET_ECR_EN1588)
Kojto	90:cb3d968589d8	1359
Kojto	90:cb3d968589d8	1360	/! @brief Set the EN1588 field to a new value. /
Kojto	90:cb3d968589d8	1361	#define BW_ENET_ECR_EN1588(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588) = (v))
Kojto	90:cb3d968589d8	1362	/@}/
Kojto	90:cb3d968589d8	1363
Kojto	90:cb3d968589d8	1364	/*!
Kojto	90:cb3d968589d8	1365	* @name Register ENET_ECR, field DBGEN[6] (RW)
Kojto	90:cb3d968589d8	1366	*
Kojto	90:cb3d968589d8	1367	* Enables the MAC to enter hardware freeze mode when the device enters debug
Kojto	90:cb3d968589d8	1368	* mode.
Kojto	90:cb3d968589d8	1369	*
Kojto	90:cb3d968589d8	1370	* Values:
Kojto	90:cb3d968589d8	1371	* - 0 - MAC continues operation in debug mode.
Kojto	90:cb3d968589d8	1372	* - 1 - MAC enters hardware freeze mode when the processor is in debug mode.
Kojto	90:cb3d968589d8	1373	*/
Kojto	90:cb3d968589d8	1374	/@{/
Kojto	90:cb3d968589d8	1375	#define BP_ENET_ECR_DBGEN (6U) /!< Bit position for ENET_ECR_DBGEN. /
Kojto	90:cb3d968589d8	1376	#define BM_ENET_ECR_DBGEN (0x00000040U) /!< Bit mask for ENET_ECR_DBGEN. /
Kojto	90:cb3d968589d8	1377	#define BS_ENET_ECR_DBGEN (1U) /!< Bit field size in bits for ENET_ECR_DBGEN. /
Kojto	90:cb3d968589d8	1378
Kojto	90:cb3d968589d8	1379	/! @brief Read current value of the ENET_ECR_DBGEN field. /
Kojto	90:cb3d968589d8	1380	#define BR_ENET_ECR_DBGEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN))
Kojto	90:cb3d968589d8	1381
Kojto	90:cb3d968589d8	1382	/! @brief Format value for bitfield ENET_ECR_DBGEN. /
Kojto	90:cb3d968589d8	1383	#define BF_ENET_ECR_DBGEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_DBGEN) & BM_ENET_ECR_DBGEN)
Kojto	90:cb3d968589d8	1384
Kojto	90:cb3d968589d8	1385	/! @brief Set the DBGEN field to a new value. /
Kojto	90:cb3d968589d8	1386	#define BW_ENET_ECR_DBGEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN) = (v))
Kojto	90:cb3d968589d8	1387	/@}/
Kojto	90:cb3d968589d8	1388
Kojto	90:cb3d968589d8	1389	/*!
Kojto	90:cb3d968589d8	1390	* @name Register ENET_ECR, field STOPEN[7] (RW)
Kojto	90:cb3d968589d8	1391	*
Kojto	90:cb3d968589d8	1392	* Controls device behavior in doze mode. In doze mode, if this field is set
Kojto	90:cb3d968589d8	1393	* then all the clocks of the ENET assembly are disabled, except the RMII /MII
Kojto	90:cb3d968589d8	1394	* clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
Kojto	90:cb3d968589d8	1395	* depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
Kojto	90:cb3d968589d8	1396	* can still wake the system after receiving a magic packet in stop mode. MAGICEN
Kojto	90:cb3d968589d8	1397	* must be set prior to entering sleep/stop mode.
Kojto	90:cb3d968589d8	1398	*/
Kojto	90:cb3d968589d8	1399	/@{/
Kojto	90:cb3d968589d8	1400	#define BP_ENET_ECR_STOPEN (7U) /!< Bit position for ENET_ECR_STOPEN. /
Kojto	90:cb3d968589d8	1401	#define BM_ENET_ECR_STOPEN (0x00000080U) /!< Bit mask for ENET_ECR_STOPEN. /
Kojto	90:cb3d968589d8	1402	#define BS_ENET_ECR_STOPEN (1U) /!< Bit field size in bits for ENET_ECR_STOPEN. /
Kojto	90:cb3d968589d8	1403
Kojto	90:cb3d968589d8	1404	/! @brief Read current value of the ENET_ECR_STOPEN field. /
Kojto	90:cb3d968589d8	1405	#define BR_ENET_ECR_STOPEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN))
Kojto	90:cb3d968589d8	1406
Kojto	90:cb3d968589d8	1407	/! @brief Format value for bitfield ENET_ECR_STOPEN. /
Kojto	90:cb3d968589d8	1408	#define BF_ENET_ECR_STOPEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_STOPEN) & BM_ENET_ECR_STOPEN)
Kojto	90:cb3d968589d8	1409
Kojto	90:cb3d968589d8	1410	/! @brief Set the STOPEN field to a new value. /
Kojto	90:cb3d968589d8	1411	#define BW_ENET_ECR_STOPEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN) = (v))
Kojto	90:cb3d968589d8	1412	/@}/
Kojto	90:cb3d968589d8	1413
Kojto	90:cb3d968589d8	1414	/*!
Kojto	90:cb3d968589d8	1415	* @name Register ENET_ECR, field DBSWP[8] (RW)
Kojto	90:cb3d968589d8	1416	*
Kojto	90:cb3d968589d8	1417	* Swaps the byte locations of the buffer descriptors. This field must be
Kojto	90:cb3d968589d8	1418	* written to 1 after reset.
Kojto	90:cb3d968589d8	1419	*
Kojto	90:cb3d968589d8	1420	* Values:
Kojto	90:cb3d968589d8	1421	* - 0 - The buffer descriptor bytes are not swapped to support big-endian
Kojto	90:cb3d968589d8	1422	* devices.
Kojto	90:cb3d968589d8	1423	* - 1 - The buffer descriptor bytes are swapped to support little-endian
Kojto	90:cb3d968589d8	1424	* devices.
Kojto	90:cb3d968589d8	1425	*/
Kojto	90:cb3d968589d8	1426	/@{/
Kojto	90:cb3d968589d8	1427	#define BP_ENET_ECR_DBSWP (8U) /!< Bit position for ENET_ECR_DBSWP. /
Kojto	90:cb3d968589d8	1428	#define BM_ENET_ECR_DBSWP (0x00000100U) /!< Bit mask for ENET_ECR_DBSWP. /
Kojto	90:cb3d968589d8	1429	#define BS_ENET_ECR_DBSWP (1U) /!< Bit field size in bits for ENET_ECR_DBSWP. /
Kojto	90:cb3d968589d8	1430
Kojto	90:cb3d968589d8	1431	/! @brief Read current value of the ENET_ECR_DBSWP field. /
Kojto	90:cb3d968589d8	1432	#define BR_ENET_ECR_DBSWP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP))
Kojto	90:cb3d968589d8	1433
Kojto	90:cb3d968589d8	1434	/! @brief Format value for bitfield ENET_ECR_DBSWP. /
Kojto	90:cb3d968589d8	1435	#define BF_ENET_ECR_DBSWP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_DBSWP) & BM_ENET_ECR_DBSWP)
Kojto	90:cb3d968589d8	1436
Kojto	90:cb3d968589d8	1437	/! @brief Set the DBSWP field to a new value. /
Kojto	90:cb3d968589d8	1438	#define BW_ENET_ECR_DBSWP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP) = (v))
Kojto	90:cb3d968589d8	1439	/@}/
Kojto	90:cb3d968589d8	1440
Kojto	90:cb3d968589d8	1441	/*******************************************************************************
Kojto	90:cb3d968589d8	1442	* HW_ENET_MMFR - MII Management Frame Register
Kojto	90:cb3d968589d8	1443	******************************************************************************/
Kojto	90:cb3d968589d8	1444
Kojto	90:cb3d968589d8	1445	/*!
Kojto	90:cb3d968589d8	1446	* @brief HW_ENET_MMFR - MII Management Frame Register (RW)
Kojto	90:cb3d968589d8	1447	*
Kojto	90:cb3d968589d8	1448	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1449	*
Kojto	90:cb3d968589d8	1450	* Writing to MMFR triggers a management frame transaction to the PHY device
Kojto	90:cb3d968589d8	1451	* unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
Kojto	90:cb3d968589d8	1452	* during a write to MMFR, an MII frame is generated with the data previously written
Kojto	90:cb3d968589d8	1453	* to the MMFR. This allows MMFR and MSCR to be programmed in either order if
Kojto	90:cb3d968589d8	1454	* MSCR is currently zero. If the MMFR register is written while frame generation is
Kojto	90:cb3d968589d8	1455	* in progress, the frame contents are altered. Software must use the EIR[MII]
Kojto	90:cb3d968589d8	1456	* interrupt indication to avoid writing to the MMFR register while frame
Kojto	90:cb3d968589d8	1457	* generation is in progress.
Kojto	90:cb3d968589d8	1458	*/
Kojto	90:cb3d968589d8	1459	typedef union _hw_enet_mmfr
Kojto	90:cb3d968589d8	1460	{
Kojto	90:cb3d968589d8	1461	uint32_t U;
Kojto	90:cb3d968589d8	1462	struct _hw_enet_mmfr_bitfields
Kojto	90:cb3d968589d8	1463	{
Kojto	90:cb3d968589d8	1464	uint32_t DATA : 16; /!< [15:0] Management Frame Data /
Kojto	90:cb3d968589d8	1465	uint32_t TA : 2; /!< [17:16] Turn Around /
Kojto	90:cb3d968589d8	1466	uint32_t RA : 5; /!< [22:18] Register Address /
Kojto	90:cb3d968589d8	1467	uint32_t PA : 5; /!< [27:23] PHY Address /
Kojto	90:cb3d968589d8	1468	uint32_t OP : 2; /!< [29:28] Operation Code /
Kojto	90:cb3d968589d8	1469	uint32_t ST : 2; /!< [31:30] Start Of Frame Delimiter /
Kojto	90:cb3d968589d8	1470	} B;
Kojto	90:cb3d968589d8	1471	} hw_enet_mmfr_t;
Kojto	90:cb3d968589d8	1472
Kojto	90:cb3d968589d8	1473	/*!
Kojto	90:cb3d968589d8	1474	* @name Constants and macros for entire ENET_MMFR register
Kojto	90:cb3d968589d8	1475	*/
Kojto	90:cb3d968589d8	1476	/@{/
Kojto	90:cb3d968589d8	1477	#define HW_ENET_MMFR_ADDR(x) ((x) + 0x40U)
Kojto	90:cb3d968589d8	1478
Kojto	90:cb3d968589d8	1479	#define HW_ENET_MMFR(x) ((__IO hw_enet_mmfr_t ) HW_ENET_MMFR_ADDR(x))
Kojto	90:cb3d968589d8	1480	#define HW_ENET_MMFR_RD(x) (HW_ENET_MMFR(x).U)
Kojto	90:cb3d968589d8	1481	#define HW_ENET_MMFR_WR(x, v) (HW_ENET_MMFR(x).U = (v))
Kojto	90:cb3d968589d8	1482	#define HW_ENET_MMFR_SET(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1483	#define HW_ENET_MMFR_CLR(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1484	#define HW_ENET_MMFR_TOG(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1485	/@}/
Kojto	90:cb3d968589d8	1486
Kojto	90:cb3d968589d8	1487	/*
Kojto	90:cb3d968589d8	1488	* Constants & macros for individual ENET_MMFR bitfields
Kojto	90:cb3d968589d8	1489	*/
Kojto	90:cb3d968589d8	1490
Kojto	90:cb3d968589d8	1491	/*!
Kojto	90:cb3d968589d8	1492	* @name Register ENET_MMFR, field DATA[15:0] (RW)
Kojto	90:cb3d968589d8	1493	*
Kojto	90:cb3d968589d8	1494	* This is the field for data to be written to or read from the PHY register.
Kojto	90:cb3d968589d8	1495	*/
Kojto	90:cb3d968589d8	1496	/@{/
Kojto	90:cb3d968589d8	1497	#define BP_ENET_MMFR_DATA (0U) /!< Bit position for ENET_MMFR_DATA. /
Kojto	90:cb3d968589d8	1498	#define BM_ENET_MMFR_DATA (0x0000FFFFU) /!< Bit mask for ENET_MMFR_DATA. /
Kojto	90:cb3d968589d8	1499	#define BS_ENET_MMFR_DATA (16U) /!< Bit field size in bits for ENET_MMFR_DATA. /
Kojto	90:cb3d968589d8	1500
Kojto	90:cb3d968589d8	1501	/! @brief Read current value of the ENET_MMFR_DATA field. /
Kojto	90:cb3d968589d8	1502	#define BR_ENET_MMFR_DATA(x) (HW_ENET_MMFR(x).B.DATA)
Kojto	90:cb3d968589d8	1503
Kojto	90:cb3d968589d8	1504	/! @brief Format value for bitfield ENET_MMFR_DATA. /
Kojto	90:cb3d968589d8	1505	#define BF_ENET_MMFR_DATA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_DATA) & BM_ENET_MMFR_DATA)
Kojto	90:cb3d968589d8	1506
Kojto	90:cb3d968589d8	1507	/! @brief Set the DATA field to a new value. /
Kojto	90:cb3d968589d8	1508	#define BW_ENET_MMFR_DATA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_DATA) \| BF_ENET_MMFR_DATA(v)))
Kojto	90:cb3d968589d8	1509	/@}/
Kojto	90:cb3d968589d8	1510
Kojto	90:cb3d968589d8	1511	/*!
Kojto	90:cb3d968589d8	1512	* @name Register ENET_MMFR, field TA[17:16] (RW)
Kojto	90:cb3d968589d8	1513	*
Kojto	90:cb3d968589d8	1514	* This field must be programmed to 10 to generate a valid MII management frame.
Kojto	90:cb3d968589d8	1515	*/
Kojto	90:cb3d968589d8	1516	/@{/
Kojto	90:cb3d968589d8	1517	#define BP_ENET_MMFR_TA (16U) /!< Bit position for ENET_MMFR_TA. /
Kojto	90:cb3d968589d8	1518	#define BM_ENET_MMFR_TA (0x00030000U) /!< Bit mask for ENET_MMFR_TA. /
Kojto	90:cb3d968589d8	1519	#define BS_ENET_MMFR_TA (2U) /!< Bit field size in bits for ENET_MMFR_TA. /
Kojto	90:cb3d968589d8	1520
Kojto	90:cb3d968589d8	1521	/! @brief Read current value of the ENET_MMFR_TA field. /
Kojto	90:cb3d968589d8	1522	#define BR_ENET_MMFR_TA(x) (HW_ENET_MMFR(x).B.TA)
Kojto	90:cb3d968589d8	1523
Kojto	90:cb3d968589d8	1524	/! @brief Format value for bitfield ENET_MMFR_TA. /
Kojto	90:cb3d968589d8	1525	#define BF_ENET_MMFR_TA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_TA) & BM_ENET_MMFR_TA)
Kojto	90:cb3d968589d8	1526
Kojto	90:cb3d968589d8	1527	/! @brief Set the TA field to a new value. /
Kojto	90:cb3d968589d8	1528	#define BW_ENET_MMFR_TA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_TA) \| BF_ENET_MMFR_TA(v)))
Kojto	90:cb3d968589d8	1529	/@}/
Kojto	90:cb3d968589d8	1530
Kojto	90:cb3d968589d8	1531	/*!
Kojto	90:cb3d968589d8	1532	* @name Register ENET_MMFR, field RA[22:18] (RW)
Kojto	90:cb3d968589d8	1533	*
Kojto	90:cb3d968589d8	1534	* Specifies one of up to 32 registers within the specified PHY device.
Kojto	90:cb3d968589d8	1535	*/
Kojto	90:cb3d968589d8	1536	/@{/
Kojto	90:cb3d968589d8	1537	#define BP_ENET_MMFR_RA (18U) /!< Bit position for ENET_MMFR_RA. /
Kojto	90:cb3d968589d8	1538	#define BM_ENET_MMFR_RA (0x007C0000U) /!< Bit mask for ENET_MMFR_RA. /
Kojto	90:cb3d968589d8	1539	#define BS_ENET_MMFR_RA (5U) /!< Bit field size in bits for ENET_MMFR_RA. /
Kojto	90:cb3d968589d8	1540
Kojto	90:cb3d968589d8	1541	/! @brief Read current value of the ENET_MMFR_RA field. /
Kojto	90:cb3d968589d8	1542	#define BR_ENET_MMFR_RA(x) (HW_ENET_MMFR(x).B.RA)
Kojto	90:cb3d968589d8	1543
Kojto	90:cb3d968589d8	1544	/! @brief Format value for bitfield ENET_MMFR_RA. /
Kojto	90:cb3d968589d8	1545	#define BF_ENET_MMFR_RA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_RA) & BM_ENET_MMFR_RA)
Kojto	90:cb3d968589d8	1546
Kojto	90:cb3d968589d8	1547	/! @brief Set the RA field to a new value. /
Kojto	90:cb3d968589d8	1548	#define BW_ENET_MMFR_RA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_RA) \| BF_ENET_MMFR_RA(v)))
Kojto	90:cb3d968589d8	1549	/@}/
Kojto	90:cb3d968589d8	1550
Kojto	90:cb3d968589d8	1551	/*!
Kojto	90:cb3d968589d8	1552	* @name Register ENET_MMFR, field PA[27:23] (RW)
Kojto	90:cb3d968589d8	1553	*
Kojto	90:cb3d968589d8	1554	* Specifies one of up to 32 attached PHY devices.
Kojto	90:cb3d968589d8	1555	*/
Kojto	90:cb3d968589d8	1556	/@{/
Kojto	90:cb3d968589d8	1557	#define BP_ENET_MMFR_PA (23U) /!< Bit position for ENET_MMFR_PA. /
Kojto	90:cb3d968589d8	1558	#define BM_ENET_MMFR_PA (0x0F800000U) /!< Bit mask for ENET_MMFR_PA. /
Kojto	90:cb3d968589d8	1559	#define BS_ENET_MMFR_PA (5U) /!< Bit field size in bits for ENET_MMFR_PA. /
Kojto	90:cb3d968589d8	1560
Kojto	90:cb3d968589d8	1561	/! @brief Read current value of the ENET_MMFR_PA field. /
Kojto	90:cb3d968589d8	1562	#define BR_ENET_MMFR_PA(x) (HW_ENET_MMFR(x).B.PA)
Kojto	90:cb3d968589d8	1563
Kojto	90:cb3d968589d8	1564	/! @brief Format value for bitfield ENET_MMFR_PA. /
Kojto	90:cb3d968589d8	1565	#define BF_ENET_MMFR_PA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_PA) & BM_ENET_MMFR_PA)
Kojto	90:cb3d968589d8	1566
Kojto	90:cb3d968589d8	1567	/! @brief Set the PA field to a new value. /
Kojto	90:cb3d968589d8	1568	#define BW_ENET_MMFR_PA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_PA) \| BF_ENET_MMFR_PA(v)))
Kojto	90:cb3d968589d8	1569	/@}/
Kojto	90:cb3d968589d8	1570
Kojto	90:cb3d968589d8	1571	/*!
Kojto	90:cb3d968589d8	1572	* @name Register ENET_MMFR, field OP[29:28] (RW)
Kojto	90:cb3d968589d8	1573	*
Kojto	90:cb3d968589d8	1574	* Determines the frame operation.
Kojto	90:cb3d968589d8	1575	*
Kojto	90:cb3d968589d8	1576	* Values:
Kojto	90:cb3d968589d8	1577	* - 00 - Write frame operation, but not MII compliant.
Kojto	90:cb3d968589d8	1578	* - 01 - Write frame operation for a valid MII management frame.
Kojto	90:cb3d968589d8	1579	* - 10 - Read frame operation for a valid MII management frame.
Kojto	90:cb3d968589d8	1580	* - 11 - Read frame operation, but not MII compliant.
Kojto	90:cb3d968589d8	1581	*/
Kojto	90:cb3d968589d8	1582	/@{/
Kojto	90:cb3d968589d8	1583	#define BP_ENET_MMFR_OP (28U) /!< Bit position for ENET_MMFR_OP. /
Kojto	90:cb3d968589d8	1584	#define BM_ENET_MMFR_OP (0x30000000U) /!< Bit mask for ENET_MMFR_OP. /
Kojto	90:cb3d968589d8	1585	#define BS_ENET_MMFR_OP (2U) /!< Bit field size in bits for ENET_MMFR_OP. /
Kojto	90:cb3d968589d8	1586
Kojto	90:cb3d968589d8	1587	/! @brief Read current value of the ENET_MMFR_OP field. /
Kojto	90:cb3d968589d8	1588	#define BR_ENET_MMFR_OP(x) (HW_ENET_MMFR(x).B.OP)
Kojto	90:cb3d968589d8	1589
Kojto	90:cb3d968589d8	1590	/! @brief Format value for bitfield ENET_MMFR_OP. /
Kojto	90:cb3d968589d8	1591	#define BF_ENET_MMFR_OP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_OP) & BM_ENET_MMFR_OP)
Kojto	90:cb3d968589d8	1592
Kojto	90:cb3d968589d8	1593	/! @brief Set the OP field to a new value. /
Kojto	90:cb3d968589d8	1594	#define BW_ENET_MMFR_OP(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_OP) \| BF_ENET_MMFR_OP(v)))
Kojto	90:cb3d968589d8	1595	/@}/
Kojto	90:cb3d968589d8	1596
Kojto	90:cb3d968589d8	1597	/*!
Kojto	90:cb3d968589d8	1598	* @name Register ENET_MMFR, field ST[31:30] (RW)
Kojto	90:cb3d968589d8	1599	*
Kojto	90:cb3d968589d8	1600	* These fields must be programmed to 01 for a valid MII management frame.
Kojto	90:cb3d968589d8	1601	*/
Kojto	90:cb3d968589d8	1602	/@{/
Kojto	90:cb3d968589d8	1603	#define BP_ENET_MMFR_ST (30U) /!< Bit position for ENET_MMFR_ST. /
Kojto	90:cb3d968589d8	1604	#define BM_ENET_MMFR_ST (0xC0000000U) /!< Bit mask for ENET_MMFR_ST. /
Kojto	90:cb3d968589d8	1605	#define BS_ENET_MMFR_ST (2U) /!< Bit field size in bits for ENET_MMFR_ST. /
Kojto	90:cb3d968589d8	1606
Kojto	90:cb3d968589d8	1607	/! @brief Read current value of the ENET_MMFR_ST field. /
Kojto	90:cb3d968589d8	1608	#define BR_ENET_MMFR_ST(x) (HW_ENET_MMFR(x).B.ST)
Kojto	90:cb3d968589d8	1609
Kojto	90:cb3d968589d8	1610	/! @brief Format value for bitfield ENET_MMFR_ST. /
Kojto	90:cb3d968589d8	1611	#define BF_ENET_MMFR_ST(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_ST) & BM_ENET_MMFR_ST)
Kojto	90:cb3d968589d8	1612
Kojto	90:cb3d968589d8	1613	/! @brief Set the ST field to a new value. /
Kojto	90:cb3d968589d8	1614	#define BW_ENET_MMFR_ST(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_ST) \| BF_ENET_MMFR_ST(v)))
Kojto	90:cb3d968589d8	1615	/@}/
Kojto	90:cb3d968589d8	1616
Kojto	90:cb3d968589d8	1617	/*******************************************************************************
Kojto	90:cb3d968589d8	1618	* HW_ENET_MSCR - MII Speed Control Register
Kojto	90:cb3d968589d8	1619	******************************************************************************/
Kojto	90:cb3d968589d8	1620
Kojto	90:cb3d968589d8	1621	/*!
Kojto	90:cb3d968589d8	1622	* @brief HW_ENET_MSCR - MII Speed Control Register (RW)
Kojto	90:cb3d968589d8	1623	*
Kojto	90:cb3d968589d8	1624	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1625	*
Kojto	90:cb3d968589d8	1626	* MSCR provides control of the MII clock (MDC pin) frequency and allows a
Kojto	90:cb3d968589d8	1627	* preamble drop on the MII management frame. The MII_SPEED field must be programmed
Kojto	90:cb3d968589d8	1628	* with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
Kojto	90:cb3d968589d8	1629	* compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
Kojto	90:cb3d968589d8	1630	* a non-zero value to source a read or write management frame. After the
Kojto	90:cb3d968589d8	1631	* management frame is complete, the MSCR register may optionally be cleared to turn
Kojto	90:cb3d968589d8	1632	* off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
Kojto	90:cb3d968589d8	1633	* changes during operation. This change takes effect following a rising or falling
Kojto	90:cb3d968589d8	1634	* edge of MDC. If the internal module clock is 25 MHz, programming this register
Kojto	90:cb3d968589d8	1635	* to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
Kojto	90:cb3d968589d8	1636	* / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
Kojto	90:cb3d968589d8	1637	* MII_SPEED as a function of internal module clock frequency. Programming Examples
Kojto	90:cb3d968589d8	1638	* for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
Kojto	90:cb3d968589d8	1639	* 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
Kojto	90:cb3d968589d8	1640	* 0xD 2.36 MHz
Kojto	90:cb3d968589d8	1641	*/
Kojto	90:cb3d968589d8	1642	typedef union _hw_enet_mscr
Kojto	90:cb3d968589d8	1643	{
Kojto	90:cb3d968589d8	1644	uint32_t U;
Kojto	90:cb3d968589d8	1645	struct _hw_enet_mscr_bitfields
Kojto	90:cb3d968589d8	1646	{
Kojto	90:cb3d968589d8	1647	uint32_t RESERVED0 : 1; /!< [0] /
Kojto	90:cb3d968589d8	1648	uint32_t MII_SPEED : 6; /!< [6:1] MII Speed /
Kojto	90:cb3d968589d8	1649	uint32_t DIS_PRE : 1; /!< [7] Disable Preamble /
Kojto	90:cb3d968589d8	1650	uint32_t HOLDTIME : 3; /!< [10:8] Hold time On MDIO Output /
Kojto	90:cb3d968589d8	1651	uint32_t RESERVED1 : 21; /!< [31:11] /
Kojto	90:cb3d968589d8	1652	} B;
Kojto	90:cb3d968589d8	1653	} hw_enet_mscr_t;
Kojto	90:cb3d968589d8	1654
Kojto	90:cb3d968589d8	1655	/*!
Kojto	90:cb3d968589d8	1656	* @name Constants and macros for entire ENET_MSCR register
Kojto	90:cb3d968589d8	1657	*/
Kojto	90:cb3d968589d8	1658	/@{/
Kojto	90:cb3d968589d8	1659	#define HW_ENET_MSCR_ADDR(x) ((x) + 0x44U)
Kojto	90:cb3d968589d8	1660
Kojto	90:cb3d968589d8	1661	#define HW_ENET_MSCR(x) ((__IO hw_enet_mscr_t ) HW_ENET_MSCR_ADDR(x))
Kojto	90:cb3d968589d8	1662	#define HW_ENET_MSCR_RD(x) (HW_ENET_MSCR(x).U)
Kojto	90:cb3d968589d8	1663	#define HW_ENET_MSCR_WR(x, v) (HW_ENET_MSCR(x).U = (v))
Kojto	90:cb3d968589d8	1664	#define HW_ENET_MSCR_SET(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1665	#define HW_ENET_MSCR_CLR(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1666	#define HW_ENET_MSCR_TOG(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1667	/@}/
Kojto	90:cb3d968589d8	1668
Kojto	90:cb3d968589d8	1669	/*
Kojto	90:cb3d968589d8	1670	* Constants & macros for individual ENET_MSCR bitfields
Kojto	90:cb3d968589d8	1671	*/
Kojto	90:cb3d968589d8	1672
Kojto	90:cb3d968589d8	1673	/*!
Kojto	90:cb3d968589d8	1674	* @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
Kojto	90:cb3d968589d8	1675	*
Kojto	90:cb3d968589d8	1676	* Controls the frequency of the MII management interface clock (MDC) relative
Kojto	90:cb3d968589d8	1677	* to the internal module clock. A value of 0 in this field turns off MDC and
Kojto	90:cb3d968589d8	1678	* leaves it in low voltage state. Any non-zero value results in the MDC frequency
Kojto	90:cb3d968589d8	1679	* of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
Kojto	90:cb3d968589d8	1680	*/
Kojto	90:cb3d968589d8	1681	/@{/
Kojto	90:cb3d968589d8	1682	#define BP_ENET_MSCR_MII_SPEED (1U) /!< Bit position for ENET_MSCR_MII_SPEED. /
Kojto	90:cb3d968589d8	1683	#define BM_ENET_MSCR_MII_SPEED (0x0000007EU) /!< Bit mask for ENET_MSCR_MII_SPEED. /
Kojto	90:cb3d968589d8	1684	#define BS_ENET_MSCR_MII_SPEED (6U) /!< Bit field size in bits for ENET_MSCR_MII_SPEED. /
Kojto	90:cb3d968589d8	1685
Kojto	90:cb3d968589d8	1686	/! @brief Read current value of the ENET_MSCR_MII_SPEED field. /
Kojto	90:cb3d968589d8	1687	#define BR_ENET_MSCR_MII_SPEED(x) (HW_ENET_MSCR(x).B.MII_SPEED)
Kojto	90:cb3d968589d8	1688
Kojto	90:cb3d968589d8	1689	/! @brief Format value for bitfield ENET_MSCR_MII_SPEED. /
Kojto	90:cb3d968589d8	1690	#define BF_ENET_MSCR_MII_SPEED(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_MII_SPEED) & BM_ENET_MSCR_MII_SPEED)
Kojto	90:cb3d968589d8	1691
Kojto	90:cb3d968589d8	1692	/! @brief Set the MII_SPEED field to a new value. /
Kojto	90:cb3d968589d8	1693	#define BW_ENET_MSCR_MII_SPEED(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_MII_SPEED) \| BF_ENET_MSCR_MII_SPEED(v)))
Kojto	90:cb3d968589d8	1694	/@}/
Kojto	90:cb3d968589d8	1695
Kojto	90:cb3d968589d8	1696	/*!
Kojto	90:cb3d968589d8	1697	* @name Register ENET_MSCR, field DIS_PRE[7] (RW)
Kojto	90:cb3d968589d8	1698	*
Kojto	90:cb3d968589d8	1699	* Enables/disables prepending a preamble to the MII management frame. The MII
Kojto	90:cb3d968589d8	1700	* standard allows the preamble to be dropped if the attached PHY devices do not
Kojto	90:cb3d968589d8	1701	* require it.
Kojto	90:cb3d968589d8	1702	*
Kojto	90:cb3d968589d8	1703	* Values:
Kojto	90:cb3d968589d8	1704	* - 0 - Preamble enabled.
Kojto	90:cb3d968589d8	1705	* - 1 - Preamble (32 ones) is not prepended to the MII management frame.
Kojto	90:cb3d968589d8	1706	*/
Kojto	90:cb3d968589d8	1707	/@{/
Kojto	90:cb3d968589d8	1708	#define BP_ENET_MSCR_DIS_PRE (7U) /!< Bit position for ENET_MSCR_DIS_PRE. /
Kojto	90:cb3d968589d8	1709	#define BM_ENET_MSCR_DIS_PRE (0x00000080U) /!< Bit mask for ENET_MSCR_DIS_PRE. /
Kojto	90:cb3d968589d8	1710	#define BS_ENET_MSCR_DIS_PRE (1U) /!< Bit field size in bits for ENET_MSCR_DIS_PRE. /
Kojto	90:cb3d968589d8	1711
Kojto	90:cb3d968589d8	1712	/! @brief Read current value of the ENET_MSCR_DIS_PRE field. /
Kojto	90:cb3d968589d8	1713	#define BR_ENET_MSCR_DIS_PRE(x) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE))
Kojto	90:cb3d968589d8	1714
Kojto	90:cb3d968589d8	1715	/! @brief Format value for bitfield ENET_MSCR_DIS_PRE. /
Kojto	90:cb3d968589d8	1716	#define BF_ENET_MSCR_DIS_PRE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_DIS_PRE) & BM_ENET_MSCR_DIS_PRE)
Kojto	90:cb3d968589d8	1717
Kojto	90:cb3d968589d8	1718	/! @brief Set the DIS_PRE field to a new value. /
Kojto	90:cb3d968589d8	1719	#define BW_ENET_MSCR_DIS_PRE(x, v) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE) = (v))
Kojto	90:cb3d968589d8	1720	/@}/
Kojto	90:cb3d968589d8	1721
Kojto	90:cb3d968589d8	1722	/*!
Kojto	90:cb3d968589d8	1723	* @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
Kojto	90:cb3d968589d8	1724	*
Kojto	90:cb3d968589d8	1725	* IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
Kojto	90:cb3d968589d8	1726	* output. Depending on the host bus frequency, the setting may need to be
Kojto	90:cb3d968589d8	1727	* increased.
Kojto	90:cb3d968589d8	1728	*
Kojto	90:cb3d968589d8	1729	* Values:
Kojto	90:cb3d968589d8	1730	* - 000 - 1 internal module clock cycle
Kojto	90:cb3d968589d8	1731	* - 001 - 2 internal module clock cycles
Kojto	90:cb3d968589d8	1732	* - 010 - 3 internal module clock cycles
Kojto	90:cb3d968589d8	1733	* - 111 - 8 internal module clock cycles
Kojto	90:cb3d968589d8	1734	*/
Kojto	90:cb3d968589d8	1735	/@{/
Kojto	90:cb3d968589d8	1736	#define BP_ENET_MSCR_HOLDTIME (8U) /!< Bit position for ENET_MSCR_HOLDTIME. /
Kojto	90:cb3d968589d8	1737	#define BM_ENET_MSCR_HOLDTIME (0x00000700U) /!< Bit mask for ENET_MSCR_HOLDTIME. /
Kojto	90:cb3d968589d8	1738	#define BS_ENET_MSCR_HOLDTIME (3U) /!< Bit field size in bits for ENET_MSCR_HOLDTIME. /
Kojto	90:cb3d968589d8	1739
Kojto	90:cb3d968589d8	1740	/! @brief Read current value of the ENET_MSCR_HOLDTIME field. /
Kojto	90:cb3d968589d8	1741	#define BR_ENET_MSCR_HOLDTIME(x) (HW_ENET_MSCR(x).B.HOLDTIME)
Kojto	90:cb3d968589d8	1742
Kojto	90:cb3d968589d8	1743	/! @brief Format value for bitfield ENET_MSCR_HOLDTIME. /
Kojto	90:cb3d968589d8	1744	#define BF_ENET_MSCR_HOLDTIME(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_HOLDTIME) & BM_ENET_MSCR_HOLDTIME)
Kojto	90:cb3d968589d8	1745
Kojto	90:cb3d968589d8	1746	/! @brief Set the HOLDTIME field to a new value. /
Kojto	90:cb3d968589d8	1747	#define BW_ENET_MSCR_HOLDTIME(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_HOLDTIME) \| BF_ENET_MSCR_HOLDTIME(v)))
Kojto	90:cb3d968589d8	1748	/@}/
Kojto	90:cb3d968589d8	1749
Kojto	90:cb3d968589d8	1750	/*******************************************************************************
Kojto	90:cb3d968589d8	1751	* HW_ENET_MIBC - MIB Control Register
Kojto	90:cb3d968589d8	1752	******************************************************************************/
Kojto	90:cb3d968589d8	1753
Kojto	90:cb3d968589d8	1754	/*!
Kojto	90:cb3d968589d8	1755	* @brief HW_ENET_MIBC - MIB Control Register (RW)
Kojto	90:cb3d968589d8	1756	*
Kojto	90:cb3d968589d8	1757	* Reset value: 0xC0000000U
Kojto	90:cb3d968589d8	1758	*
Kojto	90:cb3d968589d8	1759	* MIBC is a read/write register controlling and observing the state of the MIB
Kojto	90:cb3d968589d8	1760	* block. Access this register to disable the MIB block operation or clear the
Kojto	90:cb3d968589d8	1761	* MIB counters. The MIB_DIS field resets to 1.
Kojto	90:cb3d968589d8	1762	*/
Kojto	90:cb3d968589d8	1763	typedef union _hw_enet_mibc
Kojto	90:cb3d968589d8	1764	{
Kojto	90:cb3d968589d8	1765	uint32_t U;
Kojto	90:cb3d968589d8	1766	struct _hw_enet_mibc_bitfields
Kojto	90:cb3d968589d8	1767	{
Kojto	90:cb3d968589d8	1768	uint32_t RESERVED0 : 29; /!< [28:0] /
Kojto	90:cb3d968589d8	1769	uint32_t MIB_CLEAR : 1; /!< [29] MIB Clear /
Kojto	90:cb3d968589d8	1770	uint32_t MIB_IDLE : 1; /!< [30] MIB Idle /
Kojto	90:cb3d968589d8	1771	uint32_t MIB_DIS : 1; /!< [31] Disable MIB Logic /
Kojto	90:cb3d968589d8	1772	} B;
Kojto	90:cb3d968589d8	1773	} hw_enet_mibc_t;
Kojto	90:cb3d968589d8	1774
Kojto	90:cb3d968589d8	1775	/*!
Kojto	90:cb3d968589d8	1776	* @name Constants and macros for entire ENET_MIBC register
Kojto	90:cb3d968589d8	1777	*/
Kojto	90:cb3d968589d8	1778	/@{/
Kojto	90:cb3d968589d8	1779	#define HW_ENET_MIBC_ADDR(x) ((x) + 0x64U)
Kojto	90:cb3d968589d8	1780
Kojto	90:cb3d968589d8	1781	#define HW_ENET_MIBC(x) ((__IO hw_enet_mibc_t ) HW_ENET_MIBC_ADDR(x))
Kojto	90:cb3d968589d8	1782	#define HW_ENET_MIBC_RD(x) (HW_ENET_MIBC(x).U)
Kojto	90:cb3d968589d8	1783	#define HW_ENET_MIBC_WR(x, v) (HW_ENET_MIBC(x).U = (v))
Kojto	90:cb3d968589d8	1784	#define HW_ENET_MIBC_SET(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1785	#define HW_ENET_MIBC_CLR(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1786	#define HW_ENET_MIBC_TOG(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1787	/@}/
Kojto	90:cb3d968589d8	1788
Kojto	90:cb3d968589d8	1789	/*
Kojto	90:cb3d968589d8	1790	* Constants & macros for individual ENET_MIBC bitfields
Kojto	90:cb3d968589d8	1791	*/
Kojto	90:cb3d968589d8	1792
Kojto	90:cb3d968589d8	1793	/*!
Kojto	90:cb3d968589d8	1794	* @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
Kojto	90:cb3d968589d8	1795	*
Kojto	90:cb3d968589d8	1796	* If set, all statistics counters are reset to 0. This field is not
Kojto	90:cb3d968589d8	1797	* self-clearing. To clear the MIB counters set and then clear the field.
Kojto	90:cb3d968589d8	1798	*/
Kojto	90:cb3d968589d8	1799	/@{/
Kojto	90:cb3d968589d8	1800	#define BP_ENET_MIBC_MIB_CLEAR (29U) /!< Bit position for ENET_MIBC_MIB_CLEAR. /
Kojto	90:cb3d968589d8	1801	#define BM_ENET_MIBC_MIB_CLEAR (0x20000000U) /!< Bit mask for ENET_MIBC_MIB_CLEAR. /
Kojto	90:cb3d968589d8	1802	#define BS_ENET_MIBC_MIB_CLEAR (1U) /!< Bit field size in bits for ENET_MIBC_MIB_CLEAR. /
Kojto	90:cb3d968589d8	1803
Kojto	90:cb3d968589d8	1804	/! @brief Read current value of the ENET_MIBC_MIB_CLEAR field. /
Kojto	90:cb3d968589d8	1805	#define BR_ENET_MIBC_MIB_CLEAR(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR))
Kojto	90:cb3d968589d8	1806
Kojto	90:cb3d968589d8	1807	/! @brief Format value for bitfield ENET_MIBC_MIB_CLEAR. /
Kojto	90:cb3d968589d8	1808	#define BF_ENET_MIBC_MIB_CLEAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MIBC_MIB_CLEAR) & BM_ENET_MIBC_MIB_CLEAR)
Kojto	90:cb3d968589d8	1809
Kojto	90:cb3d968589d8	1810	/! @brief Set the MIB_CLEAR field to a new value. /
Kojto	90:cb3d968589d8	1811	#define BW_ENET_MIBC_MIB_CLEAR(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR) = (v))
Kojto	90:cb3d968589d8	1812	/@}/
Kojto	90:cb3d968589d8	1813
Kojto	90:cb3d968589d8	1814	/*!
Kojto	90:cb3d968589d8	1815	* @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
Kojto	90:cb3d968589d8	1816	*
Kojto	90:cb3d968589d8	1817	* If this status field is set, the MIB block is not currently updating any MIB
Kojto	90:cb3d968589d8	1818	* counters.
Kojto	90:cb3d968589d8	1819	*/
Kojto	90:cb3d968589d8	1820	/@{/
Kojto	90:cb3d968589d8	1821	#define BP_ENET_MIBC_MIB_IDLE (30U) /!< Bit position for ENET_MIBC_MIB_IDLE. /
Kojto	90:cb3d968589d8	1822	#define BM_ENET_MIBC_MIB_IDLE (0x40000000U) /!< Bit mask for ENET_MIBC_MIB_IDLE. /
Kojto	90:cb3d968589d8	1823	#define BS_ENET_MIBC_MIB_IDLE (1U) /!< Bit field size in bits for ENET_MIBC_MIB_IDLE. /
Kojto	90:cb3d968589d8	1824
Kojto	90:cb3d968589d8	1825	/! @brief Read current value of the ENET_MIBC_MIB_IDLE field. /
Kojto	90:cb3d968589d8	1826	#define BR_ENET_MIBC_MIB_IDLE(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_IDLE))
Kojto	90:cb3d968589d8	1827	/@}/
Kojto	90:cb3d968589d8	1828
Kojto	90:cb3d968589d8	1829	/*!
Kojto	90:cb3d968589d8	1830	* @name Register ENET_MIBC, field MIB_DIS[31] (RW)
Kojto	90:cb3d968589d8	1831	*
Kojto	90:cb3d968589d8	1832	* If this control field is set, the MIB logic halts and does not update any MIB
Kojto	90:cb3d968589d8	1833	* counters.
Kojto	90:cb3d968589d8	1834	*/
Kojto	90:cb3d968589d8	1835	/@{/
Kojto	90:cb3d968589d8	1836	#define BP_ENET_MIBC_MIB_DIS (31U) /!< Bit position for ENET_MIBC_MIB_DIS. /
Kojto	90:cb3d968589d8	1837	#define BM_ENET_MIBC_MIB_DIS (0x80000000U) /!< Bit mask for ENET_MIBC_MIB_DIS. /
Kojto	90:cb3d968589d8	1838	#define BS_ENET_MIBC_MIB_DIS (1U) /!< Bit field size in bits for ENET_MIBC_MIB_DIS. /
Kojto	90:cb3d968589d8	1839
Kojto	90:cb3d968589d8	1840	/! @brief Read current value of the ENET_MIBC_MIB_DIS field. /
Kojto	90:cb3d968589d8	1841	#define BR_ENET_MIBC_MIB_DIS(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS))
Kojto	90:cb3d968589d8	1842
Kojto	90:cb3d968589d8	1843	/! @brief Format value for bitfield ENET_MIBC_MIB_DIS. /
Kojto	90:cb3d968589d8	1844	#define BF_ENET_MIBC_MIB_DIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MIBC_MIB_DIS) & BM_ENET_MIBC_MIB_DIS)
Kojto	90:cb3d968589d8	1845
Kojto	90:cb3d968589d8	1846	/! @brief Set the MIB_DIS field to a new value. /
Kojto	90:cb3d968589d8	1847	#define BW_ENET_MIBC_MIB_DIS(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS) = (v))
Kojto	90:cb3d968589d8	1848	/@}/
Kojto	90:cb3d968589d8	1849
Kojto	90:cb3d968589d8	1850	/*******************************************************************************
Kojto	90:cb3d968589d8	1851	* HW_ENET_RCR - Receive Control Register
Kojto	90:cb3d968589d8	1852	******************************************************************************/
Kojto	90:cb3d968589d8	1853
Kojto	90:cb3d968589d8	1854	/*!
Kojto	90:cb3d968589d8	1855	* @brief HW_ENET_RCR - Receive Control Register (RW)
Kojto	90:cb3d968589d8	1856	*
Kojto	90:cb3d968589d8	1857	* Reset value: 0x05EE0001U
Kojto	90:cb3d968589d8	1858	*/
Kojto	90:cb3d968589d8	1859	typedef union _hw_enet_rcr
Kojto	90:cb3d968589d8	1860	{
Kojto	90:cb3d968589d8	1861	uint32_t U;
Kojto	90:cb3d968589d8	1862	struct _hw_enet_rcr_bitfields
Kojto	90:cb3d968589d8	1863	{
Kojto	90:cb3d968589d8	1864	uint32_t LOOP : 1; /!< [0] Internal Loopback /
Kojto	90:cb3d968589d8	1865	uint32_t DRT : 1; /!< [1] Disable Receive On Transmit /
Kojto	90:cb3d968589d8	1866	uint32_t MII_MODE : 1; /!< [2] Media Independent Interface Mode /
Kojto	90:cb3d968589d8	1867	uint32_t PROM : 1; /!< [3] Promiscuous Mode /
Kojto	90:cb3d968589d8	1868	uint32_t BC_REJ : 1; /!< [4] Broadcast Frame Reject /
Kojto	90:cb3d968589d8	1869	uint32_t FCE : 1; /!< [5] Flow Control Enable /
Kojto	90:cb3d968589d8	1870	uint32_t RESERVED0 : 2; /!< [7:6] /
Kojto	90:cb3d968589d8	1871	uint32_t RMII_MODE : 1; /!< [8] RMII Mode Enable /
Kojto	90:cb3d968589d8	1872	uint32_t RMII_10T : 1; /!< [9] /
Kojto	90:cb3d968589d8	1873	uint32_t RESERVED1 : 2; /!< [11:10] /
Kojto	90:cb3d968589d8	1874	uint32_t PADEN : 1; /*!< [12] Enable Frame Padding Remove On Receive
Kojto	90:cb3d968589d8	1875	* */
Kojto	90:cb3d968589d8	1876	uint32_t PAUFWD : 1; /!< [13] Terminate/Forward Pause Frames /
Kojto	90:cb3d968589d8	1877	uint32_t CRCFWD : 1; /!< [14] Terminate/Forward Received CRC /
Kojto	90:cb3d968589d8	1878	uint32_t CFEN : 1; /!< [15] MAC Control Frame Enable /
Kojto	90:cb3d968589d8	1879	uint32_t MAX_FL : 14; /!< [29:16] Maximum Frame Length /
Kojto	90:cb3d968589d8	1880	uint32_t NLC : 1; /!< [30] Payload Length Check Disable /
Kojto	90:cb3d968589d8	1881	uint32_t GRS : 1; /!< [31] Graceful Receive Stopped /
Kojto	90:cb3d968589d8	1882	} B;
Kojto	90:cb3d968589d8	1883	} hw_enet_rcr_t;
Kojto	90:cb3d968589d8	1884
Kojto	90:cb3d968589d8	1885	/*!
Kojto	90:cb3d968589d8	1886	* @name Constants and macros for entire ENET_RCR register
Kojto	90:cb3d968589d8	1887	*/
Kojto	90:cb3d968589d8	1888	/@{/
Kojto	90:cb3d968589d8	1889	#define HW_ENET_RCR_ADDR(x) ((x) + 0x84U)
Kojto	90:cb3d968589d8	1890
Kojto	90:cb3d968589d8	1891	#define HW_ENET_RCR(x) ((__IO hw_enet_rcr_t ) HW_ENET_RCR_ADDR(x))
Kojto	90:cb3d968589d8	1892	#define HW_ENET_RCR_RD(x) (HW_ENET_RCR(x).U)
Kojto	90:cb3d968589d8	1893	#define HW_ENET_RCR_WR(x, v) (HW_ENET_RCR(x).U = (v))
Kojto	90:cb3d968589d8	1894	#define HW_ENET_RCR_SET(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1895	#define HW_ENET_RCR_CLR(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1896	#define HW_ENET_RCR_TOG(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1897	/@}/
Kojto	90:cb3d968589d8	1898
Kojto	90:cb3d968589d8	1899	/*
Kojto	90:cb3d968589d8	1900	* Constants & macros for individual ENET_RCR bitfields
Kojto	90:cb3d968589d8	1901	*/
Kojto	90:cb3d968589d8	1902
Kojto	90:cb3d968589d8	1903	/*!
Kojto	90:cb3d968589d8	1904	* @name Register ENET_RCR, field LOOP[0] (RW)
Kojto	90:cb3d968589d8	1905	*
Kojto	90:cb3d968589d8	1906	* This is an MII internal loopback, therefore MII_MODE must be written to 1 and
Kojto	90:cb3d968589d8	1907	* RMII_MODE must be written to 0.
Kojto	90:cb3d968589d8	1908	*
Kojto	90:cb3d968589d8	1909	* Values:
Kojto	90:cb3d968589d8	1910	* - 0 - Loopback disabled.
Kojto	90:cb3d968589d8	1911	* - 1 - Transmitted frames are looped back internal to the device and transmit
Kojto	90:cb3d968589d8	1912	* MII output signals are not asserted. DRT must be cleared.
Kojto	90:cb3d968589d8	1913	*/
Kojto	90:cb3d968589d8	1914	/@{/
Kojto	90:cb3d968589d8	1915	#define BP_ENET_RCR_LOOP (0U) /!< Bit position for ENET_RCR_LOOP. /
Kojto	90:cb3d968589d8	1916	#define BM_ENET_RCR_LOOP (0x00000001U) /!< Bit mask for ENET_RCR_LOOP. /
Kojto	90:cb3d968589d8	1917	#define BS_ENET_RCR_LOOP (1U) /!< Bit field size in bits for ENET_RCR_LOOP. /
Kojto	90:cb3d968589d8	1918
Kojto	90:cb3d968589d8	1919	/! @brief Read current value of the ENET_RCR_LOOP field. /
Kojto	90:cb3d968589d8	1920	#define BR_ENET_RCR_LOOP(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP))
Kojto	90:cb3d968589d8	1921
Kojto	90:cb3d968589d8	1922	/! @brief Format value for bitfield ENET_RCR_LOOP. /
Kojto	90:cb3d968589d8	1923	#define BF_ENET_RCR_LOOP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_LOOP) & BM_ENET_RCR_LOOP)
Kojto	90:cb3d968589d8	1924
Kojto	90:cb3d968589d8	1925	/! @brief Set the LOOP field to a new value. /
Kojto	90:cb3d968589d8	1926	#define BW_ENET_RCR_LOOP(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP) = (v))
Kojto	90:cb3d968589d8	1927	/@}/
Kojto	90:cb3d968589d8	1928
Kojto	90:cb3d968589d8	1929	/*!
Kojto	90:cb3d968589d8	1930	* @name Register ENET_RCR, field DRT[1] (RW)
Kojto	90:cb3d968589d8	1931	*
Kojto	90:cb3d968589d8	1932	* Values:
Kojto	90:cb3d968589d8	1933	* - 0 - Receive path operates independently of transmit. Used for full-duplex
Kojto	90:cb3d968589d8	1934	* or to monitor transmit activity in half-duplex mode.
Kojto	90:cb3d968589d8	1935	* - 1 - Disable reception of frames while transmitting. Normally used for
Kojto	90:cb3d968589d8	1936	* half-duplex mode.
Kojto	90:cb3d968589d8	1937	*/
Kojto	90:cb3d968589d8	1938	/@{/
Kojto	90:cb3d968589d8	1939	#define BP_ENET_RCR_DRT (1U) /!< Bit position for ENET_RCR_DRT. /
Kojto	90:cb3d968589d8	1940	#define BM_ENET_RCR_DRT (0x00000002U) /!< Bit mask for ENET_RCR_DRT. /
Kojto	90:cb3d968589d8	1941	#define BS_ENET_RCR_DRT (1U) /!< Bit field size in bits for ENET_RCR_DRT. /
Kojto	90:cb3d968589d8	1942
Kojto	90:cb3d968589d8	1943	/! @brief Read current value of the ENET_RCR_DRT field. /
Kojto	90:cb3d968589d8	1944	#define BR_ENET_RCR_DRT(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT))
Kojto	90:cb3d968589d8	1945
Kojto	90:cb3d968589d8	1946	/! @brief Format value for bitfield ENET_RCR_DRT. /
Kojto	90:cb3d968589d8	1947	#define BF_ENET_RCR_DRT(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_DRT) & BM_ENET_RCR_DRT)
Kojto	90:cb3d968589d8	1948
Kojto	90:cb3d968589d8	1949	/! @brief Set the DRT field to a new value. /
Kojto	90:cb3d968589d8	1950	#define BW_ENET_RCR_DRT(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT) = (v))
Kojto	90:cb3d968589d8	1951	/@}/
Kojto	90:cb3d968589d8	1952
Kojto	90:cb3d968589d8	1953	/*!
Kojto	90:cb3d968589d8	1954	* @name Register ENET_RCR, field MII_MODE[2] (RW)
Kojto	90:cb3d968589d8	1955	*
Kojto	90:cb3d968589d8	1956	* This field must always be set.
Kojto	90:cb3d968589d8	1957	*
Kojto	90:cb3d968589d8	1958	* Values:
Kojto	90:cb3d968589d8	1959	* - 0 - Reserved.
Kojto	90:cb3d968589d8	1960	* - 1 - MII or RMII mode, as indicated by the RMII_MODE field.
Kojto	90:cb3d968589d8	1961	*/
Kojto	90:cb3d968589d8	1962	/@{/
Kojto	90:cb3d968589d8	1963	#define BP_ENET_RCR_MII_MODE (2U) /!< Bit position for ENET_RCR_MII_MODE. /
Kojto	90:cb3d968589d8	1964	#define BM_ENET_RCR_MII_MODE (0x00000004U) /!< Bit mask for ENET_RCR_MII_MODE. /
Kojto	90:cb3d968589d8	1965	#define BS_ENET_RCR_MII_MODE (1U) /!< Bit field size in bits for ENET_RCR_MII_MODE. /
Kojto	90:cb3d968589d8	1966
Kojto	90:cb3d968589d8	1967	/! @brief Read current value of the ENET_RCR_MII_MODE field. /
Kojto	90:cb3d968589d8	1968	#define BR_ENET_RCR_MII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE))
Kojto	90:cb3d968589d8	1969
Kojto	90:cb3d968589d8	1970	/! @brief Format value for bitfield ENET_RCR_MII_MODE. /
Kojto	90:cb3d968589d8	1971	#define BF_ENET_RCR_MII_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_MII_MODE) & BM_ENET_RCR_MII_MODE)
Kojto	90:cb3d968589d8	1972
Kojto	90:cb3d968589d8	1973	/! @brief Set the MII_MODE field to a new value. /
Kojto	90:cb3d968589d8	1974	#define BW_ENET_RCR_MII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE) = (v))
Kojto	90:cb3d968589d8	1975	/@}/
Kojto	90:cb3d968589d8	1976
Kojto	90:cb3d968589d8	1977	/*!
Kojto	90:cb3d968589d8	1978	* @name Register ENET_RCR, field PROM[3] (RW)
Kojto	90:cb3d968589d8	1979	*
Kojto	90:cb3d968589d8	1980	* All frames are accepted regardless of address matching.
Kojto	90:cb3d968589d8	1981	*
Kojto	90:cb3d968589d8	1982	* Values:
Kojto	90:cb3d968589d8	1983	* - 0 - Disabled.
Kojto	90:cb3d968589d8	1984	* - 1 - Enabled.
Kojto	90:cb3d968589d8	1985	*/
Kojto	90:cb3d968589d8	1986	/@{/
Kojto	90:cb3d968589d8	1987	#define BP_ENET_RCR_PROM (3U) /!< Bit position for ENET_RCR_PROM. /
Kojto	90:cb3d968589d8	1988	#define BM_ENET_RCR_PROM (0x00000008U) /!< Bit mask for ENET_RCR_PROM. /
Kojto	90:cb3d968589d8	1989	#define BS_ENET_RCR_PROM (1U) /!< Bit field size in bits for ENET_RCR_PROM. /
Kojto	90:cb3d968589d8	1990
Kojto	90:cb3d968589d8	1991	/! @brief Read current value of the ENET_RCR_PROM field. /
Kojto	90:cb3d968589d8	1992	#define BR_ENET_RCR_PROM(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM))
Kojto	90:cb3d968589d8	1993
Kojto	90:cb3d968589d8	1994	/! @brief Format value for bitfield ENET_RCR_PROM. /
Kojto	90:cb3d968589d8	1995	#define BF_ENET_RCR_PROM(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PROM) & BM_ENET_RCR_PROM)
Kojto	90:cb3d968589d8	1996
Kojto	90:cb3d968589d8	1997	/! @brief Set the PROM field to a new value. /
Kojto	90:cb3d968589d8	1998	#define BW_ENET_RCR_PROM(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM) = (v))
Kojto	90:cb3d968589d8	1999	/@}/
Kojto	90:cb3d968589d8	2000
Kojto	90:cb3d968589d8	2001	/*!
Kojto	90:cb3d968589d8	2002	* @name Register ENET_RCR, field BC_REJ[4] (RW)
Kojto	90:cb3d968589d8	2003	*
Kojto	90:cb3d968589d8	2004	* If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
Kojto	90:cb3d968589d8	2005	* rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
Kojto	90:cb3d968589d8	2006	* broadcast DA are accepted and the MISS (M) is set in the receive buffer
Kojto	90:cb3d968589d8	2007	* descriptor.
Kojto	90:cb3d968589d8	2008	*/
Kojto	90:cb3d968589d8	2009	/@{/
Kojto	90:cb3d968589d8	2010	#define BP_ENET_RCR_BC_REJ (4U) /!< Bit position for ENET_RCR_BC_REJ. /
Kojto	90:cb3d968589d8	2011	#define BM_ENET_RCR_BC_REJ (0x00000010U) /!< Bit mask for ENET_RCR_BC_REJ. /
Kojto	90:cb3d968589d8	2012	#define BS_ENET_RCR_BC_REJ (1U) /!< Bit field size in bits for ENET_RCR_BC_REJ. /
Kojto	90:cb3d968589d8	2013
Kojto	90:cb3d968589d8	2014	/! @brief Read current value of the ENET_RCR_BC_REJ field. /
Kojto	90:cb3d968589d8	2015	#define BR_ENET_RCR_BC_REJ(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ))
Kojto	90:cb3d968589d8	2016
Kojto	90:cb3d968589d8	2017	/! @brief Format value for bitfield ENET_RCR_BC_REJ. /
Kojto	90:cb3d968589d8	2018	#define BF_ENET_RCR_BC_REJ(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_BC_REJ) & BM_ENET_RCR_BC_REJ)
Kojto	90:cb3d968589d8	2019
Kojto	90:cb3d968589d8	2020	/! @brief Set the BC_REJ field to a new value. /
Kojto	90:cb3d968589d8	2021	#define BW_ENET_RCR_BC_REJ(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ) = (v))
Kojto	90:cb3d968589d8	2022	/@}/
Kojto	90:cb3d968589d8	2023
Kojto	90:cb3d968589d8	2024	/*!
Kojto	90:cb3d968589d8	2025	* @name Register ENET_RCR, field FCE[5] (RW)
Kojto	90:cb3d968589d8	2026	*
Kojto	90:cb3d968589d8	2027	* If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
Kojto	90:cb3d968589d8	2028	* transmitter stops transmitting data frames for a given duration.
Kojto	90:cb3d968589d8	2029	*/
Kojto	90:cb3d968589d8	2030	/@{/
Kojto	90:cb3d968589d8	2031	#define BP_ENET_RCR_FCE (5U) /!< Bit position for ENET_RCR_FCE. /
Kojto	90:cb3d968589d8	2032	#define BM_ENET_RCR_FCE (0x00000020U) /!< Bit mask for ENET_RCR_FCE. /
Kojto	90:cb3d968589d8	2033	#define BS_ENET_RCR_FCE (1U) /!< Bit field size in bits for ENET_RCR_FCE. /
Kojto	90:cb3d968589d8	2034
Kojto	90:cb3d968589d8	2035	/! @brief Read current value of the ENET_RCR_FCE field. /
Kojto	90:cb3d968589d8	2036	#define BR_ENET_RCR_FCE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE))
Kojto	90:cb3d968589d8	2037
Kojto	90:cb3d968589d8	2038	/! @brief Format value for bitfield ENET_RCR_FCE. /
Kojto	90:cb3d968589d8	2039	#define BF_ENET_RCR_FCE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_FCE) & BM_ENET_RCR_FCE)
Kojto	90:cb3d968589d8	2040
Kojto	90:cb3d968589d8	2041	/! @brief Set the FCE field to a new value. /
Kojto	90:cb3d968589d8	2042	#define BW_ENET_RCR_FCE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE) = (v))
Kojto	90:cb3d968589d8	2043	/@}/
Kojto	90:cb3d968589d8	2044
Kojto	90:cb3d968589d8	2045	/*!
Kojto	90:cb3d968589d8	2046	* @name Register ENET_RCR, field RMII_MODE[8] (RW)
Kojto	90:cb3d968589d8	2047	*
Kojto	90:cb3d968589d8	2048	* Specifies whether the MAC is configured for MII mode or RMII operation .
Kojto	90:cb3d968589d8	2049	*
Kojto	90:cb3d968589d8	2050	* Values:
Kojto	90:cb3d968589d8	2051	* - 0 - MAC configured for MII mode.
Kojto	90:cb3d968589d8	2052	* - 1 - MAC configured for RMII operation.
Kojto	90:cb3d968589d8	2053	*/
Kojto	90:cb3d968589d8	2054	/@{/
Kojto	90:cb3d968589d8	2055	#define BP_ENET_RCR_RMII_MODE (8U) /!< Bit position for ENET_RCR_RMII_MODE. /
Kojto	90:cb3d968589d8	2056	#define BM_ENET_RCR_RMII_MODE (0x00000100U) /!< Bit mask for ENET_RCR_RMII_MODE. /
Kojto	90:cb3d968589d8	2057	#define BS_ENET_RCR_RMII_MODE (1U) /!< Bit field size in bits for ENET_RCR_RMII_MODE. /
Kojto	90:cb3d968589d8	2058
Kojto	90:cb3d968589d8	2059	/! @brief Read current value of the ENET_RCR_RMII_MODE field. /
Kojto	90:cb3d968589d8	2060	#define BR_ENET_RCR_RMII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE))
Kojto	90:cb3d968589d8	2061
Kojto	90:cb3d968589d8	2062	/! @brief Format value for bitfield ENET_RCR_RMII_MODE. /
Kojto	90:cb3d968589d8	2063	#define BF_ENET_RCR_RMII_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_RMII_MODE) & BM_ENET_RCR_RMII_MODE)
Kojto	90:cb3d968589d8	2064
Kojto	90:cb3d968589d8	2065	/! @brief Set the RMII_MODE field to a new value. /
Kojto	90:cb3d968589d8	2066	#define BW_ENET_RCR_RMII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE) = (v))
Kojto	90:cb3d968589d8	2067	/@}/
Kojto	90:cb3d968589d8	2068
Kojto	90:cb3d968589d8	2069	/*!
Kojto	90:cb3d968589d8	2070	* @name Register ENET_RCR, field RMII_10T[9] (RW)
Kojto	90:cb3d968589d8	2071	*
Kojto	90:cb3d968589d8	2072	* Enables 10-Mbps mode of the RMII .
Kojto	90:cb3d968589d8	2073	*
Kojto	90:cb3d968589d8	2074	* Values:
Kojto	90:cb3d968589d8	2075	* - 0 - 100 Mbps operation.
Kojto	90:cb3d968589d8	2076	* - 1 - 10 Mbps operation.
Kojto	90:cb3d968589d8	2077	*/
Kojto	90:cb3d968589d8	2078	/@{/
Kojto	90:cb3d968589d8	2079	#define BP_ENET_RCR_RMII_10T (9U) /!< Bit position for ENET_RCR_RMII_10T. /
Kojto	90:cb3d968589d8	2080	#define BM_ENET_RCR_RMII_10T (0x00000200U) /!< Bit mask for ENET_RCR_RMII_10T. /
Kojto	90:cb3d968589d8	2081	#define BS_ENET_RCR_RMII_10T (1U) /!< Bit field size in bits for ENET_RCR_RMII_10T. /
Kojto	90:cb3d968589d8	2082
Kojto	90:cb3d968589d8	2083	/! @brief Read current value of the ENET_RCR_RMII_10T field. /
Kojto	90:cb3d968589d8	2084	#define BR_ENET_RCR_RMII_10T(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T))
Kojto	90:cb3d968589d8	2085
Kojto	90:cb3d968589d8	2086	/! @brief Format value for bitfield ENET_RCR_RMII_10T. /
Kojto	90:cb3d968589d8	2087	#define BF_ENET_RCR_RMII_10T(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_RMII_10T) & BM_ENET_RCR_RMII_10T)
Kojto	90:cb3d968589d8	2088
Kojto	90:cb3d968589d8	2089	/! @brief Set the RMII_10T field to a new value. /
Kojto	90:cb3d968589d8	2090	#define BW_ENET_RCR_RMII_10T(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T) = (v))
Kojto	90:cb3d968589d8	2091	/@}/
Kojto	90:cb3d968589d8	2092
Kojto	90:cb3d968589d8	2093	/*!
Kojto	90:cb3d968589d8	2094	* @name Register ENET_RCR, field PADEN[12] (RW)
Kojto	90:cb3d968589d8	2095	*
Kojto	90:cb3d968589d8	2096	* Specifies whether the MAC removes padding from received frames.
Kojto	90:cb3d968589d8	2097	*
Kojto	90:cb3d968589d8	2098	* Values:
Kojto	90:cb3d968589d8	2099	* - 0 - No padding is removed on receive by the MAC.
Kojto	90:cb3d968589d8	2100	* - 1 - Padding is removed from received frames.
Kojto	90:cb3d968589d8	2101	*/
Kojto	90:cb3d968589d8	2102	/@{/
Kojto	90:cb3d968589d8	2103	#define BP_ENET_RCR_PADEN (12U) /!< Bit position for ENET_RCR_PADEN. /
Kojto	90:cb3d968589d8	2104	#define BM_ENET_RCR_PADEN (0x00001000U) /!< Bit mask for ENET_RCR_PADEN. /
Kojto	90:cb3d968589d8	2105	#define BS_ENET_RCR_PADEN (1U) /!< Bit field size in bits for ENET_RCR_PADEN. /
Kojto	90:cb3d968589d8	2106
Kojto	90:cb3d968589d8	2107	/! @brief Read current value of the ENET_RCR_PADEN field. /
Kojto	90:cb3d968589d8	2108	#define BR_ENET_RCR_PADEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN))
Kojto	90:cb3d968589d8	2109
Kojto	90:cb3d968589d8	2110	/! @brief Format value for bitfield ENET_RCR_PADEN. /
Kojto	90:cb3d968589d8	2111	#define BF_ENET_RCR_PADEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PADEN) & BM_ENET_RCR_PADEN)
Kojto	90:cb3d968589d8	2112
Kojto	90:cb3d968589d8	2113	/! @brief Set the PADEN field to a new value. /
Kojto	90:cb3d968589d8	2114	#define BW_ENET_RCR_PADEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN) = (v))
Kojto	90:cb3d968589d8	2115	/@}/
Kojto	90:cb3d968589d8	2116
Kojto	90:cb3d968589d8	2117	/*!
Kojto	90:cb3d968589d8	2118	* @name Register ENET_RCR, field PAUFWD[13] (RW)
Kojto	90:cb3d968589d8	2119	*
Kojto	90:cb3d968589d8	2120	* Specifies whether pause frames are terminated or forwarded.
Kojto	90:cb3d968589d8	2121	*
Kojto	90:cb3d968589d8	2122	* Values:
Kojto	90:cb3d968589d8	2123	* - 0 - Pause frames are terminated and discarded in the MAC.
Kojto	90:cb3d968589d8	2124	* - 1 - Pause frames are forwarded to the user application.
Kojto	90:cb3d968589d8	2125	*/
Kojto	90:cb3d968589d8	2126	/@{/
Kojto	90:cb3d968589d8	2127	#define BP_ENET_RCR_PAUFWD (13U) /!< Bit position for ENET_RCR_PAUFWD. /
Kojto	90:cb3d968589d8	2128	#define BM_ENET_RCR_PAUFWD (0x00002000U) /!< Bit mask for ENET_RCR_PAUFWD. /
Kojto	90:cb3d968589d8	2129	#define BS_ENET_RCR_PAUFWD (1U) /!< Bit field size in bits for ENET_RCR_PAUFWD. /
Kojto	90:cb3d968589d8	2130
Kojto	90:cb3d968589d8	2131	/! @brief Read current value of the ENET_RCR_PAUFWD field. /
Kojto	90:cb3d968589d8	2132	#define BR_ENET_RCR_PAUFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD))
Kojto	90:cb3d968589d8	2133
Kojto	90:cb3d968589d8	2134	/! @brief Format value for bitfield ENET_RCR_PAUFWD. /
Kojto	90:cb3d968589d8	2135	#define BF_ENET_RCR_PAUFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PAUFWD) & BM_ENET_RCR_PAUFWD)
Kojto	90:cb3d968589d8	2136
Kojto	90:cb3d968589d8	2137	/! @brief Set the PAUFWD field to a new value. /
Kojto	90:cb3d968589d8	2138	#define BW_ENET_RCR_PAUFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD) = (v))
Kojto	90:cb3d968589d8	2139	/@}/
Kojto	90:cb3d968589d8	2140
Kojto	90:cb3d968589d8	2141	/*!
Kojto	90:cb3d968589d8	2142	* @name Register ENET_RCR, field CRCFWD[14] (RW)
Kojto	90:cb3d968589d8	2143	*
Kojto	90:cb3d968589d8	2144	* Specifies whether the CRC field of received frames is transmitted or
Kojto	90:cb3d968589d8	2145	* stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
Kojto	90:cb3d968589d8	2146	* field is checked and always terminated and removed.
Kojto	90:cb3d968589d8	2147	*
Kojto	90:cb3d968589d8	2148	* Values:
Kojto	90:cb3d968589d8	2149	* - 0 - The CRC field of received frames is transmitted to the user application.
Kojto	90:cb3d968589d8	2150	* - 1 - The CRC field is stripped from the frame.
Kojto	90:cb3d968589d8	2151	*/
Kojto	90:cb3d968589d8	2152	/@{/
Kojto	90:cb3d968589d8	2153	#define BP_ENET_RCR_CRCFWD (14U) /!< Bit position for ENET_RCR_CRCFWD. /
Kojto	90:cb3d968589d8	2154	#define BM_ENET_RCR_CRCFWD (0x00004000U) /!< Bit mask for ENET_RCR_CRCFWD. /
Kojto	90:cb3d968589d8	2155	#define BS_ENET_RCR_CRCFWD (1U) /!< Bit field size in bits for ENET_RCR_CRCFWD. /
Kojto	90:cb3d968589d8	2156
Kojto	90:cb3d968589d8	2157	/! @brief Read current value of the ENET_RCR_CRCFWD field. /
Kojto	90:cb3d968589d8	2158	#define BR_ENET_RCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD))
Kojto	90:cb3d968589d8	2159
Kojto	90:cb3d968589d8	2160	/! @brief Format value for bitfield ENET_RCR_CRCFWD. /
Kojto	90:cb3d968589d8	2161	#define BF_ENET_RCR_CRCFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_CRCFWD) & BM_ENET_RCR_CRCFWD)
Kojto	90:cb3d968589d8	2162
Kojto	90:cb3d968589d8	2163	/! @brief Set the CRCFWD field to a new value. /
Kojto	90:cb3d968589d8	2164	#define BW_ENET_RCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD) = (v))
Kojto	90:cb3d968589d8	2165	/@}/
Kojto	90:cb3d968589d8	2166
Kojto	90:cb3d968589d8	2167	/*!
Kojto	90:cb3d968589d8	2168	* @name Register ENET_RCR, field CFEN[15] (RW)
Kojto	90:cb3d968589d8	2169	*
Kojto	90:cb3d968589d8	2170	* Enables/disables the MAC control frame.
Kojto	90:cb3d968589d8	2171	*
Kojto	90:cb3d968589d8	2172	* Values:
Kojto	90:cb3d968589d8	2173	* - 0 - MAC control frames with any opcode other than 0x0001 (pause frame) are
Kojto	90:cb3d968589d8	2174	* accepted and forwarded to the client interface.
Kojto	90:cb3d968589d8	2175	* - 1 - MAC control frames with any opcode other than 0x0001 (pause frame) are
Kojto	90:cb3d968589d8	2176	* silently discarded.
Kojto	90:cb3d968589d8	2177	*/
Kojto	90:cb3d968589d8	2178	/@{/
Kojto	90:cb3d968589d8	2179	#define BP_ENET_RCR_CFEN (15U) /!< Bit position for ENET_RCR_CFEN. /
Kojto	90:cb3d968589d8	2180	#define BM_ENET_RCR_CFEN (0x00008000U) /!< Bit mask for ENET_RCR_CFEN. /
Kojto	90:cb3d968589d8	2181	#define BS_ENET_RCR_CFEN (1U) /!< Bit field size in bits for ENET_RCR_CFEN. /
Kojto	90:cb3d968589d8	2182
Kojto	90:cb3d968589d8	2183	/! @brief Read current value of the ENET_RCR_CFEN field. /
Kojto	90:cb3d968589d8	2184	#define BR_ENET_RCR_CFEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN))
Kojto	90:cb3d968589d8	2185
Kojto	90:cb3d968589d8	2186	/! @brief Format value for bitfield ENET_RCR_CFEN. /
Kojto	90:cb3d968589d8	2187	#define BF_ENET_RCR_CFEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_CFEN) & BM_ENET_RCR_CFEN)
Kojto	90:cb3d968589d8	2188
Kojto	90:cb3d968589d8	2189	/! @brief Set the CFEN field to a new value. /
Kojto	90:cb3d968589d8	2190	#define BW_ENET_RCR_CFEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN) = (v))
Kojto	90:cb3d968589d8	2191	/@}/
Kojto	90:cb3d968589d8	2192
Kojto	90:cb3d968589d8	2193	/*!
Kojto	90:cb3d968589d8	2194	* @name Register ENET_RCR, field MAX_FL[29:16] (RW)
Kojto	90:cb3d968589d8	2195	*
Kojto	90:cb3d968589d8	2196	* Resets to decimal 1518. Length is measured starting at DA and includes the
Kojto	90:cb3d968589d8	2197	* CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
Kojto	90:cb3d968589d8	2198	* interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
Kojto	90:cb3d968589d8	2199	* to occur and set the LG field in the end of frame receive buffer descriptor.
Kojto	90:cb3d968589d8	2200	* The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
Kojto	90:cb3d968589d8	2201	* supported.
Kojto	90:cb3d968589d8	2202	*/
Kojto	90:cb3d968589d8	2203	/@{/
Kojto	90:cb3d968589d8	2204	#define BP_ENET_RCR_MAX_FL (16U) /!< Bit position for ENET_RCR_MAX_FL. /
Kojto	90:cb3d968589d8	2205	#define BM_ENET_RCR_MAX_FL (0x3FFF0000U) /!< Bit mask for ENET_RCR_MAX_FL. /
Kojto	90:cb3d968589d8	2206	#define BS_ENET_RCR_MAX_FL (14U) /!< Bit field size in bits for ENET_RCR_MAX_FL. /
Kojto	90:cb3d968589d8	2207
Kojto	90:cb3d968589d8	2208	/! @brief Read current value of the ENET_RCR_MAX_FL field. /
Kojto	90:cb3d968589d8	2209	#define BR_ENET_RCR_MAX_FL(x) (HW_ENET_RCR(x).B.MAX_FL)
Kojto	90:cb3d968589d8	2210
Kojto	90:cb3d968589d8	2211	/! @brief Format value for bitfield ENET_RCR_MAX_FL. /
Kojto	90:cb3d968589d8	2212	#define BF_ENET_RCR_MAX_FL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_MAX_FL) & BM_ENET_RCR_MAX_FL)
Kojto	90:cb3d968589d8	2213
Kojto	90:cb3d968589d8	2214	/! @brief Set the MAX_FL field to a new value. /
Kojto	90:cb3d968589d8	2215	#define BW_ENET_RCR_MAX_FL(x, v) (HW_ENET_RCR_WR(x, (HW_ENET_RCR_RD(x) & ~BM_ENET_RCR_MAX_FL) \| BF_ENET_RCR_MAX_FL(v)))
Kojto	90:cb3d968589d8	2216	/@}/
Kojto	90:cb3d968589d8	2217
Kojto	90:cb3d968589d8	2218	/*!
Kojto	90:cb3d968589d8	2219	* @name Register ENET_RCR, field NLC[30] (RW)
Kojto	90:cb3d968589d8	2220	*
Kojto	90:cb3d968589d8	2221	* Enables/disables a payload length check.
Kojto	90:cb3d968589d8	2222	*
Kojto	90:cb3d968589d8	2223	* Values:
Kojto	90:cb3d968589d8	2224	* - 0 - The payload length check is disabled.
Kojto	90:cb3d968589d8	2225	* - 1 - The core checks the frame's payload length with the frame length/type
Kojto	90:cb3d968589d8	2226	* field. Errors are indicated in the EIR[PLC] field.
Kojto	90:cb3d968589d8	2227	*/
Kojto	90:cb3d968589d8	2228	/@{/
Kojto	90:cb3d968589d8	2229	#define BP_ENET_RCR_NLC (30U) /!< Bit position for ENET_RCR_NLC. /
Kojto	90:cb3d968589d8	2230	#define BM_ENET_RCR_NLC (0x40000000U) /!< Bit mask for ENET_RCR_NLC. /
Kojto	90:cb3d968589d8	2231	#define BS_ENET_RCR_NLC (1U) /!< Bit field size in bits for ENET_RCR_NLC. /
Kojto	90:cb3d968589d8	2232
Kojto	90:cb3d968589d8	2233	/! @brief Read current value of the ENET_RCR_NLC field. /
Kojto	90:cb3d968589d8	2234	#define BR_ENET_RCR_NLC(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC))
Kojto	90:cb3d968589d8	2235
Kojto	90:cb3d968589d8	2236	/! @brief Format value for bitfield ENET_RCR_NLC. /
Kojto	90:cb3d968589d8	2237	#define BF_ENET_RCR_NLC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_NLC) & BM_ENET_RCR_NLC)
Kojto	90:cb3d968589d8	2238
Kojto	90:cb3d968589d8	2239	/! @brief Set the NLC field to a new value. /
Kojto	90:cb3d968589d8	2240	#define BW_ENET_RCR_NLC(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC) = (v))
Kojto	90:cb3d968589d8	2241	/@}/
Kojto	90:cb3d968589d8	2242
Kojto	90:cb3d968589d8	2243	/*!
Kojto	90:cb3d968589d8	2244	* @name Register ENET_RCR, field GRS[31] (RO)
Kojto	90:cb3d968589d8	2245	*
Kojto	90:cb3d968589d8	2246	* Read-only status indicating that the MAC receive datapath is stopped.
Kojto	90:cb3d968589d8	2247	*/
Kojto	90:cb3d968589d8	2248	/@{/
Kojto	90:cb3d968589d8	2249	#define BP_ENET_RCR_GRS (31U) /!< Bit position for ENET_RCR_GRS. /
Kojto	90:cb3d968589d8	2250	#define BM_ENET_RCR_GRS (0x80000000U) /!< Bit mask for ENET_RCR_GRS. /
Kojto	90:cb3d968589d8	2251	#define BS_ENET_RCR_GRS (1U) /!< Bit field size in bits for ENET_RCR_GRS. /
Kojto	90:cb3d968589d8	2252
Kojto	90:cb3d968589d8	2253	/! @brief Read current value of the ENET_RCR_GRS field. /
Kojto	90:cb3d968589d8	2254	#define BR_ENET_RCR_GRS(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_GRS))
Kojto	90:cb3d968589d8	2255	/@}/
Kojto	90:cb3d968589d8	2256
Kojto	90:cb3d968589d8	2257	/*******************************************************************************
Kojto	90:cb3d968589d8	2258	* HW_ENET_TCR - Transmit Control Register
Kojto	90:cb3d968589d8	2259	******************************************************************************/
Kojto	90:cb3d968589d8	2260
Kojto	90:cb3d968589d8	2261	/*!
Kojto	90:cb3d968589d8	2262	* @brief HW_ENET_TCR - Transmit Control Register (RW)
Kojto	90:cb3d968589d8	2263	*
Kojto	90:cb3d968589d8	2264	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2265	*
Kojto	90:cb3d968589d8	2266	* TCR is read/write and configures the transmit block. This register is cleared
Kojto	90:cb3d968589d8	2267	* at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
Kojto	90:cb3d968589d8	2268	*/
Kojto	90:cb3d968589d8	2269	typedef union _hw_enet_tcr
Kojto	90:cb3d968589d8	2270	{
Kojto	90:cb3d968589d8	2271	uint32_t U;
Kojto	90:cb3d968589d8	2272	struct _hw_enet_tcr_bitfields
Kojto	90:cb3d968589d8	2273	{
Kojto	90:cb3d968589d8	2274	uint32_t GTS : 1; /!< [0] Graceful Transmit Stop /
Kojto	90:cb3d968589d8	2275	uint32_t RESERVED0 : 1; /!< [1] /
Kojto	90:cb3d968589d8	2276	uint32_t FDEN : 1; /!< [2] Full-Duplex Enable /
Kojto	90:cb3d968589d8	2277	uint32_t TFC_PAUSE : 1; /!< [3] Transmit Frame Control Pause /
Kojto	90:cb3d968589d8	2278	uint32_t RFC_PAUSE : 1; /!< [4] Receive Frame Control Pause /
Kojto	90:cb3d968589d8	2279	uint32_t ADDSEL : 3; /*!< [7:5] Source MAC Address Select On Transmit
Kojto	90:cb3d968589d8	2280	* */
Kojto	90:cb3d968589d8	2281	uint32_t ADDINS : 1; /!< [8] Set MAC Address On Transmit /
Kojto	90:cb3d968589d8	2282	uint32_t CRCFWD : 1; /*!< [9] Forward Frame From Application With CRC
Kojto	90:cb3d968589d8	2283	* */
Kojto	90:cb3d968589d8	2284	uint32_t RESERVED1 : 22; /!< [31:10] /
Kojto	90:cb3d968589d8	2285	} B;
Kojto	90:cb3d968589d8	2286	} hw_enet_tcr_t;
Kojto	90:cb3d968589d8	2287
Kojto	90:cb3d968589d8	2288	/*!
Kojto	90:cb3d968589d8	2289	* @name Constants and macros for entire ENET_TCR register
Kojto	90:cb3d968589d8	2290	*/
Kojto	90:cb3d968589d8	2291	/@{/
Kojto	90:cb3d968589d8	2292	#define HW_ENET_TCR_ADDR(x) ((x) + 0xC4U)
Kojto	90:cb3d968589d8	2293
Kojto	90:cb3d968589d8	2294	#define HW_ENET_TCR(x) ((__IO hw_enet_tcr_t ) HW_ENET_TCR_ADDR(x))
Kojto	90:cb3d968589d8	2295	#define HW_ENET_TCR_RD(x) (HW_ENET_TCR(x).U)
Kojto	90:cb3d968589d8	2296	#define HW_ENET_TCR_WR(x, v) (HW_ENET_TCR(x).U = (v))
Kojto	90:cb3d968589d8	2297	#define HW_ENET_TCR_SET(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2298	#define HW_ENET_TCR_CLR(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2299	#define HW_ENET_TCR_TOG(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2300	/@}/
Kojto	90:cb3d968589d8	2301
Kojto	90:cb3d968589d8	2302	/*
Kojto	90:cb3d968589d8	2303	* Constants & macros for individual ENET_TCR bitfields
Kojto	90:cb3d968589d8	2304	*/
Kojto	90:cb3d968589d8	2305
Kojto	90:cb3d968589d8	2306	/*!
Kojto	90:cb3d968589d8	2307	* @name Register ENET_TCR, field GTS[0] (RW)
Kojto	90:cb3d968589d8	2308	*
Kojto	90:cb3d968589d8	2309	* When this field is set, MAC stops transmission after any frame currently
Kojto	90:cb3d968589d8	2310	* transmitted is complete and EIR[GRA] is set. If frame transmission is not
Kojto	90:cb3d968589d8	2311	* currently underway, the GRA interrupt is asserted immediately. After transmission
Kojto	90:cb3d968589d8	2312	* finishes, clear GTS to restart. The next frame in the transmit FIFO is then
Kojto	90:cb3d968589d8	2313	* transmitted. If an early collision occurs during transmission when GTS is set,
Kojto	90:cb3d968589d8	2314	* transmission stops after the collision. The frame is transmitted again after GTS is
Kojto	90:cb3d968589d8	2315	* cleared. There may be old frames in the transmit FIFO that transmit when GTS
Kojto	90:cb3d968589d8	2316	* is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
Kojto	90:cb3d968589d8	2317	*/
Kojto	90:cb3d968589d8	2318	/@{/
Kojto	90:cb3d968589d8	2319	#define BP_ENET_TCR_GTS (0U) /!< Bit position for ENET_TCR_GTS. /
Kojto	90:cb3d968589d8	2320	#define BM_ENET_TCR_GTS (0x00000001U) /!< Bit mask for ENET_TCR_GTS. /
Kojto	90:cb3d968589d8	2321	#define BS_ENET_TCR_GTS (1U) /!< Bit field size in bits for ENET_TCR_GTS. /
Kojto	90:cb3d968589d8	2322
Kojto	90:cb3d968589d8	2323	/! @brief Read current value of the ENET_TCR_GTS field. /
Kojto	90:cb3d968589d8	2324	#define BR_ENET_TCR_GTS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS))
Kojto	90:cb3d968589d8	2325
Kojto	90:cb3d968589d8	2326	/! @brief Format value for bitfield ENET_TCR_GTS. /
Kojto	90:cb3d968589d8	2327	#define BF_ENET_TCR_GTS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_GTS) & BM_ENET_TCR_GTS)
Kojto	90:cb3d968589d8	2328
Kojto	90:cb3d968589d8	2329	/! @brief Set the GTS field to a new value. /
Kojto	90:cb3d968589d8	2330	#define BW_ENET_TCR_GTS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS) = (v))
Kojto	90:cb3d968589d8	2331	/@}/
Kojto	90:cb3d968589d8	2332
Kojto	90:cb3d968589d8	2333	/*!
Kojto	90:cb3d968589d8	2334	* @name Register ENET_TCR, field FDEN[2] (RW)
Kojto	90:cb3d968589d8	2335	*
Kojto	90:cb3d968589d8	2336	* If this field is set, frames transmit independent of carrier sense and
Kojto	90:cb3d968589d8	2337	* collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
Kojto	90:cb3d968589d8	2338	*/
Kojto	90:cb3d968589d8	2339	/@{/
Kojto	90:cb3d968589d8	2340	#define BP_ENET_TCR_FDEN (2U) /!< Bit position for ENET_TCR_FDEN. /
Kojto	90:cb3d968589d8	2341	#define BM_ENET_TCR_FDEN (0x00000004U) /!< Bit mask for ENET_TCR_FDEN. /
Kojto	90:cb3d968589d8	2342	#define BS_ENET_TCR_FDEN (1U) /!< Bit field size in bits for ENET_TCR_FDEN. /
Kojto	90:cb3d968589d8	2343
Kojto	90:cb3d968589d8	2344	/! @brief Read current value of the ENET_TCR_FDEN field. /
Kojto	90:cb3d968589d8	2345	#define BR_ENET_TCR_FDEN(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN))
Kojto	90:cb3d968589d8	2346
Kojto	90:cb3d968589d8	2347	/! @brief Format value for bitfield ENET_TCR_FDEN. /
Kojto	90:cb3d968589d8	2348	#define BF_ENET_TCR_FDEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_FDEN) & BM_ENET_TCR_FDEN)
Kojto	90:cb3d968589d8	2349
Kojto	90:cb3d968589d8	2350	/! @brief Set the FDEN field to a new value. /
Kojto	90:cb3d968589d8	2351	#define BW_ENET_TCR_FDEN(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN) = (v))
Kojto	90:cb3d968589d8	2352	/@}/
Kojto	90:cb3d968589d8	2353
Kojto	90:cb3d968589d8	2354	/*!
Kojto	90:cb3d968589d8	2355	* @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
Kojto	90:cb3d968589d8	2356	*
Kojto	90:cb3d968589d8	2357	* Pauses frame transmission. When this field is set, EIR[GRA] is set. With
Kojto	90:cb3d968589d8	2358	* transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
Kojto	90:cb3d968589d8	2359	* Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
Kojto	90:cb3d968589d8	2360	* transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
Kojto	90:cb3d968589d8	2361	* the MAC may continue transmitting a MAC control PAUSE frame.
Kojto	90:cb3d968589d8	2362	*
Kojto	90:cb3d968589d8	2363	* Values:
Kojto	90:cb3d968589d8	2364	* - 0 - No PAUSE frame transmitted.
Kojto	90:cb3d968589d8	2365	* - 1 - The MAC stops transmission of data frames after the current
Kojto	90:cb3d968589d8	2366	* transmission is complete.
Kojto	90:cb3d968589d8	2367	*/
Kojto	90:cb3d968589d8	2368	/@{/
Kojto	90:cb3d968589d8	2369	#define BP_ENET_TCR_TFC_PAUSE (3U) /!< Bit position for ENET_TCR_TFC_PAUSE. /
Kojto	90:cb3d968589d8	2370	#define BM_ENET_TCR_TFC_PAUSE (0x00000008U) /!< Bit mask for ENET_TCR_TFC_PAUSE. /
Kojto	90:cb3d968589d8	2371	#define BS_ENET_TCR_TFC_PAUSE (1U) /!< Bit field size in bits for ENET_TCR_TFC_PAUSE. /
Kojto	90:cb3d968589d8	2372
Kojto	90:cb3d968589d8	2373	/! @brief Read current value of the ENET_TCR_TFC_PAUSE field. /
Kojto	90:cb3d968589d8	2374	#define BR_ENET_TCR_TFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE))
Kojto	90:cb3d968589d8	2375
Kojto	90:cb3d968589d8	2376	/! @brief Format value for bitfield ENET_TCR_TFC_PAUSE. /
Kojto	90:cb3d968589d8	2377	#define BF_ENET_TCR_TFC_PAUSE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_TFC_PAUSE) & BM_ENET_TCR_TFC_PAUSE)
Kojto	90:cb3d968589d8	2378
Kojto	90:cb3d968589d8	2379	/! @brief Set the TFC_PAUSE field to a new value. /
Kojto	90:cb3d968589d8	2380	#define BW_ENET_TCR_TFC_PAUSE(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE) = (v))
Kojto	90:cb3d968589d8	2381	/@}/
Kojto	90:cb3d968589d8	2382
Kojto	90:cb3d968589d8	2383	/*!
Kojto	90:cb3d968589d8	2384	* @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
Kojto	90:cb3d968589d8	2385	*
Kojto	90:cb3d968589d8	2386	* This status field is set when a full-duplex flow control pause frame is
Kojto	90:cb3d968589d8	2387	* received and the transmitter pauses for the duration defined in this pause frame.
Kojto	90:cb3d968589d8	2388	* This field automatically clears when the pause duration is complete.
Kojto	90:cb3d968589d8	2389	*/
Kojto	90:cb3d968589d8	2390	/@{/
Kojto	90:cb3d968589d8	2391	#define BP_ENET_TCR_RFC_PAUSE (4U) /!< Bit position for ENET_TCR_RFC_PAUSE. /
Kojto	90:cb3d968589d8	2392	#define BM_ENET_TCR_RFC_PAUSE (0x00000010U) /!< Bit mask for ENET_TCR_RFC_PAUSE. /
Kojto	90:cb3d968589d8	2393	#define BS_ENET_TCR_RFC_PAUSE (1U) /!< Bit field size in bits for ENET_TCR_RFC_PAUSE. /
Kojto	90:cb3d968589d8	2394
Kojto	90:cb3d968589d8	2395	/! @brief Read current value of the ENET_TCR_RFC_PAUSE field. /
Kojto	90:cb3d968589d8	2396	#define BR_ENET_TCR_RFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_RFC_PAUSE))
Kojto	90:cb3d968589d8	2397	/@}/
Kojto	90:cb3d968589d8	2398
Kojto	90:cb3d968589d8	2399	/*!
Kojto	90:cb3d968589d8	2400	* @name Register ENET_TCR, field ADDSEL[7:5] (RW)
Kojto	90:cb3d968589d8	2401	*
Kojto	90:cb3d968589d8	2402	* If ADDINS is set, indicates the MAC address that overwrites the source MAC
Kojto	90:cb3d968589d8	2403	* address.
Kojto	90:cb3d968589d8	2404	*
Kojto	90:cb3d968589d8	2405	* Values:
Kojto	90:cb3d968589d8	2406	* - 000 - Node MAC address programmed on PADDR1/2 registers.
Kojto	90:cb3d968589d8	2407	* - 100 - Reserved.
Kojto	90:cb3d968589d8	2408	* - 101 - Reserved.
Kojto	90:cb3d968589d8	2409	* - 110 - Reserved.
Kojto	90:cb3d968589d8	2410	*/
Kojto	90:cb3d968589d8	2411	/@{/
Kojto	90:cb3d968589d8	2412	#define BP_ENET_TCR_ADDSEL (5U) /!< Bit position for ENET_TCR_ADDSEL. /
Kojto	90:cb3d968589d8	2413	#define BM_ENET_TCR_ADDSEL (0x000000E0U) /!< Bit mask for ENET_TCR_ADDSEL. /
Kojto	90:cb3d968589d8	2414	#define BS_ENET_TCR_ADDSEL (3U) /!< Bit field size in bits for ENET_TCR_ADDSEL. /
Kojto	90:cb3d968589d8	2415
Kojto	90:cb3d968589d8	2416	/! @brief Read current value of the ENET_TCR_ADDSEL field. /
Kojto	90:cb3d968589d8	2417	#define BR_ENET_TCR_ADDSEL(x) (HW_ENET_TCR(x).B.ADDSEL)
Kojto	90:cb3d968589d8	2418
Kojto	90:cb3d968589d8	2419	/! @brief Format value for bitfield ENET_TCR_ADDSEL. /
Kojto	90:cb3d968589d8	2420	#define BF_ENET_TCR_ADDSEL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_ADDSEL) & BM_ENET_TCR_ADDSEL)
Kojto	90:cb3d968589d8	2421
Kojto	90:cb3d968589d8	2422	/! @brief Set the ADDSEL field to a new value. /
Kojto	90:cb3d968589d8	2423	#define BW_ENET_TCR_ADDSEL(x, v) (HW_ENET_TCR_WR(x, (HW_ENET_TCR_RD(x) & ~BM_ENET_TCR_ADDSEL) \| BF_ENET_TCR_ADDSEL(v)))
Kojto	90:cb3d968589d8	2424	/@}/
Kojto	90:cb3d968589d8	2425
Kojto	90:cb3d968589d8	2426	/*!
Kojto	90:cb3d968589d8	2427	* @name Register ENET_TCR, field ADDINS[8] (RW)
Kojto	90:cb3d968589d8	2428	*
Kojto	90:cb3d968589d8	2429	* Values:
Kojto	90:cb3d968589d8	2430	* - 0 - The source MAC address is not modified by the MAC.
Kojto	90:cb3d968589d8	2431	* - 1 - The MAC overwrites the source MAC address with the programmed MAC
Kojto	90:cb3d968589d8	2432	* address according to ADDSEL.
Kojto	90:cb3d968589d8	2433	*/
Kojto	90:cb3d968589d8	2434	/@{/
Kojto	90:cb3d968589d8	2435	#define BP_ENET_TCR_ADDINS (8U) /!< Bit position for ENET_TCR_ADDINS. /
Kojto	90:cb3d968589d8	2436	#define BM_ENET_TCR_ADDINS (0x00000100U) /!< Bit mask for ENET_TCR_ADDINS. /
Kojto	90:cb3d968589d8	2437	#define BS_ENET_TCR_ADDINS (1U) /!< Bit field size in bits for ENET_TCR_ADDINS. /
Kojto	90:cb3d968589d8	2438
Kojto	90:cb3d968589d8	2439	/! @brief Read current value of the ENET_TCR_ADDINS field. /
Kojto	90:cb3d968589d8	2440	#define BR_ENET_TCR_ADDINS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS))
Kojto	90:cb3d968589d8	2441
Kojto	90:cb3d968589d8	2442	/! @brief Format value for bitfield ENET_TCR_ADDINS. /
Kojto	90:cb3d968589d8	2443	#define BF_ENET_TCR_ADDINS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_ADDINS) & BM_ENET_TCR_ADDINS)
Kojto	90:cb3d968589d8	2444
Kojto	90:cb3d968589d8	2445	/! @brief Set the ADDINS field to a new value. /
Kojto	90:cb3d968589d8	2446	#define BW_ENET_TCR_ADDINS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS) = (v))
Kojto	90:cb3d968589d8	2447	/@}/
Kojto	90:cb3d968589d8	2448
Kojto	90:cb3d968589d8	2449	/*!
Kojto	90:cb3d968589d8	2450	* @name Register ENET_TCR, field CRCFWD[9] (RW)
Kojto	90:cb3d968589d8	2451	*
Kojto	90:cb3d968589d8	2452	* Values:
Kojto	90:cb3d968589d8	2453	* - 0 - TxBD[TC] controls whether the frame has a CRC from the application.
Kojto	90:cb3d968589d8	2454	* - 1 - The transmitter does not append any CRC to transmitted frames, as it is
Kojto	90:cb3d968589d8	2455	* expecting a frame with CRC from the application.
Kojto	90:cb3d968589d8	2456	*/
Kojto	90:cb3d968589d8	2457	/@{/
Kojto	90:cb3d968589d8	2458	#define BP_ENET_TCR_CRCFWD (9U) /!< Bit position for ENET_TCR_CRCFWD. /
Kojto	90:cb3d968589d8	2459	#define BM_ENET_TCR_CRCFWD (0x00000200U) /!< Bit mask for ENET_TCR_CRCFWD. /
Kojto	90:cb3d968589d8	2460	#define BS_ENET_TCR_CRCFWD (1U) /!< Bit field size in bits for ENET_TCR_CRCFWD. /
Kojto	90:cb3d968589d8	2461
Kojto	90:cb3d968589d8	2462	/! @brief Read current value of the ENET_TCR_CRCFWD field. /
Kojto	90:cb3d968589d8	2463	#define BR_ENET_TCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD))
Kojto	90:cb3d968589d8	2464
Kojto	90:cb3d968589d8	2465	/! @brief Format value for bitfield ENET_TCR_CRCFWD. /
Kojto	90:cb3d968589d8	2466	#define BF_ENET_TCR_CRCFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_CRCFWD) & BM_ENET_TCR_CRCFWD)
Kojto	90:cb3d968589d8	2467
Kojto	90:cb3d968589d8	2468	/! @brief Set the CRCFWD field to a new value. /
Kojto	90:cb3d968589d8	2469	#define BW_ENET_TCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD) = (v))
Kojto	90:cb3d968589d8	2470	/@}/
Kojto	90:cb3d968589d8	2471
Kojto	90:cb3d968589d8	2472	/*******************************************************************************
Kojto	90:cb3d968589d8	2473	* HW_ENET_PALR - Physical Address Lower Register
Kojto	90:cb3d968589d8	2474	******************************************************************************/
Kojto	90:cb3d968589d8	2475
Kojto	90:cb3d968589d8	2476	/*!
Kojto	90:cb3d968589d8	2477	* @brief HW_ENET_PALR - Physical Address Lower Register (RW)
Kojto	90:cb3d968589d8	2478	*
Kojto	90:cb3d968589d8	2479	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2480	*
Kojto	90:cb3d968589d8	2481	* PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
Kojto	90:cb3d968589d8	2482	* in the address recognition process to compare with the destination address
Kojto	90:cb3d968589d8	2483	* (DA) field of receive frames with an individual DA. In addition, this register
Kojto	90:cb3d968589d8	2484	* is used in bytes 0 through 3 of the six-byte source address field when
Kojto	90:cb3d968589d8	2485	* transmitting PAUSE frames. This register is not reset and you must initialize it.
Kojto	90:cb3d968589d8	2486	*/
Kojto	90:cb3d968589d8	2487	typedef union _hw_enet_palr
Kojto	90:cb3d968589d8	2488	{
Kojto	90:cb3d968589d8	2489	uint32_t U;
Kojto	90:cb3d968589d8	2490	struct _hw_enet_palr_bitfields
Kojto	90:cb3d968589d8	2491	{
Kojto	90:cb3d968589d8	2492	uint32_t PADDR1 : 32; /!< [31:0] Pause Address /
Kojto	90:cb3d968589d8	2493	} B;
Kojto	90:cb3d968589d8	2494	} hw_enet_palr_t;
Kojto	90:cb3d968589d8	2495
Kojto	90:cb3d968589d8	2496	/*!
Kojto	90:cb3d968589d8	2497	* @name Constants and macros for entire ENET_PALR register
Kojto	90:cb3d968589d8	2498	*/
Kojto	90:cb3d968589d8	2499	/@{/
Kojto	90:cb3d968589d8	2500	#define HW_ENET_PALR_ADDR(x) ((x) + 0xE4U)
Kojto	90:cb3d968589d8	2501
Kojto	90:cb3d968589d8	2502	#define HW_ENET_PALR(x) ((__IO hw_enet_palr_t ) HW_ENET_PALR_ADDR(x))
Kojto	90:cb3d968589d8	2503	#define HW_ENET_PALR_RD(x) (HW_ENET_PALR(x).U)
Kojto	90:cb3d968589d8	2504	#define HW_ENET_PALR_WR(x, v) (HW_ENET_PALR(x).U = (v))
Kojto	90:cb3d968589d8	2505	#define HW_ENET_PALR_SET(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2506	#define HW_ENET_PALR_CLR(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2507	#define HW_ENET_PALR_TOG(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2508	/@}/
Kojto	90:cb3d968589d8	2509
Kojto	90:cb3d968589d8	2510	/*
Kojto	90:cb3d968589d8	2511	* Constants & macros for individual ENET_PALR bitfields
Kojto	90:cb3d968589d8	2512	*/
Kojto	90:cb3d968589d8	2513
Kojto	90:cb3d968589d8	2514	/*!
Kojto	90:cb3d968589d8	2515	* @name Register ENET_PALR, field PADDR1[31:0] (RW)
Kojto	90:cb3d968589d8	2516	*
Kojto	90:cb3d968589d8	2517	* Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the
Kojto	90:cb3d968589d8	2518	* 6-byte individual address are used for exact match and the source address
Kojto	90:cb3d968589d8	2519	* field in PAUSE frames.
Kojto	90:cb3d968589d8	2520	*/
Kojto	90:cb3d968589d8	2521	/@{/
Kojto	90:cb3d968589d8	2522	#define BP_ENET_PALR_PADDR1 (0U) /!< Bit position for ENET_PALR_PADDR1. /
Kojto	90:cb3d968589d8	2523	#define BM_ENET_PALR_PADDR1 (0xFFFFFFFFU) /!< Bit mask for ENET_PALR_PADDR1. /
Kojto	90:cb3d968589d8	2524	#define BS_ENET_PALR_PADDR1 (32U) /!< Bit field size in bits for ENET_PALR_PADDR1. /
Kojto	90:cb3d968589d8	2525
Kojto	90:cb3d968589d8	2526	/! @brief Read current value of the ENET_PALR_PADDR1 field. /
Kojto	90:cb3d968589d8	2527	#define BR_ENET_PALR_PADDR1(x) (HW_ENET_PALR(x).U)
Kojto	90:cb3d968589d8	2528
Kojto	90:cb3d968589d8	2529	/! @brief Format value for bitfield ENET_PALR_PADDR1. /
Kojto	90:cb3d968589d8	2530	#define BF_ENET_PALR_PADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_PALR_PADDR1) & BM_ENET_PALR_PADDR1)
Kojto	90:cb3d968589d8	2531
Kojto	90:cb3d968589d8	2532	/! @brief Set the PADDR1 field to a new value. /
Kojto	90:cb3d968589d8	2533	#define BW_ENET_PALR_PADDR1(x, v) (HW_ENET_PALR_WR(x, v))
Kojto	90:cb3d968589d8	2534	/@}/
Kojto	90:cb3d968589d8	2535
Kojto	90:cb3d968589d8	2536	/*******************************************************************************
Kojto	90:cb3d968589d8	2537	* HW_ENET_PAUR - Physical Address Upper Register
Kojto	90:cb3d968589d8	2538	******************************************************************************/
Kojto	90:cb3d968589d8	2539
Kojto	90:cb3d968589d8	2540	/*!
Kojto	90:cb3d968589d8	2541	* @brief HW_ENET_PAUR - Physical Address Upper Register (RW)
Kojto	90:cb3d968589d8	2542	*
Kojto	90:cb3d968589d8	2543	* Reset value: 0x00008808U
Kojto	90:cb3d968589d8	2544	*
Kojto	90:cb3d968589d8	2545	* PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
Kojto	90:cb3d968589d8	2546	* the address recognition process to compare with the destination address (DA)
Kojto	90:cb3d968589d8	2547	* field of receive frames with an individual DA. In addition, this register is
Kojto	90:cb3d968589d8	2548	* used in bytes 4 and 5 of the six-byte source address field when transmitting
Kojto	90:cb3d968589d8	2549	* PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
Kojto	90:cb3d968589d8	2550	* transmission of PAUSE frames. The upper 16 bits of this register are not reset and
Kojto	90:cb3d968589d8	2551	* you must initialize it.
Kojto	90:cb3d968589d8	2552	*/
Kojto	90:cb3d968589d8	2553	typedef union _hw_enet_paur
Kojto	90:cb3d968589d8	2554	{
Kojto	90:cb3d968589d8	2555	uint32_t U;
Kojto	90:cb3d968589d8	2556	struct _hw_enet_paur_bitfields
Kojto	90:cb3d968589d8	2557	{
Kojto	90:cb3d968589d8	2558	uint32_t TYPE : 16; /!< [15:0] Type Field In PAUSE Frames /
Kojto	90:cb3d968589d8	2559	uint32_t PADDR2 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	2560	} B;
Kojto	90:cb3d968589d8	2561	} hw_enet_paur_t;
Kojto	90:cb3d968589d8	2562
Kojto	90:cb3d968589d8	2563	/*!
Kojto	90:cb3d968589d8	2564	* @name Constants and macros for entire ENET_PAUR register
Kojto	90:cb3d968589d8	2565	*/
Kojto	90:cb3d968589d8	2566	/@{/
Kojto	90:cb3d968589d8	2567	#define HW_ENET_PAUR_ADDR(x) ((x) + 0xE8U)
Kojto	90:cb3d968589d8	2568
Kojto	90:cb3d968589d8	2569	#define HW_ENET_PAUR(x) ((__IO hw_enet_paur_t ) HW_ENET_PAUR_ADDR(x))
Kojto	90:cb3d968589d8	2570	#define HW_ENET_PAUR_RD(x) (HW_ENET_PAUR(x).U)
Kojto	90:cb3d968589d8	2571	#define HW_ENET_PAUR_WR(x, v) (HW_ENET_PAUR(x).U = (v))
Kojto	90:cb3d968589d8	2572	#define HW_ENET_PAUR_SET(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2573	#define HW_ENET_PAUR_CLR(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2574	#define HW_ENET_PAUR_TOG(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2575	/@}/
Kojto	90:cb3d968589d8	2576
Kojto	90:cb3d968589d8	2577	/*
Kojto	90:cb3d968589d8	2578	* Constants & macros for individual ENET_PAUR bitfields
Kojto	90:cb3d968589d8	2579	*/
Kojto	90:cb3d968589d8	2580
Kojto	90:cb3d968589d8	2581	/*!
Kojto	90:cb3d968589d8	2582	* @name Register ENET_PAUR, field TYPE[15:0] (RO)
Kojto	90:cb3d968589d8	2583	*
Kojto	90:cb3d968589d8	2584	* These fields have a constant value of 0x8808.
Kojto	90:cb3d968589d8	2585	*/
Kojto	90:cb3d968589d8	2586	/@{/
Kojto	90:cb3d968589d8	2587	#define BP_ENET_PAUR_TYPE (0U) /!< Bit position for ENET_PAUR_TYPE. /
Kojto	90:cb3d968589d8	2588	#define BM_ENET_PAUR_TYPE (0x0000FFFFU) /!< Bit mask for ENET_PAUR_TYPE. /
Kojto	90:cb3d968589d8	2589	#define BS_ENET_PAUR_TYPE (16U) /!< Bit field size in bits for ENET_PAUR_TYPE. /
Kojto	90:cb3d968589d8	2590
Kojto	90:cb3d968589d8	2591	/! @brief Read current value of the ENET_PAUR_TYPE field. /
Kojto	90:cb3d968589d8	2592	#define BR_ENET_PAUR_TYPE(x) (HW_ENET_PAUR(x).B.TYPE)
Kojto	90:cb3d968589d8	2593	/@}/
Kojto	90:cb3d968589d8	2594
Kojto	90:cb3d968589d8	2595	/*!
Kojto	90:cb3d968589d8	2596	* @name Register ENET_PAUR, field PADDR2[31:16] (RW)
Kojto	90:cb3d968589d8	2597	*
Kojto	90:cb3d968589d8	2598	* Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
Kojto	90:cb3d968589d8	2599	* for exact match, and the source address field in PAUSE frames.
Kojto	90:cb3d968589d8	2600	*/
Kojto	90:cb3d968589d8	2601	/@{/
Kojto	90:cb3d968589d8	2602	#define BP_ENET_PAUR_PADDR2 (16U) /!< Bit position for ENET_PAUR_PADDR2. /
Kojto	90:cb3d968589d8	2603	#define BM_ENET_PAUR_PADDR2 (0xFFFF0000U) /!< Bit mask for ENET_PAUR_PADDR2. /
Kojto	90:cb3d968589d8	2604	#define BS_ENET_PAUR_PADDR2 (16U) /!< Bit field size in bits for ENET_PAUR_PADDR2. /
Kojto	90:cb3d968589d8	2605
Kojto	90:cb3d968589d8	2606	/! @brief Read current value of the ENET_PAUR_PADDR2 field. /
Kojto	90:cb3d968589d8	2607	#define BR_ENET_PAUR_PADDR2(x) (HW_ENET_PAUR(x).B.PADDR2)
Kojto	90:cb3d968589d8	2608
Kojto	90:cb3d968589d8	2609	/! @brief Format value for bitfield ENET_PAUR_PADDR2. /
Kojto	90:cb3d968589d8	2610	#define BF_ENET_PAUR_PADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_PAUR_PADDR2) & BM_ENET_PAUR_PADDR2)
Kojto	90:cb3d968589d8	2611
Kojto	90:cb3d968589d8	2612	/! @brief Set the PADDR2 field to a new value. /
Kojto	90:cb3d968589d8	2613	#define BW_ENET_PAUR_PADDR2(x, v) (HW_ENET_PAUR_WR(x, (HW_ENET_PAUR_RD(x) & ~BM_ENET_PAUR_PADDR2) \| BF_ENET_PAUR_PADDR2(v)))
Kojto	90:cb3d968589d8	2614	/@}/
Kojto	90:cb3d968589d8	2615
Kojto	90:cb3d968589d8	2616	/*******************************************************************************
Kojto	90:cb3d968589d8	2617	* HW_ENET_OPD - Opcode/Pause Duration Register
Kojto	90:cb3d968589d8	2618	******************************************************************************/
Kojto	90:cb3d968589d8	2619
Kojto	90:cb3d968589d8	2620	/*!
Kojto	90:cb3d968589d8	2621	* @brief HW_ENET_OPD - Opcode/Pause Duration Register (RW)
Kojto	90:cb3d968589d8	2622	*
Kojto	90:cb3d968589d8	2623	* Reset value: 0x00010000U
Kojto	90:cb3d968589d8	2624	*
Kojto	90:cb3d968589d8	2625	* OPD is read/write accessible. This register contains the 16-bit opcode and
Kojto	90:cb3d968589d8	2626	* 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
Kojto	90:cb3d968589d8	2627	* field is a constant value, 0x0001. When another node detects a PAUSE frame,
Kojto	90:cb3d968589d8	2628	* that node pauses transmission for the duration specified in the pause duration
Kojto	90:cb3d968589d8	2629	* field. The lower 16 bits of this register are not reset and you must initialize
Kojto	90:cb3d968589d8	2630	* it.
Kojto	90:cb3d968589d8	2631	*/
Kojto	90:cb3d968589d8	2632	typedef union _hw_enet_opd
Kojto	90:cb3d968589d8	2633	{
Kojto	90:cb3d968589d8	2634	uint32_t U;
Kojto	90:cb3d968589d8	2635	struct _hw_enet_opd_bitfields
Kojto	90:cb3d968589d8	2636	{
Kojto	90:cb3d968589d8	2637	uint32_t PAUSE_DUR : 16; /!< [15:0] Pause Duration /
Kojto	90:cb3d968589d8	2638	uint32_t OPCODE : 16; /!< [31:16] Opcode Field In PAUSE Frames /
Kojto	90:cb3d968589d8	2639	} B;
Kojto	90:cb3d968589d8	2640	} hw_enet_opd_t;
Kojto	90:cb3d968589d8	2641
Kojto	90:cb3d968589d8	2642	/*!
Kojto	90:cb3d968589d8	2643	* @name Constants and macros for entire ENET_OPD register
Kojto	90:cb3d968589d8	2644	*/
Kojto	90:cb3d968589d8	2645	/@{/
Kojto	90:cb3d968589d8	2646	#define HW_ENET_OPD_ADDR(x) ((x) + 0xECU)
Kojto	90:cb3d968589d8	2647
Kojto	90:cb3d968589d8	2648	#define HW_ENET_OPD(x) ((__IO hw_enet_opd_t ) HW_ENET_OPD_ADDR(x))
Kojto	90:cb3d968589d8	2649	#define HW_ENET_OPD_RD(x) (HW_ENET_OPD(x).U)
Kojto	90:cb3d968589d8	2650	#define HW_ENET_OPD_WR(x, v) (HW_ENET_OPD(x).U = (v))
Kojto	90:cb3d968589d8	2651	#define HW_ENET_OPD_SET(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2652	#define HW_ENET_OPD_CLR(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2653	#define HW_ENET_OPD_TOG(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2654	/@}/
Kojto	90:cb3d968589d8	2655
Kojto	90:cb3d968589d8	2656	/*
Kojto	90:cb3d968589d8	2657	* Constants & macros for individual ENET_OPD bitfields
Kojto	90:cb3d968589d8	2658	*/
Kojto	90:cb3d968589d8	2659
Kojto	90:cb3d968589d8	2660	/*!
Kojto	90:cb3d968589d8	2661	* @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
Kojto	90:cb3d968589d8	2662	*
Kojto	90:cb3d968589d8	2663	* Pause duration field used in PAUSE frames.
Kojto	90:cb3d968589d8	2664	*/
Kojto	90:cb3d968589d8	2665	/@{/
Kojto	90:cb3d968589d8	2666	#define BP_ENET_OPD_PAUSE_DUR (0U) /!< Bit position for ENET_OPD_PAUSE_DUR. /
Kojto	90:cb3d968589d8	2667	#define BM_ENET_OPD_PAUSE_DUR (0x0000FFFFU) /!< Bit mask for ENET_OPD_PAUSE_DUR. /
Kojto	90:cb3d968589d8	2668	#define BS_ENET_OPD_PAUSE_DUR (16U) /!< Bit field size in bits for ENET_OPD_PAUSE_DUR. /
Kojto	90:cb3d968589d8	2669
Kojto	90:cb3d968589d8	2670	/! @brief Read current value of the ENET_OPD_PAUSE_DUR field. /
Kojto	90:cb3d968589d8	2671	#define BR_ENET_OPD_PAUSE_DUR(x) (HW_ENET_OPD(x).B.PAUSE_DUR)
Kojto	90:cb3d968589d8	2672
Kojto	90:cb3d968589d8	2673	/! @brief Format value for bitfield ENET_OPD_PAUSE_DUR. /
Kojto	90:cb3d968589d8	2674	#define BF_ENET_OPD_PAUSE_DUR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_OPD_PAUSE_DUR) & BM_ENET_OPD_PAUSE_DUR)
Kojto	90:cb3d968589d8	2675
Kojto	90:cb3d968589d8	2676	/! @brief Set the PAUSE_DUR field to a new value. /
Kojto	90:cb3d968589d8	2677	#define BW_ENET_OPD_PAUSE_DUR(x, v) (HW_ENET_OPD_WR(x, (HW_ENET_OPD_RD(x) & ~BM_ENET_OPD_PAUSE_DUR) \| BF_ENET_OPD_PAUSE_DUR(v)))
Kojto	90:cb3d968589d8	2678	/@}/
Kojto	90:cb3d968589d8	2679
Kojto	90:cb3d968589d8	2680	/*!
Kojto	90:cb3d968589d8	2681	* @name Register ENET_OPD, field OPCODE[31:16] (RO)
Kojto	90:cb3d968589d8	2682	*
Kojto	90:cb3d968589d8	2683	* These fields have a constant value of 0x0001.
Kojto	90:cb3d968589d8	2684	*/
Kojto	90:cb3d968589d8	2685	/@{/
Kojto	90:cb3d968589d8	2686	#define BP_ENET_OPD_OPCODE (16U) /!< Bit position for ENET_OPD_OPCODE. /
Kojto	90:cb3d968589d8	2687	#define BM_ENET_OPD_OPCODE (0xFFFF0000U) /!< Bit mask for ENET_OPD_OPCODE. /
Kojto	90:cb3d968589d8	2688	#define BS_ENET_OPD_OPCODE (16U) /!< Bit field size in bits for ENET_OPD_OPCODE. /
Kojto	90:cb3d968589d8	2689
Kojto	90:cb3d968589d8	2690	/! @brief Read current value of the ENET_OPD_OPCODE field. /
Kojto	90:cb3d968589d8	2691	#define BR_ENET_OPD_OPCODE(x) (HW_ENET_OPD(x).B.OPCODE)
Kojto	90:cb3d968589d8	2692	/@}/
Kojto	90:cb3d968589d8	2693
Kojto	90:cb3d968589d8	2694	/*******************************************************************************
Kojto	90:cb3d968589d8	2695	* HW_ENET_IAUR - Descriptor Individual Upper Address Register
Kojto	90:cb3d968589d8	2696	******************************************************************************/
Kojto	90:cb3d968589d8	2697
Kojto	90:cb3d968589d8	2698	/*!
Kojto	90:cb3d968589d8	2699	* @brief HW_ENET_IAUR - Descriptor Individual Upper Address Register (RW)
Kojto	90:cb3d968589d8	2700	*
Kojto	90:cb3d968589d8	2701	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2702	*
Kojto	90:cb3d968589d8	2703	* IAUR contains the upper 32 bits of the 64-bit individual address hash table.
Kojto	90:cb3d968589d8	2704	* The address recognition process uses this table to check for a possible match
Kojto	90:cb3d968589d8	2705	* with the destination address (DA) field of receive frames with an individual
Kojto	90:cb3d968589d8	2706	* DA. This register is not reset and you must initialize it.
Kojto	90:cb3d968589d8	2707	*/
Kojto	90:cb3d968589d8	2708	typedef union _hw_enet_iaur
Kojto	90:cb3d968589d8	2709	{
Kojto	90:cb3d968589d8	2710	uint32_t U;
Kojto	90:cb3d968589d8	2711	struct _hw_enet_iaur_bitfields
Kojto	90:cb3d968589d8	2712	{
Kojto	90:cb3d968589d8	2713	uint32_t IADDR1 : 32; /!< [31:0] /
Kojto	90:cb3d968589d8	2714	} B;
Kojto	90:cb3d968589d8	2715	} hw_enet_iaur_t;
Kojto	90:cb3d968589d8	2716
Kojto	90:cb3d968589d8	2717	/*!
Kojto	90:cb3d968589d8	2718	* @name Constants and macros for entire ENET_IAUR register
Kojto	90:cb3d968589d8	2719	*/
Kojto	90:cb3d968589d8	2720	/@{/
Kojto	90:cb3d968589d8	2721	#define HW_ENET_IAUR_ADDR(x) ((x) + 0x118U)
Kojto	90:cb3d968589d8	2722
Kojto	90:cb3d968589d8	2723	#define HW_ENET_IAUR(x) ((__IO hw_enet_iaur_t ) HW_ENET_IAUR_ADDR(x))
Kojto	90:cb3d968589d8	2724	#define HW_ENET_IAUR_RD(x) (HW_ENET_IAUR(x).U)
Kojto	90:cb3d968589d8	2725	#define HW_ENET_IAUR_WR(x, v) (HW_ENET_IAUR(x).U = (v))
Kojto	90:cb3d968589d8	2726	#define HW_ENET_IAUR_SET(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2727	#define HW_ENET_IAUR_CLR(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2728	#define HW_ENET_IAUR_TOG(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2729	/@}/
Kojto	90:cb3d968589d8	2730
Kojto	90:cb3d968589d8	2731	/*
Kojto	90:cb3d968589d8	2732	* Constants & macros for individual ENET_IAUR bitfields
Kojto	90:cb3d968589d8	2733	*/
Kojto	90:cb3d968589d8	2734
Kojto	90:cb3d968589d8	2735	/*!
Kojto	90:cb3d968589d8	2736	* @name Register ENET_IAUR, field IADDR1[31:0] (RW)
Kojto	90:cb3d968589d8	2737	*
Kojto	90:cb3d968589d8	2738	* Contains the upper 32 bits of the 64-bit hash table used in the address
Kojto	90:cb3d968589d8	2739	* recognition process for receive frames with a unicast address. Bit 31 of IADDR1
Kojto	90:cb3d968589d8	2740	* contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
Kojto	90:cb3d968589d8	2741	*/
Kojto	90:cb3d968589d8	2742	/@{/
Kojto	90:cb3d968589d8	2743	#define BP_ENET_IAUR_IADDR1 (0U) /!< Bit position for ENET_IAUR_IADDR1. /
Kojto	90:cb3d968589d8	2744	#define BM_ENET_IAUR_IADDR1 (0xFFFFFFFFU) /!< Bit mask for ENET_IAUR_IADDR1. /
Kojto	90:cb3d968589d8	2745	#define BS_ENET_IAUR_IADDR1 (32U) /!< Bit field size in bits for ENET_IAUR_IADDR1. /
Kojto	90:cb3d968589d8	2746
Kojto	90:cb3d968589d8	2747	/! @brief Read current value of the ENET_IAUR_IADDR1 field. /
Kojto	90:cb3d968589d8	2748	#define BR_ENET_IAUR_IADDR1(x) (HW_ENET_IAUR(x).U)
Kojto	90:cb3d968589d8	2749
Kojto	90:cb3d968589d8	2750	/! @brief Format value for bitfield ENET_IAUR_IADDR1. /
Kojto	90:cb3d968589d8	2751	#define BF_ENET_IAUR_IADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_IAUR_IADDR1) & BM_ENET_IAUR_IADDR1)
Kojto	90:cb3d968589d8	2752
Kojto	90:cb3d968589d8	2753	/! @brief Set the IADDR1 field to a new value. /
Kojto	90:cb3d968589d8	2754	#define BW_ENET_IAUR_IADDR1(x, v) (HW_ENET_IAUR_WR(x, v))
Kojto	90:cb3d968589d8	2755	/@}/
Kojto	90:cb3d968589d8	2756
Kojto	90:cb3d968589d8	2757	/*******************************************************************************
Kojto	90:cb3d968589d8	2758	* HW_ENET_IALR - Descriptor Individual Lower Address Register
Kojto	90:cb3d968589d8	2759	******************************************************************************/
Kojto	90:cb3d968589d8	2760
Kojto	90:cb3d968589d8	2761	/*!
Kojto	90:cb3d968589d8	2762	* @brief HW_ENET_IALR - Descriptor Individual Lower Address Register (RW)
Kojto	90:cb3d968589d8	2763	*
Kojto	90:cb3d968589d8	2764	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2765	*
Kojto	90:cb3d968589d8	2766	* IALR contains the lower 32 bits of the 64-bit individual address hash table.
Kojto	90:cb3d968589d8	2767	* The address recognition process uses this table to check for a possible match
Kojto	90:cb3d968589d8	2768	* with the DA field of receive frames with an individual DA. This register is
Kojto	90:cb3d968589d8	2769	* not reset and you must initialize it.
Kojto	90:cb3d968589d8	2770	*/
Kojto	90:cb3d968589d8	2771	typedef union _hw_enet_ialr
Kojto	90:cb3d968589d8	2772	{
Kojto	90:cb3d968589d8	2773	uint32_t U;
Kojto	90:cb3d968589d8	2774	struct _hw_enet_ialr_bitfields
Kojto	90:cb3d968589d8	2775	{
Kojto	90:cb3d968589d8	2776	uint32_t IADDR2 : 32; /!< [31:0] /
Kojto	90:cb3d968589d8	2777	} B;
Kojto	90:cb3d968589d8	2778	} hw_enet_ialr_t;
Kojto	90:cb3d968589d8	2779
Kojto	90:cb3d968589d8	2780	/*!
Kojto	90:cb3d968589d8	2781	* @name Constants and macros for entire ENET_IALR register
Kojto	90:cb3d968589d8	2782	*/
Kojto	90:cb3d968589d8	2783	/@{/
Kojto	90:cb3d968589d8	2784	#define HW_ENET_IALR_ADDR(x) ((x) + 0x11CU)
Kojto	90:cb3d968589d8	2785
Kojto	90:cb3d968589d8	2786	#define HW_ENET_IALR(x) ((__IO hw_enet_ialr_t ) HW_ENET_IALR_ADDR(x))
Kojto	90:cb3d968589d8	2787	#define HW_ENET_IALR_RD(x) (HW_ENET_IALR(x).U)
Kojto	90:cb3d968589d8	2788	#define HW_ENET_IALR_WR(x, v) (HW_ENET_IALR(x).U = (v))
Kojto	90:cb3d968589d8	2789	#define HW_ENET_IALR_SET(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2790	#define HW_ENET_IALR_CLR(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2791	#define HW_ENET_IALR_TOG(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2792	/@}/
Kojto	90:cb3d968589d8	2793
Kojto	90:cb3d968589d8	2794	/*
Kojto	90:cb3d968589d8	2795	* Constants & macros for individual ENET_IALR bitfields
Kojto	90:cb3d968589d8	2796	*/
Kojto	90:cb3d968589d8	2797
Kojto	90:cb3d968589d8	2798	/*!
Kojto	90:cb3d968589d8	2799	* @name Register ENET_IALR, field IADDR2[31:0] (RW)
Kojto	90:cb3d968589d8	2800	*
Kojto	90:cb3d968589d8	2801	* Contains the lower 32 bits of the 64-bit hash table used in the address
Kojto	90:cb3d968589d8	2802	* recognition process for receive frames with a unicast address. Bit 31 of IADDR2
Kojto	90:cb3d968589d8	2803	* contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
Kojto	90:cb3d968589d8	2804	*/
Kojto	90:cb3d968589d8	2805	/@{/
Kojto	90:cb3d968589d8	2806	#define BP_ENET_IALR_IADDR2 (0U) /!< Bit position for ENET_IALR_IADDR2. /
Kojto	90:cb3d968589d8	2807	#define BM_ENET_IALR_IADDR2 (0xFFFFFFFFU) /!< Bit mask for ENET_IALR_IADDR2. /
Kojto	90:cb3d968589d8	2808	#define BS_ENET_IALR_IADDR2 (32U) /!< Bit field size in bits for ENET_IALR_IADDR2. /
Kojto	90:cb3d968589d8	2809
Kojto	90:cb3d968589d8	2810	/! @brief Read current value of the ENET_IALR_IADDR2 field. /
Kojto	90:cb3d968589d8	2811	#define BR_ENET_IALR_IADDR2(x) (HW_ENET_IALR(x).U)
Kojto	90:cb3d968589d8	2812
Kojto	90:cb3d968589d8	2813	/! @brief Format value for bitfield ENET_IALR_IADDR2. /
Kojto	90:cb3d968589d8	2814	#define BF_ENET_IALR_IADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_IALR_IADDR2) & BM_ENET_IALR_IADDR2)
Kojto	90:cb3d968589d8	2815
Kojto	90:cb3d968589d8	2816	/! @brief Set the IADDR2 field to a new value. /
Kojto	90:cb3d968589d8	2817	#define BW_ENET_IALR_IADDR2(x, v) (HW_ENET_IALR_WR(x, v))
Kojto	90:cb3d968589d8	2818	/@}/
Kojto	90:cb3d968589d8	2819
Kojto	90:cb3d968589d8	2820	/*******************************************************************************
Kojto	90:cb3d968589d8	2821	* HW_ENET_GAUR - Descriptor Group Upper Address Register
Kojto	90:cb3d968589d8	2822	******************************************************************************/
Kojto	90:cb3d968589d8	2823
Kojto	90:cb3d968589d8	2824	/*!
Kojto	90:cb3d968589d8	2825	* @brief HW_ENET_GAUR - Descriptor Group Upper Address Register (RW)
Kojto	90:cb3d968589d8	2826	*
Kojto	90:cb3d968589d8	2827	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2828	*
Kojto	90:cb3d968589d8	2829	* GAUR contains the upper 32 bits of the 64-bit hash table used in the address
Kojto	90:cb3d968589d8	2830	* recognition process for receive frames with a multicast address. You must
Kojto	90:cb3d968589d8	2831	* initialize this register.
Kojto	90:cb3d968589d8	2832	*/
Kojto	90:cb3d968589d8	2833	typedef union _hw_enet_gaur
Kojto	90:cb3d968589d8	2834	{
Kojto	90:cb3d968589d8	2835	uint32_t U;
Kojto	90:cb3d968589d8	2836	struct _hw_enet_gaur_bitfields
Kojto	90:cb3d968589d8	2837	{
Kojto	90:cb3d968589d8	2838	uint32_t GADDR1 : 32; /!< [31:0] /
Kojto	90:cb3d968589d8	2839	} B;
Kojto	90:cb3d968589d8	2840	} hw_enet_gaur_t;
Kojto	90:cb3d968589d8	2841
Kojto	90:cb3d968589d8	2842	/*!
Kojto	90:cb3d968589d8	2843	* @name Constants and macros for entire ENET_GAUR register
Kojto	90:cb3d968589d8	2844	*/
Kojto	90:cb3d968589d8	2845	/@{/
Kojto	90:cb3d968589d8	2846	#define HW_ENET_GAUR_ADDR(x) ((x) + 0x120U)
Kojto	90:cb3d968589d8	2847
Kojto	90:cb3d968589d8	2848	#define HW_ENET_GAUR(x) ((__IO hw_enet_gaur_t ) HW_ENET_GAUR_ADDR(x))
Kojto	90:cb3d968589d8	2849	#define HW_ENET_GAUR_RD(x) (HW_ENET_GAUR(x).U)
Kojto	90:cb3d968589d8	2850	#define HW_ENET_GAUR_WR(x, v) (HW_ENET_GAUR(x).U = (v))
Kojto	90:cb3d968589d8	2851	#define HW_ENET_GAUR_SET(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2852	#define HW_ENET_GAUR_CLR(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2853	#define HW_ENET_GAUR_TOG(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2854	/@}/
Kojto	90:cb3d968589d8	2855
Kojto	90:cb3d968589d8	2856	/*
Kojto	90:cb3d968589d8	2857	* Constants & macros for individual ENET_GAUR bitfields
Kojto	90:cb3d968589d8	2858	*/
Kojto	90:cb3d968589d8	2859
Kojto	90:cb3d968589d8	2860	/*!
Kojto	90:cb3d968589d8	2861	* @name Register ENET_GAUR, field GADDR1[31:0] (RW)
Kojto	90:cb3d968589d8	2862	*
Kojto	90:cb3d968589d8	2863	* Contains the upper 32 bits of the 64-bit hash table used in the address
Kojto	90:cb3d968589d8	2864	* recognition process for receive frames with a multicast address. Bit 31 of GADDR1
Kojto	90:cb3d968589d8	2865	* contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
Kojto	90:cb3d968589d8	2866	*/
Kojto	90:cb3d968589d8	2867	/@{/
Kojto	90:cb3d968589d8	2868	#define BP_ENET_GAUR_GADDR1 (0U) /!< Bit position for ENET_GAUR_GADDR1. /
Kojto	90:cb3d968589d8	2869	#define BM_ENET_GAUR_GADDR1 (0xFFFFFFFFU) /!< Bit mask for ENET_GAUR_GADDR1. /
Kojto	90:cb3d968589d8	2870	#define BS_ENET_GAUR_GADDR1 (32U) /!< Bit field size in bits for ENET_GAUR_GADDR1. /
Kojto	90:cb3d968589d8	2871
Kojto	90:cb3d968589d8	2872	/! @brief Read current value of the ENET_GAUR_GADDR1 field. /
Kojto	90:cb3d968589d8	2873	#define BR_ENET_GAUR_GADDR1(x) (HW_ENET_GAUR(x).U)
Kojto	90:cb3d968589d8	2874
Kojto	90:cb3d968589d8	2875	/! @brief Format value for bitfield ENET_GAUR_GADDR1. /
Kojto	90:cb3d968589d8	2876	#define BF_ENET_GAUR_GADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_GAUR_GADDR1) & BM_ENET_GAUR_GADDR1)
Kojto	90:cb3d968589d8	2877
Kojto	90:cb3d968589d8	2878	/! @brief Set the GADDR1 field to a new value. /
Kojto	90:cb3d968589d8	2879	#define BW_ENET_GAUR_GADDR1(x, v) (HW_ENET_GAUR_WR(x, v))
Kojto	90:cb3d968589d8	2880	/@}/
Kojto	90:cb3d968589d8	2881
Kojto	90:cb3d968589d8	2882	/*******************************************************************************
Kojto	90:cb3d968589d8	2883	* HW_ENET_GALR - Descriptor Group Lower Address Register
Kojto	90:cb3d968589d8	2884	******************************************************************************/
Kojto	90:cb3d968589d8	2885
Kojto	90:cb3d968589d8	2886	/*!
Kojto	90:cb3d968589d8	2887	* @brief HW_ENET_GALR - Descriptor Group Lower Address Register (RW)
Kojto	90:cb3d968589d8	2888	*
Kojto	90:cb3d968589d8	2889	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2890	*
Kojto	90:cb3d968589d8	2891	* GALR contains the lower 32 bits of the 64-bit hash table used in the address
Kojto	90:cb3d968589d8	2892	* recognition process for receive frames with a multicast address. You must
Kojto	90:cb3d968589d8	2893	* initialize this register.
Kojto	90:cb3d968589d8	2894	*/
Kojto	90:cb3d968589d8	2895	typedef union _hw_enet_galr
Kojto	90:cb3d968589d8	2896	{
Kojto	90:cb3d968589d8	2897	uint32_t U;
Kojto	90:cb3d968589d8	2898	struct _hw_enet_galr_bitfields
Kojto	90:cb3d968589d8	2899	{
Kojto	90:cb3d968589d8	2900	uint32_t GADDR2 : 32; /!< [31:0] /
Kojto	90:cb3d968589d8	2901	} B;
Kojto	90:cb3d968589d8	2902	} hw_enet_galr_t;
Kojto	90:cb3d968589d8	2903
Kojto	90:cb3d968589d8	2904	/*!
Kojto	90:cb3d968589d8	2905	* @name Constants and macros for entire ENET_GALR register
Kojto	90:cb3d968589d8	2906	*/
Kojto	90:cb3d968589d8	2907	/@{/
Kojto	90:cb3d968589d8	2908	#define HW_ENET_GALR_ADDR(x) ((x) + 0x124U)
Kojto	90:cb3d968589d8	2909
Kojto	90:cb3d968589d8	2910	#define HW_ENET_GALR(x) ((__IO hw_enet_galr_t ) HW_ENET_GALR_ADDR(x))
Kojto	90:cb3d968589d8	2911	#define HW_ENET_GALR_RD(x) (HW_ENET_GALR(x).U)
Kojto	90:cb3d968589d8	2912	#define HW_ENET_GALR_WR(x, v) (HW_ENET_GALR(x).U = (v))
Kojto	90:cb3d968589d8	2913	#define HW_ENET_GALR_SET(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2914	#define HW_ENET_GALR_CLR(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2915	#define HW_ENET_GALR_TOG(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2916	/@}/
Kojto	90:cb3d968589d8	2917
Kojto	90:cb3d968589d8	2918	/*
Kojto	90:cb3d968589d8	2919	* Constants & macros for individual ENET_GALR bitfields
Kojto	90:cb3d968589d8	2920	*/
Kojto	90:cb3d968589d8	2921
Kojto	90:cb3d968589d8	2922	/*!
Kojto	90:cb3d968589d8	2923	* @name Register ENET_GALR, field GADDR2[31:0] (RW)
Kojto	90:cb3d968589d8	2924	*
Kojto	90:cb3d968589d8	2925	* Contains the lower 32 bits of the 64-bit hash table used in the address
Kojto	90:cb3d968589d8	2926	* recognition process for receive frames with a multicast address. Bit 31 of GADDR2
Kojto	90:cb3d968589d8	2927	* contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
Kojto	90:cb3d968589d8	2928	*/
Kojto	90:cb3d968589d8	2929	/@{/
Kojto	90:cb3d968589d8	2930	#define BP_ENET_GALR_GADDR2 (0U) /!< Bit position for ENET_GALR_GADDR2. /
Kojto	90:cb3d968589d8	2931	#define BM_ENET_GALR_GADDR2 (0xFFFFFFFFU) /!< Bit mask for ENET_GALR_GADDR2. /
Kojto	90:cb3d968589d8	2932	#define BS_ENET_GALR_GADDR2 (32U) /!< Bit field size in bits for ENET_GALR_GADDR2. /
Kojto	90:cb3d968589d8	2933
Kojto	90:cb3d968589d8	2934	/! @brief Read current value of the ENET_GALR_GADDR2 field. /
Kojto	90:cb3d968589d8	2935	#define BR_ENET_GALR_GADDR2(x) (HW_ENET_GALR(x).U)
Kojto	90:cb3d968589d8	2936
Kojto	90:cb3d968589d8	2937	/! @brief Format value for bitfield ENET_GALR_GADDR2. /
Kojto	90:cb3d968589d8	2938	#define BF_ENET_GALR_GADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_GALR_GADDR2) & BM_ENET_GALR_GADDR2)
Kojto	90:cb3d968589d8	2939
Kojto	90:cb3d968589d8	2940	/! @brief Set the GADDR2 field to a new value. /
Kojto	90:cb3d968589d8	2941	#define BW_ENET_GALR_GADDR2(x, v) (HW_ENET_GALR_WR(x, v))
Kojto	90:cb3d968589d8	2942	/@}/
Kojto	90:cb3d968589d8	2943
Kojto	90:cb3d968589d8	2944	/*******************************************************************************
Kojto	90:cb3d968589d8	2945	* HW_ENET_TFWR - Transmit FIFO Watermark Register
Kojto	90:cb3d968589d8	2946	******************************************************************************/
Kojto	90:cb3d968589d8	2947
Kojto	90:cb3d968589d8	2948	/*!
Kojto	90:cb3d968589d8	2949	* @brief HW_ENET_TFWR - Transmit FIFO Watermark Register (RW)
Kojto	90:cb3d968589d8	2950	*
Kojto	90:cb3d968589d8	2951	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2952	*
Kojto	90:cb3d968589d8	2953	* If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
Kojto	90:cb3d968589d8	2954	* in the transmit FIFO before transmission of a frame can begin. This allows you
Kojto	90:cb3d968589d8	2955	* to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
Kojto	90:cb3d968589d8	2956	* latency (TFWR = 11) due to contention for the system bus. Setting the
Kojto	90:cb3d968589d8	2957	* watermark to a high value minimizes the risk of transmit FIFO underrun due to
Kojto	90:cb3d968589d8	2958	* contention for the system bus. The byte counts associated with the TFWR field may need
Kojto	90:cb3d968589d8	2959	* to be modified to match a given system requirement. For example, worst case
Kojto	90:cb3d968589d8	2960	* bus access latency by the transmit data DMA channel. When the FIFO level
Kojto	90:cb3d968589d8	2961	* reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
Kojto	90:cb3d968589d8	2962	* transmit control logic starts frame transmission even before the end-of-frame is
Kojto	90:cb3d968589d8	2963	* available in the FIFO (cut-through operation). If a complete frame has a size
Kojto	90:cb3d968589d8	2964	* smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
Kojto	90:cb3d968589d8	2965	* to the line. To enable store and forward on the Transmit path, set STR_FWD to
Kojto	90:cb3d968589d8	2966	* '1'. In this case, the MAC starts to transmit data only when a complete frame
Kojto	90:cb3d968589d8	2967	* is stored in the Transmit FIFO.
Kojto	90:cb3d968589d8	2968	*/
Kojto	90:cb3d968589d8	2969	typedef union _hw_enet_tfwr
Kojto	90:cb3d968589d8	2970	{
Kojto	90:cb3d968589d8	2971	uint32_t U;
Kojto	90:cb3d968589d8	2972	struct _hw_enet_tfwr_bitfields
Kojto	90:cb3d968589d8	2973	{
Kojto	90:cb3d968589d8	2974	uint32_t TFWR : 6; /!< [5:0] Transmit FIFO Write /
Kojto	90:cb3d968589d8	2975	uint32_t RESERVED0 : 2; /!< [7:6] /
Kojto	90:cb3d968589d8	2976	uint32_t STRFWD : 1; /!< [8] Store And Forward Enable /
Kojto	90:cb3d968589d8	2977	uint32_t RESERVED1 : 23; /!< [31:9] /
Kojto	90:cb3d968589d8	2978	} B;
Kojto	90:cb3d968589d8	2979	} hw_enet_tfwr_t;
Kojto	90:cb3d968589d8	2980
Kojto	90:cb3d968589d8	2981	/*!
Kojto	90:cb3d968589d8	2982	* @name Constants and macros for entire ENET_TFWR register
Kojto	90:cb3d968589d8	2983	*/
Kojto	90:cb3d968589d8	2984	/@{/
Kojto	90:cb3d968589d8	2985	#define HW_ENET_TFWR_ADDR(x) ((x) + 0x144U)
Kojto	90:cb3d968589d8	2986
Kojto	90:cb3d968589d8	2987	#define HW_ENET_TFWR(x) ((__IO hw_enet_tfwr_t ) HW_ENET_TFWR_ADDR(x))
Kojto	90:cb3d968589d8	2988	#define HW_ENET_TFWR_RD(x) (HW_ENET_TFWR(x).U)
Kojto	90:cb3d968589d8	2989	#define HW_ENET_TFWR_WR(x, v) (HW_ENET_TFWR(x).U = (v))
Kojto	90:cb3d968589d8	2990	#define HW_ENET_TFWR_SET(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2991	#define HW_ENET_TFWR_CLR(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2992	#define HW_ENET_TFWR_TOG(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2993	/@}/
Kojto	90:cb3d968589d8	2994
Kojto	90:cb3d968589d8	2995	/*
Kojto	90:cb3d968589d8	2996	* Constants & macros for individual ENET_TFWR bitfields
Kojto	90:cb3d968589d8	2997	*/
Kojto	90:cb3d968589d8	2998
Kojto	90:cb3d968589d8	2999	/*!
Kojto	90:cb3d968589d8	3000	* @name Register ENET_TFWR, field TFWR[5:0] (RW)
Kojto	90:cb3d968589d8	3001	*
Kojto	90:cb3d968589d8	3002	* If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
Kojto	90:cb3d968589d8	3003	* steps of 64 bytes, written to the transmit FIFO before transmission of a frame
Kojto	90:cb3d968589d8	3004	* begins. If a frame with less than the threshold is written, it is still sent
Kojto	90:cb3d968589d8	3005	* independently of this threshold setting. The threshold is relevant only if the
Kojto	90:cb3d968589d8	3006	* frame is larger than the threshold given. This chip may not support the maximum
Kojto	90:cb3d968589d8	3007	* number of bytes written shown below. See the chip-specific information for the
Kojto	90:cb3d968589d8	3008	* ENET module for this value.
Kojto	90:cb3d968589d8	3009	*
Kojto	90:cb3d968589d8	3010	* Values:
Kojto	90:cb3d968589d8	3011	* - 000000 - 64 bytes written.
Kojto	90:cb3d968589d8	3012	* - 000001 - 64 bytes written.
Kojto	90:cb3d968589d8	3013	* - 000010 - 128 bytes written.
Kojto	90:cb3d968589d8	3014	* - 000011 - 192 bytes written.
Kojto	90:cb3d968589d8	3015	* - 111110 - 3968 bytes written.
Kojto	90:cb3d968589d8	3016	* - 111111 - 4032 bytes written.
Kojto	90:cb3d968589d8	3017	*/
Kojto	90:cb3d968589d8	3018	/@{/
Kojto	90:cb3d968589d8	3019	#define BP_ENET_TFWR_TFWR (0U) /!< Bit position for ENET_TFWR_TFWR. /
Kojto	90:cb3d968589d8	3020	#define BM_ENET_TFWR_TFWR (0x0000003FU) /!< Bit mask for ENET_TFWR_TFWR. /
Kojto	90:cb3d968589d8	3021	#define BS_ENET_TFWR_TFWR (6U) /!< Bit field size in bits for ENET_TFWR_TFWR. /
Kojto	90:cb3d968589d8	3022
Kojto	90:cb3d968589d8	3023	/! @brief Read current value of the ENET_TFWR_TFWR field. /
Kojto	90:cb3d968589d8	3024	#define BR_ENET_TFWR_TFWR(x) (HW_ENET_TFWR(x).B.TFWR)
Kojto	90:cb3d968589d8	3025
Kojto	90:cb3d968589d8	3026	/! @brief Format value for bitfield ENET_TFWR_TFWR. /
Kojto	90:cb3d968589d8	3027	#define BF_ENET_TFWR_TFWR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TFWR_TFWR) & BM_ENET_TFWR_TFWR)
Kojto	90:cb3d968589d8	3028
Kojto	90:cb3d968589d8	3029	/! @brief Set the TFWR field to a new value. /
Kojto	90:cb3d968589d8	3030	#define BW_ENET_TFWR_TFWR(x, v) (HW_ENET_TFWR_WR(x, (HW_ENET_TFWR_RD(x) & ~BM_ENET_TFWR_TFWR) \| BF_ENET_TFWR_TFWR(v)))
Kojto	90:cb3d968589d8	3031	/@}/
Kojto	90:cb3d968589d8	3032
Kojto	90:cb3d968589d8	3033	/*!
Kojto	90:cb3d968589d8	3034	* @name Register ENET_TFWR, field STRFWD[8] (RW)
Kojto	90:cb3d968589d8	3035	*
Kojto	90:cb3d968589d8	3036	* Values:
Kojto	90:cb3d968589d8	3037	* - 0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
Kojto	90:cb3d968589d8	3038	* - 1 - Enabled.
Kojto	90:cb3d968589d8	3039	*/
Kojto	90:cb3d968589d8	3040	/@{/
Kojto	90:cb3d968589d8	3041	#define BP_ENET_TFWR_STRFWD (8U) /!< Bit position for ENET_TFWR_STRFWD. /
Kojto	90:cb3d968589d8	3042	#define BM_ENET_TFWR_STRFWD (0x00000100U) /!< Bit mask for ENET_TFWR_STRFWD. /
Kojto	90:cb3d968589d8	3043	#define BS_ENET_TFWR_STRFWD (1U) /!< Bit field size in bits for ENET_TFWR_STRFWD. /
Kojto	90:cb3d968589d8	3044
Kojto	90:cb3d968589d8	3045	/! @brief Read current value of the ENET_TFWR_STRFWD field. /
Kojto	90:cb3d968589d8	3046	#define BR_ENET_TFWR_STRFWD(x) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD))
Kojto	90:cb3d968589d8	3047
Kojto	90:cb3d968589d8	3048	/! @brief Format value for bitfield ENET_TFWR_STRFWD. /
Kojto	90:cb3d968589d8	3049	#define BF_ENET_TFWR_STRFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TFWR_STRFWD) & BM_ENET_TFWR_STRFWD)
Kojto	90:cb3d968589d8	3050
Kojto	90:cb3d968589d8	3051	/! @brief Set the STRFWD field to a new value. /
Kojto	90:cb3d968589d8	3052	#define BW_ENET_TFWR_STRFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD) = (v))
Kojto	90:cb3d968589d8	3053	/@}/
Kojto	90:cb3d968589d8	3054
Kojto	90:cb3d968589d8	3055	/*******************************************************************************
Kojto	90:cb3d968589d8	3056	* HW_ENET_RDSR - Receive Descriptor Ring Start Register
Kojto	90:cb3d968589d8	3057	******************************************************************************/
Kojto	90:cb3d968589d8	3058
Kojto	90:cb3d968589d8	3059	/*!
Kojto	90:cb3d968589d8	3060	* @brief HW_ENET_RDSR - Receive Descriptor Ring Start Register (RW)
Kojto	90:cb3d968589d8	3061	*
Kojto	90:cb3d968589d8	3062	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3063	*
Kojto	90:cb3d968589d8	3064	* RDSR points to the beginning of the circular receive buffer descriptor queue
Kojto	90:cb3d968589d8	3065	* in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
Kojto	90:cb3d968589d8	3066	* zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
Kojto	90:cb3d968589d8	3067	* by 16. This register must be initialized prior to operation
Kojto	90:cb3d968589d8	3068	*/
Kojto	90:cb3d968589d8	3069	typedef union _hw_enet_rdsr
Kojto	90:cb3d968589d8	3070	{
Kojto	90:cb3d968589d8	3071	uint32_t U;
Kojto	90:cb3d968589d8	3072	struct _hw_enet_rdsr_bitfields
Kojto	90:cb3d968589d8	3073	{
Kojto	90:cb3d968589d8	3074	uint32_t RESERVED0 : 3; /!< [2:0] /
Kojto	90:cb3d968589d8	3075	uint32_t R_DES_START : 29; /!< [31:3] /
Kojto	90:cb3d968589d8	3076	} B;
Kojto	90:cb3d968589d8	3077	} hw_enet_rdsr_t;
Kojto	90:cb3d968589d8	3078
Kojto	90:cb3d968589d8	3079	/*!
Kojto	90:cb3d968589d8	3080	* @name Constants and macros for entire ENET_RDSR register
Kojto	90:cb3d968589d8	3081	*/
Kojto	90:cb3d968589d8	3082	/@{/
Kojto	90:cb3d968589d8	3083	#define HW_ENET_RDSR_ADDR(x) ((x) + 0x180U)
Kojto	90:cb3d968589d8	3084
Kojto	90:cb3d968589d8	3085	#define HW_ENET_RDSR(x) ((__IO hw_enet_rdsr_t ) HW_ENET_RDSR_ADDR(x))
Kojto	90:cb3d968589d8	3086	#define HW_ENET_RDSR_RD(x) (HW_ENET_RDSR(x).U)
Kojto	90:cb3d968589d8	3087	#define HW_ENET_RDSR_WR(x, v) (HW_ENET_RDSR(x).U = (v))
Kojto	90:cb3d968589d8	3088	#define HW_ENET_RDSR_SET(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3089	#define HW_ENET_RDSR_CLR(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3090	#define HW_ENET_RDSR_TOG(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3091	/@}/
Kojto	90:cb3d968589d8	3092
Kojto	90:cb3d968589d8	3093	/*
Kojto	90:cb3d968589d8	3094	* Constants & macros for individual ENET_RDSR bitfields
Kojto	90:cb3d968589d8	3095	*/
Kojto	90:cb3d968589d8	3096
Kojto	90:cb3d968589d8	3097	/*!
Kojto	90:cb3d968589d8	3098	* @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
Kojto	90:cb3d968589d8	3099	*
Kojto	90:cb3d968589d8	3100	* Pointer to the beginning of the receive buffer descriptor queue.
Kojto	90:cb3d968589d8	3101	*/
Kojto	90:cb3d968589d8	3102	/@{/
Kojto	90:cb3d968589d8	3103	#define BP_ENET_RDSR_R_DES_START (3U) /!< Bit position for ENET_RDSR_R_DES_START. /
Kojto	90:cb3d968589d8	3104	#define BM_ENET_RDSR_R_DES_START (0xFFFFFFF8U) /!< Bit mask for ENET_RDSR_R_DES_START. /
Kojto	90:cb3d968589d8	3105	#define BS_ENET_RDSR_R_DES_START (29U) /!< Bit field size in bits for ENET_RDSR_R_DES_START. /
Kojto	90:cb3d968589d8	3106
Kojto	90:cb3d968589d8	3107	/! @brief Read current value of the ENET_RDSR_R_DES_START field. /
Kojto	90:cb3d968589d8	3108	#define BR_ENET_RDSR_R_DES_START(x) (HW_ENET_RDSR(x).B.R_DES_START)
Kojto	90:cb3d968589d8	3109
Kojto	90:cb3d968589d8	3110	/! @brief Format value for bitfield ENET_RDSR_R_DES_START. /
Kojto	90:cb3d968589d8	3111	#define BF_ENET_RDSR_R_DES_START(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RDSR_R_DES_START) & BM_ENET_RDSR_R_DES_START)
Kojto	90:cb3d968589d8	3112
Kojto	90:cb3d968589d8	3113	/! @brief Set the R_DES_START field to a new value. /
Kojto	90:cb3d968589d8	3114	#define BW_ENET_RDSR_R_DES_START(x, v) (HW_ENET_RDSR_WR(x, (HW_ENET_RDSR_RD(x) & ~BM_ENET_RDSR_R_DES_START) \| BF_ENET_RDSR_R_DES_START(v)))
Kojto	90:cb3d968589d8	3115	/@}/
Kojto	90:cb3d968589d8	3116
Kojto	90:cb3d968589d8	3117	/*******************************************************************************
Kojto	90:cb3d968589d8	3118	* HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
Kojto	90:cb3d968589d8	3119	******************************************************************************/
Kojto	90:cb3d968589d8	3120
Kojto	90:cb3d968589d8	3121	/*!
Kojto	90:cb3d968589d8	3122	* @brief HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
Kojto	90:cb3d968589d8	3123	*
Kojto	90:cb3d968589d8	3124	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3125	*
Kojto	90:cb3d968589d8	3126	* TDSR provides a pointer to the beginning of the circular transmit buffer
Kojto	90:cb3d968589d8	3127	* descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
Kojto	90:cb3d968589d8	3128	* must be zero); however, it is recommended to be 128-bit aligned, that is,
Kojto	90:cb3d968589d8	3129	* evenly divisible by 16. This register must be initialized prior to operation.
Kojto	90:cb3d968589d8	3130	*/
Kojto	90:cb3d968589d8	3131	typedef union _hw_enet_tdsr
Kojto	90:cb3d968589d8	3132	{
Kojto	90:cb3d968589d8	3133	uint32_t U;
Kojto	90:cb3d968589d8	3134	struct _hw_enet_tdsr_bitfields
Kojto	90:cb3d968589d8	3135	{
Kojto	90:cb3d968589d8	3136	uint32_t RESERVED0 : 3; /!< [2:0] /
Kojto	90:cb3d968589d8	3137	uint32_t X_DES_START : 29; /!< [31:3] /
Kojto	90:cb3d968589d8	3138	} B;
Kojto	90:cb3d968589d8	3139	} hw_enet_tdsr_t;
Kojto	90:cb3d968589d8	3140
Kojto	90:cb3d968589d8	3141	/*!
Kojto	90:cb3d968589d8	3142	* @name Constants and macros for entire ENET_TDSR register
Kojto	90:cb3d968589d8	3143	*/
Kojto	90:cb3d968589d8	3144	/@{/
Kojto	90:cb3d968589d8	3145	#define HW_ENET_TDSR_ADDR(x) ((x) + 0x184U)
Kojto	90:cb3d968589d8	3146
Kojto	90:cb3d968589d8	3147	#define HW_ENET_TDSR(x) ((__IO hw_enet_tdsr_t ) HW_ENET_TDSR_ADDR(x))
Kojto	90:cb3d968589d8	3148	#define HW_ENET_TDSR_RD(x) (HW_ENET_TDSR(x).U)
Kojto	90:cb3d968589d8	3149	#define HW_ENET_TDSR_WR(x, v) (HW_ENET_TDSR(x).U = (v))
Kojto	90:cb3d968589d8	3150	#define HW_ENET_TDSR_SET(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3151	#define HW_ENET_TDSR_CLR(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3152	#define HW_ENET_TDSR_TOG(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3153	/@}/
Kojto	90:cb3d968589d8	3154
Kojto	90:cb3d968589d8	3155	/*
Kojto	90:cb3d968589d8	3156	* Constants & macros for individual ENET_TDSR bitfields
Kojto	90:cb3d968589d8	3157	*/
Kojto	90:cb3d968589d8	3158
Kojto	90:cb3d968589d8	3159	/*!
Kojto	90:cb3d968589d8	3160	* @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
Kojto	90:cb3d968589d8	3161	*
Kojto	90:cb3d968589d8	3162	* Pointer to the beginning of the transmit buffer descriptor queue.
Kojto	90:cb3d968589d8	3163	*/
Kojto	90:cb3d968589d8	3164	/@{/
Kojto	90:cb3d968589d8	3165	#define BP_ENET_TDSR_X_DES_START (3U) /!< Bit position for ENET_TDSR_X_DES_START. /
Kojto	90:cb3d968589d8	3166	#define BM_ENET_TDSR_X_DES_START (0xFFFFFFF8U) /!< Bit mask for ENET_TDSR_X_DES_START. /
Kojto	90:cb3d968589d8	3167	#define BS_ENET_TDSR_X_DES_START (29U) /!< Bit field size in bits for ENET_TDSR_X_DES_START. /
Kojto	90:cb3d968589d8	3168
Kojto	90:cb3d968589d8	3169	/! @brief Read current value of the ENET_TDSR_X_DES_START field. /
Kojto	90:cb3d968589d8	3170	#define BR_ENET_TDSR_X_DES_START(x) (HW_ENET_TDSR(x).B.X_DES_START)
Kojto	90:cb3d968589d8	3171
Kojto	90:cb3d968589d8	3172	/! @brief Format value for bitfield ENET_TDSR_X_DES_START. /
Kojto	90:cb3d968589d8	3173	#define BF_ENET_TDSR_X_DES_START(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TDSR_X_DES_START) & BM_ENET_TDSR_X_DES_START)
Kojto	90:cb3d968589d8	3174
Kojto	90:cb3d968589d8	3175	/! @brief Set the X_DES_START field to a new value. /
Kojto	90:cb3d968589d8	3176	#define BW_ENET_TDSR_X_DES_START(x, v) (HW_ENET_TDSR_WR(x, (HW_ENET_TDSR_RD(x) & ~BM_ENET_TDSR_X_DES_START) \| BF_ENET_TDSR_X_DES_START(v)))
Kojto	90:cb3d968589d8	3177	/@}/
Kojto	90:cb3d968589d8	3178
Kojto	90:cb3d968589d8	3179	/*******************************************************************************
Kojto	90:cb3d968589d8	3180	* HW_ENET_MRBR - Maximum Receive Buffer Size Register
Kojto	90:cb3d968589d8	3181	******************************************************************************/
Kojto	90:cb3d968589d8	3182
Kojto	90:cb3d968589d8	3183	/*!
Kojto	90:cb3d968589d8	3184	* @brief HW_ENET_MRBR - Maximum Receive Buffer Size Register (RW)
Kojto	90:cb3d968589d8	3185	*
Kojto	90:cb3d968589d8	3186	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3187	*
Kojto	90:cb3d968589d8	3188	* The MRBR is a user-programmable register that dictates the maximum size of
Kojto	90:cb3d968589d8	3189	* all receive buffers. This value should take into consideration that the receive
Kojto	90:cb3d968589d8	3190	* CRC is always written into the last receive buffer. To allow one maximum size
Kojto	90:cb3d968589d8	3191	* frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
Kojto	90:cb3d968589d8	3192	* the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
Kojto	90:cb3d968589d8	3193	* set to zero by the device. To minimize bus usage (descriptor fetches), set
Kojto	90:cb3d968589d8	3194	* MRBR greater than or equal to 256 bytes. This register must be initialized
Kojto	90:cb3d968589d8	3195	* before operation.
Kojto	90:cb3d968589d8	3196	*/
Kojto	90:cb3d968589d8	3197	typedef union _hw_enet_mrbr
Kojto	90:cb3d968589d8	3198	{
Kojto	90:cb3d968589d8	3199	uint32_t U;
Kojto	90:cb3d968589d8	3200	struct _hw_enet_mrbr_bitfields
Kojto	90:cb3d968589d8	3201	{
Kojto	90:cb3d968589d8	3202	uint32_t RESERVED0 : 4; /!< [3:0] /
Kojto	90:cb3d968589d8	3203	uint32_t R_BUF_SIZE : 10; /!< [13:4] /
Kojto	90:cb3d968589d8	3204	uint32_t RESERVED1 : 18; /!< [31:14] /
Kojto	90:cb3d968589d8	3205	} B;
Kojto	90:cb3d968589d8	3206	} hw_enet_mrbr_t;
Kojto	90:cb3d968589d8	3207
Kojto	90:cb3d968589d8	3208	/*!
Kojto	90:cb3d968589d8	3209	* @name Constants and macros for entire ENET_MRBR register
Kojto	90:cb3d968589d8	3210	*/
Kojto	90:cb3d968589d8	3211	/@{/
Kojto	90:cb3d968589d8	3212	#define HW_ENET_MRBR_ADDR(x) ((x) + 0x188U)
Kojto	90:cb3d968589d8	3213
Kojto	90:cb3d968589d8	3214	#define HW_ENET_MRBR(x) ((__IO hw_enet_mrbr_t ) HW_ENET_MRBR_ADDR(x))
Kojto	90:cb3d968589d8	3215	#define HW_ENET_MRBR_RD(x) (HW_ENET_MRBR(x).U)
Kojto	90:cb3d968589d8	3216	#define HW_ENET_MRBR_WR(x, v) (HW_ENET_MRBR(x).U = (v))
Kojto	90:cb3d968589d8	3217	#define HW_ENET_MRBR_SET(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3218	#define HW_ENET_MRBR_CLR(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3219	#define HW_ENET_MRBR_TOG(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3220	/@}/
Kojto	90:cb3d968589d8	3221
Kojto	90:cb3d968589d8	3222	/*
Kojto	90:cb3d968589d8	3223	* Constants & macros for individual ENET_MRBR bitfields
Kojto	90:cb3d968589d8	3224	*/
Kojto	90:cb3d968589d8	3225
Kojto	90:cb3d968589d8	3226	/*!
Kojto	90:cb3d968589d8	3227	* @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
Kojto	90:cb3d968589d8	3228	*
Kojto	90:cb3d968589d8	3229	* Receive buffer size in bytes.
Kojto	90:cb3d968589d8	3230	*/
Kojto	90:cb3d968589d8	3231	/@{/
Kojto	90:cb3d968589d8	3232	#define BP_ENET_MRBR_R_BUF_SIZE (4U) /!< Bit position for ENET_MRBR_R_BUF_SIZE. /
Kojto	90:cb3d968589d8	3233	#define BM_ENET_MRBR_R_BUF_SIZE (0x00003FF0U) /!< Bit mask for ENET_MRBR_R_BUF_SIZE. /
Kojto	90:cb3d968589d8	3234	#define BS_ENET_MRBR_R_BUF_SIZE (10U) /!< Bit field size in bits for ENET_MRBR_R_BUF_SIZE. /
Kojto	90:cb3d968589d8	3235
Kojto	90:cb3d968589d8	3236	/! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field. /
Kojto	90:cb3d968589d8	3237	#define BR_ENET_MRBR_R_BUF_SIZE(x) (HW_ENET_MRBR(x).B.R_BUF_SIZE)
Kojto	90:cb3d968589d8	3238
Kojto	90:cb3d968589d8	3239	/! @brief Format value for bitfield ENET_MRBR_R_BUF_SIZE. /
Kojto	90:cb3d968589d8	3240	#define BF_ENET_MRBR_R_BUF_SIZE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MRBR_R_BUF_SIZE) & BM_ENET_MRBR_R_BUF_SIZE)
Kojto	90:cb3d968589d8	3241
Kojto	90:cb3d968589d8	3242	/! @brief Set the R_BUF_SIZE field to a new value. /
Kojto	90:cb3d968589d8	3243	#define BW_ENET_MRBR_R_BUF_SIZE(x, v) (HW_ENET_MRBR_WR(x, (HW_ENET_MRBR_RD(x) & ~BM_ENET_MRBR_R_BUF_SIZE) \| BF_ENET_MRBR_R_BUF_SIZE(v)))
Kojto	90:cb3d968589d8	3244	/@}/
Kojto	90:cb3d968589d8	3245
Kojto	90:cb3d968589d8	3246	/*******************************************************************************
Kojto	90:cb3d968589d8	3247	* HW_ENET_RSFL - Receive FIFO Section Full Threshold
Kojto	90:cb3d968589d8	3248	******************************************************************************/
Kojto	90:cb3d968589d8	3249
Kojto	90:cb3d968589d8	3250	/*!
Kojto	90:cb3d968589d8	3251	* @brief HW_ENET_RSFL - Receive FIFO Section Full Threshold (RW)
Kojto	90:cb3d968589d8	3252	*
Kojto	90:cb3d968589d8	3253	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3254	*/
Kojto	90:cb3d968589d8	3255	typedef union _hw_enet_rsfl
Kojto	90:cb3d968589d8	3256	{
Kojto	90:cb3d968589d8	3257	uint32_t U;
Kojto	90:cb3d968589d8	3258	struct _hw_enet_rsfl_bitfields
Kojto	90:cb3d968589d8	3259	{
Kojto	90:cb3d968589d8	3260	uint32_t RX_SECTION_FULL : 8; /*!< [7:0] Value Of Receive FIFO
Kojto	90:cb3d968589d8	3261	* Section Full Threshold */
Kojto	90:cb3d968589d8	3262	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	3263	} B;
Kojto	90:cb3d968589d8	3264	} hw_enet_rsfl_t;
Kojto	90:cb3d968589d8	3265
Kojto	90:cb3d968589d8	3266	/*!
Kojto	90:cb3d968589d8	3267	* @name Constants and macros for entire ENET_RSFL register
Kojto	90:cb3d968589d8	3268	*/
Kojto	90:cb3d968589d8	3269	/@{/
Kojto	90:cb3d968589d8	3270	#define HW_ENET_RSFL_ADDR(x) ((x) + 0x190U)
Kojto	90:cb3d968589d8	3271
Kojto	90:cb3d968589d8	3272	#define HW_ENET_RSFL(x) ((__IO hw_enet_rsfl_t ) HW_ENET_RSFL_ADDR(x))
Kojto	90:cb3d968589d8	3273	#define HW_ENET_RSFL_RD(x) (HW_ENET_RSFL(x).U)
Kojto	90:cb3d968589d8	3274	#define HW_ENET_RSFL_WR(x, v) (HW_ENET_RSFL(x).U = (v))
Kojto	90:cb3d968589d8	3275	#define HW_ENET_RSFL_SET(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3276	#define HW_ENET_RSFL_CLR(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3277	#define HW_ENET_RSFL_TOG(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3278	/@}/
Kojto	90:cb3d968589d8	3279
Kojto	90:cb3d968589d8	3280	/*
Kojto	90:cb3d968589d8	3281	* Constants & macros for individual ENET_RSFL bitfields
Kojto	90:cb3d968589d8	3282	*/
Kojto	90:cb3d968589d8	3283
Kojto	90:cb3d968589d8	3284	/*!
Kojto	90:cb3d968589d8	3285	* @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
Kojto	90:cb3d968589d8	3286	*
Kojto	90:cb3d968589d8	3287	* Value, in 64-bit words, of the receive FIFO section full threshold. Clear
Kojto	90:cb3d968589d8	3288	* this field to enable store and forward on the RX FIFO. When programming a value
Kojto	90:cb3d968589d8	3289	* greater than 0 (cut-through operation), it must be greater than
Kojto	90:cb3d968589d8	3290	* RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
Kojto	90:cb3d968589d8	3291	* in the Receive FIFO (cut-through operation).
Kojto	90:cb3d968589d8	3292	*/
Kojto	90:cb3d968589d8	3293	/@{/
Kojto	90:cb3d968589d8	3294	#define BP_ENET_RSFL_RX_SECTION_FULL (0U) /!< Bit position for ENET_RSFL_RX_SECTION_FULL. /
Kojto	90:cb3d968589d8	3295	#define BM_ENET_RSFL_RX_SECTION_FULL (0x000000FFU) /!< Bit mask for ENET_RSFL_RX_SECTION_FULL. /
Kojto	90:cb3d968589d8	3296	#define BS_ENET_RSFL_RX_SECTION_FULL (8U) /!< Bit field size in bits for ENET_RSFL_RX_SECTION_FULL. /
Kojto	90:cb3d968589d8	3297
Kojto	90:cb3d968589d8	3298	/! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field. /
Kojto	90:cb3d968589d8	3299	#define BR_ENET_RSFL_RX_SECTION_FULL(x) (HW_ENET_RSFL(x).B.RX_SECTION_FULL)
Kojto	90:cb3d968589d8	3300
Kojto	90:cb3d968589d8	3301	/! @brief Format value for bitfield ENET_RSFL_RX_SECTION_FULL. /
Kojto	90:cb3d968589d8	3302	#define BF_ENET_RSFL_RX_SECTION_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSFL_RX_SECTION_FULL) & BM_ENET_RSFL_RX_SECTION_FULL)
Kojto	90:cb3d968589d8	3303
Kojto	90:cb3d968589d8	3304	/! @brief Set the RX_SECTION_FULL field to a new value. /
Kojto	90:cb3d968589d8	3305	#define BW_ENET_RSFL_RX_SECTION_FULL(x, v) (HW_ENET_RSFL_WR(x, (HW_ENET_RSFL_RD(x) & ~BM_ENET_RSFL_RX_SECTION_FULL) \| BF_ENET_RSFL_RX_SECTION_FULL(v)))
Kojto	90:cb3d968589d8	3306	/@}/
Kojto	90:cb3d968589d8	3307
Kojto	90:cb3d968589d8	3308	/*******************************************************************************
Kojto	90:cb3d968589d8	3309	* HW_ENET_RSEM - Receive FIFO Section Empty Threshold
Kojto	90:cb3d968589d8	3310	******************************************************************************/
Kojto	90:cb3d968589d8	3311
Kojto	90:cb3d968589d8	3312	/*!
Kojto	90:cb3d968589d8	3313	* @brief HW_ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
Kojto	90:cb3d968589d8	3314	*
Kojto	90:cb3d968589d8	3315	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3316	*/
Kojto	90:cb3d968589d8	3317	typedef union _hw_enet_rsem
Kojto	90:cb3d968589d8	3318	{
Kojto	90:cb3d968589d8	3319	uint32_t U;
Kojto	90:cb3d968589d8	3320	struct _hw_enet_rsem_bitfields
Kojto	90:cb3d968589d8	3321	{
Kojto	90:cb3d968589d8	3322	uint32_t RX_SECTION_EMPTY : 8; /*!< [7:0] Value Of The Receive FIFO
Kojto	90:cb3d968589d8	3323	* Section Empty Threshold */
Kojto	90:cb3d968589d8	3324	uint32_t RESERVED0 : 8; /!< [15:8] /
Kojto	90:cb3d968589d8	3325	uint32_t STAT_SECTION_EMPTY : 5; /*!< [20:16] RX Status FIFO Section
Kojto	90:cb3d968589d8	3326	* Empty Threshold */
Kojto	90:cb3d968589d8	3327	uint32_t RESERVED1 : 11; /!< [31:21] /
Kojto	90:cb3d968589d8	3328	} B;
Kojto	90:cb3d968589d8	3329	} hw_enet_rsem_t;
Kojto	90:cb3d968589d8	3330
Kojto	90:cb3d968589d8	3331	/*!
Kojto	90:cb3d968589d8	3332	* @name Constants and macros for entire ENET_RSEM register
Kojto	90:cb3d968589d8	3333	*/
Kojto	90:cb3d968589d8	3334	/@{/
Kojto	90:cb3d968589d8	3335	#define HW_ENET_RSEM_ADDR(x) ((x) + 0x194U)
Kojto	90:cb3d968589d8	3336
Kojto	90:cb3d968589d8	3337	#define HW_ENET_RSEM(x) ((__IO hw_enet_rsem_t ) HW_ENET_RSEM_ADDR(x))
Kojto	90:cb3d968589d8	3338	#define HW_ENET_RSEM_RD(x) (HW_ENET_RSEM(x).U)
Kojto	90:cb3d968589d8	3339	#define HW_ENET_RSEM_WR(x, v) (HW_ENET_RSEM(x).U = (v))
Kojto	90:cb3d968589d8	3340	#define HW_ENET_RSEM_SET(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3341	#define HW_ENET_RSEM_CLR(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3342	#define HW_ENET_RSEM_TOG(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3343	/@}/
Kojto	90:cb3d968589d8	3344
Kojto	90:cb3d968589d8	3345	/*
Kojto	90:cb3d968589d8	3346	* Constants & macros for individual ENET_RSEM bitfields
Kojto	90:cb3d968589d8	3347	*/
Kojto	90:cb3d968589d8	3348
Kojto	90:cb3d968589d8	3349	/*!
Kojto	90:cb3d968589d8	3350	* @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
Kojto	90:cb3d968589d8	3351	*
Kojto	90:cb3d968589d8	3352	* Value, in 64-bit words, of the receive FIFO section empty threshold. When the
Kojto	90:cb3d968589d8	3353	* FIFO has reached this level, a pause frame will be issued. A value of 0
Kojto	90:cb3d968589d8	3354	* disables automatic pause frame generation. When the FIFO level goes below the value
Kojto	90:cb3d968589d8	3355	* programmed in this field, an XON pause frame is issued to indicate the FIFO
Kojto	90:cb3d968589d8	3356	* congestion is cleared to the remote Ethernet client. The section-empty
Kojto	90:cb3d968589d8	3357	* threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
Kojto	90:cb3d968589d8	3358	*/
Kojto	90:cb3d968589d8	3359	/@{/
Kojto	90:cb3d968589d8	3360	#define BP_ENET_RSEM_RX_SECTION_EMPTY (0U) /!< Bit position for ENET_RSEM_RX_SECTION_EMPTY. /
Kojto	90:cb3d968589d8	3361	#define BM_ENET_RSEM_RX_SECTION_EMPTY (0x000000FFU) /!< Bit mask for ENET_RSEM_RX_SECTION_EMPTY. /
Kojto	90:cb3d968589d8	3362	#define BS_ENET_RSEM_RX_SECTION_EMPTY (8U) /!< Bit field size in bits for ENET_RSEM_RX_SECTION_EMPTY. /
Kojto	90:cb3d968589d8	3363
Kojto	90:cb3d968589d8	3364	/! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field. /
Kojto	90:cb3d968589d8	3365	#define BR_ENET_RSEM_RX_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.RX_SECTION_EMPTY)
Kojto	90:cb3d968589d8	3366
Kojto	90:cb3d968589d8	3367	/! @brief Format value for bitfield ENET_RSEM_RX_SECTION_EMPTY. /
Kojto	90:cb3d968589d8	3368	#define BF_ENET_RSEM_RX_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSEM_RX_SECTION_EMPTY) & BM_ENET_RSEM_RX_SECTION_EMPTY)
Kojto	90:cb3d968589d8	3369
Kojto	90:cb3d968589d8	3370	/! @brief Set the RX_SECTION_EMPTY field to a new value. /
Kojto	90:cb3d968589d8	3371	#define BW_ENET_RSEM_RX_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_RX_SECTION_EMPTY) \| BF_ENET_RSEM_RX_SECTION_EMPTY(v)))
Kojto	90:cb3d968589d8	3372	/@}/
Kojto	90:cb3d968589d8	3373
Kojto	90:cb3d968589d8	3374	/*!
Kojto	90:cb3d968589d8	3375	* @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
Kojto	90:cb3d968589d8	3376	*
Kojto	90:cb3d968589d8	3377	* Defines number of frames in the receive FIFO, independent of its size, that
Kojto	90:cb3d968589d8	3378	* can be accepted. If the limit is reached, reception will continue normally,
Kojto	90:cb3d968589d8	3379	* however a pause frame will be triggered to indicate a possible congestion to the
Kojto	90:cb3d968589d8	3380	* remote device to avoid FIFO overflow. A value of 0 disables automatic pause
Kojto	90:cb3d968589d8	3381	* frame generation
Kojto	90:cb3d968589d8	3382	*/
Kojto	90:cb3d968589d8	3383	/@{/
Kojto	90:cb3d968589d8	3384	#define BP_ENET_RSEM_STAT_SECTION_EMPTY (16U) /!< Bit position for ENET_RSEM_STAT_SECTION_EMPTY. /
Kojto	90:cb3d968589d8	3385	#define BM_ENET_RSEM_STAT_SECTION_EMPTY (0x001F0000U) /!< Bit mask for ENET_RSEM_STAT_SECTION_EMPTY. /
Kojto	90:cb3d968589d8	3386	#define BS_ENET_RSEM_STAT_SECTION_EMPTY (5U) /!< Bit field size in bits for ENET_RSEM_STAT_SECTION_EMPTY. /
Kojto	90:cb3d968589d8	3387
Kojto	90:cb3d968589d8	3388	/! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field. /
Kojto	90:cb3d968589d8	3389	#define BR_ENET_RSEM_STAT_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.STAT_SECTION_EMPTY)
Kojto	90:cb3d968589d8	3390
Kojto	90:cb3d968589d8	3391	/! @brief Format value for bitfield ENET_RSEM_STAT_SECTION_EMPTY. /
Kojto	90:cb3d968589d8	3392	#define BF_ENET_RSEM_STAT_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSEM_STAT_SECTION_EMPTY) & BM_ENET_RSEM_STAT_SECTION_EMPTY)
Kojto	90:cb3d968589d8	3393
Kojto	90:cb3d968589d8	3394	/! @brief Set the STAT_SECTION_EMPTY field to a new value. /
Kojto	90:cb3d968589d8	3395	#define BW_ENET_RSEM_STAT_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_STAT_SECTION_EMPTY) \| BF_ENET_RSEM_STAT_SECTION_EMPTY(v)))
Kojto	90:cb3d968589d8	3396	/@}/
Kojto	90:cb3d968589d8	3397
Kojto	90:cb3d968589d8	3398	/*******************************************************************************
Kojto	90:cb3d968589d8	3399	* HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
Kojto	90:cb3d968589d8	3400	******************************************************************************/
Kojto	90:cb3d968589d8	3401
Kojto	90:cb3d968589d8	3402	/*!
Kojto	90:cb3d968589d8	3403	* @brief HW_ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
Kojto	90:cb3d968589d8	3404	*
Kojto	90:cb3d968589d8	3405	* Reset value: 0x00000004U
Kojto	90:cb3d968589d8	3406	*/
Kojto	90:cb3d968589d8	3407	typedef union _hw_enet_raem
Kojto	90:cb3d968589d8	3408	{
Kojto	90:cb3d968589d8	3409	uint32_t U;
Kojto	90:cb3d968589d8	3410	struct _hw_enet_raem_bitfields
Kojto	90:cb3d968589d8	3411	{
Kojto	90:cb3d968589d8	3412	uint32_t RX_ALMOST_EMPTY : 8; /*!< [7:0] Value Of The Receive FIFO
Kojto	90:cb3d968589d8	3413	* Almost Empty Threshold */
Kojto	90:cb3d968589d8	3414	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	3415	} B;
Kojto	90:cb3d968589d8	3416	} hw_enet_raem_t;
Kojto	90:cb3d968589d8	3417
Kojto	90:cb3d968589d8	3418	/*!
Kojto	90:cb3d968589d8	3419	* @name Constants and macros for entire ENET_RAEM register
Kojto	90:cb3d968589d8	3420	*/
Kojto	90:cb3d968589d8	3421	/@{/
Kojto	90:cb3d968589d8	3422	#define HW_ENET_RAEM_ADDR(x) ((x) + 0x198U)
Kojto	90:cb3d968589d8	3423
Kojto	90:cb3d968589d8	3424	#define HW_ENET_RAEM(x) ((__IO hw_enet_raem_t ) HW_ENET_RAEM_ADDR(x))
Kojto	90:cb3d968589d8	3425	#define HW_ENET_RAEM_RD(x) (HW_ENET_RAEM(x).U)
Kojto	90:cb3d968589d8	3426	#define HW_ENET_RAEM_WR(x, v) (HW_ENET_RAEM(x).U = (v))
Kojto	90:cb3d968589d8	3427	#define HW_ENET_RAEM_SET(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3428	#define HW_ENET_RAEM_CLR(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3429	#define HW_ENET_RAEM_TOG(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3430	/@}/
Kojto	90:cb3d968589d8	3431
Kojto	90:cb3d968589d8	3432	/*
Kojto	90:cb3d968589d8	3433	* Constants & macros for individual ENET_RAEM bitfields
Kojto	90:cb3d968589d8	3434	*/
Kojto	90:cb3d968589d8	3435
Kojto	90:cb3d968589d8	3436	/*!
Kojto	90:cb3d968589d8	3437	* @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
Kojto	90:cb3d968589d8	3438	*
Kojto	90:cb3d968589d8	3439	* Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
Kojto	90:cb3d968589d8	3440	* FIFO level reaches the value programmed in this field and the end-of-frame has
Kojto	90:cb3d968589d8	3441	* not been received for the frame yet, the core receive read control stops FIFO
Kojto	90:cb3d968589d8	3442	* read (and subsequently stops transferring data to the MAC client
Kojto	90:cb3d968589d8	3443	* application). It continues to deliver the frame, if again more data than the threshold or
Kojto	90:cb3d968589d8	3444	* the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
Kojto	90:cb3d968589d8	3445	*/
Kojto	90:cb3d968589d8	3446	/@{/
Kojto	90:cb3d968589d8	3447	#define BP_ENET_RAEM_RX_ALMOST_EMPTY (0U) /!< Bit position for ENET_RAEM_RX_ALMOST_EMPTY. /
Kojto	90:cb3d968589d8	3448	#define BM_ENET_RAEM_RX_ALMOST_EMPTY (0x000000FFU) /!< Bit mask for ENET_RAEM_RX_ALMOST_EMPTY. /
Kojto	90:cb3d968589d8	3449	#define BS_ENET_RAEM_RX_ALMOST_EMPTY (8U) /!< Bit field size in bits for ENET_RAEM_RX_ALMOST_EMPTY. /
Kojto	90:cb3d968589d8	3450
Kojto	90:cb3d968589d8	3451	/! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field. /
Kojto	90:cb3d968589d8	3452	#define BR_ENET_RAEM_RX_ALMOST_EMPTY(x) (HW_ENET_RAEM(x).B.RX_ALMOST_EMPTY)
Kojto	90:cb3d968589d8	3453
Kojto	90:cb3d968589d8	3454	/! @brief Format value for bitfield ENET_RAEM_RX_ALMOST_EMPTY. /
Kojto	90:cb3d968589d8	3455	#define BF_ENET_RAEM_RX_ALMOST_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RAEM_RX_ALMOST_EMPTY) & BM_ENET_RAEM_RX_ALMOST_EMPTY)
Kojto	90:cb3d968589d8	3456
Kojto	90:cb3d968589d8	3457	/! @brief Set the RX_ALMOST_EMPTY field to a new value. /
Kojto	90:cb3d968589d8	3458	#define BW_ENET_RAEM_RX_ALMOST_EMPTY(x, v) (HW_ENET_RAEM_WR(x, (HW_ENET_RAEM_RD(x) & ~BM_ENET_RAEM_RX_ALMOST_EMPTY) \| BF_ENET_RAEM_RX_ALMOST_EMPTY(v)))
Kojto	90:cb3d968589d8	3459	/@}/
Kojto	90:cb3d968589d8	3460
Kojto	90:cb3d968589d8	3461	/*******************************************************************************
Kojto	90:cb3d968589d8	3462	* HW_ENET_RAFL - Receive FIFO Almost Full Threshold
Kojto	90:cb3d968589d8	3463	******************************************************************************/
Kojto	90:cb3d968589d8	3464
Kojto	90:cb3d968589d8	3465	/*!
Kojto	90:cb3d968589d8	3466	* @brief HW_ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
Kojto	90:cb3d968589d8	3467	*
Kojto	90:cb3d968589d8	3468	* Reset value: 0x00000004U
Kojto	90:cb3d968589d8	3469	*/
Kojto	90:cb3d968589d8	3470	typedef union _hw_enet_rafl
Kojto	90:cb3d968589d8	3471	{
Kojto	90:cb3d968589d8	3472	uint32_t U;
Kojto	90:cb3d968589d8	3473	struct _hw_enet_rafl_bitfields
Kojto	90:cb3d968589d8	3474	{
Kojto	90:cb3d968589d8	3475	uint32_t RX_ALMOST_FULL : 8; /*!< [7:0] Value Of The Receive FIFO
Kojto	90:cb3d968589d8	3476	* Almost Full Threshold */
Kojto	90:cb3d968589d8	3477	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	3478	} B;
Kojto	90:cb3d968589d8	3479	} hw_enet_rafl_t;
Kojto	90:cb3d968589d8	3480
Kojto	90:cb3d968589d8	3481	/*!
Kojto	90:cb3d968589d8	3482	* @name Constants and macros for entire ENET_RAFL register
Kojto	90:cb3d968589d8	3483	*/
Kojto	90:cb3d968589d8	3484	/@{/
Kojto	90:cb3d968589d8	3485	#define HW_ENET_RAFL_ADDR(x) ((x) + 0x19CU)
Kojto	90:cb3d968589d8	3486
Kojto	90:cb3d968589d8	3487	#define HW_ENET_RAFL(x) ((__IO hw_enet_rafl_t ) HW_ENET_RAFL_ADDR(x))
Kojto	90:cb3d968589d8	3488	#define HW_ENET_RAFL_RD(x) (HW_ENET_RAFL(x).U)
Kojto	90:cb3d968589d8	3489	#define HW_ENET_RAFL_WR(x, v) (HW_ENET_RAFL(x).U = (v))
Kojto	90:cb3d968589d8	3490	#define HW_ENET_RAFL_SET(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3491	#define HW_ENET_RAFL_CLR(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3492	#define HW_ENET_RAFL_TOG(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3493	/@}/
Kojto	90:cb3d968589d8	3494
Kojto	90:cb3d968589d8	3495	/*
Kojto	90:cb3d968589d8	3496	* Constants & macros for individual ENET_RAFL bitfields
Kojto	90:cb3d968589d8	3497	*/
Kojto	90:cb3d968589d8	3498
Kojto	90:cb3d968589d8	3499	/*!
Kojto	90:cb3d968589d8	3500	* @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
Kojto	90:cb3d968589d8	3501	*
Kojto	90:cb3d968589d8	3502	* Value, in 64-bit words, of the receive FIFO almost full threshold. When the
Kojto	90:cb3d968589d8	3503	* FIFO level comes close to the maximum, so that there is no more space for at
Kojto	90:cb3d968589d8	3504	* least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
Kojto	90:cb3d968589d8	3505	* truncates the received frame to avoid FIFO overflow. The corresponding error
Kojto	90:cb3d968589d8	3506	* status will be set when the frame is delivered to the application. A minimum
Kojto	90:cb3d968589d8	3507	* value of 4 should be set.
Kojto	90:cb3d968589d8	3508	*/
Kojto	90:cb3d968589d8	3509	/@{/
Kojto	90:cb3d968589d8	3510	#define BP_ENET_RAFL_RX_ALMOST_FULL (0U) /!< Bit position for ENET_RAFL_RX_ALMOST_FULL. /
Kojto	90:cb3d968589d8	3511	#define BM_ENET_RAFL_RX_ALMOST_FULL (0x000000FFU) /!< Bit mask for ENET_RAFL_RX_ALMOST_FULL. /
Kojto	90:cb3d968589d8	3512	#define BS_ENET_RAFL_RX_ALMOST_FULL (8U) /!< Bit field size in bits for ENET_RAFL_RX_ALMOST_FULL. /
Kojto	90:cb3d968589d8	3513
Kojto	90:cb3d968589d8	3514	/! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field. /
Kojto	90:cb3d968589d8	3515	#define BR_ENET_RAFL_RX_ALMOST_FULL(x) (HW_ENET_RAFL(x).B.RX_ALMOST_FULL)
Kojto	90:cb3d968589d8	3516
Kojto	90:cb3d968589d8	3517	/! @brief Format value for bitfield ENET_RAFL_RX_ALMOST_FULL. /
Kojto	90:cb3d968589d8	3518	#define BF_ENET_RAFL_RX_ALMOST_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RAFL_RX_ALMOST_FULL) & BM_ENET_RAFL_RX_ALMOST_FULL)
Kojto	90:cb3d968589d8	3519
Kojto	90:cb3d968589d8	3520	/! @brief Set the RX_ALMOST_FULL field to a new value. /
Kojto	90:cb3d968589d8	3521	#define BW_ENET_RAFL_RX_ALMOST_FULL(x, v) (HW_ENET_RAFL_WR(x, (HW_ENET_RAFL_RD(x) & ~BM_ENET_RAFL_RX_ALMOST_FULL) \| BF_ENET_RAFL_RX_ALMOST_FULL(v)))
Kojto	90:cb3d968589d8	3522	/@}/
Kojto	90:cb3d968589d8	3523
Kojto	90:cb3d968589d8	3524	/*******************************************************************************
Kojto	90:cb3d968589d8	3525	* HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
Kojto	90:cb3d968589d8	3526	******************************************************************************/
Kojto	90:cb3d968589d8	3527
Kojto	90:cb3d968589d8	3528	/*!
Kojto	90:cb3d968589d8	3529	* @brief HW_ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
Kojto	90:cb3d968589d8	3530	*
Kojto	90:cb3d968589d8	3531	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3532	*/
Kojto	90:cb3d968589d8	3533	typedef union _hw_enet_tsem
Kojto	90:cb3d968589d8	3534	{
Kojto	90:cb3d968589d8	3535	uint32_t U;
Kojto	90:cb3d968589d8	3536	struct _hw_enet_tsem_bitfields
Kojto	90:cb3d968589d8	3537	{
Kojto	90:cb3d968589d8	3538	uint32_t TX_SECTION_EMPTY : 8; /*!< [7:0] Value Of The Transmit FIFO
Kojto	90:cb3d968589d8	3539	* Section Empty Threshold */
Kojto	90:cb3d968589d8	3540	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	3541	} B;
Kojto	90:cb3d968589d8	3542	} hw_enet_tsem_t;
Kojto	90:cb3d968589d8	3543
Kojto	90:cb3d968589d8	3544	/*!
Kojto	90:cb3d968589d8	3545	* @name Constants and macros for entire ENET_TSEM register
Kojto	90:cb3d968589d8	3546	*/
Kojto	90:cb3d968589d8	3547	/@{/
Kojto	90:cb3d968589d8	3548	#define HW_ENET_TSEM_ADDR(x) ((x) + 0x1A0U)
Kojto	90:cb3d968589d8	3549
Kojto	90:cb3d968589d8	3550	#define HW_ENET_TSEM(x) ((__IO hw_enet_tsem_t ) HW_ENET_TSEM_ADDR(x))
Kojto	90:cb3d968589d8	3551	#define HW_ENET_TSEM_RD(x) (HW_ENET_TSEM(x).U)
Kojto	90:cb3d968589d8	3552	#define HW_ENET_TSEM_WR(x, v) (HW_ENET_TSEM(x).U = (v))
Kojto	90:cb3d968589d8	3553	#define HW_ENET_TSEM_SET(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3554	#define HW_ENET_TSEM_CLR(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3555	#define HW_ENET_TSEM_TOG(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3556	/@}/
Kojto	90:cb3d968589d8	3557
Kojto	90:cb3d968589d8	3558	/*
Kojto	90:cb3d968589d8	3559	* Constants & macros for individual ENET_TSEM bitfields
Kojto	90:cb3d968589d8	3560	*/
Kojto	90:cb3d968589d8	3561
Kojto	90:cb3d968589d8	3562	/*!
Kojto	90:cb3d968589d8	3563	* @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
Kojto	90:cb3d968589d8	3564	*
Kojto	90:cb3d968589d8	3565	* Value, in 64-bit words, of the transmit FIFO section empty threshold. See
Kojto	90:cb3d968589d8	3566	* Transmit FIFOFour programmable thresholds are available which control the core
Kojto	90:cb3d968589d8	3567	* operation. for more information.
Kojto	90:cb3d968589d8	3568	*/
Kojto	90:cb3d968589d8	3569	/@{/
Kojto	90:cb3d968589d8	3570	#define BP_ENET_TSEM_TX_SECTION_EMPTY (0U) /!< Bit position for ENET_TSEM_TX_SECTION_EMPTY. /
Kojto	90:cb3d968589d8	3571	#define BM_ENET_TSEM_TX_SECTION_EMPTY (0x000000FFU) /!< Bit mask for ENET_TSEM_TX_SECTION_EMPTY. /
Kojto	90:cb3d968589d8	3572	#define BS_ENET_TSEM_TX_SECTION_EMPTY (8U) /!< Bit field size in bits for ENET_TSEM_TX_SECTION_EMPTY. /
Kojto	90:cb3d968589d8	3573
Kojto	90:cb3d968589d8	3574	/! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field. /
Kojto	90:cb3d968589d8	3575	#define BR_ENET_TSEM_TX_SECTION_EMPTY(x) (HW_ENET_TSEM(x).B.TX_SECTION_EMPTY)
Kojto	90:cb3d968589d8	3576
Kojto	90:cb3d968589d8	3577	/! @brief Format value for bitfield ENET_TSEM_TX_SECTION_EMPTY. /
Kojto	90:cb3d968589d8	3578	#define BF_ENET_TSEM_TX_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TSEM_TX_SECTION_EMPTY) & BM_ENET_TSEM_TX_SECTION_EMPTY)
Kojto	90:cb3d968589d8	3579
Kojto	90:cb3d968589d8	3580	/! @brief Set the TX_SECTION_EMPTY field to a new value. /
Kojto	90:cb3d968589d8	3581	#define BW_ENET_TSEM_TX_SECTION_EMPTY(x, v) (HW_ENET_TSEM_WR(x, (HW_ENET_TSEM_RD(x) & ~BM_ENET_TSEM_TX_SECTION_EMPTY) \| BF_ENET_TSEM_TX_SECTION_EMPTY(v)))
Kojto	90:cb3d968589d8	3582	/@}/
Kojto	90:cb3d968589d8	3583
Kojto	90:cb3d968589d8	3584	/*******************************************************************************
Kojto	90:cb3d968589d8	3585	* HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
Kojto	90:cb3d968589d8	3586	******************************************************************************/
Kojto	90:cb3d968589d8	3587
Kojto	90:cb3d968589d8	3588	/*!
Kojto	90:cb3d968589d8	3589	* @brief HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
Kojto	90:cb3d968589d8	3590	*
Kojto	90:cb3d968589d8	3591	* Reset value: 0x00000004U
Kojto	90:cb3d968589d8	3592	*/
Kojto	90:cb3d968589d8	3593	typedef union _hw_enet_taem
Kojto	90:cb3d968589d8	3594	{
Kojto	90:cb3d968589d8	3595	uint32_t U;
Kojto	90:cb3d968589d8	3596	struct _hw_enet_taem_bitfields
Kojto	90:cb3d968589d8	3597	{
Kojto	90:cb3d968589d8	3598	uint32_t TX_ALMOST_EMPTY : 8; /*!< [7:0] Value of Transmit FIFO
Kojto	90:cb3d968589d8	3599	* Almost Empty Threshold */
Kojto	90:cb3d968589d8	3600	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	3601	} B;
Kojto	90:cb3d968589d8	3602	} hw_enet_taem_t;
Kojto	90:cb3d968589d8	3603
Kojto	90:cb3d968589d8	3604	/*!
Kojto	90:cb3d968589d8	3605	* @name Constants and macros for entire ENET_TAEM register
Kojto	90:cb3d968589d8	3606	*/
Kojto	90:cb3d968589d8	3607	/@{/
Kojto	90:cb3d968589d8	3608	#define HW_ENET_TAEM_ADDR(x) ((x) + 0x1A4U)
Kojto	90:cb3d968589d8	3609
Kojto	90:cb3d968589d8	3610	#define HW_ENET_TAEM(x) ((__IO hw_enet_taem_t ) HW_ENET_TAEM_ADDR(x))
Kojto	90:cb3d968589d8	3611	#define HW_ENET_TAEM_RD(x) (HW_ENET_TAEM(x).U)
Kojto	90:cb3d968589d8	3612	#define HW_ENET_TAEM_WR(x, v) (HW_ENET_TAEM(x).U = (v))
Kojto	90:cb3d968589d8	3613	#define HW_ENET_TAEM_SET(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3614	#define HW_ENET_TAEM_CLR(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3615	#define HW_ENET_TAEM_TOG(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3616	/@}/
Kojto	90:cb3d968589d8	3617
Kojto	90:cb3d968589d8	3618	/*
Kojto	90:cb3d968589d8	3619	* Constants & macros for individual ENET_TAEM bitfields
Kojto	90:cb3d968589d8	3620	*/
Kojto	90:cb3d968589d8	3621
Kojto	90:cb3d968589d8	3622	/*!
Kojto	90:cb3d968589d8	3623	* @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
Kojto	90:cb3d968589d8	3624	*
Kojto	90:cb3d968589d8	3625	* Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
Kojto	90:cb3d968589d8	3626	* FIFO level reaches the value programmed in this field, and no end-of-frame is
Kojto	90:cb3d968589d8	3627	* available for the frame, the MAC transmit logic, to avoid FIFO underflow,
Kojto	90:cb3d968589d8	3628	* stops reading the FIFO and transmits a frame with an MII error indication. See
Kojto	90:cb3d968589d8	3629	* Transmit FIFOFour programmable thresholds are available which control the core
Kojto	90:cb3d968589d8	3630	* operation. for more information. A minimum value of 4 should be set.
Kojto	90:cb3d968589d8	3631	*/
Kojto	90:cb3d968589d8	3632	/@{/
Kojto	90:cb3d968589d8	3633	#define BP_ENET_TAEM_TX_ALMOST_EMPTY (0U) /!< Bit position for ENET_TAEM_TX_ALMOST_EMPTY. /
Kojto	90:cb3d968589d8	3634	#define BM_ENET_TAEM_TX_ALMOST_EMPTY (0x000000FFU) /!< Bit mask for ENET_TAEM_TX_ALMOST_EMPTY. /
Kojto	90:cb3d968589d8	3635	#define BS_ENET_TAEM_TX_ALMOST_EMPTY (8U) /!< Bit field size in bits for ENET_TAEM_TX_ALMOST_EMPTY. /
Kojto	90:cb3d968589d8	3636
Kojto	90:cb3d968589d8	3637	/! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field. /
Kojto	90:cb3d968589d8	3638	#define BR_ENET_TAEM_TX_ALMOST_EMPTY(x) (HW_ENET_TAEM(x).B.TX_ALMOST_EMPTY)
Kojto	90:cb3d968589d8	3639
Kojto	90:cb3d968589d8	3640	/! @brief Format value for bitfield ENET_TAEM_TX_ALMOST_EMPTY. /
Kojto	90:cb3d968589d8	3641	#define BF_ENET_TAEM_TX_ALMOST_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TAEM_TX_ALMOST_EMPTY) & BM_ENET_TAEM_TX_ALMOST_EMPTY)
Kojto	90:cb3d968589d8	3642
Kojto	90:cb3d968589d8	3643	/! @brief Set the TX_ALMOST_EMPTY field to a new value. /
Kojto	90:cb3d968589d8	3644	#define BW_ENET_TAEM_TX_ALMOST_EMPTY(x, v) (HW_ENET_TAEM_WR(x, (HW_ENET_TAEM_RD(x) & ~BM_ENET_TAEM_TX_ALMOST_EMPTY) \| BF_ENET_TAEM_TX_ALMOST_EMPTY(v)))
Kojto	90:cb3d968589d8	3645	/@}/
Kojto	90:cb3d968589d8	3646
Kojto	90:cb3d968589d8	3647	/*******************************************************************************
Kojto	90:cb3d968589d8	3648	* HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
Kojto	90:cb3d968589d8	3649	******************************************************************************/
Kojto	90:cb3d968589d8	3650
Kojto	90:cb3d968589d8	3651	/*!
Kojto	90:cb3d968589d8	3652	* @brief HW_ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
Kojto	90:cb3d968589d8	3653	*
Kojto	90:cb3d968589d8	3654	* Reset value: 0x00000008U
Kojto	90:cb3d968589d8	3655	*/
Kojto	90:cb3d968589d8	3656	typedef union _hw_enet_tafl
Kojto	90:cb3d968589d8	3657	{
Kojto	90:cb3d968589d8	3658	uint32_t U;
Kojto	90:cb3d968589d8	3659	struct _hw_enet_tafl_bitfields
Kojto	90:cb3d968589d8	3660	{
Kojto	90:cb3d968589d8	3661	uint32_t TX_ALMOST_FULL : 8; /*!< [7:0] Value Of The Transmit FIFO
Kojto	90:cb3d968589d8	3662	* Almost Full Threshold */
Kojto	90:cb3d968589d8	3663	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	3664	} B;
Kojto	90:cb3d968589d8	3665	} hw_enet_tafl_t;
Kojto	90:cb3d968589d8	3666
Kojto	90:cb3d968589d8	3667	/*!
Kojto	90:cb3d968589d8	3668	* @name Constants and macros for entire ENET_TAFL register
Kojto	90:cb3d968589d8	3669	*/
Kojto	90:cb3d968589d8	3670	/@{/
Kojto	90:cb3d968589d8	3671	#define HW_ENET_TAFL_ADDR(x) ((x) + 0x1A8U)
Kojto	90:cb3d968589d8	3672
Kojto	90:cb3d968589d8	3673	#define HW_ENET_TAFL(x) ((__IO hw_enet_tafl_t ) HW_ENET_TAFL_ADDR(x))
Kojto	90:cb3d968589d8	3674	#define HW_ENET_TAFL_RD(x) (HW_ENET_TAFL(x).U)
Kojto	90:cb3d968589d8	3675	#define HW_ENET_TAFL_WR(x, v) (HW_ENET_TAFL(x).U = (v))
Kojto	90:cb3d968589d8	3676	#define HW_ENET_TAFL_SET(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3677	#define HW_ENET_TAFL_CLR(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3678	#define HW_ENET_TAFL_TOG(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3679	/@}/
Kojto	90:cb3d968589d8	3680
Kojto	90:cb3d968589d8	3681	/*
Kojto	90:cb3d968589d8	3682	* Constants & macros for individual ENET_TAFL bitfields
Kojto	90:cb3d968589d8	3683	*/
Kojto	90:cb3d968589d8	3684
Kojto	90:cb3d968589d8	3685	/*!
Kojto	90:cb3d968589d8	3686	* @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
Kojto	90:cb3d968589d8	3687	*
Kojto	90:cb3d968589d8	3688	* Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
Kojto	90:cb3d968589d8	3689	* value of six is required . A recommended value of at least 8 should be set
Kojto	90:cb3d968589d8	3690	* allowing a latency of two clock cycles to the application. If more latency is
Kojto	90:cb3d968589d8	3691	* required the value can be increased as necessary (latency = TAFL - 5). When the
Kojto	90:cb3d968589d8	3692	* FIFO level comes close to the maximum, so that there is no more space for at
Kojto	90:cb3d968589d8	3693	* least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
Kojto	90:cb3d968589d8	3694	* application does not react on this signal, the FIFO write control logic, to
Kojto	90:cb3d968589d8	3695	* avoid FIFO overflow, truncates the current frame and sets the error status. As a
Kojto	90:cb3d968589d8	3696	* result, the frame will be transmitted with an GMII/MII error indication. See
Kojto	90:cb3d968589d8	3697	* Transmit FIFOFour programmable thresholds are available which control the core
Kojto	90:cb3d968589d8	3698	* operation. for more information. A FIFO overflow is a fatal error and requires
Kojto	90:cb3d968589d8	3699	* a global reset on the transmit datapath or at least deassertion of ETHEREN.
Kojto	90:cb3d968589d8	3700	*/
Kojto	90:cb3d968589d8	3701	/@{/
Kojto	90:cb3d968589d8	3702	#define BP_ENET_TAFL_TX_ALMOST_FULL (0U) /!< Bit position for ENET_TAFL_TX_ALMOST_FULL. /
Kojto	90:cb3d968589d8	3703	#define BM_ENET_TAFL_TX_ALMOST_FULL (0x000000FFU) /!< Bit mask for ENET_TAFL_TX_ALMOST_FULL. /
Kojto	90:cb3d968589d8	3704	#define BS_ENET_TAFL_TX_ALMOST_FULL (8U) /!< Bit field size in bits for ENET_TAFL_TX_ALMOST_FULL. /
Kojto	90:cb3d968589d8	3705
Kojto	90:cb3d968589d8	3706	/! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field. /
Kojto	90:cb3d968589d8	3707	#define BR_ENET_TAFL_TX_ALMOST_FULL(x) (HW_ENET_TAFL(x).B.TX_ALMOST_FULL)
Kojto	90:cb3d968589d8	3708
Kojto	90:cb3d968589d8	3709	/! @brief Format value for bitfield ENET_TAFL_TX_ALMOST_FULL. /
Kojto	90:cb3d968589d8	3710	#define BF_ENET_TAFL_TX_ALMOST_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TAFL_TX_ALMOST_FULL) & BM_ENET_TAFL_TX_ALMOST_FULL)
Kojto	90:cb3d968589d8	3711
Kojto	90:cb3d968589d8	3712	/! @brief Set the TX_ALMOST_FULL field to a new value. /
Kojto	90:cb3d968589d8	3713	#define BW_ENET_TAFL_TX_ALMOST_FULL(x, v) (HW_ENET_TAFL_WR(x, (HW_ENET_TAFL_RD(x) & ~BM_ENET_TAFL_TX_ALMOST_FULL) \| BF_ENET_TAFL_TX_ALMOST_FULL(v)))
Kojto	90:cb3d968589d8	3714	/@}/
Kojto	90:cb3d968589d8	3715
Kojto	90:cb3d968589d8	3716	/*******************************************************************************
Kojto	90:cb3d968589d8	3717	* HW_ENET_TIPG - Transmit Inter-Packet Gap
Kojto	90:cb3d968589d8	3718	******************************************************************************/
Kojto	90:cb3d968589d8	3719
Kojto	90:cb3d968589d8	3720	/*!
Kojto	90:cb3d968589d8	3721	* @brief HW_ENET_TIPG - Transmit Inter-Packet Gap (RW)
Kojto	90:cb3d968589d8	3722	*
Kojto	90:cb3d968589d8	3723	* Reset value: 0x0000000CU
Kojto	90:cb3d968589d8	3724	*/
Kojto	90:cb3d968589d8	3725	typedef union _hw_enet_tipg
Kojto	90:cb3d968589d8	3726	{
Kojto	90:cb3d968589d8	3727	uint32_t U;
Kojto	90:cb3d968589d8	3728	struct _hw_enet_tipg_bitfields
Kojto	90:cb3d968589d8	3729	{
Kojto	90:cb3d968589d8	3730	uint32_t IPG : 5; /!< [4:0] Transmit Inter-Packet Gap /
Kojto	90:cb3d968589d8	3731	uint32_t RESERVED0 : 27; /!< [31:5] /
Kojto	90:cb3d968589d8	3732	} B;
Kojto	90:cb3d968589d8	3733	} hw_enet_tipg_t;
Kojto	90:cb3d968589d8	3734
Kojto	90:cb3d968589d8	3735	/*!
Kojto	90:cb3d968589d8	3736	* @name Constants and macros for entire ENET_TIPG register
Kojto	90:cb3d968589d8	3737	*/
Kojto	90:cb3d968589d8	3738	/@{/
Kojto	90:cb3d968589d8	3739	#define HW_ENET_TIPG_ADDR(x) ((x) + 0x1ACU)
Kojto	90:cb3d968589d8	3740
Kojto	90:cb3d968589d8	3741	#define HW_ENET_TIPG(x) ((__IO hw_enet_tipg_t ) HW_ENET_TIPG_ADDR(x))
Kojto	90:cb3d968589d8	3742	#define HW_ENET_TIPG_RD(x) (HW_ENET_TIPG(x).U)
Kojto	90:cb3d968589d8	3743	#define HW_ENET_TIPG_WR(x, v) (HW_ENET_TIPG(x).U = (v))
Kojto	90:cb3d968589d8	3744	#define HW_ENET_TIPG_SET(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3745	#define HW_ENET_TIPG_CLR(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3746	#define HW_ENET_TIPG_TOG(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3747	/@}/
Kojto	90:cb3d968589d8	3748
Kojto	90:cb3d968589d8	3749	/*
Kojto	90:cb3d968589d8	3750	* Constants & macros for individual ENET_TIPG bitfields
Kojto	90:cb3d968589d8	3751	*/
Kojto	90:cb3d968589d8	3752
Kojto	90:cb3d968589d8	3753	/*!
Kojto	90:cb3d968589d8	3754	* @name Register ENET_TIPG, field IPG[4:0] (RW)
Kojto	90:cb3d968589d8	3755	*
Kojto	90:cb3d968589d8	3756	* Indicates the IPG, in bytes, between transmitted frames. Valid values range
Kojto	90:cb3d968589d8	3757	* from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
Kojto	90:cb3d968589d8	3758	* 27, the IPG is 27.
Kojto	90:cb3d968589d8	3759	*/
Kojto	90:cb3d968589d8	3760	/@{/
Kojto	90:cb3d968589d8	3761	#define BP_ENET_TIPG_IPG (0U) /!< Bit position for ENET_TIPG_IPG. /
Kojto	90:cb3d968589d8	3762	#define BM_ENET_TIPG_IPG (0x0000001FU) /!< Bit mask for ENET_TIPG_IPG. /
Kojto	90:cb3d968589d8	3763	#define BS_ENET_TIPG_IPG (5U) /!< Bit field size in bits for ENET_TIPG_IPG. /
Kojto	90:cb3d968589d8	3764
Kojto	90:cb3d968589d8	3765	/! @brief Read current value of the ENET_TIPG_IPG field. /
Kojto	90:cb3d968589d8	3766	#define BR_ENET_TIPG_IPG(x) (HW_ENET_TIPG(x).B.IPG)
Kojto	90:cb3d968589d8	3767
Kojto	90:cb3d968589d8	3768	/! @brief Format value for bitfield ENET_TIPG_IPG. /
Kojto	90:cb3d968589d8	3769	#define BF_ENET_TIPG_IPG(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TIPG_IPG) & BM_ENET_TIPG_IPG)
Kojto	90:cb3d968589d8	3770
Kojto	90:cb3d968589d8	3771	/! @brief Set the IPG field to a new value. /
Kojto	90:cb3d968589d8	3772	#define BW_ENET_TIPG_IPG(x, v) (HW_ENET_TIPG_WR(x, (HW_ENET_TIPG_RD(x) & ~BM_ENET_TIPG_IPG) \| BF_ENET_TIPG_IPG(v)))
Kojto	90:cb3d968589d8	3773	/@}/
Kojto	90:cb3d968589d8	3774
Kojto	90:cb3d968589d8	3775	/*******************************************************************************
Kojto	90:cb3d968589d8	3776	* HW_ENET_FTRL - Frame Truncation Length
Kojto	90:cb3d968589d8	3777	******************************************************************************/
Kojto	90:cb3d968589d8	3778
Kojto	90:cb3d968589d8	3779	/*!
Kojto	90:cb3d968589d8	3780	* @brief HW_ENET_FTRL - Frame Truncation Length (RW)
Kojto	90:cb3d968589d8	3781	*
Kojto	90:cb3d968589d8	3782	* Reset value: 0x000007FFU
Kojto	90:cb3d968589d8	3783	*/
Kojto	90:cb3d968589d8	3784	typedef union _hw_enet_ftrl
Kojto	90:cb3d968589d8	3785	{
Kojto	90:cb3d968589d8	3786	uint32_t U;
Kojto	90:cb3d968589d8	3787	struct _hw_enet_ftrl_bitfields
Kojto	90:cb3d968589d8	3788	{
Kojto	90:cb3d968589d8	3789	uint32_t TRUNC_FL : 14; /!< [13:0] Frame Truncation Length /
Kojto	90:cb3d968589d8	3790	uint32_t RESERVED0 : 18; /!< [31:14] /
Kojto	90:cb3d968589d8	3791	} B;
Kojto	90:cb3d968589d8	3792	} hw_enet_ftrl_t;
Kojto	90:cb3d968589d8	3793
Kojto	90:cb3d968589d8	3794	/*!
Kojto	90:cb3d968589d8	3795	* @name Constants and macros for entire ENET_FTRL register
Kojto	90:cb3d968589d8	3796	*/
Kojto	90:cb3d968589d8	3797	/@{/
Kojto	90:cb3d968589d8	3798	#define HW_ENET_FTRL_ADDR(x) ((x) + 0x1B0U)
Kojto	90:cb3d968589d8	3799
Kojto	90:cb3d968589d8	3800	#define HW_ENET_FTRL(x) ((__IO hw_enet_ftrl_t ) HW_ENET_FTRL_ADDR(x))
Kojto	90:cb3d968589d8	3801	#define HW_ENET_FTRL_RD(x) (HW_ENET_FTRL(x).U)
Kojto	90:cb3d968589d8	3802	#define HW_ENET_FTRL_WR(x, v) (HW_ENET_FTRL(x).U = (v))
Kojto	90:cb3d968589d8	3803	#define HW_ENET_FTRL_SET(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3804	#define HW_ENET_FTRL_CLR(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3805	#define HW_ENET_FTRL_TOG(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3806	/@}/
Kojto	90:cb3d968589d8	3807
Kojto	90:cb3d968589d8	3808	/*
Kojto	90:cb3d968589d8	3809	* Constants & macros for individual ENET_FTRL bitfields
Kojto	90:cb3d968589d8	3810	*/
Kojto	90:cb3d968589d8	3811
Kojto	90:cb3d968589d8	3812	/*!
Kojto	90:cb3d968589d8	3813	* @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
Kojto	90:cb3d968589d8	3814	*
Kojto	90:cb3d968589d8	3815	* Indicates the value a receive frame is truncated, if it is greater than this
Kojto	90:cb3d968589d8	3816	* value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
Kojto	90:cb3d968589d8	3817	* TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
Kojto	90:cb3d968589d8	3818	* less data, guaranteeing that it never receives more than the set limit.
Kojto	90:cb3d968589d8	3819	*/
Kojto	90:cb3d968589d8	3820	/@{/
Kojto	90:cb3d968589d8	3821	#define BP_ENET_FTRL_TRUNC_FL (0U) /!< Bit position for ENET_FTRL_TRUNC_FL. /
Kojto	90:cb3d968589d8	3822	#define BM_ENET_FTRL_TRUNC_FL (0x00003FFFU) /!< Bit mask for ENET_FTRL_TRUNC_FL. /
Kojto	90:cb3d968589d8	3823	#define BS_ENET_FTRL_TRUNC_FL (14U) /!< Bit field size in bits for ENET_FTRL_TRUNC_FL. /
Kojto	90:cb3d968589d8	3824
Kojto	90:cb3d968589d8	3825	/! @brief Read current value of the ENET_FTRL_TRUNC_FL field. /
Kojto	90:cb3d968589d8	3826	#define BR_ENET_FTRL_TRUNC_FL(x) (HW_ENET_FTRL(x).B.TRUNC_FL)
Kojto	90:cb3d968589d8	3827
Kojto	90:cb3d968589d8	3828	/! @brief Format value for bitfield ENET_FTRL_TRUNC_FL. /
Kojto	90:cb3d968589d8	3829	#define BF_ENET_FTRL_TRUNC_FL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_FTRL_TRUNC_FL) & BM_ENET_FTRL_TRUNC_FL)
Kojto	90:cb3d968589d8	3830
Kojto	90:cb3d968589d8	3831	/! @brief Set the TRUNC_FL field to a new value. /
Kojto	90:cb3d968589d8	3832	#define BW_ENET_FTRL_TRUNC_FL(x, v) (HW_ENET_FTRL_WR(x, (HW_ENET_FTRL_RD(x) & ~BM_ENET_FTRL_TRUNC_FL) \| BF_ENET_FTRL_TRUNC_FL(v)))
Kojto	90:cb3d968589d8	3833	/@}/
Kojto	90:cb3d968589d8	3834
Kojto	90:cb3d968589d8	3835	/*******************************************************************************
Kojto	90:cb3d968589d8	3836	* HW_ENET_TACC - Transmit Accelerator Function Configuration
Kojto	90:cb3d968589d8	3837	******************************************************************************/
Kojto	90:cb3d968589d8	3838
Kojto	90:cb3d968589d8	3839	/*!
Kojto	90:cb3d968589d8	3840	* @brief HW_ENET_TACC - Transmit Accelerator Function Configuration (RW)
Kojto	90:cb3d968589d8	3841	*
Kojto	90:cb3d968589d8	3842	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3843	*
Kojto	90:cb3d968589d8	3844	* TACC controls accelerator actions when sending frames. The register can be
Kojto	90:cb3d968589d8	3845	* changed before or after each frame, but it must remain unmodified during frame
Kojto	90:cb3d968589d8	3846	* writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
Kojto	90:cb3d968589d8	3847	* checksum feature.
Kojto	90:cb3d968589d8	3848	*/
Kojto	90:cb3d968589d8	3849	typedef union _hw_enet_tacc
Kojto	90:cb3d968589d8	3850	{
Kojto	90:cb3d968589d8	3851	uint32_t U;
Kojto	90:cb3d968589d8	3852	struct _hw_enet_tacc_bitfields
Kojto	90:cb3d968589d8	3853	{
Kojto	90:cb3d968589d8	3854	uint32_t SHIFT16 : 1; /!< [0] TX FIFO Shift-16 /
Kojto	90:cb3d968589d8	3855	uint32_t RESERVED0 : 2; /!< [2:1] /
Kojto	90:cb3d968589d8	3856	uint32_t IPCHK : 1; /!< [3] /
Kojto	90:cb3d968589d8	3857	uint32_t PROCHK : 1; /!< [4] /
Kojto	90:cb3d968589d8	3858	uint32_t RESERVED1 : 27; /!< [31:5] /
Kojto	90:cb3d968589d8	3859	} B;
Kojto	90:cb3d968589d8	3860	} hw_enet_tacc_t;
Kojto	90:cb3d968589d8	3861
Kojto	90:cb3d968589d8	3862	/*!
Kojto	90:cb3d968589d8	3863	* @name Constants and macros for entire ENET_TACC register
Kojto	90:cb3d968589d8	3864	*/
Kojto	90:cb3d968589d8	3865	/@{/
Kojto	90:cb3d968589d8	3866	#define HW_ENET_TACC_ADDR(x) ((x) + 0x1C0U)
Kojto	90:cb3d968589d8	3867
Kojto	90:cb3d968589d8	3868	#define HW_ENET_TACC(x) ((__IO hw_enet_tacc_t ) HW_ENET_TACC_ADDR(x))
Kojto	90:cb3d968589d8	3869	#define HW_ENET_TACC_RD(x) (HW_ENET_TACC(x).U)
Kojto	90:cb3d968589d8	3870	#define HW_ENET_TACC_WR(x, v) (HW_ENET_TACC(x).U = (v))
Kojto	90:cb3d968589d8	3871	#define HW_ENET_TACC_SET(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3872	#define HW_ENET_TACC_CLR(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3873	#define HW_ENET_TACC_TOG(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3874	/@}/
Kojto	90:cb3d968589d8	3875
Kojto	90:cb3d968589d8	3876	/*
Kojto	90:cb3d968589d8	3877	* Constants & macros for individual ENET_TACC bitfields
Kojto	90:cb3d968589d8	3878	*/
Kojto	90:cb3d968589d8	3879
Kojto	90:cb3d968589d8	3880	/*!
Kojto	90:cb3d968589d8	3881	* @name Register ENET_TACC, field SHIFT16[0] (RW)
Kojto	90:cb3d968589d8	3882	*
Kojto	90:cb3d968589d8	3883	* Values:
Kojto	90:cb3d968589d8	3884	* - 0 - Disabled.
Kojto	90:cb3d968589d8	3885	* - 1 - Indicates to the transmit data FIFO that the written frames contain two
Kojto	90:cb3d968589d8	3886	* additional octets before the frame data. This means the actual frame
Kojto	90:cb3d968589d8	3887	* begins at bit 16 of the first word written into the FIFO. This function allows
Kojto	90:cb3d968589d8	3888	* putting the frame payload on a 32-bit boundary in memory, as the 14-byte
Kojto	90:cb3d968589d8	3889	* Ethernet header is extended to a 16-byte header.
Kojto	90:cb3d968589d8	3890	*/
Kojto	90:cb3d968589d8	3891	/@{/
Kojto	90:cb3d968589d8	3892	#define BP_ENET_TACC_SHIFT16 (0U) /!< Bit position for ENET_TACC_SHIFT16. /
Kojto	90:cb3d968589d8	3893	#define BM_ENET_TACC_SHIFT16 (0x00000001U) /!< Bit mask for ENET_TACC_SHIFT16. /
Kojto	90:cb3d968589d8	3894	#define BS_ENET_TACC_SHIFT16 (1U) /!< Bit field size in bits for ENET_TACC_SHIFT16. /
Kojto	90:cb3d968589d8	3895
Kojto	90:cb3d968589d8	3896	/! @brief Read current value of the ENET_TACC_SHIFT16 field. /
Kojto	90:cb3d968589d8	3897	#define BR_ENET_TACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16))
Kojto	90:cb3d968589d8	3898
Kojto	90:cb3d968589d8	3899	/! @brief Format value for bitfield ENET_TACC_SHIFT16. /
Kojto	90:cb3d968589d8	3900	#define BF_ENET_TACC_SHIFT16(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_SHIFT16) & BM_ENET_TACC_SHIFT16)
Kojto	90:cb3d968589d8	3901
Kojto	90:cb3d968589d8	3902	/! @brief Set the SHIFT16 field to a new value. /
Kojto	90:cb3d968589d8	3903	#define BW_ENET_TACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16) = (v))
Kojto	90:cb3d968589d8	3904	/@}/
Kojto	90:cb3d968589d8	3905
Kojto	90:cb3d968589d8	3906	/*!
Kojto	90:cb3d968589d8	3907	* @name Register ENET_TACC, field IPCHK[3] (RW)
Kojto	90:cb3d968589d8	3908	*
Kojto	90:cb3d968589d8	3909	* Enables insertion of IP header checksum.
Kojto	90:cb3d968589d8	3910	*
Kojto	90:cb3d968589d8	3911	* Values:
Kojto	90:cb3d968589d8	3912	* - 0 - Checksum is not inserted.
Kojto	90:cb3d968589d8	3913	* - 1 - If an IP frame is transmitted, the checksum is inserted automatically.
Kojto	90:cb3d968589d8	3914	* The IP header checksum field must be cleared. If a non-IP frame is
Kojto	90:cb3d968589d8	3915	* transmitted the frame is not modified.
Kojto	90:cb3d968589d8	3916	*/
Kojto	90:cb3d968589d8	3917	/@{/
Kojto	90:cb3d968589d8	3918	#define BP_ENET_TACC_IPCHK (3U) /!< Bit position for ENET_TACC_IPCHK. /
Kojto	90:cb3d968589d8	3919	#define BM_ENET_TACC_IPCHK (0x00000008U) /!< Bit mask for ENET_TACC_IPCHK. /
Kojto	90:cb3d968589d8	3920	#define BS_ENET_TACC_IPCHK (1U) /!< Bit field size in bits for ENET_TACC_IPCHK. /
Kojto	90:cb3d968589d8	3921
Kojto	90:cb3d968589d8	3922	/! @brief Read current value of the ENET_TACC_IPCHK field. /
Kojto	90:cb3d968589d8	3923	#define BR_ENET_TACC_IPCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK))
Kojto	90:cb3d968589d8	3924
Kojto	90:cb3d968589d8	3925	/! @brief Format value for bitfield ENET_TACC_IPCHK. /
Kojto	90:cb3d968589d8	3926	#define BF_ENET_TACC_IPCHK(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_IPCHK) & BM_ENET_TACC_IPCHK)
Kojto	90:cb3d968589d8	3927
Kojto	90:cb3d968589d8	3928	/! @brief Set the IPCHK field to a new value. /
Kojto	90:cb3d968589d8	3929	#define BW_ENET_TACC_IPCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK) = (v))
Kojto	90:cb3d968589d8	3930	/@}/
Kojto	90:cb3d968589d8	3931
Kojto	90:cb3d968589d8	3932	/*!
Kojto	90:cb3d968589d8	3933	* @name Register ENET_TACC, field PROCHK[4] (RW)
Kojto	90:cb3d968589d8	3934	*
Kojto	90:cb3d968589d8	3935	* Enables insertion of protocol checksum.
Kojto	90:cb3d968589d8	3936	*
Kojto	90:cb3d968589d8	3937	* Values:
Kojto	90:cb3d968589d8	3938	* - 0 - Checksum not inserted.
Kojto	90:cb3d968589d8	3939	* - 1 - If an IP frame with a known protocol is transmitted, the checksum is
Kojto	90:cb3d968589d8	3940	* inserted automatically into the frame. The checksum field must be cleared.
Kojto	90:cb3d968589d8	3941	* The other frames are not modified.
Kojto	90:cb3d968589d8	3942	*/
Kojto	90:cb3d968589d8	3943	/@{/
Kojto	90:cb3d968589d8	3944	#define BP_ENET_TACC_PROCHK (4U) /!< Bit position for ENET_TACC_PROCHK. /
Kojto	90:cb3d968589d8	3945	#define BM_ENET_TACC_PROCHK (0x00000010U) /!< Bit mask for ENET_TACC_PROCHK. /
Kojto	90:cb3d968589d8	3946	#define BS_ENET_TACC_PROCHK (1U) /!< Bit field size in bits for ENET_TACC_PROCHK. /
Kojto	90:cb3d968589d8	3947
Kojto	90:cb3d968589d8	3948	/! @brief Read current value of the ENET_TACC_PROCHK field. /
Kojto	90:cb3d968589d8	3949	#define BR_ENET_TACC_PROCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK))
Kojto	90:cb3d968589d8	3950
Kojto	90:cb3d968589d8	3951	/! @brief Format value for bitfield ENET_TACC_PROCHK. /
Kojto	90:cb3d968589d8	3952	#define BF_ENET_TACC_PROCHK(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_PROCHK) & BM_ENET_TACC_PROCHK)
Kojto	90:cb3d968589d8	3953
Kojto	90:cb3d968589d8	3954	/! @brief Set the PROCHK field to a new value. /
Kojto	90:cb3d968589d8	3955	#define BW_ENET_TACC_PROCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK) = (v))
Kojto	90:cb3d968589d8	3956	/@}/
Kojto	90:cb3d968589d8	3957
Kojto	90:cb3d968589d8	3958	/*******************************************************************************
Kojto	90:cb3d968589d8	3959	* HW_ENET_RACC - Receive Accelerator Function Configuration
Kojto	90:cb3d968589d8	3960	******************************************************************************/
Kojto	90:cb3d968589d8	3961
Kojto	90:cb3d968589d8	3962	/*!
Kojto	90:cb3d968589d8	3963	* @brief HW_ENET_RACC - Receive Accelerator Function Configuration (RW)
Kojto	90:cb3d968589d8	3964	*
Kojto	90:cb3d968589d8	3965	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3966	*/
Kojto	90:cb3d968589d8	3967	typedef union _hw_enet_racc
Kojto	90:cb3d968589d8	3968	{
Kojto	90:cb3d968589d8	3969	uint32_t U;
Kojto	90:cb3d968589d8	3970	struct _hw_enet_racc_bitfields
Kojto	90:cb3d968589d8	3971	{
Kojto	90:cb3d968589d8	3972	uint32_t PADREM : 1; /*!< [0] Enable Padding Removal For Short IP
Kojto	90:cb3d968589d8	3973	* Frames */
Kojto	90:cb3d968589d8	3974	uint32_t IPDIS : 1; /*!< [1] Enable Discard Of Frames With Wrong IPv4
Kojto	90:cb3d968589d8	3975	* Header Checksum */
Kojto	90:cb3d968589d8	3976	uint32_t PRODIS : 1; /*!< [2] Enable Discard Of Frames With Wrong
Kojto	90:cb3d968589d8	3977	* Protocol Checksum */
Kojto	90:cb3d968589d8	3978	uint32_t RESERVED0 : 3; /!< [5:3] /
Kojto	90:cb3d968589d8	3979	uint32_t LINEDIS : 1; /*!< [6] Enable Discard Of Frames With MAC
Kojto	90:cb3d968589d8	3980	* Layer Errors */
Kojto	90:cb3d968589d8	3981	uint32_t SHIFT16 : 1; /!< [7] RX FIFO Shift-16 /
Kojto	90:cb3d968589d8	3982	uint32_t RESERVED1 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	3983	} B;
Kojto	90:cb3d968589d8	3984	} hw_enet_racc_t;
Kojto	90:cb3d968589d8	3985
Kojto	90:cb3d968589d8	3986	/*!
Kojto	90:cb3d968589d8	3987	* @name Constants and macros for entire ENET_RACC register
Kojto	90:cb3d968589d8	3988	*/
Kojto	90:cb3d968589d8	3989	/@{/
Kojto	90:cb3d968589d8	3990	#define HW_ENET_RACC_ADDR(x) ((x) + 0x1C4U)
Kojto	90:cb3d968589d8	3991
Kojto	90:cb3d968589d8	3992	#define HW_ENET_RACC(x) ((__IO hw_enet_racc_t ) HW_ENET_RACC_ADDR(x))
Kojto	90:cb3d968589d8	3993	#define HW_ENET_RACC_RD(x) (HW_ENET_RACC(x).U)
Kojto	90:cb3d968589d8	3994	#define HW_ENET_RACC_WR(x, v) (HW_ENET_RACC(x).U = (v))
Kojto	90:cb3d968589d8	3995	#define HW_ENET_RACC_SET(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3996	#define HW_ENET_RACC_CLR(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3997	#define HW_ENET_RACC_TOG(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3998	/@}/
Kojto	90:cb3d968589d8	3999
Kojto	90:cb3d968589d8	4000	/*
Kojto	90:cb3d968589d8	4001	* Constants & macros for individual ENET_RACC bitfields
Kojto	90:cb3d968589d8	4002	*/
Kojto	90:cb3d968589d8	4003
Kojto	90:cb3d968589d8	4004	/*!
Kojto	90:cb3d968589d8	4005	* @name Register ENET_RACC, field PADREM[0] (RW)
Kojto	90:cb3d968589d8	4006	*
Kojto	90:cb3d968589d8	4007	* Values:
Kojto	90:cb3d968589d8	4008	* - 0 - Padding not removed.
Kojto	90:cb3d968589d8	4009	* - 1 - Any bytes following the IP payload section of the frame are removed
Kojto	90:cb3d968589d8	4010	* from the frame.
Kojto	90:cb3d968589d8	4011	*/
Kojto	90:cb3d968589d8	4012	/@{/
Kojto	90:cb3d968589d8	4013	#define BP_ENET_RACC_PADREM (0U) /!< Bit position for ENET_RACC_PADREM. /
Kojto	90:cb3d968589d8	4014	#define BM_ENET_RACC_PADREM (0x00000001U) /!< Bit mask for ENET_RACC_PADREM. /
Kojto	90:cb3d968589d8	4015	#define BS_ENET_RACC_PADREM (1U) /!< Bit field size in bits for ENET_RACC_PADREM. /
Kojto	90:cb3d968589d8	4016
Kojto	90:cb3d968589d8	4017	/! @brief Read current value of the ENET_RACC_PADREM field. /
Kojto	90:cb3d968589d8	4018	#define BR_ENET_RACC_PADREM(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM))
Kojto	90:cb3d968589d8	4019
Kojto	90:cb3d968589d8	4020	/! @brief Format value for bitfield ENET_RACC_PADREM. /
Kojto	90:cb3d968589d8	4021	#define BF_ENET_RACC_PADREM(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_PADREM) & BM_ENET_RACC_PADREM)
Kojto	90:cb3d968589d8	4022
Kojto	90:cb3d968589d8	4023	/! @brief Set the PADREM field to a new value. /
Kojto	90:cb3d968589d8	4024	#define BW_ENET_RACC_PADREM(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM) = (v))
Kojto	90:cb3d968589d8	4025	/@}/
Kojto	90:cb3d968589d8	4026
Kojto	90:cb3d968589d8	4027	/*!
Kojto	90:cb3d968589d8	4028	* @name Register ENET_RACC, field IPDIS[1] (RW)
Kojto	90:cb3d968589d8	4029	*
Kojto	90:cb3d968589d8	4030	* Values:
Kojto	90:cb3d968589d8	4031	* - 0 - Frames with wrong IPv4 header checksum are not discarded.
Kojto	90:cb3d968589d8	4032	* - 1 - If an IPv4 frame is received with a mismatching header checksum, the
Kojto	90:cb3d968589d8	4033	* frame is discarded. IPv6 has no header checksum and is not affected by this
Kojto	90:cb3d968589d8	4034	* setting. Discarding is only available when the RX FIFO operates in store
Kojto	90:cb3d968589d8	4035	* and forward mode (RSFL cleared).
Kojto	90:cb3d968589d8	4036	*/
Kojto	90:cb3d968589d8	4037	/@{/
Kojto	90:cb3d968589d8	4038	#define BP_ENET_RACC_IPDIS (1U) /!< Bit position for ENET_RACC_IPDIS. /
Kojto	90:cb3d968589d8	4039	#define BM_ENET_RACC_IPDIS (0x00000002U) /!< Bit mask for ENET_RACC_IPDIS. /
Kojto	90:cb3d968589d8	4040	#define BS_ENET_RACC_IPDIS (1U) /!< Bit field size in bits for ENET_RACC_IPDIS. /
Kojto	90:cb3d968589d8	4041
Kojto	90:cb3d968589d8	4042	/! @brief Read current value of the ENET_RACC_IPDIS field. /
Kojto	90:cb3d968589d8	4043	#define BR_ENET_RACC_IPDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS))
Kojto	90:cb3d968589d8	4044
Kojto	90:cb3d968589d8	4045	/! @brief Format value for bitfield ENET_RACC_IPDIS. /
Kojto	90:cb3d968589d8	4046	#define BF_ENET_RACC_IPDIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_IPDIS) & BM_ENET_RACC_IPDIS)
Kojto	90:cb3d968589d8	4047
Kojto	90:cb3d968589d8	4048	/! @brief Set the IPDIS field to a new value. /
Kojto	90:cb3d968589d8	4049	#define BW_ENET_RACC_IPDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS) = (v))
Kojto	90:cb3d968589d8	4050	/@}/
Kojto	90:cb3d968589d8	4051
Kojto	90:cb3d968589d8	4052	/*!
Kojto	90:cb3d968589d8	4053	* @name Register ENET_RACC, field PRODIS[2] (RW)
Kojto	90:cb3d968589d8	4054	*
Kojto	90:cb3d968589d8	4055	* Values:
Kojto	90:cb3d968589d8	4056	* - 0 - Frames with wrong checksum are not discarded.
Kojto	90:cb3d968589d8	4057	* - 1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP,
Kojto	90:cb3d968589d8	4058	* UDP, or ICMP checksum, the frame is discarded. Discarding is only
Kojto	90:cb3d968589d8	4059	* available when the RX FIFO operates in store and forward mode (RSFL cleared).
Kojto	90:cb3d968589d8	4060	*/
Kojto	90:cb3d968589d8	4061	/@{/
Kojto	90:cb3d968589d8	4062	#define BP_ENET_RACC_PRODIS (2U) /!< Bit position for ENET_RACC_PRODIS. /
Kojto	90:cb3d968589d8	4063	#define BM_ENET_RACC_PRODIS (0x00000004U) /!< Bit mask for ENET_RACC_PRODIS. /
Kojto	90:cb3d968589d8	4064	#define BS_ENET_RACC_PRODIS (1U) /!< Bit field size in bits for ENET_RACC_PRODIS. /
Kojto	90:cb3d968589d8	4065
Kojto	90:cb3d968589d8	4066	/! @brief Read current value of the ENET_RACC_PRODIS field. /
Kojto	90:cb3d968589d8	4067	#define BR_ENET_RACC_PRODIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS))
Kojto	90:cb3d968589d8	4068
Kojto	90:cb3d968589d8	4069	/! @brief Format value for bitfield ENET_RACC_PRODIS. /
Kojto	90:cb3d968589d8	4070	#define BF_ENET_RACC_PRODIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_PRODIS) & BM_ENET_RACC_PRODIS)
Kojto	90:cb3d968589d8	4071
Kojto	90:cb3d968589d8	4072	/! @brief Set the PRODIS field to a new value. /
Kojto	90:cb3d968589d8	4073	#define BW_ENET_RACC_PRODIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS) = (v))
Kojto	90:cb3d968589d8	4074	/@}/
Kojto	90:cb3d968589d8	4075
Kojto	90:cb3d968589d8	4076	/*!
Kojto	90:cb3d968589d8	4077	* @name Register ENET_RACC, field LINEDIS[6] (RW)
Kojto	90:cb3d968589d8	4078	*
Kojto	90:cb3d968589d8	4079	* Values:
Kojto	90:cb3d968589d8	4080	* - 0 - Frames with errors are not discarded.
Kojto	90:cb3d968589d8	4081	* - 1 - Any frame received with a CRC, length, or PHY error is automatically
Kojto	90:cb3d968589d8	4082	* discarded and not forwarded to the user application interface.
Kojto	90:cb3d968589d8	4083	*/
Kojto	90:cb3d968589d8	4084	/@{/
Kojto	90:cb3d968589d8	4085	#define BP_ENET_RACC_LINEDIS (6U) /!< Bit position for ENET_RACC_LINEDIS. /
Kojto	90:cb3d968589d8	4086	#define BM_ENET_RACC_LINEDIS (0x00000040U) /!< Bit mask for ENET_RACC_LINEDIS. /
Kojto	90:cb3d968589d8	4087	#define BS_ENET_RACC_LINEDIS (1U) /!< Bit field size in bits for ENET_RACC_LINEDIS. /
Kojto	90:cb3d968589d8	4088
Kojto	90:cb3d968589d8	4089	/! @brief Read current value of the ENET_RACC_LINEDIS field. /
Kojto	90:cb3d968589d8	4090	#define BR_ENET_RACC_LINEDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS))
Kojto	90:cb3d968589d8	4091
Kojto	90:cb3d968589d8	4092	/! @brief Format value for bitfield ENET_RACC_LINEDIS. /
Kojto	90:cb3d968589d8	4093	#define BF_ENET_RACC_LINEDIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_LINEDIS) & BM_ENET_RACC_LINEDIS)
Kojto	90:cb3d968589d8	4094
Kojto	90:cb3d968589d8	4095	/! @brief Set the LINEDIS field to a new value. /
Kojto	90:cb3d968589d8	4096	#define BW_ENET_RACC_LINEDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS) = (v))
Kojto	90:cb3d968589d8	4097	/@}/
Kojto	90:cb3d968589d8	4098
Kojto	90:cb3d968589d8	4099	/*!
Kojto	90:cb3d968589d8	4100	* @name Register ENET_RACC, field SHIFT16[7] (RW)
Kojto	90:cb3d968589d8	4101	*
Kojto	90:cb3d968589d8	4102	* When this field is set, the actual frame data starts at bit 16 of the first
Kojto	90:cb3d968589d8	4103	* word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
Kojto	90:cb3d968589d8	4104	* This function only affects the FIFO storage and has no influence on the
Kojto	90:cb3d968589d8	4105	* statistics, which use the actual length of the frame received.
Kojto	90:cb3d968589d8	4106	*
Kojto	90:cb3d968589d8	4107	* Values:
Kojto	90:cb3d968589d8	4108	* - 0 - Disabled.
Kojto	90:cb3d968589d8	4109	* - 1 - Instructs the MAC to write two additional bytes in front of each frame
Kojto	90:cb3d968589d8	4110	* received into the RX FIFO.
Kojto	90:cb3d968589d8	4111	*/
Kojto	90:cb3d968589d8	4112	/@{/
Kojto	90:cb3d968589d8	4113	#define BP_ENET_RACC_SHIFT16 (7U) /!< Bit position for ENET_RACC_SHIFT16. /
Kojto	90:cb3d968589d8	4114	#define BM_ENET_RACC_SHIFT16 (0x00000080U) /!< Bit mask for ENET_RACC_SHIFT16. /
Kojto	90:cb3d968589d8	4115	#define BS_ENET_RACC_SHIFT16 (1U) /!< Bit field size in bits for ENET_RACC_SHIFT16. /
Kojto	90:cb3d968589d8	4116
Kojto	90:cb3d968589d8	4117	/! @brief Read current value of the ENET_RACC_SHIFT16 field. /
Kojto	90:cb3d968589d8	4118	#define BR_ENET_RACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16))
Kojto	90:cb3d968589d8	4119
Kojto	90:cb3d968589d8	4120	/! @brief Format value for bitfield ENET_RACC_SHIFT16. /
Kojto	90:cb3d968589d8	4121	#define BF_ENET_RACC_SHIFT16(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_SHIFT16) & BM_ENET_RACC_SHIFT16)
Kojto	90:cb3d968589d8	4122
Kojto	90:cb3d968589d8	4123	/! @brief Set the SHIFT16 field to a new value. /
Kojto	90:cb3d968589d8	4124	#define BW_ENET_RACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16) = (v))
Kojto	90:cb3d968589d8	4125	/@}/
Kojto	90:cb3d968589d8	4126
Kojto	90:cb3d968589d8	4127	/*******************************************************************************
Kojto	90:cb3d968589d8	4128	* HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
Kojto	90:cb3d968589d8	4129	******************************************************************************/
Kojto	90:cb3d968589d8	4130
Kojto	90:cb3d968589d8	4131	/*!
Kojto	90:cb3d968589d8	4132	* @brief HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
Kojto	90:cb3d968589d8	4133	*
Kojto	90:cb3d968589d8	4134	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4135	*/
Kojto	90:cb3d968589d8	4136	typedef union _hw_enet_rmon_t_packets
Kojto	90:cb3d968589d8	4137	{
Kojto	90:cb3d968589d8	4138	uint32_t U;
Kojto	90:cb3d968589d8	4139	struct _hw_enet_rmon_t_packets_bitfields
Kojto	90:cb3d968589d8	4140	{
Kojto	90:cb3d968589d8	4141	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4142	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4143	} B;
Kojto	90:cb3d968589d8	4144	} hw_enet_rmon_t_packets_t;
Kojto	90:cb3d968589d8	4145
Kojto	90:cb3d968589d8	4146	/*!
Kojto	90:cb3d968589d8	4147	* @name Constants and macros for entire ENET_RMON_T_PACKETS register
Kojto	90:cb3d968589d8	4148	*/
Kojto	90:cb3d968589d8	4149	/@{/
Kojto	90:cb3d968589d8	4150	#define HW_ENET_RMON_T_PACKETS_ADDR(x) ((x) + 0x204U)
Kojto	90:cb3d968589d8	4151
Kojto	90:cb3d968589d8	4152	#define HW_ENET_RMON_T_PACKETS(x) ((__I hw_enet_rmon_t_packets_t ) HW_ENET_RMON_T_PACKETS_ADDR(x))
Kojto	90:cb3d968589d8	4153	#define HW_ENET_RMON_T_PACKETS_RD(x) (HW_ENET_RMON_T_PACKETS(x).U)
Kojto	90:cb3d968589d8	4154	/@}/
Kojto	90:cb3d968589d8	4155
Kojto	90:cb3d968589d8	4156	/*
Kojto	90:cb3d968589d8	4157	* Constants & macros for individual ENET_RMON_T_PACKETS bitfields
Kojto	90:cb3d968589d8	4158	*/
Kojto	90:cb3d968589d8	4159
Kojto	90:cb3d968589d8	4160	/*!
Kojto	90:cb3d968589d8	4161	* @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4162	*/
Kojto	90:cb3d968589d8	4163	/@{/
Kojto	90:cb3d968589d8	4164	#define BP_ENET_RMON_T_PACKETS_TXPKTS (0U) /!< Bit position for ENET_RMON_T_PACKETS_TXPKTS. /
Kojto	90:cb3d968589d8	4165	#define BM_ENET_RMON_T_PACKETS_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_PACKETS_TXPKTS. /
Kojto	90:cb3d968589d8	4166	#define BS_ENET_RMON_T_PACKETS_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_PACKETS_TXPKTS. /
Kojto	90:cb3d968589d8	4167
Kojto	90:cb3d968589d8	4168	/! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field. /
Kojto	90:cb3d968589d8	4169	#define BR_ENET_RMON_T_PACKETS_TXPKTS(x) (HW_ENET_RMON_T_PACKETS(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4170	/@}/
Kojto	90:cb3d968589d8	4171
Kojto	90:cb3d968589d8	4172	/*******************************************************************************
Kojto	90:cb3d968589d8	4173	* HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
Kojto	90:cb3d968589d8	4174	******************************************************************************/
Kojto	90:cb3d968589d8	4175
Kojto	90:cb3d968589d8	4176	/*!
Kojto	90:cb3d968589d8	4177	* @brief HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	4178	*
Kojto	90:cb3d968589d8	4179	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4180	*
Kojto	90:cb3d968589d8	4181	* RMON Tx Broadcast Packets
Kojto	90:cb3d968589d8	4182	*/
Kojto	90:cb3d968589d8	4183	typedef union _hw_enet_rmon_t_bc_pkt
Kojto	90:cb3d968589d8	4184	{
Kojto	90:cb3d968589d8	4185	uint32_t U;
Kojto	90:cb3d968589d8	4186	struct _hw_enet_rmon_t_bc_pkt_bitfields
Kojto	90:cb3d968589d8	4187	{
Kojto	90:cb3d968589d8	4188	uint32_t TXPKTS : 16; /!< [15:0] Broadcast packets /
Kojto	90:cb3d968589d8	4189	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4190	} B;
Kojto	90:cb3d968589d8	4191	} hw_enet_rmon_t_bc_pkt_t;
Kojto	90:cb3d968589d8	4192
Kojto	90:cb3d968589d8	4193	/*!
Kojto	90:cb3d968589d8	4194	* @name Constants and macros for entire ENET_RMON_T_BC_PKT register
Kojto	90:cb3d968589d8	4195	*/
Kojto	90:cb3d968589d8	4196	/@{/
Kojto	90:cb3d968589d8	4197	#define HW_ENET_RMON_T_BC_PKT_ADDR(x) ((x) + 0x208U)
Kojto	90:cb3d968589d8	4198
Kojto	90:cb3d968589d8	4199	#define HW_ENET_RMON_T_BC_PKT(x) ((__I hw_enet_rmon_t_bc_pkt_t ) HW_ENET_RMON_T_BC_PKT_ADDR(x))
Kojto	90:cb3d968589d8	4200	#define HW_ENET_RMON_T_BC_PKT_RD(x) (HW_ENET_RMON_T_BC_PKT(x).U)
Kojto	90:cb3d968589d8	4201	/@}/
Kojto	90:cb3d968589d8	4202
Kojto	90:cb3d968589d8	4203	/*
Kojto	90:cb3d968589d8	4204	* Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
Kojto	90:cb3d968589d8	4205	*/
Kojto	90:cb3d968589d8	4206
Kojto	90:cb3d968589d8	4207	/*!
Kojto	90:cb3d968589d8	4208	* @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4209	*/
Kojto	90:cb3d968589d8	4210	/@{/
Kojto	90:cb3d968589d8	4211	#define BP_ENET_RMON_T_BC_PKT_TXPKTS (0U) /!< Bit position for ENET_RMON_T_BC_PKT_TXPKTS. /
Kojto	90:cb3d968589d8	4212	#define BM_ENET_RMON_T_BC_PKT_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_BC_PKT_TXPKTS. /
Kojto	90:cb3d968589d8	4213	#define BS_ENET_RMON_T_BC_PKT_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_BC_PKT_TXPKTS. /
Kojto	90:cb3d968589d8	4214
Kojto	90:cb3d968589d8	4215	/! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field. /
Kojto	90:cb3d968589d8	4216	#define BR_ENET_RMON_T_BC_PKT_TXPKTS(x) (HW_ENET_RMON_T_BC_PKT(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4217	/@}/
Kojto	90:cb3d968589d8	4218
Kojto	90:cb3d968589d8	4219	/*******************************************************************************
Kojto	90:cb3d968589d8	4220	* HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
Kojto	90:cb3d968589d8	4221	******************************************************************************/
Kojto	90:cb3d968589d8	4222
Kojto	90:cb3d968589d8	4223	/*!
Kojto	90:cb3d968589d8	4224	* @brief HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	4225	*
Kojto	90:cb3d968589d8	4226	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4227	*/
Kojto	90:cb3d968589d8	4228	typedef union _hw_enet_rmon_t_mc_pkt
Kojto	90:cb3d968589d8	4229	{
Kojto	90:cb3d968589d8	4230	uint32_t U;
Kojto	90:cb3d968589d8	4231	struct _hw_enet_rmon_t_mc_pkt_bitfields
Kojto	90:cb3d968589d8	4232	{
Kojto	90:cb3d968589d8	4233	uint32_t TXPKTS : 16; /!< [15:0] Multicast packets /
Kojto	90:cb3d968589d8	4234	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4235	} B;
Kojto	90:cb3d968589d8	4236	} hw_enet_rmon_t_mc_pkt_t;
Kojto	90:cb3d968589d8	4237
Kojto	90:cb3d968589d8	4238	/*!
Kojto	90:cb3d968589d8	4239	* @name Constants and macros for entire ENET_RMON_T_MC_PKT register
Kojto	90:cb3d968589d8	4240	*/
Kojto	90:cb3d968589d8	4241	/@{/
Kojto	90:cb3d968589d8	4242	#define HW_ENET_RMON_T_MC_PKT_ADDR(x) ((x) + 0x20CU)
Kojto	90:cb3d968589d8	4243
Kojto	90:cb3d968589d8	4244	#define HW_ENET_RMON_T_MC_PKT(x) ((__I hw_enet_rmon_t_mc_pkt_t ) HW_ENET_RMON_T_MC_PKT_ADDR(x))
Kojto	90:cb3d968589d8	4245	#define HW_ENET_RMON_T_MC_PKT_RD(x) (HW_ENET_RMON_T_MC_PKT(x).U)
Kojto	90:cb3d968589d8	4246	/@}/
Kojto	90:cb3d968589d8	4247
Kojto	90:cb3d968589d8	4248	/*
Kojto	90:cb3d968589d8	4249	* Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
Kojto	90:cb3d968589d8	4250	*/
Kojto	90:cb3d968589d8	4251
Kojto	90:cb3d968589d8	4252	/*!
Kojto	90:cb3d968589d8	4253	* @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4254	*/
Kojto	90:cb3d968589d8	4255	/@{/
Kojto	90:cb3d968589d8	4256	#define BP_ENET_RMON_T_MC_PKT_TXPKTS (0U) /!< Bit position for ENET_RMON_T_MC_PKT_TXPKTS. /
Kojto	90:cb3d968589d8	4257	#define BM_ENET_RMON_T_MC_PKT_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_MC_PKT_TXPKTS. /
Kojto	90:cb3d968589d8	4258	#define BS_ENET_RMON_T_MC_PKT_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_MC_PKT_TXPKTS. /
Kojto	90:cb3d968589d8	4259
Kojto	90:cb3d968589d8	4260	/! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field. /
Kojto	90:cb3d968589d8	4261	#define BR_ENET_RMON_T_MC_PKT_TXPKTS(x) (HW_ENET_RMON_T_MC_PKT(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4262	/@}/
Kojto	90:cb3d968589d8	4263
Kojto	90:cb3d968589d8	4264	/*******************************************************************************
Kojto	90:cb3d968589d8	4265	* HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
Kojto	90:cb3d968589d8	4266	******************************************************************************/
Kojto	90:cb3d968589d8	4267
Kojto	90:cb3d968589d8	4268	/*!
Kojto	90:cb3d968589d8	4269	* @brief HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
Kojto	90:cb3d968589d8	4270	*
Kojto	90:cb3d968589d8	4271	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4272	*/
Kojto	90:cb3d968589d8	4273	typedef union _hw_enet_rmon_t_crc_align
Kojto	90:cb3d968589d8	4274	{
Kojto	90:cb3d968589d8	4275	uint32_t U;
Kojto	90:cb3d968589d8	4276	struct _hw_enet_rmon_t_crc_align_bitfields
Kojto	90:cb3d968589d8	4277	{
Kojto	90:cb3d968589d8	4278	uint32_t TXPKTS : 16; /!< [15:0] Packets with CRC/align error /
Kojto	90:cb3d968589d8	4279	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4280	} B;
Kojto	90:cb3d968589d8	4281	} hw_enet_rmon_t_crc_align_t;
Kojto	90:cb3d968589d8	4282
Kojto	90:cb3d968589d8	4283	/*!
Kojto	90:cb3d968589d8	4284	* @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
Kojto	90:cb3d968589d8	4285	*/
Kojto	90:cb3d968589d8	4286	/@{/
Kojto	90:cb3d968589d8	4287	#define HW_ENET_RMON_T_CRC_ALIGN_ADDR(x) ((x) + 0x210U)
Kojto	90:cb3d968589d8	4288
Kojto	90:cb3d968589d8	4289	#define HW_ENET_RMON_T_CRC_ALIGN(x) ((__I hw_enet_rmon_t_crc_align_t ) HW_ENET_RMON_T_CRC_ALIGN_ADDR(x))
Kojto	90:cb3d968589d8	4290	#define HW_ENET_RMON_T_CRC_ALIGN_RD(x) (HW_ENET_RMON_T_CRC_ALIGN(x).U)
Kojto	90:cb3d968589d8	4291	/@}/
Kojto	90:cb3d968589d8	4292
Kojto	90:cb3d968589d8	4293	/*
Kojto	90:cb3d968589d8	4294	* Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
Kojto	90:cb3d968589d8	4295	*/
Kojto	90:cb3d968589d8	4296
Kojto	90:cb3d968589d8	4297	/*!
Kojto	90:cb3d968589d8	4298	* @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4299	*/
Kojto	90:cb3d968589d8	4300	/@{/
Kojto	90:cb3d968589d8	4301	#define BP_ENET_RMON_T_CRC_ALIGN_TXPKTS (0U) /!< Bit position for ENET_RMON_T_CRC_ALIGN_TXPKTS. /
Kojto	90:cb3d968589d8	4302	#define BM_ENET_RMON_T_CRC_ALIGN_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_CRC_ALIGN_TXPKTS. /
Kojto	90:cb3d968589d8	4303	#define BS_ENET_RMON_T_CRC_ALIGN_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_CRC_ALIGN_TXPKTS. /
Kojto	90:cb3d968589d8	4304
Kojto	90:cb3d968589d8	4305	/! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field. /
Kojto	90:cb3d968589d8	4306	#define BR_ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (HW_ENET_RMON_T_CRC_ALIGN(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4307	/@}/
Kojto	90:cb3d968589d8	4308
Kojto	90:cb3d968589d8	4309	/*******************************************************************************
Kojto	90:cb3d968589d8	4310	* HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
Kojto	90:cb3d968589d8	4311	******************************************************************************/
Kojto	90:cb3d968589d8	4312
Kojto	90:cb3d968589d8	4313	/*!
Kojto	90:cb3d968589d8	4314	* @brief HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
Kojto	90:cb3d968589d8	4315	*
Kojto	90:cb3d968589d8	4316	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4317	*/
Kojto	90:cb3d968589d8	4318	typedef union _hw_enet_rmon_t_undersize
Kojto	90:cb3d968589d8	4319	{
Kojto	90:cb3d968589d8	4320	uint32_t U;
Kojto	90:cb3d968589d8	4321	struct _hw_enet_rmon_t_undersize_bitfields
Kojto	90:cb3d968589d8	4322	{
Kojto	90:cb3d968589d8	4323	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4324	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4325	} B;
Kojto	90:cb3d968589d8	4326	} hw_enet_rmon_t_undersize_t;
Kojto	90:cb3d968589d8	4327
Kojto	90:cb3d968589d8	4328	/*!
Kojto	90:cb3d968589d8	4329	* @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
Kojto	90:cb3d968589d8	4330	*/
Kojto	90:cb3d968589d8	4331	/@{/
Kojto	90:cb3d968589d8	4332	#define HW_ENET_RMON_T_UNDERSIZE_ADDR(x) ((x) + 0x214U)
Kojto	90:cb3d968589d8	4333
Kojto	90:cb3d968589d8	4334	#define HW_ENET_RMON_T_UNDERSIZE(x) ((__I hw_enet_rmon_t_undersize_t ) HW_ENET_RMON_T_UNDERSIZE_ADDR(x))
Kojto	90:cb3d968589d8	4335	#define HW_ENET_RMON_T_UNDERSIZE_RD(x) (HW_ENET_RMON_T_UNDERSIZE(x).U)
Kojto	90:cb3d968589d8	4336	/@}/
Kojto	90:cb3d968589d8	4337
Kojto	90:cb3d968589d8	4338	/*
Kojto	90:cb3d968589d8	4339	* Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
Kojto	90:cb3d968589d8	4340	*/
Kojto	90:cb3d968589d8	4341
Kojto	90:cb3d968589d8	4342	/*!
Kojto	90:cb3d968589d8	4343	* @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4344	*/
Kojto	90:cb3d968589d8	4345	/@{/
Kojto	90:cb3d968589d8	4346	#define BP_ENET_RMON_T_UNDERSIZE_TXPKTS (0U) /!< Bit position for ENET_RMON_T_UNDERSIZE_TXPKTS. /
Kojto	90:cb3d968589d8	4347	#define BM_ENET_RMON_T_UNDERSIZE_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_UNDERSIZE_TXPKTS. /
Kojto	90:cb3d968589d8	4348	#define BS_ENET_RMON_T_UNDERSIZE_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_UNDERSIZE_TXPKTS. /
Kojto	90:cb3d968589d8	4349
Kojto	90:cb3d968589d8	4350	/! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field. /
Kojto	90:cb3d968589d8	4351	#define BR_ENET_RMON_T_UNDERSIZE_TXPKTS(x) (HW_ENET_RMON_T_UNDERSIZE(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4352	/@}/
Kojto	90:cb3d968589d8	4353
Kojto	90:cb3d968589d8	4354	/*******************************************************************************
Kojto	90:cb3d968589d8	4355	* HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
Kojto	90:cb3d968589d8	4356	******************************************************************************/
Kojto	90:cb3d968589d8	4357
Kojto	90:cb3d968589d8	4358	/*!
Kojto	90:cb3d968589d8	4359	* @brief HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
Kojto	90:cb3d968589d8	4360	*
Kojto	90:cb3d968589d8	4361	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4362	*/
Kojto	90:cb3d968589d8	4363	typedef union _hw_enet_rmon_t_oversize
Kojto	90:cb3d968589d8	4364	{
Kojto	90:cb3d968589d8	4365	uint32_t U;
Kojto	90:cb3d968589d8	4366	struct _hw_enet_rmon_t_oversize_bitfields
Kojto	90:cb3d968589d8	4367	{
Kojto	90:cb3d968589d8	4368	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4369	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4370	} B;
Kojto	90:cb3d968589d8	4371	} hw_enet_rmon_t_oversize_t;
Kojto	90:cb3d968589d8	4372
Kojto	90:cb3d968589d8	4373	/*!
Kojto	90:cb3d968589d8	4374	* @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
Kojto	90:cb3d968589d8	4375	*/
Kojto	90:cb3d968589d8	4376	/@{/
Kojto	90:cb3d968589d8	4377	#define HW_ENET_RMON_T_OVERSIZE_ADDR(x) ((x) + 0x218U)
Kojto	90:cb3d968589d8	4378
Kojto	90:cb3d968589d8	4379	#define HW_ENET_RMON_T_OVERSIZE(x) ((__I hw_enet_rmon_t_oversize_t ) HW_ENET_RMON_T_OVERSIZE_ADDR(x))
Kojto	90:cb3d968589d8	4380	#define HW_ENET_RMON_T_OVERSIZE_RD(x) (HW_ENET_RMON_T_OVERSIZE(x).U)
Kojto	90:cb3d968589d8	4381	/@}/
Kojto	90:cb3d968589d8	4382
Kojto	90:cb3d968589d8	4383	/*
Kojto	90:cb3d968589d8	4384	* Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
Kojto	90:cb3d968589d8	4385	*/
Kojto	90:cb3d968589d8	4386
Kojto	90:cb3d968589d8	4387	/*!
Kojto	90:cb3d968589d8	4388	* @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4389	*/
Kojto	90:cb3d968589d8	4390	/@{/
Kojto	90:cb3d968589d8	4391	#define BP_ENET_RMON_T_OVERSIZE_TXPKTS (0U) /!< Bit position for ENET_RMON_T_OVERSIZE_TXPKTS. /
Kojto	90:cb3d968589d8	4392	#define BM_ENET_RMON_T_OVERSIZE_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_OVERSIZE_TXPKTS. /
Kojto	90:cb3d968589d8	4393	#define BS_ENET_RMON_T_OVERSIZE_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_OVERSIZE_TXPKTS. /
Kojto	90:cb3d968589d8	4394
Kojto	90:cb3d968589d8	4395	/! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field. /
Kojto	90:cb3d968589d8	4396	#define BR_ENET_RMON_T_OVERSIZE_TXPKTS(x) (HW_ENET_RMON_T_OVERSIZE(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4397	/@}/
Kojto	90:cb3d968589d8	4398
Kojto	90:cb3d968589d8	4399	/*******************************************************************************
Kojto	90:cb3d968589d8	4400	* HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
Kojto	90:cb3d968589d8	4401	******************************************************************************/
Kojto	90:cb3d968589d8	4402
Kojto	90:cb3d968589d8	4403	/*!
Kojto	90:cb3d968589d8	4404	* @brief HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
Kojto	90:cb3d968589d8	4405	*
Kojto	90:cb3d968589d8	4406	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4407	*
Kojto	90:cb3d968589d8	4408	* .
Kojto	90:cb3d968589d8	4409	*/
Kojto	90:cb3d968589d8	4410	typedef union _hw_enet_rmon_t_frag
Kojto	90:cb3d968589d8	4411	{
Kojto	90:cb3d968589d8	4412	uint32_t U;
Kojto	90:cb3d968589d8	4413	struct _hw_enet_rmon_t_frag_bitfields
Kojto	90:cb3d968589d8	4414	{
Kojto	90:cb3d968589d8	4415	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4416	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4417	} B;
Kojto	90:cb3d968589d8	4418	} hw_enet_rmon_t_frag_t;
Kojto	90:cb3d968589d8	4419
Kojto	90:cb3d968589d8	4420	/*!
Kojto	90:cb3d968589d8	4421	* @name Constants and macros for entire ENET_RMON_T_FRAG register
Kojto	90:cb3d968589d8	4422	*/
Kojto	90:cb3d968589d8	4423	/@{/
Kojto	90:cb3d968589d8	4424	#define HW_ENET_RMON_T_FRAG_ADDR(x) ((x) + 0x21CU)
Kojto	90:cb3d968589d8	4425
Kojto	90:cb3d968589d8	4426	#define HW_ENET_RMON_T_FRAG(x) ((__I hw_enet_rmon_t_frag_t ) HW_ENET_RMON_T_FRAG_ADDR(x))
Kojto	90:cb3d968589d8	4427	#define HW_ENET_RMON_T_FRAG_RD(x) (HW_ENET_RMON_T_FRAG(x).U)
Kojto	90:cb3d968589d8	4428	/@}/
Kojto	90:cb3d968589d8	4429
Kojto	90:cb3d968589d8	4430	/*
Kojto	90:cb3d968589d8	4431	* Constants & macros for individual ENET_RMON_T_FRAG bitfields
Kojto	90:cb3d968589d8	4432	*/
Kojto	90:cb3d968589d8	4433
Kojto	90:cb3d968589d8	4434	/*!
Kojto	90:cb3d968589d8	4435	* @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4436	*/
Kojto	90:cb3d968589d8	4437	/@{/
Kojto	90:cb3d968589d8	4438	#define BP_ENET_RMON_T_FRAG_TXPKTS (0U) /!< Bit position for ENET_RMON_T_FRAG_TXPKTS. /
Kojto	90:cb3d968589d8	4439	#define BM_ENET_RMON_T_FRAG_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_FRAG_TXPKTS. /
Kojto	90:cb3d968589d8	4440	#define BS_ENET_RMON_T_FRAG_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_FRAG_TXPKTS. /
Kojto	90:cb3d968589d8	4441
Kojto	90:cb3d968589d8	4442	/! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field. /
Kojto	90:cb3d968589d8	4443	#define BR_ENET_RMON_T_FRAG_TXPKTS(x) (HW_ENET_RMON_T_FRAG(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4444	/@}/
Kojto	90:cb3d968589d8	4445
Kojto	90:cb3d968589d8	4446	/*******************************************************************************
Kojto	90:cb3d968589d8	4447	* HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
Kojto	90:cb3d968589d8	4448	******************************************************************************/
Kojto	90:cb3d968589d8	4449
Kojto	90:cb3d968589d8	4450	/*!
Kojto	90:cb3d968589d8	4451	* @brief HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
Kojto	90:cb3d968589d8	4452	*
Kojto	90:cb3d968589d8	4453	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4454	*/
Kojto	90:cb3d968589d8	4455	typedef union _hw_enet_rmon_t_jab
Kojto	90:cb3d968589d8	4456	{
Kojto	90:cb3d968589d8	4457	uint32_t U;
Kojto	90:cb3d968589d8	4458	struct _hw_enet_rmon_t_jab_bitfields
Kojto	90:cb3d968589d8	4459	{
Kojto	90:cb3d968589d8	4460	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4461	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4462	} B;
Kojto	90:cb3d968589d8	4463	} hw_enet_rmon_t_jab_t;
Kojto	90:cb3d968589d8	4464
Kojto	90:cb3d968589d8	4465	/*!
Kojto	90:cb3d968589d8	4466	* @name Constants and macros for entire ENET_RMON_T_JAB register
Kojto	90:cb3d968589d8	4467	*/
Kojto	90:cb3d968589d8	4468	/@{/
Kojto	90:cb3d968589d8	4469	#define HW_ENET_RMON_T_JAB_ADDR(x) ((x) + 0x220U)
Kojto	90:cb3d968589d8	4470
Kojto	90:cb3d968589d8	4471	#define HW_ENET_RMON_T_JAB(x) ((__I hw_enet_rmon_t_jab_t ) HW_ENET_RMON_T_JAB_ADDR(x))
Kojto	90:cb3d968589d8	4472	#define HW_ENET_RMON_T_JAB_RD(x) (HW_ENET_RMON_T_JAB(x).U)
Kojto	90:cb3d968589d8	4473	/@}/
Kojto	90:cb3d968589d8	4474
Kojto	90:cb3d968589d8	4475	/*
Kojto	90:cb3d968589d8	4476	* Constants & macros for individual ENET_RMON_T_JAB bitfields
Kojto	90:cb3d968589d8	4477	*/
Kojto	90:cb3d968589d8	4478
Kojto	90:cb3d968589d8	4479	/*!
Kojto	90:cb3d968589d8	4480	* @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4481	*/
Kojto	90:cb3d968589d8	4482	/@{/
Kojto	90:cb3d968589d8	4483	#define BP_ENET_RMON_T_JAB_TXPKTS (0U) /!< Bit position for ENET_RMON_T_JAB_TXPKTS. /
Kojto	90:cb3d968589d8	4484	#define BM_ENET_RMON_T_JAB_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_JAB_TXPKTS. /
Kojto	90:cb3d968589d8	4485	#define BS_ENET_RMON_T_JAB_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_JAB_TXPKTS. /
Kojto	90:cb3d968589d8	4486
Kojto	90:cb3d968589d8	4487	/! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field. /
Kojto	90:cb3d968589d8	4488	#define BR_ENET_RMON_T_JAB_TXPKTS(x) (HW_ENET_RMON_T_JAB(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4489	/@}/
Kojto	90:cb3d968589d8	4490
Kojto	90:cb3d968589d8	4491	/*******************************************************************************
Kojto	90:cb3d968589d8	4492	* HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
Kojto	90:cb3d968589d8	4493	******************************************************************************/
Kojto	90:cb3d968589d8	4494
Kojto	90:cb3d968589d8	4495	/*!
Kojto	90:cb3d968589d8	4496	* @brief HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
Kojto	90:cb3d968589d8	4497	*
Kojto	90:cb3d968589d8	4498	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4499	*/
Kojto	90:cb3d968589d8	4500	typedef union _hw_enet_rmon_t_col
Kojto	90:cb3d968589d8	4501	{
Kojto	90:cb3d968589d8	4502	uint32_t U;
Kojto	90:cb3d968589d8	4503	struct _hw_enet_rmon_t_col_bitfields
Kojto	90:cb3d968589d8	4504	{
Kojto	90:cb3d968589d8	4505	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4506	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4507	} B;
Kojto	90:cb3d968589d8	4508	} hw_enet_rmon_t_col_t;
Kojto	90:cb3d968589d8	4509
Kojto	90:cb3d968589d8	4510	/*!
Kojto	90:cb3d968589d8	4511	* @name Constants and macros for entire ENET_RMON_T_COL register
Kojto	90:cb3d968589d8	4512	*/
Kojto	90:cb3d968589d8	4513	/@{/
Kojto	90:cb3d968589d8	4514	#define HW_ENET_RMON_T_COL_ADDR(x) ((x) + 0x224U)
Kojto	90:cb3d968589d8	4515
Kojto	90:cb3d968589d8	4516	#define HW_ENET_RMON_T_COL(x) ((__I hw_enet_rmon_t_col_t ) HW_ENET_RMON_T_COL_ADDR(x))
Kojto	90:cb3d968589d8	4517	#define HW_ENET_RMON_T_COL_RD(x) (HW_ENET_RMON_T_COL(x).U)
Kojto	90:cb3d968589d8	4518	/@}/
Kojto	90:cb3d968589d8	4519
Kojto	90:cb3d968589d8	4520	/*
Kojto	90:cb3d968589d8	4521	* Constants & macros for individual ENET_RMON_T_COL bitfields
Kojto	90:cb3d968589d8	4522	*/
Kojto	90:cb3d968589d8	4523
Kojto	90:cb3d968589d8	4524	/*!
Kojto	90:cb3d968589d8	4525	* @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4526	*/
Kojto	90:cb3d968589d8	4527	/@{/
Kojto	90:cb3d968589d8	4528	#define BP_ENET_RMON_T_COL_TXPKTS (0U) /!< Bit position for ENET_RMON_T_COL_TXPKTS. /
Kojto	90:cb3d968589d8	4529	#define BM_ENET_RMON_T_COL_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_COL_TXPKTS. /
Kojto	90:cb3d968589d8	4530	#define BS_ENET_RMON_T_COL_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_COL_TXPKTS. /
Kojto	90:cb3d968589d8	4531
Kojto	90:cb3d968589d8	4532	/! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field. /
Kojto	90:cb3d968589d8	4533	#define BR_ENET_RMON_T_COL_TXPKTS(x) (HW_ENET_RMON_T_COL(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4534	/@}/
Kojto	90:cb3d968589d8	4535
Kojto	90:cb3d968589d8	4536	/*******************************************************************************
Kojto	90:cb3d968589d8	4537	* HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	4538	******************************************************************************/
Kojto	90:cb3d968589d8	4539
Kojto	90:cb3d968589d8	4540	/*!
Kojto	90:cb3d968589d8	4541	* @brief HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	4542	*
Kojto	90:cb3d968589d8	4543	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4544	*
Kojto	90:cb3d968589d8	4545	* .
Kojto	90:cb3d968589d8	4546	*/
Kojto	90:cb3d968589d8	4547	typedef union _hw_enet_rmon_t_p64
Kojto	90:cb3d968589d8	4548	{
Kojto	90:cb3d968589d8	4549	uint32_t U;
Kojto	90:cb3d968589d8	4550	struct _hw_enet_rmon_t_p64_bitfields
Kojto	90:cb3d968589d8	4551	{
Kojto	90:cb3d968589d8	4552	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4553	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4554	} B;
Kojto	90:cb3d968589d8	4555	} hw_enet_rmon_t_p64_t;
Kojto	90:cb3d968589d8	4556
Kojto	90:cb3d968589d8	4557	/*!
Kojto	90:cb3d968589d8	4558	* @name Constants and macros for entire ENET_RMON_T_P64 register
Kojto	90:cb3d968589d8	4559	*/
Kojto	90:cb3d968589d8	4560	/@{/
Kojto	90:cb3d968589d8	4561	#define HW_ENET_RMON_T_P64_ADDR(x) ((x) + 0x228U)
Kojto	90:cb3d968589d8	4562
Kojto	90:cb3d968589d8	4563	#define HW_ENET_RMON_T_P64(x) ((__I hw_enet_rmon_t_p64_t ) HW_ENET_RMON_T_P64_ADDR(x))
Kojto	90:cb3d968589d8	4564	#define HW_ENET_RMON_T_P64_RD(x) (HW_ENET_RMON_T_P64(x).U)
Kojto	90:cb3d968589d8	4565	/@}/
Kojto	90:cb3d968589d8	4566
Kojto	90:cb3d968589d8	4567	/*
Kojto	90:cb3d968589d8	4568	* Constants & macros for individual ENET_RMON_T_P64 bitfields
Kojto	90:cb3d968589d8	4569	*/
Kojto	90:cb3d968589d8	4570
Kojto	90:cb3d968589d8	4571	/*!
Kojto	90:cb3d968589d8	4572	* @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4573	*/
Kojto	90:cb3d968589d8	4574	/@{/
Kojto	90:cb3d968589d8	4575	#define BP_ENET_RMON_T_P64_TXPKTS (0U) /!< Bit position for ENET_RMON_T_P64_TXPKTS. /
Kojto	90:cb3d968589d8	4576	#define BM_ENET_RMON_T_P64_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_P64_TXPKTS. /
Kojto	90:cb3d968589d8	4577	#define BS_ENET_RMON_T_P64_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_P64_TXPKTS. /
Kojto	90:cb3d968589d8	4578
Kojto	90:cb3d968589d8	4579	/! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field. /
Kojto	90:cb3d968589d8	4580	#define BR_ENET_RMON_T_P64_TXPKTS(x) (HW_ENET_RMON_T_P64(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4581	/@}/
Kojto	90:cb3d968589d8	4582
Kojto	90:cb3d968589d8	4583	/*******************************************************************************
Kojto	90:cb3d968589d8	4584	* HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
Kojto	90:cb3d968589d8	4585	******************************************************************************/
Kojto	90:cb3d968589d8	4586
Kojto	90:cb3d968589d8	4587	/*!
Kojto	90:cb3d968589d8	4588	* @brief HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	4589	*
Kojto	90:cb3d968589d8	4590	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4591	*/
Kojto	90:cb3d968589d8	4592	typedef union _hw_enet_rmon_t_p65to127
Kojto	90:cb3d968589d8	4593	{
Kojto	90:cb3d968589d8	4594	uint32_t U;
Kojto	90:cb3d968589d8	4595	struct _hw_enet_rmon_t_p65to127_bitfields
Kojto	90:cb3d968589d8	4596	{
Kojto	90:cb3d968589d8	4597	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4598	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4599	} B;
Kojto	90:cb3d968589d8	4600	} hw_enet_rmon_t_p65to127_t;
Kojto	90:cb3d968589d8	4601
Kojto	90:cb3d968589d8	4602	/*!
Kojto	90:cb3d968589d8	4603	* @name Constants and macros for entire ENET_RMON_T_P65TO127 register
Kojto	90:cb3d968589d8	4604	*/
Kojto	90:cb3d968589d8	4605	/@{/
Kojto	90:cb3d968589d8	4606	#define HW_ENET_RMON_T_P65TO127_ADDR(x) ((x) + 0x22CU)
Kojto	90:cb3d968589d8	4607
Kojto	90:cb3d968589d8	4608	#define HW_ENET_RMON_T_P65TO127(x) ((__I hw_enet_rmon_t_p65to127_t ) HW_ENET_RMON_T_P65TO127_ADDR(x))
Kojto	90:cb3d968589d8	4609	#define HW_ENET_RMON_T_P65TO127_RD(x) (HW_ENET_RMON_T_P65TO127(x).U)
Kojto	90:cb3d968589d8	4610	/@}/
Kojto	90:cb3d968589d8	4611
Kojto	90:cb3d968589d8	4612	/*
Kojto	90:cb3d968589d8	4613	* Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
Kojto	90:cb3d968589d8	4614	*/
Kojto	90:cb3d968589d8	4615
Kojto	90:cb3d968589d8	4616	/*!
Kojto	90:cb3d968589d8	4617	* @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4618	*/
Kojto	90:cb3d968589d8	4619	/@{/
Kojto	90:cb3d968589d8	4620	#define BP_ENET_RMON_T_P65TO127_TXPKTS (0U) /!< Bit position for ENET_RMON_T_P65TO127_TXPKTS. /
Kojto	90:cb3d968589d8	4621	#define BM_ENET_RMON_T_P65TO127_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_P65TO127_TXPKTS. /
Kojto	90:cb3d968589d8	4622	#define BS_ENET_RMON_T_P65TO127_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_P65TO127_TXPKTS. /
Kojto	90:cb3d968589d8	4623
Kojto	90:cb3d968589d8	4624	/! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field. /
Kojto	90:cb3d968589d8	4625	#define BR_ENET_RMON_T_P65TO127_TXPKTS(x) (HW_ENET_RMON_T_P65TO127(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4626	/@}/
Kojto	90:cb3d968589d8	4627
Kojto	90:cb3d968589d8	4628	/*******************************************************************************
Kojto	90:cb3d968589d8	4629	* HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
Kojto	90:cb3d968589d8	4630	******************************************************************************/
Kojto	90:cb3d968589d8	4631
Kojto	90:cb3d968589d8	4632	/*!
Kojto	90:cb3d968589d8	4633	* @brief HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	4634	*
Kojto	90:cb3d968589d8	4635	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4636	*/
Kojto	90:cb3d968589d8	4637	typedef union _hw_enet_rmon_t_p128to255
Kojto	90:cb3d968589d8	4638	{
Kojto	90:cb3d968589d8	4639	uint32_t U;
Kojto	90:cb3d968589d8	4640	struct _hw_enet_rmon_t_p128to255_bitfields
Kojto	90:cb3d968589d8	4641	{
Kojto	90:cb3d968589d8	4642	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4643	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4644	} B;
Kojto	90:cb3d968589d8	4645	} hw_enet_rmon_t_p128to255_t;
Kojto	90:cb3d968589d8	4646
Kojto	90:cb3d968589d8	4647	/*!
Kojto	90:cb3d968589d8	4648	* @name Constants and macros for entire ENET_RMON_T_P128TO255 register
Kojto	90:cb3d968589d8	4649	*/
Kojto	90:cb3d968589d8	4650	/@{/
Kojto	90:cb3d968589d8	4651	#define HW_ENET_RMON_T_P128TO255_ADDR(x) ((x) + 0x230U)
Kojto	90:cb3d968589d8	4652
Kojto	90:cb3d968589d8	4653	#define HW_ENET_RMON_T_P128TO255(x) ((__I hw_enet_rmon_t_p128to255_t ) HW_ENET_RMON_T_P128TO255_ADDR(x))
Kojto	90:cb3d968589d8	4654	#define HW_ENET_RMON_T_P128TO255_RD(x) (HW_ENET_RMON_T_P128TO255(x).U)
Kojto	90:cb3d968589d8	4655	/@}/
Kojto	90:cb3d968589d8	4656
Kojto	90:cb3d968589d8	4657	/*
Kojto	90:cb3d968589d8	4658	* Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
Kojto	90:cb3d968589d8	4659	*/
Kojto	90:cb3d968589d8	4660
Kojto	90:cb3d968589d8	4661	/*!
Kojto	90:cb3d968589d8	4662	* @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4663	*/
Kojto	90:cb3d968589d8	4664	/@{/
Kojto	90:cb3d968589d8	4665	#define BP_ENET_RMON_T_P128TO255_TXPKTS (0U) /!< Bit position for ENET_RMON_T_P128TO255_TXPKTS. /
Kojto	90:cb3d968589d8	4666	#define BM_ENET_RMON_T_P128TO255_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_P128TO255_TXPKTS. /
Kojto	90:cb3d968589d8	4667	#define BS_ENET_RMON_T_P128TO255_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_P128TO255_TXPKTS. /
Kojto	90:cb3d968589d8	4668
Kojto	90:cb3d968589d8	4669	/! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field. /
Kojto	90:cb3d968589d8	4670	#define BR_ENET_RMON_T_P128TO255_TXPKTS(x) (HW_ENET_RMON_T_P128TO255(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4671	/@}/
Kojto	90:cb3d968589d8	4672
Kojto	90:cb3d968589d8	4673	/*******************************************************************************
Kojto	90:cb3d968589d8	4674	* HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
Kojto	90:cb3d968589d8	4675	******************************************************************************/
Kojto	90:cb3d968589d8	4676
Kojto	90:cb3d968589d8	4677	/*!
Kojto	90:cb3d968589d8	4678	* @brief HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	4679	*
Kojto	90:cb3d968589d8	4680	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4681	*/
Kojto	90:cb3d968589d8	4682	typedef union _hw_enet_rmon_t_p256to511
Kojto	90:cb3d968589d8	4683	{
Kojto	90:cb3d968589d8	4684	uint32_t U;
Kojto	90:cb3d968589d8	4685	struct _hw_enet_rmon_t_p256to511_bitfields
Kojto	90:cb3d968589d8	4686	{
Kojto	90:cb3d968589d8	4687	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4688	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4689	} B;
Kojto	90:cb3d968589d8	4690	} hw_enet_rmon_t_p256to511_t;
Kojto	90:cb3d968589d8	4691
Kojto	90:cb3d968589d8	4692	/*!
Kojto	90:cb3d968589d8	4693	* @name Constants and macros for entire ENET_RMON_T_P256TO511 register
Kojto	90:cb3d968589d8	4694	*/
Kojto	90:cb3d968589d8	4695	/@{/
Kojto	90:cb3d968589d8	4696	#define HW_ENET_RMON_T_P256TO511_ADDR(x) ((x) + 0x234U)
Kojto	90:cb3d968589d8	4697
Kojto	90:cb3d968589d8	4698	#define HW_ENET_RMON_T_P256TO511(x) ((__I hw_enet_rmon_t_p256to511_t ) HW_ENET_RMON_T_P256TO511_ADDR(x))
Kojto	90:cb3d968589d8	4699	#define HW_ENET_RMON_T_P256TO511_RD(x) (HW_ENET_RMON_T_P256TO511(x).U)
Kojto	90:cb3d968589d8	4700	/@}/
Kojto	90:cb3d968589d8	4701
Kojto	90:cb3d968589d8	4702	/*
Kojto	90:cb3d968589d8	4703	* Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
Kojto	90:cb3d968589d8	4704	*/
Kojto	90:cb3d968589d8	4705
Kojto	90:cb3d968589d8	4706	/*!
Kojto	90:cb3d968589d8	4707	* @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4708	*/
Kojto	90:cb3d968589d8	4709	/@{/
Kojto	90:cb3d968589d8	4710	#define BP_ENET_RMON_T_P256TO511_TXPKTS (0U) /!< Bit position for ENET_RMON_T_P256TO511_TXPKTS. /
Kojto	90:cb3d968589d8	4711	#define BM_ENET_RMON_T_P256TO511_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_P256TO511_TXPKTS. /
Kojto	90:cb3d968589d8	4712	#define BS_ENET_RMON_T_P256TO511_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_P256TO511_TXPKTS. /
Kojto	90:cb3d968589d8	4713
Kojto	90:cb3d968589d8	4714	/! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field. /
Kojto	90:cb3d968589d8	4715	#define BR_ENET_RMON_T_P256TO511_TXPKTS(x) (HW_ENET_RMON_T_P256TO511(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4716	/@}/
Kojto	90:cb3d968589d8	4717
Kojto	90:cb3d968589d8	4718	/*******************************************************************************
Kojto	90:cb3d968589d8	4719	* HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
Kojto	90:cb3d968589d8	4720	******************************************************************************/
Kojto	90:cb3d968589d8	4721
Kojto	90:cb3d968589d8	4722	/*!
Kojto	90:cb3d968589d8	4723	* @brief HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	4724	*
Kojto	90:cb3d968589d8	4725	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4726	*
Kojto	90:cb3d968589d8	4727	* .
Kojto	90:cb3d968589d8	4728	*/
Kojto	90:cb3d968589d8	4729	typedef union _hw_enet_rmon_t_p512to1023
Kojto	90:cb3d968589d8	4730	{
Kojto	90:cb3d968589d8	4731	uint32_t U;
Kojto	90:cb3d968589d8	4732	struct _hw_enet_rmon_t_p512to1023_bitfields
Kojto	90:cb3d968589d8	4733	{
Kojto	90:cb3d968589d8	4734	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4735	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4736	} B;
Kojto	90:cb3d968589d8	4737	} hw_enet_rmon_t_p512to1023_t;
Kojto	90:cb3d968589d8	4738
Kojto	90:cb3d968589d8	4739	/*!
Kojto	90:cb3d968589d8	4740	* @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
Kojto	90:cb3d968589d8	4741	*/
Kojto	90:cb3d968589d8	4742	/@{/
Kojto	90:cb3d968589d8	4743	#define HW_ENET_RMON_T_P512TO1023_ADDR(x) ((x) + 0x238U)
Kojto	90:cb3d968589d8	4744
Kojto	90:cb3d968589d8	4745	#define HW_ENET_RMON_T_P512TO1023(x) ((__I hw_enet_rmon_t_p512to1023_t ) HW_ENET_RMON_T_P512TO1023_ADDR(x))
Kojto	90:cb3d968589d8	4746	#define HW_ENET_RMON_T_P512TO1023_RD(x) (HW_ENET_RMON_T_P512TO1023(x).U)
Kojto	90:cb3d968589d8	4747	/@}/
Kojto	90:cb3d968589d8	4748
Kojto	90:cb3d968589d8	4749	/*
Kojto	90:cb3d968589d8	4750	* Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
Kojto	90:cb3d968589d8	4751	*/
Kojto	90:cb3d968589d8	4752
Kojto	90:cb3d968589d8	4753	/*!
Kojto	90:cb3d968589d8	4754	* @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4755	*/
Kojto	90:cb3d968589d8	4756	/@{/
Kojto	90:cb3d968589d8	4757	#define BP_ENET_RMON_T_P512TO1023_TXPKTS (0U) /!< Bit position for ENET_RMON_T_P512TO1023_TXPKTS. /
Kojto	90:cb3d968589d8	4758	#define BM_ENET_RMON_T_P512TO1023_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_P512TO1023_TXPKTS. /
Kojto	90:cb3d968589d8	4759	#define BS_ENET_RMON_T_P512TO1023_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_P512TO1023_TXPKTS. /
Kojto	90:cb3d968589d8	4760
Kojto	90:cb3d968589d8	4761	/! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field. /
Kojto	90:cb3d968589d8	4762	#define BR_ENET_RMON_T_P512TO1023_TXPKTS(x) (HW_ENET_RMON_T_P512TO1023(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4763	/@}/
Kojto	90:cb3d968589d8	4764
Kojto	90:cb3d968589d8	4765	/*******************************************************************************
Kojto	90:cb3d968589d8	4766	* HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
Kojto	90:cb3d968589d8	4767	******************************************************************************/
Kojto	90:cb3d968589d8	4768
Kojto	90:cb3d968589d8	4769	/*!
Kojto	90:cb3d968589d8	4770	* @brief HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	4771	*
Kojto	90:cb3d968589d8	4772	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4773	*/
Kojto	90:cb3d968589d8	4774	typedef union _hw_enet_rmon_t_p1024to2047
Kojto	90:cb3d968589d8	4775	{
Kojto	90:cb3d968589d8	4776	uint32_t U;
Kojto	90:cb3d968589d8	4777	struct _hw_enet_rmon_t_p1024to2047_bitfields
Kojto	90:cb3d968589d8	4778	{
Kojto	90:cb3d968589d8	4779	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4780	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4781	} B;
Kojto	90:cb3d968589d8	4782	} hw_enet_rmon_t_p1024to2047_t;
Kojto	90:cb3d968589d8	4783
Kojto	90:cb3d968589d8	4784	/*!
Kojto	90:cb3d968589d8	4785	* @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
Kojto	90:cb3d968589d8	4786	*/
Kojto	90:cb3d968589d8	4787	/@{/
Kojto	90:cb3d968589d8	4788	#define HW_ENET_RMON_T_P1024TO2047_ADDR(x) ((x) + 0x23CU)
Kojto	90:cb3d968589d8	4789
Kojto	90:cb3d968589d8	4790	#define HW_ENET_RMON_T_P1024TO2047(x) ((__I hw_enet_rmon_t_p1024to2047_t ) HW_ENET_RMON_T_P1024TO2047_ADDR(x))
Kojto	90:cb3d968589d8	4791	#define HW_ENET_RMON_T_P1024TO2047_RD(x) (HW_ENET_RMON_T_P1024TO2047(x).U)
Kojto	90:cb3d968589d8	4792	/@}/
Kojto	90:cb3d968589d8	4793
Kojto	90:cb3d968589d8	4794	/*
Kojto	90:cb3d968589d8	4795	* Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
Kojto	90:cb3d968589d8	4796	*/
Kojto	90:cb3d968589d8	4797
Kojto	90:cb3d968589d8	4798	/*!
Kojto	90:cb3d968589d8	4799	* @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4800	*/
Kojto	90:cb3d968589d8	4801	/@{/
Kojto	90:cb3d968589d8	4802	#define BP_ENET_RMON_T_P1024TO2047_TXPKTS (0U) /!< Bit position for ENET_RMON_T_P1024TO2047_TXPKTS. /
Kojto	90:cb3d968589d8	4803	#define BM_ENET_RMON_T_P1024TO2047_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_P1024TO2047_TXPKTS. /
Kojto	90:cb3d968589d8	4804	#define BS_ENET_RMON_T_P1024TO2047_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_P1024TO2047_TXPKTS. /
Kojto	90:cb3d968589d8	4805
Kojto	90:cb3d968589d8	4806	/! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field. /
Kojto	90:cb3d968589d8	4807	#define BR_ENET_RMON_T_P1024TO2047_TXPKTS(x) (HW_ENET_RMON_T_P1024TO2047(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4808	/@}/
Kojto	90:cb3d968589d8	4809
Kojto	90:cb3d968589d8	4810	/*******************************************************************************
Kojto	90:cb3d968589d8	4811	* HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
Kojto	90:cb3d968589d8	4812	******************************************************************************/
Kojto	90:cb3d968589d8	4813
Kojto	90:cb3d968589d8	4814	/*!
Kojto	90:cb3d968589d8	4815	* @brief HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
Kojto	90:cb3d968589d8	4816	*
Kojto	90:cb3d968589d8	4817	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4818	*/
Kojto	90:cb3d968589d8	4819	typedef union _hw_enet_rmon_t_p_gte2048
Kojto	90:cb3d968589d8	4820	{
Kojto	90:cb3d968589d8	4821	uint32_t U;
Kojto	90:cb3d968589d8	4822	struct _hw_enet_rmon_t_p_gte2048_bitfields
Kojto	90:cb3d968589d8	4823	{
Kojto	90:cb3d968589d8	4824	uint32_t TXPKTS : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	4825	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4826	} B;
Kojto	90:cb3d968589d8	4827	} hw_enet_rmon_t_p_gte2048_t;
Kojto	90:cb3d968589d8	4828
Kojto	90:cb3d968589d8	4829	/*!
Kojto	90:cb3d968589d8	4830	* @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
Kojto	90:cb3d968589d8	4831	*/
Kojto	90:cb3d968589d8	4832	/@{/
Kojto	90:cb3d968589d8	4833	#define HW_ENET_RMON_T_P_GTE2048_ADDR(x) ((x) + 0x240U)
Kojto	90:cb3d968589d8	4834
Kojto	90:cb3d968589d8	4835	#define HW_ENET_RMON_T_P_GTE2048(x) ((__I hw_enet_rmon_t_p_gte2048_t ) HW_ENET_RMON_T_P_GTE2048_ADDR(x))
Kojto	90:cb3d968589d8	4836	#define HW_ENET_RMON_T_P_GTE2048_RD(x) (HW_ENET_RMON_T_P_GTE2048(x).U)
Kojto	90:cb3d968589d8	4837	/@}/
Kojto	90:cb3d968589d8	4838
Kojto	90:cb3d968589d8	4839	/*
Kojto	90:cb3d968589d8	4840	* Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
Kojto	90:cb3d968589d8	4841	*/
Kojto	90:cb3d968589d8	4842
Kojto	90:cb3d968589d8	4843	/*!
Kojto	90:cb3d968589d8	4844	* @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
Kojto	90:cb3d968589d8	4845	*/
Kojto	90:cb3d968589d8	4846	/@{/
Kojto	90:cb3d968589d8	4847	#define BP_ENET_RMON_T_P_GTE2048_TXPKTS (0U) /!< Bit position for ENET_RMON_T_P_GTE2048_TXPKTS. /
Kojto	90:cb3d968589d8	4848	#define BM_ENET_RMON_T_P_GTE2048_TXPKTS (0x0000FFFFU) /!< Bit mask for ENET_RMON_T_P_GTE2048_TXPKTS. /
Kojto	90:cb3d968589d8	4849	#define BS_ENET_RMON_T_P_GTE2048_TXPKTS (16U) /!< Bit field size in bits for ENET_RMON_T_P_GTE2048_TXPKTS. /
Kojto	90:cb3d968589d8	4850
Kojto	90:cb3d968589d8	4851	/! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field. /
Kojto	90:cb3d968589d8	4852	#define BR_ENET_RMON_T_P_GTE2048_TXPKTS(x) (HW_ENET_RMON_T_P_GTE2048(x).B.TXPKTS)
Kojto	90:cb3d968589d8	4853	/@}/
Kojto	90:cb3d968589d8	4854
Kojto	90:cb3d968589d8	4855	/*******************************************************************************
Kojto	90:cb3d968589d8	4856	* HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
Kojto	90:cb3d968589d8	4857	******************************************************************************/
Kojto	90:cb3d968589d8	4858
Kojto	90:cb3d968589d8	4859	/*!
Kojto	90:cb3d968589d8	4860	* @brief HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
Kojto	90:cb3d968589d8	4861	*
Kojto	90:cb3d968589d8	4862	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4863	*/
Kojto	90:cb3d968589d8	4864	typedef union _hw_enet_rmon_t_octets
Kojto	90:cb3d968589d8	4865	{
Kojto	90:cb3d968589d8	4866	uint32_t U;
Kojto	90:cb3d968589d8	4867	struct _hw_enet_rmon_t_octets_bitfields
Kojto	90:cb3d968589d8	4868	{
Kojto	90:cb3d968589d8	4869	uint32_t TXOCTS : 32; /!< [31:0] Octet count /
Kojto	90:cb3d968589d8	4870	} B;
Kojto	90:cb3d968589d8	4871	} hw_enet_rmon_t_octets_t;
Kojto	90:cb3d968589d8	4872
Kojto	90:cb3d968589d8	4873	/*!
Kojto	90:cb3d968589d8	4874	* @name Constants and macros for entire ENET_RMON_T_OCTETS register
Kojto	90:cb3d968589d8	4875	*/
Kojto	90:cb3d968589d8	4876	/@{/
Kojto	90:cb3d968589d8	4877	#define HW_ENET_RMON_T_OCTETS_ADDR(x) ((x) + 0x244U)
Kojto	90:cb3d968589d8	4878
Kojto	90:cb3d968589d8	4879	#define HW_ENET_RMON_T_OCTETS(x) ((__I hw_enet_rmon_t_octets_t ) HW_ENET_RMON_T_OCTETS_ADDR(x))
Kojto	90:cb3d968589d8	4880	#define HW_ENET_RMON_T_OCTETS_RD(x) (HW_ENET_RMON_T_OCTETS(x).U)
Kojto	90:cb3d968589d8	4881	/@}/
Kojto	90:cb3d968589d8	4882
Kojto	90:cb3d968589d8	4883	/*
Kojto	90:cb3d968589d8	4884	* Constants & macros for individual ENET_RMON_T_OCTETS bitfields
Kojto	90:cb3d968589d8	4885	*/
Kojto	90:cb3d968589d8	4886
Kojto	90:cb3d968589d8	4887	/*!
Kojto	90:cb3d968589d8	4888	* @name Register ENET_RMON_T_OCTETS, field TXOCTS[31:0] (RO)
Kojto	90:cb3d968589d8	4889	*/
Kojto	90:cb3d968589d8	4890	/@{/
Kojto	90:cb3d968589d8	4891	#define BP_ENET_RMON_T_OCTETS_TXOCTS (0U) /!< Bit position for ENET_RMON_T_OCTETS_TXOCTS. /
Kojto	90:cb3d968589d8	4892	#define BM_ENET_RMON_T_OCTETS_TXOCTS (0xFFFFFFFFU) /!< Bit mask for ENET_RMON_T_OCTETS_TXOCTS. /
Kojto	90:cb3d968589d8	4893	#define BS_ENET_RMON_T_OCTETS_TXOCTS (32U) /!< Bit field size in bits for ENET_RMON_T_OCTETS_TXOCTS. /
Kojto	90:cb3d968589d8	4894
Kojto	90:cb3d968589d8	4895	/! @brief Read current value of the ENET_RMON_T_OCTETS_TXOCTS field. /
Kojto	90:cb3d968589d8	4896	#define BR_ENET_RMON_T_OCTETS_TXOCTS(x) (HW_ENET_RMON_T_OCTETS(x).U)
Kojto	90:cb3d968589d8	4897	/@}/
Kojto	90:cb3d968589d8	4898
Kojto	90:cb3d968589d8	4899	/*******************************************************************************
Kojto	90:cb3d968589d8	4900	* HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
Kojto	90:cb3d968589d8	4901	******************************************************************************/
Kojto	90:cb3d968589d8	4902
Kojto	90:cb3d968589d8	4903	/*!
Kojto	90:cb3d968589d8	4904	* @brief HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
Kojto	90:cb3d968589d8	4905	*
Kojto	90:cb3d968589d8	4906	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4907	*/
Kojto	90:cb3d968589d8	4908	typedef union _hw_enet_ieee_t_frame_ok
Kojto	90:cb3d968589d8	4909	{
Kojto	90:cb3d968589d8	4910	uint32_t U;
Kojto	90:cb3d968589d8	4911	struct _hw_enet_ieee_t_frame_ok_bitfields
Kojto	90:cb3d968589d8	4912	{
Kojto	90:cb3d968589d8	4913	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	4914	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4915	} B;
Kojto	90:cb3d968589d8	4916	} hw_enet_ieee_t_frame_ok_t;
Kojto	90:cb3d968589d8	4917
Kojto	90:cb3d968589d8	4918	/*!
Kojto	90:cb3d968589d8	4919	* @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
Kojto	90:cb3d968589d8	4920	*/
Kojto	90:cb3d968589d8	4921	/@{/
Kojto	90:cb3d968589d8	4922	#define HW_ENET_IEEE_T_FRAME_OK_ADDR(x) ((x) + 0x24CU)
Kojto	90:cb3d968589d8	4923
Kojto	90:cb3d968589d8	4924	#define HW_ENET_IEEE_T_FRAME_OK(x) ((__I hw_enet_ieee_t_frame_ok_t ) HW_ENET_IEEE_T_FRAME_OK_ADDR(x))
Kojto	90:cb3d968589d8	4925	#define HW_ENET_IEEE_T_FRAME_OK_RD(x) (HW_ENET_IEEE_T_FRAME_OK(x).U)
Kojto	90:cb3d968589d8	4926	/@}/
Kojto	90:cb3d968589d8	4927
Kojto	90:cb3d968589d8	4928	/*
Kojto	90:cb3d968589d8	4929	* Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
Kojto	90:cb3d968589d8	4930	*/
Kojto	90:cb3d968589d8	4931
Kojto	90:cb3d968589d8	4932	/*!
Kojto	90:cb3d968589d8	4933	* @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	4934	*/
Kojto	90:cb3d968589d8	4935	/@{/
Kojto	90:cb3d968589d8	4936	#define BP_ENET_IEEE_T_FRAME_OK_COUNT (0U) /!< Bit position for ENET_IEEE_T_FRAME_OK_COUNT. /
Kojto	90:cb3d968589d8	4937	#define BM_ENET_IEEE_T_FRAME_OK_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_T_FRAME_OK_COUNT. /
Kojto	90:cb3d968589d8	4938	#define BS_ENET_IEEE_T_FRAME_OK_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_T_FRAME_OK_COUNT. /
Kojto	90:cb3d968589d8	4939
Kojto	90:cb3d968589d8	4940	/! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field. /
Kojto	90:cb3d968589d8	4941	#define BR_ENET_IEEE_T_FRAME_OK_COUNT(x) (HW_ENET_IEEE_T_FRAME_OK(x).B.COUNT)
Kojto	90:cb3d968589d8	4942	/@}/
Kojto	90:cb3d968589d8	4943
Kojto	90:cb3d968589d8	4944	/*******************************************************************************
Kojto	90:cb3d968589d8	4945	* HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
Kojto	90:cb3d968589d8	4946	******************************************************************************/
Kojto	90:cb3d968589d8	4947
Kojto	90:cb3d968589d8	4948	/*!
Kojto	90:cb3d968589d8	4949	* @brief HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
Kojto	90:cb3d968589d8	4950	*
Kojto	90:cb3d968589d8	4951	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4952	*/
Kojto	90:cb3d968589d8	4953	typedef union _hw_enet_ieee_t_1col
Kojto	90:cb3d968589d8	4954	{
Kojto	90:cb3d968589d8	4955	uint32_t U;
Kojto	90:cb3d968589d8	4956	struct _hw_enet_ieee_t_1col_bitfields
Kojto	90:cb3d968589d8	4957	{
Kojto	90:cb3d968589d8	4958	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	4959	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4960	} B;
Kojto	90:cb3d968589d8	4961	} hw_enet_ieee_t_1col_t;
Kojto	90:cb3d968589d8	4962
Kojto	90:cb3d968589d8	4963	/*!
Kojto	90:cb3d968589d8	4964	* @name Constants and macros for entire ENET_IEEE_T_1COL register
Kojto	90:cb3d968589d8	4965	*/
Kojto	90:cb3d968589d8	4966	/@{/
Kojto	90:cb3d968589d8	4967	#define HW_ENET_IEEE_T_1COL_ADDR(x) ((x) + 0x250U)
Kojto	90:cb3d968589d8	4968
Kojto	90:cb3d968589d8	4969	#define HW_ENET_IEEE_T_1COL(x) ((__I hw_enet_ieee_t_1col_t ) HW_ENET_IEEE_T_1COL_ADDR(x))
Kojto	90:cb3d968589d8	4970	#define HW_ENET_IEEE_T_1COL_RD(x) (HW_ENET_IEEE_T_1COL(x).U)
Kojto	90:cb3d968589d8	4971	/@}/
Kojto	90:cb3d968589d8	4972
Kojto	90:cb3d968589d8	4973	/*
Kojto	90:cb3d968589d8	4974	* Constants & macros for individual ENET_IEEE_T_1COL bitfields
Kojto	90:cb3d968589d8	4975	*/
Kojto	90:cb3d968589d8	4976
Kojto	90:cb3d968589d8	4977	/*!
Kojto	90:cb3d968589d8	4978	* @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	4979	*/
Kojto	90:cb3d968589d8	4980	/@{/
Kojto	90:cb3d968589d8	4981	#define BP_ENET_IEEE_T_1COL_COUNT (0U) /!< Bit position for ENET_IEEE_T_1COL_COUNT. /
Kojto	90:cb3d968589d8	4982	#define BM_ENET_IEEE_T_1COL_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_T_1COL_COUNT. /
Kojto	90:cb3d968589d8	4983	#define BS_ENET_IEEE_T_1COL_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_T_1COL_COUNT. /
Kojto	90:cb3d968589d8	4984
Kojto	90:cb3d968589d8	4985	/! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field. /
Kojto	90:cb3d968589d8	4986	#define BR_ENET_IEEE_T_1COL_COUNT(x) (HW_ENET_IEEE_T_1COL(x).B.COUNT)
Kojto	90:cb3d968589d8	4987	/@}/
Kojto	90:cb3d968589d8	4988
Kojto	90:cb3d968589d8	4989	/*******************************************************************************
Kojto	90:cb3d968589d8	4990	* HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
Kojto	90:cb3d968589d8	4991	******************************************************************************/
Kojto	90:cb3d968589d8	4992
Kojto	90:cb3d968589d8	4993	/*!
Kojto	90:cb3d968589d8	4994	* @brief HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
Kojto	90:cb3d968589d8	4995	*
Kojto	90:cb3d968589d8	4996	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4997	*/
Kojto	90:cb3d968589d8	4998	typedef union _hw_enet_ieee_t_mcol
Kojto	90:cb3d968589d8	4999	{
Kojto	90:cb3d968589d8	5000	uint32_t U;
Kojto	90:cb3d968589d8	5001	struct _hw_enet_ieee_t_mcol_bitfields
Kojto	90:cb3d968589d8	5002	{
Kojto	90:cb3d968589d8	5003	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	5004	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5005	} B;
Kojto	90:cb3d968589d8	5006	} hw_enet_ieee_t_mcol_t;
Kojto	90:cb3d968589d8	5007
Kojto	90:cb3d968589d8	5008	/*!
Kojto	90:cb3d968589d8	5009	* @name Constants and macros for entire ENET_IEEE_T_MCOL register
Kojto	90:cb3d968589d8	5010	*/
Kojto	90:cb3d968589d8	5011	/@{/
Kojto	90:cb3d968589d8	5012	#define HW_ENET_IEEE_T_MCOL_ADDR(x) ((x) + 0x254U)
Kojto	90:cb3d968589d8	5013
Kojto	90:cb3d968589d8	5014	#define HW_ENET_IEEE_T_MCOL(x) ((__I hw_enet_ieee_t_mcol_t ) HW_ENET_IEEE_T_MCOL_ADDR(x))
Kojto	90:cb3d968589d8	5015	#define HW_ENET_IEEE_T_MCOL_RD(x) (HW_ENET_IEEE_T_MCOL(x).U)
Kojto	90:cb3d968589d8	5016	/@}/
Kojto	90:cb3d968589d8	5017
Kojto	90:cb3d968589d8	5018	/*
Kojto	90:cb3d968589d8	5019	* Constants & macros for individual ENET_IEEE_T_MCOL bitfields
Kojto	90:cb3d968589d8	5020	*/
Kojto	90:cb3d968589d8	5021
Kojto	90:cb3d968589d8	5022	/*!
Kojto	90:cb3d968589d8	5023	* @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5024	*/
Kojto	90:cb3d968589d8	5025	/@{/
Kojto	90:cb3d968589d8	5026	#define BP_ENET_IEEE_T_MCOL_COUNT (0U) /!< Bit position for ENET_IEEE_T_MCOL_COUNT. /
Kojto	90:cb3d968589d8	5027	#define BM_ENET_IEEE_T_MCOL_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_T_MCOL_COUNT. /
Kojto	90:cb3d968589d8	5028	#define BS_ENET_IEEE_T_MCOL_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_T_MCOL_COUNT. /
Kojto	90:cb3d968589d8	5029
Kojto	90:cb3d968589d8	5030	/! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field. /
Kojto	90:cb3d968589d8	5031	#define BR_ENET_IEEE_T_MCOL_COUNT(x) (HW_ENET_IEEE_T_MCOL(x).B.COUNT)
Kojto	90:cb3d968589d8	5032	/@}/
Kojto	90:cb3d968589d8	5033
Kojto	90:cb3d968589d8	5034	/*******************************************************************************
Kojto	90:cb3d968589d8	5035	* HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
Kojto	90:cb3d968589d8	5036	******************************************************************************/
Kojto	90:cb3d968589d8	5037
Kojto	90:cb3d968589d8	5038	/*!
Kojto	90:cb3d968589d8	5039	* @brief HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
Kojto	90:cb3d968589d8	5040	*
Kojto	90:cb3d968589d8	5041	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5042	*/
Kojto	90:cb3d968589d8	5043	typedef union _hw_enet_ieee_t_def
Kojto	90:cb3d968589d8	5044	{
Kojto	90:cb3d968589d8	5045	uint32_t U;
Kojto	90:cb3d968589d8	5046	struct _hw_enet_ieee_t_def_bitfields
Kojto	90:cb3d968589d8	5047	{
Kojto	90:cb3d968589d8	5048	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	5049	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5050	} B;
Kojto	90:cb3d968589d8	5051	} hw_enet_ieee_t_def_t;
Kojto	90:cb3d968589d8	5052
Kojto	90:cb3d968589d8	5053	/*!
Kojto	90:cb3d968589d8	5054	* @name Constants and macros for entire ENET_IEEE_T_DEF register
Kojto	90:cb3d968589d8	5055	*/
Kojto	90:cb3d968589d8	5056	/@{/
Kojto	90:cb3d968589d8	5057	#define HW_ENET_IEEE_T_DEF_ADDR(x) ((x) + 0x258U)
Kojto	90:cb3d968589d8	5058
Kojto	90:cb3d968589d8	5059	#define HW_ENET_IEEE_T_DEF(x) ((__I hw_enet_ieee_t_def_t ) HW_ENET_IEEE_T_DEF_ADDR(x))
Kojto	90:cb3d968589d8	5060	#define HW_ENET_IEEE_T_DEF_RD(x) (HW_ENET_IEEE_T_DEF(x).U)
Kojto	90:cb3d968589d8	5061	/@}/
Kojto	90:cb3d968589d8	5062
Kojto	90:cb3d968589d8	5063	/*
Kojto	90:cb3d968589d8	5064	* Constants & macros for individual ENET_IEEE_T_DEF bitfields
Kojto	90:cb3d968589d8	5065	*/
Kojto	90:cb3d968589d8	5066
Kojto	90:cb3d968589d8	5067	/*!
Kojto	90:cb3d968589d8	5068	* @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5069	*/
Kojto	90:cb3d968589d8	5070	/@{/
Kojto	90:cb3d968589d8	5071	#define BP_ENET_IEEE_T_DEF_COUNT (0U) /!< Bit position for ENET_IEEE_T_DEF_COUNT. /
Kojto	90:cb3d968589d8	5072	#define BM_ENET_IEEE_T_DEF_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_T_DEF_COUNT. /
Kojto	90:cb3d968589d8	5073	#define BS_ENET_IEEE_T_DEF_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_T_DEF_COUNT. /
Kojto	90:cb3d968589d8	5074
Kojto	90:cb3d968589d8	5075	/! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field. /
Kojto	90:cb3d968589d8	5076	#define BR_ENET_IEEE_T_DEF_COUNT(x) (HW_ENET_IEEE_T_DEF(x).B.COUNT)
Kojto	90:cb3d968589d8	5077	/@}/
Kojto	90:cb3d968589d8	5078
Kojto	90:cb3d968589d8	5079	/*******************************************************************************
Kojto	90:cb3d968589d8	5080	* HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
Kojto	90:cb3d968589d8	5081	******************************************************************************/
Kojto	90:cb3d968589d8	5082
Kojto	90:cb3d968589d8	5083	/*!
Kojto	90:cb3d968589d8	5084	* @brief HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
Kojto	90:cb3d968589d8	5085	*
Kojto	90:cb3d968589d8	5086	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5087	*/
Kojto	90:cb3d968589d8	5088	typedef union _hw_enet_ieee_t_lcol
Kojto	90:cb3d968589d8	5089	{
Kojto	90:cb3d968589d8	5090	uint32_t U;
Kojto	90:cb3d968589d8	5091	struct _hw_enet_ieee_t_lcol_bitfields
Kojto	90:cb3d968589d8	5092	{
Kojto	90:cb3d968589d8	5093	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	5094	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5095	} B;
Kojto	90:cb3d968589d8	5096	} hw_enet_ieee_t_lcol_t;
Kojto	90:cb3d968589d8	5097
Kojto	90:cb3d968589d8	5098	/*!
Kojto	90:cb3d968589d8	5099	* @name Constants and macros for entire ENET_IEEE_T_LCOL register
Kojto	90:cb3d968589d8	5100	*/
Kojto	90:cb3d968589d8	5101	/@{/
Kojto	90:cb3d968589d8	5102	#define HW_ENET_IEEE_T_LCOL_ADDR(x) ((x) + 0x25CU)
Kojto	90:cb3d968589d8	5103
Kojto	90:cb3d968589d8	5104	#define HW_ENET_IEEE_T_LCOL(x) ((__I hw_enet_ieee_t_lcol_t ) HW_ENET_IEEE_T_LCOL_ADDR(x))
Kojto	90:cb3d968589d8	5105	#define HW_ENET_IEEE_T_LCOL_RD(x) (HW_ENET_IEEE_T_LCOL(x).U)
Kojto	90:cb3d968589d8	5106	/@}/
Kojto	90:cb3d968589d8	5107
Kojto	90:cb3d968589d8	5108	/*
Kojto	90:cb3d968589d8	5109	* Constants & macros for individual ENET_IEEE_T_LCOL bitfields
Kojto	90:cb3d968589d8	5110	*/
Kojto	90:cb3d968589d8	5111
Kojto	90:cb3d968589d8	5112	/*!
Kojto	90:cb3d968589d8	5113	* @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5114	*/
Kojto	90:cb3d968589d8	5115	/@{/
Kojto	90:cb3d968589d8	5116	#define BP_ENET_IEEE_T_LCOL_COUNT (0U) /!< Bit position for ENET_IEEE_T_LCOL_COUNT. /
Kojto	90:cb3d968589d8	5117	#define BM_ENET_IEEE_T_LCOL_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_T_LCOL_COUNT. /
Kojto	90:cb3d968589d8	5118	#define BS_ENET_IEEE_T_LCOL_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_T_LCOL_COUNT. /
Kojto	90:cb3d968589d8	5119
Kojto	90:cb3d968589d8	5120	/! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field. /
Kojto	90:cb3d968589d8	5121	#define BR_ENET_IEEE_T_LCOL_COUNT(x) (HW_ENET_IEEE_T_LCOL(x).B.COUNT)
Kojto	90:cb3d968589d8	5122	/@}/
Kojto	90:cb3d968589d8	5123
Kojto	90:cb3d968589d8	5124	/*******************************************************************************
Kojto	90:cb3d968589d8	5125	* HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
Kojto	90:cb3d968589d8	5126	******************************************************************************/
Kojto	90:cb3d968589d8	5127
Kojto	90:cb3d968589d8	5128	/*!
Kojto	90:cb3d968589d8	5129	* @brief HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
Kojto	90:cb3d968589d8	5130	*
Kojto	90:cb3d968589d8	5131	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5132	*/
Kojto	90:cb3d968589d8	5133	typedef union _hw_enet_ieee_t_excol
Kojto	90:cb3d968589d8	5134	{
Kojto	90:cb3d968589d8	5135	uint32_t U;
Kojto	90:cb3d968589d8	5136	struct _hw_enet_ieee_t_excol_bitfields
Kojto	90:cb3d968589d8	5137	{
Kojto	90:cb3d968589d8	5138	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	5139	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5140	} B;
Kojto	90:cb3d968589d8	5141	} hw_enet_ieee_t_excol_t;
Kojto	90:cb3d968589d8	5142
Kojto	90:cb3d968589d8	5143	/*!
Kojto	90:cb3d968589d8	5144	* @name Constants and macros for entire ENET_IEEE_T_EXCOL register
Kojto	90:cb3d968589d8	5145	*/
Kojto	90:cb3d968589d8	5146	/@{/
Kojto	90:cb3d968589d8	5147	#define HW_ENET_IEEE_T_EXCOL_ADDR(x) ((x) + 0x260U)
Kojto	90:cb3d968589d8	5148
Kojto	90:cb3d968589d8	5149	#define HW_ENET_IEEE_T_EXCOL(x) ((__I hw_enet_ieee_t_excol_t ) HW_ENET_IEEE_T_EXCOL_ADDR(x))
Kojto	90:cb3d968589d8	5150	#define HW_ENET_IEEE_T_EXCOL_RD(x) (HW_ENET_IEEE_T_EXCOL(x).U)
Kojto	90:cb3d968589d8	5151	/@}/
Kojto	90:cb3d968589d8	5152
Kojto	90:cb3d968589d8	5153	/*
Kojto	90:cb3d968589d8	5154	* Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
Kojto	90:cb3d968589d8	5155	*/
Kojto	90:cb3d968589d8	5156
Kojto	90:cb3d968589d8	5157	/*!
Kojto	90:cb3d968589d8	5158	* @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5159	*/
Kojto	90:cb3d968589d8	5160	/@{/
Kojto	90:cb3d968589d8	5161	#define BP_ENET_IEEE_T_EXCOL_COUNT (0U) /!< Bit position for ENET_IEEE_T_EXCOL_COUNT. /
Kojto	90:cb3d968589d8	5162	#define BM_ENET_IEEE_T_EXCOL_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_T_EXCOL_COUNT. /
Kojto	90:cb3d968589d8	5163	#define BS_ENET_IEEE_T_EXCOL_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_T_EXCOL_COUNT. /
Kojto	90:cb3d968589d8	5164
Kojto	90:cb3d968589d8	5165	/! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field. /
Kojto	90:cb3d968589d8	5166	#define BR_ENET_IEEE_T_EXCOL_COUNT(x) (HW_ENET_IEEE_T_EXCOL(x).B.COUNT)
Kojto	90:cb3d968589d8	5167	/@}/
Kojto	90:cb3d968589d8	5168
Kojto	90:cb3d968589d8	5169	/*******************************************************************************
Kojto	90:cb3d968589d8	5170	* HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
Kojto	90:cb3d968589d8	5171	******************************************************************************/
Kojto	90:cb3d968589d8	5172
Kojto	90:cb3d968589d8	5173	/*!
Kojto	90:cb3d968589d8	5174	* @brief HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
Kojto	90:cb3d968589d8	5175	*
Kojto	90:cb3d968589d8	5176	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5177	*/
Kojto	90:cb3d968589d8	5178	typedef union _hw_enet_ieee_t_macerr
Kojto	90:cb3d968589d8	5179	{
Kojto	90:cb3d968589d8	5180	uint32_t U;
Kojto	90:cb3d968589d8	5181	struct _hw_enet_ieee_t_macerr_bitfields
Kojto	90:cb3d968589d8	5182	{
Kojto	90:cb3d968589d8	5183	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	5184	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5185	} B;
Kojto	90:cb3d968589d8	5186	} hw_enet_ieee_t_macerr_t;
Kojto	90:cb3d968589d8	5187
Kojto	90:cb3d968589d8	5188	/*!
Kojto	90:cb3d968589d8	5189	* @name Constants and macros for entire ENET_IEEE_T_MACERR register
Kojto	90:cb3d968589d8	5190	*/
Kojto	90:cb3d968589d8	5191	/@{/
Kojto	90:cb3d968589d8	5192	#define HW_ENET_IEEE_T_MACERR_ADDR(x) ((x) + 0x264U)
Kojto	90:cb3d968589d8	5193
Kojto	90:cb3d968589d8	5194	#define HW_ENET_IEEE_T_MACERR(x) ((__I hw_enet_ieee_t_macerr_t ) HW_ENET_IEEE_T_MACERR_ADDR(x))
Kojto	90:cb3d968589d8	5195	#define HW_ENET_IEEE_T_MACERR_RD(x) (HW_ENET_IEEE_T_MACERR(x).U)
Kojto	90:cb3d968589d8	5196	/@}/
Kojto	90:cb3d968589d8	5197
Kojto	90:cb3d968589d8	5198	/*
Kojto	90:cb3d968589d8	5199	* Constants & macros for individual ENET_IEEE_T_MACERR bitfields
Kojto	90:cb3d968589d8	5200	*/
Kojto	90:cb3d968589d8	5201
Kojto	90:cb3d968589d8	5202	/*!
Kojto	90:cb3d968589d8	5203	* @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5204	*/
Kojto	90:cb3d968589d8	5205	/@{/
Kojto	90:cb3d968589d8	5206	#define BP_ENET_IEEE_T_MACERR_COUNT (0U) /!< Bit position for ENET_IEEE_T_MACERR_COUNT. /
Kojto	90:cb3d968589d8	5207	#define BM_ENET_IEEE_T_MACERR_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_T_MACERR_COUNT. /
Kojto	90:cb3d968589d8	5208	#define BS_ENET_IEEE_T_MACERR_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_T_MACERR_COUNT. /
Kojto	90:cb3d968589d8	5209
Kojto	90:cb3d968589d8	5210	/! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field. /
Kojto	90:cb3d968589d8	5211	#define BR_ENET_IEEE_T_MACERR_COUNT(x) (HW_ENET_IEEE_T_MACERR(x).B.COUNT)
Kojto	90:cb3d968589d8	5212	/@}/
Kojto	90:cb3d968589d8	5213
Kojto	90:cb3d968589d8	5214	/*******************************************************************************
Kojto	90:cb3d968589d8	5215	* HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
Kojto	90:cb3d968589d8	5216	******************************************************************************/
Kojto	90:cb3d968589d8	5217
Kojto	90:cb3d968589d8	5218	/*!
Kojto	90:cb3d968589d8	5219	* @brief HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
Kojto	90:cb3d968589d8	5220	*
Kojto	90:cb3d968589d8	5221	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5222	*/
Kojto	90:cb3d968589d8	5223	typedef union _hw_enet_ieee_t_cserr
Kojto	90:cb3d968589d8	5224	{
Kojto	90:cb3d968589d8	5225	uint32_t U;
Kojto	90:cb3d968589d8	5226	struct _hw_enet_ieee_t_cserr_bitfields
Kojto	90:cb3d968589d8	5227	{
Kojto	90:cb3d968589d8	5228	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	5229	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5230	} B;
Kojto	90:cb3d968589d8	5231	} hw_enet_ieee_t_cserr_t;
Kojto	90:cb3d968589d8	5232
Kojto	90:cb3d968589d8	5233	/*!
Kojto	90:cb3d968589d8	5234	* @name Constants and macros for entire ENET_IEEE_T_CSERR register
Kojto	90:cb3d968589d8	5235	*/
Kojto	90:cb3d968589d8	5236	/@{/
Kojto	90:cb3d968589d8	5237	#define HW_ENET_IEEE_T_CSERR_ADDR(x) ((x) + 0x268U)
Kojto	90:cb3d968589d8	5238
Kojto	90:cb3d968589d8	5239	#define HW_ENET_IEEE_T_CSERR(x) ((__I hw_enet_ieee_t_cserr_t ) HW_ENET_IEEE_T_CSERR_ADDR(x))
Kojto	90:cb3d968589d8	5240	#define HW_ENET_IEEE_T_CSERR_RD(x) (HW_ENET_IEEE_T_CSERR(x).U)
Kojto	90:cb3d968589d8	5241	/@}/
Kojto	90:cb3d968589d8	5242
Kojto	90:cb3d968589d8	5243	/*
Kojto	90:cb3d968589d8	5244	* Constants & macros for individual ENET_IEEE_T_CSERR bitfields
Kojto	90:cb3d968589d8	5245	*/
Kojto	90:cb3d968589d8	5246
Kojto	90:cb3d968589d8	5247	/*!
Kojto	90:cb3d968589d8	5248	* @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5249	*/
Kojto	90:cb3d968589d8	5250	/@{/
Kojto	90:cb3d968589d8	5251	#define BP_ENET_IEEE_T_CSERR_COUNT (0U) /!< Bit position for ENET_IEEE_T_CSERR_COUNT. /
Kojto	90:cb3d968589d8	5252	#define BM_ENET_IEEE_T_CSERR_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_T_CSERR_COUNT. /
Kojto	90:cb3d968589d8	5253	#define BS_ENET_IEEE_T_CSERR_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_T_CSERR_COUNT. /
Kojto	90:cb3d968589d8	5254
Kojto	90:cb3d968589d8	5255	/! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field. /
Kojto	90:cb3d968589d8	5256	#define BR_ENET_IEEE_T_CSERR_COUNT(x) (HW_ENET_IEEE_T_CSERR(x).B.COUNT)
Kojto	90:cb3d968589d8	5257	/@}/
Kojto	90:cb3d968589d8	5258
Kojto	90:cb3d968589d8	5259	/*******************************************************************************
Kojto	90:cb3d968589d8	5260	* HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
Kojto	90:cb3d968589d8	5261	******************************************************************************/
Kojto	90:cb3d968589d8	5262
Kojto	90:cb3d968589d8	5263	/*!
Kojto	90:cb3d968589d8	5264	* @brief HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
Kojto	90:cb3d968589d8	5265	*
Kojto	90:cb3d968589d8	5266	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5267	*/
Kojto	90:cb3d968589d8	5268	typedef union _hw_enet_ieee_t_fdxfc
Kojto	90:cb3d968589d8	5269	{
Kojto	90:cb3d968589d8	5270	uint32_t U;
Kojto	90:cb3d968589d8	5271	struct _hw_enet_ieee_t_fdxfc_bitfields
Kojto	90:cb3d968589d8	5272	{
Kojto	90:cb3d968589d8	5273	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	5274	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5275	} B;
Kojto	90:cb3d968589d8	5276	} hw_enet_ieee_t_fdxfc_t;
Kojto	90:cb3d968589d8	5277
Kojto	90:cb3d968589d8	5278	/*!
Kojto	90:cb3d968589d8	5279	* @name Constants and macros for entire ENET_IEEE_T_FDXFC register
Kojto	90:cb3d968589d8	5280	*/
Kojto	90:cb3d968589d8	5281	/@{/
Kojto	90:cb3d968589d8	5282	#define HW_ENET_IEEE_T_FDXFC_ADDR(x) ((x) + 0x270U)
Kojto	90:cb3d968589d8	5283
Kojto	90:cb3d968589d8	5284	#define HW_ENET_IEEE_T_FDXFC(x) ((__I hw_enet_ieee_t_fdxfc_t ) HW_ENET_IEEE_T_FDXFC_ADDR(x))
Kojto	90:cb3d968589d8	5285	#define HW_ENET_IEEE_T_FDXFC_RD(x) (HW_ENET_IEEE_T_FDXFC(x).U)
Kojto	90:cb3d968589d8	5286	/@}/
Kojto	90:cb3d968589d8	5287
Kojto	90:cb3d968589d8	5288	/*
Kojto	90:cb3d968589d8	5289	* Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
Kojto	90:cb3d968589d8	5290	*/
Kojto	90:cb3d968589d8	5291
Kojto	90:cb3d968589d8	5292	/*!
Kojto	90:cb3d968589d8	5293	* @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5294	*/
Kojto	90:cb3d968589d8	5295	/@{/
Kojto	90:cb3d968589d8	5296	#define BP_ENET_IEEE_T_FDXFC_COUNT (0U) /!< Bit position for ENET_IEEE_T_FDXFC_COUNT. /
Kojto	90:cb3d968589d8	5297	#define BM_ENET_IEEE_T_FDXFC_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_T_FDXFC_COUNT. /
Kojto	90:cb3d968589d8	5298	#define BS_ENET_IEEE_T_FDXFC_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_T_FDXFC_COUNT. /
Kojto	90:cb3d968589d8	5299
Kojto	90:cb3d968589d8	5300	/! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field. /
Kojto	90:cb3d968589d8	5301	#define BR_ENET_IEEE_T_FDXFC_COUNT(x) (HW_ENET_IEEE_T_FDXFC(x).B.COUNT)
Kojto	90:cb3d968589d8	5302	/@}/
Kojto	90:cb3d968589d8	5303
Kojto	90:cb3d968589d8	5304	/*******************************************************************************
Kojto	90:cb3d968589d8	5305	* HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
Kojto	90:cb3d968589d8	5306	******************************************************************************/
Kojto	90:cb3d968589d8	5307
Kojto	90:cb3d968589d8	5308	/*!
Kojto	90:cb3d968589d8	5309	* @brief HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
Kojto	90:cb3d968589d8	5310	*
Kojto	90:cb3d968589d8	5311	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5312	*
Kojto	90:cb3d968589d8	5313	* Counts total octets (includes header and FCS fields).
Kojto	90:cb3d968589d8	5314	*/
Kojto	90:cb3d968589d8	5315	typedef union _hw_enet_ieee_t_octets_ok
Kojto	90:cb3d968589d8	5316	{
Kojto	90:cb3d968589d8	5317	uint32_t U;
Kojto	90:cb3d968589d8	5318	struct _hw_enet_ieee_t_octets_ok_bitfields
Kojto	90:cb3d968589d8	5319	{
Kojto	90:cb3d968589d8	5320	uint32_t COUNT : 32; /!< [31:0] Octet count /
Kojto	90:cb3d968589d8	5321	} B;
Kojto	90:cb3d968589d8	5322	} hw_enet_ieee_t_octets_ok_t;
Kojto	90:cb3d968589d8	5323
Kojto	90:cb3d968589d8	5324	/*!
Kojto	90:cb3d968589d8	5325	* @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
Kojto	90:cb3d968589d8	5326	*/
Kojto	90:cb3d968589d8	5327	/@{/
Kojto	90:cb3d968589d8	5328	#define HW_ENET_IEEE_T_OCTETS_OK_ADDR(x) ((x) + 0x274U)
Kojto	90:cb3d968589d8	5329
Kojto	90:cb3d968589d8	5330	#define HW_ENET_IEEE_T_OCTETS_OK(x) ((__I hw_enet_ieee_t_octets_ok_t ) HW_ENET_IEEE_T_OCTETS_OK_ADDR(x))
Kojto	90:cb3d968589d8	5331	#define HW_ENET_IEEE_T_OCTETS_OK_RD(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
Kojto	90:cb3d968589d8	5332	/@}/
Kojto	90:cb3d968589d8	5333
Kojto	90:cb3d968589d8	5334	/*
Kojto	90:cb3d968589d8	5335	* Constants & macros for individual ENET_IEEE_T_OCTETS_OK bitfields
Kojto	90:cb3d968589d8	5336	*/
Kojto	90:cb3d968589d8	5337
Kojto	90:cb3d968589d8	5338	/*!
Kojto	90:cb3d968589d8	5339	* @name Register ENET_IEEE_T_OCTETS_OK, field COUNT[31:0] (RO)
Kojto	90:cb3d968589d8	5340	*/
Kojto	90:cb3d968589d8	5341	/@{/
Kojto	90:cb3d968589d8	5342	#define BP_ENET_IEEE_T_OCTETS_OK_COUNT (0U) /!< Bit position for ENET_IEEE_T_OCTETS_OK_COUNT. /
Kojto	90:cb3d968589d8	5343	#define BM_ENET_IEEE_T_OCTETS_OK_COUNT (0xFFFFFFFFU) /!< Bit mask for ENET_IEEE_T_OCTETS_OK_COUNT. /
Kojto	90:cb3d968589d8	5344	#define BS_ENET_IEEE_T_OCTETS_OK_COUNT (32U) /!< Bit field size in bits for ENET_IEEE_T_OCTETS_OK_COUNT. /
Kojto	90:cb3d968589d8	5345
Kojto	90:cb3d968589d8	5346	/! @brief Read current value of the ENET_IEEE_T_OCTETS_OK_COUNT field. /
Kojto	90:cb3d968589d8	5347	#define BR_ENET_IEEE_T_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
Kojto	90:cb3d968589d8	5348	/@}/
Kojto	90:cb3d968589d8	5349
Kojto	90:cb3d968589d8	5350	/*******************************************************************************
Kojto	90:cb3d968589d8	5351	* HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
Kojto	90:cb3d968589d8	5352	******************************************************************************/
Kojto	90:cb3d968589d8	5353
Kojto	90:cb3d968589d8	5354	/*!
Kojto	90:cb3d968589d8	5355	* @brief HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
Kojto	90:cb3d968589d8	5356	*
Kojto	90:cb3d968589d8	5357	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5358	*/
Kojto	90:cb3d968589d8	5359	typedef union _hw_enet_rmon_r_packets
Kojto	90:cb3d968589d8	5360	{
Kojto	90:cb3d968589d8	5361	uint32_t U;
Kojto	90:cb3d968589d8	5362	struct _hw_enet_rmon_r_packets_bitfields
Kojto	90:cb3d968589d8	5363	{
Kojto	90:cb3d968589d8	5364	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5365	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5366	} B;
Kojto	90:cb3d968589d8	5367	} hw_enet_rmon_r_packets_t;
Kojto	90:cb3d968589d8	5368
Kojto	90:cb3d968589d8	5369	/*!
Kojto	90:cb3d968589d8	5370	* @name Constants and macros for entire ENET_RMON_R_PACKETS register
Kojto	90:cb3d968589d8	5371	*/
Kojto	90:cb3d968589d8	5372	/@{/
Kojto	90:cb3d968589d8	5373	#define HW_ENET_RMON_R_PACKETS_ADDR(x) ((x) + 0x284U)
Kojto	90:cb3d968589d8	5374
Kojto	90:cb3d968589d8	5375	#define HW_ENET_RMON_R_PACKETS(x) ((__I hw_enet_rmon_r_packets_t ) HW_ENET_RMON_R_PACKETS_ADDR(x))
Kojto	90:cb3d968589d8	5376	#define HW_ENET_RMON_R_PACKETS_RD(x) (HW_ENET_RMON_R_PACKETS(x).U)
Kojto	90:cb3d968589d8	5377	/@}/
Kojto	90:cb3d968589d8	5378
Kojto	90:cb3d968589d8	5379	/*
Kojto	90:cb3d968589d8	5380	* Constants & macros for individual ENET_RMON_R_PACKETS bitfields
Kojto	90:cb3d968589d8	5381	*/
Kojto	90:cb3d968589d8	5382
Kojto	90:cb3d968589d8	5383	/*!
Kojto	90:cb3d968589d8	5384	* @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5385	*/
Kojto	90:cb3d968589d8	5386	/@{/
Kojto	90:cb3d968589d8	5387	#define BP_ENET_RMON_R_PACKETS_COUNT (0U) /!< Bit position for ENET_RMON_R_PACKETS_COUNT. /
Kojto	90:cb3d968589d8	5388	#define BM_ENET_RMON_R_PACKETS_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_PACKETS_COUNT. /
Kojto	90:cb3d968589d8	5389	#define BS_ENET_RMON_R_PACKETS_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_PACKETS_COUNT. /
Kojto	90:cb3d968589d8	5390
Kojto	90:cb3d968589d8	5391	/! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field. /
Kojto	90:cb3d968589d8	5392	#define BR_ENET_RMON_R_PACKETS_COUNT(x) (HW_ENET_RMON_R_PACKETS(x).B.COUNT)
Kojto	90:cb3d968589d8	5393	/@}/
Kojto	90:cb3d968589d8	5394
Kojto	90:cb3d968589d8	5395	/*******************************************************************************
Kojto	90:cb3d968589d8	5396	* HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
Kojto	90:cb3d968589d8	5397	******************************************************************************/
Kojto	90:cb3d968589d8	5398
Kojto	90:cb3d968589d8	5399	/*!
Kojto	90:cb3d968589d8	5400	* @brief HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	5401	*
Kojto	90:cb3d968589d8	5402	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5403	*/
Kojto	90:cb3d968589d8	5404	typedef union _hw_enet_rmon_r_bc_pkt
Kojto	90:cb3d968589d8	5405	{
Kojto	90:cb3d968589d8	5406	uint32_t U;
Kojto	90:cb3d968589d8	5407	struct _hw_enet_rmon_r_bc_pkt_bitfields
Kojto	90:cb3d968589d8	5408	{
Kojto	90:cb3d968589d8	5409	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5410	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5411	} B;
Kojto	90:cb3d968589d8	5412	} hw_enet_rmon_r_bc_pkt_t;
Kojto	90:cb3d968589d8	5413
Kojto	90:cb3d968589d8	5414	/*!
Kojto	90:cb3d968589d8	5415	* @name Constants and macros for entire ENET_RMON_R_BC_PKT register
Kojto	90:cb3d968589d8	5416	*/
Kojto	90:cb3d968589d8	5417	/@{/
Kojto	90:cb3d968589d8	5418	#define HW_ENET_RMON_R_BC_PKT_ADDR(x) ((x) + 0x288U)
Kojto	90:cb3d968589d8	5419
Kojto	90:cb3d968589d8	5420	#define HW_ENET_RMON_R_BC_PKT(x) ((__I hw_enet_rmon_r_bc_pkt_t ) HW_ENET_RMON_R_BC_PKT_ADDR(x))
Kojto	90:cb3d968589d8	5421	#define HW_ENET_RMON_R_BC_PKT_RD(x) (HW_ENET_RMON_R_BC_PKT(x).U)
Kojto	90:cb3d968589d8	5422	/@}/
Kojto	90:cb3d968589d8	5423
Kojto	90:cb3d968589d8	5424	/*
Kojto	90:cb3d968589d8	5425	* Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
Kojto	90:cb3d968589d8	5426	*/
Kojto	90:cb3d968589d8	5427
Kojto	90:cb3d968589d8	5428	/*!
Kojto	90:cb3d968589d8	5429	* @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5430	*/
Kojto	90:cb3d968589d8	5431	/@{/
Kojto	90:cb3d968589d8	5432	#define BP_ENET_RMON_R_BC_PKT_COUNT (0U) /!< Bit position for ENET_RMON_R_BC_PKT_COUNT. /
Kojto	90:cb3d968589d8	5433	#define BM_ENET_RMON_R_BC_PKT_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_BC_PKT_COUNT. /
Kojto	90:cb3d968589d8	5434	#define BS_ENET_RMON_R_BC_PKT_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_BC_PKT_COUNT. /
Kojto	90:cb3d968589d8	5435
Kojto	90:cb3d968589d8	5436	/! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field. /
Kojto	90:cb3d968589d8	5437	#define BR_ENET_RMON_R_BC_PKT_COUNT(x) (HW_ENET_RMON_R_BC_PKT(x).B.COUNT)
Kojto	90:cb3d968589d8	5438	/@}/
Kojto	90:cb3d968589d8	5439
Kojto	90:cb3d968589d8	5440	/*******************************************************************************
Kojto	90:cb3d968589d8	5441	* HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
Kojto	90:cb3d968589d8	5442	******************************************************************************/
Kojto	90:cb3d968589d8	5443
Kojto	90:cb3d968589d8	5444	/*!
Kojto	90:cb3d968589d8	5445	* @brief HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	5446	*
Kojto	90:cb3d968589d8	5447	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5448	*/
Kojto	90:cb3d968589d8	5449	typedef union _hw_enet_rmon_r_mc_pkt
Kojto	90:cb3d968589d8	5450	{
Kojto	90:cb3d968589d8	5451	uint32_t U;
Kojto	90:cb3d968589d8	5452	struct _hw_enet_rmon_r_mc_pkt_bitfields
Kojto	90:cb3d968589d8	5453	{
Kojto	90:cb3d968589d8	5454	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5455	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5456	} B;
Kojto	90:cb3d968589d8	5457	} hw_enet_rmon_r_mc_pkt_t;
Kojto	90:cb3d968589d8	5458
Kojto	90:cb3d968589d8	5459	/*!
Kojto	90:cb3d968589d8	5460	* @name Constants and macros for entire ENET_RMON_R_MC_PKT register
Kojto	90:cb3d968589d8	5461	*/
Kojto	90:cb3d968589d8	5462	/@{/
Kojto	90:cb3d968589d8	5463	#define HW_ENET_RMON_R_MC_PKT_ADDR(x) ((x) + 0x28CU)
Kojto	90:cb3d968589d8	5464
Kojto	90:cb3d968589d8	5465	#define HW_ENET_RMON_R_MC_PKT(x) ((__I hw_enet_rmon_r_mc_pkt_t ) HW_ENET_RMON_R_MC_PKT_ADDR(x))
Kojto	90:cb3d968589d8	5466	#define HW_ENET_RMON_R_MC_PKT_RD(x) (HW_ENET_RMON_R_MC_PKT(x).U)
Kojto	90:cb3d968589d8	5467	/@}/
Kojto	90:cb3d968589d8	5468
Kojto	90:cb3d968589d8	5469	/*
Kojto	90:cb3d968589d8	5470	* Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
Kojto	90:cb3d968589d8	5471	*/
Kojto	90:cb3d968589d8	5472
Kojto	90:cb3d968589d8	5473	/*!
Kojto	90:cb3d968589d8	5474	* @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5475	*/
Kojto	90:cb3d968589d8	5476	/@{/
Kojto	90:cb3d968589d8	5477	#define BP_ENET_RMON_R_MC_PKT_COUNT (0U) /!< Bit position for ENET_RMON_R_MC_PKT_COUNT. /
Kojto	90:cb3d968589d8	5478	#define BM_ENET_RMON_R_MC_PKT_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_MC_PKT_COUNT. /
Kojto	90:cb3d968589d8	5479	#define BS_ENET_RMON_R_MC_PKT_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_MC_PKT_COUNT. /
Kojto	90:cb3d968589d8	5480
Kojto	90:cb3d968589d8	5481	/! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field. /
Kojto	90:cb3d968589d8	5482	#define BR_ENET_RMON_R_MC_PKT_COUNT(x) (HW_ENET_RMON_R_MC_PKT(x).B.COUNT)
Kojto	90:cb3d968589d8	5483	/@}/
Kojto	90:cb3d968589d8	5484
Kojto	90:cb3d968589d8	5485	/*******************************************************************************
Kojto	90:cb3d968589d8	5486	* HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
Kojto	90:cb3d968589d8	5487	******************************************************************************/
Kojto	90:cb3d968589d8	5488
Kojto	90:cb3d968589d8	5489	/*!
Kojto	90:cb3d968589d8	5490	* @brief HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
Kojto	90:cb3d968589d8	5491	*
Kojto	90:cb3d968589d8	5492	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5493	*/
Kojto	90:cb3d968589d8	5494	typedef union _hw_enet_rmon_r_crc_align
Kojto	90:cb3d968589d8	5495	{
Kojto	90:cb3d968589d8	5496	uint32_t U;
Kojto	90:cb3d968589d8	5497	struct _hw_enet_rmon_r_crc_align_bitfields
Kojto	90:cb3d968589d8	5498	{
Kojto	90:cb3d968589d8	5499	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5500	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5501	} B;
Kojto	90:cb3d968589d8	5502	} hw_enet_rmon_r_crc_align_t;
Kojto	90:cb3d968589d8	5503
Kojto	90:cb3d968589d8	5504	/*!
Kojto	90:cb3d968589d8	5505	* @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
Kojto	90:cb3d968589d8	5506	*/
Kojto	90:cb3d968589d8	5507	/@{/
Kojto	90:cb3d968589d8	5508	#define HW_ENET_RMON_R_CRC_ALIGN_ADDR(x) ((x) + 0x290U)
Kojto	90:cb3d968589d8	5509
Kojto	90:cb3d968589d8	5510	#define HW_ENET_RMON_R_CRC_ALIGN(x) ((__I hw_enet_rmon_r_crc_align_t ) HW_ENET_RMON_R_CRC_ALIGN_ADDR(x))
Kojto	90:cb3d968589d8	5511	#define HW_ENET_RMON_R_CRC_ALIGN_RD(x) (HW_ENET_RMON_R_CRC_ALIGN(x).U)
Kojto	90:cb3d968589d8	5512	/@}/
Kojto	90:cb3d968589d8	5513
Kojto	90:cb3d968589d8	5514	/*
Kojto	90:cb3d968589d8	5515	* Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
Kojto	90:cb3d968589d8	5516	*/
Kojto	90:cb3d968589d8	5517
Kojto	90:cb3d968589d8	5518	/*!
Kojto	90:cb3d968589d8	5519	* @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5520	*/
Kojto	90:cb3d968589d8	5521	/@{/
Kojto	90:cb3d968589d8	5522	#define BP_ENET_RMON_R_CRC_ALIGN_COUNT (0U) /!< Bit position for ENET_RMON_R_CRC_ALIGN_COUNT. /
Kojto	90:cb3d968589d8	5523	#define BM_ENET_RMON_R_CRC_ALIGN_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_CRC_ALIGN_COUNT. /
Kojto	90:cb3d968589d8	5524	#define BS_ENET_RMON_R_CRC_ALIGN_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_CRC_ALIGN_COUNT. /
Kojto	90:cb3d968589d8	5525
Kojto	90:cb3d968589d8	5526	/! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field. /
Kojto	90:cb3d968589d8	5527	#define BR_ENET_RMON_R_CRC_ALIGN_COUNT(x) (HW_ENET_RMON_R_CRC_ALIGN(x).B.COUNT)
Kojto	90:cb3d968589d8	5528	/@}/
Kojto	90:cb3d968589d8	5529
Kojto	90:cb3d968589d8	5530	/*******************************************************************************
Kojto	90:cb3d968589d8	5531	* HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
Kojto	90:cb3d968589d8	5532	******************************************************************************/
Kojto	90:cb3d968589d8	5533
Kojto	90:cb3d968589d8	5534	/*!
Kojto	90:cb3d968589d8	5535	* @brief HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
Kojto	90:cb3d968589d8	5536	*
Kojto	90:cb3d968589d8	5537	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5538	*/
Kojto	90:cb3d968589d8	5539	typedef union _hw_enet_rmon_r_undersize
Kojto	90:cb3d968589d8	5540	{
Kojto	90:cb3d968589d8	5541	uint32_t U;
Kojto	90:cb3d968589d8	5542	struct _hw_enet_rmon_r_undersize_bitfields
Kojto	90:cb3d968589d8	5543	{
Kojto	90:cb3d968589d8	5544	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5545	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5546	} B;
Kojto	90:cb3d968589d8	5547	} hw_enet_rmon_r_undersize_t;
Kojto	90:cb3d968589d8	5548
Kojto	90:cb3d968589d8	5549	/*!
Kojto	90:cb3d968589d8	5550	* @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
Kojto	90:cb3d968589d8	5551	*/
Kojto	90:cb3d968589d8	5552	/@{/
Kojto	90:cb3d968589d8	5553	#define HW_ENET_RMON_R_UNDERSIZE_ADDR(x) ((x) + 0x294U)
Kojto	90:cb3d968589d8	5554
Kojto	90:cb3d968589d8	5555	#define HW_ENET_RMON_R_UNDERSIZE(x) ((__I hw_enet_rmon_r_undersize_t ) HW_ENET_RMON_R_UNDERSIZE_ADDR(x))
Kojto	90:cb3d968589d8	5556	#define HW_ENET_RMON_R_UNDERSIZE_RD(x) (HW_ENET_RMON_R_UNDERSIZE(x).U)
Kojto	90:cb3d968589d8	5557	/@}/
Kojto	90:cb3d968589d8	5558
Kojto	90:cb3d968589d8	5559	/*
Kojto	90:cb3d968589d8	5560	* Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
Kojto	90:cb3d968589d8	5561	*/
Kojto	90:cb3d968589d8	5562
Kojto	90:cb3d968589d8	5563	/*!
Kojto	90:cb3d968589d8	5564	* @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5565	*/
Kojto	90:cb3d968589d8	5566	/@{/
Kojto	90:cb3d968589d8	5567	#define BP_ENET_RMON_R_UNDERSIZE_COUNT (0U) /!< Bit position for ENET_RMON_R_UNDERSIZE_COUNT. /
Kojto	90:cb3d968589d8	5568	#define BM_ENET_RMON_R_UNDERSIZE_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_UNDERSIZE_COUNT. /
Kojto	90:cb3d968589d8	5569	#define BS_ENET_RMON_R_UNDERSIZE_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_UNDERSIZE_COUNT. /
Kojto	90:cb3d968589d8	5570
Kojto	90:cb3d968589d8	5571	/! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field. /
Kojto	90:cb3d968589d8	5572	#define BR_ENET_RMON_R_UNDERSIZE_COUNT(x) (HW_ENET_RMON_R_UNDERSIZE(x).B.COUNT)
Kojto	90:cb3d968589d8	5573	/@}/
Kojto	90:cb3d968589d8	5574
Kojto	90:cb3d968589d8	5575	/*******************************************************************************
Kojto	90:cb3d968589d8	5576	* HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
Kojto	90:cb3d968589d8	5577	******************************************************************************/
Kojto	90:cb3d968589d8	5578
Kojto	90:cb3d968589d8	5579	/*!
Kojto	90:cb3d968589d8	5580	* @brief HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
Kojto	90:cb3d968589d8	5581	*
Kojto	90:cb3d968589d8	5582	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5583	*/
Kojto	90:cb3d968589d8	5584	typedef union _hw_enet_rmon_r_oversize
Kojto	90:cb3d968589d8	5585	{
Kojto	90:cb3d968589d8	5586	uint32_t U;
Kojto	90:cb3d968589d8	5587	struct _hw_enet_rmon_r_oversize_bitfields
Kojto	90:cb3d968589d8	5588	{
Kojto	90:cb3d968589d8	5589	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5590	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5591	} B;
Kojto	90:cb3d968589d8	5592	} hw_enet_rmon_r_oversize_t;
Kojto	90:cb3d968589d8	5593
Kojto	90:cb3d968589d8	5594	/*!
Kojto	90:cb3d968589d8	5595	* @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
Kojto	90:cb3d968589d8	5596	*/
Kojto	90:cb3d968589d8	5597	/@{/
Kojto	90:cb3d968589d8	5598	#define HW_ENET_RMON_R_OVERSIZE_ADDR(x) ((x) + 0x298U)
Kojto	90:cb3d968589d8	5599
Kojto	90:cb3d968589d8	5600	#define HW_ENET_RMON_R_OVERSIZE(x) ((__I hw_enet_rmon_r_oversize_t ) HW_ENET_RMON_R_OVERSIZE_ADDR(x))
Kojto	90:cb3d968589d8	5601	#define HW_ENET_RMON_R_OVERSIZE_RD(x) (HW_ENET_RMON_R_OVERSIZE(x).U)
Kojto	90:cb3d968589d8	5602	/@}/
Kojto	90:cb3d968589d8	5603
Kojto	90:cb3d968589d8	5604	/*
Kojto	90:cb3d968589d8	5605	* Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
Kojto	90:cb3d968589d8	5606	*/
Kojto	90:cb3d968589d8	5607
Kojto	90:cb3d968589d8	5608	/*!
Kojto	90:cb3d968589d8	5609	* @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5610	*/
Kojto	90:cb3d968589d8	5611	/@{/
Kojto	90:cb3d968589d8	5612	#define BP_ENET_RMON_R_OVERSIZE_COUNT (0U) /!< Bit position for ENET_RMON_R_OVERSIZE_COUNT. /
Kojto	90:cb3d968589d8	5613	#define BM_ENET_RMON_R_OVERSIZE_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_OVERSIZE_COUNT. /
Kojto	90:cb3d968589d8	5614	#define BS_ENET_RMON_R_OVERSIZE_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_OVERSIZE_COUNT. /
Kojto	90:cb3d968589d8	5615
Kojto	90:cb3d968589d8	5616	/! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field. /
Kojto	90:cb3d968589d8	5617	#define BR_ENET_RMON_R_OVERSIZE_COUNT(x) (HW_ENET_RMON_R_OVERSIZE(x).B.COUNT)
Kojto	90:cb3d968589d8	5618	/@}/
Kojto	90:cb3d968589d8	5619
Kojto	90:cb3d968589d8	5620	/*******************************************************************************
Kojto	90:cb3d968589d8	5621	* HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
Kojto	90:cb3d968589d8	5622	******************************************************************************/
Kojto	90:cb3d968589d8	5623
Kojto	90:cb3d968589d8	5624	/*!
Kojto	90:cb3d968589d8	5625	* @brief HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
Kojto	90:cb3d968589d8	5626	*
Kojto	90:cb3d968589d8	5627	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5628	*/
Kojto	90:cb3d968589d8	5629	typedef union _hw_enet_rmon_r_frag
Kojto	90:cb3d968589d8	5630	{
Kojto	90:cb3d968589d8	5631	uint32_t U;
Kojto	90:cb3d968589d8	5632	struct _hw_enet_rmon_r_frag_bitfields
Kojto	90:cb3d968589d8	5633	{
Kojto	90:cb3d968589d8	5634	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5635	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5636	} B;
Kojto	90:cb3d968589d8	5637	} hw_enet_rmon_r_frag_t;
Kojto	90:cb3d968589d8	5638
Kojto	90:cb3d968589d8	5639	/*!
Kojto	90:cb3d968589d8	5640	* @name Constants and macros for entire ENET_RMON_R_FRAG register
Kojto	90:cb3d968589d8	5641	*/
Kojto	90:cb3d968589d8	5642	/@{/
Kojto	90:cb3d968589d8	5643	#define HW_ENET_RMON_R_FRAG_ADDR(x) ((x) + 0x29CU)
Kojto	90:cb3d968589d8	5644
Kojto	90:cb3d968589d8	5645	#define HW_ENET_RMON_R_FRAG(x) ((__I hw_enet_rmon_r_frag_t ) HW_ENET_RMON_R_FRAG_ADDR(x))
Kojto	90:cb3d968589d8	5646	#define HW_ENET_RMON_R_FRAG_RD(x) (HW_ENET_RMON_R_FRAG(x).U)
Kojto	90:cb3d968589d8	5647	/@}/
Kojto	90:cb3d968589d8	5648
Kojto	90:cb3d968589d8	5649	/*
Kojto	90:cb3d968589d8	5650	* Constants & macros for individual ENET_RMON_R_FRAG bitfields
Kojto	90:cb3d968589d8	5651	*/
Kojto	90:cb3d968589d8	5652
Kojto	90:cb3d968589d8	5653	/*!
Kojto	90:cb3d968589d8	5654	* @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5655	*/
Kojto	90:cb3d968589d8	5656	/@{/
Kojto	90:cb3d968589d8	5657	#define BP_ENET_RMON_R_FRAG_COUNT (0U) /!< Bit position for ENET_RMON_R_FRAG_COUNT. /
Kojto	90:cb3d968589d8	5658	#define BM_ENET_RMON_R_FRAG_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_FRAG_COUNT. /
Kojto	90:cb3d968589d8	5659	#define BS_ENET_RMON_R_FRAG_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_FRAG_COUNT. /
Kojto	90:cb3d968589d8	5660
Kojto	90:cb3d968589d8	5661	/! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field. /
Kojto	90:cb3d968589d8	5662	#define BR_ENET_RMON_R_FRAG_COUNT(x) (HW_ENET_RMON_R_FRAG(x).B.COUNT)
Kojto	90:cb3d968589d8	5663	/@}/
Kojto	90:cb3d968589d8	5664
Kojto	90:cb3d968589d8	5665	/*******************************************************************************
Kojto	90:cb3d968589d8	5666	* HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
Kojto	90:cb3d968589d8	5667	******************************************************************************/
Kojto	90:cb3d968589d8	5668
Kojto	90:cb3d968589d8	5669	/*!
Kojto	90:cb3d968589d8	5670	* @brief HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
Kojto	90:cb3d968589d8	5671	*
Kojto	90:cb3d968589d8	5672	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5673	*/
Kojto	90:cb3d968589d8	5674	typedef union _hw_enet_rmon_r_jab
Kojto	90:cb3d968589d8	5675	{
Kojto	90:cb3d968589d8	5676	uint32_t U;
Kojto	90:cb3d968589d8	5677	struct _hw_enet_rmon_r_jab_bitfields
Kojto	90:cb3d968589d8	5678	{
Kojto	90:cb3d968589d8	5679	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5680	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5681	} B;
Kojto	90:cb3d968589d8	5682	} hw_enet_rmon_r_jab_t;
Kojto	90:cb3d968589d8	5683
Kojto	90:cb3d968589d8	5684	/*!
Kojto	90:cb3d968589d8	5685	* @name Constants and macros for entire ENET_RMON_R_JAB register
Kojto	90:cb3d968589d8	5686	*/
Kojto	90:cb3d968589d8	5687	/@{/
Kojto	90:cb3d968589d8	5688	#define HW_ENET_RMON_R_JAB_ADDR(x) ((x) + 0x2A0U)
Kojto	90:cb3d968589d8	5689
Kojto	90:cb3d968589d8	5690	#define HW_ENET_RMON_R_JAB(x) ((__I hw_enet_rmon_r_jab_t ) HW_ENET_RMON_R_JAB_ADDR(x))
Kojto	90:cb3d968589d8	5691	#define HW_ENET_RMON_R_JAB_RD(x) (HW_ENET_RMON_R_JAB(x).U)
Kojto	90:cb3d968589d8	5692	/@}/
Kojto	90:cb3d968589d8	5693
Kojto	90:cb3d968589d8	5694	/*
Kojto	90:cb3d968589d8	5695	* Constants & macros for individual ENET_RMON_R_JAB bitfields
Kojto	90:cb3d968589d8	5696	*/
Kojto	90:cb3d968589d8	5697
Kojto	90:cb3d968589d8	5698	/*!
Kojto	90:cb3d968589d8	5699	* @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5700	*/
Kojto	90:cb3d968589d8	5701	/@{/
Kojto	90:cb3d968589d8	5702	#define BP_ENET_RMON_R_JAB_COUNT (0U) /!< Bit position for ENET_RMON_R_JAB_COUNT. /
Kojto	90:cb3d968589d8	5703	#define BM_ENET_RMON_R_JAB_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_JAB_COUNT. /
Kojto	90:cb3d968589d8	5704	#define BS_ENET_RMON_R_JAB_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_JAB_COUNT. /
Kojto	90:cb3d968589d8	5705
Kojto	90:cb3d968589d8	5706	/! @brief Read current value of the ENET_RMON_R_JAB_COUNT field. /
Kojto	90:cb3d968589d8	5707	#define BR_ENET_RMON_R_JAB_COUNT(x) (HW_ENET_RMON_R_JAB(x).B.COUNT)
Kojto	90:cb3d968589d8	5708	/@}/
Kojto	90:cb3d968589d8	5709
Kojto	90:cb3d968589d8	5710	/*******************************************************************************
Kojto	90:cb3d968589d8	5711	* HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	5712	******************************************************************************/
Kojto	90:cb3d968589d8	5713
Kojto	90:cb3d968589d8	5714	/*!
Kojto	90:cb3d968589d8	5715	* @brief HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	5716	*
Kojto	90:cb3d968589d8	5717	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5718	*/
Kojto	90:cb3d968589d8	5719	typedef union _hw_enet_rmon_r_p64
Kojto	90:cb3d968589d8	5720	{
Kojto	90:cb3d968589d8	5721	uint32_t U;
Kojto	90:cb3d968589d8	5722	struct _hw_enet_rmon_r_p64_bitfields
Kojto	90:cb3d968589d8	5723	{
Kojto	90:cb3d968589d8	5724	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5725	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5726	} B;
Kojto	90:cb3d968589d8	5727	} hw_enet_rmon_r_p64_t;
Kojto	90:cb3d968589d8	5728
Kojto	90:cb3d968589d8	5729	/*!
Kojto	90:cb3d968589d8	5730	* @name Constants and macros for entire ENET_RMON_R_P64 register
Kojto	90:cb3d968589d8	5731	*/
Kojto	90:cb3d968589d8	5732	/@{/
Kojto	90:cb3d968589d8	5733	#define HW_ENET_RMON_R_P64_ADDR(x) ((x) + 0x2A8U)
Kojto	90:cb3d968589d8	5734
Kojto	90:cb3d968589d8	5735	#define HW_ENET_RMON_R_P64(x) ((__I hw_enet_rmon_r_p64_t ) HW_ENET_RMON_R_P64_ADDR(x))
Kojto	90:cb3d968589d8	5736	#define HW_ENET_RMON_R_P64_RD(x) (HW_ENET_RMON_R_P64(x).U)
Kojto	90:cb3d968589d8	5737	/@}/
Kojto	90:cb3d968589d8	5738
Kojto	90:cb3d968589d8	5739	/*
Kojto	90:cb3d968589d8	5740	* Constants & macros for individual ENET_RMON_R_P64 bitfields
Kojto	90:cb3d968589d8	5741	*/
Kojto	90:cb3d968589d8	5742
Kojto	90:cb3d968589d8	5743	/*!
Kojto	90:cb3d968589d8	5744	* @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5745	*/
Kojto	90:cb3d968589d8	5746	/@{/
Kojto	90:cb3d968589d8	5747	#define BP_ENET_RMON_R_P64_COUNT (0U) /!< Bit position for ENET_RMON_R_P64_COUNT. /
Kojto	90:cb3d968589d8	5748	#define BM_ENET_RMON_R_P64_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_P64_COUNT. /
Kojto	90:cb3d968589d8	5749	#define BS_ENET_RMON_R_P64_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_P64_COUNT. /
Kojto	90:cb3d968589d8	5750
Kojto	90:cb3d968589d8	5751	/! @brief Read current value of the ENET_RMON_R_P64_COUNT field. /
Kojto	90:cb3d968589d8	5752	#define BR_ENET_RMON_R_P64_COUNT(x) (HW_ENET_RMON_R_P64(x).B.COUNT)
Kojto	90:cb3d968589d8	5753	/@}/
Kojto	90:cb3d968589d8	5754
Kojto	90:cb3d968589d8	5755	/*******************************************************************************
Kojto	90:cb3d968589d8	5756	* HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	5757	******************************************************************************/
Kojto	90:cb3d968589d8	5758
Kojto	90:cb3d968589d8	5759	/*!
Kojto	90:cb3d968589d8	5760	* @brief HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	5761	*
Kojto	90:cb3d968589d8	5762	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5763	*/
Kojto	90:cb3d968589d8	5764	typedef union _hw_enet_rmon_r_p65to127
Kojto	90:cb3d968589d8	5765	{
Kojto	90:cb3d968589d8	5766	uint32_t U;
Kojto	90:cb3d968589d8	5767	struct _hw_enet_rmon_r_p65to127_bitfields
Kojto	90:cb3d968589d8	5768	{
Kojto	90:cb3d968589d8	5769	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5770	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5771	} B;
Kojto	90:cb3d968589d8	5772	} hw_enet_rmon_r_p65to127_t;
Kojto	90:cb3d968589d8	5773
Kojto	90:cb3d968589d8	5774	/*!
Kojto	90:cb3d968589d8	5775	* @name Constants and macros for entire ENET_RMON_R_P65TO127 register
Kojto	90:cb3d968589d8	5776	*/
Kojto	90:cb3d968589d8	5777	/@{/
Kojto	90:cb3d968589d8	5778	#define HW_ENET_RMON_R_P65TO127_ADDR(x) ((x) + 0x2ACU)
Kojto	90:cb3d968589d8	5779
Kojto	90:cb3d968589d8	5780	#define HW_ENET_RMON_R_P65TO127(x) ((__I hw_enet_rmon_r_p65to127_t ) HW_ENET_RMON_R_P65TO127_ADDR(x))
Kojto	90:cb3d968589d8	5781	#define HW_ENET_RMON_R_P65TO127_RD(x) (HW_ENET_RMON_R_P65TO127(x).U)
Kojto	90:cb3d968589d8	5782	/@}/
Kojto	90:cb3d968589d8	5783
Kojto	90:cb3d968589d8	5784	/*
Kojto	90:cb3d968589d8	5785	* Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
Kojto	90:cb3d968589d8	5786	*/
Kojto	90:cb3d968589d8	5787
Kojto	90:cb3d968589d8	5788	/*!
Kojto	90:cb3d968589d8	5789	* @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5790	*/
Kojto	90:cb3d968589d8	5791	/@{/
Kojto	90:cb3d968589d8	5792	#define BP_ENET_RMON_R_P65TO127_COUNT (0U) /!< Bit position for ENET_RMON_R_P65TO127_COUNT. /
Kojto	90:cb3d968589d8	5793	#define BM_ENET_RMON_R_P65TO127_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_P65TO127_COUNT. /
Kojto	90:cb3d968589d8	5794	#define BS_ENET_RMON_R_P65TO127_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_P65TO127_COUNT. /
Kojto	90:cb3d968589d8	5795
Kojto	90:cb3d968589d8	5796	/! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field. /
Kojto	90:cb3d968589d8	5797	#define BR_ENET_RMON_R_P65TO127_COUNT(x) (HW_ENET_RMON_R_P65TO127(x).B.COUNT)
Kojto	90:cb3d968589d8	5798	/@}/
Kojto	90:cb3d968589d8	5799
Kojto	90:cb3d968589d8	5800	/*******************************************************************************
Kojto	90:cb3d968589d8	5801	* HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	5802	******************************************************************************/
Kojto	90:cb3d968589d8	5803
Kojto	90:cb3d968589d8	5804	/*!
Kojto	90:cb3d968589d8	5805	* @brief HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	5806	*
Kojto	90:cb3d968589d8	5807	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5808	*/
Kojto	90:cb3d968589d8	5809	typedef union _hw_enet_rmon_r_p128to255
Kojto	90:cb3d968589d8	5810	{
Kojto	90:cb3d968589d8	5811	uint32_t U;
Kojto	90:cb3d968589d8	5812	struct _hw_enet_rmon_r_p128to255_bitfields
Kojto	90:cb3d968589d8	5813	{
Kojto	90:cb3d968589d8	5814	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5815	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5816	} B;
Kojto	90:cb3d968589d8	5817	} hw_enet_rmon_r_p128to255_t;
Kojto	90:cb3d968589d8	5818
Kojto	90:cb3d968589d8	5819	/*!
Kojto	90:cb3d968589d8	5820	* @name Constants and macros for entire ENET_RMON_R_P128TO255 register
Kojto	90:cb3d968589d8	5821	*/
Kojto	90:cb3d968589d8	5822	/@{/
Kojto	90:cb3d968589d8	5823	#define HW_ENET_RMON_R_P128TO255_ADDR(x) ((x) + 0x2B0U)
Kojto	90:cb3d968589d8	5824
Kojto	90:cb3d968589d8	5825	#define HW_ENET_RMON_R_P128TO255(x) ((__I hw_enet_rmon_r_p128to255_t ) HW_ENET_RMON_R_P128TO255_ADDR(x))
Kojto	90:cb3d968589d8	5826	#define HW_ENET_RMON_R_P128TO255_RD(x) (HW_ENET_RMON_R_P128TO255(x).U)
Kojto	90:cb3d968589d8	5827	/@}/
Kojto	90:cb3d968589d8	5828
Kojto	90:cb3d968589d8	5829	/*
Kojto	90:cb3d968589d8	5830	* Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
Kojto	90:cb3d968589d8	5831	*/
Kojto	90:cb3d968589d8	5832
Kojto	90:cb3d968589d8	5833	/*!
Kojto	90:cb3d968589d8	5834	* @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5835	*/
Kojto	90:cb3d968589d8	5836	/@{/
Kojto	90:cb3d968589d8	5837	#define BP_ENET_RMON_R_P128TO255_COUNT (0U) /!< Bit position for ENET_RMON_R_P128TO255_COUNT. /
Kojto	90:cb3d968589d8	5838	#define BM_ENET_RMON_R_P128TO255_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_P128TO255_COUNT. /
Kojto	90:cb3d968589d8	5839	#define BS_ENET_RMON_R_P128TO255_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_P128TO255_COUNT. /
Kojto	90:cb3d968589d8	5840
Kojto	90:cb3d968589d8	5841	/! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field. /
Kojto	90:cb3d968589d8	5842	#define BR_ENET_RMON_R_P128TO255_COUNT(x) (HW_ENET_RMON_R_P128TO255(x).B.COUNT)
Kojto	90:cb3d968589d8	5843	/@}/
Kojto	90:cb3d968589d8	5844
Kojto	90:cb3d968589d8	5845	/*******************************************************************************
Kojto	90:cb3d968589d8	5846	* HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	5847	******************************************************************************/
Kojto	90:cb3d968589d8	5848
Kojto	90:cb3d968589d8	5849	/*!
Kojto	90:cb3d968589d8	5850	* @brief HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	5851	*
Kojto	90:cb3d968589d8	5852	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5853	*/
Kojto	90:cb3d968589d8	5854	typedef union _hw_enet_rmon_r_p256to511
Kojto	90:cb3d968589d8	5855	{
Kojto	90:cb3d968589d8	5856	uint32_t U;
Kojto	90:cb3d968589d8	5857	struct _hw_enet_rmon_r_p256to511_bitfields
Kojto	90:cb3d968589d8	5858	{
Kojto	90:cb3d968589d8	5859	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5860	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5861	} B;
Kojto	90:cb3d968589d8	5862	} hw_enet_rmon_r_p256to511_t;
Kojto	90:cb3d968589d8	5863
Kojto	90:cb3d968589d8	5864	/*!
Kojto	90:cb3d968589d8	5865	* @name Constants and macros for entire ENET_RMON_R_P256TO511 register
Kojto	90:cb3d968589d8	5866	*/
Kojto	90:cb3d968589d8	5867	/@{/
Kojto	90:cb3d968589d8	5868	#define HW_ENET_RMON_R_P256TO511_ADDR(x) ((x) + 0x2B4U)
Kojto	90:cb3d968589d8	5869
Kojto	90:cb3d968589d8	5870	#define HW_ENET_RMON_R_P256TO511(x) ((__I hw_enet_rmon_r_p256to511_t ) HW_ENET_RMON_R_P256TO511_ADDR(x))
Kojto	90:cb3d968589d8	5871	#define HW_ENET_RMON_R_P256TO511_RD(x) (HW_ENET_RMON_R_P256TO511(x).U)
Kojto	90:cb3d968589d8	5872	/@}/
Kojto	90:cb3d968589d8	5873
Kojto	90:cb3d968589d8	5874	/*
Kojto	90:cb3d968589d8	5875	* Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
Kojto	90:cb3d968589d8	5876	*/
Kojto	90:cb3d968589d8	5877
Kojto	90:cb3d968589d8	5878	/*!
Kojto	90:cb3d968589d8	5879	* @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5880	*/
Kojto	90:cb3d968589d8	5881	/@{/
Kojto	90:cb3d968589d8	5882	#define BP_ENET_RMON_R_P256TO511_COUNT (0U) /!< Bit position for ENET_RMON_R_P256TO511_COUNT. /
Kojto	90:cb3d968589d8	5883	#define BM_ENET_RMON_R_P256TO511_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_P256TO511_COUNT. /
Kojto	90:cb3d968589d8	5884	#define BS_ENET_RMON_R_P256TO511_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_P256TO511_COUNT. /
Kojto	90:cb3d968589d8	5885
Kojto	90:cb3d968589d8	5886	/! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field. /
Kojto	90:cb3d968589d8	5887	#define BR_ENET_RMON_R_P256TO511_COUNT(x) (HW_ENET_RMON_R_P256TO511(x).B.COUNT)
Kojto	90:cb3d968589d8	5888	/@}/
Kojto	90:cb3d968589d8	5889
Kojto	90:cb3d968589d8	5890	/*******************************************************************************
Kojto	90:cb3d968589d8	5891	* HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	5892	******************************************************************************/
Kojto	90:cb3d968589d8	5893
Kojto	90:cb3d968589d8	5894	/*!
Kojto	90:cb3d968589d8	5895	* @brief HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	5896	*
Kojto	90:cb3d968589d8	5897	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5898	*/
Kojto	90:cb3d968589d8	5899	typedef union _hw_enet_rmon_r_p512to1023
Kojto	90:cb3d968589d8	5900	{
Kojto	90:cb3d968589d8	5901	uint32_t U;
Kojto	90:cb3d968589d8	5902	struct _hw_enet_rmon_r_p512to1023_bitfields
Kojto	90:cb3d968589d8	5903	{
Kojto	90:cb3d968589d8	5904	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5905	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5906	} B;
Kojto	90:cb3d968589d8	5907	} hw_enet_rmon_r_p512to1023_t;
Kojto	90:cb3d968589d8	5908
Kojto	90:cb3d968589d8	5909	/*!
Kojto	90:cb3d968589d8	5910	* @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
Kojto	90:cb3d968589d8	5911	*/
Kojto	90:cb3d968589d8	5912	/@{/
Kojto	90:cb3d968589d8	5913	#define HW_ENET_RMON_R_P512TO1023_ADDR(x) ((x) + 0x2B8U)
Kojto	90:cb3d968589d8	5914
Kojto	90:cb3d968589d8	5915	#define HW_ENET_RMON_R_P512TO1023(x) ((__I hw_enet_rmon_r_p512to1023_t ) HW_ENET_RMON_R_P512TO1023_ADDR(x))
Kojto	90:cb3d968589d8	5916	#define HW_ENET_RMON_R_P512TO1023_RD(x) (HW_ENET_RMON_R_P512TO1023(x).U)
Kojto	90:cb3d968589d8	5917	/@}/
Kojto	90:cb3d968589d8	5918
Kojto	90:cb3d968589d8	5919	/*
Kojto	90:cb3d968589d8	5920	* Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
Kojto	90:cb3d968589d8	5921	*/
Kojto	90:cb3d968589d8	5922
Kojto	90:cb3d968589d8	5923	/*!
Kojto	90:cb3d968589d8	5924	* @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5925	*/
Kojto	90:cb3d968589d8	5926	/@{/
Kojto	90:cb3d968589d8	5927	#define BP_ENET_RMON_R_P512TO1023_COUNT (0U) /!< Bit position for ENET_RMON_R_P512TO1023_COUNT. /
Kojto	90:cb3d968589d8	5928	#define BM_ENET_RMON_R_P512TO1023_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_P512TO1023_COUNT. /
Kojto	90:cb3d968589d8	5929	#define BS_ENET_RMON_R_P512TO1023_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_P512TO1023_COUNT. /
Kojto	90:cb3d968589d8	5930
Kojto	90:cb3d968589d8	5931	/! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field. /
Kojto	90:cb3d968589d8	5932	#define BR_ENET_RMON_R_P512TO1023_COUNT(x) (HW_ENET_RMON_R_P512TO1023(x).B.COUNT)
Kojto	90:cb3d968589d8	5933	/@}/
Kojto	90:cb3d968589d8	5934
Kojto	90:cb3d968589d8	5935	/*******************************************************************************
Kojto	90:cb3d968589d8	5936	* HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
Kojto	90:cb3d968589d8	5937	******************************************************************************/
Kojto	90:cb3d968589d8	5938
Kojto	90:cb3d968589d8	5939	/*!
Kojto	90:cb3d968589d8	5940	* @brief HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
Kojto	90:cb3d968589d8	5941	*
Kojto	90:cb3d968589d8	5942	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5943	*/
Kojto	90:cb3d968589d8	5944	typedef union _hw_enet_rmon_r_p1024to2047
Kojto	90:cb3d968589d8	5945	{
Kojto	90:cb3d968589d8	5946	uint32_t U;
Kojto	90:cb3d968589d8	5947	struct _hw_enet_rmon_r_p1024to2047_bitfields
Kojto	90:cb3d968589d8	5948	{
Kojto	90:cb3d968589d8	5949	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5950	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5951	} B;
Kojto	90:cb3d968589d8	5952	} hw_enet_rmon_r_p1024to2047_t;
Kojto	90:cb3d968589d8	5953
Kojto	90:cb3d968589d8	5954	/*!
Kojto	90:cb3d968589d8	5955	* @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
Kojto	90:cb3d968589d8	5956	*/
Kojto	90:cb3d968589d8	5957	/@{/
Kojto	90:cb3d968589d8	5958	#define HW_ENET_RMON_R_P1024TO2047_ADDR(x) ((x) + 0x2BCU)
Kojto	90:cb3d968589d8	5959
Kojto	90:cb3d968589d8	5960	#define HW_ENET_RMON_R_P1024TO2047(x) ((__I hw_enet_rmon_r_p1024to2047_t ) HW_ENET_RMON_R_P1024TO2047_ADDR(x))
Kojto	90:cb3d968589d8	5961	#define HW_ENET_RMON_R_P1024TO2047_RD(x) (HW_ENET_RMON_R_P1024TO2047(x).U)
Kojto	90:cb3d968589d8	5962	/@}/
Kojto	90:cb3d968589d8	5963
Kojto	90:cb3d968589d8	5964	/*
Kojto	90:cb3d968589d8	5965	* Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
Kojto	90:cb3d968589d8	5966	*/
Kojto	90:cb3d968589d8	5967
Kojto	90:cb3d968589d8	5968	/*!
Kojto	90:cb3d968589d8	5969	* @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	5970	*/
Kojto	90:cb3d968589d8	5971	/@{/
Kojto	90:cb3d968589d8	5972	#define BP_ENET_RMON_R_P1024TO2047_COUNT (0U) /!< Bit position for ENET_RMON_R_P1024TO2047_COUNT. /
Kojto	90:cb3d968589d8	5973	#define BM_ENET_RMON_R_P1024TO2047_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_P1024TO2047_COUNT. /
Kojto	90:cb3d968589d8	5974	#define BS_ENET_RMON_R_P1024TO2047_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_P1024TO2047_COUNT. /
Kojto	90:cb3d968589d8	5975
Kojto	90:cb3d968589d8	5976	/! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field. /
Kojto	90:cb3d968589d8	5977	#define BR_ENET_RMON_R_P1024TO2047_COUNT(x) (HW_ENET_RMON_R_P1024TO2047(x).B.COUNT)
Kojto	90:cb3d968589d8	5978	/@}/
Kojto	90:cb3d968589d8	5979
Kojto	90:cb3d968589d8	5980	/*******************************************************************************
Kojto	90:cb3d968589d8	5981	* HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
Kojto	90:cb3d968589d8	5982	******************************************************************************/
Kojto	90:cb3d968589d8	5983
Kojto	90:cb3d968589d8	5984	/*!
Kojto	90:cb3d968589d8	5985	* @brief HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
Kojto	90:cb3d968589d8	5986	*
Kojto	90:cb3d968589d8	5987	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	5988	*/
Kojto	90:cb3d968589d8	5989	typedef union _hw_enet_rmon_r_p_gte2048
Kojto	90:cb3d968589d8	5990	{
Kojto	90:cb3d968589d8	5991	uint32_t U;
Kojto	90:cb3d968589d8	5992	struct _hw_enet_rmon_r_p_gte2048_bitfields
Kojto	90:cb3d968589d8	5993	{
Kojto	90:cb3d968589d8	5994	uint32_t COUNT : 16; /!< [15:0] Packet count /
Kojto	90:cb3d968589d8	5995	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5996	} B;
Kojto	90:cb3d968589d8	5997	} hw_enet_rmon_r_p_gte2048_t;
Kojto	90:cb3d968589d8	5998
Kojto	90:cb3d968589d8	5999	/*!
Kojto	90:cb3d968589d8	6000	* @name Constants and macros for entire ENET_RMON_R_P_GTE2048 register
Kojto	90:cb3d968589d8	6001	*/
Kojto	90:cb3d968589d8	6002	/@{/
Kojto	90:cb3d968589d8	6003	#define HW_ENET_RMON_R_P_GTE2048_ADDR(x) ((x) + 0x2C0U)
Kojto	90:cb3d968589d8	6004
Kojto	90:cb3d968589d8	6005	#define HW_ENET_RMON_R_P_GTE2048(x) ((__I hw_enet_rmon_r_p_gte2048_t ) HW_ENET_RMON_R_P_GTE2048_ADDR(x))
Kojto	90:cb3d968589d8	6006	#define HW_ENET_RMON_R_P_GTE2048_RD(x) (HW_ENET_RMON_R_P_GTE2048(x).U)
Kojto	90:cb3d968589d8	6007	/@}/
Kojto	90:cb3d968589d8	6008
Kojto	90:cb3d968589d8	6009	/*
Kojto	90:cb3d968589d8	6010	* Constants & macros for individual ENET_RMON_R_P_GTE2048 bitfields
Kojto	90:cb3d968589d8	6011	*/
Kojto	90:cb3d968589d8	6012
Kojto	90:cb3d968589d8	6013	/*!
Kojto	90:cb3d968589d8	6014	* @name Register ENET_RMON_R_P_GTE2048, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	6015	*/
Kojto	90:cb3d968589d8	6016	/@{/
Kojto	90:cb3d968589d8	6017	#define BP_ENET_RMON_R_P_GTE2048_COUNT (0U) /!< Bit position for ENET_RMON_R_P_GTE2048_COUNT. /
Kojto	90:cb3d968589d8	6018	#define BM_ENET_RMON_R_P_GTE2048_COUNT (0x0000FFFFU) /!< Bit mask for ENET_RMON_R_P_GTE2048_COUNT. /
Kojto	90:cb3d968589d8	6019	#define BS_ENET_RMON_R_P_GTE2048_COUNT (16U) /!< Bit field size in bits for ENET_RMON_R_P_GTE2048_COUNT. /
Kojto	90:cb3d968589d8	6020
Kojto	90:cb3d968589d8	6021	/! @brief Read current value of the ENET_RMON_R_P_GTE2048_COUNT field. /
Kojto	90:cb3d968589d8	6022	#define BR_ENET_RMON_R_P_GTE2048_COUNT(x) (HW_ENET_RMON_R_P_GTE2048(x).B.COUNT)
Kojto	90:cb3d968589d8	6023	/@}/
Kojto	90:cb3d968589d8	6024
Kojto	90:cb3d968589d8	6025	/*******************************************************************************
Kojto	90:cb3d968589d8	6026	* HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
Kojto	90:cb3d968589d8	6027	******************************************************************************/
Kojto	90:cb3d968589d8	6028
Kojto	90:cb3d968589d8	6029	/*!
Kojto	90:cb3d968589d8	6030	* @brief HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
Kojto	90:cb3d968589d8	6031	*
Kojto	90:cb3d968589d8	6032	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6033	*/
Kojto	90:cb3d968589d8	6034	typedef union _hw_enet_rmon_r_octets
Kojto	90:cb3d968589d8	6035	{
Kojto	90:cb3d968589d8	6036	uint32_t U;
Kojto	90:cb3d968589d8	6037	struct _hw_enet_rmon_r_octets_bitfields
Kojto	90:cb3d968589d8	6038	{
Kojto	90:cb3d968589d8	6039	uint32_t COUNT : 32; /!< [31:0] Octet count /
Kojto	90:cb3d968589d8	6040	} B;
Kojto	90:cb3d968589d8	6041	} hw_enet_rmon_r_octets_t;
Kojto	90:cb3d968589d8	6042
Kojto	90:cb3d968589d8	6043	/*!
Kojto	90:cb3d968589d8	6044	* @name Constants and macros for entire ENET_RMON_R_OCTETS register
Kojto	90:cb3d968589d8	6045	*/
Kojto	90:cb3d968589d8	6046	/@{/
Kojto	90:cb3d968589d8	6047	#define HW_ENET_RMON_R_OCTETS_ADDR(x) ((x) + 0x2C4U)
Kojto	90:cb3d968589d8	6048
Kojto	90:cb3d968589d8	6049	#define HW_ENET_RMON_R_OCTETS(x) ((__I hw_enet_rmon_r_octets_t ) HW_ENET_RMON_R_OCTETS_ADDR(x))
Kojto	90:cb3d968589d8	6050	#define HW_ENET_RMON_R_OCTETS_RD(x) (HW_ENET_RMON_R_OCTETS(x).U)
Kojto	90:cb3d968589d8	6051	/@}/
Kojto	90:cb3d968589d8	6052
Kojto	90:cb3d968589d8	6053	/*
Kojto	90:cb3d968589d8	6054	* Constants & macros for individual ENET_RMON_R_OCTETS bitfields
Kojto	90:cb3d968589d8	6055	*/
Kojto	90:cb3d968589d8	6056
Kojto	90:cb3d968589d8	6057	/*!
Kojto	90:cb3d968589d8	6058	* @name Register ENET_RMON_R_OCTETS, field COUNT[31:0] (RO)
Kojto	90:cb3d968589d8	6059	*/
Kojto	90:cb3d968589d8	6060	/@{/
Kojto	90:cb3d968589d8	6061	#define BP_ENET_RMON_R_OCTETS_COUNT (0U) /!< Bit position for ENET_RMON_R_OCTETS_COUNT. /
Kojto	90:cb3d968589d8	6062	#define BM_ENET_RMON_R_OCTETS_COUNT (0xFFFFFFFFU) /!< Bit mask for ENET_RMON_R_OCTETS_COUNT. /
Kojto	90:cb3d968589d8	6063	#define BS_ENET_RMON_R_OCTETS_COUNT (32U) /!< Bit field size in bits for ENET_RMON_R_OCTETS_COUNT. /
Kojto	90:cb3d968589d8	6064
Kojto	90:cb3d968589d8	6065	/! @brief Read current value of the ENET_RMON_R_OCTETS_COUNT field. /
Kojto	90:cb3d968589d8	6066	#define BR_ENET_RMON_R_OCTETS_COUNT(x) (HW_ENET_RMON_R_OCTETS(x).U)
Kojto	90:cb3d968589d8	6067	/@}/
Kojto	90:cb3d968589d8	6068
Kojto	90:cb3d968589d8	6069	/*******************************************************************************
Kojto	90:cb3d968589d8	6070	* HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
Kojto	90:cb3d968589d8	6071	******************************************************************************/
Kojto	90:cb3d968589d8	6072
Kojto	90:cb3d968589d8	6073	/*!
Kojto	90:cb3d968589d8	6074	* @brief HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
Kojto	90:cb3d968589d8	6075	*
Kojto	90:cb3d968589d8	6076	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6077	*
Kojto	90:cb3d968589d8	6078	* Counter increments if a frame with invalid or missing SFD character is
Kojto	90:cb3d968589d8	6079	* detected and has been dropped. None of the other counters increments if this counter
Kojto	90:cb3d968589d8	6080	* increments.
Kojto	90:cb3d968589d8	6081	*/
Kojto	90:cb3d968589d8	6082	typedef union _hw_enet_ieee_r_drop
Kojto	90:cb3d968589d8	6083	{
Kojto	90:cb3d968589d8	6084	uint32_t U;
Kojto	90:cb3d968589d8	6085	struct _hw_enet_ieee_r_drop_bitfields
Kojto	90:cb3d968589d8	6086	{
Kojto	90:cb3d968589d8	6087	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	6088	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	6089	} B;
Kojto	90:cb3d968589d8	6090	} hw_enet_ieee_r_drop_t;
Kojto	90:cb3d968589d8	6091
Kojto	90:cb3d968589d8	6092	/*!
Kojto	90:cb3d968589d8	6093	* @name Constants and macros for entire ENET_IEEE_R_DROP register
Kojto	90:cb3d968589d8	6094	*/
Kojto	90:cb3d968589d8	6095	/@{/
Kojto	90:cb3d968589d8	6096	#define HW_ENET_IEEE_R_DROP_ADDR(x) ((x) + 0x2C8U)
Kojto	90:cb3d968589d8	6097
Kojto	90:cb3d968589d8	6098	#define HW_ENET_IEEE_R_DROP(x) ((__I hw_enet_ieee_r_drop_t ) HW_ENET_IEEE_R_DROP_ADDR(x))
Kojto	90:cb3d968589d8	6099	#define HW_ENET_IEEE_R_DROP_RD(x) (HW_ENET_IEEE_R_DROP(x).U)
Kojto	90:cb3d968589d8	6100	/@}/
Kojto	90:cb3d968589d8	6101
Kojto	90:cb3d968589d8	6102	/*
Kojto	90:cb3d968589d8	6103	* Constants & macros for individual ENET_IEEE_R_DROP bitfields
Kojto	90:cb3d968589d8	6104	*/
Kojto	90:cb3d968589d8	6105
Kojto	90:cb3d968589d8	6106	/*!
Kojto	90:cb3d968589d8	6107	* @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	6108	*/
Kojto	90:cb3d968589d8	6109	/@{/
Kojto	90:cb3d968589d8	6110	#define BP_ENET_IEEE_R_DROP_COUNT (0U) /!< Bit position for ENET_IEEE_R_DROP_COUNT. /
Kojto	90:cb3d968589d8	6111	#define BM_ENET_IEEE_R_DROP_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_R_DROP_COUNT. /
Kojto	90:cb3d968589d8	6112	#define BS_ENET_IEEE_R_DROP_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_R_DROP_COUNT. /
Kojto	90:cb3d968589d8	6113
Kojto	90:cb3d968589d8	6114	/! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field. /
Kojto	90:cb3d968589d8	6115	#define BR_ENET_IEEE_R_DROP_COUNT(x) (HW_ENET_IEEE_R_DROP(x).B.COUNT)
Kojto	90:cb3d968589d8	6116	/@}/
Kojto	90:cb3d968589d8	6117
Kojto	90:cb3d968589d8	6118	/*******************************************************************************
Kojto	90:cb3d968589d8	6119	* HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
Kojto	90:cb3d968589d8	6120	******************************************************************************/
Kojto	90:cb3d968589d8	6121
Kojto	90:cb3d968589d8	6122	/*!
Kojto	90:cb3d968589d8	6123	* @brief HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
Kojto	90:cb3d968589d8	6124	*
Kojto	90:cb3d968589d8	6125	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6126	*/
Kojto	90:cb3d968589d8	6127	typedef union _hw_enet_ieee_r_frame_ok
Kojto	90:cb3d968589d8	6128	{
Kojto	90:cb3d968589d8	6129	uint32_t U;
Kojto	90:cb3d968589d8	6130	struct _hw_enet_ieee_r_frame_ok_bitfields
Kojto	90:cb3d968589d8	6131	{
Kojto	90:cb3d968589d8	6132	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	6133	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	6134	} B;
Kojto	90:cb3d968589d8	6135	} hw_enet_ieee_r_frame_ok_t;
Kojto	90:cb3d968589d8	6136
Kojto	90:cb3d968589d8	6137	/*!
Kojto	90:cb3d968589d8	6138	* @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
Kojto	90:cb3d968589d8	6139	*/
Kojto	90:cb3d968589d8	6140	/@{/
Kojto	90:cb3d968589d8	6141	#define HW_ENET_IEEE_R_FRAME_OK_ADDR(x) ((x) + 0x2CCU)
Kojto	90:cb3d968589d8	6142
Kojto	90:cb3d968589d8	6143	#define HW_ENET_IEEE_R_FRAME_OK(x) ((__I hw_enet_ieee_r_frame_ok_t ) HW_ENET_IEEE_R_FRAME_OK_ADDR(x))
Kojto	90:cb3d968589d8	6144	#define HW_ENET_IEEE_R_FRAME_OK_RD(x) (HW_ENET_IEEE_R_FRAME_OK(x).U)
Kojto	90:cb3d968589d8	6145	/@}/
Kojto	90:cb3d968589d8	6146
Kojto	90:cb3d968589d8	6147	/*
Kojto	90:cb3d968589d8	6148	* Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
Kojto	90:cb3d968589d8	6149	*/
Kojto	90:cb3d968589d8	6150
Kojto	90:cb3d968589d8	6151	/*!
Kojto	90:cb3d968589d8	6152	* @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	6153	*/
Kojto	90:cb3d968589d8	6154	/@{/
Kojto	90:cb3d968589d8	6155	#define BP_ENET_IEEE_R_FRAME_OK_COUNT (0U) /!< Bit position for ENET_IEEE_R_FRAME_OK_COUNT. /
Kojto	90:cb3d968589d8	6156	#define BM_ENET_IEEE_R_FRAME_OK_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_R_FRAME_OK_COUNT. /
Kojto	90:cb3d968589d8	6157	#define BS_ENET_IEEE_R_FRAME_OK_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_R_FRAME_OK_COUNT. /
Kojto	90:cb3d968589d8	6158
Kojto	90:cb3d968589d8	6159	/! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field. /
Kojto	90:cb3d968589d8	6160	#define BR_ENET_IEEE_R_FRAME_OK_COUNT(x) (HW_ENET_IEEE_R_FRAME_OK(x).B.COUNT)
Kojto	90:cb3d968589d8	6161	/@}/
Kojto	90:cb3d968589d8	6162
Kojto	90:cb3d968589d8	6163	/*******************************************************************************
Kojto	90:cb3d968589d8	6164	* HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
Kojto	90:cb3d968589d8	6165	******************************************************************************/
Kojto	90:cb3d968589d8	6166
Kojto	90:cb3d968589d8	6167	/*!
Kojto	90:cb3d968589d8	6168	* @brief HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
Kojto	90:cb3d968589d8	6169	*
Kojto	90:cb3d968589d8	6170	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6171	*/
Kojto	90:cb3d968589d8	6172	typedef union _hw_enet_ieee_r_crc
Kojto	90:cb3d968589d8	6173	{
Kojto	90:cb3d968589d8	6174	uint32_t U;
Kojto	90:cb3d968589d8	6175	struct _hw_enet_ieee_r_crc_bitfields
Kojto	90:cb3d968589d8	6176	{
Kojto	90:cb3d968589d8	6177	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	6178	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	6179	} B;
Kojto	90:cb3d968589d8	6180	} hw_enet_ieee_r_crc_t;
Kojto	90:cb3d968589d8	6181
Kojto	90:cb3d968589d8	6182	/*!
Kojto	90:cb3d968589d8	6183	* @name Constants and macros for entire ENET_IEEE_R_CRC register
Kojto	90:cb3d968589d8	6184	*/
Kojto	90:cb3d968589d8	6185	/@{/
Kojto	90:cb3d968589d8	6186	#define HW_ENET_IEEE_R_CRC_ADDR(x) ((x) + 0x2D0U)
Kojto	90:cb3d968589d8	6187
Kojto	90:cb3d968589d8	6188	#define HW_ENET_IEEE_R_CRC(x) ((__I hw_enet_ieee_r_crc_t ) HW_ENET_IEEE_R_CRC_ADDR(x))
Kojto	90:cb3d968589d8	6189	#define HW_ENET_IEEE_R_CRC_RD(x) (HW_ENET_IEEE_R_CRC(x).U)
Kojto	90:cb3d968589d8	6190	/@}/
Kojto	90:cb3d968589d8	6191
Kojto	90:cb3d968589d8	6192	/*
Kojto	90:cb3d968589d8	6193	* Constants & macros for individual ENET_IEEE_R_CRC bitfields
Kojto	90:cb3d968589d8	6194	*/
Kojto	90:cb3d968589d8	6195
Kojto	90:cb3d968589d8	6196	/*!
Kojto	90:cb3d968589d8	6197	* @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	6198	*/
Kojto	90:cb3d968589d8	6199	/@{/
Kojto	90:cb3d968589d8	6200	#define BP_ENET_IEEE_R_CRC_COUNT (0U) /!< Bit position for ENET_IEEE_R_CRC_COUNT. /
Kojto	90:cb3d968589d8	6201	#define BM_ENET_IEEE_R_CRC_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_R_CRC_COUNT. /
Kojto	90:cb3d968589d8	6202	#define BS_ENET_IEEE_R_CRC_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_R_CRC_COUNT. /
Kojto	90:cb3d968589d8	6203
Kojto	90:cb3d968589d8	6204	/! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field. /
Kojto	90:cb3d968589d8	6205	#define BR_ENET_IEEE_R_CRC_COUNT(x) (HW_ENET_IEEE_R_CRC(x).B.COUNT)
Kojto	90:cb3d968589d8	6206	/@}/
Kojto	90:cb3d968589d8	6207
Kojto	90:cb3d968589d8	6208	/*******************************************************************************
Kojto	90:cb3d968589d8	6209	* HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
Kojto	90:cb3d968589d8	6210	******************************************************************************/
Kojto	90:cb3d968589d8	6211
Kojto	90:cb3d968589d8	6212	/*!
Kojto	90:cb3d968589d8	6213	* @brief HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
Kojto	90:cb3d968589d8	6214	*
Kojto	90:cb3d968589d8	6215	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6216	*/
Kojto	90:cb3d968589d8	6217	typedef union _hw_enet_ieee_r_align
Kojto	90:cb3d968589d8	6218	{
Kojto	90:cb3d968589d8	6219	uint32_t U;
Kojto	90:cb3d968589d8	6220	struct _hw_enet_ieee_r_align_bitfields
Kojto	90:cb3d968589d8	6221	{
Kojto	90:cb3d968589d8	6222	uint32_t COUNT : 16; /!< [15:0] Frame count /
Kojto	90:cb3d968589d8	6223	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	6224	} B;
Kojto	90:cb3d968589d8	6225	} hw_enet_ieee_r_align_t;
Kojto	90:cb3d968589d8	6226
Kojto	90:cb3d968589d8	6227	/*!
Kojto	90:cb3d968589d8	6228	* @name Constants and macros for entire ENET_IEEE_R_ALIGN register
Kojto	90:cb3d968589d8	6229	*/
Kojto	90:cb3d968589d8	6230	/@{/
Kojto	90:cb3d968589d8	6231	#define HW_ENET_IEEE_R_ALIGN_ADDR(x) ((x) + 0x2D4U)
Kojto	90:cb3d968589d8	6232
Kojto	90:cb3d968589d8	6233	#define HW_ENET_IEEE_R_ALIGN(x) ((__I hw_enet_ieee_r_align_t ) HW_ENET_IEEE_R_ALIGN_ADDR(x))
Kojto	90:cb3d968589d8	6234	#define HW_ENET_IEEE_R_ALIGN_RD(x) (HW_ENET_IEEE_R_ALIGN(x).U)
Kojto	90:cb3d968589d8	6235	/@}/
Kojto	90:cb3d968589d8	6236
Kojto	90:cb3d968589d8	6237	/*
Kojto	90:cb3d968589d8	6238	* Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
Kojto	90:cb3d968589d8	6239	*/
Kojto	90:cb3d968589d8	6240
Kojto	90:cb3d968589d8	6241	/*!
Kojto	90:cb3d968589d8	6242	* @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	6243	*/
Kojto	90:cb3d968589d8	6244	/@{/
Kojto	90:cb3d968589d8	6245	#define BP_ENET_IEEE_R_ALIGN_COUNT (0U) /!< Bit position for ENET_IEEE_R_ALIGN_COUNT. /
Kojto	90:cb3d968589d8	6246	#define BM_ENET_IEEE_R_ALIGN_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_R_ALIGN_COUNT. /
Kojto	90:cb3d968589d8	6247	#define BS_ENET_IEEE_R_ALIGN_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_R_ALIGN_COUNT. /
Kojto	90:cb3d968589d8	6248
Kojto	90:cb3d968589d8	6249	/! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field. /
Kojto	90:cb3d968589d8	6250	#define BR_ENET_IEEE_R_ALIGN_COUNT(x) (HW_ENET_IEEE_R_ALIGN(x).B.COUNT)
Kojto	90:cb3d968589d8	6251	/@}/
Kojto	90:cb3d968589d8	6252
Kojto	90:cb3d968589d8	6253	/*******************************************************************************
Kojto	90:cb3d968589d8	6254	* HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
Kojto	90:cb3d968589d8	6255	******************************************************************************/
Kojto	90:cb3d968589d8	6256
Kojto	90:cb3d968589d8	6257	/*!
Kojto	90:cb3d968589d8	6258	* @brief HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
Kojto	90:cb3d968589d8	6259	*
Kojto	90:cb3d968589d8	6260	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6261	*/
Kojto	90:cb3d968589d8	6262	typedef union _hw_enet_ieee_r_macerr
Kojto	90:cb3d968589d8	6263	{
Kojto	90:cb3d968589d8	6264	uint32_t U;
Kojto	90:cb3d968589d8	6265	struct _hw_enet_ieee_r_macerr_bitfields
Kojto	90:cb3d968589d8	6266	{
Kojto	90:cb3d968589d8	6267	uint32_t COUNT : 16; /!< [15:0] Count /
Kojto	90:cb3d968589d8	6268	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	6269	} B;
Kojto	90:cb3d968589d8	6270	} hw_enet_ieee_r_macerr_t;
Kojto	90:cb3d968589d8	6271
Kojto	90:cb3d968589d8	6272	/*!
Kojto	90:cb3d968589d8	6273	* @name Constants and macros for entire ENET_IEEE_R_MACERR register
Kojto	90:cb3d968589d8	6274	*/
Kojto	90:cb3d968589d8	6275	/@{/
Kojto	90:cb3d968589d8	6276	#define HW_ENET_IEEE_R_MACERR_ADDR(x) ((x) + 0x2D8U)
Kojto	90:cb3d968589d8	6277
Kojto	90:cb3d968589d8	6278	#define HW_ENET_IEEE_R_MACERR(x) ((__I hw_enet_ieee_r_macerr_t ) HW_ENET_IEEE_R_MACERR_ADDR(x))
Kojto	90:cb3d968589d8	6279	#define HW_ENET_IEEE_R_MACERR_RD(x) (HW_ENET_IEEE_R_MACERR(x).U)
Kojto	90:cb3d968589d8	6280	/@}/
Kojto	90:cb3d968589d8	6281
Kojto	90:cb3d968589d8	6282	/*
Kojto	90:cb3d968589d8	6283	* Constants & macros for individual ENET_IEEE_R_MACERR bitfields
Kojto	90:cb3d968589d8	6284	*/
Kojto	90:cb3d968589d8	6285
Kojto	90:cb3d968589d8	6286	/*!
Kojto	90:cb3d968589d8	6287	* @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	6288	*/
Kojto	90:cb3d968589d8	6289	/@{/
Kojto	90:cb3d968589d8	6290	#define BP_ENET_IEEE_R_MACERR_COUNT (0U) /!< Bit position for ENET_IEEE_R_MACERR_COUNT. /
Kojto	90:cb3d968589d8	6291	#define BM_ENET_IEEE_R_MACERR_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_R_MACERR_COUNT. /
Kojto	90:cb3d968589d8	6292	#define BS_ENET_IEEE_R_MACERR_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_R_MACERR_COUNT. /
Kojto	90:cb3d968589d8	6293
Kojto	90:cb3d968589d8	6294	/! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field. /
Kojto	90:cb3d968589d8	6295	#define BR_ENET_IEEE_R_MACERR_COUNT(x) (HW_ENET_IEEE_R_MACERR(x).B.COUNT)
Kojto	90:cb3d968589d8	6296	/@}/
Kojto	90:cb3d968589d8	6297
Kojto	90:cb3d968589d8	6298	/*******************************************************************************
Kojto	90:cb3d968589d8	6299	* HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
Kojto	90:cb3d968589d8	6300	******************************************************************************/
Kojto	90:cb3d968589d8	6301
Kojto	90:cb3d968589d8	6302	/*!
Kojto	90:cb3d968589d8	6303	* @brief HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
Kojto	90:cb3d968589d8	6304	*
Kojto	90:cb3d968589d8	6305	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6306	*/
Kojto	90:cb3d968589d8	6307	typedef union _hw_enet_ieee_r_fdxfc
Kojto	90:cb3d968589d8	6308	{
Kojto	90:cb3d968589d8	6309	uint32_t U;
Kojto	90:cb3d968589d8	6310	struct _hw_enet_ieee_r_fdxfc_bitfields
Kojto	90:cb3d968589d8	6311	{
Kojto	90:cb3d968589d8	6312	uint32_t COUNT : 16; /!< [15:0] Pause frame count /
Kojto	90:cb3d968589d8	6313	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	6314	} B;
Kojto	90:cb3d968589d8	6315	} hw_enet_ieee_r_fdxfc_t;
Kojto	90:cb3d968589d8	6316
Kojto	90:cb3d968589d8	6317	/*!
Kojto	90:cb3d968589d8	6318	* @name Constants and macros for entire ENET_IEEE_R_FDXFC register
Kojto	90:cb3d968589d8	6319	*/
Kojto	90:cb3d968589d8	6320	/@{/
Kojto	90:cb3d968589d8	6321	#define HW_ENET_IEEE_R_FDXFC_ADDR(x) ((x) + 0x2DCU)
Kojto	90:cb3d968589d8	6322
Kojto	90:cb3d968589d8	6323	#define HW_ENET_IEEE_R_FDXFC(x) ((__I hw_enet_ieee_r_fdxfc_t ) HW_ENET_IEEE_R_FDXFC_ADDR(x))
Kojto	90:cb3d968589d8	6324	#define HW_ENET_IEEE_R_FDXFC_RD(x) (HW_ENET_IEEE_R_FDXFC(x).U)
Kojto	90:cb3d968589d8	6325	/@}/
Kojto	90:cb3d968589d8	6326
Kojto	90:cb3d968589d8	6327	/*
Kojto	90:cb3d968589d8	6328	* Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
Kojto	90:cb3d968589d8	6329	*/
Kojto	90:cb3d968589d8	6330
Kojto	90:cb3d968589d8	6331	/*!
Kojto	90:cb3d968589d8	6332	* @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
Kojto	90:cb3d968589d8	6333	*/
Kojto	90:cb3d968589d8	6334	/@{/
Kojto	90:cb3d968589d8	6335	#define BP_ENET_IEEE_R_FDXFC_COUNT (0U) /!< Bit position for ENET_IEEE_R_FDXFC_COUNT. /
Kojto	90:cb3d968589d8	6336	#define BM_ENET_IEEE_R_FDXFC_COUNT (0x0000FFFFU) /!< Bit mask for ENET_IEEE_R_FDXFC_COUNT. /
Kojto	90:cb3d968589d8	6337	#define BS_ENET_IEEE_R_FDXFC_COUNT (16U) /!< Bit field size in bits for ENET_IEEE_R_FDXFC_COUNT. /
Kojto	90:cb3d968589d8	6338
Kojto	90:cb3d968589d8	6339	/! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field. /
Kojto	90:cb3d968589d8	6340	#define BR_ENET_IEEE_R_FDXFC_COUNT(x) (HW_ENET_IEEE_R_FDXFC(x).B.COUNT)
Kojto	90:cb3d968589d8	6341	/@}/
Kojto	90:cb3d968589d8	6342
Kojto	90:cb3d968589d8	6343	/*******************************************************************************
Kojto	90:cb3d968589d8	6344	* HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
Kojto	90:cb3d968589d8	6345	******************************************************************************/
Kojto	90:cb3d968589d8	6346
Kojto	90:cb3d968589d8	6347	/*!
Kojto	90:cb3d968589d8	6348	* @brief HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
Kojto	90:cb3d968589d8	6349	*
Kojto	90:cb3d968589d8	6350	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6351	*/
Kojto	90:cb3d968589d8	6352	typedef union _hw_enet_ieee_r_octets_ok
Kojto	90:cb3d968589d8	6353	{
Kojto	90:cb3d968589d8	6354	uint32_t U;
Kojto	90:cb3d968589d8	6355	struct _hw_enet_ieee_r_octets_ok_bitfields
Kojto	90:cb3d968589d8	6356	{
Kojto	90:cb3d968589d8	6357	uint32_t COUNT : 32; /!< [31:0] Octet count /
Kojto	90:cb3d968589d8	6358	} B;
Kojto	90:cb3d968589d8	6359	} hw_enet_ieee_r_octets_ok_t;
Kojto	90:cb3d968589d8	6360
Kojto	90:cb3d968589d8	6361	/*!
Kojto	90:cb3d968589d8	6362	* @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
Kojto	90:cb3d968589d8	6363	*/
Kojto	90:cb3d968589d8	6364	/@{/
Kojto	90:cb3d968589d8	6365	#define HW_ENET_IEEE_R_OCTETS_OK_ADDR(x) ((x) + 0x2E0U)
Kojto	90:cb3d968589d8	6366
Kojto	90:cb3d968589d8	6367	#define HW_ENET_IEEE_R_OCTETS_OK(x) ((__I hw_enet_ieee_r_octets_ok_t ) HW_ENET_IEEE_R_OCTETS_OK_ADDR(x))
Kojto	90:cb3d968589d8	6368	#define HW_ENET_IEEE_R_OCTETS_OK_RD(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
Kojto	90:cb3d968589d8	6369	/@}/
Kojto	90:cb3d968589d8	6370
Kojto	90:cb3d968589d8	6371	/*
Kojto	90:cb3d968589d8	6372	* Constants & macros for individual ENET_IEEE_R_OCTETS_OK bitfields
Kojto	90:cb3d968589d8	6373	*/
Kojto	90:cb3d968589d8	6374
Kojto	90:cb3d968589d8	6375	/*!
Kojto	90:cb3d968589d8	6376	* @name Register ENET_IEEE_R_OCTETS_OK, field COUNT[31:0] (RO)
Kojto	90:cb3d968589d8	6377	*/
Kojto	90:cb3d968589d8	6378	/@{/
Kojto	90:cb3d968589d8	6379	#define BP_ENET_IEEE_R_OCTETS_OK_COUNT (0U) /!< Bit position for ENET_IEEE_R_OCTETS_OK_COUNT. /
Kojto	90:cb3d968589d8	6380	#define BM_ENET_IEEE_R_OCTETS_OK_COUNT (0xFFFFFFFFU) /!< Bit mask for ENET_IEEE_R_OCTETS_OK_COUNT. /
Kojto	90:cb3d968589d8	6381	#define BS_ENET_IEEE_R_OCTETS_OK_COUNT (32U) /!< Bit field size in bits for ENET_IEEE_R_OCTETS_OK_COUNT. /
Kojto	90:cb3d968589d8	6382
Kojto	90:cb3d968589d8	6383	/! @brief Read current value of the ENET_IEEE_R_OCTETS_OK_COUNT field. /
Kojto	90:cb3d968589d8	6384	#define BR_ENET_IEEE_R_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
Kojto	90:cb3d968589d8	6385	/@}/
Kojto	90:cb3d968589d8	6386
Kojto	90:cb3d968589d8	6387	/*******************************************************************************
Kojto	90:cb3d968589d8	6388	* HW_ENET_ATCR - Adjustable Timer Control Register
Kojto	90:cb3d968589d8	6389	******************************************************************************/
Kojto	90:cb3d968589d8	6390
Kojto	90:cb3d968589d8	6391	/*!
Kojto	90:cb3d968589d8	6392	* @brief HW_ENET_ATCR - Adjustable Timer Control Register (RW)
Kojto	90:cb3d968589d8	6393	*
Kojto	90:cb3d968589d8	6394	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6395	*
Kojto	90:cb3d968589d8	6396	* ATCR command fields can trigger the corresponding events directly. It is not
Kojto	90:cb3d968589d8	6397	* necessary to preserve any of the configuration fields when a command field is
Kojto	90:cb3d968589d8	6398	* set in the register, that is, no read-modify-write is required. The fields are
Kojto	90:cb3d968589d8	6399	* automatically cleared after the command completes.
Kojto	90:cb3d968589d8	6400	*/
Kojto	90:cb3d968589d8	6401	typedef union _hw_enet_atcr
Kojto	90:cb3d968589d8	6402	{
Kojto	90:cb3d968589d8	6403	uint32_t U;
Kojto	90:cb3d968589d8	6404	struct _hw_enet_atcr_bitfields
Kojto	90:cb3d968589d8	6405	{
Kojto	90:cb3d968589d8	6406	uint32_t EN : 1; /!< [0] Enable Timer /
Kojto	90:cb3d968589d8	6407	uint32_t RESERVED0 : 1; /!< [1] /
Kojto	90:cb3d968589d8	6408	uint32_t OFFEN : 1; /!< [2] Enable One-Shot Offset Event /
Kojto	90:cb3d968589d8	6409	uint32_t OFFRST : 1; /!< [3] Reset Timer On Offset Event /
Kojto	90:cb3d968589d8	6410	uint32_t PEREN : 1; /!< [4] Enable Periodical Event /
Kojto	90:cb3d968589d8	6411	uint32_t RESERVED1 : 2; /!< [6:5] /
Kojto	90:cb3d968589d8	6412	uint32_t PINPER : 1; /!< [7] /
Kojto	90:cb3d968589d8	6413	uint32_t RESERVED2 : 1; /!< [8] /
Kojto	90:cb3d968589d8	6414	uint32_t RESTART : 1; /!< [9] Reset Timer /
Kojto	90:cb3d968589d8	6415	uint32_t RESERVED3 : 1; /!< [10] /
Kojto	90:cb3d968589d8	6416	uint32_t CAPTURE : 1; /!< [11] Capture Timer Value /
Kojto	90:cb3d968589d8	6417	uint32_t RESERVED4 : 1; /!< [12] /
Kojto	90:cb3d968589d8	6418	uint32_t SLAVE : 1; /!< [13] Enable Timer Slave Mode /
Kojto	90:cb3d968589d8	6419	uint32_t RESERVED5 : 18; /!< [31:14] /
Kojto	90:cb3d968589d8	6420	} B;
Kojto	90:cb3d968589d8	6421	} hw_enet_atcr_t;
Kojto	90:cb3d968589d8	6422
Kojto	90:cb3d968589d8	6423	/*!
Kojto	90:cb3d968589d8	6424	* @name Constants and macros for entire ENET_ATCR register
Kojto	90:cb3d968589d8	6425	*/
Kojto	90:cb3d968589d8	6426	/@{/
Kojto	90:cb3d968589d8	6427	#define HW_ENET_ATCR_ADDR(x) ((x) + 0x400U)
Kojto	90:cb3d968589d8	6428
Kojto	90:cb3d968589d8	6429	#define HW_ENET_ATCR(x) ((__IO hw_enet_atcr_t ) HW_ENET_ATCR_ADDR(x))
Kojto	90:cb3d968589d8	6430	#define HW_ENET_ATCR_RD(x) (HW_ENET_ATCR(x).U)
Kojto	90:cb3d968589d8	6431	#define HW_ENET_ATCR_WR(x, v) (HW_ENET_ATCR(x).U = (v))
Kojto	90:cb3d968589d8	6432	#define HW_ENET_ATCR_SET(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	6433	#define HW_ENET_ATCR_CLR(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	6434	#define HW_ENET_ATCR_TOG(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	6435	/@}/
Kojto	90:cb3d968589d8	6436
Kojto	90:cb3d968589d8	6437	/*
Kojto	90:cb3d968589d8	6438	* Constants & macros for individual ENET_ATCR bitfields
Kojto	90:cb3d968589d8	6439	*/
Kojto	90:cb3d968589d8	6440
Kojto	90:cb3d968589d8	6441	/*!
Kojto	90:cb3d968589d8	6442	* @name Register ENET_ATCR, field EN[0] (RW)
Kojto	90:cb3d968589d8	6443	*
Kojto	90:cb3d968589d8	6444	* Values:
Kojto	90:cb3d968589d8	6445	* - 0 - The timer stops at the current value.
Kojto	90:cb3d968589d8	6446	* - 1 - The timer starts incrementing.
Kojto	90:cb3d968589d8	6447	*/
Kojto	90:cb3d968589d8	6448	/@{/
Kojto	90:cb3d968589d8	6449	#define BP_ENET_ATCR_EN (0U) /!< Bit position for ENET_ATCR_EN. /
Kojto	90:cb3d968589d8	6450	#define BM_ENET_ATCR_EN (0x00000001U) /!< Bit mask for ENET_ATCR_EN. /
Kojto	90:cb3d968589d8	6451	#define BS_ENET_ATCR_EN (1U) /!< Bit field size in bits for ENET_ATCR_EN. /
Kojto	90:cb3d968589d8	6452
Kojto	90:cb3d968589d8	6453	/! @brief Read current value of the ENET_ATCR_EN field. /
Kojto	90:cb3d968589d8	6454	#define BR_ENET_ATCR_EN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN))
Kojto	90:cb3d968589d8	6455
Kojto	90:cb3d968589d8	6456	/! @brief Format value for bitfield ENET_ATCR_EN. /
Kojto	90:cb3d968589d8	6457	#define BF_ENET_ATCR_EN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_EN) & BM_ENET_ATCR_EN)
Kojto	90:cb3d968589d8	6458
Kojto	90:cb3d968589d8	6459	/! @brief Set the EN field to a new value. /
Kojto	90:cb3d968589d8	6460	#define BW_ENET_ATCR_EN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN) = (v))
Kojto	90:cb3d968589d8	6461	/@}/
Kojto	90:cb3d968589d8	6462
Kojto	90:cb3d968589d8	6463	/*!
Kojto	90:cb3d968589d8	6464	* @name Register ENET_ATCR, field OFFEN[2] (RW)
Kojto	90:cb3d968589d8	6465	*
Kojto	90:cb3d968589d8	6466	* Values:
Kojto	90:cb3d968589d8	6467	* - 0 - Disable.
Kojto	90:cb3d968589d8	6468	* - 1 - The timer can be reset to zero when the given offset time is reached
Kojto	90:cb3d968589d8	6469	* (offset event). The field is cleared when the offset event is reached, so no
Kojto	90:cb3d968589d8	6470	* further event occurs until the field is set again. The timer offset value
Kojto	90:cb3d968589d8	6471	* must be set before setting this field.
Kojto	90:cb3d968589d8	6472	*/
Kojto	90:cb3d968589d8	6473	/@{/
Kojto	90:cb3d968589d8	6474	#define BP_ENET_ATCR_OFFEN (2U) /!< Bit position for ENET_ATCR_OFFEN. /
Kojto	90:cb3d968589d8	6475	#define BM_ENET_ATCR_OFFEN (0x00000004U) /!< Bit mask for ENET_ATCR_OFFEN. /
Kojto	90:cb3d968589d8	6476	#define BS_ENET_ATCR_OFFEN (1U) /!< Bit field size in bits for ENET_ATCR_OFFEN. /
Kojto	90:cb3d968589d8	6477
Kojto	90:cb3d968589d8	6478	/! @brief Read current value of the ENET_ATCR_OFFEN field. /
Kojto	90:cb3d968589d8	6479	#define BR_ENET_ATCR_OFFEN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN))
Kojto	90:cb3d968589d8	6480
Kojto	90:cb3d968589d8	6481	/! @brief Format value for bitfield ENET_ATCR_OFFEN. /
Kojto	90:cb3d968589d8	6482	#define BF_ENET_ATCR_OFFEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_OFFEN) & BM_ENET_ATCR_OFFEN)
Kojto	90:cb3d968589d8	6483
Kojto	90:cb3d968589d8	6484	/! @brief Set the OFFEN field to a new value. /
Kojto	90:cb3d968589d8	6485	#define BW_ENET_ATCR_OFFEN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN) = (v))
Kojto	90:cb3d968589d8	6486	/@}/
Kojto	90:cb3d968589d8	6487
Kojto	90:cb3d968589d8	6488	/*!
Kojto	90:cb3d968589d8	6489	* @name Register ENET_ATCR, field OFFRST[3] (RW)
Kojto	90:cb3d968589d8	6490	*
Kojto	90:cb3d968589d8	6491	* Values:
Kojto	90:cb3d968589d8	6492	* - 0 - The timer is not affected and no action occurs, besides clearing OFFEN,
Kojto	90:cb3d968589d8	6493	* when the offset is reached.
Kojto	90:cb3d968589d8	6494	* - 1 - If OFFEN is set, the timer resets to zero when the offset setting is
Kojto	90:cb3d968589d8	6495	* reached. The offset event does not cause a timer interrupt.
Kojto	90:cb3d968589d8	6496	*/
Kojto	90:cb3d968589d8	6497	/@{/
Kojto	90:cb3d968589d8	6498	#define BP_ENET_ATCR_OFFRST (3U) /!< Bit position for ENET_ATCR_OFFRST. /
Kojto	90:cb3d968589d8	6499	#define BM_ENET_ATCR_OFFRST (0x00000008U) /!< Bit mask for ENET_ATCR_OFFRST. /
Kojto	90:cb3d968589d8	6500	#define BS_ENET_ATCR_OFFRST (1U) /!< Bit field size in bits for ENET_ATCR_OFFRST. /
Kojto	90:cb3d968589d8	6501
Kojto	90:cb3d968589d8	6502	/! @brief Read current value of the ENET_ATCR_OFFRST field. /
Kojto	90:cb3d968589d8	6503	#define BR_ENET_ATCR_OFFRST(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST))
Kojto	90:cb3d968589d8	6504
Kojto	90:cb3d968589d8	6505	/! @brief Format value for bitfield ENET_ATCR_OFFRST. /
Kojto	90:cb3d968589d8	6506	#define BF_ENET_ATCR_OFFRST(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_OFFRST) & BM_ENET_ATCR_OFFRST)
Kojto	90:cb3d968589d8	6507
Kojto	90:cb3d968589d8	6508	/! @brief Set the OFFRST field to a new value. /
Kojto	90:cb3d968589d8	6509	#define BW_ENET_ATCR_OFFRST(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST) = (v))
Kojto	90:cb3d968589d8	6510	/@}/
Kojto	90:cb3d968589d8	6511
Kojto	90:cb3d968589d8	6512	/*!
Kojto	90:cb3d968589d8	6513	* @name Register ENET_ATCR, field PEREN[4] (RW)
Kojto	90:cb3d968589d8	6514	*
Kojto	90:cb3d968589d8	6515	* Values:
Kojto	90:cb3d968589d8	6516	* - 0 - Disable.
Kojto	90:cb3d968589d8	6517	* - 1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the event
Kojto	90:cb3d968589d8	6518	* signal output is asserted when the timer wraps around according to the
Kojto	90:cb3d968589d8	6519	* periodic setting ATPER. The timer period value must be set before setting
Kojto	90:cb3d968589d8	6520	* this bit. Not all devices contain the event signal output. See the chip
Kojto	90:cb3d968589d8	6521	* configuration details.
Kojto	90:cb3d968589d8	6522	*/
Kojto	90:cb3d968589d8	6523	/@{/
Kojto	90:cb3d968589d8	6524	#define BP_ENET_ATCR_PEREN (4U) /!< Bit position for ENET_ATCR_PEREN. /
Kojto	90:cb3d968589d8	6525	#define BM_ENET_ATCR_PEREN (0x00000010U) /!< Bit mask for ENET_ATCR_PEREN. /
Kojto	90:cb3d968589d8	6526	#define BS_ENET_ATCR_PEREN (1U) /!< Bit field size in bits for ENET_ATCR_PEREN. /
Kojto	90:cb3d968589d8	6527
Kojto	90:cb3d968589d8	6528	/! @brief Read current value of the ENET_ATCR_PEREN field. /
Kojto	90:cb3d968589d8	6529	#define BR_ENET_ATCR_PEREN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN))
Kojto	90:cb3d968589d8	6530
Kojto	90:cb3d968589d8	6531	/! @brief Format value for bitfield ENET_ATCR_PEREN. /
Kojto	90:cb3d968589d8	6532	#define BF_ENET_ATCR_PEREN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_PEREN) & BM_ENET_ATCR_PEREN)
Kojto	90:cb3d968589d8	6533
Kojto	90:cb3d968589d8	6534	/! @brief Set the PEREN field to a new value. /
Kojto	90:cb3d968589d8	6535	#define BW_ENET_ATCR_PEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN) = (v))
Kojto	90:cb3d968589d8	6536	/@}/
Kojto	90:cb3d968589d8	6537
Kojto	90:cb3d968589d8	6538	/*!
Kojto	90:cb3d968589d8	6539	* @name Register ENET_ATCR, field PINPER[7] (RW)
Kojto	90:cb3d968589d8	6540	*
Kojto	90:cb3d968589d8	6541	* Enables event signal output assertion on period event. Not all devices
Kojto	90:cb3d968589d8	6542	* contain the event signal output. See the chip configuration details.
Kojto	90:cb3d968589d8	6543	*
Kojto	90:cb3d968589d8	6544	* Values:
Kojto	90:cb3d968589d8	6545	* - 0 - Disable.
Kojto	90:cb3d968589d8	6546	* - 1 - Enable.
Kojto	90:cb3d968589d8	6547	*/
Kojto	90:cb3d968589d8	6548	/@{/
Kojto	90:cb3d968589d8	6549	#define BP_ENET_ATCR_PINPER (7U) /!< Bit position for ENET_ATCR_PINPER. /
Kojto	90:cb3d968589d8	6550	#define BM_ENET_ATCR_PINPER (0x00000080U) /!< Bit mask for ENET_ATCR_PINPER. /
Kojto	90:cb3d968589d8	6551	#define BS_ENET_ATCR_PINPER (1U) /!< Bit field size in bits for ENET_ATCR_PINPER. /
Kojto	90:cb3d968589d8	6552
Kojto	90:cb3d968589d8	6553	/! @brief Read current value of the ENET_ATCR_PINPER field. /
Kojto	90:cb3d968589d8	6554	#define BR_ENET_ATCR_PINPER(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER))
Kojto	90:cb3d968589d8	6555
Kojto	90:cb3d968589d8	6556	/! @brief Format value for bitfield ENET_ATCR_PINPER. /
Kojto	90:cb3d968589d8	6557	#define BF_ENET_ATCR_PINPER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_PINPER) & BM_ENET_ATCR_PINPER)
Kojto	90:cb3d968589d8	6558
Kojto	90:cb3d968589d8	6559	/! @brief Set the PINPER field to a new value. /
Kojto	90:cb3d968589d8	6560	#define BW_ENET_ATCR_PINPER(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER) = (v))
Kojto	90:cb3d968589d8	6561	/@}/
Kojto	90:cb3d968589d8	6562
Kojto	90:cb3d968589d8	6563	/*!
Kojto	90:cb3d968589d8	6564	* @name Register ENET_ATCR, field RESTART[9] (RW)
Kojto	90:cb3d968589d8	6565	*
Kojto	90:cb3d968589d8	6566	* Resets the timer to zero. This has no effect on the counter enable. If the
Kojto	90:cb3d968589d8	6567	* counter is enabled when this field is set, the timer is reset to zero and starts
Kojto	90:cb3d968589d8	6568	* counting from there. When set, all other fields are ignored during a write.
Kojto	90:cb3d968589d8	6569	*/
Kojto	90:cb3d968589d8	6570	/@{/
Kojto	90:cb3d968589d8	6571	#define BP_ENET_ATCR_RESTART (9U) /!< Bit position for ENET_ATCR_RESTART. /
Kojto	90:cb3d968589d8	6572	#define BM_ENET_ATCR_RESTART (0x00000200U) /!< Bit mask for ENET_ATCR_RESTART. /
Kojto	90:cb3d968589d8	6573	#define BS_ENET_ATCR_RESTART (1U) /!< Bit field size in bits for ENET_ATCR_RESTART. /
Kojto	90:cb3d968589d8	6574
Kojto	90:cb3d968589d8	6575	/! @brief Read current value of the ENET_ATCR_RESTART field. /
Kojto	90:cb3d968589d8	6576	#define BR_ENET_ATCR_RESTART(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART))
Kojto	90:cb3d968589d8	6577
Kojto	90:cb3d968589d8	6578	/! @brief Format value for bitfield ENET_ATCR_RESTART. /
Kojto	90:cb3d968589d8	6579	#define BF_ENET_ATCR_RESTART(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_RESTART) & BM_ENET_ATCR_RESTART)
Kojto	90:cb3d968589d8	6580
Kojto	90:cb3d968589d8	6581	/! @brief Set the RESTART field to a new value. /
Kojto	90:cb3d968589d8	6582	#define BW_ENET_ATCR_RESTART(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART) = (v))
Kojto	90:cb3d968589d8	6583	/@}/
Kojto	90:cb3d968589d8	6584
Kojto	90:cb3d968589d8	6585	/*!
Kojto	90:cb3d968589d8	6586	* @name Register ENET_ATCR, field CAPTURE[11] (RW)
Kojto	90:cb3d968589d8	6587	*
Kojto	90:cb3d968589d8	6588	* Values:
Kojto	90:cb3d968589d8	6589	* - 0 - No effect.
Kojto	90:cb3d968589d8	6590	* - 1 - The current time is captured and can be read from the ATVR register.
Kojto	90:cb3d968589d8	6591	*/
Kojto	90:cb3d968589d8	6592	/@{/
Kojto	90:cb3d968589d8	6593	#define BP_ENET_ATCR_CAPTURE (11U) /!< Bit position for ENET_ATCR_CAPTURE. /
Kojto	90:cb3d968589d8	6594	#define BM_ENET_ATCR_CAPTURE (0x00000800U) /!< Bit mask for ENET_ATCR_CAPTURE. /
Kojto	90:cb3d968589d8	6595	#define BS_ENET_ATCR_CAPTURE (1U) /!< Bit field size in bits for ENET_ATCR_CAPTURE. /
Kojto	90:cb3d968589d8	6596
Kojto	90:cb3d968589d8	6597	/! @brief Read current value of the ENET_ATCR_CAPTURE field. /
Kojto	90:cb3d968589d8	6598	#define BR_ENET_ATCR_CAPTURE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE))
Kojto	90:cb3d968589d8	6599
Kojto	90:cb3d968589d8	6600	/! @brief Format value for bitfield ENET_ATCR_CAPTURE. /
Kojto	90:cb3d968589d8	6601	#define BF_ENET_ATCR_CAPTURE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_CAPTURE) & BM_ENET_ATCR_CAPTURE)
Kojto	90:cb3d968589d8	6602
Kojto	90:cb3d968589d8	6603	/! @brief Set the CAPTURE field to a new value. /
Kojto	90:cb3d968589d8	6604	#define BW_ENET_ATCR_CAPTURE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE) = (v))
Kojto	90:cb3d968589d8	6605	/@}/
Kojto	90:cb3d968589d8	6606
Kojto	90:cb3d968589d8	6607	/*!
Kojto	90:cb3d968589d8	6608	* @name Register ENET_ATCR, field SLAVE[13] (RW)
Kojto	90:cb3d968589d8	6609	*
Kojto	90:cb3d968589d8	6610	* Values:
Kojto	90:cb3d968589d8	6611	* - 0 - The timer is active and all configuration fields in this register are
Kojto	90:cb3d968589d8	6612	* relevant.
Kojto	90:cb3d968589d8	6613	* - 1 - The internal timer is disabled and the externally provided timer value
Kojto	90:cb3d968589d8	6614	* is used. All other fields, except CAPTURE, in this register have no
Kojto	90:cb3d968589d8	6615	* effect. CAPTURE can still be used to capture the current timer value.
Kojto	90:cb3d968589d8	6616	*/
Kojto	90:cb3d968589d8	6617	/@{/
Kojto	90:cb3d968589d8	6618	#define BP_ENET_ATCR_SLAVE (13U) /!< Bit position for ENET_ATCR_SLAVE. /
Kojto	90:cb3d968589d8	6619	#define BM_ENET_ATCR_SLAVE (0x00002000U) /!< Bit mask for ENET_ATCR_SLAVE. /
Kojto	90:cb3d968589d8	6620	#define BS_ENET_ATCR_SLAVE (1U) /!< Bit field size in bits for ENET_ATCR_SLAVE. /
Kojto	90:cb3d968589d8	6621
Kojto	90:cb3d968589d8	6622	/! @brief Read current value of the ENET_ATCR_SLAVE field. /
Kojto	90:cb3d968589d8	6623	#define BR_ENET_ATCR_SLAVE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE))
Kojto	90:cb3d968589d8	6624
Kojto	90:cb3d968589d8	6625	/! @brief Format value for bitfield ENET_ATCR_SLAVE. /
Kojto	90:cb3d968589d8	6626	#define BF_ENET_ATCR_SLAVE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_SLAVE) & BM_ENET_ATCR_SLAVE)
Kojto	90:cb3d968589d8	6627
Kojto	90:cb3d968589d8	6628	/! @brief Set the SLAVE field to a new value. /
Kojto	90:cb3d968589d8	6629	#define BW_ENET_ATCR_SLAVE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE) = (v))
Kojto	90:cb3d968589d8	6630	/@}/
Kojto	90:cb3d968589d8	6631
Kojto	90:cb3d968589d8	6632	/*******************************************************************************
Kojto	90:cb3d968589d8	6633	* HW_ENET_ATVR - Timer Value Register
Kojto	90:cb3d968589d8	6634	******************************************************************************/
Kojto	90:cb3d968589d8	6635
Kojto	90:cb3d968589d8	6636	/*!
Kojto	90:cb3d968589d8	6637	* @brief HW_ENET_ATVR - Timer Value Register (RW)
Kojto	90:cb3d968589d8	6638	*
Kojto	90:cb3d968589d8	6639	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6640	*/
Kojto	90:cb3d968589d8	6641	typedef union _hw_enet_atvr
Kojto	90:cb3d968589d8	6642	{
Kojto	90:cb3d968589d8	6643	uint32_t U;
Kojto	90:cb3d968589d8	6644	struct _hw_enet_atvr_bitfields
Kojto	90:cb3d968589d8	6645	{
Kojto	90:cb3d968589d8	6646	uint32_t ATIME : 32; /!< [31:0] /
Kojto	90:cb3d968589d8	6647	} B;
Kojto	90:cb3d968589d8	6648	} hw_enet_atvr_t;
Kojto	90:cb3d968589d8	6649
Kojto	90:cb3d968589d8	6650	/*!
Kojto	90:cb3d968589d8	6651	* @name Constants and macros for entire ENET_ATVR register
Kojto	90:cb3d968589d8	6652	*/
Kojto	90:cb3d968589d8	6653	/@{/
Kojto	90:cb3d968589d8	6654	#define HW_ENET_ATVR_ADDR(x) ((x) + 0x404U)
Kojto	90:cb3d968589d8	6655
Kojto	90:cb3d968589d8	6656	#define HW_ENET_ATVR(x) ((__IO hw_enet_atvr_t ) HW_ENET_ATVR_ADDR(x))
Kojto	90:cb3d968589d8	6657	#define HW_ENET_ATVR_RD(x) (HW_ENET_ATVR(x).U)
Kojto	90:cb3d968589d8	6658	#define HW_ENET_ATVR_WR(x, v) (HW_ENET_ATVR(x).U = (v))
Kojto	90:cb3d968589d8	6659	#define HW_ENET_ATVR_SET(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	6660	#define HW_ENET_ATVR_CLR(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	6661	#define HW_ENET_ATVR_TOG(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	6662	/@}/
Kojto	90:cb3d968589d8	6663
Kojto	90:cb3d968589d8	6664	/*
Kojto	90:cb3d968589d8	6665	* Constants & macros for individual ENET_ATVR bitfields
Kojto	90:cb3d968589d8	6666	*/
Kojto	90:cb3d968589d8	6667
Kojto	90:cb3d968589d8	6668	/*!
Kojto	90:cb3d968589d8	6669	* @name Register ENET_ATVR, field ATIME[31:0] (RW)
Kojto	90:cb3d968589d8	6670	*
Kojto	90:cb3d968589d8	6671	* A write sets the timer. A read returns the last captured value. To read the
Kojto	90:cb3d968589d8	6672	* current value, issue a capture command (set ATCR[CAPTURE]) prior to reading
Kojto	90:cb3d968589d8	6673	* this register.
Kojto	90:cb3d968589d8	6674	*/
Kojto	90:cb3d968589d8	6675	/@{/
Kojto	90:cb3d968589d8	6676	#define BP_ENET_ATVR_ATIME (0U) /!< Bit position for ENET_ATVR_ATIME. /
Kojto	90:cb3d968589d8	6677	#define BM_ENET_ATVR_ATIME (0xFFFFFFFFU) /!< Bit mask for ENET_ATVR_ATIME. /
Kojto	90:cb3d968589d8	6678	#define BS_ENET_ATVR_ATIME (32U) /!< Bit field size in bits for ENET_ATVR_ATIME. /
Kojto	90:cb3d968589d8	6679
Kojto	90:cb3d968589d8	6680	/! @brief Read current value of the ENET_ATVR_ATIME field. /
Kojto	90:cb3d968589d8	6681	#define BR_ENET_ATVR_ATIME(x) (HW_ENET_ATVR(x).U)
Kojto	90:cb3d968589d8	6682
Kojto	90:cb3d968589d8	6683	/! @brief Format value for bitfield ENET_ATVR_ATIME. /
Kojto	90:cb3d968589d8	6684	#define BF_ENET_ATVR_ATIME(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATVR_ATIME) & BM_ENET_ATVR_ATIME)
Kojto	90:cb3d968589d8	6685
Kojto	90:cb3d968589d8	6686	/! @brief Set the ATIME field to a new value. /
Kojto	90:cb3d968589d8	6687	#define BW_ENET_ATVR_ATIME(x, v) (HW_ENET_ATVR_WR(x, v))
Kojto	90:cb3d968589d8	6688	/@}/
Kojto	90:cb3d968589d8	6689
Kojto	90:cb3d968589d8	6690	/*******************************************************************************
Kojto	90:cb3d968589d8	6691	* HW_ENET_ATOFF - Timer Offset Register
Kojto	90:cb3d968589d8	6692	******************************************************************************/
Kojto	90:cb3d968589d8	6693
Kojto	90:cb3d968589d8	6694	/*!
Kojto	90:cb3d968589d8	6695	* @brief HW_ENET_ATOFF - Timer Offset Register (RW)
Kojto	90:cb3d968589d8	6696	*
Kojto	90:cb3d968589d8	6697	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6698	*/
Kojto	90:cb3d968589d8	6699	typedef union _hw_enet_atoff
Kojto	90:cb3d968589d8	6700	{
Kojto	90:cb3d968589d8	6701	uint32_t U;
Kojto	90:cb3d968589d8	6702	struct _hw_enet_atoff_bitfields
Kojto	90:cb3d968589d8	6703	{
Kojto	90:cb3d968589d8	6704	uint32_t OFFSET : 32; /!< [31:0] /
Kojto	90:cb3d968589d8	6705	} B;
Kojto	90:cb3d968589d8	6706	} hw_enet_atoff_t;
Kojto	90:cb3d968589d8	6707
Kojto	90:cb3d968589d8	6708	/*!
Kojto	90:cb3d968589d8	6709	* @name Constants and macros for entire ENET_ATOFF register
Kojto	90:cb3d968589d8	6710	*/
Kojto	90:cb3d968589d8	6711	/@{/
Kojto	90:cb3d968589d8	6712	#define HW_ENET_ATOFF_ADDR(x) ((x) + 0x408U)
Kojto	90:cb3d968589d8	6713
Kojto	90:cb3d968589d8	6714	#define HW_ENET_ATOFF(x) ((__IO hw_enet_atoff_t ) HW_ENET_ATOFF_ADDR(x))
Kojto	90:cb3d968589d8	6715	#define HW_ENET_ATOFF_RD(x) (HW_ENET_ATOFF(x).U)
Kojto	90:cb3d968589d8	6716	#define HW_ENET_ATOFF_WR(x, v) (HW_ENET_ATOFF(x).U = (v))
Kojto	90:cb3d968589d8	6717	#define HW_ENET_ATOFF_SET(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) \| (v)))
Kojto	90:cb3d968589d8	6718	#define HW_ENET_ATOFF_CLR(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	6719	#define HW_ENET_ATOFF_TOG(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	6720	/@}/
Kojto	90:cb3d968589d8	6721
Kojto	90:cb3d968589d8	6722	/*
Kojto	90:cb3d968589d8	6723	* Constants & macros for individual ENET_ATOFF bitfields
Kojto	90:cb3d968589d8	6724	*/
Kojto	90:cb3d968589d8	6725
Kojto	90:cb3d968589d8	6726	/*!
Kojto	90:cb3d968589d8	6727	* @name Register ENET_ATOFF, field OFFSET[31:0] (RW)
Kojto	90:cb3d968589d8	6728	*
Kojto	90:cb3d968589d8	6729	* Offset value for one-shot event generation. When the timer reaches the value,
Kojto	90:cb3d968589d8	6730	* an event can be generated to reset the counter. If the increment value in
Kojto	90:cb3d968589d8	6731	* ATINC is given in true nanoseconds, this value is also given in true nanoseconds.
Kojto	90:cb3d968589d8	6732	*/
Kojto	90:cb3d968589d8	6733	/@{/
Kojto	90:cb3d968589d8	6734	#define BP_ENET_ATOFF_OFFSET (0U) /!< Bit position for ENET_ATOFF_OFFSET. /
Kojto	90:cb3d968589d8	6735	#define BM_ENET_ATOFF_OFFSET (0xFFFFFFFFU) /!< Bit mask for ENET_ATOFF_OFFSET. /
Kojto	90:cb3d968589d8	6736	#define BS_ENET_ATOFF_OFFSET (32U) /!< Bit field size in bits for ENET_ATOFF_OFFSET. /
Kojto	90:cb3d968589d8	6737
Kojto	90:cb3d968589d8	6738	/! @brief Read current value of the ENET_ATOFF_OFFSET field. /
Kojto	90:cb3d968589d8	6739	#define BR_ENET_ATOFF_OFFSET(x) (HW_ENET_ATOFF(x).U)
Kojto	90:cb3d968589d8	6740
Kojto	90:cb3d968589d8	6741	/! @brief Format value for bitfield ENET_ATOFF_OFFSET. /
Kojto	90:cb3d968589d8	6742	#define BF_ENET_ATOFF_OFFSET(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATOFF_OFFSET) & BM_ENET_ATOFF_OFFSET)
Kojto	90:cb3d968589d8	6743
Kojto	90:cb3d968589d8	6744	/! @brief Set the OFFSET field to a new value. /
Kojto	90:cb3d968589d8	6745	#define BW_ENET_ATOFF_OFFSET(x, v) (HW_ENET_ATOFF_WR(x, v))
Kojto	90:cb3d968589d8	6746	/@}/
Kojto	90:cb3d968589d8	6747
Kojto	90:cb3d968589d8	6748	/*******************************************************************************
Kojto	90:cb3d968589d8	6749	* HW_ENET_ATPER - Timer Period Register
Kojto	90:cb3d968589d8	6750	******************************************************************************/
Kojto	90:cb3d968589d8	6751
Kojto	90:cb3d968589d8	6752	/*!
Kojto	90:cb3d968589d8	6753	* @brief HW_ENET_ATPER - Timer Period Register (RW)
Kojto	90:cb3d968589d8	6754	*
Kojto	90:cb3d968589d8	6755	* Reset value: 0x3B9ACA00U
Kojto	90:cb3d968589d8	6756	*/
Kojto	90:cb3d968589d8	6757	typedef union _hw_enet_atper
Kojto	90:cb3d968589d8	6758	{
Kojto	90:cb3d968589d8	6759	uint32_t U;
Kojto	90:cb3d968589d8	6760	struct _hw_enet_atper_bitfields
Kojto	90:cb3d968589d8	6761	{
Kojto	90:cb3d968589d8	6762	uint32_t PERIOD : 32; /!< [31:0] /
Kojto	90:cb3d968589d8	6763	} B;
Kojto	90:cb3d968589d8	6764	} hw_enet_atper_t;
Kojto	90:cb3d968589d8	6765
Kojto	90:cb3d968589d8	6766	/*!
Kojto	90:cb3d968589d8	6767	* @name Constants and macros for entire ENET_ATPER register
Kojto	90:cb3d968589d8	6768	*/
Kojto	90:cb3d968589d8	6769	/@{/
Kojto	90:cb3d968589d8	6770	#define HW_ENET_ATPER_ADDR(x) ((x) + 0x40CU)
Kojto	90:cb3d968589d8	6771
Kojto	90:cb3d968589d8	6772	#define HW_ENET_ATPER(x) ((__IO hw_enet_atper_t ) HW_ENET_ATPER_ADDR(x))
Kojto	90:cb3d968589d8	6773	#define HW_ENET_ATPER_RD(x) (HW_ENET_ATPER(x).U)
Kojto	90:cb3d968589d8	6774	#define HW_ENET_ATPER_WR(x, v) (HW_ENET_ATPER(x).U = (v))
Kojto	90:cb3d968589d8	6775	#define HW_ENET_ATPER_SET(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) \| (v)))
Kojto	90:cb3d968589d8	6776	#define HW_ENET_ATPER_CLR(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	6777	#define HW_ENET_ATPER_TOG(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	6778	/@}/
Kojto	90:cb3d968589d8	6779
Kojto	90:cb3d968589d8	6780	/*
Kojto	90:cb3d968589d8	6781	* Constants & macros for individual ENET_ATPER bitfields
Kojto	90:cb3d968589d8	6782	*/
Kojto	90:cb3d968589d8	6783
Kojto	90:cb3d968589d8	6784	/*!
Kojto	90:cb3d968589d8	6785	* @name Register ENET_ATPER, field PERIOD[31:0] (RW)
Kojto	90:cb3d968589d8	6786	*
Kojto	90:cb3d968589d8	6787	* Value for generating periodic events. Each instance the timer reaches this
Kojto	90:cb3d968589d8	6788	* value, the period event occurs and the timer restarts. If the increment value in
Kojto	90:cb3d968589d8	6789	* ATINC is given in true nanoseconds, this value is also given in true
Kojto	90:cb3d968589d8	6790	* nanoseconds. The value should be initialized to 1,000,000,000 (1 x 10 9 ) to represent
Kojto	90:cb3d968589d8	6791	* a timer wrap around of one second. The increment value set in ATINC should be
Kojto	90:cb3d968589d8	6792	* set to the true nanoseconds of the period of clock ts_clk, hence implementing
Kojto	90:cb3d968589d8	6793	* a true 1 second counter.
Kojto	90:cb3d968589d8	6794	*/
Kojto	90:cb3d968589d8	6795	/@{/
Kojto	90:cb3d968589d8	6796	#define BP_ENET_ATPER_PERIOD (0U) /!< Bit position for ENET_ATPER_PERIOD. /
Kojto	90:cb3d968589d8	6797	#define BM_ENET_ATPER_PERIOD (0xFFFFFFFFU) /!< Bit mask for ENET_ATPER_PERIOD. /
Kojto	90:cb3d968589d8	6798	#define BS_ENET_ATPER_PERIOD (32U) /!< Bit field size in bits for ENET_ATPER_PERIOD. /
Kojto	90:cb3d968589d8	6799
Kojto	90:cb3d968589d8	6800	/! @brief Read current value of the ENET_ATPER_PERIOD field. /
Kojto	90:cb3d968589d8	6801	#define BR_ENET_ATPER_PERIOD(x) (HW_ENET_ATPER(x).U)
Kojto	90:cb3d968589d8	6802
Kojto	90:cb3d968589d8	6803	/! @brief Format value for bitfield ENET_ATPER_PERIOD. /
Kojto	90:cb3d968589d8	6804	#define BF_ENET_ATPER_PERIOD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATPER_PERIOD) & BM_ENET_ATPER_PERIOD)
Kojto	90:cb3d968589d8	6805
Kojto	90:cb3d968589d8	6806	/! @brief Set the PERIOD field to a new value. /
Kojto	90:cb3d968589d8	6807	#define BW_ENET_ATPER_PERIOD(x, v) (HW_ENET_ATPER_WR(x, v))
Kojto	90:cb3d968589d8	6808	/@}/
Kojto	90:cb3d968589d8	6809
Kojto	90:cb3d968589d8	6810	/*******************************************************************************
Kojto	90:cb3d968589d8	6811	* HW_ENET_ATCOR - Timer Correction Register
Kojto	90:cb3d968589d8	6812	******************************************************************************/
Kojto	90:cb3d968589d8	6813
Kojto	90:cb3d968589d8	6814	/*!
Kojto	90:cb3d968589d8	6815	* @brief HW_ENET_ATCOR - Timer Correction Register (RW)
Kojto	90:cb3d968589d8	6816	*
Kojto	90:cb3d968589d8	6817	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6818	*/
Kojto	90:cb3d968589d8	6819	typedef union _hw_enet_atcor
Kojto	90:cb3d968589d8	6820	{
Kojto	90:cb3d968589d8	6821	uint32_t U;
Kojto	90:cb3d968589d8	6822	struct _hw_enet_atcor_bitfields
Kojto	90:cb3d968589d8	6823	{
Kojto	90:cb3d968589d8	6824	uint32_t COR : 31; /!< [30:0] Correction Counter Wrap-Around Value /
Kojto	90:cb3d968589d8	6825	uint32_t RESERVED0 : 1; /!< [31] /
Kojto	90:cb3d968589d8	6826	} B;
Kojto	90:cb3d968589d8	6827	} hw_enet_atcor_t;
Kojto	90:cb3d968589d8	6828
Kojto	90:cb3d968589d8	6829	/*!
Kojto	90:cb3d968589d8	6830	* @name Constants and macros for entire ENET_ATCOR register
Kojto	90:cb3d968589d8	6831	*/
Kojto	90:cb3d968589d8	6832	/@{/
Kojto	90:cb3d968589d8	6833	#define HW_ENET_ATCOR_ADDR(x) ((x) + 0x410U)
Kojto	90:cb3d968589d8	6834
Kojto	90:cb3d968589d8	6835	#define HW_ENET_ATCOR(x) ((__IO hw_enet_atcor_t ) HW_ENET_ATCOR_ADDR(x))
Kojto	90:cb3d968589d8	6836	#define HW_ENET_ATCOR_RD(x) (HW_ENET_ATCOR(x).U)
Kojto	90:cb3d968589d8	6837	#define HW_ENET_ATCOR_WR(x, v) (HW_ENET_ATCOR(x).U = (v))
Kojto	90:cb3d968589d8	6838	#define HW_ENET_ATCOR_SET(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	6839	#define HW_ENET_ATCOR_CLR(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	6840	#define HW_ENET_ATCOR_TOG(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	6841	/@}/
Kojto	90:cb3d968589d8	6842
Kojto	90:cb3d968589d8	6843	/*
Kojto	90:cb3d968589d8	6844	* Constants & macros for individual ENET_ATCOR bitfields
Kojto	90:cb3d968589d8	6845	*/
Kojto	90:cb3d968589d8	6846
Kojto	90:cb3d968589d8	6847	/*!
Kojto	90:cb3d968589d8	6848	* @name Register ENET_ATCOR, field COR[30:0] (RW)
Kojto	90:cb3d968589d8	6849	*
Kojto	90:cb3d968589d8	6850	* Defines after how many timer clock cycles (ts_clk) the correction counter
Kojto	90:cb3d968589d8	6851	* should be reset and trigger a correction increment on the timer. The amount of
Kojto	90:cb3d968589d8	6852	* correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
Kojto	90:cb3d968589d8	6853	* counter and no corrections occur. This value is given in clock cycles, not in
Kojto	90:cb3d968589d8	6854	* nanoseconds as all other values.
Kojto	90:cb3d968589d8	6855	*/
Kojto	90:cb3d968589d8	6856	/@{/
Kojto	90:cb3d968589d8	6857	#define BP_ENET_ATCOR_COR (0U) /!< Bit position for ENET_ATCOR_COR. /
Kojto	90:cb3d968589d8	6858	#define BM_ENET_ATCOR_COR (0x7FFFFFFFU) /!< Bit mask for ENET_ATCOR_COR. /
Kojto	90:cb3d968589d8	6859	#define BS_ENET_ATCOR_COR (31U) /!< Bit field size in bits for ENET_ATCOR_COR. /
Kojto	90:cb3d968589d8	6860
Kojto	90:cb3d968589d8	6861	/! @brief Read current value of the ENET_ATCOR_COR field. /
Kojto	90:cb3d968589d8	6862	#define BR_ENET_ATCOR_COR(x) (HW_ENET_ATCOR(x).B.COR)
Kojto	90:cb3d968589d8	6863
Kojto	90:cb3d968589d8	6864	/! @brief Format value for bitfield ENET_ATCOR_COR. /
Kojto	90:cb3d968589d8	6865	#define BF_ENET_ATCOR_COR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCOR_COR) & BM_ENET_ATCOR_COR)
Kojto	90:cb3d968589d8	6866
Kojto	90:cb3d968589d8	6867	/! @brief Set the COR field to a new value. /
Kojto	90:cb3d968589d8	6868	#define BW_ENET_ATCOR_COR(x, v) (HW_ENET_ATCOR_WR(x, (HW_ENET_ATCOR_RD(x) & ~BM_ENET_ATCOR_COR) \| BF_ENET_ATCOR_COR(v)))
Kojto	90:cb3d968589d8	6869	/@}/
Kojto	90:cb3d968589d8	6870
Kojto	90:cb3d968589d8	6871	/*******************************************************************************
Kojto	90:cb3d968589d8	6872	* HW_ENET_ATINC - Time-Stamping Clock Period Register
Kojto	90:cb3d968589d8	6873	******************************************************************************/
Kojto	90:cb3d968589d8	6874
Kojto	90:cb3d968589d8	6875	/*!
Kojto	90:cb3d968589d8	6876	* @brief HW_ENET_ATINC - Time-Stamping Clock Period Register (RW)
Kojto	90:cb3d968589d8	6877	*
Kojto	90:cb3d968589d8	6878	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6879	*/
Kojto	90:cb3d968589d8	6880	typedef union _hw_enet_atinc
Kojto	90:cb3d968589d8	6881	{
Kojto	90:cb3d968589d8	6882	uint32_t U;
Kojto	90:cb3d968589d8	6883	struct _hw_enet_atinc_bitfields
Kojto	90:cb3d968589d8	6884	{
Kojto	90:cb3d968589d8	6885	uint32_t INC : 7; /*!< [6:0] Clock Period Of The Timestamping Clock
Kojto	90:cb3d968589d8	6886	* (ts_clk) In Nanoseconds */
Kojto	90:cb3d968589d8	6887	uint32_t RESERVED0 : 1; /!< [7] /
Kojto	90:cb3d968589d8	6888	uint32_t INC_CORR : 7; /!< [14:8] Correction Increment Value /
Kojto	90:cb3d968589d8	6889	uint32_t RESERVED1 : 17; /!< [31:15] /
Kojto	90:cb3d968589d8	6890	} B;
Kojto	90:cb3d968589d8	6891	} hw_enet_atinc_t;
Kojto	90:cb3d968589d8	6892
Kojto	90:cb3d968589d8	6893	/*!
Kojto	90:cb3d968589d8	6894	* @name Constants and macros for entire ENET_ATINC register
Kojto	90:cb3d968589d8	6895	*/
Kojto	90:cb3d968589d8	6896	/@{/
Kojto	90:cb3d968589d8	6897	#define HW_ENET_ATINC_ADDR(x) ((x) + 0x414U)
Kojto	90:cb3d968589d8	6898
Kojto	90:cb3d968589d8	6899	#define HW_ENET_ATINC(x) ((__IO hw_enet_atinc_t ) HW_ENET_ATINC_ADDR(x))
Kojto	90:cb3d968589d8	6900	#define HW_ENET_ATINC_RD(x) (HW_ENET_ATINC(x).U)
Kojto	90:cb3d968589d8	6901	#define HW_ENET_ATINC_WR(x, v) (HW_ENET_ATINC(x).U = (v))
Kojto	90:cb3d968589d8	6902	#define HW_ENET_ATINC_SET(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) \| (v)))
Kojto	90:cb3d968589d8	6903	#define HW_ENET_ATINC_CLR(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	6904	#define HW_ENET_ATINC_TOG(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	6905	/@}/
Kojto	90:cb3d968589d8	6906
Kojto	90:cb3d968589d8	6907	/*
Kojto	90:cb3d968589d8	6908	* Constants & macros for individual ENET_ATINC bitfields
Kojto	90:cb3d968589d8	6909	*/
Kojto	90:cb3d968589d8	6910
Kojto	90:cb3d968589d8	6911	/*!
Kojto	90:cb3d968589d8	6912	* @name Register ENET_ATINC, field INC[6:0] (RW)
Kojto	90:cb3d968589d8	6913	*
Kojto	90:cb3d968589d8	6914	* The timer increments by this amount each clock cycle. For example, set to 10
Kojto	90:cb3d968589d8	6915	* for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
Kojto	90:cb3d968589d8	6916	* that is an integer fraction of the period set in ATPER.
Kojto	90:cb3d968589d8	6917	*/
Kojto	90:cb3d968589d8	6918	/@{/
Kojto	90:cb3d968589d8	6919	#define BP_ENET_ATINC_INC (0U) /!< Bit position for ENET_ATINC_INC. /
Kojto	90:cb3d968589d8	6920	#define BM_ENET_ATINC_INC (0x0000007FU) /!< Bit mask for ENET_ATINC_INC. /
Kojto	90:cb3d968589d8	6921	#define BS_ENET_ATINC_INC (7U) /!< Bit field size in bits for ENET_ATINC_INC. /
Kojto	90:cb3d968589d8	6922
Kojto	90:cb3d968589d8	6923	/! @brief Read current value of the ENET_ATINC_INC field. /
Kojto	90:cb3d968589d8	6924	#define BR_ENET_ATINC_INC(x) (HW_ENET_ATINC(x).B.INC)
Kojto	90:cb3d968589d8	6925
Kojto	90:cb3d968589d8	6926	/! @brief Format value for bitfield ENET_ATINC_INC. /
Kojto	90:cb3d968589d8	6927	#define BF_ENET_ATINC_INC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATINC_INC) & BM_ENET_ATINC_INC)
Kojto	90:cb3d968589d8	6928
Kojto	90:cb3d968589d8	6929	/! @brief Set the INC field to a new value. /
Kojto	90:cb3d968589d8	6930	#define BW_ENET_ATINC_INC(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC) \| BF_ENET_ATINC_INC(v)))
Kojto	90:cb3d968589d8	6931	/@}/
Kojto	90:cb3d968589d8	6932
Kojto	90:cb3d968589d8	6933	/*!
Kojto	90:cb3d968589d8	6934	* @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
Kojto	90:cb3d968589d8	6935	*
Kojto	90:cb3d968589d8	6936	* This value is added every time the correction timer expires (every clock
Kojto	90:cb3d968589d8	6937	* cycle given in ATCOR). A value less than INC slows down the timer. A value greater
Kojto	90:cb3d968589d8	6938	* than INC speeds up the timer.
Kojto	90:cb3d968589d8	6939	*/
Kojto	90:cb3d968589d8	6940	/@{/
Kojto	90:cb3d968589d8	6941	#define BP_ENET_ATINC_INC_CORR (8U) /!< Bit position for ENET_ATINC_INC_CORR. /
Kojto	90:cb3d968589d8	6942	#define BM_ENET_ATINC_INC_CORR (0x00007F00U) /!< Bit mask for ENET_ATINC_INC_CORR. /
Kojto	90:cb3d968589d8	6943	#define BS_ENET_ATINC_INC_CORR (7U) /!< Bit field size in bits for ENET_ATINC_INC_CORR. /
Kojto	90:cb3d968589d8	6944
Kojto	90:cb3d968589d8	6945	/! @brief Read current value of the ENET_ATINC_INC_CORR field. /
Kojto	90:cb3d968589d8	6946	#define BR_ENET_ATINC_INC_CORR(x) (HW_ENET_ATINC(x).B.INC_CORR)
Kojto	90:cb3d968589d8	6947
Kojto	90:cb3d968589d8	6948	/! @brief Format value for bitfield ENET_ATINC_INC_CORR. /
Kojto	90:cb3d968589d8	6949	#define BF_ENET_ATINC_INC_CORR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATINC_INC_CORR) & BM_ENET_ATINC_INC_CORR)
Kojto	90:cb3d968589d8	6950
Kojto	90:cb3d968589d8	6951	/! @brief Set the INC_CORR field to a new value. /
Kojto	90:cb3d968589d8	6952	#define BW_ENET_ATINC_INC_CORR(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC_CORR) \| BF_ENET_ATINC_INC_CORR(v)))
Kojto	90:cb3d968589d8	6953	/@}/
Kojto	90:cb3d968589d8	6954
Kojto	90:cb3d968589d8	6955	/*******************************************************************************
Kojto	90:cb3d968589d8	6956	* HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
Kojto	90:cb3d968589d8	6957	******************************************************************************/
Kojto	90:cb3d968589d8	6958
Kojto	90:cb3d968589d8	6959	/*!
Kojto	90:cb3d968589d8	6960	* @brief HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
Kojto	90:cb3d968589d8	6961	*
Kojto	90:cb3d968589d8	6962	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	6963	*/
Kojto	90:cb3d968589d8	6964	typedef union _hw_enet_atstmp
Kojto	90:cb3d968589d8	6965	{
Kojto	90:cb3d968589d8	6966	uint32_t U;
Kojto	90:cb3d968589d8	6967	struct _hw_enet_atstmp_bitfields
Kojto	90:cb3d968589d8	6968	{
Kojto	90:cb3d968589d8	6969	uint32_t TIMESTAMP : 32; /!< [31:0] /
Kojto	90:cb3d968589d8	6970	} B;
Kojto	90:cb3d968589d8	6971	} hw_enet_atstmp_t;
Kojto	90:cb3d968589d8	6972
Kojto	90:cb3d968589d8	6973	/*!
Kojto	90:cb3d968589d8	6974	* @name Constants and macros for entire ENET_ATSTMP register
Kojto	90:cb3d968589d8	6975	*/
Kojto	90:cb3d968589d8	6976	/@{/
Kojto	90:cb3d968589d8	6977	#define HW_ENET_ATSTMP_ADDR(x) ((x) + 0x418U)
Kojto	90:cb3d968589d8	6978
Kojto	90:cb3d968589d8	6979	#define HW_ENET_ATSTMP(x) ((__I hw_enet_atstmp_t ) HW_ENET_ATSTMP_ADDR(x))
Kojto	90:cb3d968589d8	6980	#define HW_ENET_ATSTMP_RD(x) (HW_ENET_ATSTMP(x).U)
Kojto	90:cb3d968589d8	6981	/@}/
Kojto	90:cb3d968589d8	6982
Kojto	90:cb3d968589d8	6983	/*
Kojto	90:cb3d968589d8	6984	* Constants & macros for individual ENET_ATSTMP bitfields
Kojto	90:cb3d968589d8	6985	*/
Kojto	90:cb3d968589d8	6986
Kojto	90:cb3d968589d8	6987	/*!
Kojto	90:cb3d968589d8	6988	* @name Register ENET_ATSTMP, field TIMESTAMP[31:0] (RO)
Kojto	90:cb3d968589d8	6989	*
Kojto	90:cb3d968589d8	6990	* Timestamp of the last frame transmitted by the core that had TxBD[TS] set .
Kojto	90:cb3d968589d8	6991	* This register is only valid when EIR[TS_AVAIL] is set.
Kojto	90:cb3d968589d8	6992	*/
Kojto	90:cb3d968589d8	6993	/@{/
Kojto	90:cb3d968589d8	6994	#define BP_ENET_ATSTMP_TIMESTAMP (0U) /!< Bit position for ENET_ATSTMP_TIMESTAMP. /
Kojto	90:cb3d968589d8	6995	#define BM_ENET_ATSTMP_TIMESTAMP (0xFFFFFFFFU) /!< Bit mask for ENET_ATSTMP_TIMESTAMP. /
Kojto	90:cb3d968589d8	6996	#define BS_ENET_ATSTMP_TIMESTAMP (32U) /!< Bit field size in bits for ENET_ATSTMP_TIMESTAMP. /
Kojto	90:cb3d968589d8	6997
Kojto	90:cb3d968589d8	6998	/! @brief Read current value of the ENET_ATSTMP_TIMESTAMP field. /
Kojto	90:cb3d968589d8	6999	#define BR_ENET_ATSTMP_TIMESTAMP(x) (HW_ENET_ATSTMP(x).U)
Kojto	90:cb3d968589d8	7000	/@}/
Kojto	90:cb3d968589d8	7001
Kojto	90:cb3d968589d8	7002	/*******************************************************************************
Kojto	90:cb3d968589d8	7003	* HW_ENET_TGSR - Timer Global Status Register
Kojto	90:cb3d968589d8	7004	******************************************************************************/
Kojto	90:cb3d968589d8	7005
Kojto	90:cb3d968589d8	7006	/*!
Kojto	90:cb3d968589d8	7007	* @brief HW_ENET_TGSR - Timer Global Status Register (RW)
Kojto	90:cb3d968589d8	7008	*
Kojto	90:cb3d968589d8	7009	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	7010	*/
Kojto	90:cb3d968589d8	7011	typedef union _hw_enet_tgsr
Kojto	90:cb3d968589d8	7012	{
Kojto	90:cb3d968589d8	7013	uint32_t U;
Kojto	90:cb3d968589d8	7014	struct _hw_enet_tgsr_bitfields
Kojto	90:cb3d968589d8	7015	{
Kojto	90:cb3d968589d8	7016	uint32_t TF0 : 1; /!< [0] Copy Of Timer Flag For Channel 0 /
Kojto	90:cb3d968589d8	7017	uint32_t TF1 : 1; /!< [1] Copy Of Timer Flag For Channel 1 /
Kojto	90:cb3d968589d8	7018	uint32_t TF2 : 1; /!< [2] Copy Of Timer Flag For Channel 2 /
Kojto	90:cb3d968589d8	7019	uint32_t TF3 : 1; /!< [3] Copy Of Timer Flag For Channel 3 /
Kojto	90:cb3d968589d8	7020	uint32_t RESERVED0 : 28; /!< [31:4] /
Kojto	90:cb3d968589d8	7021	} B;
Kojto	90:cb3d968589d8	7022	} hw_enet_tgsr_t;
Kojto	90:cb3d968589d8	7023
Kojto	90:cb3d968589d8	7024	/*!
Kojto	90:cb3d968589d8	7025	* @name Constants and macros for entire ENET_TGSR register
Kojto	90:cb3d968589d8	7026	*/
Kojto	90:cb3d968589d8	7027	/@{/
Kojto	90:cb3d968589d8	7028	#define HW_ENET_TGSR_ADDR(x) ((x) + 0x604U)
Kojto	90:cb3d968589d8	7029
Kojto	90:cb3d968589d8	7030	#define HW_ENET_TGSR(x) ((__IO hw_enet_tgsr_t ) HW_ENET_TGSR_ADDR(x))
Kojto	90:cb3d968589d8	7031	#define HW_ENET_TGSR_RD(x) (HW_ENET_TGSR(x).U)
Kojto	90:cb3d968589d8	7032	#define HW_ENET_TGSR_WR(x, v) (HW_ENET_TGSR(x).U = (v))
Kojto	90:cb3d968589d8	7033	#define HW_ENET_TGSR_SET(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	7034	#define HW_ENET_TGSR_CLR(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	7035	#define HW_ENET_TGSR_TOG(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	7036	/@}/
Kojto	90:cb3d968589d8	7037
Kojto	90:cb3d968589d8	7038	/*
Kojto	90:cb3d968589d8	7039	* Constants & macros for individual ENET_TGSR bitfields
Kojto	90:cb3d968589d8	7040	*/
Kojto	90:cb3d968589d8	7041
Kojto	90:cb3d968589d8	7042	/*!
Kojto	90:cb3d968589d8	7043	* @name Register ENET_TGSR, field TF0[0] (W1C)
Kojto	90:cb3d968589d8	7044	*
Kojto	90:cb3d968589d8	7045	* Values:
Kojto	90:cb3d968589d8	7046	* - 0 - Timer Flag for Channel 0 is clear
Kojto	90:cb3d968589d8	7047	* - 1 - Timer Flag for Channel 0 is set
Kojto	90:cb3d968589d8	7048	*/
Kojto	90:cb3d968589d8	7049	/@{/
Kojto	90:cb3d968589d8	7050	#define BP_ENET_TGSR_TF0 (0U) /!< Bit position for ENET_TGSR_TF0. /
Kojto	90:cb3d968589d8	7051	#define BM_ENET_TGSR_TF0 (0x00000001U) /!< Bit mask for ENET_TGSR_TF0. /
Kojto	90:cb3d968589d8	7052	#define BS_ENET_TGSR_TF0 (1U) /!< Bit field size in bits for ENET_TGSR_TF0. /
Kojto	90:cb3d968589d8	7053
Kojto	90:cb3d968589d8	7054	/! @brief Read current value of the ENET_TGSR_TF0 field. /
Kojto	90:cb3d968589d8	7055	#define BR_ENET_TGSR_TF0(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0))
Kojto	90:cb3d968589d8	7056
Kojto	90:cb3d968589d8	7057	/! @brief Format value for bitfield ENET_TGSR_TF0. /
Kojto	90:cb3d968589d8	7058	#define BF_ENET_TGSR_TF0(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF0) & BM_ENET_TGSR_TF0)
Kojto	90:cb3d968589d8	7059
Kojto	90:cb3d968589d8	7060	/! @brief Set the TF0 field to a new value. /
Kojto	90:cb3d968589d8	7061	#define BW_ENET_TGSR_TF0(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0) = (v))
Kojto	90:cb3d968589d8	7062	/@}/
Kojto	90:cb3d968589d8	7063
Kojto	90:cb3d968589d8	7064	/*!
Kojto	90:cb3d968589d8	7065	* @name Register ENET_TGSR, field TF1[1] (W1C)
Kojto	90:cb3d968589d8	7066	*
Kojto	90:cb3d968589d8	7067	* Values:
Kojto	90:cb3d968589d8	7068	* - 0 - Timer Flag for Channel 1 is clear
Kojto	90:cb3d968589d8	7069	* - 1 - Timer Flag for Channel 1 is set
Kojto	90:cb3d968589d8	7070	*/
Kojto	90:cb3d968589d8	7071	/@{/
Kojto	90:cb3d968589d8	7072	#define BP_ENET_TGSR_TF1 (1U) /!< Bit position for ENET_TGSR_TF1. /
Kojto	90:cb3d968589d8	7073	#define BM_ENET_TGSR_TF1 (0x00000002U) /!< Bit mask for ENET_TGSR_TF1. /
Kojto	90:cb3d968589d8	7074	#define BS_ENET_TGSR_TF1 (1U) /!< Bit field size in bits for ENET_TGSR_TF1. /
Kojto	90:cb3d968589d8	7075
Kojto	90:cb3d968589d8	7076	/! @brief Read current value of the ENET_TGSR_TF1 field. /
Kojto	90:cb3d968589d8	7077	#define BR_ENET_TGSR_TF1(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1))
Kojto	90:cb3d968589d8	7078
Kojto	90:cb3d968589d8	7079	/! @brief Format value for bitfield ENET_TGSR_TF1. /
Kojto	90:cb3d968589d8	7080	#define BF_ENET_TGSR_TF1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF1) & BM_ENET_TGSR_TF1)
Kojto	90:cb3d968589d8	7081
Kojto	90:cb3d968589d8	7082	/! @brief Set the TF1 field to a new value. /
Kojto	90:cb3d968589d8	7083	#define BW_ENET_TGSR_TF1(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1) = (v))
Kojto	90:cb3d968589d8	7084	/@}/
Kojto	90:cb3d968589d8	7085
Kojto	90:cb3d968589d8	7086	/*!
Kojto	90:cb3d968589d8	7087	* @name Register ENET_TGSR, field TF2[2] (W1C)
Kojto	90:cb3d968589d8	7088	*
Kojto	90:cb3d968589d8	7089	* Values:
Kojto	90:cb3d968589d8	7090	* - 0 - Timer Flag for Channel 2 is clear
Kojto	90:cb3d968589d8	7091	* - 1 - Timer Flag for Channel 2 is set
Kojto	90:cb3d968589d8	7092	*/
Kojto	90:cb3d968589d8	7093	/@{/
Kojto	90:cb3d968589d8	7094	#define BP_ENET_TGSR_TF2 (2U) /!< Bit position for ENET_TGSR_TF2. /
Kojto	90:cb3d968589d8	7095	#define BM_ENET_TGSR_TF2 (0x00000004U) /!< Bit mask for ENET_TGSR_TF2. /
Kojto	90:cb3d968589d8	7096	#define BS_ENET_TGSR_TF2 (1U) /!< Bit field size in bits for ENET_TGSR_TF2. /
Kojto	90:cb3d968589d8	7097
Kojto	90:cb3d968589d8	7098	/! @brief Read current value of the ENET_TGSR_TF2 field. /
Kojto	90:cb3d968589d8	7099	#define BR_ENET_TGSR_TF2(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2))
Kojto	90:cb3d968589d8	7100
Kojto	90:cb3d968589d8	7101	/! @brief Format value for bitfield ENET_TGSR_TF2. /
Kojto	90:cb3d968589d8	7102	#define BF_ENET_TGSR_TF2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF2) & BM_ENET_TGSR_TF2)
Kojto	90:cb3d968589d8	7103
Kojto	90:cb3d968589d8	7104	/! @brief Set the TF2 field to a new value. /
Kojto	90:cb3d968589d8	7105	#define BW_ENET_TGSR_TF2(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2) = (v))
Kojto	90:cb3d968589d8	7106	/@}/
Kojto	90:cb3d968589d8	7107
Kojto	90:cb3d968589d8	7108	/*!
Kojto	90:cb3d968589d8	7109	* @name Register ENET_TGSR, field TF3[3] (W1C)
Kojto	90:cb3d968589d8	7110	*
Kojto	90:cb3d968589d8	7111	* Values:
Kojto	90:cb3d968589d8	7112	* - 0 - Timer Flag for Channel 3 is clear
Kojto	90:cb3d968589d8	7113	* - 1 - Timer Flag for Channel 3 is set
Kojto	90:cb3d968589d8	7114	*/
Kojto	90:cb3d968589d8	7115	/@{/
Kojto	90:cb3d968589d8	7116	#define BP_ENET_TGSR_TF3 (3U) /!< Bit position for ENET_TGSR_TF3. /
Kojto	90:cb3d968589d8	7117	#define BM_ENET_TGSR_TF3 (0x00000008U) /!< Bit mask for ENET_TGSR_TF3. /
Kojto	90:cb3d968589d8	7118	#define BS_ENET_TGSR_TF3 (1U) /!< Bit field size in bits for ENET_TGSR_TF3. /
Kojto	90:cb3d968589d8	7119
Kojto	90:cb3d968589d8	7120	/! @brief Read current value of the ENET_TGSR_TF3 field. /
Kojto	90:cb3d968589d8	7121	#define BR_ENET_TGSR_TF3(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3))
Kojto	90:cb3d968589d8	7122
Kojto	90:cb3d968589d8	7123	/! @brief Format value for bitfield ENET_TGSR_TF3. /
Kojto	90:cb3d968589d8	7124	#define BF_ENET_TGSR_TF3(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF3) & BM_ENET_TGSR_TF3)
Kojto	90:cb3d968589d8	7125
Kojto	90:cb3d968589d8	7126	/! @brief Set the TF3 field to a new value. /
Kojto	90:cb3d968589d8	7127	#define BW_ENET_TGSR_TF3(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3) = (v))
Kojto	90:cb3d968589d8	7128	/@}/
Kojto	90:cb3d968589d8	7129
Kojto	90:cb3d968589d8	7130	/*******************************************************************************
Kojto	90:cb3d968589d8	7131	* HW_ENET_TCSRn - Timer Control Status Register
Kojto	90:cb3d968589d8	7132	******************************************************************************/
Kojto	90:cb3d968589d8	7133
Kojto	90:cb3d968589d8	7134	/*!
Kojto	90:cb3d968589d8	7135	* @brief HW_ENET_TCSRn - Timer Control Status Register (RW)
Kojto	90:cb3d968589d8	7136	*
Kojto	90:cb3d968589d8	7137	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	7138	*/
Kojto	90:cb3d968589d8	7139	typedef union _hw_enet_tcsrn
Kojto	90:cb3d968589d8	7140	{
Kojto	90:cb3d968589d8	7141	uint32_t U;
Kojto	90:cb3d968589d8	7142	struct _hw_enet_tcsrn_bitfields
Kojto	90:cb3d968589d8	7143	{
Kojto	90:cb3d968589d8	7144	uint32_t TDRE : 1; /!< [0] Timer DMA Request Enable /
Kojto	90:cb3d968589d8	7145	uint32_t RESERVED0 : 1; /!< [1] /
Kojto	90:cb3d968589d8	7146	uint32_t TMODE : 4; /!< [5:2] Timer Mode /
Kojto	90:cb3d968589d8	7147	uint32_t TIE : 1; /!< [6] Timer Interrupt Enable /
Kojto	90:cb3d968589d8	7148	uint32_t TF : 1; /!< [7] Timer Flag /
Kojto	90:cb3d968589d8	7149	uint32_t RESERVED1 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	7150	} B;
Kojto	90:cb3d968589d8	7151	} hw_enet_tcsrn_t;
Kojto	90:cb3d968589d8	7152
Kojto	90:cb3d968589d8	7153	/*!
Kojto	90:cb3d968589d8	7154	* @name Constants and macros for entire ENET_TCSRn register
Kojto	90:cb3d968589d8	7155	*/
Kojto	90:cb3d968589d8	7156	/@{/
Kojto	90:cb3d968589d8	7157	#define HW_ENET_TCSRn_COUNT (4U)
Kojto	90:cb3d968589d8	7158
Kojto	90:cb3d968589d8	7159	#define HW_ENET_TCSRn_ADDR(x, n) ((x) + 0x608U + (0x8U * (n)))
Kojto	90:cb3d968589d8	7160
Kojto	90:cb3d968589d8	7161	#define HW_ENET_TCSRn(x, n) ((__IO hw_enet_tcsrn_t ) HW_ENET_TCSRn_ADDR(x, n))
Kojto	90:cb3d968589d8	7162	#define HW_ENET_TCSRn_RD(x, n) (HW_ENET_TCSRn(x, n).U)
Kojto	90:cb3d968589d8	7163	#define HW_ENET_TCSRn_WR(x, n, v) (HW_ENET_TCSRn(x, n).U = (v))
Kojto	90:cb3d968589d8	7164	#define HW_ENET_TCSRn_SET(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	7165	#define HW_ENET_TCSRn_CLR(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	7166	#define HW_ENET_TCSRn_TOG(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	7167	/@}/
Kojto	90:cb3d968589d8	7168
Kojto	90:cb3d968589d8	7169	/*
Kojto	90:cb3d968589d8	7170	* Constants & macros for individual ENET_TCSRn bitfields
Kojto	90:cb3d968589d8	7171	*/
Kojto	90:cb3d968589d8	7172
Kojto	90:cb3d968589d8	7173	/*!
Kojto	90:cb3d968589d8	7174	* @name Register ENET_TCSRn, field TDRE[0] (RW)
Kojto	90:cb3d968589d8	7175	*
Kojto	90:cb3d968589d8	7176	* Values:
Kojto	90:cb3d968589d8	7177	* - 0 - DMA request is disabled
Kojto	90:cb3d968589d8	7178	* - 1 - DMA request is enabled
Kojto	90:cb3d968589d8	7179	*/
Kojto	90:cb3d968589d8	7180	/@{/
Kojto	90:cb3d968589d8	7181	#define BP_ENET_TCSRn_TDRE (0U) /!< Bit position for ENET_TCSRn_TDRE. /
Kojto	90:cb3d968589d8	7182	#define BM_ENET_TCSRn_TDRE (0x00000001U) /!< Bit mask for ENET_TCSRn_TDRE. /
Kojto	90:cb3d968589d8	7183	#define BS_ENET_TCSRn_TDRE (1U) /!< Bit field size in bits for ENET_TCSRn_TDRE. /
Kojto	90:cb3d968589d8	7184
Kojto	90:cb3d968589d8	7185	/! @brief Read current value of the ENET_TCSRn_TDRE field. /
Kojto	90:cb3d968589d8	7186	#define BR_ENET_TCSRn_TDRE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE))
Kojto	90:cb3d968589d8	7187
Kojto	90:cb3d968589d8	7188	/! @brief Format value for bitfield ENET_TCSRn_TDRE. /
Kojto	90:cb3d968589d8	7189	#define BF_ENET_TCSRn_TDRE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TDRE) & BM_ENET_TCSRn_TDRE)
Kojto	90:cb3d968589d8	7190
Kojto	90:cb3d968589d8	7191	/! @brief Set the TDRE field to a new value. /
Kojto	90:cb3d968589d8	7192	#define BW_ENET_TCSRn_TDRE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE) = (v))
Kojto	90:cb3d968589d8	7193	/@}/
Kojto	90:cb3d968589d8	7194
Kojto	90:cb3d968589d8	7195	/*!
Kojto	90:cb3d968589d8	7196	* @name Register ENET_TCSRn, field TMODE[5:2] (RW)
Kojto	90:cb3d968589d8	7197	*
Kojto	90:cb3d968589d8	7198	* Updating the Timer Mode field takes a few cycles to register because it is
Kojto	90:cb3d968589d8	7199	* synchronized to the 1588 clock. The version of Timer Mode returned on a read is
Kojto	90:cb3d968589d8	7200	* from the 1588 clock domain. When changing Timer Mode, always disable the
Kojto	90:cb3d968589d8	7201	* channel and read this register to verify the channel is disabled first.
Kojto	90:cb3d968589d8	7202	*
Kojto	90:cb3d968589d8	7203	* Values:
Kojto	90:cb3d968589d8	7204	* - 0000 - Timer Channel is disabled.
Kojto	90:cb3d968589d8	7205	* - 0001 - Timer Channel is configured for Input Capture on rising edge
Kojto	90:cb3d968589d8	7206	* - 0010 - Timer Channel is configured for Input Capture on falling edge
Kojto	90:cb3d968589d8	7207	* - 0011 - Timer Channel is configured for Input Capture on both edges
Kojto	90:cb3d968589d8	7208	* - 0100 - Timer Channel is configured for Output Compare - software only
Kojto	90:cb3d968589d8	7209	* - 0101 - Timer Channel is configured for Output Compare - toggle output on
Kojto	90:cb3d968589d8	7210	* compare
Kojto	90:cb3d968589d8	7211	* - 0110 - Timer Channel is configured for Output Compare - clear output on
Kojto	90:cb3d968589d8	7212	* compare
Kojto	90:cb3d968589d8	7213	* - 0111 - Timer Channel is configured for Output Compare - set output on
Kojto	90:cb3d968589d8	7214	* compare
Kojto	90:cb3d968589d8	7215	* - 1000 - Reserved
Kojto	90:cb3d968589d8	7216	* - 1010 - Timer Channel is configured for Output Compare - clear output on
Kojto	90:cb3d968589d8	7217	* compare, set output on overflow
Kojto	90:cb3d968589d8	7218	* - 10x1 - Timer Channel is configured for Output Compare - set output on
Kojto	90:cb3d968589d8	7219	* compare, clear output on overflow
Kojto	90:cb3d968589d8	7220	* - 1100 - Reserved
Kojto	90:cb3d968589d8	7221	* - 1110 - Timer Channel is configured for Output Compare - pulse output low on
Kojto	90:cb3d968589d8	7222	* compare for one 1588 clock cycle
Kojto	90:cb3d968589d8	7223	* - 1111 - Timer Channel is configured for Output Compare - pulse output high
Kojto	90:cb3d968589d8	7224	* on compare for one 1588 clock cycle
Kojto	90:cb3d968589d8	7225	*/
Kojto	90:cb3d968589d8	7226	/@{/
Kojto	90:cb3d968589d8	7227	#define BP_ENET_TCSRn_TMODE (2U) /!< Bit position for ENET_TCSRn_TMODE. /
Kojto	90:cb3d968589d8	7228	#define BM_ENET_TCSRn_TMODE (0x0000003CU) /!< Bit mask for ENET_TCSRn_TMODE. /
Kojto	90:cb3d968589d8	7229	#define BS_ENET_TCSRn_TMODE (4U) /!< Bit field size in bits for ENET_TCSRn_TMODE. /
Kojto	90:cb3d968589d8	7230
Kojto	90:cb3d968589d8	7231	/! @brief Read current value of the ENET_TCSRn_TMODE field. /
Kojto	90:cb3d968589d8	7232	#define BR_ENET_TCSRn_TMODE(x, n) (HW_ENET_TCSRn(x, n).B.TMODE)
Kojto	90:cb3d968589d8	7233
Kojto	90:cb3d968589d8	7234	/! @brief Format value for bitfield ENET_TCSRn_TMODE. /
Kojto	90:cb3d968589d8	7235	#define BF_ENET_TCSRn_TMODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TMODE) & BM_ENET_TCSRn_TMODE)
Kojto	90:cb3d968589d8	7236
Kojto	90:cb3d968589d8	7237	/! @brief Set the TMODE field to a new value. /
Kojto	90:cb3d968589d8	7238	#define BW_ENET_TCSRn_TMODE(x, n, v) (HW_ENET_TCSRn_WR(x, n, (HW_ENET_TCSRn_RD(x, n) & ~BM_ENET_TCSRn_TMODE) \| BF_ENET_TCSRn_TMODE(v)))
Kojto	90:cb3d968589d8	7239	/@}/
Kojto	90:cb3d968589d8	7240
Kojto	90:cb3d968589d8	7241	/*!
Kojto	90:cb3d968589d8	7242	* @name Register ENET_TCSRn, field TIE[6] (RW)
Kojto	90:cb3d968589d8	7243	*
Kojto	90:cb3d968589d8	7244	* Values:
Kojto	90:cb3d968589d8	7245	* - 0 - Interrupt is disabled
Kojto	90:cb3d968589d8	7246	* - 1 - Interrupt is enabled
Kojto	90:cb3d968589d8	7247	*/
Kojto	90:cb3d968589d8	7248	/@{/
Kojto	90:cb3d968589d8	7249	#define BP_ENET_TCSRn_TIE (6U) /!< Bit position for ENET_TCSRn_TIE. /
Kojto	90:cb3d968589d8	7250	#define BM_ENET_TCSRn_TIE (0x00000040U) /!< Bit mask for ENET_TCSRn_TIE. /
Kojto	90:cb3d968589d8	7251	#define BS_ENET_TCSRn_TIE (1U) /!< Bit field size in bits for ENET_TCSRn_TIE. /
Kojto	90:cb3d968589d8	7252
Kojto	90:cb3d968589d8	7253	/! @brief Read current value of the ENET_TCSRn_TIE field. /
Kojto	90:cb3d968589d8	7254	#define BR_ENET_TCSRn_TIE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE))
Kojto	90:cb3d968589d8	7255
Kojto	90:cb3d968589d8	7256	/! @brief Format value for bitfield ENET_TCSRn_TIE. /
Kojto	90:cb3d968589d8	7257	#define BF_ENET_TCSRn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TIE) & BM_ENET_TCSRn_TIE)
Kojto	90:cb3d968589d8	7258
Kojto	90:cb3d968589d8	7259	/! @brief Set the TIE field to a new value. /
Kojto	90:cb3d968589d8	7260	#define BW_ENET_TCSRn_TIE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE) = (v))
Kojto	90:cb3d968589d8	7261	/@}/
Kojto	90:cb3d968589d8	7262
Kojto	90:cb3d968589d8	7263	/*!
Kojto	90:cb3d968589d8	7264	* @name Register ENET_TCSRn, field TF[7] (W1C)
Kojto	90:cb3d968589d8	7265	*
Kojto	90:cb3d968589d8	7266	* Sets when input capture or output compare occurs. This flag is double
Kojto	90:cb3d968589d8	7267	* buffered between the module clock and 1588 clock domains. When this field is 1, it
Kojto	90:cb3d968589d8	7268	* can be cleared to 0 by writing 1 to it.
Kojto	90:cb3d968589d8	7269	*
Kojto	90:cb3d968589d8	7270	* Values:
Kojto	90:cb3d968589d8	7271	* - 0 - Input Capture or Output Compare has not occurred
Kojto	90:cb3d968589d8	7272	* - 1 - Input Capture or Output Compare has occurred
Kojto	90:cb3d968589d8	7273	*/
Kojto	90:cb3d968589d8	7274	/@{/
Kojto	90:cb3d968589d8	7275	#define BP_ENET_TCSRn_TF (7U) /!< Bit position for ENET_TCSRn_TF. /
Kojto	90:cb3d968589d8	7276	#define BM_ENET_TCSRn_TF (0x00000080U) /!< Bit mask for ENET_TCSRn_TF. /
Kojto	90:cb3d968589d8	7277	#define BS_ENET_TCSRn_TF (1U) /!< Bit field size in bits for ENET_TCSRn_TF. /
Kojto	90:cb3d968589d8	7278
Kojto	90:cb3d968589d8	7279	/! @brief Read current value of the ENET_TCSRn_TF field. /
Kojto	90:cb3d968589d8	7280	#define BR_ENET_TCSRn_TF(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF))
Kojto	90:cb3d968589d8	7281
Kojto	90:cb3d968589d8	7282	/! @brief Format value for bitfield ENET_TCSRn_TF. /
Kojto	90:cb3d968589d8	7283	#define BF_ENET_TCSRn_TF(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TF) & BM_ENET_TCSRn_TF)
Kojto	90:cb3d968589d8	7284
Kojto	90:cb3d968589d8	7285	/! @brief Set the TF field to a new value. /
Kojto	90:cb3d968589d8	7286	#define BW_ENET_TCSRn_TF(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF) = (v))
Kojto	90:cb3d968589d8	7287	/@}/
Kojto	90:cb3d968589d8	7288	/*******************************************************************************
Kojto	90:cb3d968589d8	7289	* HW_ENET_TCCRn - Timer Compare Capture Register
Kojto	90:cb3d968589d8	7290	******************************************************************************/
Kojto	90:cb3d968589d8	7291
Kojto	90:cb3d968589d8	7292	/*!
Kojto	90:cb3d968589d8	7293	* @brief HW_ENET_TCCRn - Timer Compare Capture Register (RW)
Kojto	90:cb3d968589d8	7294	*
Kojto	90:cb3d968589d8	7295	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	7296	*/
Kojto	90:cb3d968589d8	7297	typedef union _hw_enet_tccrn
Kojto	90:cb3d968589d8	7298	{
Kojto	90:cb3d968589d8	7299	uint32_t U;
Kojto	90:cb3d968589d8	7300	struct _hw_enet_tccrn_bitfields
Kojto	90:cb3d968589d8	7301	{
Kojto	90:cb3d968589d8	7302	uint32_t TCC : 32; /!< [31:0] Timer Capture Compare /
Kojto	90:cb3d968589d8	7303	} B;
Kojto	90:cb3d968589d8	7304	} hw_enet_tccrn_t;
Kojto	90:cb3d968589d8	7305
Kojto	90:cb3d968589d8	7306	/*!
Kojto	90:cb3d968589d8	7307	* @name Constants and macros for entire ENET_TCCRn register
Kojto	90:cb3d968589d8	7308	*/
Kojto	90:cb3d968589d8	7309	/@{/
Kojto	90:cb3d968589d8	7310	#define HW_ENET_TCCRn_COUNT (4U)
Kojto	90:cb3d968589d8	7311
Kojto	90:cb3d968589d8	7312	#define HW_ENET_TCCRn_ADDR(x, n) ((x) + 0x60CU + (0x8U * (n)))
Kojto	90:cb3d968589d8	7313
Kojto	90:cb3d968589d8	7314	#define HW_ENET_TCCRn(x, n) ((__IO hw_enet_tccrn_t ) HW_ENET_TCCRn_ADDR(x, n))
Kojto	90:cb3d968589d8	7315	#define HW_ENET_TCCRn_RD(x, n) (HW_ENET_TCCRn(x, n).U)
Kojto	90:cb3d968589d8	7316	#define HW_ENET_TCCRn_WR(x, n, v) (HW_ENET_TCCRn(x, n).U = (v))
Kojto	90:cb3d968589d8	7317	#define HW_ENET_TCCRn_SET(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	7318	#define HW_ENET_TCCRn_CLR(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	7319	#define HW_ENET_TCCRn_TOG(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	7320	/@}/
Kojto	90:cb3d968589d8	7321
Kojto	90:cb3d968589d8	7322	/*
Kojto	90:cb3d968589d8	7323	* Constants & macros for individual ENET_TCCRn bitfields
Kojto	90:cb3d968589d8	7324	*/
Kojto	90:cb3d968589d8	7325
Kojto	90:cb3d968589d8	7326	/*!
Kojto	90:cb3d968589d8	7327	* @name Register ENET_TCCRn, field TCC[31:0] (RW)
Kojto	90:cb3d968589d8	7328	*
Kojto	90:cb3d968589d8	7329	* This register is double buffered between the module clock and 1588 clock
Kojto	90:cb3d968589d8	7330	* domains. When configured for compare, the 1588 clock domain updates with the value
Kojto	90:cb3d968589d8	7331	* in the module clock domain whenever the Timer Channel is first enabled and on
Kojto	90:cb3d968589d8	7332	* each subsequent compare. Write to this register with the first compare value
Kojto	90:cb3d968589d8	7333	* before enabling the Timer Channel. When the Timer Channel is enabled, write
Kojto	90:cb3d968589d8	7334	* the second compare value either immediately, or at least before the first
Kojto	90:cb3d968589d8	7335	* compare occurs. After each compare, write the next compare value before the previous
Kojto	90:cb3d968589d8	7336	* compare occurs and before clearing the Timer Flag. The compare occurs one
Kojto	90:cb3d968589d8	7337	* 1588 clock cycle after the IEEE 1588 Counter increments past the compare value in
Kojto	90:cb3d968589d8	7338	* the 1588 clock domain. If the compare value is less than the value of the
Kojto	90:cb3d968589d8	7339	* 1588 Counter when the Timer Channel is first enabled, then the compare does not
Kojto	90:cb3d968589d8	7340	* occur until following the next overflow of the 1588 Counter. If the compare
Kojto	90:cb3d968589d8	7341	* value is greater than the IEEE 1588 Counter when the 1588 Counter overflows, or
Kojto	90:cb3d968589d8	7342	* the compare value is less than the value of the IEEE 1588 Counter after the
Kojto	90:cb3d968589d8	7343	* overflow, then the compare occurs one 1588 clock cycle following the overflow.
Kojto	90:cb3d968589d8	7344	* When configured for Capture, the value of the IEEE 1588 Counter is captured into
Kojto	90:cb3d968589d8	7345	* the 1588 clock domain and then updated into the module clock domain, provided
Kojto	90:cb3d968589d8	7346	* the Timer Flag is clear. Always read the capture value before clearing the
Kojto	90:cb3d968589d8	7347	* Timer Flag.
Kojto	90:cb3d968589d8	7348	*/
Kojto	90:cb3d968589d8	7349	/@{/
Kojto	90:cb3d968589d8	7350	#define BP_ENET_TCCRn_TCC (0U) /!< Bit position for ENET_TCCRn_TCC. /
Kojto	90:cb3d968589d8	7351	#define BM_ENET_TCCRn_TCC (0xFFFFFFFFU) /!< Bit mask for ENET_TCCRn_TCC. /
Kojto	90:cb3d968589d8	7352	#define BS_ENET_TCCRn_TCC (32U) /!< Bit field size in bits for ENET_TCCRn_TCC. /
Kojto	90:cb3d968589d8	7353
Kojto	90:cb3d968589d8	7354	/! @brief Read current value of the ENET_TCCRn_TCC field. /
Kojto	90:cb3d968589d8	7355	#define BR_ENET_TCCRn_TCC(x, n) (HW_ENET_TCCRn(x, n).U)
Kojto	90:cb3d968589d8	7356
Kojto	90:cb3d968589d8	7357	/! @brief Format value for bitfield ENET_TCCRn_TCC. /
Kojto	90:cb3d968589d8	7358	#define BF_ENET_TCCRn_TCC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCCRn_TCC) & BM_ENET_TCCRn_TCC)
Kojto	90:cb3d968589d8	7359
Kojto	90:cb3d968589d8	7360	/! @brief Set the TCC field to a new value. /
Kojto	90:cb3d968589d8	7361	#define BW_ENET_TCCRn_TCC(x, n, v) (HW_ENET_TCCRn_WR(x, n, v))
Kojto	90:cb3d968589d8	7362	/@}/
Kojto	90:cb3d968589d8	7363
Kojto	90:cb3d968589d8	7364	/*******************************************************************************
Kojto	90:cb3d968589d8	7365	* hw_enet_t - module struct
Kojto	90:cb3d968589d8	7366	******************************************************************************/
Kojto	90:cb3d968589d8	7367	/*!
Kojto	90:cb3d968589d8	7368	* @brief All ENET module registers.
Kojto	90:cb3d968589d8	7369	*/
Kojto	90:cb3d968589d8	7370	#pragma pack(1)
Kojto	90:cb3d968589d8	7371	typedef struct _hw_enet
Kojto	90:cb3d968589d8	7372	{
Kojto	90:cb3d968589d8	7373	uint8_t _reserved0[4];
Kojto	90:cb3d968589d8	7374	__IO hw_enet_eir_t EIR; /!< [0x4] Interrupt Event Register /
Kojto	90:cb3d968589d8	7375	__IO hw_enet_eimr_t EIMR; /!< [0x8] Interrupt Mask Register /
Kojto	90:cb3d968589d8	7376	uint8_t _reserved1[4];
Kojto	90:cb3d968589d8	7377	__IO hw_enet_rdar_t RDAR; /!< [0x10] Receive Descriptor Active Register /
Kojto	90:cb3d968589d8	7378	__IO hw_enet_tdar_t TDAR; /!< [0x14] Transmit Descriptor Active Register /
Kojto	90:cb3d968589d8	7379	uint8_t _reserved2[12];
Kojto	90:cb3d968589d8	7380	__IO hw_enet_ecr_t ECR; /!< [0x24] Ethernet Control Register /
Kojto	90:cb3d968589d8	7381	uint8_t _reserved3[24];
Kojto	90:cb3d968589d8	7382	__IO hw_enet_mmfr_t MMFR; /!< [0x40] MII Management Frame Register /
Kojto	90:cb3d968589d8	7383	__IO hw_enet_mscr_t MSCR; /!< [0x44] MII Speed Control Register /
Kojto	90:cb3d968589d8	7384	uint8_t _reserved4[28];
Kojto	90:cb3d968589d8	7385	__IO hw_enet_mibc_t MIBC; /!< [0x64] MIB Control Register /
Kojto	90:cb3d968589d8	7386	uint8_t _reserved5[28];
Kojto	90:cb3d968589d8	7387	__IO hw_enet_rcr_t RCR; /!< [0x84] Receive Control Register /
Kojto	90:cb3d968589d8	7388	uint8_t _reserved6[60];
Kojto	90:cb3d968589d8	7389	__IO hw_enet_tcr_t TCR; /!< [0xC4] Transmit Control Register /
Kojto	90:cb3d968589d8	7390	uint8_t _reserved7[28];
Kojto	90:cb3d968589d8	7391	__IO hw_enet_palr_t PALR; /!< [0xE4] Physical Address Lower Register /
Kojto	90:cb3d968589d8	7392	__IO hw_enet_paur_t PAUR; /!< [0xE8] Physical Address Upper Register /
Kojto	90:cb3d968589d8	7393	__IO hw_enet_opd_t OPD; /!< [0xEC] Opcode/Pause Duration Register /
Kojto	90:cb3d968589d8	7394	uint8_t _reserved8[40];
Kojto	90:cb3d968589d8	7395	__IO hw_enet_iaur_t IAUR; /!< [0x118] Descriptor Individual Upper Address Register /
Kojto	90:cb3d968589d8	7396	__IO hw_enet_ialr_t IALR; /!< [0x11C] Descriptor Individual Lower Address Register /
Kojto	90:cb3d968589d8	7397	__IO hw_enet_gaur_t GAUR; /!< [0x120] Descriptor Group Upper Address Register /
Kojto	90:cb3d968589d8	7398	__IO hw_enet_galr_t GALR; /!< [0x124] Descriptor Group Lower Address Register /
Kojto	90:cb3d968589d8	7399	uint8_t _reserved9[28];
Kojto	90:cb3d968589d8	7400	__IO hw_enet_tfwr_t TFWR; /!< [0x144] Transmit FIFO Watermark Register /
Kojto	90:cb3d968589d8	7401	uint8_t _reserved10[56];
Kojto	90:cb3d968589d8	7402	__IO hw_enet_rdsr_t RDSR; /!< [0x180] Receive Descriptor Ring Start Register /
Kojto	90:cb3d968589d8	7403	__IO hw_enet_tdsr_t TDSR; /!< [0x184] Transmit Buffer Descriptor Ring Start Register /
Kojto	90:cb3d968589d8	7404	__IO hw_enet_mrbr_t MRBR; /!< [0x188] Maximum Receive Buffer Size Register /
Kojto	90:cb3d968589d8	7405	uint8_t _reserved11[4];
Kojto	90:cb3d968589d8	7406	__IO hw_enet_rsfl_t RSFL; /!< [0x190] Receive FIFO Section Full Threshold /
Kojto	90:cb3d968589d8	7407	__IO hw_enet_rsem_t RSEM; /!< [0x194] Receive FIFO Section Empty Threshold /
Kojto	90:cb3d968589d8	7408	__IO hw_enet_raem_t RAEM; /!< [0x198] Receive FIFO Almost Empty Threshold /
Kojto	90:cb3d968589d8	7409	__IO hw_enet_rafl_t RAFL; /!< [0x19C] Receive FIFO Almost Full Threshold /
Kojto	90:cb3d968589d8	7410	__IO hw_enet_tsem_t TSEM; /!< [0x1A0] Transmit FIFO Section Empty Threshold /
Kojto	90:cb3d968589d8	7411	__IO hw_enet_taem_t TAEM; /!< [0x1A4] Transmit FIFO Almost Empty Threshold /
Kojto	90:cb3d968589d8	7412	__IO hw_enet_tafl_t TAFL; /!< [0x1A8] Transmit FIFO Almost Full Threshold /
Kojto	90:cb3d968589d8	7413	__IO hw_enet_tipg_t TIPG; /!< [0x1AC] Transmit Inter-Packet Gap /
Kojto	90:cb3d968589d8	7414	__IO hw_enet_ftrl_t FTRL; /!< [0x1B0] Frame Truncation Length /
Kojto	90:cb3d968589d8	7415	uint8_t _reserved12[12];
Kojto	90:cb3d968589d8	7416	__IO hw_enet_tacc_t TACC; /!< [0x1C0] Transmit Accelerator Function Configuration /
Kojto	90:cb3d968589d8	7417	__IO hw_enet_racc_t RACC; /!< [0x1C4] Receive Accelerator Function Configuration /
Kojto	90:cb3d968589d8	7418	uint8_t _reserved13[60];
Kojto	90:cb3d968589d8	7419	__I hw_enet_rmon_t_packets_t RMON_T_PACKETS; /!< [0x204] Tx Packet Count Statistic Register /
Kojto	90:cb3d968589d8	7420	__I hw_enet_rmon_t_bc_pkt_t RMON_T_BC_PKT; /!< [0x208] Tx Broadcast Packets Statistic Register /
Kojto	90:cb3d968589d8	7421	__I hw_enet_rmon_t_mc_pkt_t RMON_T_MC_PKT; /!< [0x20C] Tx Multicast Packets Statistic Register /
Kojto	90:cb3d968589d8	7422	__I hw_enet_rmon_t_crc_align_t RMON_T_CRC_ALIGN; /!< [0x210] Tx Packets with CRC/Align Error Statistic Register /
Kojto	90:cb3d968589d8	7423	__I hw_enet_rmon_t_undersize_t RMON_T_UNDERSIZE; /!< [0x214] Tx Packets Less Than Bytes and Good CRC Statistic Register /
Kojto	90:cb3d968589d8	7424	__I hw_enet_rmon_t_oversize_t RMON_T_OVERSIZE; /!< [0x218] Tx Packets GT MAX_FL bytes and Good CRC Statistic Register /
Kojto	90:cb3d968589d8	7425	__I hw_enet_rmon_t_frag_t RMON_T_FRAG; /!< [0x21C] Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register /
Kojto	90:cb3d968589d8	7426	__I hw_enet_rmon_t_jab_t RMON_T_JAB; /!< [0x220] Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register /
Kojto	90:cb3d968589d8	7427	__I hw_enet_rmon_t_col_t RMON_T_COL; /!< [0x224] Tx Collision Count Statistic Register /
Kojto	90:cb3d968589d8	7428	__I hw_enet_rmon_t_p64_t RMON_T_P64; /!< [0x228] Tx 64-Byte Packets Statistic Register /
Kojto	90:cb3d968589d8	7429	__I hw_enet_rmon_t_p65to127_t RMON_T_P65TO127; /!< [0x22C] Tx 65- to 127-byte Packets Statistic Register /
Kojto	90:cb3d968589d8	7430	__I hw_enet_rmon_t_p128to255_t RMON_T_P128TO255; /!< [0x230] Tx 128- to 255-byte Packets Statistic Register /
Kojto	90:cb3d968589d8	7431	__I hw_enet_rmon_t_p256to511_t RMON_T_P256TO511; /!< [0x234] Tx 256- to 511-byte Packets Statistic Register /
Kojto	90:cb3d968589d8	7432	__I hw_enet_rmon_t_p512to1023_t RMON_T_P512TO1023; /!< [0x238] Tx 512- to 1023-byte Packets Statistic Register /
Kojto	90:cb3d968589d8	7433	__I hw_enet_rmon_t_p1024to2047_t RMON_T_P1024TO2047; /!< [0x23C] Tx 1024- to 2047-byte Packets Statistic Register /
Kojto	90:cb3d968589d8	7434	__I hw_enet_rmon_t_p_gte2048_t RMON_T_P_GTE2048; /!< [0x240] Tx Packets Greater Than 2048 Bytes Statistic Register /
Kojto	90:cb3d968589d8	7435	__I hw_enet_rmon_t_octets_t RMON_T_OCTETS; /!< [0x244] Tx Octets Statistic Register /
Kojto	90:cb3d968589d8	7436	uint8_t _reserved14[4];
Kojto	90:cb3d968589d8	7437	__I hw_enet_ieee_t_frame_ok_t IEEE_T_FRAME_OK; /!< [0x24C] Frames Transmitted OK Statistic Register /
Kojto	90:cb3d968589d8	7438	__I hw_enet_ieee_t_1col_t IEEE_T_1COL; /!< [0x250] Frames Transmitted with Single Collision Statistic Register /
Kojto	90:cb3d968589d8	7439	__I hw_enet_ieee_t_mcol_t IEEE_T_MCOL; /!< [0x254] Frames Transmitted with Multiple Collisions Statistic Register /
Kojto	90:cb3d968589d8	7440	__I hw_enet_ieee_t_def_t IEEE_T_DEF; /!< [0x258] Frames Transmitted after Deferral Delay Statistic Register /
Kojto	90:cb3d968589d8	7441	__I hw_enet_ieee_t_lcol_t IEEE_T_LCOL; /!< [0x25C] Frames Transmitted with Late Collision Statistic Register /
Kojto	90:cb3d968589d8	7442	__I hw_enet_ieee_t_excol_t IEEE_T_EXCOL; /!< [0x260] Frames Transmitted with Excessive Collisions Statistic Register /
Kojto	90:cb3d968589d8	7443	__I hw_enet_ieee_t_macerr_t IEEE_T_MACERR; /!< [0x264] Frames Transmitted with Tx FIFO Underrun Statistic Register /
Kojto	90:cb3d968589d8	7444	__I hw_enet_ieee_t_cserr_t IEEE_T_CSERR; /!< [0x268] Frames Transmitted with Carrier Sense Error Statistic Register /
Kojto	90:cb3d968589d8	7445	uint8_t _reserved15[4];
Kojto	90:cb3d968589d8	7446	__I hw_enet_ieee_t_fdxfc_t IEEE_T_FDXFC; /!< [0x270] Flow Control Pause Frames Transmitted Statistic Register /
Kojto	90:cb3d968589d8	7447	__I hw_enet_ieee_t_octets_ok_t IEEE_T_OCTETS_OK; /!< [0x274] Octet Count for Frames Transmitted w/o Error Statistic Register /
Kojto	90:cb3d968589d8	7448	uint8_t _reserved16[12];
Kojto	90:cb3d968589d8	7449	__I hw_enet_rmon_r_packets_t RMON_R_PACKETS; /!< [0x284] Rx Packet Count Statistic Register /
Kojto	90:cb3d968589d8	7450	__I hw_enet_rmon_r_bc_pkt_t RMON_R_BC_PKT; /!< [0x288] Rx Broadcast Packets Statistic Register /
Kojto	90:cb3d968589d8	7451	__I hw_enet_rmon_r_mc_pkt_t RMON_R_MC_PKT; /!< [0x28C] Rx Multicast Packets Statistic Register /
Kojto	90:cb3d968589d8	7452	__I hw_enet_rmon_r_crc_align_t RMON_R_CRC_ALIGN; /!< [0x290] Rx Packets with CRC/Align Error Statistic Register /
Kojto	90:cb3d968589d8	7453	__I hw_enet_rmon_r_undersize_t RMON_R_UNDERSIZE; /!< [0x294] Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register /
Kojto	90:cb3d968589d8	7454	__I hw_enet_rmon_r_oversize_t RMON_R_OVERSIZE; /!< [0x298] Rx Packets Greater Than MAX_FL and Good CRC Statistic Register /
Kojto	90:cb3d968589d8	7455	__I hw_enet_rmon_r_frag_t RMON_R_FRAG; /!< [0x29C] Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register /
Kojto	90:cb3d968589d8	7456	__I hw_enet_rmon_r_jab_t RMON_R_JAB; /!< [0x2A0] Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register /
Kojto	90:cb3d968589d8	7457	uint8_t _reserved17[4];
Kojto	90:cb3d968589d8	7458	__I hw_enet_rmon_r_p64_t RMON_R_P64; /!< [0x2A8] Rx 64-Byte Packets Statistic Register /
Kojto	90:cb3d968589d8	7459	__I hw_enet_rmon_r_p65to127_t RMON_R_P65TO127; /!< [0x2AC] Rx 65- to 127-Byte Packets Statistic Register /
Kojto	90:cb3d968589d8	7460	__I hw_enet_rmon_r_p128to255_t RMON_R_P128TO255; /!< [0x2B0] Rx 128- to 255-Byte Packets Statistic Register /
Kojto	90:cb3d968589d8	7461	__I hw_enet_rmon_r_p256to511_t RMON_R_P256TO511; /!< [0x2B4] Rx 256- to 511-Byte Packets Statistic Register /
Kojto	90:cb3d968589d8	7462	__I hw_enet_rmon_r_p512to1023_t RMON_R_P512TO1023; /!< [0x2B8] Rx 512- to 1023-Byte Packets Statistic Register /
Kojto	90:cb3d968589d8	7463	__I hw_enet_rmon_r_p1024to2047_t RMON_R_P1024TO2047; /!< [0x2BC] Rx 1024- to 2047-Byte Packets Statistic Register /
Kojto	90:cb3d968589d8	7464	__I hw_enet_rmon_r_p_gte2048_t RMON_R_P_GTE2048; /!< [0x2C0] Rx Packets Greater than 2048 Bytes Statistic Register /
Kojto	90:cb3d968589d8	7465	__I hw_enet_rmon_r_octets_t RMON_R_OCTETS; /!< [0x2C4] Rx Octets Statistic Register /
Kojto	90:cb3d968589d8	7466	__I hw_enet_ieee_r_drop_t IEEE_R_DROP; /!< [0x2C8] Frames not Counted Correctly Statistic Register /
Kojto	90:cb3d968589d8	7467	__I hw_enet_ieee_r_frame_ok_t IEEE_R_FRAME_OK; /!< [0x2CC] Frames Received OK Statistic Register /
Kojto	90:cb3d968589d8	7468	__I hw_enet_ieee_r_crc_t IEEE_R_CRC; /!< [0x2D0] Frames Received with CRC Error Statistic Register /
Kojto	90:cb3d968589d8	7469	__I hw_enet_ieee_r_align_t IEEE_R_ALIGN; /!< [0x2D4] Frames Received with Alignment Error Statistic Register /
Kojto	90:cb3d968589d8	7470	__I hw_enet_ieee_r_macerr_t IEEE_R_MACERR; /!< [0x2D8] Receive FIFO Overflow Count Statistic Register /
Kojto	90:cb3d968589d8	7471	__I hw_enet_ieee_r_fdxfc_t IEEE_R_FDXFC; /!< [0x2DC] Flow Control Pause Frames Received Statistic Register /
Kojto	90:cb3d968589d8	7472	__I hw_enet_ieee_r_octets_ok_t IEEE_R_OCTETS_OK; /!< [0x2E0] Octet Count for Frames Received without Error Statistic Register /
Kojto	90:cb3d968589d8	7473	uint8_t _reserved18[284];
Kojto	90:cb3d968589d8	7474	__IO hw_enet_atcr_t ATCR; /!< [0x400] Adjustable Timer Control Register /
Kojto	90:cb3d968589d8	7475	__IO hw_enet_atvr_t ATVR; /!< [0x404] Timer Value Register /
Kojto	90:cb3d968589d8	7476	__IO hw_enet_atoff_t ATOFF; /!< [0x408] Timer Offset Register /
Kojto	90:cb3d968589d8	7477	__IO hw_enet_atper_t ATPER; /!< [0x40C] Timer Period Register /
Kojto	90:cb3d968589d8	7478	__IO hw_enet_atcor_t ATCOR; /!< [0x410] Timer Correction Register /
Kojto	90:cb3d968589d8	7479	__IO hw_enet_atinc_t ATINC; /!< [0x414] Time-Stamping Clock Period Register /
Kojto	90:cb3d968589d8	7480	__I hw_enet_atstmp_t ATSTMP; /!< [0x418] Timestamp of Last Transmitted Frame /
Kojto	90:cb3d968589d8	7481	uint8_t _reserved19[488];
Kojto	90:cb3d968589d8	7482	__IO hw_enet_tgsr_t TGSR; /!< [0x604] Timer Global Status Register /
Kojto	90:cb3d968589d8	7483	struct {
Kojto	90:cb3d968589d8	7484	__IO hw_enet_tcsrn_t TCSRn; /!< [0x608] Timer Control Status Register /
Kojto	90:cb3d968589d8	7485	__IO hw_enet_tccrn_t TCCRn; /!< [0x60C] Timer Compare Capture Register /
Kojto	90:cb3d968589d8	7486	} CHANNEL[4];
Kojto	90:cb3d968589d8	7487	} hw_enet_t;
Kojto	90:cb3d968589d8	7488	#pragma pack()
Kojto	90:cb3d968589d8	7489
Kojto	90:cb3d968589d8	7490	/! @brief Macro to access all ENET registers. /
Kojto	90:cb3d968589d8	7491	/! @param x ENET module instance base address. /
Kojto	90:cb3d968589d8	7492	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto	90:cb3d968589d8	7493	* use the '&' operator, like <code>&HW_ENET(ENET_BASE)</code>. */
Kojto	90:cb3d968589d8	7494	#define HW_ENET(x) ((hw_enet_t )(x))
Kojto	90:cb3d968589d8	7495
Kojto	90:cb3d968589d8	7496	#endif /* __HW_ENET_REGISTERS_H__ */
Kojto	90:cb3d968589d8	7497	/* EOF */