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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cmt.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_CMT_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_CMT_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 CMT
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * Carrier Modulator Transmitter
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
Kojto 90:cb3d968589d8 93 * - HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
Kojto 90:cb3d968589d8 94 * - HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
Kojto 90:cb3d968589d8 95 * - HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
Kojto 90:cb3d968589d8 96 * - HW_CMT_OC - CMT Output Control Register
Kojto 90:cb3d968589d8 97 * - HW_CMT_MSC - CMT Modulator Status and Control Register
Kojto 90:cb3d968589d8 98 * - HW_CMT_CMD1 - CMT Modulator Data Register Mark High
Kojto 90:cb3d968589d8 99 * - HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
Kojto 90:cb3d968589d8 100 * - HW_CMT_CMD3 - CMT Modulator Data Register Space High
Kojto 90:cb3d968589d8 101 * - HW_CMT_CMD4 - CMT Modulator Data Register Space Low
Kojto 90:cb3d968589d8 102 * - HW_CMT_PPS - CMT Primary Prescaler Register
Kojto 90:cb3d968589d8 103 * - HW_CMT_DMA - CMT Direct Memory Access Register
Kojto 90:cb3d968589d8 104 *
Kojto 90:cb3d968589d8 105 * - hw_cmt_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 106 */
Kojto 90:cb3d968589d8 107
Kojto 90:cb3d968589d8 108 #define HW_CMT_INSTANCE_COUNT (1U) /*!< Number of instances of the CMT module. */
Kojto 90:cb3d968589d8 109
Kojto 90:cb3d968589d8 110 /*******************************************************************************
Kojto 90:cb3d968589d8 111 * HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
Kojto 90:cb3d968589d8 112 ******************************************************************************/
Kojto 90:cb3d968589d8 113
Kojto 90:cb3d968589d8 114 /*!
Kojto 90:cb3d968589d8 115 * @brief HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
Kojto 90:cb3d968589d8 116 *
Kojto 90:cb3d968589d8 117 * Reset value: 0x00U
Kojto 90:cb3d968589d8 118 *
Kojto 90:cb3d968589d8 119 * This data register contains the primary high value for generating the carrier
Kojto 90:cb3d968589d8 120 * output.
Kojto 90:cb3d968589d8 121 */
Kojto 90:cb3d968589d8 122 typedef union _hw_cmt_cgh1
Kojto 90:cb3d968589d8 123 {
Kojto 90:cb3d968589d8 124 uint8_t U;
Kojto 90:cb3d968589d8 125 struct _hw_cmt_cgh1_bitfields
Kojto 90:cb3d968589d8 126 {
Kojto 90:cb3d968589d8 127 uint8_t PH : 8; /*!< [7:0] Primary Carrier High Time Data Value */
Kojto 90:cb3d968589d8 128 } B;
Kojto 90:cb3d968589d8 129 } hw_cmt_cgh1_t;
Kojto 90:cb3d968589d8 130
Kojto 90:cb3d968589d8 131 /*!
Kojto 90:cb3d968589d8 132 * @name Constants and macros for entire CMT_CGH1 register
Kojto 90:cb3d968589d8 133 */
Kojto 90:cb3d968589d8 134 /*@{*/
Kojto 90:cb3d968589d8 135 #define HW_CMT_CGH1_ADDR(x) ((x) + 0x0U)
Kojto 90:cb3d968589d8 136
Kojto 90:cb3d968589d8 137 #define HW_CMT_CGH1(x) (*(__IO hw_cmt_cgh1_t *) HW_CMT_CGH1_ADDR(x))
Kojto 90:cb3d968589d8 138 #define HW_CMT_CGH1_RD(x) (HW_CMT_CGH1(x).U)
Kojto 90:cb3d968589d8 139 #define HW_CMT_CGH1_WR(x, v) (HW_CMT_CGH1(x).U = (v))
Kojto 90:cb3d968589d8 140 #define HW_CMT_CGH1_SET(x, v) (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) | (v)))
Kojto 90:cb3d968589d8 141 #define HW_CMT_CGH1_CLR(x, v) (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 142 #define HW_CMT_CGH1_TOG(x, v) (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 143 /*@}*/
Kojto 90:cb3d968589d8 144
Kojto 90:cb3d968589d8 145 /*
Kojto 90:cb3d968589d8 146 * Constants & macros for individual CMT_CGH1 bitfields
Kojto 90:cb3d968589d8 147 */
Kojto 90:cb3d968589d8 148
Kojto 90:cb3d968589d8 149 /*!
Kojto 90:cb3d968589d8 150 * @name Register CMT_CGH1, field PH[7:0] (RW)
Kojto 90:cb3d968589d8 151 *
Kojto 90:cb3d968589d8 152 * Contains the number of input clocks required to generate the carrier high
Kojto 90:cb3d968589d8 153 * time period. When operating in Time mode, this register is always selected. When
Kojto 90:cb3d968589d8 154 * operating in FSK mode, this register and the secondary register pair are
Kojto 90:cb3d968589d8 155 * alternately selected under the control of the modulator. The primary carrier high
Kojto 90:cb3d968589d8 156 * time value is undefined out of reset. This register must be written to nonzero
Kojto 90:cb3d968589d8 157 * values before the carrier generator is enabled to avoid spurious results.
Kojto 90:cb3d968589d8 158 */
Kojto 90:cb3d968589d8 159 /*@{*/
Kojto 90:cb3d968589d8 160 #define BP_CMT_CGH1_PH (0U) /*!< Bit position for CMT_CGH1_PH. */
Kojto 90:cb3d968589d8 161 #define BM_CMT_CGH1_PH (0xFFU) /*!< Bit mask for CMT_CGH1_PH. */
Kojto 90:cb3d968589d8 162 #define BS_CMT_CGH1_PH (8U) /*!< Bit field size in bits for CMT_CGH1_PH. */
Kojto 90:cb3d968589d8 163
Kojto 90:cb3d968589d8 164 /*! @brief Read current value of the CMT_CGH1_PH field. */
Kojto 90:cb3d968589d8 165 #define BR_CMT_CGH1_PH(x) (HW_CMT_CGH1(x).U)
Kojto 90:cb3d968589d8 166
Kojto 90:cb3d968589d8 167 /*! @brief Format value for bitfield CMT_CGH1_PH. */
Kojto 90:cb3d968589d8 168 #define BF_CMT_CGH1_PH(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGH1_PH) & BM_CMT_CGH1_PH)
Kojto 90:cb3d968589d8 169
Kojto 90:cb3d968589d8 170 /*! @brief Set the PH field to a new value. */
Kojto 90:cb3d968589d8 171 #define BW_CMT_CGH1_PH(x, v) (HW_CMT_CGH1_WR(x, v))
Kojto 90:cb3d968589d8 172 /*@}*/
Kojto 90:cb3d968589d8 173
Kojto 90:cb3d968589d8 174 /*******************************************************************************
Kojto 90:cb3d968589d8 175 * HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
Kojto 90:cb3d968589d8 176 ******************************************************************************/
Kojto 90:cb3d968589d8 177
Kojto 90:cb3d968589d8 178 /*!
Kojto 90:cb3d968589d8 179 * @brief HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
Kojto 90:cb3d968589d8 180 *
Kojto 90:cb3d968589d8 181 * Reset value: 0x00U
Kojto 90:cb3d968589d8 182 *
Kojto 90:cb3d968589d8 183 * This data register contains the primary low value for generating the carrier
Kojto 90:cb3d968589d8 184 * output.
Kojto 90:cb3d968589d8 185 */
Kojto 90:cb3d968589d8 186 typedef union _hw_cmt_cgl1
Kojto 90:cb3d968589d8 187 {
Kojto 90:cb3d968589d8 188 uint8_t U;
Kojto 90:cb3d968589d8 189 struct _hw_cmt_cgl1_bitfields
Kojto 90:cb3d968589d8 190 {
Kojto 90:cb3d968589d8 191 uint8_t PL : 8; /*!< [7:0] Primary Carrier Low Time Data Value */
Kojto 90:cb3d968589d8 192 } B;
Kojto 90:cb3d968589d8 193 } hw_cmt_cgl1_t;
Kojto 90:cb3d968589d8 194
Kojto 90:cb3d968589d8 195 /*!
Kojto 90:cb3d968589d8 196 * @name Constants and macros for entire CMT_CGL1 register
Kojto 90:cb3d968589d8 197 */
Kojto 90:cb3d968589d8 198 /*@{*/
Kojto 90:cb3d968589d8 199 #define HW_CMT_CGL1_ADDR(x) ((x) + 0x1U)
Kojto 90:cb3d968589d8 200
Kojto 90:cb3d968589d8 201 #define HW_CMT_CGL1(x) (*(__IO hw_cmt_cgl1_t *) HW_CMT_CGL1_ADDR(x))
Kojto 90:cb3d968589d8 202 #define HW_CMT_CGL1_RD(x) (HW_CMT_CGL1(x).U)
Kojto 90:cb3d968589d8 203 #define HW_CMT_CGL1_WR(x, v) (HW_CMT_CGL1(x).U = (v))
Kojto 90:cb3d968589d8 204 #define HW_CMT_CGL1_SET(x, v) (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) | (v)))
Kojto 90:cb3d968589d8 205 #define HW_CMT_CGL1_CLR(x, v) (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 206 #define HW_CMT_CGL1_TOG(x, v) (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 207 /*@}*/
Kojto 90:cb3d968589d8 208
Kojto 90:cb3d968589d8 209 /*
Kojto 90:cb3d968589d8 210 * Constants & macros for individual CMT_CGL1 bitfields
Kojto 90:cb3d968589d8 211 */
Kojto 90:cb3d968589d8 212
Kojto 90:cb3d968589d8 213 /*!
Kojto 90:cb3d968589d8 214 * @name Register CMT_CGL1, field PL[7:0] (RW)
Kojto 90:cb3d968589d8 215 *
Kojto 90:cb3d968589d8 216 * Contains the number of input clocks required to generate the carrier low time
Kojto 90:cb3d968589d8 217 * period. When operating in Time mode, this register is always selected. When
Kojto 90:cb3d968589d8 218 * operating in FSK mode, this register and the secondary register pair are
Kojto 90:cb3d968589d8 219 * alternately selected under the control of the modulator. The primary carrier low
Kojto 90:cb3d968589d8 220 * time value is undefined out of reset. This register must be written to nonzero
Kojto 90:cb3d968589d8 221 * values before the carrier generator is enabled to avoid spurious results.
Kojto 90:cb3d968589d8 222 */
Kojto 90:cb3d968589d8 223 /*@{*/
Kojto 90:cb3d968589d8 224 #define BP_CMT_CGL1_PL (0U) /*!< Bit position for CMT_CGL1_PL. */
Kojto 90:cb3d968589d8 225 #define BM_CMT_CGL1_PL (0xFFU) /*!< Bit mask for CMT_CGL1_PL. */
Kojto 90:cb3d968589d8 226 #define BS_CMT_CGL1_PL (8U) /*!< Bit field size in bits for CMT_CGL1_PL. */
Kojto 90:cb3d968589d8 227
Kojto 90:cb3d968589d8 228 /*! @brief Read current value of the CMT_CGL1_PL field. */
Kojto 90:cb3d968589d8 229 #define BR_CMT_CGL1_PL(x) (HW_CMT_CGL1(x).U)
Kojto 90:cb3d968589d8 230
Kojto 90:cb3d968589d8 231 /*! @brief Format value for bitfield CMT_CGL1_PL. */
Kojto 90:cb3d968589d8 232 #define BF_CMT_CGL1_PL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGL1_PL) & BM_CMT_CGL1_PL)
Kojto 90:cb3d968589d8 233
Kojto 90:cb3d968589d8 234 /*! @brief Set the PL field to a new value. */
Kojto 90:cb3d968589d8 235 #define BW_CMT_CGL1_PL(x, v) (HW_CMT_CGL1_WR(x, v))
Kojto 90:cb3d968589d8 236 /*@}*/
Kojto 90:cb3d968589d8 237
Kojto 90:cb3d968589d8 238 /*******************************************************************************
Kojto 90:cb3d968589d8 239 * HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
Kojto 90:cb3d968589d8 240 ******************************************************************************/
Kojto 90:cb3d968589d8 241
Kojto 90:cb3d968589d8 242 /*!
Kojto 90:cb3d968589d8 243 * @brief HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
Kojto 90:cb3d968589d8 244 *
Kojto 90:cb3d968589d8 245 * Reset value: 0x00U
Kojto 90:cb3d968589d8 246 *
Kojto 90:cb3d968589d8 247 * This data register contains the secondary high value for generating the
Kojto 90:cb3d968589d8 248 * carrier output.
Kojto 90:cb3d968589d8 249 */
Kojto 90:cb3d968589d8 250 typedef union _hw_cmt_cgh2
Kojto 90:cb3d968589d8 251 {
Kojto 90:cb3d968589d8 252 uint8_t U;
Kojto 90:cb3d968589d8 253 struct _hw_cmt_cgh2_bitfields
Kojto 90:cb3d968589d8 254 {
Kojto 90:cb3d968589d8 255 uint8_t SH : 8; /*!< [7:0] Secondary Carrier High Time Data Value */
Kojto 90:cb3d968589d8 256 } B;
Kojto 90:cb3d968589d8 257 } hw_cmt_cgh2_t;
Kojto 90:cb3d968589d8 258
Kojto 90:cb3d968589d8 259 /*!
Kojto 90:cb3d968589d8 260 * @name Constants and macros for entire CMT_CGH2 register
Kojto 90:cb3d968589d8 261 */
Kojto 90:cb3d968589d8 262 /*@{*/
Kojto 90:cb3d968589d8 263 #define HW_CMT_CGH2_ADDR(x) ((x) + 0x2U)
Kojto 90:cb3d968589d8 264
Kojto 90:cb3d968589d8 265 #define HW_CMT_CGH2(x) (*(__IO hw_cmt_cgh2_t *) HW_CMT_CGH2_ADDR(x))
Kojto 90:cb3d968589d8 266 #define HW_CMT_CGH2_RD(x) (HW_CMT_CGH2(x).U)
Kojto 90:cb3d968589d8 267 #define HW_CMT_CGH2_WR(x, v) (HW_CMT_CGH2(x).U = (v))
Kojto 90:cb3d968589d8 268 #define HW_CMT_CGH2_SET(x, v) (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) | (v)))
Kojto 90:cb3d968589d8 269 #define HW_CMT_CGH2_CLR(x, v) (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 270 #define HW_CMT_CGH2_TOG(x, v) (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 271 /*@}*/
Kojto 90:cb3d968589d8 272
Kojto 90:cb3d968589d8 273 /*
Kojto 90:cb3d968589d8 274 * Constants & macros for individual CMT_CGH2 bitfields
Kojto 90:cb3d968589d8 275 */
Kojto 90:cb3d968589d8 276
Kojto 90:cb3d968589d8 277 /*!
Kojto 90:cb3d968589d8 278 * @name Register CMT_CGH2, field SH[7:0] (RW)
Kojto 90:cb3d968589d8 279 *
Kojto 90:cb3d968589d8 280 * Contains the number of input clocks required to generate the carrier high
Kojto 90:cb3d968589d8 281 * time period. When operating in Time mode, this register is never selected. When
Kojto 90:cb3d968589d8 282 * operating in FSK mode, this register and the primary register pair are
Kojto 90:cb3d968589d8 283 * alternately selected under control of the modulator. The secondary carrier high time
Kojto 90:cb3d968589d8 284 * value is undefined out of reset. This register must be written to nonzero
Kojto 90:cb3d968589d8 285 * values before the carrier generator is enabled when operating in FSK mode.
Kojto 90:cb3d968589d8 286 */
Kojto 90:cb3d968589d8 287 /*@{*/
Kojto 90:cb3d968589d8 288 #define BP_CMT_CGH2_SH (0U) /*!< Bit position for CMT_CGH2_SH. */
Kojto 90:cb3d968589d8 289 #define BM_CMT_CGH2_SH (0xFFU) /*!< Bit mask for CMT_CGH2_SH. */
Kojto 90:cb3d968589d8 290 #define BS_CMT_CGH2_SH (8U) /*!< Bit field size in bits for CMT_CGH2_SH. */
Kojto 90:cb3d968589d8 291
Kojto 90:cb3d968589d8 292 /*! @brief Read current value of the CMT_CGH2_SH field. */
Kojto 90:cb3d968589d8 293 #define BR_CMT_CGH2_SH(x) (HW_CMT_CGH2(x).U)
Kojto 90:cb3d968589d8 294
Kojto 90:cb3d968589d8 295 /*! @brief Format value for bitfield CMT_CGH2_SH. */
Kojto 90:cb3d968589d8 296 #define BF_CMT_CGH2_SH(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGH2_SH) & BM_CMT_CGH2_SH)
Kojto 90:cb3d968589d8 297
Kojto 90:cb3d968589d8 298 /*! @brief Set the SH field to a new value. */
Kojto 90:cb3d968589d8 299 #define BW_CMT_CGH2_SH(x, v) (HW_CMT_CGH2_WR(x, v))
Kojto 90:cb3d968589d8 300 /*@}*/
Kojto 90:cb3d968589d8 301
Kojto 90:cb3d968589d8 302 /*******************************************************************************
Kojto 90:cb3d968589d8 303 * HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
Kojto 90:cb3d968589d8 304 ******************************************************************************/
Kojto 90:cb3d968589d8 305
Kojto 90:cb3d968589d8 306 /*!
Kojto 90:cb3d968589d8 307 * @brief HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
Kojto 90:cb3d968589d8 308 *
Kojto 90:cb3d968589d8 309 * Reset value: 0x00U
Kojto 90:cb3d968589d8 310 *
Kojto 90:cb3d968589d8 311 * This data register contains the secondary low value for generating the
Kojto 90:cb3d968589d8 312 * carrier output.
Kojto 90:cb3d968589d8 313 */
Kojto 90:cb3d968589d8 314 typedef union _hw_cmt_cgl2
Kojto 90:cb3d968589d8 315 {
Kojto 90:cb3d968589d8 316 uint8_t U;
Kojto 90:cb3d968589d8 317 struct _hw_cmt_cgl2_bitfields
Kojto 90:cb3d968589d8 318 {
Kojto 90:cb3d968589d8 319 uint8_t SL : 8; /*!< [7:0] Secondary Carrier Low Time Data Value */
Kojto 90:cb3d968589d8 320 } B;
Kojto 90:cb3d968589d8 321 } hw_cmt_cgl2_t;
Kojto 90:cb3d968589d8 322
Kojto 90:cb3d968589d8 323 /*!
Kojto 90:cb3d968589d8 324 * @name Constants and macros for entire CMT_CGL2 register
Kojto 90:cb3d968589d8 325 */
Kojto 90:cb3d968589d8 326 /*@{*/
Kojto 90:cb3d968589d8 327 #define HW_CMT_CGL2_ADDR(x) ((x) + 0x3U)
Kojto 90:cb3d968589d8 328
Kojto 90:cb3d968589d8 329 #define HW_CMT_CGL2(x) (*(__IO hw_cmt_cgl2_t *) HW_CMT_CGL2_ADDR(x))
Kojto 90:cb3d968589d8 330 #define HW_CMT_CGL2_RD(x) (HW_CMT_CGL2(x).U)
Kojto 90:cb3d968589d8 331 #define HW_CMT_CGL2_WR(x, v) (HW_CMT_CGL2(x).U = (v))
Kojto 90:cb3d968589d8 332 #define HW_CMT_CGL2_SET(x, v) (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) | (v)))
Kojto 90:cb3d968589d8 333 #define HW_CMT_CGL2_CLR(x, v) (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 334 #define HW_CMT_CGL2_TOG(x, v) (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 335 /*@}*/
Kojto 90:cb3d968589d8 336
Kojto 90:cb3d968589d8 337 /*
Kojto 90:cb3d968589d8 338 * Constants & macros for individual CMT_CGL2 bitfields
Kojto 90:cb3d968589d8 339 */
Kojto 90:cb3d968589d8 340
Kojto 90:cb3d968589d8 341 /*!
Kojto 90:cb3d968589d8 342 * @name Register CMT_CGL2, field SL[7:0] (RW)
Kojto 90:cb3d968589d8 343 *
Kojto 90:cb3d968589d8 344 * Contains the number of input clocks required to generate the carrier low time
Kojto 90:cb3d968589d8 345 * period. When operating in Time mode, this register is never selected. When
Kojto 90:cb3d968589d8 346 * operating in FSK mode, this register and the primary register pair are
Kojto 90:cb3d968589d8 347 * alternately selected under the control of the modulator. The secondary carrier low time
Kojto 90:cb3d968589d8 348 * value is undefined out of reset. This register must be written to nonzero
Kojto 90:cb3d968589d8 349 * values before the carrier generator is enabled when operating in FSK mode.
Kojto 90:cb3d968589d8 350 */
Kojto 90:cb3d968589d8 351 /*@{*/
Kojto 90:cb3d968589d8 352 #define BP_CMT_CGL2_SL (0U) /*!< Bit position for CMT_CGL2_SL. */
Kojto 90:cb3d968589d8 353 #define BM_CMT_CGL2_SL (0xFFU) /*!< Bit mask for CMT_CGL2_SL. */
Kojto 90:cb3d968589d8 354 #define BS_CMT_CGL2_SL (8U) /*!< Bit field size in bits for CMT_CGL2_SL. */
Kojto 90:cb3d968589d8 355
Kojto 90:cb3d968589d8 356 /*! @brief Read current value of the CMT_CGL2_SL field. */
Kojto 90:cb3d968589d8 357 #define BR_CMT_CGL2_SL(x) (HW_CMT_CGL2(x).U)
Kojto 90:cb3d968589d8 358
Kojto 90:cb3d968589d8 359 /*! @brief Format value for bitfield CMT_CGL2_SL. */
Kojto 90:cb3d968589d8 360 #define BF_CMT_CGL2_SL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGL2_SL) & BM_CMT_CGL2_SL)
Kojto 90:cb3d968589d8 361
Kojto 90:cb3d968589d8 362 /*! @brief Set the SL field to a new value. */
Kojto 90:cb3d968589d8 363 #define BW_CMT_CGL2_SL(x, v) (HW_CMT_CGL2_WR(x, v))
Kojto 90:cb3d968589d8 364 /*@}*/
Kojto 90:cb3d968589d8 365
Kojto 90:cb3d968589d8 366 /*******************************************************************************
Kojto 90:cb3d968589d8 367 * HW_CMT_OC - CMT Output Control Register
Kojto 90:cb3d968589d8 368 ******************************************************************************/
Kojto 90:cb3d968589d8 369
Kojto 90:cb3d968589d8 370 /*!
Kojto 90:cb3d968589d8 371 * @brief HW_CMT_OC - CMT Output Control Register (RW)
Kojto 90:cb3d968589d8 372 *
Kojto 90:cb3d968589d8 373 * Reset value: 0x00U
Kojto 90:cb3d968589d8 374 *
Kojto 90:cb3d968589d8 375 * This register is used to control the IRO signal of the CMT module.
Kojto 90:cb3d968589d8 376 */
Kojto 90:cb3d968589d8 377 typedef union _hw_cmt_oc
Kojto 90:cb3d968589d8 378 {
Kojto 90:cb3d968589d8 379 uint8_t U;
Kojto 90:cb3d968589d8 380 struct _hw_cmt_oc_bitfields
Kojto 90:cb3d968589d8 381 {
Kojto 90:cb3d968589d8 382 uint8_t RESERVED0 : 5; /*!< [4:0] */
Kojto 90:cb3d968589d8 383 uint8_t IROPEN : 1; /*!< [5] IRO Pin Enable */
Kojto 90:cb3d968589d8 384 uint8_t CMTPOL : 1; /*!< [6] CMT Output Polarity */
Kojto 90:cb3d968589d8 385 uint8_t IROL : 1; /*!< [7] IRO Latch Control */
Kojto 90:cb3d968589d8 386 } B;
Kojto 90:cb3d968589d8 387 } hw_cmt_oc_t;
Kojto 90:cb3d968589d8 388
Kojto 90:cb3d968589d8 389 /*!
Kojto 90:cb3d968589d8 390 * @name Constants and macros for entire CMT_OC register
Kojto 90:cb3d968589d8 391 */
Kojto 90:cb3d968589d8 392 /*@{*/
Kojto 90:cb3d968589d8 393 #define HW_CMT_OC_ADDR(x) ((x) + 0x4U)
Kojto 90:cb3d968589d8 394
Kojto 90:cb3d968589d8 395 #define HW_CMT_OC(x) (*(__IO hw_cmt_oc_t *) HW_CMT_OC_ADDR(x))
Kojto 90:cb3d968589d8 396 #define HW_CMT_OC_RD(x) (HW_CMT_OC(x).U)
Kojto 90:cb3d968589d8 397 #define HW_CMT_OC_WR(x, v) (HW_CMT_OC(x).U = (v))
Kojto 90:cb3d968589d8 398 #define HW_CMT_OC_SET(x, v) (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) | (v)))
Kojto 90:cb3d968589d8 399 #define HW_CMT_OC_CLR(x, v) (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 400 #define HW_CMT_OC_TOG(x, v) (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 401 /*@}*/
Kojto 90:cb3d968589d8 402
Kojto 90:cb3d968589d8 403 /*
Kojto 90:cb3d968589d8 404 * Constants & macros for individual CMT_OC bitfields
Kojto 90:cb3d968589d8 405 */
Kojto 90:cb3d968589d8 406
Kojto 90:cb3d968589d8 407 /*!
Kojto 90:cb3d968589d8 408 * @name Register CMT_OC, field IROPEN[5] (RW)
Kojto 90:cb3d968589d8 409 *
Kojto 90:cb3d968589d8 410 * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
Kojto 90:cb3d968589d8 411 * output that drives out either the CMT transmitter output or the state of IROL
Kojto 90:cb3d968589d8 412 * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
Kojto 90:cb3d968589d8 413 * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
Kojto 90:cb3d968589d8 414 * signal is disabled, it is in a high-impedance state and is unable to draw any
Kojto 90:cb3d968589d8 415 * current. This signal is disabled during reset.
Kojto 90:cb3d968589d8 416 *
Kojto 90:cb3d968589d8 417 * Values:
Kojto 90:cb3d968589d8 418 * - 0 - The IRO signal is disabled.
Kojto 90:cb3d968589d8 419 * - 1 - The IRO signal is enabled as output.
Kojto 90:cb3d968589d8 420 */
Kojto 90:cb3d968589d8 421 /*@{*/
Kojto 90:cb3d968589d8 422 #define BP_CMT_OC_IROPEN (5U) /*!< Bit position for CMT_OC_IROPEN. */
Kojto 90:cb3d968589d8 423 #define BM_CMT_OC_IROPEN (0x20U) /*!< Bit mask for CMT_OC_IROPEN. */
Kojto 90:cb3d968589d8 424 #define BS_CMT_OC_IROPEN (1U) /*!< Bit field size in bits for CMT_OC_IROPEN. */
Kojto 90:cb3d968589d8 425
Kojto 90:cb3d968589d8 426 /*! @brief Read current value of the CMT_OC_IROPEN field. */
Kojto 90:cb3d968589d8 427 #define BR_CMT_OC_IROPEN(x) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROPEN))
Kojto 90:cb3d968589d8 428
Kojto 90:cb3d968589d8 429 /*! @brief Format value for bitfield CMT_OC_IROPEN. */
Kojto 90:cb3d968589d8 430 #define BF_CMT_OC_IROPEN(v) ((uint8_t)((uint8_t)(v) << BP_CMT_OC_IROPEN) & BM_CMT_OC_IROPEN)
Kojto 90:cb3d968589d8 431
Kojto 90:cb3d968589d8 432 /*! @brief Set the IROPEN field to a new value. */
Kojto 90:cb3d968589d8 433 #define BW_CMT_OC_IROPEN(x, v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROPEN) = (v))
Kojto 90:cb3d968589d8 434 /*@}*/
Kojto 90:cb3d968589d8 435
Kojto 90:cb3d968589d8 436 /*!
Kojto 90:cb3d968589d8 437 * @name Register CMT_OC, field CMTPOL[6] (RW)
Kojto 90:cb3d968589d8 438 *
Kojto 90:cb3d968589d8 439 * Controls the polarity of the IRO signal.
Kojto 90:cb3d968589d8 440 *
Kojto 90:cb3d968589d8 441 * Values:
Kojto 90:cb3d968589d8 442 * - 0 - The IRO signal is active-low.
Kojto 90:cb3d968589d8 443 * - 1 - The IRO signal is active-high.
Kojto 90:cb3d968589d8 444 */
Kojto 90:cb3d968589d8 445 /*@{*/
Kojto 90:cb3d968589d8 446 #define BP_CMT_OC_CMTPOL (6U) /*!< Bit position for CMT_OC_CMTPOL. */
Kojto 90:cb3d968589d8 447 #define BM_CMT_OC_CMTPOL (0x40U) /*!< Bit mask for CMT_OC_CMTPOL. */
Kojto 90:cb3d968589d8 448 #define BS_CMT_OC_CMTPOL (1U) /*!< Bit field size in bits for CMT_OC_CMTPOL. */
Kojto 90:cb3d968589d8 449
Kojto 90:cb3d968589d8 450 /*! @brief Read current value of the CMT_OC_CMTPOL field. */
Kojto 90:cb3d968589d8 451 #define BR_CMT_OC_CMTPOL(x) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_CMTPOL))
Kojto 90:cb3d968589d8 452
Kojto 90:cb3d968589d8 453 /*! @brief Format value for bitfield CMT_OC_CMTPOL. */
Kojto 90:cb3d968589d8 454 #define BF_CMT_OC_CMTPOL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_OC_CMTPOL) & BM_CMT_OC_CMTPOL)
Kojto 90:cb3d968589d8 455
Kojto 90:cb3d968589d8 456 /*! @brief Set the CMTPOL field to a new value. */
Kojto 90:cb3d968589d8 457 #define BW_CMT_OC_CMTPOL(x, v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_CMTPOL) = (v))
Kojto 90:cb3d968589d8 458 /*@}*/
Kojto 90:cb3d968589d8 459
Kojto 90:cb3d968589d8 460 /*!
Kojto 90:cb3d968589d8 461 * @name Register CMT_OC, field IROL[7] (RW)
Kojto 90:cb3d968589d8 462 *
Kojto 90:cb3d968589d8 463 * Reads the state of the IRO latch. Writing to IROL changes the state of the
Kojto 90:cb3d968589d8 464 * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
Kojto 90:cb3d968589d8 465 */
Kojto 90:cb3d968589d8 466 /*@{*/
Kojto 90:cb3d968589d8 467 #define BP_CMT_OC_IROL (7U) /*!< Bit position for CMT_OC_IROL. */
Kojto 90:cb3d968589d8 468 #define BM_CMT_OC_IROL (0x80U) /*!< Bit mask for CMT_OC_IROL. */
Kojto 90:cb3d968589d8 469 #define BS_CMT_OC_IROL (1U) /*!< Bit field size in bits for CMT_OC_IROL. */
Kojto 90:cb3d968589d8 470
Kojto 90:cb3d968589d8 471 /*! @brief Read current value of the CMT_OC_IROL field. */
Kojto 90:cb3d968589d8 472 #define BR_CMT_OC_IROL(x) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROL))
Kojto 90:cb3d968589d8 473
Kojto 90:cb3d968589d8 474 /*! @brief Format value for bitfield CMT_OC_IROL. */
Kojto 90:cb3d968589d8 475 #define BF_CMT_OC_IROL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_OC_IROL) & BM_CMT_OC_IROL)
Kojto 90:cb3d968589d8 476
Kojto 90:cb3d968589d8 477 /*! @brief Set the IROL field to a new value. */
Kojto 90:cb3d968589d8 478 #define BW_CMT_OC_IROL(x, v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROL) = (v))
Kojto 90:cb3d968589d8 479 /*@}*/
Kojto 90:cb3d968589d8 480
Kojto 90:cb3d968589d8 481 /*******************************************************************************
Kojto 90:cb3d968589d8 482 * HW_CMT_MSC - CMT Modulator Status and Control Register
Kojto 90:cb3d968589d8 483 ******************************************************************************/
Kojto 90:cb3d968589d8 484
Kojto 90:cb3d968589d8 485 /*!
Kojto 90:cb3d968589d8 486 * @brief HW_CMT_MSC - CMT Modulator Status and Control Register (RW)
Kojto 90:cb3d968589d8 487 *
Kojto 90:cb3d968589d8 488 * Reset value: 0x00U
Kojto 90:cb3d968589d8 489 *
Kojto 90:cb3d968589d8 490 * This register contains the modulator and carrier generator enable (MCGEN),
Kojto 90:cb3d968589d8 491 * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
Kojto 90:cb3d968589d8 492 * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
Kojto 90:cb3d968589d8 493 * (EOCF) status bit.
Kojto 90:cb3d968589d8 494 */
Kojto 90:cb3d968589d8 495 typedef union _hw_cmt_msc
Kojto 90:cb3d968589d8 496 {
Kojto 90:cb3d968589d8 497 uint8_t U;
Kojto 90:cb3d968589d8 498 struct _hw_cmt_msc_bitfields
Kojto 90:cb3d968589d8 499 {
Kojto 90:cb3d968589d8 500 uint8_t MCGEN : 1; /*!< [0] Modulator and Carrier Generator Enable */
Kojto 90:cb3d968589d8 501 uint8_t EOCIE : 1; /*!< [1] End of Cycle Interrupt Enable */
Kojto 90:cb3d968589d8 502 uint8_t FSK : 1; /*!< [2] FSK Mode Select */
Kojto 90:cb3d968589d8 503 uint8_t BASE : 1; /*!< [3] Baseband Enable */
Kojto 90:cb3d968589d8 504 uint8_t EXSPC : 1; /*!< [4] Extended Space Enable */
Kojto 90:cb3d968589d8 505 uint8_t CMTDIV : 2; /*!< [6:5] CMT Clock Divide Prescaler */
Kojto 90:cb3d968589d8 506 uint8_t EOCF : 1; /*!< [7] End Of Cycle Status Flag */
Kojto 90:cb3d968589d8 507 } B;
Kojto 90:cb3d968589d8 508 } hw_cmt_msc_t;
Kojto 90:cb3d968589d8 509
Kojto 90:cb3d968589d8 510 /*!
Kojto 90:cb3d968589d8 511 * @name Constants and macros for entire CMT_MSC register
Kojto 90:cb3d968589d8 512 */
Kojto 90:cb3d968589d8 513 /*@{*/
Kojto 90:cb3d968589d8 514 #define HW_CMT_MSC_ADDR(x) ((x) + 0x5U)
Kojto 90:cb3d968589d8 515
Kojto 90:cb3d968589d8 516 #define HW_CMT_MSC(x) (*(__IO hw_cmt_msc_t *) HW_CMT_MSC_ADDR(x))
Kojto 90:cb3d968589d8 517 #define HW_CMT_MSC_RD(x) (HW_CMT_MSC(x).U)
Kojto 90:cb3d968589d8 518 #define HW_CMT_MSC_WR(x, v) (HW_CMT_MSC(x).U = (v))
Kojto 90:cb3d968589d8 519 #define HW_CMT_MSC_SET(x, v) (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) | (v)))
Kojto 90:cb3d968589d8 520 #define HW_CMT_MSC_CLR(x, v) (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 521 #define HW_CMT_MSC_TOG(x, v) (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 522 /*@}*/
Kojto 90:cb3d968589d8 523
Kojto 90:cb3d968589d8 524 /*
Kojto 90:cb3d968589d8 525 * Constants & macros for individual CMT_MSC bitfields
Kojto 90:cb3d968589d8 526 */
Kojto 90:cb3d968589d8 527
Kojto 90:cb3d968589d8 528 /*!
Kojto 90:cb3d968589d8 529 * @name Register CMT_MSC, field MCGEN[0] (RW)
Kojto 90:cb3d968589d8 530 *
Kojto 90:cb3d968589d8 531 * Setting MCGEN will initialize the carrier generator and modulator and will
Kojto 90:cb3d968589d8 532 * enable all clocks. When enabled, the carrier generator and modulator will
Kojto 90:cb3d968589d8 533 * function continuously. When MCGEN is cleared, the current modulator cycle will be
Kojto 90:cb3d968589d8 534 * allowed to expire before all carrier and modulator clocks are disabled to save
Kojto 90:cb3d968589d8 535 * power and the modulator output is forced low. To prevent spurious operation,
Kojto 90:cb3d968589d8 536 * the user should initialize all data and control registers before enabling the
Kojto 90:cb3d968589d8 537 * system.
Kojto 90:cb3d968589d8 538 *
Kojto 90:cb3d968589d8 539 * Values:
Kojto 90:cb3d968589d8 540 * - 0 - Modulator and carrier generator disabled
Kojto 90:cb3d968589d8 541 * - 1 - Modulator and carrier generator enabled
Kojto 90:cb3d968589d8 542 */
Kojto 90:cb3d968589d8 543 /*@{*/
Kojto 90:cb3d968589d8 544 #define BP_CMT_MSC_MCGEN (0U) /*!< Bit position for CMT_MSC_MCGEN. */
Kojto 90:cb3d968589d8 545 #define BM_CMT_MSC_MCGEN (0x01U) /*!< Bit mask for CMT_MSC_MCGEN. */
Kojto 90:cb3d968589d8 546 #define BS_CMT_MSC_MCGEN (1U) /*!< Bit field size in bits for CMT_MSC_MCGEN. */
Kojto 90:cb3d968589d8 547
Kojto 90:cb3d968589d8 548 /*! @brief Read current value of the CMT_MSC_MCGEN field. */
Kojto 90:cb3d968589d8 549 #define BR_CMT_MSC_MCGEN(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_MCGEN))
Kojto 90:cb3d968589d8 550
Kojto 90:cb3d968589d8 551 /*! @brief Format value for bitfield CMT_MSC_MCGEN. */
Kojto 90:cb3d968589d8 552 #define BF_CMT_MSC_MCGEN(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_MCGEN) & BM_CMT_MSC_MCGEN)
Kojto 90:cb3d968589d8 553
Kojto 90:cb3d968589d8 554 /*! @brief Set the MCGEN field to a new value. */
Kojto 90:cb3d968589d8 555 #define BW_CMT_MSC_MCGEN(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_MCGEN) = (v))
Kojto 90:cb3d968589d8 556 /*@}*/
Kojto 90:cb3d968589d8 557
Kojto 90:cb3d968589d8 558 /*!
Kojto 90:cb3d968589d8 559 * @name Register CMT_MSC, field EOCIE[1] (RW)
Kojto 90:cb3d968589d8 560 *
Kojto 90:cb3d968589d8 561 * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
Kojto 90:cb3d968589d8 562 *
Kojto 90:cb3d968589d8 563 * Values:
Kojto 90:cb3d968589d8 564 * - 0 - CPU interrupt is disabled.
Kojto 90:cb3d968589d8 565 * - 1 - CPU interrupt is enabled.
Kojto 90:cb3d968589d8 566 */
Kojto 90:cb3d968589d8 567 /*@{*/
Kojto 90:cb3d968589d8 568 #define BP_CMT_MSC_EOCIE (1U) /*!< Bit position for CMT_MSC_EOCIE. */
Kojto 90:cb3d968589d8 569 #define BM_CMT_MSC_EOCIE (0x02U) /*!< Bit mask for CMT_MSC_EOCIE. */
Kojto 90:cb3d968589d8 570 #define BS_CMT_MSC_EOCIE (1U) /*!< Bit field size in bits for CMT_MSC_EOCIE. */
Kojto 90:cb3d968589d8 571
Kojto 90:cb3d968589d8 572 /*! @brief Read current value of the CMT_MSC_EOCIE field. */
Kojto 90:cb3d968589d8 573 #define BR_CMT_MSC_EOCIE(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCIE))
Kojto 90:cb3d968589d8 574
Kojto 90:cb3d968589d8 575 /*! @brief Format value for bitfield CMT_MSC_EOCIE. */
Kojto 90:cb3d968589d8 576 #define BF_CMT_MSC_EOCIE(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_EOCIE) & BM_CMT_MSC_EOCIE)
Kojto 90:cb3d968589d8 577
Kojto 90:cb3d968589d8 578 /*! @brief Set the EOCIE field to a new value. */
Kojto 90:cb3d968589d8 579 #define BW_CMT_MSC_EOCIE(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCIE) = (v))
Kojto 90:cb3d968589d8 580 /*@}*/
Kojto 90:cb3d968589d8 581
Kojto 90:cb3d968589d8 582 /*!
Kojto 90:cb3d968589d8 583 * @name Register CMT_MSC, field FSK[2] (RW)
Kojto 90:cb3d968589d8 584 *
Kojto 90:cb3d968589d8 585 * Enables FSK operation.
Kojto 90:cb3d968589d8 586 *
Kojto 90:cb3d968589d8 587 * Values:
Kojto 90:cb3d968589d8 588 * - 0 - The CMT operates in Time or Baseband mode.
Kojto 90:cb3d968589d8 589 * - 1 - The CMT operates in FSK mode.
Kojto 90:cb3d968589d8 590 */
Kojto 90:cb3d968589d8 591 /*@{*/
Kojto 90:cb3d968589d8 592 #define BP_CMT_MSC_FSK (2U) /*!< Bit position for CMT_MSC_FSK. */
Kojto 90:cb3d968589d8 593 #define BM_CMT_MSC_FSK (0x04U) /*!< Bit mask for CMT_MSC_FSK. */
Kojto 90:cb3d968589d8 594 #define BS_CMT_MSC_FSK (1U) /*!< Bit field size in bits for CMT_MSC_FSK. */
Kojto 90:cb3d968589d8 595
Kojto 90:cb3d968589d8 596 /*! @brief Read current value of the CMT_MSC_FSK field. */
Kojto 90:cb3d968589d8 597 #define BR_CMT_MSC_FSK(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_FSK))
Kojto 90:cb3d968589d8 598
Kojto 90:cb3d968589d8 599 /*! @brief Format value for bitfield CMT_MSC_FSK. */
Kojto 90:cb3d968589d8 600 #define BF_CMT_MSC_FSK(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_FSK) & BM_CMT_MSC_FSK)
Kojto 90:cb3d968589d8 601
Kojto 90:cb3d968589d8 602 /*! @brief Set the FSK field to a new value. */
Kojto 90:cb3d968589d8 603 #define BW_CMT_MSC_FSK(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_FSK) = (v))
Kojto 90:cb3d968589d8 604 /*@}*/
Kojto 90:cb3d968589d8 605
Kojto 90:cb3d968589d8 606 /*!
Kojto 90:cb3d968589d8 607 * @name Register CMT_MSC, field BASE[3] (RW)
Kojto 90:cb3d968589d8 608 *
Kojto 90:cb3d968589d8 609 * When set, BASE disables the carrier generator and forces the carrier output
Kojto 90:cb3d968589d8 610 * high for generation of baseband protocols. When BASE is cleared, the carrier
Kojto 90:cb3d968589d8 611 * generator is enabled and the carrier output toggles at the frequency determined
Kojto 90:cb3d968589d8 612 * by values stored in the carrier data registers. This field is cleared by
Kojto 90:cb3d968589d8 613 * reset. This field is not double-buffered and must not be written to during a
Kojto 90:cb3d968589d8 614 * transmission.
Kojto 90:cb3d968589d8 615 *
Kojto 90:cb3d968589d8 616 * Values:
Kojto 90:cb3d968589d8 617 * - 0 - Baseband mode is disabled.
Kojto 90:cb3d968589d8 618 * - 1 - Baseband mode is enabled.
Kojto 90:cb3d968589d8 619 */
Kojto 90:cb3d968589d8 620 /*@{*/
Kojto 90:cb3d968589d8 621 #define BP_CMT_MSC_BASE (3U) /*!< Bit position for CMT_MSC_BASE. */
Kojto 90:cb3d968589d8 622 #define BM_CMT_MSC_BASE (0x08U) /*!< Bit mask for CMT_MSC_BASE. */
Kojto 90:cb3d968589d8 623 #define BS_CMT_MSC_BASE (1U) /*!< Bit field size in bits for CMT_MSC_BASE. */
Kojto 90:cb3d968589d8 624
Kojto 90:cb3d968589d8 625 /*! @brief Read current value of the CMT_MSC_BASE field. */
Kojto 90:cb3d968589d8 626 #define BR_CMT_MSC_BASE(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_BASE))
Kojto 90:cb3d968589d8 627
Kojto 90:cb3d968589d8 628 /*! @brief Format value for bitfield CMT_MSC_BASE. */
Kojto 90:cb3d968589d8 629 #define BF_CMT_MSC_BASE(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_BASE) & BM_CMT_MSC_BASE)
Kojto 90:cb3d968589d8 630
Kojto 90:cb3d968589d8 631 /*! @brief Set the BASE field to a new value. */
Kojto 90:cb3d968589d8 632 #define BW_CMT_MSC_BASE(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_BASE) = (v))
Kojto 90:cb3d968589d8 633 /*@}*/
Kojto 90:cb3d968589d8 634
Kojto 90:cb3d968589d8 635 /*!
Kojto 90:cb3d968589d8 636 * @name Register CMT_MSC, field EXSPC[4] (RW)
Kojto 90:cb3d968589d8 637 *
Kojto 90:cb3d968589d8 638 * Enables the extended space operation.
Kojto 90:cb3d968589d8 639 *
Kojto 90:cb3d968589d8 640 * Values:
Kojto 90:cb3d968589d8 641 * - 0 - Extended space is disabled.
Kojto 90:cb3d968589d8 642 * - 1 - Extended space is enabled.
Kojto 90:cb3d968589d8 643 */
Kojto 90:cb3d968589d8 644 /*@{*/
Kojto 90:cb3d968589d8 645 #define BP_CMT_MSC_EXSPC (4U) /*!< Bit position for CMT_MSC_EXSPC. */
Kojto 90:cb3d968589d8 646 #define BM_CMT_MSC_EXSPC (0x10U) /*!< Bit mask for CMT_MSC_EXSPC. */
Kojto 90:cb3d968589d8 647 #define BS_CMT_MSC_EXSPC (1U) /*!< Bit field size in bits for CMT_MSC_EXSPC. */
Kojto 90:cb3d968589d8 648
Kojto 90:cb3d968589d8 649 /*! @brief Read current value of the CMT_MSC_EXSPC field. */
Kojto 90:cb3d968589d8 650 #define BR_CMT_MSC_EXSPC(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EXSPC))
Kojto 90:cb3d968589d8 651
Kojto 90:cb3d968589d8 652 /*! @brief Format value for bitfield CMT_MSC_EXSPC. */
Kojto 90:cb3d968589d8 653 #define BF_CMT_MSC_EXSPC(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_EXSPC) & BM_CMT_MSC_EXSPC)
Kojto 90:cb3d968589d8 654
Kojto 90:cb3d968589d8 655 /*! @brief Set the EXSPC field to a new value. */
Kojto 90:cb3d968589d8 656 #define BW_CMT_MSC_EXSPC(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EXSPC) = (v))
Kojto 90:cb3d968589d8 657 /*@}*/
Kojto 90:cb3d968589d8 658
Kojto 90:cb3d968589d8 659 /*!
Kojto 90:cb3d968589d8 660 * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
Kojto 90:cb3d968589d8 661 *
Kojto 90:cb3d968589d8 662 * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
Kojto 90:cb3d968589d8 663 * divided by 2 ,4, or 8 . This field must not be changed during a transmission
Kojto 90:cb3d968589d8 664 * because it is not double-buffered.
Kojto 90:cb3d968589d8 665 *
Kojto 90:cb3d968589d8 666 * Values:
Kojto 90:cb3d968589d8 667 * - 00 - IF * 1
Kojto 90:cb3d968589d8 668 * - 01 - IF * 2
Kojto 90:cb3d968589d8 669 * - 10 - IF * 4
Kojto 90:cb3d968589d8 670 * - 11 - IF * 8
Kojto 90:cb3d968589d8 671 */
Kojto 90:cb3d968589d8 672 /*@{*/
Kojto 90:cb3d968589d8 673 #define BP_CMT_MSC_CMTDIV (5U) /*!< Bit position for CMT_MSC_CMTDIV. */
Kojto 90:cb3d968589d8 674 #define BM_CMT_MSC_CMTDIV (0x60U) /*!< Bit mask for CMT_MSC_CMTDIV. */
Kojto 90:cb3d968589d8 675 #define BS_CMT_MSC_CMTDIV (2U) /*!< Bit field size in bits for CMT_MSC_CMTDIV. */
Kojto 90:cb3d968589d8 676
Kojto 90:cb3d968589d8 677 /*! @brief Read current value of the CMT_MSC_CMTDIV field. */
Kojto 90:cb3d968589d8 678 #define BR_CMT_MSC_CMTDIV(x) (HW_CMT_MSC(x).B.CMTDIV)
Kojto 90:cb3d968589d8 679
Kojto 90:cb3d968589d8 680 /*! @brief Format value for bitfield CMT_MSC_CMTDIV. */
Kojto 90:cb3d968589d8 681 #define BF_CMT_MSC_CMTDIV(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_CMTDIV) & BM_CMT_MSC_CMTDIV)
Kojto 90:cb3d968589d8 682
Kojto 90:cb3d968589d8 683 /*! @brief Set the CMTDIV field to a new value. */
Kojto 90:cb3d968589d8 684 #define BW_CMT_MSC_CMTDIV(x, v) (HW_CMT_MSC_WR(x, (HW_CMT_MSC_RD(x) & ~BM_CMT_MSC_CMTDIV) | BF_CMT_MSC_CMTDIV(v)))
Kojto 90:cb3d968589d8 685 /*@}*/
Kojto 90:cb3d968589d8 686
Kojto 90:cb3d968589d8 687 /*!
Kojto 90:cb3d968589d8 688 * @name Register CMT_MSC, field EOCF[7] (RO)
Kojto 90:cb3d968589d8 689 *
Kojto 90:cb3d968589d8 690 * Sets when: The modulator is not currently active and MCGEN is set to begin
Kojto 90:cb3d968589d8 691 * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
Kojto 90:cb3d968589d8 692 * set. This is recognized when a match occurs between the contents of the space
Kojto 90:cb3d968589d8 693 * period register and the down counter. At this time, the counter is
Kojto 90:cb3d968589d8 694 * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
Kojto 90:cb3d968589d8 695 * the space period register is loaded with, possibly new contents of the space
Kojto 90:cb3d968589d8 696 * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
Kojto 90:cb3d968589d8 697 * access of CMD2 or CMD4, or by the DMA transfer.
Kojto 90:cb3d968589d8 698 *
Kojto 90:cb3d968589d8 699 * Values:
Kojto 90:cb3d968589d8 700 * - 0 - End of modulation cycle has not occured since the flag last cleared.
Kojto 90:cb3d968589d8 701 * - 1 - End of modulator cycle has occurred.
Kojto 90:cb3d968589d8 702 */
Kojto 90:cb3d968589d8 703 /*@{*/
Kojto 90:cb3d968589d8 704 #define BP_CMT_MSC_EOCF (7U) /*!< Bit position for CMT_MSC_EOCF. */
Kojto 90:cb3d968589d8 705 #define BM_CMT_MSC_EOCF (0x80U) /*!< Bit mask for CMT_MSC_EOCF. */
Kojto 90:cb3d968589d8 706 #define BS_CMT_MSC_EOCF (1U) /*!< Bit field size in bits for CMT_MSC_EOCF. */
Kojto 90:cb3d968589d8 707
Kojto 90:cb3d968589d8 708 /*! @brief Read current value of the CMT_MSC_EOCF field. */
Kojto 90:cb3d968589d8 709 #define BR_CMT_MSC_EOCF(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCF))
Kojto 90:cb3d968589d8 710 /*@}*/
Kojto 90:cb3d968589d8 711
Kojto 90:cb3d968589d8 712 /*******************************************************************************
Kojto 90:cb3d968589d8 713 * HW_CMT_CMD1 - CMT Modulator Data Register Mark High
Kojto 90:cb3d968589d8 714 ******************************************************************************/
Kojto 90:cb3d968589d8 715
Kojto 90:cb3d968589d8 716 /*!
Kojto 90:cb3d968589d8 717 * @brief HW_CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
Kojto 90:cb3d968589d8 718 *
Kojto 90:cb3d968589d8 719 * Reset value: 0x00U
Kojto 90:cb3d968589d8 720 *
Kojto 90:cb3d968589d8 721 * The contents of this register are transferred to the modulator down counter
Kojto 90:cb3d968589d8 722 * upon the completion of a modulation period.
Kojto 90:cb3d968589d8 723 */
Kojto 90:cb3d968589d8 724 typedef union _hw_cmt_cmd1
Kojto 90:cb3d968589d8 725 {
Kojto 90:cb3d968589d8 726 uint8_t U;
Kojto 90:cb3d968589d8 727 struct _hw_cmt_cmd1_bitfields
Kojto 90:cb3d968589d8 728 {
Kojto 90:cb3d968589d8 729 uint8_t MB : 8; /*!< [7:0] */
Kojto 90:cb3d968589d8 730 } B;
Kojto 90:cb3d968589d8 731 } hw_cmt_cmd1_t;
Kojto 90:cb3d968589d8 732
Kojto 90:cb3d968589d8 733 /*!
Kojto 90:cb3d968589d8 734 * @name Constants and macros for entire CMT_CMD1 register
Kojto 90:cb3d968589d8 735 */
Kojto 90:cb3d968589d8 736 /*@{*/
Kojto 90:cb3d968589d8 737 #define HW_CMT_CMD1_ADDR(x) ((x) + 0x6U)
Kojto 90:cb3d968589d8 738
Kojto 90:cb3d968589d8 739 #define HW_CMT_CMD1(x) (*(__IO hw_cmt_cmd1_t *) HW_CMT_CMD1_ADDR(x))
Kojto 90:cb3d968589d8 740 #define HW_CMT_CMD1_RD(x) (HW_CMT_CMD1(x).U)
Kojto 90:cb3d968589d8 741 #define HW_CMT_CMD1_WR(x, v) (HW_CMT_CMD1(x).U = (v))
Kojto 90:cb3d968589d8 742 #define HW_CMT_CMD1_SET(x, v) (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) | (v)))
Kojto 90:cb3d968589d8 743 #define HW_CMT_CMD1_CLR(x, v) (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 744 #define HW_CMT_CMD1_TOG(x, v) (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 745 /*@}*/
Kojto 90:cb3d968589d8 746
Kojto 90:cb3d968589d8 747 /*
Kojto 90:cb3d968589d8 748 * Constants & macros for individual CMT_CMD1 bitfields
Kojto 90:cb3d968589d8 749 */
Kojto 90:cb3d968589d8 750
Kojto 90:cb3d968589d8 751 /*!
Kojto 90:cb3d968589d8 752 * @name Register CMT_CMD1, field MB[7:0] (RW)
Kojto 90:cb3d968589d8 753 *
Kojto 90:cb3d968589d8 754 * Controls the upper mark periods of the modulator for all modes.
Kojto 90:cb3d968589d8 755 */
Kojto 90:cb3d968589d8 756 /*@{*/
Kojto 90:cb3d968589d8 757 #define BP_CMT_CMD1_MB (0U) /*!< Bit position for CMT_CMD1_MB. */
Kojto 90:cb3d968589d8 758 #define BM_CMT_CMD1_MB (0xFFU) /*!< Bit mask for CMT_CMD1_MB. */
Kojto 90:cb3d968589d8 759 #define BS_CMT_CMD1_MB (8U) /*!< Bit field size in bits for CMT_CMD1_MB. */
Kojto 90:cb3d968589d8 760
Kojto 90:cb3d968589d8 761 /*! @brief Read current value of the CMT_CMD1_MB field. */
Kojto 90:cb3d968589d8 762 #define BR_CMT_CMD1_MB(x) (HW_CMT_CMD1(x).U)
Kojto 90:cb3d968589d8 763
Kojto 90:cb3d968589d8 764 /*! @brief Format value for bitfield CMT_CMD1_MB. */
Kojto 90:cb3d968589d8 765 #define BF_CMT_CMD1_MB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD1_MB) & BM_CMT_CMD1_MB)
Kojto 90:cb3d968589d8 766
Kojto 90:cb3d968589d8 767 /*! @brief Set the MB field to a new value. */
Kojto 90:cb3d968589d8 768 #define BW_CMT_CMD1_MB(x, v) (HW_CMT_CMD1_WR(x, v))
Kojto 90:cb3d968589d8 769 /*@}*/
Kojto 90:cb3d968589d8 770
Kojto 90:cb3d968589d8 771 /*******************************************************************************
Kojto 90:cb3d968589d8 772 * HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
Kojto 90:cb3d968589d8 773 ******************************************************************************/
Kojto 90:cb3d968589d8 774
Kojto 90:cb3d968589d8 775 /*!
Kojto 90:cb3d968589d8 776 * @brief HW_CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
Kojto 90:cb3d968589d8 777 *
Kojto 90:cb3d968589d8 778 * Reset value: 0x00U
Kojto 90:cb3d968589d8 779 *
Kojto 90:cb3d968589d8 780 * The contents of this register are transferred to the modulator down counter
Kojto 90:cb3d968589d8 781 * upon the completion of a modulation period.
Kojto 90:cb3d968589d8 782 */
Kojto 90:cb3d968589d8 783 typedef union _hw_cmt_cmd2
Kojto 90:cb3d968589d8 784 {
Kojto 90:cb3d968589d8 785 uint8_t U;
Kojto 90:cb3d968589d8 786 struct _hw_cmt_cmd2_bitfields
Kojto 90:cb3d968589d8 787 {
Kojto 90:cb3d968589d8 788 uint8_t MB : 8; /*!< [7:0] */
Kojto 90:cb3d968589d8 789 } B;
Kojto 90:cb3d968589d8 790 } hw_cmt_cmd2_t;
Kojto 90:cb3d968589d8 791
Kojto 90:cb3d968589d8 792 /*!
Kojto 90:cb3d968589d8 793 * @name Constants and macros for entire CMT_CMD2 register
Kojto 90:cb3d968589d8 794 */
Kojto 90:cb3d968589d8 795 /*@{*/
Kojto 90:cb3d968589d8 796 #define HW_CMT_CMD2_ADDR(x) ((x) + 0x7U)
Kojto 90:cb3d968589d8 797
Kojto 90:cb3d968589d8 798 #define HW_CMT_CMD2(x) (*(__IO hw_cmt_cmd2_t *) HW_CMT_CMD2_ADDR(x))
Kojto 90:cb3d968589d8 799 #define HW_CMT_CMD2_RD(x) (HW_CMT_CMD2(x).U)
Kojto 90:cb3d968589d8 800 #define HW_CMT_CMD2_WR(x, v) (HW_CMT_CMD2(x).U = (v))
Kojto 90:cb3d968589d8 801 #define HW_CMT_CMD2_SET(x, v) (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) | (v)))
Kojto 90:cb3d968589d8 802 #define HW_CMT_CMD2_CLR(x, v) (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 803 #define HW_CMT_CMD2_TOG(x, v) (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 804 /*@}*/
Kojto 90:cb3d968589d8 805
Kojto 90:cb3d968589d8 806 /*
Kojto 90:cb3d968589d8 807 * Constants & macros for individual CMT_CMD2 bitfields
Kojto 90:cb3d968589d8 808 */
Kojto 90:cb3d968589d8 809
Kojto 90:cb3d968589d8 810 /*!
Kojto 90:cb3d968589d8 811 * @name Register CMT_CMD2, field MB[7:0] (RW)
Kojto 90:cb3d968589d8 812 *
Kojto 90:cb3d968589d8 813 * Controls the lower mark periods of the modulator for all modes.
Kojto 90:cb3d968589d8 814 */
Kojto 90:cb3d968589d8 815 /*@{*/
Kojto 90:cb3d968589d8 816 #define BP_CMT_CMD2_MB (0U) /*!< Bit position for CMT_CMD2_MB. */
Kojto 90:cb3d968589d8 817 #define BM_CMT_CMD2_MB (0xFFU) /*!< Bit mask for CMT_CMD2_MB. */
Kojto 90:cb3d968589d8 818 #define BS_CMT_CMD2_MB (8U) /*!< Bit field size in bits for CMT_CMD2_MB. */
Kojto 90:cb3d968589d8 819
Kojto 90:cb3d968589d8 820 /*! @brief Read current value of the CMT_CMD2_MB field. */
Kojto 90:cb3d968589d8 821 #define BR_CMT_CMD2_MB(x) (HW_CMT_CMD2(x).U)
Kojto 90:cb3d968589d8 822
Kojto 90:cb3d968589d8 823 /*! @brief Format value for bitfield CMT_CMD2_MB. */
Kojto 90:cb3d968589d8 824 #define BF_CMT_CMD2_MB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD2_MB) & BM_CMT_CMD2_MB)
Kojto 90:cb3d968589d8 825
Kojto 90:cb3d968589d8 826 /*! @brief Set the MB field to a new value. */
Kojto 90:cb3d968589d8 827 #define BW_CMT_CMD2_MB(x, v) (HW_CMT_CMD2_WR(x, v))
Kojto 90:cb3d968589d8 828 /*@}*/
Kojto 90:cb3d968589d8 829
Kojto 90:cb3d968589d8 830 /*******************************************************************************
Kojto 90:cb3d968589d8 831 * HW_CMT_CMD3 - CMT Modulator Data Register Space High
Kojto 90:cb3d968589d8 832 ******************************************************************************/
Kojto 90:cb3d968589d8 833
Kojto 90:cb3d968589d8 834 /*!
Kojto 90:cb3d968589d8 835 * @brief HW_CMT_CMD3 - CMT Modulator Data Register Space High (RW)
Kojto 90:cb3d968589d8 836 *
Kojto 90:cb3d968589d8 837 * Reset value: 0x00U
Kojto 90:cb3d968589d8 838 *
Kojto 90:cb3d968589d8 839 * The contents of this register are transferred to the space period register
Kojto 90:cb3d968589d8 840 * upon the completion of a modulation period.
Kojto 90:cb3d968589d8 841 */
Kojto 90:cb3d968589d8 842 typedef union _hw_cmt_cmd3
Kojto 90:cb3d968589d8 843 {
Kojto 90:cb3d968589d8 844 uint8_t U;
Kojto 90:cb3d968589d8 845 struct _hw_cmt_cmd3_bitfields
Kojto 90:cb3d968589d8 846 {
Kojto 90:cb3d968589d8 847 uint8_t SB : 8; /*!< [7:0] */
Kojto 90:cb3d968589d8 848 } B;
Kojto 90:cb3d968589d8 849 } hw_cmt_cmd3_t;
Kojto 90:cb3d968589d8 850
Kojto 90:cb3d968589d8 851 /*!
Kojto 90:cb3d968589d8 852 * @name Constants and macros for entire CMT_CMD3 register
Kojto 90:cb3d968589d8 853 */
Kojto 90:cb3d968589d8 854 /*@{*/
Kojto 90:cb3d968589d8 855 #define HW_CMT_CMD3_ADDR(x) ((x) + 0x8U)
Kojto 90:cb3d968589d8 856
Kojto 90:cb3d968589d8 857 #define HW_CMT_CMD3(x) (*(__IO hw_cmt_cmd3_t *) HW_CMT_CMD3_ADDR(x))
Kojto 90:cb3d968589d8 858 #define HW_CMT_CMD3_RD(x) (HW_CMT_CMD3(x).U)
Kojto 90:cb3d968589d8 859 #define HW_CMT_CMD3_WR(x, v) (HW_CMT_CMD3(x).U = (v))
Kojto 90:cb3d968589d8 860 #define HW_CMT_CMD3_SET(x, v) (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) | (v)))
Kojto 90:cb3d968589d8 861 #define HW_CMT_CMD3_CLR(x, v) (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 862 #define HW_CMT_CMD3_TOG(x, v) (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 863 /*@}*/
Kojto 90:cb3d968589d8 864
Kojto 90:cb3d968589d8 865 /*
Kojto 90:cb3d968589d8 866 * Constants & macros for individual CMT_CMD3 bitfields
Kojto 90:cb3d968589d8 867 */
Kojto 90:cb3d968589d8 868
Kojto 90:cb3d968589d8 869 /*!
Kojto 90:cb3d968589d8 870 * @name Register CMT_CMD3, field SB[7:0] (RW)
Kojto 90:cb3d968589d8 871 *
Kojto 90:cb3d968589d8 872 * Controls the upper space periods of the modulator for all modes.
Kojto 90:cb3d968589d8 873 */
Kojto 90:cb3d968589d8 874 /*@{*/
Kojto 90:cb3d968589d8 875 #define BP_CMT_CMD3_SB (0U) /*!< Bit position for CMT_CMD3_SB. */
Kojto 90:cb3d968589d8 876 #define BM_CMT_CMD3_SB (0xFFU) /*!< Bit mask for CMT_CMD3_SB. */
Kojto 90:cb3d968589d8 877 #define BS_CMT_CMD3_SB (8U) /*!< Bit field size in bits for CMT_CMD3_SB. */
Kojto 90:cb3d968589d8 878
Kojto 90:cb3d968589d8 879 /*! @brief Read current value of the CMT_CMD3_SB field. */
Kojto 90:cb3d968589d8 880 #define BR_CMT_CMD3_SB(x) (HW_CMT_CMD3(x).U)
Kojto 90:cb3d968589d8 881
Kojto 90:cb3d968589d8 882 /*! @brief Format value for bitfield CMT_CMD3_SB. */
Kojto 90:cb3d968589d8 883 #define BF_CMT_CMD3_SB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD3_SB) & BM_CMT_CMD3_SB)
Kojto 90:cb3d968589d8 884
Kojto 90:cb3d968589d8 885 /*! @brief Set the SB field to a new value. */
Kojto 90:cb3d968589d8 886 #define BW_CMT_CMD3_SB(x, v) (HW_CMT_CMD3_WR(x, v))
Kojto 90:cb3d968589d8 887 /*@}*/
Kojto 90:cb3d968589d8 888
Kojto 90:cb3d968589d8 889 /*******************************************************************************
Kojto 90:cb3d968589d8 890 * HW_CMT_CMD4 - CMT Modulator Data Register Space Low
Kojto 90:cb3d968589d8 891 ******************************************************************************/
Kojto 90:cb3d968589d8 892
Kojto 90:cb3d968589d8 893 /*!
Kojto 90:cb3d968589d8 894 * @brief HW_CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
Kojto 90:cb3d968589d8 895 *
Kojto 90:cb3d968589d8 896 * Reset value: 0x00U
Kojto 90:cb3d968589d8 897 *
Kojto 90:cb3d968589d8 898 * The contents of this register are transferred to the space period register
Kojto 90:cb3d968589d8 899 * upon the completion of a modulation period.
Kojto 90:cb3d968589d8 900 */
Kojto 90:cb3d968589d8 901 typedef union _hw_cmt_cmd4
Kojto 90:cb3d968589d8 902 {
Kojto 90:cb3d968589d8 903 uint8_t U;
Kojto 90:cb3d968589d8 904 struct _hw_cmt_cmd4_bitfields
Kojto 90:cb3d968589d8 905 {
Kojto 90:cb3d968589d8 906 uint8_t SB : 8; /*!< [7:0] */
Kojto 90:cb3d968589d8 907 } B;
Kojto 90:cb3d968589d8 908 } hw_cmt_cmd4_t;
Kojto 90:cb3d968589d8 909
Kojto 90:cb3d968589d8 910 /*!
Kojto 90:cb3d968589d8 911 * @name Constants and macros for entire CMT_CMD4 register
Kojto 90:cb3d968589d8 912 */
Kojto 90:cb3d968589d8 913 /*@{*/
Kojto 90:cb3d968589d8 914 #define HW_CMT_CMD4_ADDR(x) ((x) + 0x9U)
Kojto 90:cb3d968589d8 915
Kojto 90:cb3d968589d8 916 #define HW_CMT_CMD4(x) (*(__IO hw_cmt_cmd4_t *) HW_CMT_CMD4_ADDR(x))
Kojto 90:cb3d968589d8 917 #define HW_CMT_CMD4_RD(x) (HW_CMT_CMD4(x).U)
Kojto 90:cb3d968589d8 918 #define HW_CMT_CMD4_WR(x, v) (HW_CMT_CMD4(x).U = (v))
Kojto 90:cb3d968589d8 919 #define HW_CMT_CMD4_SET(x, v) (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) | (v)))
Kojto 90:cb3d968589d8 920 #define HW_CMT_CMD4_CLR(x, v) (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 921 #define HW_CMT_CMD4_TOG(x, v) (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 922 /*@}*/
Kojto 90:cb3d968589d8 923
Kojto 90:cb3d968589d8 924 /*
Kojto 90:cb3d968589d8 925 * Constants & macros for individual CMT_CMD4 bitfields
Kojto 90:cb3d968589d8 926 */
Kojto 90:cb3d968589d8 927
Kojto 90:cb3d968589d8 928 /*!
Kojto 90:cb3d968589d8 929 * @name Register CMT_CMD4, field SB[7:0] (RW)
Kojto 90:cb3d968589d8 930 *
Kojto 90:cb3d968589d8 931 * Controls the lower space periods of the modulator for all modes.
Kojto 90:cb3d968589d8 932 */
Kojto 90:cb3d968589d8 933 /*@{*/
Kojto 90:cb3d968589d8 934 #define BP_CMT_CMD4_SB (0U) /*!< Bit position for CMT_CMD4_SB. */
Kojto 90:cb3d968589d8 935 #define BM_CMT_CMD4_SB (0xFFU) /*!< Bit mask for CMT_CMD4_SB. */
Kojto 90:cb3d968589d8 936 #define BS_CMT_CMD4_SB (8U) /*!< Bit field size in bits for CMT_CMD4_SB. */
Kojto 90:cb3d968589d8 937
Kojto 90:cb3d968589d8 938 /*! @brief Read current value of the CMT_CMD4_SB field. */
Kojto 90:cb3d968589d8 939 #define BR_CMT_CMD4_SB(x) (HW_CMT_CMD4(x).U)
Kojto 90:cb3d968589d8 940
Kojto 90:cb3d968589d8 941 /*! @brief Format value for bitfield CMT_CMD4_SB. */
Kojto 90:cb3d968589d8 942 #define BF_CMT_CMD4_SB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD4_SB) & BM_CMT_CMD4_SB)
Kojto 90:cb3d968589d8 943
Kojto 90:cb3d968589d8 944 /*! @brief Set the SB field to a new value. */
Kojto 90:cb3d968589d8 945 #define BW_CMT_CMD4_SB(x, v) (HW_CMT_CMD4_WR(x, v))
Kojto 90:cb3d968589d8 946 /*@}*/
Kojto 90:cb3d968589d8 947
Kojto 90:cb3d968589d8 948 /*******************************************************************************
Kojto 90:cb3d968589d8 949 * HW_CMT_PPS - CMT Primary Prescaler Register
Kojto 90:cb3d968589d8 950 ******************************************************************************/
Kojto 90:cb3d968589d8 951
Kojto 90:cb3d968589d8 952 /*!
Kojto 90:cb3d968589d8 953 * @brief HW_CMT_PPS - CMT Primary Prescaler Register (RW)
Kojto 90:cb3d968589d8 954 *
Kojto 90:cb3d968589d8 955 * Reset value: 0x00U
Kojto 90:cb3d968589d8 956 *
Kojto 90:cb3d968589d8 957 * This register is used to set the Primary Prescaler Divider field (PPSDIV).
Kojto 90:cb3d968589d8 958 */
Kojto 90:cb3d968589d8 959 typedef union _hw_cmt_pps
Kojto 90:cb3d968589d8 960 {
Kojto 90:cb3d968589d8 961 uint8_t U;
Kojto 90:cb3d968589d8 962 struct _hw_cmt_pps_bitfields
Kojto 90:cb3d968589d8 963 {
Kojto 90:cb3d968589d8 964 uint8_t PPSDIV : 4; /*!< [3:0] Primary Prescaler Divider */
Kojto 90:cb3d968589d8 965 uint8_t RESERVED0 : 4; /*!< [7:4] */
Kojto 90:cb3d968589d8 966 } B;
Kojto 90:cb3d968589d8 967 } hw_cmt_pps_t;
Kojto 90:cb3d968589d8 968
Kojto 90:cb3d968589d8 969 /*!
Kojto 90:cb3d968589d8 970 * @name Constants and macros for entire CMT_PPS register
Kojto 90:cb3d968589d8 971 */
Kojto 90:cb3d968589d8 972 /*@{*/
Kojto 90:cb3d968589d8 973 #define HW_CMT_PPS_ADDR(x) ((x) + 0xAU)
Kojto 90:cb3d968589d8 974
Kojto 90:cb3d968589d8 975 #define HW_CMT_PPS(x) (*(__IO hw_cmt_pps_t *) HW_CMT_PPS_ADDR(x))
Kojto 90:cb3d968589d8 976 #define HW_CMT_PPS_RD(x) (HW_CMT_PPS(x).U)
Kojto 90:cb3d968589d8 977 #define HW_CMT_PPS_WR(x, v) (HW_CMT_PPS(x).U = (v))
Kojto 90:cb3d968589d8 978 #define HW_CMT_PPS_SET(x, v) (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) | (v)))
Kojto 90:cb3d968589d8 979 #define HW_CMT_PPS_CLR(x, v) (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 980 #define HW_CMT_PPS_TOG(x, v) (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 981 /*@}*/
Kojto 90:cb3d968589d8 982
Kojto 90:cb3d968589d8 983 /*
Kojto 90:cb3d968589d8 984 * Constants & macros for individual CMT_PPS bitfields
Kojto 90:cb3d968589d8 985 */
Kojto 90:cb3d968589d8 986
Kojto 90:cb3d968589d8 987 /*!
Kojto 90:cb3d968589d8 988 * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
Kojto 90:cb3d968589d8 989 *
Kojto 90:cb3d968589d8 990 * Divides the CMT clock to generate the Intermediate Frequency clock enable to
Kojto 90:cb3d968589d8 991 * the secondary prescaler.
Kojto 90:cb3d968589d8 992 *
Kojto 90:cb3d968589d8 993 * Values:
Kojto 90:cb3d968589d8 994 * - 0000 - Bus clock * 1
Kojto 90:cb3d968589d8 995 * - 0001 - Bus clock * 2
Kojto 90:cb3d968589d8 996 * - 0010 - Bus clock * 3
Kojto 90:cb3d968589d8 997 * - 0011 - Bus clock * 4
Kojto 90:cb3d968589d8 998 * - 0100 - Bus clock * 5
Kojto 90:cb3d968589d8 999 * - 0101 - Bus clock * 6
Kojto 90:cb3d968589d8 1000 * - 0110 - Bus clock * 7
Kojto 90:cb3d968589d8 1001 * - 0111 - Bus clock * 8
Kojto 90:cb3d968589d8 1002 * - 1000 - Bus clock * 9
Kojto 90:cb3d968589d8 1003 * - 1001 - Bus clock * 10
Kojto 90:cb3d968589d8 1004 * - 1010 - Bus clock * 11
Kojto 90:cb3d968589d8 1005 * - 1011 - Bus clock * 12
Kojto 90:cb3d968589d8 1006 * - 1100 - Bus clock * 13
Kojto 90:cb3d968589d8 1007 * - 1101 - Bus clock * 14
Kojto 90:cb3d968589d8 1008 * - 1110 - Bus clock * 15
Kojto 90:cb3d968589d8 1009 * - 1111 - Bus clock * 16
Kojto 90:cb3d968589d8 1010 */
Kojto 90:cb3d968589d8 1011 /*@{*/
Kojto 90:cb3d968589d8 1012 #define BP_CMT_PPS_PPSDIV (0U) /*!< Bit position for CMT_PPS_PPSDIV. */
Kojto 90:cb3d968589d8 1013 #define BM_CMT_PPS_PPSDIV (0x0FU) /*!< Bit mask for CMT_PPS_PPSDIV. */
Kojto 90:cb3d968589d8 1014 #define BS_CMT_PPS_PPSDIV (4U) /*!< Bit field size in bits for CMT_PPS_PPSDIV. */
Kojto 90:cb3d968589d8 1015
Kojto 90:cb3d968589d8 1016 /*! @brief Read current value of the CMT_PPS_PPSDIV field. */
Kojto 90:cb3d968589d8 1017 #define BR_CMT_PPS_PPSDIV(x) (HW_CMT_PPS(x).B.PPSDIV)
Kojto 90:cb3d968589d8 1018
Kojto 90:cb3d968589d8 1019 /*! @brief Format value for bitfield CMT_PPS_PPSDIV. */
Kojto 90:cb3d968589d8 1020 #define BF_CMT_PPS_PPSDIV(v) ((uint8_t)((uint8_t)(v) << BP_CMT_PPS_PPSDIV) & BM_CMT_PPS_PPSDIV)
Kojto 90:cb3d968589d8 1021
Kojto 90:cb3d968589d8 1022 /*! @brief Set the PPSDIV field to a new value. */
Kojto 90:cb3d968589d8 1023 #define BW_CMT_PPS_PPSDIV(x, v) (HW_CMT_PPS_WR(x, (HW_CMT_PPS_RD(x) & ~BM_CMT_PPS_PPSDIV) | BF_CMT_PPS_PPSDIV(v)))
Kojto 90:cb3d968589d8 1024 /*@}*/
Kojto 90:cb3d968589d8 1025
Kojto 90:cb3d968589d8 1026 /*******************************************************************************
Kojto 90:cb3d968589d8 1027 * HW_CMT_DMA - CMT Direct Memory Access Register
Kojto 90:cb3d968589d8 1028 ******************************************************************************/
Kojto 90:cb3d968589d8 1029
Kojto 90:cb3d968589d8 1030 /*!
Kojto 90:cb3d968589d8 1031 * @brief HW_CMT_DMA - CMT Direct Memory Access Register (RW)
Kojto 90:cb3d968589d8 1032 *
Kojto 90:cb3d968589d8 1033 * Reset value: 0x00U
Kojto 90:cb3d968589d8 1034 *
Kojto 90:cb3d968589d8 1035 * This register is used to enable/disable direct memory access (DMA).
Kojto 90:cb3d968589d8 1036 */
Kojto 90:cb3d968589d8 1037 typedef union _hw_cmt_dma
Kojto 90:cb3d968589d8 1038 {
Kojto 90:cb3d968589d8 1039 uint8_t U;
Kojto 90:cb3d968589d8 1040 struct _hw_cmt_dma_bitfields
Kojto 90:cb3d968589d8 1041 {
Kojto 90:cb3d968589d8 1042 uint8_t DMA : 1; /*!< [0] DMA Enable */
Kojto 90:cb3d968589d8 1043 uint8_t RESERVED0 : 7; /*!< [7:1] */
Kojto 90:cb3d968589d8 1044 } B;
Kojto 90:cb3d968589d8 1045 } hw_cmt_dma_t;
Kojto 90:cb3d968589d8 1046
Kojto 90:cb3d968589d8 1047 /*!
Kojto 90:cb3d968589d8 1048 * @name Constants and macros for entire CMT_DMA register
Kojto 90:cb3d968589d8 1049 */
Kojto 90:cb3d968589d8 1050 /*@{*/
Kojto 90:cb3d968589d8 1051 #define HW_CMT_DMA_ADDR(x) ((x) + 0xBU)
Kojto 90:cb3d968589d8 1052
Kojto 90:cb3d968589d8 1053 #define HW_CMT_DMA(x) (*(__IO hw_cmt_dma_t *) HW_CMT_DMA_ADDR(x))
Kojto 90:cb3d968589d8 1054 #define HW_CMT_DMA_RD(x) (HW_CMT_DMA(x).U)
Kojto 90:cb3d968589d8 1055 #define HW_CMT_DMA_WR(x, v) (HW_CMT_DMA(x).U = (v))
Kojto 90:cb3d968589d8 1056 #define HW_CMT_DMA_SET(x, v) (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) | (v)))
Kojto 90:cb3d968589d8 1057 #define HW_CMT_DMA_CLR(x, v) (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 1058 #define HW_CMT_DMA_TOG(x, v) (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 1059 /*@}*/
Kojto 90:cb3d968589d8 1060
Kojto 90:cb3d968589d8 1061 /*
Kojto 90:cb3d968589d8 1062 * Constants & macros for individual CMT_DMA bitfields
Kojto 90:cb3d968589d8 1063 */
Kojto 90:cb3d968589d8 1064
Kojto 90:cb3d968589d8 1065 /*!
Kojto 90:cb3d968589d8 1066 * @name Register CMT_DMA, field DMA[0] (RW)
Kojto 90:cb3d968589d8 1067 *
Kojto 90:cb3d968589d8 1068 * Enables the DMA protocol.
Kojto 90:cb3d968589d8 1069 *
Kojto 90:cb3d968589d8 1070 * Values:
Kojto 90:cb3d968589d8 1071 * - 0 - DMA transfer request and done are disabled.
Kojto 90:cb3d968589d8 1072 * - 1 - DMA transfer request and done are enabled.
Kojto 90:cb3d968589d8 1073 */
Kojto 90:cb3d968589d8 1074 /*@{*/
Kojto 90:cb3d968589d8 1075 #define BP_CMT_DMA_DMA (0U) /*!< Bit position for CMT_DMA_DMA. */
Kojto 90:cb3d968589d8 1076 #define BM_CMT_DMA_DMA (0x01U) /*!< Bit mask for CMT_DMA_DMA. */
Kojto 90:cb3d968589d8 1077 #define BS_CMT_DMA_DMA (1U) /*!< Bit field size in bits for CMT_DMA_DMA. */
Kojto 90:cb3d968589d8 1078
Kojto 90:cb3d968589d8 1079 /*! @brief Read current value of the CMT_DMA_DMA field. */
Kojto 90:cb3d968589d8 1080 #define BR_CMT_DMA_DMA(x) (BITBAND_ACCESS8(HW_CMT_DMA_ADDR(x), BP_CMT_DMA_DMA))
Kojto 90:cb3d968589d8 1081
Kojto 90:cb3d968589d8 1082 /*! @brief Format value for bitfield CMT_DMA_DMA. */
Kojto 90:cb3d968589d8 1083 #define BF_CMT_DMA_DMA(v) ((uint8_t)((uint8_t)(v) << BP_CMT_DMA_DMA) & BM_CMT_DMA_DMA)
Kojto 90:cb3d968589d8 1084
Kojto 90:cb3d968589d8 1085 /*! @brief Set the DMA field to a new value. */
Kojto 90:cb3d968589d8 1086 #define BW_CMT_DMA_DMA(x, v) (BITBAND_ACCESS8(HW_CMT_DMA_ADDR(x), BP_CMT_DMA_DMA) = (v))
Kojto 90:cb3d968589d8 1087 /*@}*/
Kojto 90:cb3d968589d8 1088
Kojto 90:cb3d968589d8 1089 /*******************************************************************************
Kojto 90:cb3d968589d8 1090 * hw_cmt_t - module struct
Kojto 90:cb3d968589d8 1091 ******************************************************************************/
Kojto 90:cb3d968589d8 1092 /*!
Kojto 90:cb3d968589d8 1093 * @brief All CMT module registers.
Kojto 90:cb3d968589d8 1094 */
Kojto 90:cb3d968589d8 1095 #pragma pack(1)
Kojto 90:cb3d968589d8 1096 typedef struct _hw_cmt
Kojto 90:cb3d968589d8 1097 {
Kojto 90:cb3d968589d8 1098 __IO hw_cmt_cgh1_t CGH1; /*!< [0x0] CMT Carrier Generator High Data Register 1 */
Kojto 90:cb3d968589d8 1099 __IO hw_cmt_cgl1_t CGL1; /*!< [0x1] CMT Carrier Generator Low Data Register 1 */
Kojto 90:cb3d968589d8 1100 __IO hw_cmt_cgh2_t CGH2; /*!< [0x2] CMT Carrier Generator High Data Register 2 */
Kojto 90:cb3d968589d8 1101 __IO hw_cmt_cgl2_t CGL2; /*!< [0x3] CMT Carrier Generator Low Data Register 2 */
Kojto 90:cb3d968589d8 1102 __IO hw_cmt_oc_t OC; /*!< [0x4] CMT Output Control Register */
Kojto 90:cb3d968589d8 1103 __IO hw_cmt_msc_t MSC; /*!< [0x5] CMT Modulator Status and Control Register */
Kojto 90:cb3d968589d8 1104 __IO hw_cmt_cmd1_t CMD1; /*!< [0x6] CMT Modulator Data Register Mark High */
Kojto 90:cb3d968589d8 1105 __IO hw_cmt_cmd2_t CMD2; /*!< [0x7] CMT Modulator Data Register Mark Low */
Kojto 90:cb3d968589d8 1106 __IO hw_cmt_cmd3_t CMD3; /*!< [0x8] CMT Modulator Data Register Space High */
Kojto 90:cb3d968589d8 1107 __IO hw_cmt_cmd4_t CMD4; /*!< [0x9] CMT Modulator Data Register Space Low */
Kojto 90:cb3d968589d8 1108 __IO hw_cmt_pps_t PPS; /*!< [0xA] CMT Primary Prescaler Register */
Kojto 90:cb3d968589d8 1109 __IO hw_cmt_dma_t DMA; /*!< [0xB] CMT Direct Memory Access Register */
Kojto 90:cb3d968589d8 1110 } hw_cmt_t;
Kojto 90:cb3d968589d8 1111 #pragma pack()
Kojto 90:cb3d968589d8 1112
Kojto 90:cb3d968589d8 1113 /*! @brief Macro to access all CMT registers. */
Kojto 90:cb3d968589d8 1114 /*! @param x CMT module instance base address. */
Kojto 90:cb3d968589d8 1115 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 1116 * use the '&' operator, like <code>&HW_CMT(CMT_BASE)</code>. */
Kojto 90:cb3d968589d8 1117 #define HW_CMT(x) (*(hw_cmt_t *)(x))
Kojto 90:cb3d968589d8 1118
Kojto 90:cb3d968589d8 1119 #endif /* __HW_CMT_REGISTERS_H__ */
Kojto 90:cb3d968589d8 1120 /* EOF */