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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_axbs.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_AXBS_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_AXBS_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 AXBS
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * Crossbar switch
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_AXBS_PRSn - Priority Registers Slave
Kojto 90:cb3d968589d8 93 * - HW_AXBS_CRSn - Control Register
Kojto 90:cb3d968589d8 94 * - HW_AXBS_MGPCR0 - Master General Purpose Control Register
Kojto 90:cb3d968589d8 95 * - HW_AXBS_MGPCR1 - Master General Purpose Control Register
Kojto 90:cb3d968589d8 96 * - HW_AXBS_MGPCR2 - Master General Purpose Control Register
Kojto 90:cb3d968589d8 97 * - HW_AXBS_MGPCR3 - Master General Purpose Control Register
Kojto 90:cb3d968589d8 98 * - HW_AXBS_MGPCR4 - Master General Purpose Control Register
Kojto 90:cb3d968589d8 99 * - HW_AXBS_MGPCR5 - Master General Purpose Control Register
Kojto 90:cb3d968589d8 100 *
Kojto 90:cb3d968589d8 101 * - hw_axbs_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 102 */
Kojto 90:cb3d968589d8 103
Kojto 90:cb3d968589d8 104 #define HW_AXBS_INSTANCE_COUNT (1U) /*!< Number of instances of the AXBS module. */
Kojto 90:cb3d968589d8 105
Kojto 90:cb3d968589d8 106 /*******************************************************************************
Kojto 90:cb3d968589d8 107 * HW_AXBS_PRSn - Priority Registers Slave
Kojto 90:cb3d968589d8 108 ******************************************************************************/
Kojto 90:cb3d968589d8 109
Kojto 90:cb3d968589d8 110 /*!
Kojto 90:cb3d968589d8 111 * @brief HW_AXBS_PRSn - Priority Registers Slave (RW)
Kojto 90:cb3d968589d8 112 *
Kojto 90:cb3d968589d8 113 * Reset value: 0x00543210U
Kojto 90:cb3d968589d8 114 *
Kojto 90:cb3d968589d8 115 * The priority registers (PRSn) set the priority of each master port on a per
Kojto 90:cb3d968589d8 116 * slave port basis and reside in each slave port. The priority register can be
Kojto 90:cb3d968589d8 117 * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
Kojto 90:cb3d968589d8 118 * register can only be read; attempts to write to it have no effect on PRSn and
Kojto 90:cb3d968589d8 119 * result in a bus-error response to the master initiating the write. Two available
Kojto 90:cb3d968589d8 120 * masters must not be programmed with the same priority level. Attempts to
Kojto 90:cb3d968589d8 121 * program two or more masters with the same priority level result in a bus-error
Kojto 90:cb3d968589d8 122 * response and the PRSn is not updated. Valid values for the Mn priority fields
Kojto 90:cb3d968589d8 123 * depend on which masters are available on the chip. This information can be found in
Kojto 90:cb3d968589d8 124 * the chip-specific information for the crossbar. If the chip contains less
Kojto 90:cb3d968589d8 125 * than five masters, values 0 to 3 are valid. Writing other values will result in
Kojto 90:cb3d968589d8 126 * an error. If the chip contains five or more masters, valid values are 0 to n-1,
Kojto 90:cb3d968589d8 127 * where n is the number of masters attached to the AXBS module. Other values
Kojto 90:cb3d968589d8 128 * will result in an error.
Kojto 90:cb3d968589d8 129 */
Kojto 90:cb3d968589d8 130 typedef union _hw_axbs_prsn
Kojto 90:cb3d968589d8 131 {
Kojto 90:cb3d968589d8 132 uint32_t U;
Kojto 90:cb3d968589d8 133 struct _hw_axbs_prsn_bitfields
Kojto 90:cb3d968589d8 134 {
Kojto 90:cb3d968589d8 135 uint32_t M0 : 3; /*!< [2:0] Master 0 Priority. Sets the arbitration
Kojto 90:cb3d968589d8 136 * priority for this port on the associated slave port. */
Kojto 90:cb3d968589d8 137 uint32_t RESERVED0 : 1; /*!< [3] */
Kojto 90:cb3d968589d8 138 uint32_t M1 : 3; /*!< [6:4] Master 1 Priority. Sets the arbitration
Kojto 90:cb3d968589d8 139 * priority for this port on the associated slave port. */
Kojto 90:cb3d968589d8 140 uint32_t RESERVED1 : 1; /*!< [7] */
Kojto 90:cb3d968589d8 141 uint32_t M2 : 3; /*!< [10:8] Master 2 Priority. Sets the arbitration
Kojto 90:cb3d968589d8 142 * priority for this port on the associated slave port. */
Kojto 90:cb3d968589d8 143 uint32_t RESERVED2 : 1; /*!< [11] */
Kojto 90:cb3d968589d8 144 uint32_t M3 : 3; /*!< [14:12] Master 3 Priority. Sets the arbitration
Kojto 90:cb3d968589d8 145 * priority for this port on the associated slave port. */
Kojto 90:cb3d968589d8 146 uint32_t RESERVED3 : 1; /*!< [15] */
Kojto 90:cb3d968589d8 147 uint32_t M4 : 3; /*!< [18:16] Master 4 Priority. Sets the arbitration
Kojto 90:cb3d968589d8 148 * priority for this port on the associated slave port. */
Kojto 90:cb3d968589d8 149 uint32_t RESERVED4 : 1; /*!< [19] */
Kojto 90:cb3d968589d8 150 uint32_t M5 : 3; /*!< [22:20] Master 5 Priority. Sets the arbitration
Kojto 90:cb3d968589d8 151 * priority for this port on the associated slave port. */
Kojto 90:cb3d968589d8 152 uint32_t RESERVED5 : 9; /*!< [31:23] */
Kojto 90:cb3d968589d8 153 } B;
Kojto 90:cb3d968589d8 154 } hw_axbs_prsn_t;
Kojto 90:cb3d968589d8 155
Kojto 90:cb3d968589d8 156 /*!
Kojto 90:cb3d968589d8 157 * @name Constants and macros for entire AXBS_PRSn register
Kojto 90:cb3d968589d8 158 */
Kojto 90:cb3d968589d8 159 /*@{*/
Kojto 90:cb3d968589d8 160 #define HW_AXBS_PRSn_COUNT (5U)
Kojto 90:cb3d968589d8 161
Kojto 90:cb3d968589d8 162 #define HW_AXBS_PRSn_ADDR(x, n) ((x) + 0x0U + (0x100U * (n)))
Kojto 90:cb3d968589d8 163
Kojto 90:cb3d968589d8 164 #define HW_AXBS_PRSn(x, n) (*(__IO hw_axbs_prsn_t *) HW_AXBS_PRSn_ADDR(x, n))
Kojto 90:cb3d968589d8 165 #define HW_AXBS_PRSn_RD(x, n) (HW_AXBS_PRSn(x, n).U)
Kojto 90:cb3d968589d8 166 #define HW_AXBS_PRSn_WR(x, n, v) (HW_AXBS_PRSn(x, n).U = (v))
Kojto 90:cb3d968589d8 167 #define HW_AXBS_PRSn_SET(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 168 #define HW_AXBS_PRSn_CLR(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 169 #define HW_AXBS_PRSn_TOG(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 170 /*@}*/
Kojto 90:cb3d968589d8 171
Kojto 90:cb3d968589d8 172 /*
Kojto 90:cb3d968589d8 173 * Constants & macros for individual AXBS_PRSn bitfields
Kojto 90:cb3d968589d8 174 */
Kojto 90:cb3d968589d8 175
Kojto 90:cb3d968589d8 176 /*!
Kojto 90:cb3d968589d8 177 * @name Register AXBS_PRSn, field M0[2:0] (RW)
Kojto 90:cb3d968589d8 178 *
Kojto 90:cb3d968589d8 179 * Values:
Kojto 90:cb3d968589d8 180 * - 000 - This master has level 1, or highest, priority when accessing the
Kojto 90:cb3d968589d8 181 * slave port.
Kojto 90:cb3d968589d8 182 * - 001 - This master has level 2 priority when accessing the slave port.
Kojto 90:cb3d968589d8 183 * - 010 - This master has level 3 priority when accessing the slave port.
Kojto 90:cb3d968589d8 184 * - 011 - This master has level 4 priority when accessing the slave port.
Kojto 90:cb3d968589d8 185 * - 100 - This master has level 5 priority when accessing the slave port.
Kojto 90:cb3d968589d8 186 * - 101 - This master has level 6 priority when accessing the slave port.
Kojto 90:cb3d968589d8 187 * - 110 - This master has level 7 priority when accessing the slave port.
Kojto 90:cb3d968589d8 188 * - 111 - This master has level 8, or lowest, priority when accessing the slave
Kojto 90:cb3d968589d8 189 * port.
Kojto 90:cb3d968589d8 190 */
Kojto 90:cb3d968589d8 191 /*@{*/
Kojto 90:cb3d968589d8 192 #define BP_AXBS_PRSn_M0 (0U) /*!< Bit position for AXBS_PRSn_M0. */
Kojto 90:cb3d968589d8 193 #define BM_AXBS_PRSn_M0 (0x00000007U) /*!< Bit mask for AXBS_PRSn_M0. */
Kojto 90:cb3d968589d8 194 #define BS_AXBS_PRSn_M0 (3U) /*!< Bit field size in bits for AXBS_PRSn_M0. */
Kojto 90:cb3d968589d8 195
Kojto 90:cb3d968589d8 196 /*! @brief Read current value of the AXBS_PRSn_M0 field. */
Kojto 90:cb3d968589d8 197 #define BR_AXBS_PRSn_M0(x, n) (HW_AXBS_PRSn(x, n).B.M0)
Kojto 90:cb3d968589d8 198
Kojto 90:cb3d968589d8 199 /*! @brief Format value for bitfield AXBS_PRSn_M0. */
Kojto 90:cb3d968589d8 200 #define BF_AXBS_PRSn_M0(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M0) & BM_AXBS_PRSn_M0)
Kojto 90:cb3d968589d8 201
Kojto 90:cb3d968589d8 202 /*! @brief Set the M0 field to a new value. */
Kojto 90:cb3d968589d8 203 #define BW_AXBS_PRSn_M0(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M0) | BF_AXBS_PRSn_M0(v)))
Kojto 90:cb3d968589d8 204 /*@}*/
Kojto 90:cb3d968589d8 205
Kojto 90:cb3d968589d8 206 /*!
Kojto 90:cb3d968589d8 207 * @name Register AXBS_PRSn, field M1[6:4] (RW)
Kojto 90:cb3d968589d8 208 *
Kojto 90:cb3d968589d8 209 * Values:
Kojto 90:cb3d968589d8 210 * - 000 - This master has level 1, or highest, priority when accessing the
Kojto 90:cb3d968589d8 211 * slave port.
Kojto 90:cb3d968589d8 212 * - 001 - This master has level 2 priority when accessing the slave port.
Kojto 90:cb3d968589d8 213 * - 010 - This master has level 3 priority when accessing the slave port.
Kojto 90:cb3d968589d8 214 * - 011 - This master has level 4 priority when accessing the slave port.
Kojto 90:cb3d968589d8 215 * - 100 - This master has level 5 priority when accessing the slave port.
Kojto 90:cb3d968589d8 216 * - 101 - This master has level 6 priority when accessing the slave port.
Kojto 90:cb3d968589d8 217 * - 110 - This master has level 7 priority when accessing the slave port.
Kojto 90:cb3d968589d8 218 * - 111 - This master has level 8, or lowest, priority when accessing the slave
Kojto 90:cb3d968589d8 219 * port.
Kojto 90:cb3d968589d8 220 */
Kojto 90:cb3d968589d8 221 /*@{*/
Kojto 90:cb3d968589d8 222 #define BP_AXBS_PRSn_M1 (4U) /*!< Bit position for AXBS_PRSn_M1. */
Kojto 90:cb3d968589d8 223 #define BM_AXBS_PRSn_M1 (0x00000070U) /*!< Bit mask for AXBS_PRSn_M1. */
Kojto 90:cb3d968589d8 224 #define BS_AXBS_PRSn_M1 (3U) /*!< Bit field size in bits for AXBS_PRSn_M1. */
Kojto 90:cb3d968589d8 225
Kojto 90:cb3d968589d8 226 /*! @brief Read current value of the AXBS_PRSn_M1 field. */
Kojto 90:cb3d968589d8 227 #define BR_AXBS_PRSn_M1(x, n) (HW_AXBS_PRSn(x, n).B.M1)
Kojto 90:cb3d968589d8 228
Kojto 90:cb3d968589d8 229 /*! @brief Format value for bitfield AXBS_PRSn_M1. */
Kojto 90:cb3d968589d8 230 #define BF_AXBS_PRSn_M1(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M1) & BM_AXBS_PRSn_M1)
Kojto 90:cb3d968589d8 231
Kojto 90:cb3d968589d8 232 /*! @brief Set the M1 field to a new value. */
Kojto 90:cb3d968589d8 233 #define BW_AXBS_PRSn_M1(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M1) | BF_AXBS_PRSn_M1(v)))
Kojto 90:cb3d968589d8 234 /*@}*/
Kojto 90:cb3d968589d8 235
Kojto 90:cb3d968589d8 236 /*!
Kojto 90:cb3d968589d8 237 * @name Register AXBS_PRSn, field M2[10:8] (RW)
Kojto 90:cb3d968589d8 238 *
Kojto 90:cb3d968589d8 239 * Values:
Kojto 90:cb3d968589d8 240 * - 000 - This master has level 1, or highest, priority when accessing the
Kojto 90:cb3d968589d8 241 * slave port.
Kojto 90:cb3d968589d8 242 * - 001 - This master has level 2 priority when accessing the slave port.
Kojto 90:cb3d968589d8 243 * - 010 - This master has level 3 priority when accessing the slave port.
Kojto 90:cb3d968589d8 244 * - 011 - This master has level 4 priority when accessing the slave port.
Kojto 90:cb3d968589d8 245 * - 100 - This master has level 5 priority when accessing the slave port.
Kojto 90:cb3d968589d8 246 * - 101 - This master has level 6 priority when accessing the slave port.
Kojto 90:cb3d968589d8 247 * - 110 - This master has level 7 priority when accessing the slave port.
Kojto 90:cb3d968589d8 248 * - 111 - This master has level 8, or lowest, priority when accessing the slave
Kojto 90:cb3d968589d8 249 * port.
Kojto 90:cb3d968589d8 250 */
Kojto 90:cb3d968589d8 251 /*@{*/
Kojto 90:cb3d968589d8 252 #define BP_AXBS_PRSn_M2 (8U) /*!< Bit position for AXBS_PRSn_M2. */
Kojto 90:cb3d968589d8 253 #define BM_AXBS_PRSn_M2 (0x00000700U) /*!< Bit mask for AXBS_PRSn_M2. */
Kojto 90:cb3d968589d8 254 #define BS_AXBS_PRSn_M2 (3U) /*!< Bit field size in bits for AXBS_PRSn_M2. */
Kojto 90:cb3d968589d8 255
Kojto 90:cb3d968589d8 256 /*! @brief Read current value of the AXBS_PRSn_M2 field. */
Kojto 90:cb3d968589d8 257 #define BR_AXBS_PRSn_M2(x, n) (HW_AXBS_PRSn(x, n).B.M2)
Kojto 90:cb3d968589d8 258
Kojto 90:cb3d968589d8 259 /*! @brief Format value for bitfield AXBS_PRSn_M2. */
Kojto 90:cb3d968589d8 260 #define BF_AXBS_PRSn_M2(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M2) & BM_AXBS_PRSn_M2)
Kojto 90:cb3d968589d8 261
Kojto 90:cb3d968589d8 262 /*! @brief Set the M2 field to a new value. */
Kojto 90:cb3d968589d8 263 #define BW_AXBS_PRSn_M2(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M2) | BF_AXBS_PRSn_M2(v)))
Kojto 90:cb3d968589d8 264 /*@}*/
Kojto 90:cb3d968589d8 265
Kojto 90:cb3d968589d8 266 /*!
Kojto 90:cb3d968589d8 267 * @name Register AXBS_PRSn, field M3[14:12] (RW)
Kojto 90:cb3d968589d8 268 *
Kojto 90:cb3d968589d8 269 * Values:
Kojto 90:cb3d968589d8 270 * - 000 - This master has level 1, or highest, priority when accessing the
Kojto 90:cb3d968589d8 271 * slave port.
Kojto 90:cb3d968589d8 272 * - 001 - This master has level 2 priority when accessing the slave port.
Kojto 90:cb3d968589d8 273 * - 010 - This master has level 3 priority when accessing the slave port.
Kojto 90:cb3d968589d8 274 * - 011 - This master has level 4 priority when accessing the slave port.
Kojto 90:cb3d968589d8 275 * - 100 - This master has level 5 priority when accessing the slave port.
Kojto 90:cb3d968589d8 276 * - 101 - This master has level 6 priority when accessing the slave port.
Kojto 90:cb3d968589d8 277 * - 110 - This master has level 7 priority when accessing the slave port.
Kojto 90:cb3d968589d8 278 * - 111 - This master has level 8, or lowest, priority when accessing the slave
Kojto 90:cb3d968589d8 279 * port.
Kojto 90:cb3d968589d8 280 */
Kojto 90:cb3d968589d8 281 /*@{*/
Kojto 90:cb3d968589d8 282 #define BP_AXBS_PRSn_M3 (12U) /*!< Bit position for AXBS_PRSn_M3. */
Kojto 90:cb3d968589d8 283 #define BM_AXBS_PRSn_M3 (0x00007000U) /*!< Bit mask for AXBS_PRSn_M3. */
Kojto 90:cb3d968589d8 284 #define BS_AXBS_PRSn_M3 (3U) /*!< Bit field size in bits for AXBS_PRSn_M3. */
Kojto 90:cb3d968589d8 285
Kojto 90:cb3d968589d8 286 /*! @brief Read current value of the AXBS_PRSn_M3 field. */
Kojto 90:cb3d968589d8 287 #define BR_AXBS_PRSn_M3(x, n) (HW_AXBS_PRSn(x, n).B.M3)
Kojto 90:cb3d968589d8 288
Kojto 90:cb3d968589d8 289 /*! @brief Format value for bitfield AXBS_PRSn_M3. */
Kojto 90:cb3d968589d8 290 #define BF_AXBS_PRSn_M3(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M3) & BM_AXBS_PRSn_M3)
Kojto 90:cb3d968589d8 291
Kojto 90:cb3d968589d8 292 /*! @brief Set the M3 field to a new value. */
Kojto 90:cb3d968589d8 293 #define BW_AXBS_PRSn_M3(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M3) | BF_AXBS_PRSn_M3(v)))
Kojto 90:cb3d968589d8 294 /*@}*/
Kojto 90:cb3d968589d8 295
Kojto 90:cb3d968589d8 296 /*!
Kojto 90:cb3d968589d8 297 * @name Register AXBS_PRSn, field M4[18:16] (RW)
Kojto 90:cb3d968589d8 298 *
Kojto 90:cb3d968589d8 299 * Values:
Kojto 90:cb3d968589d8 300 * - 000 - This master has level 1, or highest, priority when accessing the
Kojto 90:cb3d968589d8 301 * slave port.
Kojto 90:cb3d968589d8 302 * - 001 - This master has level 2 priority when accessing the slave port.
Kojto 90:cb3d968589d8 303 * - 010 - This master has level 3 priority when accessing the slave port.
Kojto 90:cb3d968589d8 304 * - 011 - This master has level 4 priority when accessing the slave port.
Kojto 90:cb3d968589d8 305 * - 100 - This master has level 5 priority when accessing the slave port.
Kojto 90:cb3d968589d8 306 * - 101 - This master has level 6 priority when accessing the slave port.
Kojto 90:cb3d968589d8 307 * - 110 - This master has level 7 priority when accessing the slave port.
Kojto 90:cb3d968589d8 308 * - 111 - This master has level 8, or lowest, priority when accessing the slave
Kojto 90:cb3d968589d8 309 * port.
Kojto 90:cb3d968589d8 310 */
Kojto 90:cb3d968589d8 311 /*@{*/
Kojto 90:cb3d968589d8 312 #define BP_AXBS_PRSn_M4 (16U) /*!< Bit position for AXBS_PRSn_M4. */
Kojto 90:cb3d968589d8 313 #define BM_AXBS_PRSn_M4 (0x00070000U) /*!< Bit mask for AXBS_PRSn_M4. */
Kojto 90:cb3d968589d8 314 #define BS_AXBS_PRSn_M4 (3U) /*!< Bit field size in bits for AXBS_PRSn_M4. */
Kojto 90:cb3d968589d8 315
Kojto 90:cb3d968589d8 316 /*! @brief Read current value of the AXBS_PRSn_M4 field. */
Kojto 90:cb3d968589d8 317 #define BR_AXBS_PRSn_M4(x, n) (HW_AXBS_PRSn(x, n).B.M4)
Kojto 90:cb3d968589d8 318
Kojto 90:cb3d968589d8 319 /*! @brief Format value for bitfield AXBS_PRSn_M4. */
Kojto 90:cb3d968589d8 320 #define BF_AXBS_PRSn_M4(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M4) & BM_AXBS_PRSn_M4)
Kojto 90:cb3d968589d8 321
Kojto 90:cb3d968589d8 322 /*! @brief Set the M4 field to a new value. */
Kojto 90:cb3d968589d8 323 #define BW_AXBS_PRSn_M4(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M4) | BF_AXBS_PRSn_M4(v)))
Kojto 90:cb3d968589d8 324 /*@}*/
Kojto 90:cb3d968589d8 325
Kojto 90:cb3d968589d8 326 /*!
Kojto 90:cb3d968589d8 327 * @name Register AXBS_PRSn, field M5[22:20] (RW)
Kojto 90:cb3d968589d8 328 *
Kojto 90:cb3d968589d8 329 * Values:
Kojto 90:cb3d968589d8 330 * - 000 - This master has level 1, or highest, priority when accessing the
Kojto 90:cb3d968589d8 331 * slave port.
Kojto 90:cb3d968589d8 332 * - 001 - This master has level 2 priority when accessing the slave port.
Kojto 90:cb3d968589d8 333 * - 010 - This master has level 3 priority when accessing the slave port.
Kojto 90:cb3d968589d8 334 * - 011 - This master has level 4 priority when accessing the slave port.
Kojto 90:cb3d968589d8 335 * - 100 - This master has level 5 priority when accessing the slave port.
Kojto 90:cb3d968589d8 336 * - 101 - This master has level 6 priority when accessing the slave port.
Kojto 90:cb3d968589d8 337 * - 110 - This master has level 7 priority when accessing the slave port.
Kojto 90:cb3d968589d8 338 * - 111 - This master has level 8, or lowest, priority when accessing the slave
Kojto 90:cb3d968589d8 339 * port.
Kojto 90:cb3d968589d8 340 */
Kojto 90:cb3d968589d8 341 /*@{*/
Kojto 90:cb3d968589d8 342 #define BP_AXBS_PRSn_M5 (20U) /*!< Bit position for AXBS_PRSn_M5. */
Kojto 90:cb3d968589d8 343 #define BM_AXBS_PRSn_M5 (0x00700000U) /*!< Bit mask for AXBS_PRSn_M5. */
Kojto 90:cb3d968589d8 344 #define BS_AXBS_PRSn_M5 (3U) /*!< Bit field size in bits for AXBS_PRSn_M5. */
Kojto 90:cb3d968589d8 345
Kojto 90:cb3d968589d8 346 /*! @brief Read current value of the AXBS_PRSn_M5 field. */
Kojto 90:cb3d968589d8 347 #define BR_AXBS_PRSn_M5(x, n) (HW_AXBS_PRSn(x, n).B.M5)
Kojto 90:cb3d968589d8 348
Kojto 90:cb3d968589d8 349 /*! @brief Format value for bitfield AXBS_PRSn_M5. */
Kojto 90:cb3d968589d8 350 #define BF_AXBS_PRSn_M5(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M5) & BM_AXBS_PRSn_M5)
Kojto 90:cb3d968589d8 351
Kojto 90:cb3d968589d8 352 /*! @brief Set the M5 field to a new value. */
Kojto 90:cb3d968589d8 353 #define BW_AXBS_PRSn_M5(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M5) | BF_AXBS_PRSn_M5(v)))
Kojto 90:cb3d968589d8 354 /*@}*/
Kojto 90:cb3d968589d8 355 /*******************************************************************************
Kojto 90:cb3d968589d8 356 * HW_AXBS_CRSn - Control Register
Kojto 90:cb3d968589d8 357 ******************************************************************************/
Kojto 90:cb3d968589d8 358
Kojto 90:cb3d968589d8 359 /*!
Kojto 90:cb3d968589d8 360 * @brief HW_AXBS_CRSn - Control Register (RW)
Kojto 90:cb3d968589d8 361 *
Kojto 90:cb3d968589d8 362 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 363 *
Kojto 90:cb3d968589d8 364 * These registers control several features of each slave port and must be
Kojto 90:cb3d968589d8 365 * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
Kojto 90:cb3d968589d8 366 * attempts to write to it have no effect and result in an error response.
Kojto 90:cb3d968589d8 367 */
Kojto 90:cb3d968589d8 368 typedef union _hw_axbs_crsn
Kojto 90:cb3d968589d8 369 {
Kojto 90:cb3d968589d8 370 uint32_t U;
Kojto 90:cb3d968589d8 371 struct _hw_axbs_crsn_bitfields
Kojto 90:cb3d968589d8 372 {
Kojto 90:cb3d968589d8 373 uint32_t PARK : 3; /*!< [2:0] Park */
Kojto 90:cb3d968589d8 374 uint32_t RESERVED0 : 1; /*!< [3] */
Kojto 90:cb3d968589d8 375 uint32_t PCTL : 2; /*!< [5:4] Parking Control */
Kojto 90:cb3d968589d8 376 uint32_t RESERVED1 : 2; /*!< [7:6] */
Kojto 90:cb3d968589d8 377 uint32_t ARB : 2; /*!< [9:8] Arbitration Mode */
Kojto 90:cb3d968589d8 378 uint32_t RESERVED2 : 20; /*!< [29:10] */
Kojto 90:cb3d968589d8 379 uint32_t HLP : 1; /*!< [30] Halt Low Priority */
Kojto 90:cb3d968589d8 380 uint32_t RO : 1; /*!< [31] Read Only */
Kojto 90:cb3d968589d8 381 } B;
Kojto 90:cb3d968589d8 382 } hw_axbs_crsn_t;
Kojto 90:cb3d968589d8 383
Kojto 90:cb3d968589d8 384 /*!
Kojto 90:cb3d968589d8 385 * @name Constants and macros for entire AXBS_CRSn register
Kojto 90:cb3d968589d8 386 */
Kojto 90:cb3d968589d8 387 /*@{*/
Kojto 90:cb3d968589d8 388 #define HW_AXBS_CRSn_COUNT (5U)
Kojto 90:cb3d968589d8 389
Kojto 90:cb3d968589d8 390 #define HW_AXBS_CRSn_ADDR(x, n) ((x) + 0x10U + (0x100U * (n)))
Kojto 90:cb3d968589d8 391
Kojto 90:cb3d968589d8 392 #define HW_AXBS_CRSn(x, n) (*(__IO hw_axbs_crsn_t *) HW_AXBS_CRSn_ADDR(x, n))
Kojto 90:cb3d968589d8 393 #define HW_AXBS_CRSn_RD(x, n) (HW_AXBS_CRSn(x, n).U)
Kojto 90:cb3d968589d8 394 #define HW_AXBS_CRSn_WR(x, n, v) (HW_AXBS_CRSn(x, n).U = (v))
Kojto 90:cb3d968589d8 395 #define HW_AXBS_CRSn_SET(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 396 #define HW_AXBS_CRSn_CLR(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 397 #define HW_AXBS_CRSn_TOG(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 398 /*@}*/
Kojto 90:cb3d968589d8 399
Kojto 90:cb3d968589d8 400 /*
Kojto 90:cb3d968589d8 401 * Constants & macros for individual AXBS_CRSn bitfields
Kojto 90:cb3d968589d8 402 */
Kojto 90:cb3d968589d8 403
Kojto 90:cb3d968589d8 404 /*!
Kojto 90:cb3d968589d8 405 * @name Register AXBS_CRSn, field PARK[2:0] (RW)
Kojto 90:cb3d968589d8 406 *
Kojto 90:cb3d968589d8 407 * Determines which master port the current slave port parks on when no masters
Kojto 90:cb3d968589d8 408 * are actively making requests and the PCTL bits are cleared. Select only master
Kojto 90:cb3d968589d8 409 * ports that are present on the chip. Otherwise, undefined behavior might occur.
Kojto 90:cb3d968589d8 410 *
Kojto 90:cb3d968589d8 411 * Values:
Kojto 90:cb3d968589d8 412 * - 000 - Park on master port M0
Kojto 90:cb3d968589d8 413 * - 001 - Park on master port M1
Kojto 90:cb3d968589d8 414 * - 010 - Park on master port M2
Kojto 90:cb3d968589d8 415 * - 011 - Park on master port M3
Kojto 90:cb3d968589d8 416 * - 100 - Park on master port M4
Kojto 90:cb3d968589d8 417 * - 101 - Park on master port M5
Kojto 90:cb3d968589d8 418 * - 110 - Park on master port M6
Kojto 90:cb3d968589d8 419 * - 111 - Park on master port M7
Kojto 90:cb3d968589d8 420 */
Kojto 90:cb3d968589d8 421 /*@{*/
Kojto 90:cb3d968589d8 422 #define BP_AXBS_CRSn_PARK (0U) /*!< Bit position for AXBS_CRSn_PARK. */
Kojto 90:cb3d968589d8 423 #define BM_AXBS_CRSn_PARK (0x00000007U) /*!< Bit mask for AXBS_CRSn_PARK. */
Kojto 90:cb3d968589d8 424 #define BS_AXBS_CRSn_PARK (3U) /*!< Bit field size in bits for AXBS_CRSn_PARK. */
Kojto 90:cb3d968589d8 425
Kojto 90:cb3d968589d8 426 /*! @brief Read current value of the AXBS_CRSn_PARK field. */
Kojto 90:cb3d968589d8 427 #define BR_AXBS_CRSn_PARK(x, n) (HW_AXBS_CRSn(x, n).B.PARK)
Kojto 90:cb3d968589d8 428
Kojto 90:cb3d968589d8 429 /*! @brief Format value for bitfield AXBS_CRSn_PARK. */
Kojto 90:cb3d968589d8 430 #define BF_AXBS_CRSn_PARK(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_PARK) & BM_AXBS_CRSn_PARK)
Kojto 90:cb3d968589d8 431
Kojto 90:cb3d968589d8 432 /*! @brief Set the PARK field to a new value. */
Kojto 90:cb3d968589d8 433 #define BW_AXBS_CRSn_PARK(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_PARK) | BF_AXBS_CRSn_PARK(v)))
Kojto 90:cb3d968589d8 434 /*@}*/
Kojto 90:cb3d968589d8 435
Kojto 90:cb3d968589d8 436 /*!
Kojto 90:cb3d968589d8 437 * @name Register AXBS_CRSn, field PCTL[5:4] (RW)
Kojto 90:cb3d968589d8 438 *
Kojto 90:cb3d968589d8 439 * Determines the slave port's parking control. The low-power park feature
Kojto 90:cb3d968589d8 440 * results in an overall power savings if the slave port is not saturated. However,
Kojto 90:cb3d968589d8 441 * this forces an extra latency clock when any master tries to access the slave
Kojto 90:cb3d968589d8 442 * port while not in use because it is not parked on any master.
Kojto 90:cb3d968589d8 443 *
Kojto 90:cb3d968589d8 444 * Values:
Kojto 90:cb3d968589d8 445 * - 00 - When no master makes a request, the arbiter parks the slave port on
Kojto 90:cb3d968589d8 446 * the master port defined by the PARK field
Kojto 90:cb3d968589d8 447 * - 01 - When no master makes a request, the arbiter parks the slave port on
Kojto 90:cb3d968589d8 448 * the last master to be in control of the slave port
Kojto 90:cb3d968589d8 449 * - 10 - When no master makes a request, the slave port is not parked on a
Kojto 90:cb3d968589d8 450 * master and the arbiter drives all outputs to a constant safe state
Kojto 90:cb3d968589d8 451 * - 11 - Reserved
Kojto 90:cb3d968589d8 452 */
Kojto 90:cb3d968589d8 453 /*@{*/
Kojto 90:cb3d968589d8 454 #define BP_AXBS_CRSn_PCTL (4U) /*!< Bit position for AXBS_CRSn_PCTL. */
Kojto 90:cb3d968589d8 455 #define BM_AXBS_CRSn_PCTL (0x00000030U) /*!< Bit mask for AXBS_CRSn_PCTL. */
Kojto 90:cb3d968589d8 456 #define BS_AXBS_CRSn_PCTL (2U) /*!< Bit field size in bits for AXBS_CRSn_PCTL. */
Kojto 90:cb3d968589d8 457
Kojto 90:cb3d968589d8 458 /*! @brief Read current value of the AXBS_CRSn_PCTL field. */
Kojto 90:cb3d968589d8 459 #define BR_AXBS_CRSn_PCTL(x, n) (HW_AXBS_CRSn(x, n).B.PCTL)
Kojto 90:cb3d968589d8 460
Kojto 90:cb3d968589d8 461 /*! @brief Format value for bitfield AXBS_CRSn_PCTL. */
Kojto 90:cb3d968589d8 462 #define BF_AXBS_CRSn_PCTL(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_PCTL) & BM_AXBS_CRSn_PCTL)
Kojto 90:cb3d968589d8 463
Kojto 90:cb3d968589d8 464 /*! @brief Set the PCTL field to a new value. */
Kojto 90:cb3d968589d8 465 #define BW_AXBS_CRSn_PCTL(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_PCTL) | BF_AXBS_CRSn_PCTL(v)))
Kojto 90:cb3d968589d8 466 /*@}*/
Kojto 90:cb3d968589d8 467
Kojto 90:cb3d968589d8 468 /*!
Kojto 90:cb3d968589d8 469 * @name Register AXBS_CRSn, field ARB[9:8] (RW)
Kojto 90:cb3d968589d8 470 *
Kojto 90:cb3d968589d8 471 * Selects the arbitration policy for the slave port.
Kojto 90:cb3d968589d8 472 *
Kojto 90:cb3d968589d8 473 * Values:
Kojto 90:cb3d968589d8 474 * - 00 - Fixed priority
Kojto 90:cb3d968589d8 475 * - 01 - Round-robin, or rotating, priority
Kojto 90:cb3d968589d8 476 * - 10 - Reserved
Kojto 90:cb3d968589d8 477 * - 11 - Reserved
Kojto 90:cb3d968589d8 478 */
Kojto 90:cb3d968589d8 479 /*@{*/
Kojto 90:cb3d968589d8 480 #define BP_AXBS_CRSn_ARB (8U) /*!< Bit position for AXBS_CRSn_ARB. */
Kojto 90:cb3d968589d8 481 #define BM_AXBS_CRSn_ARB (0x00000300U) /*!< Bit mask for AXBS_CRSn_ARB. */
Kojto 90:cb3d968589d8 482 #define BS_AXBS_CRSn_ARB (2U) /*!< Bit field size in bits for AXBS_CRSn_ARB. */
Kojto 90:cb3d968589d8 483
Kojto 90:cb3d968589d8 484 /*! @brief Read current value of the AXBS_CRSn_ARB field. */
Kojto 90:cb3d968589d8 485 #define BR_AXBS_CRSn_ARB(x, n) (HW_AXBS_CRSn(x, n).B.ARB)
Kojto 90:cb3d968589d8 486
Kojto 90:cb3d968589d8 487 /*! @brief Format value for bitfield AXBS_CRSn_ARB. */
Kojto 90:cb3d968589d8 488 #define BF_AXBS_CRSn_ARB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_ARB) & BM_AXBS_CRSn_ARB)
Kojto 90:cb3d968589d8 489
Kojto 90:cb3d968589d8 490 /*! @brief Set the ARB field to a new value. */
Kojto 90:cb3d968589d8 491 #define BW_AXBS_CRSn_ARB(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_ARB) | BF_AXBS_CRSn_ARB(v)))
Kojto 90:cb3d968589d8 492 /*@}*/
Kojto 90:cb3d968589d8 493
Kojto 90:cb3d968589d8 494 /*!
Kojto 90:cb3d968589d8 495 * @name Register AXBS_CRSn, field HLP[30] (RW)
Kojto 90:cb3d968589d8 496 *
Kojto 90:cb3d968589d8 497 * Sets the initial arbitration priority for low power mode requests . Setting
Kojto 90:cb3d968589d8 498 * this bit will not affect the request for low power mode from attaining highest
Kojto 90:cb3d968589d8 499 * priority once it has control of the slave ports.
Kojto 90:cb3d968589d8 500 *
Kojto 90:cb3d968589d8 501 * Values:
Kojto 90:cb3d968589d8 502 * - 0 - The low power mode request has the highest priority for arbitration on
Kojto 90:cb3d968589d8 503 * this slave port
Kojto 90:cb3d968589d8 504 * - 1 - The low power mode request has the lowest initial priority for
Kojto 90:cb3d968589d8 505 * arbitration on this slave port
Kojto 90:cb3d968589d8 506 */
Kojto 90:cb3d968589d8 507 /*@{*/
Kojto 90:cb3d968589d8 508 #define BP_AXBS_CRSn_HLP (30U) /*!< Bit position for AXBS_CRSn_HLP. */
Kojto 90:cb3d968589d8 509 #define BM_AXBS_CRSn_HLP (0x40000000U) /*!< Bit mask for AXBS_CRSn_HLP. */
Kojto 90:cb3d968589d8 510 #define BS_AXBS_CRSn_HLP (1U) /*!< Bit field size in bits for AXBS_CRSn_HLP. */
Kojto 90:cb3d968589d8 511
Kojto 90:cb3d968589d8 512 /*! @brief Read current value of the AXBS_CRSn_HLP field. */
Kojto 90:cb3d968589d8 513 #define BR_AXBS_CRSn_HLP(x, n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_HLP))
Kojto 90:cb3d968589d8 514
Kojto 90:cb3d968589d8 515 /*! @brief Format value for bitfield AXBS_CRSn_HLP. */
Kojto 90:cb3d968589d8 516 #define BF_AXBS_CRSn_HLP(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_HLP) & BM_AXBS_CRSn_HLP)
Kojto 90:cb3d968589d8 517
Kojto 90:cb3d968589d8 518 /*! @brief Set the HLP field to a new value. */
Kojto 90:cb3d968589d8 519 #define BW_AXBS_CRSn_HLP(x, n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_HLP) = (v))
Kojto 90:cb3d968589d8 520 /*@}*/
Kojto 90:cb3d968589d8 521
Kojto 90:cb3d968589d8 522 /*!
Kojto 90:cb3d968589d8 523 * @name Register AXBS_CRSn, field RO[31] (RW)
Kojto 90:cb3d968589d8 524 *
Kojto 90:cb3d968589d8 525 * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
Kojto 90:cb3d968589d8 526 * only a hardware reset clears it.
Kojto 90:cb3d968589d8 527 *
Kojto 90:cb3d968589d8 528 * Values:
Kojto 90:cb3d968589d8 529 * - 0 - The slave port's registers are writeable
Kojto 90:cb3d968589d8 530 * - 1 - The slave port's registers are read-only and cannot be written.
Kojto 90:cb3d968589d8 531 * Attempted writes have no effect on the registers and result in a bus error
Kojto 90:cb3d968589d8 532 * response.
Kojto 90:cb3d968589d8 533 */
Kojto 90:cb3d968589d8 534 /*@{*/
Kojto 90:cb3d968589d8 535 #define BP_AXBS_CRSn_RO (31U) /*!< Bit position for AXBS_CRSn_RO. */
Kojto 90:cb3d968589d8 536 #define BM_AXBS_CRSn_RO (0x80000000U) /*!< Bit mask for AXBS_CRSn_RO. */
Kojto 90:cb3d968589d8 537 #define BS_AXBS_CRSn_RO (1U) /*!< Bit field size in bits for AXBS_CRSn_RO. */
Kojto 90:cb3d968589d8 538
Kojto 90:cb3d968589d8 539 /*! @brief Read current value of the AXBS_CRSn_RO field. */
Kojto 90:cb3d968589d8 540 #define BR_AXBS_CRSn_RO(x, n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_RO))
Kojto 90:cb3d968589d8 541
Kojto 90:cb3d968589d8 542 /*! @brief Format value for bitfield AXBS_CRSn_RO. */
Kojto 90:cb3d968589d8 543 #define BF_AXBS_CRSn_RO(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_RO) & BM_AXBS_CRSn_RO)
Kojto 90:cb3d968589d8 544
Kojto 90:cb3d968589d8 545 /*! @brief Set the RO field to a new value. */
Kojto 90:cb3d968589d8 546 #define BW_AXBS_CRSn_RO(x, n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_RO) = (v))
Kojto 90:cb3d968589d8 547 /*@}*/
Kojto 90:cb3d968589d8 548
Kojto 90:cb3d968589d8 549 /*******************************************************************************
Kojto 90:cb3d968589d8 550 * HW_AXBS_MGPCR0 - Master General Purpose Control Register
Kojto 90:cb3d968589d8 551 ******************************************************************************/
Kojto 90:cb3d968589d8 552
Kojto 90:cb3d968589d8 553 /*!
Kojto 90:cb3d968589d8 554 * @brief HW_AXBS_MGPCR0 - Master General Purpose Control Register (RW)
Kojto 90:cb3d968589d8 555 *
Kojto 90:cb3d968589d8 556 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 557 *
Kojto 90:cb3d968589d8 558 * The MGPCR controls only whether the master's undefined length burst accesses
Kojto 90:cb3d968589d8 559 * are allowed to complete uninterrupted or whether they can be broken by
Kojto 90:cb3d968589d8 560 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
Kojto 90:cb3d968589d8 561 * mode with 32-bit accesses.
Kojto 90:cb3d968589d8 562 */
Kojto 90:cb3d968589d8 563 typedef union _hw_axbs_mgpcr0
Kojto 90:cb3d968589d8 564 {
Kojto 90:cb3d968589d8 565 uint32_t U;
Kojto 90:cb3d968589d8 566 struct _hw_axbs_mgpcr0_bitfields
Kojto 90:cb3d968589d8 567 {
Kojto 90:cb3d968589d8 568 uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */
Kojto 90:cb3d968589d8 569 uint32_t RESERVED0 : 29; /*!< [31:3] */
Kojto 90:cb3d968589d8 570 } B;
Kojto 90:cb3d968589d8 571 } hw_axbs_mgpcr0_t;
Kojto 90:cb3d968589d8 572
Kojto 90:cb3d968589d8 573 /*!
Kojto 90:cb3d968589d8 574 * @name Constants and macros for entire AXBS_MGPCR0 register
Kojto 90:cb3d968589d8 575 */
Kojto 90:cb3d968589d8 576 /*@{*/
Kojto 90:cb3d968589d8 577 #define HW_AXBS_MGPCR0_ADDR(x) ((x) + 0x800U)
Kojto 90:cb3d968589d8 578
Kojto 90:cb3d968589d8 579 #define HW_AXBS_MGPCR0(x) (*(__IO hw_axbs_mgpcr0_t *) HW_AXBS_MGPCR0_ADDR(x))
Kojto 90:cb3d968589d8 580 #define HW_AXBS_MGPCR0_RD(x) (HW_AXBS_MGPCR0(x).U)
Kojto 90:cb3d968589d8 581 #define HW_AXBS_MGPCR0_WR(x, v) (HW_AXBS_MGPCR0(x).U = (v))
Kojto 90:cb3d968589d8 582 #define HW_AXBS_MGPCR0_SET(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) | (v)))
Kojto 90:cb3d968589d8 583 #define HW_AXBS_MGPCR0_CLR(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 584 #define HW_AXBS_MGPCR0_TOG(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 585 /*@}*/
Kojto 90:cb3d968589d8 586
Kojto 90:cb3d968589d8 587 /*
Kojto 90:cb3d968589d8 588 * Constants & macros for individual AXBS_MGPCR0 bitfields
Kojto 90:cb3d968589d8 589 */
Kojto 90:cb3d968589d8 590
Kojto 90:cb3d968589d8 591 /*!
Kojto 90:cb3d968589d8 592 * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
Kojto 90:cb3d968589d8 593 *
Kojto 90:cb3d968589d8 594 * Determines whether, and when, the crossbar switch arbitrates away the slave
Kojto 90:cb3d968589d8 595 * port the master owns when the master is performing undefined length burst
Kojto 90:cb3d968589d8 596 * accesses.
Kojto 90:cb3d968589d8 597 *
Kojto 90:cb3d968589d8 598 * Values:
Kojto 90:cb3d968589d8 599 * - 000 - No arbitration is allowed during an undefined length burst
Kojto 90:cb3d968589d8 600 * - 001 - Arbitration is allowed at any time during an undefined length burst
Kojto 90:cb3d968589d8 601 * - 010 - Arbitration is allowed after four beats of an undefined length burst
Kojto 90:cb3d968589d8 602 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
Kojto 90:cb3d968589d8 603 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
Kojto 90:cb3d968589d8 604 * - 101 - Reserved
Kojto 90:cb3d968589d8 605 * - 110 - Reserved
Kojto 90:cb3d968589d8 606 * - 111 - Reserved
Kojto 90:cb3d968589d8 607 */
Kojto 90:cb3d968589d8 608 /*@{*/
Kojto 90:cb3d968589d8 609 #define BP_AXBS_MGPCR0_AULB (0U) /*!< Bit position for AXBS_MGPCR0_AULB. */
Kojto 90:cb3d968589d8 610 #define BM_AXBS_MGPCR0_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR0_AULB. */
Kojto 90:cb3d968589d8 611 #define BS_AXBS_MGPCR0_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR0_AULB. */
Kojto 90:cb3d968589d8 612
Kojto 90:cb3d968589d8 613 /*! @brief Read current value of the AXBS_MGPCR0_AULB field. */
Kojto 90:cb3d968589d8 614 #define BR_AXBS_MGPCR0_AULB(x) (HW_AXBS_MGPCR0(x).B.AULB)
Kojto 90:cb3d968589d8 615
Kojto 90:cb3d968589d8 616 /*! @brief Format value for bitfield AXBS_MGPCR0_AULB. */
Kojto 90:cb3d968589d8 617 #define BF_AXBS_MGPCR0_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR0_AULB) & BM_AXBS_MGPCR0_AULB)
Kojto 90:cb3d968589d8 618
Kojto 90:cb3d968589d8 619 /*! @brief Set the AULB field to a new value. */
Kojto 90:cb3d968589d8 620 #define BW_AXBS_MGPCR0_AULB(x, v) (HW_AXBS_MGPCR0_WR(x, (HW_AXBS_MGPCR0_RD(x) & ~BM_AXBS_MGPCR0_AULB) | BF_AXBS_MGPCR0_AULB(v)))
Kojto 90:cb3d968589d8 621 /*@}*/
Kojto 90:cb3d968589d8 622
Kojto 90:cb3d968589d8 623 /*******************************************************************************
Kojto 90:cb3d968589d8 624 * HW_AXBS_MGPCR1 - Master General Purpose Control Register
Kojto 90:cb3d968589d8 625 ******************************************************************************/
Kojto 90:cb3d968589d8 626
Kojto 90:cb3d968589d8 627 /*!
Kojto 90:cb3d968589d8 628 * @brief HW_AXBS_MGPCR1 - Master General Purpose Control Register (RW)
Kojto 90:cb3d968589d8 629 *
Kojto 90:cb3d968589d8 630 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 631 *
Kojto 90:cb3d968589d8 632 * The MGPCR controls only whether the master's undefined length burst accesses
Kojto 90:cb3d968589d8 633 * are allowed to complete uninterrupted or whether they can be broken by
Kojto 90:cb3d968589d8 634 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
Kojto 90:cb3d968589d8 635 * mode with 32-bit accesses.
Kojto 90:cb3d968589d8 636 */
Kojto 90:cb3d968589d8 637 typedef union _hw_axbs_mgpcr1
Kojto 90:cb3d968589d8 638 {
Kojto 90:cb3d968589d8 639 uint32_t U;
Kojto 90:cb3d968589d8 640 struct _hw_axbs_mgpcr1_bitfields
Kojto 90:cb3d968589d8 641 {
Kojto 90:cb3d968589d8 642 uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */
Kojto 90:cb3d968589d8 643 uint32_t RESERVED0 : 29; /*!< [31:3] */
Kojto 90:cb3d968589d8 644 } B;
Kojto 90:cb3d968589d8 645 } hw_axbs_mgpcr1_t;
Kojto 90:cb3d968589d8 646
Kojto 90:cb3d968589d8 647 /*!
Kojto 90:cb3d968589d8 648 * @name Constants and macros for entire AXBS_MGPCR1 register
Kojto 90:cb3d968589d8 649 */
Kojto 90:cb3d968589d8 650 /*@{*/
Kojto 90:cb3d968589d8 651 #define HW_AXBS_MGPCR1_ADDR(x) ((x) + 0x900U)
Kojto 90:cb3d968589d8 652
Kojto 90:cb3d968589d8 653 #define HW_AXBS_MGPCR1(x) (*(__IO hw_axbs_mgpcr1_t *) HW_AXBS_MGPCR1_ADDR(x))
Kojto 90:cb3d968589d8 654 #define HW_AXBS_MGPCR1_RD(x) (HW_AXBS_MGPCR1(x).U)
Kojto 90:cb3d968589d8 655 #define HW_AXBS_MGPCR1_WR(x, v) (HW_AXBS_MGPCR1(x).U = (v))
Kojto 90:cb3d968589d8 656 #define HW_AXBS_MGPCR1_SET(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) | (v)))
Kojto 90:cb3d968589d8 657 #define HW_AXBS_MGPCR1_CLR(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 658 #define HW_AXBS_MGPCR1_TOG(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 659 /*@}*/
Kojto 90:cb3d968589d8 660
Kojto 90:cb3d968589d8 661 /*
Kojto 90:cb3d968589d8 662 * Constants & macros for individual AXBS_MGPCR1 bitfields
Kojto 90:cb3d968589d8 663 */
Kojto 90:cb3d968589d8 664
Kojto 90:cb3d968589d8 665 /*!
Kojto 90:cb3d968589d8 666 * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
Kojto 90:cb3d968589d8 667 *
Kojto 90:cb3d968589d8 668 * Determines whether, and when, the crossbar switch arbitrates away the slave
Kojto 90:cb3d968589d8 669 * port the master owns when the master is performing undefined length burst
Kojto 90:cb3d968589d8 670 * accesses.
Kojto 90:cb3d968589d8 671 *
Kojto 90:cb3d968589d8 672 * Values:
Kojto 90:cb3d968589d8 673 * - 000 - No arbitration is allowed during an undefined length burst
Kojto 90:cb3d968589d8 674 * - 001 - Arbitration is allowed at any time during an undefined length burst
Kojto 90:cb3d968589d8 675 * - 010 - Arbitration is allowed after four beats of an undefined length burst
Kojto 90:cb3d968589d8 676 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
Kojto 90:cb3d968589d8 677 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
Kojto 90:cb3d968589d8 678 * - 101 - Reserved
Kojto 90:cb3d968589d8 679 * - 110 - Reserved
Kojto 90:cb3d968589d8 680 * - 111 - Reserved
Kojto 90:cb3d968589d8 681 */
Kojto 90:cb3d968589d8 682 /*@{*/
Kojto 90:cb3d968589d8 683 #define BP_AXBS_MGPCR1_AULB (0U) /*!< Bit position for AXBS_MGPCR1_AULB. */
Kojto 90:cb3d968589d8 684 #define BM_AXBS_MGPCR1_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR1_AULB. */
Kojto 90:cb3d968589d8 685 #define BS_AXBS_MGPCR1_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR1_AULB. */
Kojto 90:cb3d968589d8 686
Kojto 90:cb3d968589d8 687 /*! @brief Read current value of the AXBS_MGPCR1_AULB field. */
Kojto 90:cb3d968589d8 688 #define BR_AXBS_MGPCR1_AULB(x) (HW_AXBS_MGPCR1(x).B.AULB)
Kojto 90:cb3d968589d8 689
Kojto 90:cb3d968589d8 690 /*! @brief Format value for bitfield AXBS_MGPCR1_AULB. */
Kojto 90:cb3d968589d8 691 #define BF_AXBS_MGPCR1_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR1_AULB) & BM_AXBS_MGPCR1_AULB)
Kojto 90:cb3d968589d8 692
Kojto 90:cb3d968589d8 693 /*! @brief Set the AULB field to a new value. */
Kojto 90:cb3d968589d8 694 #define BW_AXBS_MGPCR1_AULB(x, v) (HW_AXBS_MGPCR1_WR(x, (HW_AXBS_MGPCR1_RD(x) & ~BM_AXBS_MGPCR1_AULB) | BF_AXBS_MGPCR1_AULB(v)))
Kojto 90:cb3d968589d8 695 /*@}*/
Kojto 90:cb3d968589d8 696
Kojto 90:cb3d968589d8 697 /*******************************************************************************
Kojto 90:cb3d968589d8 698 * HW_AXBS_MGPCR2 - Master General Purpose Control Register
Kojto 90:cb3d968589d8 699 ******************************************************************************/
Kojto 90:cb3d968589d8 700
Kojto 90:cb3d968589d8 701 /*!
Kojto 90:cb3d968589d8 702 * @brief HW_AXBS_MGPCR2 - Master General Purpose Control Register (RW)
Kojto 90:cb3d968589d8 703 *
Kojto 90:cb3d968589d8 704 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 705 *
Kojto 90:cb3d968589d8 706 * The MGPCR controls only whether the master's undefined length burst accesses
Kojto 90:cb3d968589d8 707 * are allowed to complete uninterrupted or whether they can be broken by
Kojto 90:cb3d968589d8 708 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
Kojto 90:cb3d968589d8 709 * mode with 32-bit accesses.
Kojto 90:cb3d968589d8 710 */
Kojto 90:cb3d968589d8 711 typedef union _hw_axbs_mgpcr2
Kojto 90:cb3d968589d8 712 {
Kojto 90:cb3d968589d8 713 uint32_t U;
Kojto 90:cb3d968589d8 714 struct _hw_axbs_mgpcr2_bitfields
Kojto 90:cb3d968589d8 715 {
Kojto 90:cb3d968589d8 716 uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */
Kojto 90:cb3d968589d8 717 uint32_t RESERVED0 : 29; /*!< [31:3] */
Kojto 90:cb3d968589d8 718 } B;
Kojto 90:cb3d968589d8 719 } hw_axbs_mgpcr2_t;
Kojto 90:cb3d968589d8 720
Kojto 90:cb3d968589d8 721 /*!
Kojto 90:cb3d968589d8 722 * @name Constants and macros for entire AXBS_MGPCR2 register
Kojto 90:cb3d968589d8 723 */
Kojto 90:cb3d968589d8 724 /*@{*/
Kojto 90:cb3d968589d8 725 #define HW_AXBS_MGPCR2_ADDR(x) ((x) + 0xA00U)
Kojto 90:cb3d968589d8 726
Kojto 90:cb3d968589d8 727 #define HW_AXBS_MGPCR2(x) (*(__IO hw_axbs_mgpcr2_t *) HW_AXBS_MGPCR2_ADDR(x))
Kojto 90:cb3d968589d8 728 #define HW_AXBS_MGPCR2_RD(x) (HW_AXBS_MGPCR2(x).U)
Kojto 90:cb3d968589d8 729 #define HW_AXBS_MGPCR2_WR(x, v) (HW_AXBS_MGPCR2(x).U = (v))
Kojto 90:cb3d968589d8 730 #define HW_AXBS_MGPCR2_SET(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) | (v)))
Kojto 90:cb3d968589d8 731 #define HW_AXBS_MGPCR2_CLR(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 732 #define HW_AXBS_MGPCR2_TOG(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 733 /*@}*/
Kojto 90:cb3d968589d8 734
Kojto 90:cb3d968589d8 735 /*
Kojto 90:cb3d968589d8 736 * Constants & macros for individual AXBS_MGPCR2 bitfields
Kojto 90:cb3d968589d8 737 */
Kojto 90:cb3d968589d8 738
Kojto 90:cb3d968589d8 739 /*!
Kojto 90:cb3d968589d8 740 * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
Kojto 90:cb3d968589d8 741 *
Kojto 90:cb3d968589d8 742 * Determines whether, and when, the crossbar switch arbitrates away the slave
Kojto 90:cb3d968589d8 743 * port the master owns when the master is performing undefined length burst
Kojto 90:cb3d968589d8 744 * accesses.
Kojto 90:cb3d968589d8 745 *
Kojto 90:cb3d968589d8 746 * Values:
Kojto 90:cb3d968589d8 747 * - 000 - No arbitration is allowed during an undefined length burst
Kojto 90:cb3d968589d8 748 * - 001 - Arbitration is allowed at any time during an undefined length burst
Kojto 90:cb3d968589d8 749 * - 010 - Arbitration is allowed after four beats of an undefined length burst
Kojto 90:cb3d968589d8 750 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
Kojto 90:cb3d968589d8 751 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
Kojto 90:cb3d968589d8 752 * - 101 - Reserved
Kojto 90:cb3d968589d8 753 * - 110 - Reserved
Kojto 90:cb3d968589d8 754 * - 111 - Reserved
Kojto 90:cb3d968589d8 755 */
Kojto 90:cb3d968589d8 756 /*@{*/
Kojto 90:cb3d968589d8 757 #define BP_AXBS_MGPCR2_AULB (0U) /*!< Bit position for AXBS_MGPCR2_AULB. */
Kojto 90:cb3d968589d8 758 #define BM_AXBS_MGPCR2_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR2_AULB. */
Kojto 90:cb3d968589d8 759 #define BS_AXBS_MGPCR2_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR2_AULB. */
Kojto 90:cb3d968589d8 760
Kojto 90:cb3d968589d8 761 /*! @brief Read current value of the AXBS_MGPCR2_AULB field. */
Kojto 90:cb3d968589d8 762 #define BR_AXBS_MGPCR2_AULB(x) (HW_AXBS_MGPCR2(x).B.AULB)
Kojto 90:cb3d968589d8 763
Kojto 90:cb3d968589d8 764 /*! @brief Format value for bitfield AXBS_MGPCR2_AULB. */
Kojto 90:cb3d968589d8 765 #define BF_AXBS_MGPCR2_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR2_AULB) & BM_AXBS_MGPCR2_AULB)
Kojto 90:cb3d968589d8 766
Kojto 90:cb3d968589d8 767 /*! @brief Set the AULB field to a new value. */
Kojto 90:cb3d968589d8 768 #define BW_AXBS_MGPCR2_AULB(x, v) (HW_AXBS_MGPCR2_WR(x, (HW_AXBS_MGPCR2_RD(x) & ~BM_AXBS_MGPCR2_AULB) | BF_AXBS_MGPCR2_AULB(v)))
Kojto 90:cb3d968589d8 769 /*@}*/
Kojto 90:cb3d968589d8 770
Kojto 90:cb3d968589d8 771 /*******************************************************************************
Kojto 90:cb3d968589d8 772 * HW_AXBS_MGPCR3 - Master General Purpose Control Register
Kojto 90:cb3d968589d8 773 ******************************************************************************/
Kojto 90:cb3d968589d8 774
Kojto 90:cb3d968589d8 775 /*!
Kojto 90:cb3d968589d8 776 * @brief HW_AXBS_MGPCR3 - Master General Purpose Control Register (RW)
Kojto 90:cb3d968589d8 777 *
Kojto 90:cb3d968589d8 778 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 779 *
Kojto 90:cb3d968589d8 780 * The MGPCR controls only whether the master's undefined length burst accesses
Kojto 90:cb3d968589d8 781 * are allowed to complete uninterrupted or whether they can be broken by
Kojto 90:cb3d968589d8 782 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
Kojto 90:cb3d968589d8 783 * mode with 32-bit accesses.
Kojto 90:cb3d968589d8 784 */
Kojto 90:cb3d968589d8 785 typedef union _hw_axbs_mgpcr3
Kojto 90:cb3d968589d8 786 {
Kojto 90:cb3d968589d8 787 uint32_t U;
Kojto 90:cb3d968589d8 788 struct _hw_axbs_mgpcr3_bitfields
Kojto 90:cb3d968589d8 789 {
Kojto 90:cb3d968589d8 790 uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */
Kojto 90:cb3d968589d8 791 uint32_t RESERVED0 : 29; /*!< [31:3] */
Kojto 90:cb3d968589d8 792 } B;
Kojto 90:cb3d968589d8 793 } hw_axbs_mgpcr3_t;
Kojto 90:cb3d968589d8 794
Kojto 90:cb3d968589d8 795 /*!
Kojto 90:cb3d968589d8 796 * @name Constants and macros for entire AXBS_MGPCR3 register
Kojto 90:cb3d968589d8 797 */
Kojto 90:cb3d968589d8 798 /*@{*/
Kojto 90:cb3d968589d8 799 #define HW_AXBS_MGPCR3_ADDR(x) ((x) + 0xB00U)
Kojto 90:cb3d968589d8 800
Kojto 90:cb3d968589d8 801 #define HW_AXBS_MGPCR3(x) (*(__IO hw_axbs_mgpcr3_t *) HW_AXBS_MGPCR3_ADDR(x))
Kojto 90:cb3d968589d8 802 #define HW_AXBS_MGPCR3_RD(x) (HW_AXBS_MGPCR3(x).U)
Kojto 90:cb3d968589d8 803 #define HW_AXBS_MGPCR3_WR(x, v) (HW_AXBS_MGPCR3(x).U = (v))
Kojto 90:cb3d968589d8 804 #define HW_AXBS_MGPCR3_SET(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) | (v)))
Kojto 90:cb3d968589d8 805 #define HW_AXBS_MGPCR3_CLR(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 806 #define HW_AXBS_MGPCR3_TOG(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 807 /*@}*/
Kojto 90:cb3d968589d8 808
Kojto 90:cb3d968589d8 809 /*
Kojto 90:cb3d968589d8 810 * Constants & macros for individual AXBS_MGPCR3 bitfields
Kojto 90:cb3d968589d8 811 */
Kojto 90:cb3d968589d8 812
Kojto 90:cb3d968589d8 813 /*!
Kojto 90:cb3d968589d8 814 * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
Kojto 90:cb3d968589d8 815 *
Kojto 90:cb3d968589d8 816 * Determines whether, and when, the crossbar switch arbitrates away the slave
Kojto 90:cb3d968589d8 817 * port the master owns when the master is performing undefined length burst
Kojto 90:cb3d968589d8 818 * accesses.
Kojto 90:cb3d968589d8 819 *
Kojto 90:cb3d968589d8 820 * Values:
Kojto 90:cb3d968589d8 821 * - 000 - No arbitration is allowed during an undefined length burst
Kojto 90:cb3d968589d8 822 * - 001 - Arbitration is allowed at any time during an undefined length burst
Kojto 90:cb3d968589d8 823 * - 010 - Arbitration is allowed after four beats of an undefined length burst
Kojto 90:cb3d968589d8 824 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
Kojto 90:cb3d968589d8 825 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
Kojto 90:cb3d968589d8 826 * - 101 - Reserved
Kojto 90:cb3d968589d8 827 * - 110 - Reserved
Kojto 90:cb3d968589d8 828 * - 111 - Reserved
Kojto 90:cb3d968589d8 829 */
Kojto 90:cb3d968589d8 830 /*@{*/
Kojto 90:cb3d968589d8 831 #define BP_AXBS_MGPCR3_AULB (0U) /*!< Bit position for AXBS_MGPCR3_AULB. */
Kojto 90:cb3d968589d8 832 #define BM_AXBS_MGPCR3_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR3_AULB. */
Kojto 90:cb3d968589d8 833 #define BS_AXBS_MGPCR3_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR3_AULB. */
Kojto 90:cb3d968589d8 834
Kojto 90:cb3d968589d8 835 /*! @brief Read current value of the AXBS_MGPCR3_AULB field. */
Kojto 90:cb3d968589d8 836 #define BR_AXBS_MGPCR3_AULB(x) (HW_AXBS_MGPCR3(x).B.AULB)
Kojto 90:cb3d968589d8 837
Kojto 90:cb3d968589d8 838 /*! @brief Format value for bitfield AXBS_MGPCR3_AULB. */
Kojto 90:cb3d968589d8 839 #define BF_AXBS_MGPCR3_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR3_AULB) & BM_AXBS_MGPCR3_AULB)
Kojto 90:cb3d968589d8 840
Kojto 90:cb3d968589d8 841 /*! @brief Set the AULB field to a new value. */
Kojto 90:cb3d968589d8 842 #define BW_AXBS_MGPCR3_AULB(x, v) (HW_AXBS_MGPCR3_WR(x, (HW_AXBS_MGPCR3_RD(x) & ~BM_AXBS_MGPCR3_AULB) | BF_AXBS_MGPCR3_AULB(v)))
Kojto 90:cb3d968589d8 843 /*@}*/
Kojto 90:cb3d968589d8 844
Kojto 90:cb3d968589d8 845 /*******************************************************************************
Kojto 90:cb3d968589d8 846 * HW_AXBS_MGPCR4 - Master General Purpose Control Register
Kojto 90:cb3d968589d8 847 ******************************************************************************/
Kojto 90:cb3d968589d8 848
Kojto 90:cb3d968589d8 849 /*!
Kojto 90:cb3d968589d8 850 * @brief HW_AXBS_MGPCR4 - Master General Purpose Control Register (RW)
Kojto 90:cb3d968589d8 851 *
Kojto 90:cb3d968589d8 852 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 853 *
Kojto 90:cb3d968589d8 854 * The MGPCR controls only whether the master's undefined length burst accesses
Kojto 90:cb3d968589d8 855 * are allowed to complete uninterrupted or whether they can be broken by
Kojto 90:cb3d968589d8 856 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
Kojto 90:cb3d968589d8 857 * mode with 32-bit accesses.
Kojto 90:cb3d968589d8 858 */
Kojto 90:cb3d968589d8 859 typedef union _hw_axbs_mgpcr4
Kojto 90:cb3d968589d8 860 {
Kojto 90:cb3d968589d8 861 uint32_t U;
Kojto 90:cb3d968589d8 862 struct _hw_axbs_mgpcr4_bitfields
Kojto 90:cb3d968589d8 863 {
Kojto 90:cb3d968589d8 864 uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */
Kojto 90:cb3d968589d8 865 uint32_t RESERVED0 : 29; /*!< [31:3] */
Kojto 90:cb3d968589d8 866 } B;
Kojto 90:cb3d968589d8 867 } hw_axbs_mgpcr4_t;
Kojto 90:cb3d968589d8 868
Kojto 90:cb3d968589d8 869 /*!
Kojto 90:cb3d968589d8 870 * @name Constants and macros for entire AXBS_MGPCR4 register
Kojto 90:cb3d968589d8 871 */
Kojto 90:cb3d968589d8 872 /*@{*/
Kojto 90:cb3d968589d8 873 #define HW_AXBS_MGPCR4_ADDR(x) ((x) + 0xC00U)
Kojto 90:cb3d968589d8 874
Kojto 90:cb3d968589d8 875 #define HW_AXBS_MGPCR4(x) (*(__IO hw_axbs_mgpcr4_t *) HW_AXBS_MGPCR4_ADDR(x))
Kojto 90:cb3d968589d8 876 #define HW_AXBS_MGPCR4_RD(x) (HW_AXBS_MGPCR4(x).U)
Kojto 90:cb3d968589d8 877 #define HW_AXBS_MGPCR4_WR(x, v) (HW_AXBS_MGPCR4(x).U = (v))
Kojto 90:cb3d968589d8 878 #define HW_AXBS_MGPCR4_SET(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) | (v)))
Kojto 90:cb3d968589d8 879 #define HW_AXBS_MGPCR4_CLR(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 880 #define HW_AXBS_MGPCR4_TOG(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 881 /*@}*/
Kojto 90:cb3d968589d8 882
Kojto 90:cb3d968589d8 883 /*
Kojto 90:cb3d968589d8 884 * Constants & macros for individual AXBS_MGPCR4 bitfields
Kojto 90:cb3d968589d8 885 */
Kojto 90:cb3d968589d8 886
Kojto 90:cb3d968589d8 887 /*!
Kojto 90:cb3d968589d8 888 * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
Kojto 90:cb3d968589d8 889 *
Kojto 90:cb3d968589d8 890 * Determines whether, and when, the crossbar switch arbitrates away the slave
Kojto 90:cb3d968589d8 891 * port the master owns when the master is performing undefined length burst
Kojto 90:cb3d968589d8 892 * accesses.
Kojto 90:cb3d968589d8 893 *
Kojto 90:cb3d968589d8 894 * Values:
Kojto 90:cb3d968589d8 895 * - 000 - No arbitration is allowed during an undefined length burst
Kojto 90:cb3d968589d8 896 * - 001 - Arbitration is allowed at any time during an undefined length burst
Kojto 90:cb3d968589d8 897 * - 010 - Arbitration is allowed after four beats of an undefined length burst
Kojto 90:cb3d968589d8 898 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
Kojto 90:cb3d968589d8 899 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
Kojto 90:cb3d968589d8 900 * - 101 - Reserved
Kojto 90:cb3d968589d8 901 * - 110 - Reserved
Kojto 90:cb3d968589d8 902 * - 111 - Reserved
Kojto 90:cb3d968589d8 903 */
Kojto 90:cb3d968589d8 904 /*@{*/
Kojto 90:cb3d968589d8 905 #define BP_AXBS_MGPCR4_AULB (0U) /*!< Bit position for AXBS_MGPCR4_AULB. */
Kojto 90:cb3d968589d8 906 #define BM_AXBS_MGPCR4_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR4_AULB. */
Kojto 90:cb3d968589d8 907 #define BS_AXBS_MGPCR4_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR4_AULB. */
Kojto 90:cb3d968589d8 908
Kojto 90:cb3d968589d8 909 /*! @brief Read current value of the AXBS_MGPCR4_AULB field. */
Kojto 90:cb3d968589d8 910 #define BR_AXBS_MGPCR4_AULB(x) (HW_AXBS_MGPCR4(x).B.AULB)
Kojto 90:cb3d968589d8 911
Kojto 90:cb3d968589d8 912 /*! @brief Format value for bitfield AXBS_MGPCR4_AULB. */
Kojto 90:cb3d968589d8 913 #define BF_AXBS_MGPCR4_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR4_AULB) & BM_AXBS_MGPCR4_AULB)
Kojto 90:cb3d968589d8 914
Kojto 90:cb3d968589d8 915 /*! @brief Set the AULB field to a new value. */
Kojto 90:cb3d968589d8 916 #define BW_AXBS_MGPCR4_AULB(x, v) (HW_AXBS_MGPCR4_WR(x, (HW_AXBS_MGPCR4_RD(x) & ~BM_AXBS_MGPCR4_AULB) | BF_AXBS_MGPCR4_AULB(v)))
Kojto 90:cb3d968589d8 917 /*@}*/
Kojto 90:cb3d968589d8 918
Kojto 90:cb3d968589d8 919 /*******************************************************************************
Kojto 90:cb3d968589d8 920 * HW_AXBS_MGPCR5 - Master General Purpose Control Register
Kojto 90:cb3d968589d8 921 ******************************************************************************/
Kojto 90:cb3d968589d8 922
Kojto 90:cb3d968589d8 923 /*!
Kojto 90:cb3d968589d8 924 * @brief HW_AXBS_MGPCR5 - Master General Purpose Control Register (RW)
Kojto 90:cb3d968589d8 925 *
Kojto 90:cb3d968589d8 926 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 927 *
Kojto 90:cb3d968589d8 928 * The MGPCR controls only whether the master's undefined length burst accesses
Kojto 90:cb3d968589d8 929 * are allowed to complete uninterrupted or whether they can be broken by
Kojto 90:cb3d968589d8 930 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
Kojto 90:cb3d968589d8 931 * mode with 32-bit accesses.
Kojto 90:cb3d968589d8 932 */
Kojto 90:cb3d968589d8 933 typedef union _hw_axbs_mgpcr5
Kojto 90:cb3d968589d8 934 {
Kojto 90:cb3d968589d8 935 uint32_t U;
Kojto 90:cb3d968589d8 936 struct _hw_axbs_mgpcr5_bitfields
Kojto 90:cb3d968589d8 937 {
Kojto 90:cb3d968589d8 938 uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */
Kojto 90:cb3d968589d8 939 uint32_t RESERVED0 : 29; /*!< [31:3] */
Kojto 90:cb3d968589d8 940 } B;
Kojto 90:cb3d968589d8 941 } hw_axbs_mgpcr5_t;
Kojto 90:cb3d968589d8 942
Kojto 90:cb3d968589d8 943 /*!
Kojto 90:cb3d968589d8 944 * @name Constants and macros for entire AXBS_MGPCR5 register
Kojto 90:cb3d968589d8 945 */
Kojto 90:cb3d968589d8 946 /*@{*/
Kojto 90:cb3d968589d8 947 #define HW_AXBS_MGPCR5_ADDR(x) ((x) + 0xD00U)
Kojto 90:cb3d968589d8 948
Kojto 90:cb3d968589d8 949 #define HW_AXBS_MGPCR5(x) (*(__IO hw_axbs_mgpcr5_t *) HW_AXBS_MGPCR5_ADDR(x))
Kojto 90:cb3d968589d8 950 #define HW_AXBS_MGPCR5_RD(x) (HW_AXBS_MGPCR5(x).U)
Kojto 90:cb3d968589d8 951 #define HW_AXBS_MGPCR5_WR(x, v) (HW_AXBS_MGPCR5(x).U = (v))
Kojto 90:cb3d968589d8 952 #define HW_AXBS_MGPCR5_SET(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) | (v)))
Kojto 90:cb3d968589d8 953 #define HW_AXBS_MGPCR5_CLR(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 954 #define HW_AXBS_MGPCR5_TOG(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 955 /*@}*/
Kojto 90:cb3d968589d8 956
Kojto 90:cb3d968589d8 957 /*
Kojto 90:cb3d968589d8 958 * Constants & macros for individual AXBS_MGPCR5 bitfields
Kojto 90:cb3d968589d8 959 */
Kojto 90:cb3d968589d8 960
Kojto 90:cb3d968589d8 961 /*!
Kojto 90:cb3d968589d8 962 * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
Kojto 90:cb3d968589d8 963 *
Kojto 90:cb3d968589d8 964 * Determines whether, and when, the crossbar switch arbitrates away the slave
Kojto 90:cb3d968589d8 965 * port the master owns when the master is performing undefined length burst
Kojto 90:cb3d968589d8 966 * accesses.
Kojto 90:cb3d968589d8 967 *
Kojto 90:cb3d968589d8 968 * Values:
Kojto 90:cb3d968589d8 969 * - 000 - No arbitration is allowed during an undefined length burst
Kojto 90:cb3d968589d8 970 * - 001 - Arbitration is allowed at any time during an undefined length burst
Kojto 90:cb3d968589d8 971 * - 010 - Arbitration is allowed after four beats of an undefined length burst
Kojto 90:cb3d968589d8 972 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
Kojto 90:cb3d968589d8 973 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
Kojto 90:cb3d968589d8 974 * - 101 - Reserved
Kojto 90:cb3d968589d8 975 * - 110 - Reserved
Kojto 90:cb3d968589d8 976 * - 111 - Reserved
Kojto 90:cb3d968589d8 977 */
Kojto 90:cb3d968589d8 978 /*@{*/
Kojto 90:cb3d968589d8 979 #define BP_AXBS_MGPCR5_AULB (0U) /*!< Bit position for AXBS_MGPCR5_AULB. */
Kojto 90:cb3d968589d8 980 #define BM_AXBS_MGPCR5_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR5_AULB. */
Kojto 90:cb3d968589d8 981 #define BS_AXBS_MGPCR5_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR5_AULB. */
Kojto 90:cb3d968589d8 982
Kojto 90:cb3d968589d8 983 /*! @brief Read current value of the AXBS_MGPCR5_AULB field. */
Kojto 90:cb3d968589d8 984 #define BR_AXBS_MGPCR5_AULB(x) (HW_AXBS_MGPCR5(x).B.AULB)
Kojto 90:cb3d968589d8 985
Kojto 90:cb3d968589d8 986 /*! @brief Format value for bitfield AXBS_MGPCR5_AULB. */
Kojto 90:cb3d968589d8 987 #define BF_AXBS_MGPCR5_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR5_AULB) & BM_AXBS_MGPCR5_AULB)
Kojto 90:cb3d968589d8 988
Kojto 90:cb3d968589d8 989 /*! @brief Set the AULB field to a new value. */
Kojto 90:cb3d968589d8 990 #define BW_AXBS_MGPCR5_AULB(x, v) (HW_AXBS_MGPCR5_WR(x, (HW_AXBS_MGPCR5_RD(x) & ~BM_AXBS_MGPCR5_AULB) | BF_AXBS_MGPCR5_AULB(v)))
Kojto 90:cb3d968589d8 991 /*@}*/
Kojto 90:cb3d968589d8 992
Kojto 90:cb3d968589d8 993 /*******************************************************************************
Kojto 90:cb3d968589d8 994 * hw_axbs_t - module struct
Kojto 90:cb3d968589d8 995 ******************************************************************************/
Kojto 90:cb3d968589d8 996 /*!
Kojto 90:cb3d968589d8 997 * @brief All AXBS module registers.
Kojto 90:cb3d968589d8 998 */
Kojto 90:cb3d968589d8 999 #pragma pack(1)
Kojto 90:cb3d968589d8 1000 typedef struct _hw_axbs
Kojto 90:cb3d968589d8 1001 {
Kojto 90:cb3d968589d8 1002 struct {
Kojto 90:cb3d968589d8 1003 __IO hw_axbs_prsn_t PRSn; /*!< [0x0] Priority Registers Slave */
Kojto 90:cb3d968589d8 1004 uint8_t _reserved0[12];
Kojto 90:cb3d968589d8 1005 __IO hw_axbs_crsn_t CRSn; /*!< [0x10] Control Register */
Kojto 90:cb3d968589d8 1006 uint8_t _reserved1[236];
Kojto 90:cb3d968589d8 1007 } SLAVE[5];
Kojto 90:cb3d968589d8 1008 uint8_t _reserved0[768];
Kojto 90:cb3d968589d8 1009 __IO hw_axbs_mgpcr0_t MGPCR0; /*!< [0x800] Master General Purpose Control Register */
Kojto 90:cb3d968589d8 1010 uint8_t _reserved1[252];
Kojto 90:cb3d968589d8 1011 __IO hw_axbs_mgpcr1_t MGPCR1; /*!< [0x900] Master General Purpose Control Register */
Kojto 90:cb3d968589d8 1012 uint8_t _reserved2[252];
Kojto 90:cb3d968589d8 1013 __IO hw_axbs_mgpcr2_t MGPCR2; /*!< [0xA00] Master General Purpose Control Register */
Kojto 90:cb3d968589d8 1014 uint8_t _reserved3[252];
Kojto 90:cb3d968589d8 1015 __IO hw_axbs_mgpcr3_t MGPCR3; /*!< [0xB00] Master General Purpose Control Register */
Kojto 90:cb3d968589d8 1016 uint8_t _reserved4[252];
Kojto 90:cb3d968589d8 1017 __IO hw_axbs_mgpcr4_t MGPCR4; /*!< [0xC00] Master General Purpose Control Register */
Kojto 90:cb3d968589d8 1018 uint8_t _reserved5[252];
Kojto 90:cb3d968589d8 1019 __IO hw_axbs_mgpcr5_t MGPCR5; /*!< [0xD00] Master General Purpose Control Register */
Kojto 90:cb3d968589d8 1020 } hw_axbs_t;
Kojto 90:cb3d968589d8 1021 #pragma pack()
Kojto 90:cb3d968589d8 1022
Kojto 90:cb3d968589d8 1023 /*! @brief Macro to access all AXBS registers. */
Kojto 90:cb3d968589d8 1024 /*! @param x AXBS module instance base address. */
Kojto 90:cb3d968589d8 1025 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 1026 * use the '&' operator, like <code>&HW_AXBS(AXBS_BASE)</code>. */
Kojto 90:cb3d968589d8 1027 #define HW_AXBS(x) (*(hw_axbs_t *)(x))
Kojto 90:cb3d968589d8 1028
Kojto 90:cb3d968589d8 1029 #endif /* __HW_AXBS_REGISTERS_H__ */
Kojto 90:cb3d968589d8 1030 /* EOF */