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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F410RB/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
128:9bcdf88f62b0
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**
Kojto 122:f9eeca106725 2 ******************************************************************************
Kojto 122:f9eeca106725 3 * @file stm32f4xx_ll_sdmmc.h
Kojto 122:f9eeca106725 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.0
Kojto 122:f9eeca106725 6 * @date 06-May-2016
Kojto 122:f9eeca106725 7 * @brief Header file of SDMMC HAL module.
Kojto 122:f9eeca106725 8 ******************************************************************************
Kojto 122:f9eeca106725 9 * @attention
Kojto 122:f9eeca106725 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 122:f9eeca106725 12 *
Kojto 122:f9eeca106725 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 14 * are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 122:f9eeca106725 16 * this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 122:f9eeca106725 18 * this list of conditions and the following disclaimer in the documentation
Kojto 122:f9eeca106725 19 * and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 122:f9eeca106725 21 * may be used to endorse or promote products derived from this software
Kojto 122:f9eeca106725 22 * without specific prior written permission.
Kojto 122:f9eeca106725 23 *
Kojto 122:f9eeca106725 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 122:f9eeca106725 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 122:f9eeca106725 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 122:f9eeca106725 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 122:f9eeca106725 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 122:f9eeca106725 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 122:f9eeca106725 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 34 *
Kojto 122:f9eeca106725 35 ******************************************************************************
Kojto 122:f9eeca106725 36 */
Kojto 122:f9eeca106725 37
Kojto 122:f9eeca106725 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 122:f9eeca106725 39 #ifndef __STM32F4xx_LL_SDMMC_H
Kojto 122:f9eeca106725 40 #define __STM32F4xx_LL_SDMMC_H
Kojto 122:f9eeca106725 41
Kojto 122:f9eeca106725 42 #ifdef __cplusplus
Kojto 122:f9eeca106725 43 extern "C" {
Kojto 122:f9eeca106725 44 #endif
Kojto 122:f9eeca106725 45 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
Kojto 122:f9eeca106725 46 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
Kojto 122:f9eeca106725 47 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
Kojto 122:f9eeca106725 48 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
Kojto 122:f9eeca106725 49 defined(STM32F412Rx) || defined(STM32F412Cx)
Kojto 122:f9eeca106725 50 /* Includes ------------------------------------------------------------------*/
Kojto 122:f9eeca106725 51 #include "stm32f4xx_hal_def.h"
Kojto 122:f9eeca106725 52
Kojto 122:f9eeca106725 53 /** @addtogroup STM32F4xx_Driver
Kojto 122:f9eeca106725 54 * @{
Kojto 122:f9eeca106725 55 */
Kojto 122:f9eeca106725 56
Kojto 122:f9eeca106725 57 /** @addtogroup SDMMC_LL
Kojto 122:f9eeca106725 58 * @{
Kojto 122:f9eeca106725 59 */
Kojto 122:f9eeca106725 60
Kojto 122:f9eeca106725 61 /* Exported types ------------------------------------------------------------*/
Kojto 122:f9eeca106725 62 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
Kojto 122:f9eeca106725 63 * @{
Kojto 122:f9eeca106725 64 */
Kojto 122:f9eeca106725 65
Kojto 122:f9eeca106725 66 /**
Kojto 122:f9eeca106725 67 * @brief SDMMC Configuration Structure definition
Kojto 122:f9eeca106725 68 */
Kojto 122:f9eeca106725 69 typedef struct
Kojto 122:f9eeca106725 70 {
Kojto 122:f9eeca106725 71 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
Kojto 122:f9eeca106725 72 This parameter can be a value of @ref SDIO_Clock_Edge */
Kojto 122:f9eeca106725 73
Kojto 122:f9eeca106725 74 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
Kojto 122:f9eeca106725 75 enabled or disabled.
Kojto 122:f9eeca106725 76 This parameter can be a value of @ref SDIO_Clock_Bypass */
Kojto 122:f9eeca106725 77
Kojto 122:f9eeca106725 78 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
Kojto 122:f9eeca106725 79 disabled when the bus is idle.
Kojto 122:f9eeca106725 80 This parameter can be a value of @ref SDIO_Clock_Power_Save */
Kojto 122:f9eeca106725 81
Kojto 122:f9eeca106725 82 uint32_t BusWide; /*!< Specifies the SDIO bus width.
Kojto 122:f9eeca106725 83 This parameter can be a value of @ref SDIO_Bus_Wide */
Kojto 122:f9eeca106725 84
Kojto 122:f9eeca106725 85 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
Kojto 122:f9eeca106725 86 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
Kojto 122:f9eeca106725 87
Kojto 122:f9eeca106725 88 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
Kojto 122:f9eeca106725 89 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto 122:f9eeca106725 90
Kojto 122:f9eeca106725 91 }SDIO_InitTypeDef;
Kojto 122:f9eeca106725 92
Kojto 122:f9eeca106725 93
Kojto 122:f9eeca106725 94 /**
Kojto 122:f9eeca106725 95 * @brief SDIO Command Control structure
Kojto 122:f9eeca106725 96 */
Kojto 122:f9eeca106725 97 typedef struct
Kojto 122:f9eeca106725 98 {
Kojto 122:f9eeca106725 99 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
Kojto 122:f9eeca106725 100 to a card as part of a command message. If a command
Kojto 122:f9eeca106725 101 contains an argument, it must be loaded into this register
Kojto 122:f9eeca106725 102 before writing the command to the command register. */
Kojto 122:f9eeca106725 103
Kojto 122:f9eeca106725 104 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
Kojto 122:f9eeca106725 105 Max_Data = 64 */
Kojto 122:f9eeca106725 106
Kojto 122:f9eeca106725 107 uint32_t Response; /*!< Specifies the SDIO response type.
Kojto 122:f9eeca106725 108 This parameter can be a value of @ref SDIO_Response_Type */
Kojto 122:f9eeca106725 109
Kojto 122:f9eeca106725 110 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
Kojto 122:f9eeca106725 111 enabled or disabled.
Kojto 122:f9eeca106725 112 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
Kojto 122:f9eeca106725 113
Kojto 122:f9eeca106725 114 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
Kojto 122:f9eeca106725 115 is enabled or disabled.
Kojto 122:f9eeca106725 116 This parameter can be a value of @ref SDIO_CPSM_State */
Kojto 122:f9eeca106725 117 }SDIO_CmdInitTypeDef;
Kojto 122:f9eeca106725 118
Kojto 122:f9eeca106725 119
Kojto 122:f9eeca106725 120 /**
Kojto 122:f9eeca106725 121 * @brief SDIO Data Control structure
Kojto 122:f9eeca106725 122 */
Kojto 122:f9eeca106725 123 typedef struct
Kojto 122:f9eeca106725 124 {
Kojto 122:f9eeca106725 125 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
Kojto 122:f9eeca106725 126
Kojto 122:f9eeca106725 127 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
Kojto 122:f9eeca106725 128
Kojto 122:f9eeca106725 129 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
Kojto 122:f9eeca106725 130 This parameter can be a value of @ref SDIO_Data_Block_Size */
Kojto 122:f9eeca106725 131
Kojto 122:f9eeca106725 132 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
Kojto 122:f9eeca106725 133 is a read or write.
Kojto 122:f9eeca106725 134 This parameter can be a value of @ref SDIO_Transfer_Direction */
Kojto 122:f9eeca106725 135
Kojto 122:f9eeca106725 136 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
Kojto 122:f9eeca106725 137 This parameter can be a value of @ref SDIO_Transfer_Type */
Kojto 122:f9eeca106725 138
Kojto 122:f9eeca106725 139 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
Kojto 122:f9eeca106725 140 is enabled or disabled.
Kojto 122:f9eeca106725 141 This parameter can be a value of @ref SDIO_DPSM_State */
Kojto 122:f9eeca106725 142 }SDIO_DataInitTypeDef;
Kojto 122:f9eeca106725 143
Kojto 122:f9eeca106725 144 /**
Kojto 122:f9eeca106725 145 * @}
Kojto 122:f9eeca106725 146 */
Kojto 122:f9eeca106725 147
Kojto 122:f9eeca106725 148 /* Exported constants --------------------------------------------------------*/
Kojto 122:f9eeca106725 149 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
Kojto 122:f9eeca106725 150 * @{
Kojto 122:f9eeca106725 151 */
Kojto 122:f9eeca106725 152
Kojto 122:f9eeca106725 153 /** @defgroup SDIO_Clock_Edge Clock Edge
Kojto 122:f9eeca106725 154 * @{
Kojto 122:f9eeca106725 155 */
Kojto 122:f9eeca106725 156 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 157 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
Kojto 122:f9eeca106725 158
Kojto 122:f9eeca106725 159 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
Kojto 122:f9eeca106725 160 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
Kojto 122:f9eeca106725 161 /**
Kojto 122:f9eeca106725 162 * @}
Kojto 122:f9eeca106725 163 */
Kojto 122:f9eeca106725 164
Kojto 122:f9eeca106725 165 /** @defgroup SDIO_Clock_Bypass Clock Bypass
Kojto 122:f9eeca106725 166 * @{
Kojto 122:f9eeca106725 167 */
Kojto 122:f9eeca106725 168 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 169 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
Kojto 122:f9eeca106725 170
Kojto 122:f9eeca106725 171 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
Kojto 122:f9eeca106725 172 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
Kojto 122:f9eeca106725 173 /**
Kojto 122:f9eeca106725 174 * @}
Kojto 122:f9eeca106725 175 */
Kojto 122:f9eeca106725 176
Kojto 122:f9eeca106725 177 /** @defgroup SDIO_Clock_Power_Save Clock Power Saving
Kojto 122:f9eeca106725 178 * @{
Kojto 122:f9eeca106725 179 */
Kojto 122:f9eeca106725 180 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 181 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
Kojto 122:f9eeca106725 182
Kojto 122:f9eeca106725 183 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
Kojto 122:f9eeca106725 184 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
Kojto 122:f9eeca106725 185 /**
Kojto 122:f9eeca106725 186 * @}
Kojto 122:f9eeca106725 187 */
Kojto 122:f9eeca106725 188
Kojto 122:f9eeca106725 189 /** @defgroup SDIO_Bus_Wide Bus Width
Kojto 122:f9eeca106725 190 * @{
Kojto 122:f9eeca106725 191 */
Kojto 122:f9eeca106725 192 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 193 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
Kojto 122:f9eeca106725 194 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
Kojto 122:f9eeca106725 195
Kojto 122:f9eeca106725 196 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
Kojto 122:f9eeca106725 197 ((WIDE) == SDIO_BUS_WIDE_4B) || \
Kojto 122:f9eeca106725 198 ((WIDE) == SDIO_BUS_WIDE_8B))
Kojto 122:f9eeca106725 199 /**
Kojto 122:f9eeca106725 200 * @}
Kojto 122:f9eeca106725 201 */
Kojto 122:f9eeca106725 202
Kojto 122:f9eeca106725 203 /** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
Kojto 122:f9eeca106725 204 * @{
Kojto 122:f9eeca106725 205 */
Kojto 122:f9eeca106725 206 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 207 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
Kojto 122:f9eeca106725 208
Kojto 122:f9eeca106725 209 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
Kojto 122:f9eeca106725 210 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
Kojto 122:f9eeca106725 211 /**
Kojto 122:f9eeca106725 212 * @}
Kojto 122:f9eeca106725 213 */
Kojto 122:f9eeca106725 214
Kojto 122:f9eeca106725 215 /** @defgroup SDIO_Clock_Division Clock Division
Kojto 122:f9eeca106725 216 * @{
Kojto 122:f9eeca106725 217 */
Kojto 122:f9eeca106725 218 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
Kojto 122:f9eeca106725 219 /**
Kojto 122:f9eeca106725 220 * @}
Kojto 122:f9eeca106725 221 */
Kojto 122:f9eeca106725 222
Kojto 122:f9eeca106725 223 /** @defgroup SDIO_Command_Index Command Index
Kojto 122:f9eeca106725 224 * @{
Kojto 122:f9eeca106725 225 */
Kojto 122:f9eeca106725 226 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
Kojto 122:f9eeca106725 227 /**
Kojto 122:f9eeca106725 228 * @}
Kojto 122:f9eeca106725 229 */
Kojto 122:f9eeca106725 230
Kojto 122:f9eeca106725 231 /** @defgroup SDIO_Response_Type Response Type
Kojto 122:f9eeca106725 232 * @{
Kojto 122:f9eeca106725 233 */
Kojto 122:f9eeca106725 234 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 235 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
Kojto 122:f9eeca106725 236 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
Kojto 122:f9eeca106725 237
Kojto 122:f9eeca106725 238 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
Kojto 122:f9eeca106725 239 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
Kojto 122:f9eeca106725 240 ((RESPONSE) == SDIO_RESPONSE_LONG))
Kojto 122:f9eeca106725 241 /**
Kojto 122:f9eeca106725 242 * @}
Kojto 122:f9eeca106725 243 */
Kojto 122:f9eeca106725 244
Kojto 122:f9eeca106725 245 /** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
Kojto 122:f9eeca106725 246 * @{
Kojto 122:f9eeca106725 247 */
Kojto 122:f9eeca106725 248 #define SDIO_WAIT_NO ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 249 #define SDIO_WAIT_IT SDIO_CMD_WAITINT
Kojto 122:f9eeca106725 250 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
Kojto 122:f9eeca106725 251
Kojto 122:f9eeca106725 252 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
Kojto 122:f9eeca106725 253 ((WAIT) == SDIO_WAIT_IT) || \
Kojto 122:f9eeca106725 254 ((WAIT) == SDIO_WAIT_PEND))
Kojto 122:f9eeca106725 255 /**
Kojto 122:f9eeca106725 256 * @}
Kojto 122:f9eeca106725 257 */
Kojto 122:f9eeca106725 258
Kojto 122:f9eeca106725 259 /** @defgroup SDIO_CPSM_State CPSM State
Kojto 122:f9eeca106725 260 * @{
Kojto 122:f9eeca106725 261 */
Kojto 122:f9eeca106725 262 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 263 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
Kojto 122:f9eeca106725 264
Kojto 122:f9eeca106725 265 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
Kojto 122:f9eeca106725 266 ((CPSM) == SDIO_CPSM_ENABLE))
Kojto 122:f9eeca106725 267 /**
Kojto 122:f9eeca106725 268 * @}
Kojto 122:f9eeca106725 269 */
Kojto 122:f9eeca106725 270
Kojto 122:f9eeca106725 271 /** @defgroup SDIO_Response_Registers Response Register
Kojto 122:f9eeca106725 272 * @{
Kojto 122:f9eeca106725 273 */
Kojto 122:f9eeca106725 274 #define SDIO_RESP1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 275 #define SDIO_RESP2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 276 #define SDIO_RESP3 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 277 #define SDIO_RESP4 ((uint32_t)0x0000000CU)
Kojto 122:f9eeca106725 278
Kojto 122:f9eeca106725 279 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
Kojto 122:f9eeca106725 280 ((RESP) == SDIO_RESP2) || \
Kojto 122:f9eeca106725 281 ((RESP) == SDIO_RESP3) || \
Kojto 122:f9eeca106725 282 ((RESP) == SDIO_RESP4))
Kojto 122:f9eeca106725 283 /**
Kojto 122:f9eeca106725 284 * @}
Kojto 122:f9eeca106725 285 */
Kojto 122:f9eeca106725 286
Kojto 122:f9eeca106725 287 /** @defgroup SDIO_Data_Length Data Lenght
Kojto 122:f9eeca106725 288 * @{
Kojto 122:f9eeca106725 289 */
Kojto 122:f9eeca106725 290 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
Kojto 122:f9eeca106725 291 /**
Kojto 122:f9eeca106725 292 * @}
Kojto 122:f9eeca106725 293 */
Kojto 122:f9eeca106725 294
Kojto 122:f9eeca106725 295 /** @defgroup SDIO_Data_Block_Size Data Block Size
Kojto 122:f9eeca106725 296 * @{
Kojto 122:f9eeca106725 297 */
Kojto 122:f9eeca106725 298 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 299 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
Kojto 122:f9eeca106725 300 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
Kojto 122:f9eeca106725 301 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030U)
Kojto 122:f9eeca106725 302 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
Kojto 122:f9eeca106725 303 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050U)
Kojto 122:f9eeca106725 304 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060U)
Kojto 122:f9eeca106725 305 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070U)
Kojto 122:f9eeca106725 306 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
Kojto 122:f9eeca106725 307 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090U)
Kojto 122:f9eeca106725 308 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0U)
Kojto 122:f9eeca106725 309 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0U)
Kojto 122:f9eeca106725 310 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0U)
Kojto 122:f9eeca106725 311 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0U)
Kojto 122:f9eeca106725 312 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0U)
Kojto 122:f9eeca106725 313
Kojto 122:f9eeca106725 314 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
Kojto 122:f9eeca106725 315 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
Kojto 122:f9eeca106725 316 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
Kojto 122:f9eeca106725 317 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
Kojto 122:f9eeca106725 318 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
Kojto 122:f9eeca106725 319 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
Kojto 122:f9eeca106725 320 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
Kojto 122:f9eeca106725 321 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
Kojto 122:f9eeca106725 322 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
Kojto 122:f9eeca106725 323 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
Kojto 122:f9eeca106725 324 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
Kojto 122:f9eeca106725 325 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
Kojto 122:f9eeca106725 326 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
Kojto 122:f9eeca106725 327 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
Kojto 122:f9eeca106725 328 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
Kojto 122:f9eeca106725 329 /**
Kojto 122:f9eeca106725 330 * @}
Kojto 122:f9eeca106725 331 */
Kojto 122:f9eeca106725 332
Kojto 122:f9eeca106725 333 /** @defgroup SDIO_Transfer_Direction Transfer Direction
Kojto 122:f9eeca106725 334 * @{
Kojto 122:f9eeca106725 335 */
Kojto 122:f9eeca106725 336 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 337 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
Kojto 122:f9eeca106725 338
Kojto 122:f9eeca106725 339 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
Kojto 122:f9eeca106725 340 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
Kojto 122:f9eeca106725 341 /**
Kojto 122:f9eeca106725 342 * @}
Kojto 122:f9eeca106725 343 */
Kojto 122:f9eeca106725 344
Kojto 122:f9eeca106725 345 /** @defgroup SDIO_Transfer_Type Transfer Type
Kojto 122:f9eeca106725 346 * @{
Kojto 122:f9eeca106725 347 */
Kojto 122:f9eeca106725 348 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 349 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
Kojto 122:f9eeca106725 350
Kojto 122:f9eeca106725 351 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
Kojto 122:f9eeca106725 352 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
Kojto 122:f9eeca106725 353 /**
Kojto 122:f9eeca106725 354 * @}
Kojto 122:f9eeca106725 355 */
Kojto 122:f9eeca106725 356
Kojto 122:f9eeca106725 357 /** @defgroup SDIO_DPSM_State DPSM State
Kojto 122:f9eeca106725 358 * @{
Kojto 122:f9eeca106725 359 */
Kojto 122:f9eeca106725 360 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 361 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
Kojto 122:f9eeca106725 362
Kojto 122:f9eeca106725 363 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
Kojto 122:f9eeca106725 364 ((DPSM) == SDIO_DPSM_ENABLE))
Kojto 122:f9eeca106725 365 /**
Kojto 122:f9eeca106725 366 * @}
Kojto 122:f9eeca106725 367 */
Kojto 122:f9eeca106725 368
Kojto 122:f9eeca106725 369 /** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
Kojto 122:f9eeca106725 370 * @{
Kojto 122:f9eeca106725 371 */
Kojto 122:f9eeca106725 372 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 373 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 374
Kojto 122:f9eeca106725 375 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
Kojto 122:f9eeca106725 376 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
Kojto 122:f9eeca106725 377 /**
Kojto 122:f9eeca106725 378 * @}
Kojto 122:f9eeca106725 379 */
Kojto 122:f9eeca106725 380
Kojto 122:f9eeca106725 381 /** @defgroup SDIO_Interrupt_sources Interrupt Sources
Kojto 122:f9eeca106725 382 * @{
Kojto 122:f9eeca106725 383 */
Kojto 122:f9eeca106725 384 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
Kojto 122:f9eeca106725 385 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
Kojto 122:f9eeca106725 386 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
Kojto 122:f9eeca106725 387 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
Kojto 122:f9eeca106725 388 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
Kojto 122:f9eeca106725 389 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
Kojto 122:f9eeca106725 390 #define SDIO_IT_CMDREND SDIO_STA_CMDREND
Kojto 122:f9eeca106725 391 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
Kojto 122:f9eeca106725 392 #define SDIO_IT_DATAEND SDIO_STA_DATAEND
Kojto 122:f9eeca106725 393 #define SDIO_IT_STBITERR SDIO_STA_STBITERR
Kojto 122:f9eeca106725 394 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
Kojto 122:f9eeca106725 395 #define SDIO_IT_CMDACT SDIO_STA_CMDACT
Kojto 122:f9eeca106725 396 #define SDIO_IT_TXACT SDIO_STA_TXACT
Kojto 122:f9eeca106725 397 #define SDIO_IT_RXACT SDIO_STA_RXACT
Kojto 122:f9eeca106725 398 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
Kojto 122:f9eeca106725 399 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
Kojto 122:f9eeca106725 400 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
Kojto 122:f9eeca106725 401 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
Kojto 122:f9eeca106725 402 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
Kojto 122:f9eeca106725 403 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
Kojto 122:f9eeca106725 404 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
Kojto 122:f9eeca106725 405 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
Kojto 122:f9eeca106725 406 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
Kojto 122:f9eeca106725 407 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
Kojto 122:f9eeca106725 408 /**
Kojto 122:f9eeca106725 409 * @}
Kojto 122:f9eeca106725 410 */
Kojto 122:f9eeca106725 411
Kojto 122:f9eeca106725 412 /** @defgroup SDIO_Flags Flags
Kojto 122:f9eeca106725 413 * @{
Kojto 122:f9eeca106725 414 */
Kojto 122:f9eeca106725 415 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
Kojto 122:f9eeca106725 416 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
Kojto 122:f9eeca106725 417 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
Kojto 122:f9eeca106725 418 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
Kojto 122:f9eeca106725 419 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
Kojto 122:f9eeca106725 420 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
Kojto 122:f9eeca106725 421 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
Kojto 122:f9eeca106725 422 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
Kojto 122:f9eeca106725 423 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
Kojto 122:f9eeca106725 424 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
Kojto 122:f9eeca106725 425 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
Kojto 122:f9eeca106725 426 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
Kojto 122:f9eeca106725 427 #define SDIO_FLAG_TXACT SDIO_STA_TXACT
Kojto 122:f9eeca106725 428 #define SDIO_FLAG_RXACT SDIO_STA_RXACT
Kojto 122:f9eeca106725 429 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
Kojto 122:f9eeca106725 430 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
Kojto 122:f9eeca106725 431 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
Kojto 122:f9eeca106725 432 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
Kojto 122:f9eeca106725 433 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
Kojto 122:f9eeca106725 434 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
Kojto 122:f9eeca106725 435 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
Kojto 122:f9eeca106725 436 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
Kojto 122:f9eeca106725 437 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
Kojto 122:f9eeca106725 438 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
Kojto 122:f9eeca106725 439 /**
Kojto 122:f9eeca106725 440 * @}
Kojto 122:f9eeca106725 441 */
Kojto 122:f9eeca106725 442
Kojto 122:f9eeca106725 443 /**
Kojto 122:f9eeca106725 444 * @}
Kojto 122:f9eeca106725 445 */
Kojto 122:f9eeca106725 446 /* Exported macro ------------------------------------------------------------*/
Kojto 122:f9eeca106725 447 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
Kojto 122:f9eeca106725 448 * @{
Kojto 122:f9eeca106725 449 */
Kojto 122:f9eeca106725 450
Kojto 122:f9eeca106725 451 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
Kojto 122:f9eeca106725 452 * @{
Kojto 122:f9eeca106725 453 */
Kojto 122:f9eeca106725 454 /* ------------ SDIO registers bit address in the alias region -------------- */
Kojto 122:f9eeca106725 455 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
Kojto 122:f9eeca106725 456
Kojto 122:f9eeca106725 457 /* --- CLKCR Register ---*/
Kojto 122:f9eeca106725 458 /* Alias word address of CLKEN bit */
Kojto 122:f9eeca106725 459 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
Kojto 122:f9eeca106725 460 #define CLKEN_BITNUMBER 0x08U
Kojto 122:f9eeca106725 461 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
Kojto 122:f9eeca106725 462
Kojto 122:f9eeca106725 463 /* --- CMD Register ---*/
Kojto 122:f9eeca106725 464 /* Alias word address of SDIOSUSPEND bit */
Kojto 122:f9eeca106725 465 #define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
Kojto 122:f9eeca106725 466 #define SDIOSUSPEND_BITNUMBER 0x0BU
Kojto 122:f9eeca106725 467 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
Kojto 122:f9eeca106725 468
Kojto 122:f9eeca106725 469 /* Alias word address of ENCMDCOMPL bit */
Kojto 122:f9eeca106725 470 #define ENCMDCOMPL_BITNUMBER 0x0CU
Kojto 122:f9eeca106725 471 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
Kojto 122:f9eeca106725 472
Kojto 122:f9eeca106725 473 /* Alias word address of NIEN bit */
Kojto 122:f9eeca106725 474 #define NIEN_BITNUMBER 0x0DU
Kojto 122:f9eeca106725 475 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
Kojto 122:f9eeca106725 476
Kojto 122:f9eeca106725 477 /* Alias word address of ATACMD bit */
Kojto 122:f9eeca106725 478 #define ATACMD_BITNUMBER 0x0EU
Kojto 122:f9eeca106725 479 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
Kojto 122:f9eeca106725 480
Kojto 122:f9eeca106725 481 /* --- DCTRL Register ---*/
Kojto 122:f9eeca106725 482 /* Alias word address of DMAEN bit */
Kojto 122:f9eeca106725 483 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
Kojto 122:f9eeca106725 484 #define DMAEN_BITNUMBER 0x03U
Kojto 122:f9eeca106725 485 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
Kojto 122:f9eeca106725 486
Kojto 122:f9eeca106725 487 /* Alias word address of RWSTART bit */
Kojto 122:f9eeca106725 488 #define RWSTART_BITNUMBER 0x08U
Kojto 122:f9eeca106725 489 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
Kojto 122:f9eeca106725 490
Kojto 122:f9eeca106725 491 /* Alias word address of RWSTOP bit */
Kojto 122:f9eeca106725 492 #define RWSTOP_BITNUMBER 0x09U
Kojto 122:f9eeca106725 493 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
Kojto 122:f9eeca106725 494
Kojto 122:f9eeca106725 495 /* Alias word address of RWMOD bit */
Kojto 122:f9eeca106725 496 #define RWMOD_BITNUMBER 0x0AU
Kojto 122:f9eeca106725 497 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
Kojto 122:f9eeca106725 498
Kojto 122:f9eeca106725 499 /* Alias word address of SDIOEN bit */
Kojto 122:f9eeca106725 500 #define SDIOEN_BITNUMBER 0x0BU
Kojto 122:f9eeca106725 501 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
Kojto 122:f9eeca106725 502 /**
Kojto 122:f9eeca106725 503 * @}
Kojto 122:f9eeca106725 504 */
Kojto 122:f9eeca106725 505
Kojto 122:f9eeca106725 506 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
Kojto 122:f9eeca106725 507 * @brief SDMMC_LL registers bit address in the alias region
Kojto 122:f9eeca106725 508 * @{
Kojto 122:f9eeca106725 509 */
Kojto 122:f9eeca106725 510
Kojto 122:f9eeca106725 511 /* ---------------------- SDIO registers bit mask --------------------------- */
Kojto 122:f9eeca106725 512 /* --- CLKCR Register ---*/
Kojto 122:f9eeca106725 513 /* CLKCR register clear mask */
Kojto 122:f9eeca106725 514 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
Kojto 122:f9eeca106725 515 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
Kojto 122:f9eeca106725 516 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
Kojto 122:f9eeca106725 517
Kojto 122:f9eeca106725 518 /* --- PWRCTRL Register ---*/
Kojto 122:f9eeca106725 519 /* --- DCTRL Register ---*/
Kojto 122:f9eeca106725 520 /* SDIO DCTRL Clear Mask */
Kojto 122:f9eeca106725 521 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
Kojto 122:f9eeca106725 522 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
Kojto 122:f9eeca106725 523
Kojto 122:f9eeca106725 524 /* --- CMD Register ---*/
Kojto 122:f9eeca106725 525 /* CMD Register clear mask */
Kojto 122:f9eeca106725 526 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
Kojto 122:f9eeca106725 527 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
Kojto 122:f9eeca106725 528 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
Kojto 122:f9eeca106725 529
Kojto 122:f9eeca106725 530 /* SDIO RESP Registers Address */
Kojto 122:f9eeca106725 531 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14U))
Kojto 122:f9eeca106725 532
Kojto 122:f9eeca106725 533 /* SDIO Initialization Frequency (400KHz max) */
Kojto 122:f9eeca106725 534 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76U)
Kojto 122:f9eeca106725 535
Kojto 122:f9eeca106725 536 /* SDIO Data Transfer Frequency (25MHz max) */
Kojto 122:f9eeca106725 537 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x00U)
Kojto 122:f9eeca106725 538 /**
Kojto 122:f9eeca106725 539 * @}
Kojto 122:f9eeca106725 540 */
Kojto 122:f9eeca106725 541
Kojto 122:f9eeca106725 542 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
Kojto 122:f9eeca106725 543 * @brief macros to handle interrupts and specific clock configurations
Kojto 122:f9eeca106725 544 * @{
Kojto 122:f9eeca106725 545 */
Kojto 122:f9eeca106725 546
Kojto 122:f9eeca106725 547 /**
Kojto 122:f9eeca106725 548 * @brief Enable the SDIO device.
Kojto 122:f9eeca106725 549 * @retval None
Kojto 122:f9eeca106725 550 */
Kojto 122:f9eeca106725 551 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
Kojto 122:f9eeca106725 552
Kojto 122:f9eeca106725 553 /**
Kojto 122:f9eeca106725 554 * @brief Disable the SDIO device.
Kojto 122:f9eeca106725 555 * @retval None
Kojto 122:f9eeca106725 556 */
Kojto 122:f9eeca106725 557 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
Kojto 122:f9eeca106725 558
Kojto 122:f9eeca106725 559 /**
Kojto 122:f9eeca106725 560 * @brief Enable the SDIO DMA transfer.
Kojto 122:f9eeca106725 561 * @retval None
Kojto 122:f9eeca106725 562 */
Kojto 122:f9eeca106725 563 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
Kojto 122:f9eeca106725 564
Kojto 122:f9eeca106725 565 /**
Kojto 122:f9eeca106725 566 * @brief Disable the SDIO DMA transfer.
Kojto 122:f9eeca106725 567 * @retval None
Kojto 122:f9eeca106725 568 */
Kojto 122:f9eeca106725 569 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
Kojto 122:f9eeca106725 570
Kojto 122:f9eeca106725 571 /**
Kojto 122:f9eeca106725 572 * @brief Enable the SDIO device interrupt.
Kojto 122:f9eeca106725 573 * @param __INSTANCE__ : Pointer to SDIO register base
Kojto 122:f9eeca106725 574 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
Kojto 122:f9eeca106725 575 * This parameter can be one or a combination of the following values:
Kojto 122:f9eeca106725 576 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
Kojto 122:f9eeca106725 577 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
Kojto 122:f9eeca106725 578 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
Kojto 122:f9eeca106725 579 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
Kojto 122:f9eeca106725 580 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
Kojto 122:f9eeca106725 581 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
Kojto 122:f9eeca106725 582 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
Kojto 122:f9eeca106725 583 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
Kojto 122:f9eeca106725 584 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
Kojto 122:f9eeca106725 585 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
Kojto 122:f9eeca106725 586 * bus mode interrupt
Kojto 122:f9eeca106725 587 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
Kojto 122:f9eeca106725 588 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
Kojto 122:f9eeca106725 589 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
Kojto 122:f9eeca106725 590 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
Kojto 122:f9eeca106725 591 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
Kojto 122:f9eeca106725 592 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
Kojto 122:f9eeca106725 593 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
Kojto 122:f9eeca106725 594 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
Kojto 122:f9eeca106725 595 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
Kojto 122:f9eeca106725 596 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
Kojto 122:f9eeca106725 597 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
Kojto 122:f9eeca106725 598 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
Kojto 122:f9eeca106725 599 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
Kojto 122:f9eeca106725 600 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
Kojto 122:f9eeca106725 601 * @retval None
Kojto 122:f9eeca106725 602 */
Kojto 122:f9eeca106725 603 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
Kojto 122:f9eeca106725 604
Kojto 122:f9eeca106725 605 /**
Kojto 122:f9eeca106725 606 * @brief Disable the SDIO device interrupt.
Kojto 122:f9eeca106725 607 * @param __INSTANCE__ : Pointer to SDIO register base
Kojto 122:f9eeca106725 608 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
Kojto 122:f9eeca106725 609 * This parameter can be one or a combination of the following values:
Kojto 122:f9eeca106725 610 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
Kojto 122:f9eeca106725 611 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
Kojto 122:f9eeca106725 612 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
Kojto 122:f9eeca106725 613 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
Kojto 122:f9eeca106725 614 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
Kojto 122:f9eeca106725 615 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
Kojto 122:f9eeca106725 616 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
Kojto 122:f9eeca106725 617 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
Kojto 122:f9eeca106725 618 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
Kojto 122:f9eeca106725 619 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
Kojto 122:f9eeca106725 620 * bus mode interrupt
Kojto 122:f9eeca106725 621 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
Kojto 122:f9eeca106725 622 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
Kojto 122:f9eeca106725 623 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
Kojto 122:f9eeca106725 624 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
Kojto 122:f9eeca106725 625 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
Kojto 122:f9eeca106725 626 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
Kojto 122:f9eeca106725 627 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
Kojto 122:f9eeca106725 628 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
Kojto 122:f9eeca106725 629 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
Kojto 122:f9eeca106725 630 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
Kojto 122:f9eeca106725 631 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
Kojto 122:f9eeca106725 632 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
Kojto 122:f9eeca106725 633 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
Kojto 122:f9eeca106725 634 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
Kojto 122:f9eeca106725 635 * @retval None
Kojto 122:f9eeca106725 636 */
Kojto 122:f9eeca106725 637 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
Kojto 122:f9eeca106725 638
Kojto 122:f9eeca106725 639 /**
Kojto 122:f9eeca106725 640 * @brief Checks whether the specified SDIO flag is set or not.
Kojto 122:f9eeca106725 641 * @param __INSTANCE__ : Pointer to SDIO register base
Kojto 122:f9eeca106725 642 * @param __FLAG__: specifies the flag to check.
Kojto 122:f9eeca106725 643 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 644 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
Kojto 122:f9eeca106725 645 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
Kojto 122:f9eeca106725 646 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
Kojto 122:f9eeca106725 647 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
Kojto 122:f9eeca106725 648 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
Kojto 122:f9eeca106725 649 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
Kojto 122:f9eeca106725 650 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
Kojto 122:f9eeca106725 651 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
Kojto 122:f9eeca106725 652 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
Kojto 122:f9eeca106725 653 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
Kojto 122:f9eeca106725 654 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
Kojto 122:f9eeca106725 655 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
Kojto 122:f9eeca106725 656 * @arg SDIO_FLAG_TXACT: Data transmit in progress
Kojto 122:f9eeca106725 657 * @arg SDIO_FLAG_RXACT: Data receive in progress
Kojto 122:f9eeca106725 658 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
Kojto 122:f9eeca106725 659 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
Kojto 122:f9eeca106725 660 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
Kojto 122:f9eeca106725 661 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
Kojto 122:f9eeca106725 662 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
Kojto 122:f9eeca106725 663 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
Kojto 122:f9eeca106725 664 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
Kojto 122:f9eeca106725 665 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
Kojto 122:f9eeca106725 666 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
Kojto 122:f9eeca106725 667 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
Kojto 122:f9eeca106725 668 * @retval The new state of SDIO_FLAG (SET or RESET).
Kojto 122:f9eeca106725 669 */
Kojto 122:f9eeca106725 670 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
Kojto 122:f9eeca106725 671
Kojto 122:f9eeca106725 672
Kojto 122:f9eeca106725 673 /**
Kojto 122:f9eeca106725 674 * @brief Clears the SDIO pending flags.
Kojto 122:f9eeca106725 675 * @param __INSTANCE__ : Pointer to SDIO register base
Kojto 122:f9eeca106725 676 * @param __FLAG__: specifies the flag to clear.
Kojto 122:f9eeca106725 677 * This parameter can be one or a combination of the following values:
Kojto 122:f9eeca106725 678 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
Kojto 122:f9eeca106725 679 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
Kojto 122:f9eeca106725 680 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
Kojto 122:f9eeca106725 681 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
Kojto 122:f9eeca106725 682 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
Kojto 122:f9eeca106725 683 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
Kojto 122:f9eeca106725 684 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
Kojto 122:f9eeca106725 685 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
Kojto 122:f9eeca106725 686 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
Kojto 122:f9eeca106725 687 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
Kojto 122:f9eeca106725 688 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
Kojto 122:f9eeca106725 689 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
Kojto 122:f9eeca106725 690 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
Kojto 122:f9eeca106725 691 * @retval None
Kojto 122:f9eeca106725 692 */
Kojto 122:f9eeca106725 693 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
Kojto 122:f9eeca106725 694
Kojto 122:f9eeca106725 695 /**
Kojto 122:f9eeca106725 696 * @brief Checks whether the specified SDIO interrupt has occurred or not.
Kojto 122:f9eeca106725 697 * @param __INSTANCE__ : Pointer to SDIO register base
Kojto 122:f9eeca106725 698 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
Kojto 122:f9eeca106725 699 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 700 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
Kojto 122:f9eeca106725 701 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
Kojto 122:f9eeca106725 702 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
Kojto 122:f9eeca106725 703 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
Kojto 122:f9eeca106725 704 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
Kojto 122:f9eeca106725 705 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
Kojto 122:f9eeca106725 706 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
Kojto 122:f9eeca106725 707 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
Kojto 122:f9eeca106725 708 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
Kojto 122:f9eeca106725 709 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
Kojto 122:f9eeca106725 710 * bus mode interrupt
Kojto 122:f9eeca106725 711 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
Kojto 122:f9eeca106725 712 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
Kojto 122:f9eeca106725 713 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
Kojto 122:f9eeca106725 714 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
Kojto 122:f9eeca106725 715 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
Kojto 122:f9eeca106725 716 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
Kojto 122:f9eeca106725 717 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
Kojto 122:f9eeca106725 718 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
Kojto 122:f9eeca106725 719 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
Kojto 122:f9eeca106725 720 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
Kojto 122:f9eeca106725 721 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
Kojto 122:f9eeca106725 722 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
Kojto 122:f9eeca106725 723 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
Kojto 122:f9eeca106725 724 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
Kojto 122:f9eeca106725 725 * @retval The new state of SDIO_IT (SET or RESET).
Kojto 122:f9eeca106725 726 */
Kojto 122:f9eeca106725 727 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
Kojto 122:f9eeca106725 728
Kojto 122:f9eeca106725 729 /**
Kojto 122:f9eeca106725 730 * @brief Clears the SDIO's interrupt pending bits.
Kojto 122:f9eeca106725 731 * @param __INSTANCE__ : Pointer to SDIO register base
Kojto 122:f9eeca106725 732 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto 122:f9eeca106725 733 * This parameter can be one or a combination of the following values:
Kojto 122:f9eeca106725 734 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
Kojto 122:f9eeca106725 735 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
Kojto 122:f9eeca106725 736 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
Kojto 122:f9eeca106725 737 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
Kojto 122:f9eeca106725 738 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
Kojto 122:f9eeca106725 739 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
Kojto 122:f9eeca106725 740 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
Kojto 122:f9eeca106725 741 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
Kojto 122:f9eeca106725 742 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
Kojto 122:f9eeca106725 743 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
Kojto 122:f9eeca106725 744 * bus mode interrupt
Kojto 122:f9eeca106725 745 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
Kojto 122:f9eeca106725 746 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
Kojto 122:f9eeca106725 747 * @retval None
Kojto 122:f9eeca106725 748 */
Kojto 122:f9eeca106725 749 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
Kojto 122:f9eeca106725 750
Kojto 122:f9eeca106725 751 /**
Kojto 122:f9eeca106725 752 * @brief Enable Start the SD I/O Read Wait operation.
Kojto 122:f9eeca106725 753 * @retval None
Kojto 122:f9eeca106725 754 */
Kojto 122:f9eeca106725 755 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
Kojto 122:f9eeca106725 756
Kojto 122:f9eeca106725 757 /**
Kojto 122:f9eeca106725 758 * @brief Disable Start the SD I/O Read Wait operations.
Kojto 122:f9eeca106725 759 * @retval None
Kojto 122:f9eeca106725 760 */
Kojto 122:f9eeca106725 761 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
Kojto 122:f9eeca106725 762
Kojto 122:f9eeca106725 763 /**
Kojto 122:f9eeca106725 764 * @brief Enable Start the SD I/O Read Wait operation.
Kojto 122:f9eeca106725 765 * @retval None
Kojto 122:f9eeca106725 766 */
Kojto 122:f9eeca106725 767 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
Kojto 122:f9eeca106725 768
Kojto 122:f9eeca106725 769 /**
Kojto 122:f9eeca106725 770 * @brief Disable Stop the SD I/O Read Wait operations.
Kojto 122:f9eeca106725 771 * @retval None
Kojto 122:f9eeca106725 772 */
Kojto 122:f9eeca106725 773 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
Kojto 122:f9eeca106725 774
Kojto 122:f9eeca106725 775 /**
Kojto 122:f9eeca106725 776 * @brief Enable the SD I/O Mode Operation.
Kojto 122:f9eeca106725 777 * @retval None
Kojto 122:f9eeca106725 778 */
Kojto 122:f9eeca106725 779 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
Kojto 122:f9eeca106725 780
Kojto 122:f9eeca106725 781 /**
Kojto 122:f9eeca106725 782 * @brief Disable the SD I/O Mode Operation.
Kojto 122:f9eeca106725 783 * @retval None
Kojto 122:f9eeca106725 784 */
Kojto 122:f9eeca106725 785 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
Kojto 122:f9eeca106725 786
Kojto 122:f9eeca106725 787 /**
Kojto 122:f9eeca106725 788 * @brief Enable the SD I/O Suspend command sending.
Kojto 122:f9eeca106725 789 * @retval None
Kojto 122:f9eeca106725 790 */
Kojto 122:f9eeca106725 791 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
Kojto 122:f9eeca106725 792
Kojto 122:f9eeca106725 793 /**
Kojto 122:f9eeca106725 794 * @brief Disable the SD I/O Suspend command sending.
Kojto 122:f9eeca106725 795 * @retval None
Kojto 122:f9eeca106725 796 */
Kojto 122:f9eeca106725 797 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
Kojto 122:f9eeca106725 798
Kojto 122:f9eeca106725 799 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
Kojto 122:f9eeca106725 800 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 122:f9eeca106725 801 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) ||\
Kojto 122:f9eeca106725 802 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
Kojto 122:f9eeca106725 803 /**
Kojto 122:f9eeca106725 804 * @brief Enable the command completion signal.
Kojto 122:f9eeca106725 805 * @retval None
Kojto 122:f9eeca106725 806 */
Kojto 122:f9eeca106725 807 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
Kojto 122:f9eeca106725 808
Kojto 122:f9eeca106725 809 /**
Kojto 122:f9eeca106725 810 * @brief Disable the command completion signal.
Kojto 122:f9eeca106725 811 * @retval None
Kojto 122:f9eeca106725 812 */
Kojto 122:f9eeca106725 813 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
Kojto 122:f9eeca106725 814
Kojto 122:f9eeca106725 815 /**
Kojto 122:f9eeca106725 816 * @brief Enable the CE-ATA interrupt.
Kojto 122:f9eeca106725 817 * @retval None
Kojto 122:f9eeca106725 818 */
Kojto 122:f9eeca106725 819 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
Kojto 122:f9eeca106725 820
Kojto 122:f9eeca106725 821 /**
Kojto 122:f9eeca106725 822 * @brief Disable the CE-ATA interrupt.
Kojto 122:f9eeca106725 823 * @retval None
Kojto 122:f9eeca106725 824 */
Kojto 122:f9eeca106725 825 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
Kojto 122:f9eeca106725 826
Kojto 122:f9eeca106725 827 /**
Kojto 122:f9eeca106725 828 * @brief Enable send CE-ATA command (CMD61).
Kojto 122:f9eeca106725 829 * @retval None
Kojto 122:f9eeca106725 830 */
Kojto 122:f9eeca106725 831 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
Kojto 122:f9eeca106725 832
Kojto 122:f9eeca106725 833 /**
Kojto 122:f9eeca106725 834 * @brief Disable send CE-ATA command (CMD61).
Kojto 122:f9eeca106725 835 * @retval None
Kojto 122:f9eeca106725 836 */
Kojto 122:f9eeca106725 837 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
Kojto 122:f9eeca106725 838 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE ||\
Kojto 122:f9eeca106725 839 STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\
Kojto 122:f9eeca106725 840 STM32F412Cx */
Kojto 122:f9eeca106725 841 /**
Kojto 122:f9eeca106725 842 * @}
Kojto 122:f9eeca106725 843 */
Kojto 122:f9eeca106725 844
Kojto 122:f9eeca106725 845 /**
Kojto 122:f9eeca106725 846 * @}
Kojto 122:f9eeca106725 847 */
Kojto 122:f9eeca106725 848
Kojto 122:f9eeca106725 849 /* Exported functions --------------------------------------------------------*/
Kojto 122:f9eeca106725 850 /** @addtogroup SDMMC_LL_Exported_Functions
Kojto 122:f9eeca106725 851 * @{
Kojto 122:f9eeca106725 852 */
Kojto 122:f9eeca106725 853
Kojto 122:f9eeca106725 854 /* Initialization/de-initialization functions **********************************/
Kojto 122:f9eeca106725 855 /** @addtogroup HAL_SDMMC_LL_Group1
Kojto 122:f9eeca106725 856 * @{
Kojto 122:f9eeca106725 857 */
Kojto 122:f9eeca106725 858 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
Kojto 122:f9eeca106725 859 /**
Kojto 122:f9eeca106725 860 * @}
Kojto 122:f9eeca106725 861 */
Kojto 122:f9eeca106725 862
Kojto 122:f9eeca106725 863 /* I/O operation functions *****************************************************/
Kojto 122:f9eeca106725 864 /** @addtogroup HAL_SDMMC_LL_Group2
Kojto 122:f9eeca106725 865 * @{
Kojto 122:f9eeca106725 866 */
Kojto 122:f9eeca106725 867 /* Blocking mode: Polling */
Kojto 122:f9eeca106725 868 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
Kojto 122:f9eeca106725 869 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
Kojto 122:f9eeca106725 870 /**
Kojto 122:f9eeca106725 871 * @}
Kojto 122:f9eeca106725 872 */
Kojto 122:f9eeca106725 873
Kojto 122:f9eeca106725 874 /* Peripheral Control functions ************************************************/
Kojto 122:f9eeca106725 875 /** @addtogroup HAL_SDMMC_LL_Group3
Kojto 122:f9eeca106725 876 * @{
Kojto 122:f9eeca106725 877 */
Kojto 122:f9eeca106725 878 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
Kojto 122:f9eeca106725 879 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
Kojto 122:f9eeca106725 880 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
Kojto 122:f9eeca106725 881
Kojto 122:f9eeca106725 882 /* Command path state machine (CPSM) management functions */
Kojto 122:f9eeca106725 883 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
Kojto 122:f9eeca106725 884 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
Kojto 122:f9eeca106725 885 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
Kojto 122:f9eeca106725 886
Kojto 122:f9eeca106725 887 /* Data path state machine (DPSM) management functions */
Kojto 122:f9eeca106725 888 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
Kojto 122:f9eeca106725 889 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
Kojto 122:f9eeca106725 890 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
Kojto 122:f9eeca106725 891
Kojto 122:f9eeca106725 892 /* SDIO IO Cards mode management functions */
Kojto 122:f9eeca106725 893 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
Kojto 122:f9eeca106725 894
Kojto 122:f9eeca106725 895 /**
Kojto 122:f9eeca106725 896 * @}
Kojto 122:f9eeca106725 897 */
Kojto 122:f9eeca106725 898
Kojto 122:f9eeca106725 899 /**
Kojto 122:f9eeca106725 900 * @}
Kojto 122:f9eeca106725 901 */
Kojto 122:f9eeca106725 902
Kojto 122:f9eeca106725 903 /**
Kojto 122:f9eeca106725 904 * @}
Kojto 122:f9eeca106725 905 */
Kojto 122:f9eeca106725 906
Kojto 122:f9eeca106725 907 /**
Kojto 122:f9eeca106725 908 * @}
Kojto 122:f9eeca106725 909 */
Kojto 122:f9eeca106725 910 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
Kojto 122:f9eeca106725 911 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
Kojto 122:f9eeca106725 912 STM32F412Rx || STM32F412Cx */
Kojto 122:f9eeca106725 913 #ifdef __cplusplus
Kojto 122:f9eeca106725 914 }
Kojto 122:f9eeca106725 915 #endif
Kojto 122:f9eeca106725 916
Kojto 122:f9eeca106725 917 #endif /* __STM32F4xx_LL_SDMMC_H */
Kojto 122:f9eeca106725 918
Kojto 122:f9eeca106725 919 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/