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TARGET_NUCLEO_F410RB/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:: <>
Date:: Mon Jan 16 12:05:23 2017 +0000
Revision:: 134:ad3be0349dc5
Parent:: 128:9bcdf88f62b0
Child:: 145:64910690c574

Release 134 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	89:552587b429a1	1	/**
bogdanm	89:552587b429a1	2	******************************************************************************
bogdanm	89:552587b429a1	3	* @file stm32f4xx_hal_rcc_ex.h
bogdanm	89:552587b429a1	4	* @author MCD Application Team
Kojto	122:f9eeca106725	5	* @version V1.5.0
Kojto	122:f9eeca106725	6	* @date 06-May-2016
bogdanm	89:552587b429a1	7	* @brief Header file of RCC HAL Extension module.
bogdanm	89:552587b429a1	8	******************************************************************************
bogdanm	89:552587b429a1	9	* @attention
bogdanm	89:552587b429a1	10	*
Kojto	122:f9eeca106725	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	89:552587b429a1	12	*
bogdanm	89:552587b429a1	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	89:552587b429a1	14	* are permitted provided that the following conditions are met:
bogdanm	89:552587b429a1	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	89:552587b429a1	16	* this list of conditions and the following disclaimer.
bogdanm	89:552587b429a1	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	89:552587b429a1	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	89:552587b429a1	19	* and/or other materials provided with the distribution.
bogdanm	89:552587b429a1	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	89:552587b429a1	21	* may be used to endorse or promote products derived from this software
bogdanm	89:552587b429a1	22	* without specific prior written permission.
bogdanm	89:552587b429a1	23	*
bogdanm	89:552587b429a1	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	89:552587b429a1	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	89:552587b429a1	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	89:552587b429a1	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	89:552587b429a1	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	89:552587b429a1	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	89:552587b429a1	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	89:552587b429a1	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	89:552587b429a1	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	89:552587b429a1	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	89:552587b429a1	34	*
bogdanm	89:552587b429a1	35	******************************************************************************
bogdanm	89:552587b429a1	36	*/
bogdanm	89:552587b429a1	37
bogdanm	89:552587b429a1	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	89:552587b429a1	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
bogdanm	89:552587b429a1	40	#define __STM32F4xx_HAL_RCC_EX_H
bogdanm	89:552587b429a1	41
bogdanm	89:552587b429a1	42	#ifdef __cplusplus
bogdanm	89:552587b429a1	43	extern "C" {
bogdanm	89:552587b429a1	44	#endif
bogdanm	89:552587b429a1	45
bogdanm	89:552587b429a1	46	/* Includes ------------------------------------------------------------------*/
bogdanm	89:552587b429a1	47	#include "stm32f4xx_hal_def.h"
bogdanm	89:552587b429a1	48
bogdanm	89:552587b429a1	49	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	89:552587b429a1	50	* @{
bogdanm	89:552587b429a1	51	*/
bogdanm	89:552587b429a1	52
bogdanm	89:552587b429a1	53	/** @addtogroup RCCEx
bogdanm	89:552587b429a1	54	* @{
bogdanm	89:552587b429a1	55	*/
bogdanm	89:552587b429a1	56
Kojto	99:dbbf35b96557	57	/* Exported types ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto	99:dbbf35b96557	59	* @{
Kojto	99:dbbf35b96557	60	*/
Kojto	99:dbbf35b96557	61
Kojto	99:dbbf35b96557	62	/**
Kojto	99:dbbf35b96557	63	* @brief RCC PLL configuration structure definition
Kojto	99:dbbf35b96557	64	*/
Kojto	99:dbbf35b96557	65	typedef struct
Kojto	99:dbbf35b96557	66	{
Kojto	99:dbbf35b96557	67	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	99:dbbf35b96557	68	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	99:dbbf35b96557	69
Kojto	99:dbbf35b96557	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto	110:165afa46840b	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	99:dbbf35b96557	72
Kojto	99:dbbf35b96557	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto	110:165afa46840b	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
Kojto	99:dbbf35b96557	75
Kojto	99:dbbf35b96557	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto	122:f9eeca106725	77	This parameter must be a number between Min_Data = 50 and Max_Data = 432
Kojto	122:f9eeca106725	78	except for STM32F411xE devices where the Min_Data = 192 */
Kojto	99:dbbf35b96557	79
Kojto	99:dbbf35b96557	80	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
Kojto	99:dbbf35b96557	81	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto	99:dbbf35b96557	82
Kojto	99:dbbf35b96557	83	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	84	This parameter must be a number between Min_Data = 4 and Max_Data = 15 */
Kojto	110:165afa46840b	85	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
Kojto	122:f9eeca106725	86	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	99:dbbf35b96557	87	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto	122:f9eeca106725	88	This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
Kojto	122:f9eeca106725	89	and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
Kojto	99:dbbf35b96557	90	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
Kojto	122:f9eeca106725	91	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	99:dbbf35b96557	92	}RCC_PLLInitTypeDef;
Kojto	99:dbbf35b96557	93
Kojto	99:dbbf35b96557	94	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	95	/**
Kojto	99:dbbf35b96557	96	* @brief PLLI2S Clock structure definition
Kojto	99:dbbf35b96557	97	*/
Kojto	99:dbbf35b96557	98	typedef struct
Kojto	99:dbbf35b96557	99	{
Kojto	99:dbbf35b96557	100	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
Kojto	110:165afa46840b	101	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	99:dbbf35b96557	102
Kojto	99:dbbf35b96557	103	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	104	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
Kojto	99:dbbf35b96557	105
Kojto	99:dbbf35b96557	106	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
Kojto	99:dbbf35b96557	107	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
Kojto	99:dbbf35b96557	108
Kojto	99:dbbf35b96557	109	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
Kojto	99:dbbf35b96557	110	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	110:165afa46840b	111	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	112
Kojto	99:dbbf35b96557	113	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	99:dbbf35b96557	114	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	115	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
Kojto	99:dbbf35b96557	116	}RCC_PLLI2SInitTypeDef;
Kojto	99:dbbf35b96557	117
Kojto	99:dbbf35b96557	118	/**
Kojto	99:dbbf35b96557	119	* @brief PLLSAI Clock structure definition
Kojto	99:dbbf35b96557	120	*/
Kojto	99:dbbf35b96557	121	typedef struct
Kojto	99:dbbf35b96557	122	{
Kojto	99:dbbf35b96557	123	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
Kojto	110:165afa46840b	124	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	99:dbbf35b96557	125
Kojto	99:dbbf35b96557	126	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	127	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
Kojto	99:dbbf35b96557	128
Kojto	99:dbbf35b96557	129	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	130	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
Kojto	99:dbbf35b96557	131
Kojto	99:dbbf35b96557	132	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
Kojto	99:dbbf35b96557	133	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	134	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	135	}RCC_PLLSAIInitTypeDef;
Kojto	122:f9eeca106725	136
Kojto	99:dbbf35b96557	137	/**
Kojto	99:dbbf35b96557	138	* @brief RCC extended clocks structure definition
Kojto	99:dbbf35b96557	139	*/
Kojto	99:dbbf35b96557	140	typedef struct
Kojto	99:dbbf35b96557	141	{
Kojto	99:dbbf35b96557	142	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	99:dbbf35b96557	143	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	99:dbbf35b96557	144
Kojto	99:dbbf35b96557	145	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	99:dbbf35b96557	146	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	99:dbbf35b96557	147
Kojto	99:dbbf35b96557	148	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto	99:dbbf35b96557	149	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto	99:dbbf35b96557	150
Kojto	99:dbbf35b96557	151	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	99:dbbf35b96557	152	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	99:dbbf35b96557	153	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	154
Kojto	99:dbbf35b96557	155	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	99:dbbf35b96557	156	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	99:dbbf35b96557	157	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	99:dbbf35b96557	158
Kojto	99:dbbf35b96557	159	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
Kojto	99:dbbf35b96557	160	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto	99:dbbf35b96557	161
Kojto	99:dbbf35b96557	162	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
Kojto	99:dbbf35b96557	163	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto	99:dbbf35b96557	164
Kojto	99:dbbf35b96557	165	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
Kojto	99:dbbf35b96557	166	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
Kojto	99:dbbf35b96557	167
Kojto	99:dbbf35b96557	168	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
Kojto	99:dbbf35b96557	169	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
Kojto	99:dbbf35b96557	170
Kojto	99:dbbf35b96557	171	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	99:dbbf35b96557	172	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	99:dbbf35b96557	173
Kojto	99:dbbf35b96557	174	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto	99:dbbf35b96557	175	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto	99:dbbf35b96557	176
Kojto	99:dbbf35b96557	177	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
Kojto	99:dbbf35b96557	178	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	99:dbbf35b96557	179
Kojto	99:dbbf35b96557	180	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto	99:dbbf35b96557	181	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto	99:dbbf35b96557	182
Kojto	99:dbbf35b96557	183	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
Kojto	99:dbbf35b96557	184	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
Kojto	99:dbbf35b96557	185
Kojto	122:f9eeca106725	186	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto	122:f9eeca106725	187	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
Kojto	99:dbbf35b96557	188
Kojto	99:dbbf35b96557	189	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	99:dbbf35b96557	190	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	99:dbbf35b96557	191	}RCC_PeriphCLKInitTypeDef;
Kojto	99:dbbf35b96557	192	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	193
Kojto	110:165afa46840b	194	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	195	/**
Kojto	110:165afa46840b	196	* @brief RCC extended clocks structure definition
Kojto	110:165afa46840b	197	*/
Kojto	110:165afa46840b	198	typedef struct
Kojto	110:165afa46840b	199	{
Kojto	110:165afa46840b	200	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	110:165afa46840b	201	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	110:165afa46840b	202
Kojto	110:165afa46840b	203	uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	110:165afa46840b	204	This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
Kojto	110:165afa46840b	205
Kojto	110:165afa46840b	206	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	110:165afa46840b	207	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	110:165afa46840b	208
Kojto	110:165afa46840b	209	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
Kojto	110:165afa46840b	210	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Kojto	110:165afa46840b	211
Kojto	110:165afa46840b	212	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto	122:f9eeca106725	213	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto	122:f9eeca106725	214
Kojto	110:165afa46840b	215	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	110:165afa46840b	216	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	110:165afa46840b	217	}RCC_PeriphCLKInitTypeDef;
Kojto	110:165afa46840b	218	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	219
Kojto	122:f9eeca106725	220	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	122:f9eeca106725	221	/**
Kojto	122:f9eeca106725	222	* @brief PLLI2S Clock structure definition
Kojto	122:f9eeca106725	223	*/
Kojto	122:f9eeca106725	224	typedef struct
Kojto	122:f9eeca106725	225	{
Kojto	122:f9eeca106725	226	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
Kojto	122:f9eeca106725	227	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	122:f9eeca106725	228
Kojto	122:f9eeca106725	229	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	230	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
Kojto	122:f9eeca106725	231
Kojto	122:f9eeca106725	232	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
Kojto	122:f9eeca106725	233	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	122:f9eeca106725	234	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	122:f9eeca106725	235
Kojto	122:f9eeca106725	236	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	122:f9eeca106725	237	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	122:f9eeca106725	238	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
Kojto	122:f9eeca106725	239	}RCC_PLLI2SInitTypeDef;
Kojto	122:f9eeca106725	240
Kojto	122:f9eeca106725	241	/**
Kojto	122:f9eeca106725	242	* @brief RCC extended clocks structure definition
Kojto	122:f9eeca106725	243	*/
Kojto	122:f9eeca106725	244	typedef struct
Kojto	122:f9eeca106725	245	{
Kojto	122:f9eeca106725	246	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	122:f9eeca106725	247	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	122:f9eeca106725	248
Kojto	122:f9eeca106725	249	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	122:f9eeca106725	250	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
Kojto	122:f9eeca106725	251
Kojto	122:f9eeca106725	252	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
Kojto	122:f9eeca106725	253	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
Kojto	122:f9eeca106725	254
Kojto	122:f9eeca106725	255	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
Kojto	122:f9eeca106725	256	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
Kojto	122:f9eeca106725	257
Kojto	122:f9eeca106725	258	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	122:f9eeca106725	259	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	122:f9eeca106725	260
Kojto	122:f9eeca106725	261	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto	122:f9eeca106725	262	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto	122:f9eeca106725	263
Kojto	122:f9eeca106725	264	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto	122:f9eeca106725	265	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto	122:f9eeca106725	266
Kojto	122:f9eeca106725	267	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto	122:f9eeca106725	268	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
Kojto	122:f9eeca106725	269
Kojto	122:f9eeca106725	270	uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection.
Kojto	122:f9eeca106725	271	This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
Kojto	122:f9eeca106725	272
Kojto	122:f9eeca106725	273	uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
Kojto	122:f9eeca106725	274	This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
Kojto	122:f9eeca106725	275
Kojto	122:f9eeca106725	276	uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection.
Kojto	122:f9eeca106725	277	This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
Kojto	122:f9eeca106725	278
Kojto	122:f9eeca106725	279	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	122:f9eeca106725	280	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	122:f9eeca106725	281	}RCC_PeriphCLKInitTypeDef;
Kojto	122:f9eeca106725	282	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	122:f9eeca106725	283
Kojto	110:165afa46840b	284	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	89:552587b429a1	285	/**
bogdanm	89:552587b429a1	286	* @brief PLLI2S Clock structure definition
bogdanm	89:552587b429a1	287	*/
bogdanm	89:552587b429a1	288	typedef struct
bogdanm	89:552587b429a1	289	{
bogdanm	89:552587b429a1	290	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	291	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
bogdanm	89:552587b429a1	292	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	89:552587b429a1	293
bogdanm	89:552587b429a1	294	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	89:552587b429a1	295	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	89:552587b429a1	296	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	89:552587b429a1	297
bogdanm	89:552587b429a1	298	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	89:552587b429a1	299	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	89:552587b429a1	300	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm	89:552587b429a1	301	}RCC_PLLI2SInitTypeDef;
bogdanm	89:552587b429a1	302
bogdanm	89:552587b429a1	303	/**
bogdanm	89:552587b429a1	304	* @brief PLLSAI Clock structure definition
bogdanm	89:552587b429a1	305	*/
bogdanm	89:552587b429a1	306	typedef struct
bogdanm	89:552587b429a1	307	{
bogdanm	89:552587b429a1	308	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	309	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
bogdanm	89:552587b429a1	310	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto	110:165afa46840b	311	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	312	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
Kojto	110:165afa46840b	313	This parameter is only available in STM32F469xx/STM32F479xx devices.
Kojto	110:165afa46840b	314	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
Kojto	110:165afa46840b	315	#endif /* STM32F469xx \|\| STM32F479xx */
bogdanm	89:552587b429a1	316
bogdanm	89:552587b429a1	317	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm	89:552587b429a1	318	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	89:552587b429a1	319	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
bogdanm	89:552587b429a1	320
bogdanm	89:552587b429a1	321	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
bogdanm	89:552587b429a1	322	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	89:552587b429a1	323	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
bogdanm	89:552587b429a1	324
bogdanm	89:552587b429a1	325	}RCC_PLLSAIInitTypeDef;
Kojto	122:f9eeca106725	326
bogdanm	89:552587b429a1	327	/**
bogdanm	89:552587b429a1	328	* @brief RCC extended clocks structure definition
bogdanm	89:552587b429a1	329	*/
bogdanm	89:552587b429a1	330	typedef struct
bogdanm	89:552587b429a1	331	{
bogdanm	89:552587b429a1	332	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	89:552587b429a1	333	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	89:552587b429a1	334
bogdanm	89:552587b429a1	335	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm	89:552587b429a1	336	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	89:552587b429a1	337
bogdanm	89:552587b429a1	338	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
bogdanm	89:552587b429a1	339	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
bogdanm	89:552587b429a1	340
bogdanm	89:552587b429a1	341	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm	89:552587b429a1	342	This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm	89:552587b429a1	343	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm	89:552587b429a1	344
bogdanm	89:552587b429a1	345	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm	89:552587b429a1	346	This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm	89:552587b429a1	347	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
bogdanm	89:552587b429a1	348
bogdanm	89:552587b429a1	349	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
bogdanm	89:552587b429a1	350	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
bogdanm	89:552587b429a1	351
bogdanm	89:552587b429a1	352	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
bogdanm	89:552587b429a1	353	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	89:552587b429a1	354
bogdanm	89:552587b429a1	355	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
bogdanm	89:552587b429a1	356	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	110:165afa46840b	357	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	358	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto	122:f9eeca106725	359	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
Kojto	110:165afa46840b	360
Kojto	110:165afa46840b	361	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto	110:165afa46840b	362	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto	110:165afa46840b	363	#endif /* STM32F469xx \|\| STM32F479xx */
bogdanm	89:552587b429a1	364	}RCC_PeriphCLKInitTypeDef;
Kojto	122:f9eeca106725	365
Kojto	110:165afa46840b	366	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	367
Kojto	110:165afa46840b	368	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
bogdanm	92:4fc01daae5a5	369	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
bogdanm	89:552587b429a1	370	/**
bogdanm	89:552587b429a1	371	* @brief PLLI2S Clock structure definition
bogdanm	89:552587b429a1	372	*/
bogdanm	89:552587b429a1	373	typedef struct
bogdanm	89:552587b429a1	374	{
Kojto	110:165afa46840b	375	#if defined(STM32F411xE)
bogdanm	92:4fc01daae5a5	376	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
bogdanm	92:4fc01daae5a5	377	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
bogdanm	92:4fc01daae5a5	378	#endif /* STM32F411xE */
bogdanm	92:4fc01daae5a5	379
bogdanm	89:552587b429a1	380	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	381	This parameter must be a number between Min_Data = 50 and Max_Data = 432
Kojto	122:f9eeca106725	382	Except for STM32F411xE devices where the Min_Data = 192.
bogdanm	89:552587b429a1	383	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	89:552587b429a1	384
bogdanm	89:552587b429a1	385	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm	89:552587b429a1	386	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	89:552587b429a1	387	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	89:552587b429a1	388
bogdanm	89:552587b429a1	389	}RCC_PLLI2SInitTypeDef;
bogdanm	89:552587b429a1	390
bogdanm	89:552587b429a1	391	/**
bogdanm	89:552587b429a1	392	* @brief RCC extended clocks structure definition
bogdanm	89:552587b429a1	393	*/
bogdanm	89:552587b429a1	394	typedef struct
bogdanm	89:552587b429a1	395	{
bogdanm	89:552587b429a1	396	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	89:552587b429a1	397	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	89:552587b429a1	398
bogdanm	89:552587b429a1	399	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm	89:552587b429a1	400	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm	89:552587b429a1	401
bogdanm	89:552587b429a1	402	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto	110:165afa46840b	403	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	122:f9eeca106725	404	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	122:f9eeca106725	405	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	122:f9eeca106725	406	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	122:f9eeca106725	407	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
bogdanm	89:552587b429a1	408	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	409	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	99:dbbf35b96557	410	/**
Kojto	99:dbbf35b96557	411	* @}
Kojto	99:dbbf35b96557	412	*/
Kojto	99:dbbf35b96557	413
bogdanm	89:552587b429a1	414	/* Exported constants --------------------------------------------------------*/
Kojto	99:dbbf35b96557	415	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
bogdanm	89:552587b429a1	416	* @{
bogdanm	89:552587b429a1	417	*/
bogdanm	89:552587b429a1	418
Kojto	99:dbbf35b96557	419	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
bogdanm	89:552587b429a1	420	* @{
bogdanm	89:552587b429a1	421	*/
Kojto	122:f9eeca106725	422	/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
Kojto	122:f9eeca106725	423	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	122:f9eeca106725	424	#define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	425	#define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	426	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	427	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	428	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	429	#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00000020U)
Kojto	122:f9eeca106725	430	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000040U)
Kojto	122:f9eeca106725	431	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000080U)
Kojto	122:f9eeca106725	432	#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00000100U)
Kojto	122:f9eeca106725	433	#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x00000200U)
Kojto	122:f9eeca106725	434	#endif /* STM32F412Zx \|\| STM32F412Vx) \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	122:f9eeca106725	435	/----------------------------------------------------------------------------/
Kojto	122:f9eeca106725	436
Kojto	110:165afa46840b	437	/------------------- Peripheral Clock source for STM32F410xx ----------------/
Kojto	110:165afa46840b	438	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	122:f9eeca106725	439	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	440	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	441	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	442	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	443	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000010U)
Kojto	110:165afa46840b	444	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	445	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	446
Kojto	110:165afa46840b	447	/------------------- Peripheral Clock source for STM32F446xx ----------------/
Kojto	99:dbbf35b96557	448	#if defined(STM32F446xx)
Kojto	122:f9eeca106725	449	#define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	450	#define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	451	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	452	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	453	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	454	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
Kojto	122:f9eeca106725	455	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000040U)
Kojto	122:f9eeca106725	456	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000080U)
Kojto	122:f9eeca106725	457	#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00000100U)
Kojto	122:f9eeca106725	458	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000200U)
Kojto	122:f9eeca106725	459	#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400U)
Kojto	122:f9eeca106725	460	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800U)
Kojto	99:dbbf35b96557	461	#endif /* STM32F446xx */
Kojto	110:165afa46840b	462	/-----------------------------------------------------------------------------/
Kojto	110:165afa46840b	463
Kojto	110:165afa46840b	464	/----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------/
Kojto	110:165afa46840b	465	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	466	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	467	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	468	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	469	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	470	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	471	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
Kojto	122:f9eeca106725	472	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040U)
Kojto	122:f9eeca106725	473	#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00000080U)
Kojto	122:f9eeca106725	474	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000100U)
Kojto	110:165afa46840b	475	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	476	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	477
Kojto	110:165afa46840b	478	/-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------/
Kojto	99:dbbf35b96557	479	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	122:f9eeca106725	480	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	481	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	482	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	483	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	484	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	485	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
Kojto	122:f9eeca106725	486	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040U)
bogdanm	89:552587b429a1	487	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	110:165afa46840b	488	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	489
Kojto	110:165afa46840b	490	/-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------/
bogdanm	92:4fc01daae5a5	491	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
bogdanm	92:4fc01daae5a5	492	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	122:f9eeca106725	493	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	494	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	495	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004U)
bogdanm	92:4fc01daae5a5	496	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	122:f9eeca106725	497	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	122:f9eeca106725	498	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	499	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	110:165afa46840b	500	/----------------------------------------------------------------------------/
bogdanm	89:552587b429a1	501	/**
bogdanm	89:552587b429a1	502	* @}
bogdanm	89:552587b429a1	503	*/
Kojto	110:165afa46840b	504	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	505	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	506	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	122:f9eeca106725	507	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
Kojto	122:f9eeca106725	508	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	110:165afa46840b	509	/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
Kojto	110:165afa46840b	510	* @{
Kojto	110:165afa46840b	511	*/
Kojto	122:f9eeca106725	512	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	513	#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001U)
Kojto	110:165afa46840b	514	/**
Kojto	110:165afa46840b	515	* @}
Kojto	110:165afa46840b	516	*/
Kojto	110:165afa46840b	517	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	122:f9eeca106725	518	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
Kojto	122:f9eeca106725	519	STM32F412Rx \|\| STM32F412Cx */
bogdanm	89:552587b429a1	520
Kojto	99:dbbf35b96557	521	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
bogdanm	89:552587b429a1	522	* @{
Kojto	99:dbbf35b96557	523	*/
Kojto	110:165afa46840b	524	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
Kojto	110:165afa46840b	525	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	526	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	527	#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000U)
Kojto	122:f9eeca106725	528	#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000U)
Kojto	122:f9eeca106725	529	#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000U)
Kojto	110:165afa46840b	530	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	89:552587b429a1	531	/**
bogdanm	89:552587b429a1	532	* @}
bogdanm	89:552587b429a1	533	*/
bogdanm	89:552587b429a1	534
Kojto	99:dbbf35b96557	535	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
bogdanm	89:552587b429a1	536	* @{
bogdanm	89:552587b429a1	537	*/
Kojto	122:f9eeca106725	538	#if defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
Kojto	122:f9eeca106725	539	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	122:f9eeca106725	540	#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	541	#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	542	#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006U)
Kojto	122:f9eeca106725	543	#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	544	#endif /* STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
bogdanm	89:552587b429a1	545	/**
bogdanm	89:552587b429a1	546	* @}
bogdanm	89:552587b429a1	547	*/
bogdanm	89:552587b429a1	548
Kojto	99:dbbf35b96557	549	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
bogdanm	89:552587b429a1	550	* @{
Kojto	99:dbbf35b96557	551	*/
Kojto	110:165afa46840b	552	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	553	#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	554	#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	555	#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006U)
Kojto	122:f9eeca106725	556	#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008U)
Kojto	110:165afa46840b	557	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	89:552587b429a1	558	/**
bogdanm	89:552587b429a1	559	* @}
bogdanm	89:552587b429a1	560	*/
bogdanm	89:552587b429a1	561
Kojto	110:165afa46840b	562	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	563	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
bogdanm	89:552587b429a1	564	* @{
bogdanm	89:552587b429a1	565	*/
Kojto	122:f9eeca106725	566	#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	567	#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000U)
Kojto	122:f9eeca106725	568	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000U)
bogdanm	89:552587b429a1	569	/**
bogdanm	89:552587b429a1	570	* @}
bogdanm	89:552587b429a1	571	*/
bogdanm	89:552587b429a1	572
Kojto	99:dbbf35b96557	573	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
bogdanm	89:552587b429a1	574	* @{
bogdanm	89:552587b429a1	575	*/
Kojto	122:f9eeca106725	576	#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	577	#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000U)
Kojto	122:f9eeca106725	578	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000U)
bogdanm	89:552587b429a1	579	/**
bogdanm	89:552587b429a1	580	* @}
bogdanm	89:552587b429a1	581	*/
Kojto	110:165afa46840b	582	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	583
Kojto	110:165afa46840b	584	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	585	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
Kojto	122:f9eeca106725	586	* @{
Kojto	122:f9eeca106725	587	*/
Kojto	122:f9eeca106725	588	#define RCC_CLK48CLKSOURCE_PLLQ ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	589	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
Kojto	110:165afa46840b	590	/**
Kojto	110:165afa46840b	591	* @}
Kojto	110:165afa46840b	592	*/
Kojto	110:165afa46840b	593
Kojto	110:165afa46840b	594	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto	110:165afa46840b	595	* @{
Kojto	110:165afa46840b	596	*/
Kojto	122:f9eeca106725	597	#define RCC_SDIOCLKSOURCE_CLK48 ((uint32_t)0x00000000U)
Kojto	110:165afa46840b	598	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
Kojto	110:165afa46840b	599	/**
Kojto	110:165afa46840b	600	* @}
Kojto	110:165afa46840b	601	*/
Kojto	110:165afa46840b	602
Kojto	110:165afa46840b	603	/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
Kojto	110:165afa46840b	604	* @{
Kojto	110:165afa46840b	605	*/
Kojto	122:f9eeca106725	606	#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U)
Kojto	110:165afa46840b	607	#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
Kojto	110:165afa46840b	608	/**
Kojto	110:165afa46840b	609	* @}
Kojto	110:165afa46840b	610	*/
Kojto	110:165afa46840b	611	#endif /* STM32F469xx \|\| STM32F479xx */
bogdanm	89:552587b429a1	612
Kojto	99:dbbf35b96557	613	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	614	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
Kojto	99:dbbf35b96557	615	* @{
Kojto	99:dbbf35b96557	616	*/
Kojto	122:f9eeca106725	617	#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
Kojto	99:dbbf35b96557	618	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
Kojto	99:dbbf35b96557	619	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
Kojto	99:dbbf35b96557	620	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
Kojto	99:dbbf35b96557	621	/**
Kojto	99:dbbf35b96557	622	* @}
Kojto	99:dbbf35b96557	623	*/
Kojto	99:dbbf35b96557	624
Kojto	99:dbbf35b96557	625	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
Kojto	99:dbbf35b96557	626	* @{
Kojto	99:dbbf35b96557	627	*/
Kojto	122:f9eeca106725	628	#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
Kojto	99:dbbf35b96557	629	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
Kojto	99:dbbf35b96557	630	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
Kojto	99:dbbf35b96557	631	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
Kojto	99:dbbf35b96557	632	/**
Kojto	99:dbbf35b96557	633	* @}
Kojto	99:dbbf35b96557	634	*/
Kojto	99:dbbf35b96557	635
Kojto	99:dbbf35b96557	636	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
Kojto	99:dbbf35b96557	637	* @{
Kojto	99:dbbf35b96557	638	*/
Kojto	122:f9eeca106725	639	#define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
Kojto	99:dbbf35b96557	640	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
Kojto	99:dbbf35b96557	641	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
Kojto	99:dbbf35b96557	642	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
Kojto	99:dbbf35b96557	643	/**
Kojto	99:dbbf35b96557	644	* @}
Kojto	99:dbbf35b96557	645	*/
Kojto	99:dbbf35b96557	646
Kojto	99:dbbf35b96557	647	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
Kojto	99:dbbf35b96557	648	* @{
Kojto	99:dbbf35b96557	649	*/
Kojto	122:f9eeca106725	650	#define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
Kojto	99:dbbf35b96557	651	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
Kojto	99:dbbf35b96557	652	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
Kojto	99:dbbf35b96557	653	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
Kojto	99:dbbf35b96557	654	/**
Kojto	99:dbbf35b96557	655	* @}
Kojto	99:dbbf35b96557	656	*/
Kojto	99:dbbf35b96557	657
Kojto	99:dbbf35b96557	658	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto	99:dbbf35b96557	659	* @{
Kojto	99:dbbf35b96557	660	*/
Kojto	122:f9eeca106725	661	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000U)
Kojto	99:dbbf35b96557	662	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
Kojto	99:dbbf35b96557	663	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto	99:dbbf35b96557	664	/**
Kojto	99:dbbf35b96557	665	* @}
Kojto	99:dbbf35b96557	666	*/
Kojto	99:dbbf35b96557	667
Kojto	99:dbbf35b96557	668	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
Kojto	99:dbbf35b96557	669	* @{
Kojto	99:dbbf35b96557	670	*/
Kojto	122:f9eeca106725	671	#define RCC_CECCLKSOURCE_HSI ((uint32_t)0x00000000U)
Kojto	99:dbbf35b96557	672	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
Kojto	99:dbbf35b96557	673	/**
Kojto	99:dbbf35b96557	674	* @}
Kojto	99:dbbf35b96557	675	*/
Kojto	99:dbbf35b96557	676
Kojto	122:f9eeca106725	677	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
Kojto	122:f9eeca106725	678	* @{
Kojto	122:f9eeca106725	679	*/
Kojto	122:f9eeca106725	680	#define RCC_CLK48CLKSOURCE_PLLQ ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	681	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
Kojto	99:dbbf35b96557	682	/**
Kojto	99:dbbf35b96557	683	* @}
Kojto	99:dbbf35b96557	684	*/
Kojto	99:dbbf35b96557	685
Kojto	99:dbbf35b96557	686	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto	99:dbbf35b96557	687	* @{
Kojto	99:dbbf35b96557	688	*/
Kojto	122:f9eeca106725	689	#define RCC_SDIOCLKSOURCE_CLK48 ((uint32_t)0x00000000U)
Kojto	99:dbbf35b96557	690	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
Kojto	99:dbbf35b96557	691	/**
Kojto	99:dbbf35b96557	692	* @}
Kojto	99:dbbf35b96557	693	*/
Kojto	99:dbbf35b96557	694
Kojto	99:dbbf35b96557	695	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
Kojto	99:dbbf35b96557	696	* @{
Kojto	99:dbbf35b96557	697	*/
Kojto	122:f9eeca106725	698	#define RCC_SPDIFRXCLKSOURCE_PLLR ((uint32_t)0x00000000U)
Kojto	99:dbbf35b96557	699	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
Kojto	99:dbbf35b96557	700	/**
Kojto	99:dbbf35b96557	701	* @}
Kojto	99:dbbf35b96557	702	*/
Kojto	99:dbbf35b96557	703	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	704
Kojto	122:f9eeca106725	705	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	122:f9eeca106725	706	/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
Kojto	122:f9eeca106725	707	* @{
Kojto	122:f9eeca106725	708	*/
Kojto	122:f9eeca106725	709	#define RCC_PLLI2SCLKSOURCE_PLLSRC ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	710	#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
Kojto	122:f9eeca106725	711	/**
Kojto	122:f9eeca106725	712	* @}
Kojto	122:f9eeca106725	713	*/
Kojto	122:f9eeca106725	714
Kojto	122:f9eeca106725	715	/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source
Kojto	122:f9eeca106725	716	* @{
Kojto	122:f9eeca106725	717	*/
Kojto	122:f9eeca106725	718	#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	719	#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
Kojto	122:f9eeca106725	720	/**
Kojto	122:f9eeca106725	721	* @}
Kojto	122:f9eeca106725	722	*/
Kojto	122:f9eeca106725	723
Kojto	122:f9eeca106725	724	/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source
Kojto	122:f9eeca106725	725	* @{
Kojto	122:f9eeca106725	726	*/
Kojto	122:f9eeca106725	727	#define RCC_DFSDM1CLKSOURCE_APB2 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	728	#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
Kojto	122:f9eeca106725	729	/**
Kojto	122:f9eeca106725	730	* @}
Kojto	122:f9eeca106725	731	*/
Kojto	122:f9eeca106725	732
Kojto	122:f9eeca106725	733	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
Kojto	122:f9eeca106725	734	* @{
Kojto	122:f9eeca106725	735	*/
Kojto	122:f9eeca106725	736	#define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	737	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
Kojto	122:f9eeca106725	738	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
Kojto	122:f9eeca106725	739	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
Kojto	122:f9eeca106725	740	/**
Kojto	122:f9eeca106725	741	* @}
Kojto	122:f9eeca106725	742	*/
Kojto	122:f9eeca106725	743
Kojto	122:f9eeca106725	744	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
Kojto	122:f9eeca106725	745	* @{
Kojto	122:f9eeca106725	746	*/
Kojto	122:f9eeca106725	747	#define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	748	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
Kojto	122:f9eeca106725	749	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
Kojto	122:f9eeca106725	750	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
Kojto	122:f9eeca106725	751	/**
Kojto	122:f9eeca106725	752	* @}
Kojto	122:f9eeca106725	753	*/
Kojto	122:f9eeca106725	754
Kojto	122:f9eeca106725	755	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto	122:f9eeca106725	756	* @{
Kojto	122:f9eeca106725	757	*/
Kojto	122:f9eeca106725	758	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	759	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
Kojto	122:f9eeca106725	760	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto	122:f9eeca106725	761	/**
Kojto	122:f9eeca106725	762	* @}
Kojto	122:f9eeca106725	763	*/
Kojto	122:f9eeca106725	764
Kojto	122:f9eeca106725	765	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
Kojto	122:f9eeca106725	766	* @{
Kojto	122:f9eeca106725	767	*/
Kojto	122:f9eeca106725	768	#define RCC_CLK48CLKSOURCE_PLLQ ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	769	#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
Kojto	122:f9eeca106725	770	/**
Kojto	122:f9eeca106725	771	* @}
Kojto	122:f9eeca106725	772	*/
Kojto	122:f9eeca106725	773
Kojto	122:f9eeca106725	774	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto	122:f9eeca106725	775	* @{
Kojto	122:f9eeca106725	776	*/
Kojto	122:f9eeca106725	777	#define RCC_SDIOCLKSOURCE_CLK48 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	778	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
Kojto	122:f9eeca106725	779	/**
Kojto	122:f9eeca106725	780	* @}
Kojto	122:f9eeca106725	781	*/
Kojto	122:f9eeca106725	782	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	122:f9eeca106725	783
Kojto	110:165afa46840b	784	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	785	/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
Kojto	110:165afa46840b	786	* @{
Kojto	110:165afa46840b	787	*/
Kojto	122:f9eeca106725	788	#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000U)
Kojto	110:165afa46840b	789	#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
Kojto	110:165afa46840b	790	#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
Kojto	110:165afa46840b	791	/**
Kojto	110:165afa46840b	792	* @}
Kojto	110:165afa46840b	793	*/
Kojto	110:165afa46840b	794
Kojto	110:165afa46840b	795	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto	110:165afa46840b	796	* @{
Kojto	110:165afa46840b	797	*/
Kojto	122:f9eeca106725	798	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000U)
Kojto	110:165afa46840b	799	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
Kojto	110:165afa46840b	800	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto	110:165afa46840b	801	/**
Kojto	110:165afa46840b	802	* @}
Kojto	110:165afa46840b	803	*/
Kojto	110:165afa46840b	804
Kojto	110:165afa46840b	805	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
Kojto	110:165afa46840b	806	* @{
Kojto	110:165afa46840b	807	*/
Kojto	122:f9eeca106725	808	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
Kojto	110:165afa46840b	809	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
Kojto	110:165afa46840b	810	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
Kojto	110:165afa46840b	811	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
Kojto	110:165afa46840b	812	/**
Kojto	110:165afa46840b	813	* @}
Kojto	110:165afa46840b	814	*/
Kojto	110:165afa46840b	815	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	816
Kojto	110:165afa46840b	817	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	122:f9eeca106725	818	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
Kojto	122:f9eeca106725	819	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
Kojto	122:f9eeca106725	820	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
Kojto	122:f9eeca106725	821	defined(STM32F412Cx)
Kojto	110:165afa46840b	822	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
Kojto	110:165afa46840b	823	* @{
Kojto	110:165afa46840b	824	*/
Kojto	122:f9eeca106725	825	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00U)
Kojto	122:f9eeca106725	826	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01U)
Kojto	110:165afa46840b	827	/**
Kojto	110:165afa46840b	828	* @}
Kojto	110:165afa46840b	829	*/
Kojto	110:165afa46840b	830	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
Kojto	122:f9eeca106725	831	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
Kojto	122:f9eeca106725	832	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	110:165afa46840b	833
Kojto	110:165afa46840b	834	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
Kojto	122:f9eeca106725	835	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
Kojto	122:f9eeca106725	836	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	99:dbbf35b96557	837	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
bogdanm	92:4fc01daae5a5	838	* @{
bogdanm	92:4fc01daae5a5	839	*/
Kojto	122:f9eeca106725	840	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00U)
Kojto	122:f9eeca106725	841	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01U)
Kojto	122:f9eeca106725	842	/**
Kojto	122:f9eeca106725	843	* @}
Kojto	122:f9eeca106725	844	*/
Kojto	122:f9eeca106725	845	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|\
Kojto	122:f9eeca106725	846	STM32F412Rx \|\| STM32F412Cx */
Kojto	122:f9eeca106725	847
Kojto	110:165afa46840b	848	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	849	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	850	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	122:f9eeca106725	851	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
Kojto	122:f9eeca106725	852	defined(STM32F412Rx)
Kojto	110:165afa46840b	853	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
Kojto	110:165afa46840b	854	* @{
Kojto	110:165afa46840b	855	*/
Kojto	122:f9eeca106725	856	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
Kojto	110:165afa46840b	857	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
Kojto	110:165afa46840b	858	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
Kojto	110:165afa46840b	859	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
Kojto	110:165afa46840b	860	/**
Kojto	110:165afa46840b	861	* @}
Kojto	110:165afa46840b	862	*/
Kojto	110:165afa46840b	863	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	122:f9eeca106725	864	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
Kojto	122:f9eeca106725	865	STM32F412Rx */
Kojto	110:165afa46840b	866
Kojto	110:165afa46840b	867	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	868	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
Kojto	110:165afa46840b	869	* @{
Kojto	110:165afa46840b	870	*/
Kojto	122:f9eeca106725	871	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
Kojto	110:165afa46840b	872	#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
Kojto	110:165afa46840b	873	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
Kojto	110:165afa46840b	874	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
Kojto	110:165afa46840b	875	/**
Kojto	110:165afa46840b	876	* @}
Kojto	110:165afa46840b	877	*/
Kojto	110:165afa46840b	878	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	879
bogdanm	89:552587b429a1	880	/**
bogdanm	89:552587b429a1	881	* @}
bogdanm	89:552587b429a1	882	*/
bogdanm	89:552587b429a1	883
bogdanm	89:552587b429a1	884	/* Exported macro ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	885	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto	99:dbbf35b96557	886	* @{
Kojto	99:dbbf35b96557	887	*/
Kojto	110:165afa46840b	888	/------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------/
Kojto	110:165afa46840b	889	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	890	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	891	* @brief Enables or disables the AHB1 peripheral clock.
bogdanm	89:552587b429a1	892	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	89:552587b429a1	893	* is disabled and the application software has to enable this clock before
bogdanm	89:552587b429a1	894	* using it.
Kojto	122:f9eeca106725	895	* @{
bogdanm	89:552587b429a1	896	*/
Kojto	110:165afa46840b	897	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	898	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	899	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	900	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	901	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	902	UNUSED(tmpreg); \
Kojto	110:165afa46840b	903	} while(0)
Kojto	110:165afa46840b	904	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	905	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	906	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	907	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	908	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	909	UNUSED(tmpreg); \
Kojto	110:165afa46840b	910	} while(0)
Kojto	110:165afa46840b	911	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	912	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	913	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	914	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	915	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	916	UNUSED(tmpreg); \
Kojto	110:165afa46840b	917	} while(0)
Kojto	122:f9eeca106725	918	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	919	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	920	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	921	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	922	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	923	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	924	} while(0)
Kojto	122:f9eeca106725	925	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	926	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	927	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	928	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	929	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	930	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	931	} while(0)
Kojto	99:dbbf35b96557	932	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	933	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	934	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	935	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	936	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	937	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	938	} while(0)
Kojto	99:dbbf35b96557	939	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	940	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	941	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	942	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	943	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	944	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	945	} while(0)
Kojto	99:dbbf35b96557	946	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	947	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	948	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	949	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	950	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	951	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	952	} while(0)
Kojto	99:dbbf35b96557	953	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	954	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	955	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	99:dbbf35b96557	956	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	957	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	99:dbbf35b96557	958	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	959	} while(0)
Kojto	99:dbbf35b96557	960	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	961	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	962	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	99:dbbf35b96557	963	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	964	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	99:dbbf35b96557	965	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	966	} while(0)
Kojto	99:dbbf35b96557	967	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	968	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	969	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	99:dbbf35b96557	970	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	971	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	99:dbbf35b96557	972	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	973	} while(0)
Kojto	99:dbbf35b96557	974	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	975	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	976	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	977	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	978	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	979	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	980	} while(0)
Kojto	99:dbbf35b96557	981	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	982	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	983	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	984	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	985	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	986	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	987	} while(0)
Kojto	99:dbbf35b96557	988	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	989	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	990	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	991	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	992	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	993	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	994	} while(0)
Kojto	99:dbbf35b96557	995	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	996	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	997	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	998	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	999	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	1000	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1001	} while(0)
Kojto	99:dbbf35b96557	1002	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1003	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1004	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	1005	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1006	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	1007	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1008	} while(0)
Kojto	99:dbbf35b96557	1009	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1010	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1011	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	1012	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1013	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	1014	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1015	} while(0)
Kojto	110:165afa46840b	1016	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	1017	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	99:dbbf35b96557	1018	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	99:dbbf35b96557	1019	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	99:dbbf35b96557	1020	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	99:dbbf35b96557	1021	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
Kojto	99:dbbf35b96557	1022	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
Kojto	99:dbbf35b96557	1023	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
Kojto	99:dbbf35b96557	1024	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	99:dbbf35b96557	1025	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	99:dbbf35b96557	1026	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	99:dbbf35b96557	1027	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	99:dbbf35b96557	1028	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	99:dbbf35b96557	1029	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	110:165afa46840b	1030	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	1031	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	1032	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
bogdanm	92:4fc01daae5a5	1033
bogdanm	92:4fc01daae5a5	1034	/**
bogdanm	92:4fc01daae5a5	1035	* @brief Enable ETHERNET clock.
bogdanm	92:4fc01daae5a5	1036	*/
Kojto	99:dbbf35b96557	1037	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	1038	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	1039	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	1040	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	1041	} while(0)
bogdanm	92:4fc01daae5a5	1042	/**
bogdanm	92:4fc01daae5a5	1043	* @brief Disable ETHERNET clock.
bogdanm	92:4fc01daae5a5	1044	*/
Kojto	99:dbbf35b96557	1045	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto	99:dbbf35b96557	1046	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	1047	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	1048	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	1049	} while(0)
Kojto	110:165afa46840b	1050	/**
Kojto	110:165afa46840b	1051	* @}
Kojto	110:165afa46840b	1052	*/
Kojto	122:f9eeca106725	1053
Kojto	122:f9eeca106725	1054	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	1055	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	1056	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	1057	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1058	* using it.
Kojto	122:f9eeca106725	1059	* @{
Kojto	122:f9eeca106725	1060	*/
Kojto	122:f9eeca106725	1061	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	1062	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	122:f9eeca106725	1063	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
Kojto	122:f9eeca106725	1064	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
Kojto	122:f9eeca106725	1065	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
Kojto	122:f9eeca106725	1066	#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
Kojto	122:f9eeca106725	1067	#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
Kojto	122:f9eeca106725	1068	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
Kojto	122:f9eeca106725	1069	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
Kojto	122:f9eeca106725	1070	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
Kojto	122:f9eeca106725	1071	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
Kojto	122:f9eeca106725	1072	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
Kojto	122:f9eeca106725	1073	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
Kojto	122:f9eeca106725	1074	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
Kojto	122:f9eeca106725	1075	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Kojto	122:f9eeca106725	1076	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
Kojto	122:f9eeca106725	1077	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	1078	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
Kojto	122:f9eeca106725	1079	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
Kojto	122:f9eeca106725	1080	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
Kojto	122:f9eeca106725	1081
Kojto	122:f9eeca106725	1082	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	1083	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	122:f9eeca106725	1084	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
Kojto	122:f9eeca106725	1085	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
Kojto	122:f9eeca106725	1086	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
Kojto	122:f9eeca106725	1087	#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
Kojto	122:f9eeca106725	1088	#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
Kojto	122:f9eeca106725	1089	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
Kojto	122:f9eeca106725	1090	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
Kojto	122:f9eeca106725	1091	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
Kojto	122:f9eeca106725	1092	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
Kojto	122:f9eeca106725	1093	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
Kojto	122:f9eeca106725	1094	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
Kojto	122:f9eeca106725	1095	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
Kojto	122:f9eeca106725	1096	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
Kojto	122:f9eeca106725	1097	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
Kojto	122:f9eeca106725	1098	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	1099	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
Kojto	122:f9eeca106725	1100	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
Kojto	122:f9eeca106725	1101	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
Kojto	122:f9eeca106725	1102	/**
Kojto	122:f9eeca106725	1103	* @}
Kojto	122:f9eeca106725	1104	*/
Kojto	122:f9eeca106725	1105
Kojto	110:165afa46840b	1106	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1107	* @brief Enable or disable the AHB2 peripheral clock.
bogdanm	92:4fc01daae5a5	1108	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	1109	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	1110	* using it.
Kojto	122:f9eeca106725	1111	* @{
bogdanm	92:4fc01daae5a5	1112	*/
Kojto	110:165afa46840b	1113	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1114	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1115	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	1116	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1117	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	1118	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1119	} while(0)
Kojto	99:dbbf35b96557	1120	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm	92:4fc01daae5a5	1121
Kojto	110:165afa46840b	1122	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1123	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1124	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1125	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	1126	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1127	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	1128	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1129	} while(0)
Kojto	99:dbbf35b96557	1130	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1131	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1132	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	1133	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1134	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	1135	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1136	} while(0)
bogdanm	92:4fc01daae5a5	1137
Kojto	99:dbbf35b96557	1138	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	99:dbbf35b96557	1139	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto	110:165afa46840b	1140	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	1141
Kojto	110:165afa46840b	1142	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	1143	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	110:165afa46840b	1144	}while(0)
Kojto	110:165afa46840b	1145
Kojto	122:f9eeca106725	1146	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	110:165afa46840b	1147
Kojto	110:165afa46840b	1148	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1149	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1150	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	1151	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1152	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	1153	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1154	} while(0)
Kojto	110:165afa46840b	1155	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	110:165afa46840b	1156	/**
Kojto	110:165afa46840b	1157	* @}
Kojto	110:165afa46840b	1158	*/
Kojto	122:f9eeca106725	1159
Kojto	122:f9eeca106725	1160	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	1161	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	1162	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	1163	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1164	* using it.
Kojto	122:f9eeca106725	1165	* @{
Kojto	122:f9eeca106725	1166	*/
Kojto	122:f9eeca106725	1167	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
Kojto	122:f9eeca106725	1168	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
Kojto	122:f9eeca106725	1169
Kojto	122:f9eeca106725	1170	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	1171	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
Kojto	122:f9eeca106725	1172	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
Kojto	122:f9eeca106725	1173
Kojto	122:f9eeca106725	1174	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
Kojto	122:f9eeca106725	1175	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
Kojto	122:f9eeca106725	1176	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	1177
Kojto	122:f9eeca106725	1178	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto	122:f9eeca106725	1179	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	122:f9eeca106725	1180
Kojto	122:f9eeca106725	1181	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
Kojto	122:f9eeca106725	1182	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
Kojto	122:f9eeca106725	1183	/**
Kojto	122:f9eeca106725	1184	* @}
Kojto	122:f9eeca106725	1185	*/
Kojto	110:165afa46840b	1186
Kojto	110:165afa46840b	1187	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1188	* @brief Enables or disables the AHB3 peripheral clock.
bogdanm	92:4fc01daae5a5	1189	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	1190	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1191	* using it.
Kojto	122:f9eeca106725	1192	* @{
bogdanm	92:4fc01daae5a5	1193	*/
Kojto	99:dbbf35b96557	1194	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1195	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1196	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	1197	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1198	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	1199	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1200	} while(0)
Kojto	99:dbbf35b96557	1201	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	110:165afa46840b	1202	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1203	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1204	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1205	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	110:165afa46840b	1206	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1207	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	110:165afa46840b	1208	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1209	} while(0)
Kojto	110:165afa46840b	1210	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto	110:165afa46840b	1211	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1212	/**
Kojto	110:165afa46840b	1213	* @}
Kojto	110:165afa46840b	1214	*/
Kojto	110:165afa46840b	1215
Kojto	122:f9eeca106725	1216
Kojto	122:f9eeca106725	1217	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	1218	* @brief Get the enable or disable status of the AHB3 peripheral clock.
Kojto	122:f9eeca106725	1219	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	1220	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1221	* using it.
Kojto	122:f9eeca106725	1222	* @{
Kojto	122:f9eeca106725	1223	*/
Kojto	122:f9eeca106725	1224	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
Kojto	122:f9eeca106725	1225	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
Kojto	122:f9eeca106725	1226	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	1227	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
Kojto	122:f9eeca106725	1228	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
Kojto	122:f9eeca106725	1229	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	1230	/**
Kojto	122:f9eeca106725	1231	* @}
Kojto	122:f9eeca106725	1232	*/
Kojto	122:f9eeca106725	1233
Kojto	110:165afa46840b	1234	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1235	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	92:4fc01daae5a5	1236	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	1237	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1238	* using it.
Kojto	122:f9eeca106725	1239	* @{
bogdanm	92:4fc01daae5a5	1240	*/
Kojto	99:dbbf35b96557	1241	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1242	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1243	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	1244	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1245	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	1246	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1247	} while(0)
Kojto	99:dbbf35b96557	1248	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1249	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1250	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	1251	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1252	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	1253	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1254	} while(0)
Kojto	99:dbbf35b96557	1255	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1256	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1257	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	1258	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1259	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	1260	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1261	} while(0)
Kojto	99:dbbf35b96557	1262	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1263	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1264	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	1265	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1266	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	1267	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1268	} while(0)
Kojto	99:dbbf35b96557	1269	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1270	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1271	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1272	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1273	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1274	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1275	} while(0)
Kojto	99:dbbf35b96557	1276	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1277	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1278	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1279	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1280	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	1281	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1282	} while(0)
Kojto	99:dbbf35b96557	1283	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1284	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1285	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	1286	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1287	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	1288	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1289	} while(0)
Kojto	99:dbbf35b96557	1290	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1291	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1292	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	1293	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1294	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	1295	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1296	} while(0)
Kojto	99:dbbf35b96557	1297	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1298	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1299	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	1300	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1301	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	1302	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1303	} while(0)
Kojto	99:dbbf35b96557	1304	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1305	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1306	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	1307	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1308	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	1309	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1310	} while(0)
Kojto	99:dbbf35b96557	1311	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1312	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1313	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	1314	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1315	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	1316	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1317	} while(0)
Kojto	99:dbbf35b96557	1318	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1319	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1320	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	1321	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1322	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	1323	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1324	} while(0)
Kojto	99:dbbf35b96557	1325	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1326	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1327	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	99:dbbf35b96557	1328	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1329	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	99:dbbf35b96557	1330	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1331	} while(0)
Kojto	99:dbbf35b96557	1332	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1333	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1334	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	99:dbbf35b96557	1335	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1336	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	99:dbbf35b96557	1337	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1338	} while(0)
Kojto	110:165afa46840b	1339	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1340	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1341	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	1342	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1343	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	1344	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	1345	} while(0)
Kojto	110:165afa46840b	1346	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1347	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1348	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	1349	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1350	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	1351	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	1352	} while(0)
Kojto	110:165afa46840b	1353	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1354	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1355	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	1356	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1357	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	1358	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	1359	} while(0)
Kojto	110:165afa46840b	1360	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1361	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1362	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	1363	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1364	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	1365	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	1366	} while(0)
Kojto	110:165afa46840b	1367	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1368	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1369	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	1370	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1371	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	1372	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	1373	} while(0)
Kojto	110:165afa46840b	1374	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	1375	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	1376	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	1377	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	1378	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	99:dbbf35b96557	1379	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	99:dbbf35b96557	1380	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	99:dbbf35b96557	1381	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	99:dbbf35b96557	1382	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	99:dbbf35b96557	1383	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	99:dbbf35b96557	1384	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	99:dbbf35b96557	1385	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	99:dbbf35b96557	1386	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	99:dbbf35b96557	1387	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	99:dbbf35b96557	1388	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	99:dbbf35b96557	1389	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	99:dbbf35b96557	1390	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
Kojto	99:dbbf35b96557	1391	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
Kojto	110:165afa46840b	1392	/**
Kojto	110:165afa46840b	1393	* @}
Kojto	110:165afa46840b	1394	*/
Kojto	110:165afa46840b	1395
Kojto	122:f9eeca106725	1396	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	1397	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	1398	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	1399	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1400	* using it.
Kojto	122:f9eeca106725	1401	* @{
Kojto	122:f9eeca106725	1402	*/
Kojto	122:f9eeca106725	1403	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	1404	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	122:f9eeca106725	1405	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	122:f9eeca106725	1406	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto	122:f9eeca106725	1407	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	122:f9eeca106725	1408	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	122:f9eeca106725	1409	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto	122:f9eeca106725	1410	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto	122:f9eeca106725	1411	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto	122:f9eeca106725	1412	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto	122:f9eeca106725	1413	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto	122:f9eeca106725	1414	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto	122:f9eeca106725	1415	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto	122:f9eeca106725	1416	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto	122:f9eeca106725	1417	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
Kojto	122:f9eeca106725	1418	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto	122:f9eeca106725	1419	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
Kojto	122:f9eeca106725	1420	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
Kojto	122:f9eeca106725	1421
Kojto	122:f9eeca106725	1422	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	1423	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	122:f9eeca106725	1424	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	122:f9eeca106725	1425	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto	122:f9eeca106725	1426	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	122:f9eeca106725	1427	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	122:f9eeca106725	1428	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto	122:f9eeca106725	1429	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto	122:f9eeca106725	1430	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto	122:f9eeca106725	1431	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto	122:f9eeca106725	1432	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto	122:f9eeca106725	1433	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto	122:f9eeca106725	1434	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto	122:f9eeca106725	1435	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto	122:f9eeca106725	1436	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Kojto	122:f9eeca106725	1437	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto	122:f9eeca106725	1438	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
Kojto	122:f9eeca106725	1439	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
Kojto	122:f9eeca106725	1440	/**
Kojto	122:f9eeca106725	1441	* @}
Kojto	122:f9eeca106725	1442	*/
Kojto	122:f9eeca106725	1443
Kojto	110:165afa46840b	1444	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1445	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	92:4fc01daae5a5	1446	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	1447	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	1448	* using it.
Kojto	122:f9eeca106725	1449	* @{
bogdanm	92:4fc01daae5a5	1450	*/
Kojto	99:dbbf35b96557	1451	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1452	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1453	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	1454	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1455	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	1456	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1457	} while(0)
Kojto	99:dbbf35b96557	1458	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1459	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1460	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	1461	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1462	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	1463	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1464	} while(0)
Kojto	99:dbbf35b96557	1465	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1466	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1467	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	1468	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1469	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	1470	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1471	} while(0)
Kojto	99:dbbf35b96557	1472	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1473	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1474	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	1475	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1476	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	1477	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1478	} while(0)
Kojto	99:dbbf35b96557	1479	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1480	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1481	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	99:dbbf35b96557	1482	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1483	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	99:dbbf35b96557	1484	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1485	} while(0)
Kojto	99:dbbf35b96557	1486	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1487	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1488	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	1489	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1490	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	1491	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1492	} while(0)
Kojto	110:165afa46840b	1493	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1494	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1495	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	1496	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1497	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	1498	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	1499	} while(0)
Kojto	110:165afa46840b	1500	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1501	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1502	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	1503	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1504	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	1505	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	1506	} while(0)
Kojto	110:165afa46840b	1507	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1508	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1509	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	1510	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1511	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	1512	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	1513	} while(0)
Kojto	110:165afa46840b	1514	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	1515	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	1516	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	1517	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	110:165afa46840b	1518	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	110:165afa46840b	1519	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	110:165afa46840b	1520	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	110:165afa46840b	1521	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
Kojto	110:165afa46840b	1522	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	110:165afa46840b	1523
Kojto	110:165afa46840b	1524	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1525	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1526	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1527	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto	110:165afa46840b	1528	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1529	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto	110:165afa46840b	1530	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1531	} while(0)
bogdanm	92:4fc01daae5a5	1532
Kojto	99:dbbf35b96557	1533	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
Kojto	110:165afa46840b	1534	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1535
Kojto	110:165afa46840b	1536	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1537	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1538	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1539	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
Kojto	110:165afa46840b	1540	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1541	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
Kojto	110:165afa46840b	1542	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1543	} while(0)
Kojto	110:165afa46840b	1544
Kojto	110:165afa46840b	1545	#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
Kojto	110:165afa46840b	1546	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1547	/**
Kojto	110:165afa46840b	1548	* @}
Kojto	110:165afa46840b	1549	*/
Kojto	122:f9eeca106725	1550
Kojto	122:f9eeca106725	1551	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	1552	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	1553	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	1554	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	1555	* using it.
Kojto	122:f9eeca106725	1556	* @{
Kojto	122:f9eeca106725	1557	*/
Kojto	122:f9eeca106725	1558	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
Kojto	122:f9eeca106725	1559	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
Kojto	122:f9eeca106725	1560	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
Kojto	122:f9eeca106725	1561	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
Kojto	122:f9eeca106725	1562	#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
Kojto	122:f9eeca106725	1563	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
Kojto	122:f9eeca106725	1564	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
Kojto	122:f9eeca106725	1565	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto	122:f9eeca106725	1566	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
Kojto	122:f9eeca106725	1567
Kojto	122:f9eeca106725	1568	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
Kojto	122:f9eeca106725	1569	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto	122:f9eeca106725	1570	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
Kojto	122:f9eeca106725	1571	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
Kojto	122:f9eeca106725	1572	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
Kojto	122:f9eeca106725	1573	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
Kojto	122:f9eeca106725	1574	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
Kojto	122:f9eeca106725	1575	#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
Kojto	122:f9eeca106725	1576	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
Kojto	122:f9eeca106725	1577
Kojto	122:f9eeca106725	1578	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	1579	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
Kojto	122:f9eeca106725	1580	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
Kojto	122:f9eeca106725	1581	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	1582
Kojto	122:f9eeca106725	1583	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	1584	#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
Kojto	122:f9eeca106725	1585	#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
Kojto	122:f9eeca106725	1586	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	1587	/**
Kojto	122:f9eeca106725	1588	* @}
Kojto	122:f9eeca106725	1589	*/
Kojto	110:165afa46840b	1590
Kojto	110:165afa46840b	1591	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	1592	* @brief Force or release AHB1 peripheral reset.
Kojto	122:f9eeca106725	1593	* @{
Kojto	110:165afa46840b	1594	*/
Kojto	110:165afa46840b	1595	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	1596	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	1597	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	1598	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	1599	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	1600	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	1601	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	99:dbbf35b96557	1602	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
Kojto	99:dbbf35b96557	1603	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
Kojto	99:dbbf35b96557	1604	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
Kojto	110:165afa46840b	1605	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	1606
Kojto	110:165afa46840b	1607	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	1608	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	1609	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	1610	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	1611	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	1612	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	1613	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	99:dbbf35b96557	1614	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
Kojto	99:dbbf35b96557	1615	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
Kojto	99:dbbf35b96557	1616	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
Kojto	110:165afa46840b	1617	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	1618	/**
Kojto	110:165afa46840b	1619	* @}
Kojto	110:165afa46840b	1620	*/
Kojto	110:165afa46840b	1621
Kojto	110:165afa46840b	1622	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	1623	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	1624	* @{
Kojto	110:165afa46840b	1625	*/
Kojto	122:f9eeca106725	1626	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	1627	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	122:f9eeca106725	1628	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	99:dbbf35b96557	1629	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	110:165afa46840b	1630
Kojto	122:f9eeca106725	1631	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto	110:165afa46840b	1632	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	122:f9eeca106725	1633	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	99:dbbf35b96557	1634	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm	92:4fc01daae5a5	1635
Kojto	110:165afa46840b	1636	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1637	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	1638	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
bogdanm	92:4fc01daae5a5	1639
Kojto	99:dbbf35b96557	1640	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	1641	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto	110:165afa46840b	1642	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1643	/**
Kojto	110:165afa46840b	1644	* @}
Kojto	110:165afa46840b	1645	*/
Kojto	110:165afa46840b	1646
Kojto	110:165afa46840b	1647	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	1648	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	1649	* @{
bogdanm	92:4fc01daae5a5	1650	*/
Kojto	122:f9eeca106725	1651	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	1652	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	99:dbbf35b96557	1653	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	99:dbbf35b96557	1654	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	110:165afa46840b	1655
Kojto	122:f9eeca106725	1656	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1657	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	110:165afa46840b	1658	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	110:165afa46840b	1659	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1660	/**
Kojto	110:165afa46840b	1661	* @}
Kojto	110:165afa46840b	1662	*/
Kojto	110:165afa46840b	1663
Kojto	110:165afa46840b	1664	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	1665	* @brief Force or release APB1 peripheral reset.
Kojto	122:f9eeca106725	1666	* @{
bogdanm	92:4fc01daae5a5	1667	*/
Kojto	99:dbbf35b96557	1668	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	1669	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	1670	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	1671	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	1672	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	1673	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	1674	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	1675	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	1676	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	1677	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	1678	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	99:dbbf35b96557	1679	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
Kojto	99:dbbf35b96557	1680	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
Kojto	110:165afa46840b	1681	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	1682	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	1683	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	1684	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	1685	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	1686
Kojto	110:165afa46840b	1687	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	1688	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	1689	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	1690	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	1691	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	99:dbbf35b96557	1692	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	1693	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	1694	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	1695	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	1696	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	1697	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	1698	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	1699	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	1700	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	1701	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	1702	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	99:dbbf35b96557	1703	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
Kojto	99:dbbf35b96557	1704	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
Kojto	110:165afa46840b	1705	/**
Kojto	110:165afa46840b	1706	* @}
Kojto	110:165afa46840b	1707	*/
Kojto	110:165afa46840b	1708
Kojto	110:165afa46840b	1709	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	1710	* @brief Force or release APB2 peripheral reset.
Kojto	122:f9eeca106725	1711	* @{
bogdanm	92:4fc01daae5a5	1712	*/
Kojto	99:dbbf35b96557	1713	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	99:dbbf35b96557	1714	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	99:dbbf35b96557	1715	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
Kojto	99:dbbf35b96557	1716	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	110:165afa46840b	1717	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	1718	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	1719	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	122:f9eeca106725	1720
Kojto	110:165afa46840b	1721	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	1722	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	1723	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	99:dbbf35b96557	1724	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	99:dbbf35b96557	1725	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	99:dbbf35b96557	1726	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
Kojto	99:dbbf35b96557	1727	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
bogdanm	92:4fc01daae5a5	1728
Kojto	110:165afa46840b	1729	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1730	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
Kojto	99:dbbf35b96557	1731	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
Kojto	110:165afa46840b	1732	#endif /* STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1733
Kojto	110:165afa46840b	1734	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1735	#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DSIRST))
Kojto	110:165afa46840b	1736	#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
Kojto	110:165afa46840b	1737	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1738	/**
Kojto	110:165afa46840b	1739	* @}
Kojto	110:165afa46840b	1740	*/
Kojto	110:165afa46840b	1741
Kojto	110:165afa46840b	1742	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1743	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	1744	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	1745	* power consumption.
bogdanm	92:4fc01daae5a5	1746	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	1747	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	1748	* @{
Kojto	110:165afa46840b	1749	*/
Kojto	110:165afa46840b	1750	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	1751	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	1752	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	1753	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	1754	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	1755	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	1756	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	1757	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	1758	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	1759	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	1760	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	1761	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	99:dbbf35b96557	1762	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
Kojto	99:dbbf35b96557	1763	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
Kojto	99:dbbf35b96557	1764	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
Kojto	99:dbbf35b96557	1765	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
Kojto	110:165afa46840b	1766	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	1767	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	1768	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	1769	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	1770
Kojto	110:165afa46840b	1771	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	1772	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	1773	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	1774	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	1775	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	1776	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	1777	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	1778	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	1779	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	1780	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	1781	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	1782	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	99:dbbf35b96557	1783	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
Kojto	99:dbbf35b96557	1784	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
Kojto	99:dbbf35b96557	1785	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
Kojto	110:165afa46840b	1786	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	1787	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	1788	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	1789	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	1790	/**
Kojto	110:165afa46840b	1791	* @}
Kojto	110:165afa46840b	1792	*/
Kojto	122:f9eeca106725	1793
Kojto	110:165afa46840b	1794	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1795	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	1796	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	1797	* power consumption.
Kojto	110:165afa46840b	1798	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	1799	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	1800	* @{
Kojto	110:165afa46840b	1801	*/
Kojto	110:165afa46840b	1802	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	1803	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	1804
Kojto	110:165afa46840b	1805	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	1806	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	1807
Kojto	99:dbbf35b96557	1808	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	1809	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
bogdanm	92:4fc01daae5a5	1810
Kojto	110:165afa46840b	1811	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1812	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	1813	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
bogdanm	92:4fc01daae5a5	1814
Kojto	99:dbbf35b96557	1815	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	1816	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto	110:165afa46840b	1817	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1818	/**
Kojto	110:165afa46840b	1819	* @}
Kojto	110:165afa46840b	1820	*/
Kojto	122:f9eeca106725	1821
Kojto	110:165afa46840b	1822	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1823	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	1824	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	1825	* power consumption.
bogdanm	92:4fc01daae5a5	1826	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	1827	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	1828	* @{
bogdanm	92:4fc01daae5a5	1829	*/
Kojto	99:dbbf35b96557	1830	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	99:dbbf35b96557	1831	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
bogdanm	92:4fc01daae5a5	1832
Kojto	110:165afa46840b	1833	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1834	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	110:165afa46840b	1835	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	110:165afa46840b	1836	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1837	/**
Kojto	110:165afa46840b	1838	* @}
Kojto	110:165afa46840b	1839	*/
Kojto	122:f9eeca106725	1840
Kojto	110:165afa46840b	1841	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1842	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	1843	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	1844	* power consumption.
bogdanm	92:4fc01daae5a5	1845	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	1846	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	1847	* @{
bogdanm	92:4fc01daae5a5	1848	*/
Kojto	99:dbbf35b96557	1849	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	1850	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	1851	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	1852	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	1853	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	1854	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	1855	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	1856	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	1857	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	1858	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	1859	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	99:dbbf35b96557	1860	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
Kojto	99:dbbf35b96557	1861	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
Kojto	110:165afa46840b	1862	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	1863	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	1864	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	1865	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	1866	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	1867
Kojto	110:165afa46840b	1868	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	1869	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	1870	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	1871	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	1872	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	99:dbbf35b96557	1873	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	1874	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	1875	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	1876	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	1877	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	1878	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	1879	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	1880	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	1881	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	1882	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	1883	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	99:dbbf35b96557	1884	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
Kojto	99:dbbf35b96557	1885	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
Kojto	110:165afa46840b	1886	/**
Kojto	110:165afa46840b	1887	* @}
Kojto	110:165afa46840b	1888	*/
Kojto	110:165afa46840b	1889
Kojto	110:165afa46840b	1890	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	1891	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	1892	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	1893	* power consumption.
bogdanm	92:4fc01daae5a5	1894	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	1895	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	1896	* @{
bogdanm	92:4fc01daae5a5	1897	*/
Kojto	99:dbbf35b96557	1898	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	1899	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	1900	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	1901	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	99:dbbf35b96557	1902	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
Kojto	99:dbbf35b96557	1903	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	110:165afa46840b	1904	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	1905	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	1906	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	1907
Kojto	110:165afa46840b	1908	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	1909	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	1910	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	99:dbbf35b96557	1911	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	1912	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	1913	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	1914	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	99:dbbf35b96557	1915	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
Kojto	99:dbbf35b96557	1916	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
bogdanm	92:4fc01daae5a5	1917
Kojto	110:165afa46840b	1918	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1919	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
bogdanm	92:4fc01daae5a5	1920
Kojto	99:dbbf35b96557	1921	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
Kojto	110:165afa46840b	1922	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1923
Kojto	110:165afa46840b	1924	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	1925	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DSILPEN))
Kojto	110:165afa46840b	1926	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
Kojto	110:165afa46840b	1927	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1928	/**
Kojto	110:165afa46840b	1929	* @}
Kojto	110:165afa46840b	1930	*/
Kojto	110:165afa46840b	1931	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	1932	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	1933
Kojto	110:165afa46840b	1934	/----------------------------------- STM32F40xxx/STM32F41xxx-----------------/
bogdanm	92:4fc01daae5a5	1935	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	110:165afa46840b	1936	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	1937	* @brief Enables or disables the AHB1 peripheral clock.
bogdanm	92:4fc01daae5a5	1938	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	1939	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	1940	* using it.
Kojto	122:f9eeca106725	1941	* @{
bogdanm	92:4fc01daae5a5	1942	*/
Kojto	110:165afa46840b	1943	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1944	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1945	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	1946	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1947	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	1948	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1949	} while(0)
Kojto	110:165afa46840b	1950	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1951	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1952	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	1953	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1954	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	1955	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1956	} while(0)
Kojto	110:165afa46840b	1957	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1958	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1959	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	1960	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1961	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	1962	UNUSED(tmpreg); \
Kojto	110:165afa46840b	1963	} while(0)
Kojto	122:f9eeca106725	1964	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1965	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1966	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	1967	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1968	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	1969	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	1970	} while(0)
Kojto	122:f9eeca106725	1971	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1972	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	1973	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	1974	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	1975	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	1976	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	1977	} while(0)
Kojto	99:dbbf35b96557	1978	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1979	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1980	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	1981	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1982	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	99:dbbf35b96557	1983	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1984	} while(0)
Kojto	99:dbbf35b96557	1985	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1986	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1987	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	1988	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1989	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	1990	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1991	} while(0)
Kojto	99:dbbf35b96557	1992	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	1993	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	1994	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	1995	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	1996	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	1997	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	1998	} while(0)
Kojto	99:dbbf35b96557	1999	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2000	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2001	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	2002	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2003	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	2004	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2005	} while(0)
Kojto	99:dbbf35b96557	2006	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2007	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2008	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	2009	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2010	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	2011	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2012	} while(0)
Kojto	110:165afa46840b	2013	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	2014	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	99:dbbf35b96557	2015	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	99:dbbf35b96557	2016	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	99:dbbf35b96557	2017	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	99:dbbf35b96557	2018	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	99:dbbf35b96557	2019	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	110:165afa46840b	2020	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	2021	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	2022	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
bogdanm	92:4fc01daae5a5	2023	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
bogdanm	92:4fc01daae5a5	2024	/**
bogdanm	92:4fc01daae5a5	2025	* @brief Enable ETHERNET clock.
bogdanm	92:4fc01daae5a5	2026	*/
Kojto	99:dbbf35b96557	2027	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2028	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2029	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	2030	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2031	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	99:dbbf35b96557	2032	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2033	} while(0)
Kojto	99:dbbf35b96557	2034	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2035	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2036	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	2037	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2038	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	99:dbbf35b96557	2039	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2040	} while(0)
Kojto	99:dbbf35b96557	2041	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2042	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2043	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	2044	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2045	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	99:dbbf35b96557	2046	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2047	} while(0)
Kojto	99:dbbf35b96557	2048	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2049	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2050	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	2051	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2052	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	99:dbbf35b96557	2053	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2054	} while(0)
Kojto	99:dbbf35b96557	2055	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	2056	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	2057	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	2058	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto	99:dbbf35b96557	2059	} while(0)
bogdanm	89:552587b429a1	2060
bogdanm	89:552587b429a1	2061	/**
bogdanm	89:552587b429a1	2062	* @brief Disable ETHERNET clock.
bogdanm	89:552587b429a1	2063	*/
Kojto	99:dbbf35b96557	2064	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	99:dbbf35b96557	2065	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	99:dbbf35b96557	2066	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	99:dbbf35b96557	2067	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	99:dbbf35b96557	2068	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto	99:dbbf35b96557	2069	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	2070	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto	99:dbbf35b96557	2071	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
bogdanm	89:552587b429a1	2072	} while(0)
bogdanm	92:4fc01daae5a5	2073	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2074	/**
Kojto	110:165afa46840b	2075	* @}
Kojto	110:165afa46840b	2076	*/
Kojto	122:f9eeca106725	2077
Kojto	122:f9eeca106725	2078	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2079	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	2080	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2081	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2082	* using it.
Kojto	122:f9eeca106725	2083	* @{
Kojto	122:f9eeca106725	2084	*/
Kojto	122:f9eeca106725	2085	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Kojto	122:f9eeca106725	2086	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
Kojto	122:f9eeca106725	2087	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	2088	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	2089	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	122:f9eeca106725	2090	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
Kojto	122:f9eeca106725	2091	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
Kojto	122:f9eeca106725	2092	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
Kojto	122:f9eeca106725	2093	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
Kojto	122:f9eeca106725	2094	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
Kojto	122:f9eeca106725	2095
Kojto	122:f9eeca106725	2096	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	2097	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	122:f9eeca106725	2098	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
Kojto	122:f9eeca106725	2099	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
Kojto	122:f9eeca106725	2100	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
Kojto	122:f9eeca106725	2101	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
Kojto	122:f9eeca106725	2102	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
Kojto	122:f9eeca106725	2103	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
Kojto	122:f9eeca106725	2104	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
Kojto	122:f9eeca106725	2105	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	2106	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	122:f9eeca106725	2107	/**
Kojto	122:f9eeca106725	2108	* @brief Enable ETHERNET clock.
Kojto	122:f9eeca106725	2109	*/
Kojto	122:f9eeca106725	2110	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
Kojto	122:f9eeca106725	2111	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
Kojto	122:f9eeca106725	2112	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
Kojto	122:f9eeca106725	2113	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
Kojto	122:f9eeca106725	2114	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
Kojto	122:f9eeca106725	2115	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
Kojto	122:f9eeca106725	2116	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
Kojto	122:f9eeca106725	2117	/**
Kojto	122:f9eeca106725	2118	* @brief Disable ETHERNET clock.
Kojto	122:f9eeca106725	2119	*/
Kojto	122:f9eeca106725	2120	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
Kojto	122:f9eeca106725	2121	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
Kojto	122:f9eeca106725	2122	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
Kojto	122:f9eeca106725	2123	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
Kojto	122:f9eeca106725	2124	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
Kojto	122:f9eeca106725	2125	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
Kojto	122:f9eeca106725	2126	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
Kojto	122:f9eeca106725	2127	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	122:f9eeca106725	2128	/**
Kojto	122:f9eeca106725	2129	* @}
Kojto	122:f9eeca106725	2130	*/
Kojto	122:f9eeca106725	2131
Kojto	110:165afa46840b	2132	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2133	* @brief Enable or disable the AHB2 peripheral clock.
bogdanm	89:552587b429a1	2134	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	89:552587b429a1	2135	* is disabled and the application software has to enable this clock before
bogdanm	89:552587b429a1	2136	* using it.
Kojto	122:f9eeca106725	2137	* @{
bogdanm	89:552587b429a1	2138	*/
Kojto	110:165afa46840b	2139	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	2140	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	110:165afa46840b	2141	}while(0)
Kojto	110:165afa46840b	2142
Kojto	122:f9eeca106725	2143	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	110:165afa46840b	2144
Kojto	110:165afa46840b	2145	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2146	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2147	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	2148	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2149	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	2150	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2151	} while(0)
Kojto	110:165afa46840b	2152	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	110:165afa46840b	2153
bogdanm	92:4fc01daae5a5	2154	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2155	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2156	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2157	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	2158	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2159	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	2160	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2161	} while(0)
Kojto	99:dbbf35b96557	2162	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm	92:4fc01daae5a5	2163	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	89:552587b429a1	2164
bogdanm	92:4fc01daae5a5	2165	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2166	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2167	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2168	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	2169	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2170	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	99:dbbf35b96557	2171	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2172	} while(0)
Kojto	99:dbbf35b96557	2173	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2174	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2175	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	2176	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2177	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	99:dbbf35b96557	2178	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2179	} while(0)
Kojto	99:dbbf35b96557	2180	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	99:dbbf35b96557	2181	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
bogdanm	92:4fc01daae5a5	2182	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2183	/**
Kojto	110:165afa46840b	2184	* @}
Kojto	110:165afa46840b	2185	*/
Kojto	110:165afa46840b	2186
Kojto	122:f9eeca106725	2187
Kojto	122:f9eeca106725	2188	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2189	* @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto	122:f9eeca106725	2190	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2191	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2192	* using it.
Kojto	122:f9eeca106725	2193	* @{
Kojto	122:f9eeca106725	2194	*/
Kojto	122:f9eeca106725	2195	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto	122:f9eeca106725	2196	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	122:f9eeca106725	2197
Kojto	122:f9eeca106725	2198	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
Kojto	122:f9eeca106725	2199	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
Kojto	122:f9eeca106725	2200
Kojto	122:f9eeca106725	2201	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	122:f9eeca106725	2202	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
Kojto	122:f9eeca106725	2203	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
Kojto	122:f9eeca106725	2204	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	122:f9eeca106725	2205
Kojto	122:f9eeca106725	2206	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	122:f9eeca106725	2207	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
Kojto	122:f9eeca106725	2208	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
Kojto	122:f9eeca106725	2209
Kojto	122:f9eeca106725	2210	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
Kojto	122:f9eeca106725	2211	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
Kojto	122:f9eeca106725	2212	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	122:f9eeca106725	2213	/**
Kojto	122:f9eeca106725	2214	* @}
Kojto	122:f9eeca106725	2215	*/
Kojto	122:f9eeca106725	2216
Kojto	110:165afa46840b	2217	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2218	* @brief Enables or disables the AHB3 peripheral clock.
bogdanm	89:552587b429a1	2219	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	89:552587b429a1	2220	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2221	* using it.
Kojto	122:f9eeca106725	2222	* @{
bogdanm	89:552587b429a1	2223	*/
Kojto	99:dbbf35b96557	2224	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2225	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2226	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	99:dbbf35b96557	2227	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2228	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	99:dbbf35b96557	2229	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2230	} while(0)
Kojto	99:dbbf35b96557	2231	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
Kojto	110:165afa46840b	2232	/**
Kojto	110:165afa46840b	2233	* @}
Kojto	110:165afa46840b	2234	*/
Kojto	110:165afa46840b	2235
Kojto	122:f9eeca106725	2236	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2237	* @brief Get the enable or disable status of the AHB3 peripheral clock.
Kojto	122:f9eeca106725	2238	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2239	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2240	* using it.
Kojto	122:f9eeca106725	2241	* @{
Kojto	122:f9eeca106725	2242	*/
Kojto	122:f9eeca106725	2243	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
Kojto	122:f9eeca106725	2244	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
Kojto	122:f9eeca106725	2245	/**
Kojto	122:f9eeca106725	2246	* @}
Kojto	122:f9eeca106725	2247	*/
Kojto	122:f9eeca106725	2248
Kojto	110:165afa46840b	2249	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2250	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	89:552587b429a1	2251	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	89:552587b429a1	2252	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2253	* using it.
Kojto	122:f9eeca106725	2254	* @{
bogdanm	89:552587b429a1	2255	*/
Kojto	99:dbbf35b96557	2256	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2257	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2258	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	2259	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2260	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	2261	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2262	} while(0)
Kojto	99:dbbf35b96557	2263	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2264	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2265	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	2266	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2267	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	2268	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2269	} while(0)
Kojto	99:dbbf35b96557	2270	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2271	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2272	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	2273	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2274	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	2275	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2276	} while(0)
Kojto	99:dbbf35b96557	2277	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2278	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2279	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	2280	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2281	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	2282	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2283	} while(0)
Kojto	99:dbbf35b96557	2284	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2285	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2286	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	2287	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2288	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	2289	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2290	} while(0)
Kojto	99:dbbf35b96557	2291	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2292	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2293	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	2294	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2295	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	2296	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2297	} while(0)
Kojto	99:dbbf35b96557	2298	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2299	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2300	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	2301	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2302	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	2303	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2304	} while(0)
Kojto	99:dbbf35b96557	2305	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2306	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2307	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	2308	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2309	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	2310	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2311	} while(0)
Kojto	99:dbbf35b96557	2312	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2313	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2314	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	2315	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2316	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	2317	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2318	} while(0)
Kojto	99:dbbf35b96557	2319	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2320	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2321	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	2322	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2323	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	2324	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2325	} while(0)
Kojto	99:dbbf35b96557	2326	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2327	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2328	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	2329	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2330	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	2331	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2332	} while(0)
Kojto	110:165afa46840b	2333	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2334	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2335	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	2336	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2337	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	2338	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2339	} while(0)
Kojto	110:165afa46840b	2340	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2341	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2342	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	2343	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2344	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	2345	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2346	} while(0)
Kojto	110:165afa46840b	2347	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2348	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2349	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	2350	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2351	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	2352	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2353	} while(0)
Kojto	110:165afa46840b	2354	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2355	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2356	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	2357	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2358	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	2359	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2360	} while(0)
Kojto	110:165afa46840b	2361	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2362	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2363	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	2364	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2365	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	2366	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2367	} while(0)
Kojto	110:165afa46840b	2368	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	2369	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	2370	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	2371	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	2372	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	99:dbbf35b96557	2373	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	99:dbbf35b96557	2374	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	99:dbbf35b96557	2375	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	99:dbbf35b96557	2376	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	99:dbbf35b96557	2377	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	99:dbbf35b96557	2378	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	99:dbbf35b96557	2379	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	99:dbbf35b96557	2380	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	99:dbbf35b96557	2381	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	99:dbbf35b96557	2382	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	99:dbbf35b96557	2383	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	110:165afa46840b	2384	/**
Kojto	110:165afa46840b	2385	* @}
Kojto	110:165afa46840b	2386	*/
Kojto	122:f9eeca106725	2387
Kojto	122:f9eeca106725	2388	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2389	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	2390	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2391	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2392	* using it.
Kojto	122:f9eeca106725	2393	* @{
Kojto	122:f9eeca106725	2394	*/
Kojto	122:f9eeca106725	2395	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	2396	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	122:f9eeca106725	2397	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	122:f9eeca106725	2398	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto	122:f9eeca106725	2399	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	122:f9eeca106725	2400	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	122:f9eeca106725	2401	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto	122:f9eeca106725	2402	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto	122:f9eeca106725	2403	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto	122:f9eeca106725	2404	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto	122:f9eeca106725	2405	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto	122:f9eeca106725	2406	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto	122:f9eeca106725	2407	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto	122:f9eeca106725	2408	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto	122:f9eeca106725	2409	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
Kojto	122:f9eeca106725	2410	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto	122:f9eeca106725	2411
Kojto	122:f9eeca106725	2412	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	2413	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	122:f9eeca106725	2414	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	122:f9eeca106725	2415	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto	122:f9eeca106725	2416	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	122:f9eeca106725	2417	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	122:f9eeca106725	2418	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto	122:f9eeca106725	2419	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto	122:f9eeca106725	2420	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto	122:f9eeca106725	2421	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto	122:f9eeca106725	2422	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto	122:f9eeca106725	2423	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto	122:f9eeca106725	2424	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto	122:f9eeca106725	2425	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto	122:f9eeca106725	2426	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Kojto	122:f9eeca106725	2427	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto	122:f9eeca106725	2428	/**
Kojto	122:f9eeca106725	2429	* @}
Kojto	122:f9eeca106725	2430	*/
Kojto	122:f9eeca106725	2431
Kojto	110:165afa46840b	2432	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2433	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	89:552587b429a1	2434	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	89:552587b429a1	2435	* is disabled and the application software has to enable this clock before
bogdanm	89:552587b429a1	2436	* using it.
Kojto	122:f9eeca106725	2437	* @{
Kojto	122:f9eeca106725	2438	*/
Kojto	99:dbbf35b96557	2439	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2440	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2441	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	2442	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2443	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	2444	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2445	} while(0)
Kojto	99:dbbf35b96557	2446	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2447	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2448	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	2449	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2450	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	2451	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2452	} while(0)
Kojto	99:dbbf35b96557	2453	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2454	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	2455	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	2456	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	2457	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	2458	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	2459	} while(0)
Kojto	110:165afa46840b	2460	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2461	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2462	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	2463	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2464	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	2465	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2466	} while(0)
Kojto	110:165afa46840b	2467	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2468	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2469	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	2470	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2471	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	2472	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2473	} while(0)
Kojto	110:165afa46840b	2474	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2475	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2476	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	2477	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2478	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	2479	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2480	} while(0)
Kojto	110:165afa46840b	2481
Kojto	110:165afa46840b	2482	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	2483	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	2484	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	2485	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	110:165afa46840b	2486	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	110:165afa46840b	2487	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	110:165afa46840b	2488	/**
Kojto	110:165afa46840b	2489	* @}
Kojto	110:165afa46840b	2490	*/
Kojto	110:165afa46840b	2491
Kojto	122:f9eeca106725	2492	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2493	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	2494	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2495	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2496	* using it.
Kojto	122:f9eeca106725	2497	* @{
Kojto	122:f9eeca106725	2498	*/
Kojto	122:f9eeca106725	2499	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
Kojto	122:f9eeca106725	2500	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto	122:f9eeca106725	2501	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
Kojto	122:f9eeca106725	2502	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
Kojto	122:f9eeca106725	2503	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
Kojto	122:f9eeca106725	2504	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
Kojto	122:f9eeca106725	2505
Kojto	122:f9eeca106725	2506	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
Kojto	122:f9eeca106725	2507	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto	122:f9eeca106725	2508	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto	122:f9eeca106725	2509	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
Kojto	122:f9eeca106725	2510	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
Kojto	122:f9eeca106725	2511	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
Kojto	122:f9eeca106725	2512	/**
Kojto	122:f9eeca106725	2513	* @}
Kojto	122:f9eeca106725	2514	*/
Kojto	122:f9eeca106725	2515
Kojto	110:165afa46840b	2516	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	2517	* @brief Force or release AHB1 peripheral reset.
Kojto	122:f9eeca106725	2518	* @{
Kojto	110:165afa46840b	2519	*/
Kojto	110:165afa46840b	2520	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	2521	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	2522	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	2523	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	2524	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	2525	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	2526	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	110:165afa46840b	2527	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	2528
Kojto	110:165afa46840b	2529	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	2530	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	2531	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	2532	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	2533	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	99:dbbf35b96557	2534	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	99:dbbf35b96557	2535	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	110:165afa46840b	2536	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	2537	/**
Kojto	110:165afa46840b	2538	* @}
Kojto	110:165afa46840b	2539	*/
Kojto	110:165afa46840b	2540
Kojto	110:165afa46840b	2541	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	2542	* @brief Force or release AHB2 peripheral reset.
Kojto	122:f9eeca106725	2543	* @{
Kojto	122:f9eeca106725	2544	*/
Kojto	122:f9eeca106725	2545	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	2546	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto	110:165afa46840b	2547
bogdanm	92:4fc01daae5a5	2548	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2549	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	99:dbbf35b96557	2550	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm	92:4fc01daae5a5	2551	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	89:552587b429a1	2552
bogdanm	92:4fc01daae5a5	2553	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2554	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	2555	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
bogdanm	89:552587b429a1	2556
Kojto	99:dbbf35b96557	2557	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	99:dbbf35b96557	2558	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
bogdanm	92:4fc01daae5a5	2559	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2560
Kojto	110:165afa46840b	2561	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	2562	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	2563
Kojto	110:165afa46840b	2564	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	110:165afa46840b	2565	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	110:165afa46840b	2566	/**
Kojto	110:165afa46840b	2567	* @}
Kojto	110:165afa46840b	2568	*/
Kojto	110:165afa46840b	2569
Kojto	110:165afa46840b	2570	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	2571	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	2572	* @{
Kojto	110:165afa46840b	2573	*/
Kojto	122:f9eeca106725	2574	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	2575	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	110:165afa46840b	2576
Kojto	99:dbbf35b96557	2577	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
Kojto	99:dbbf35b96557	2578	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
Kojto	110:165afa46840b	2579	/**
Kojto	110:165afa46840b	2580	* @}
Kojto	110:165afa46840b	2581	*/
Kojto	110:165afa46840b	2582
Kojto	110:165afa46840b	2583	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	2584	* @brief Force or release APB1 peripheral reset.
Kojto	122:f9eeca106725	2585	* @{
Kojto	122:f9eeca106725	2586	*/
Kojto	99:dbbf35b96557	2587	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	2588	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	2589	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	2590	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	2591	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	2592	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	2593	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	2594	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	2595	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	2596	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	2597	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	2598	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	2599	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	2600	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	2601	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	2602	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	2603
Kojto	110:165afa46840b	2604	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	2605	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	2606	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	2607	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	2608	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	99:dbbf35b96557	2609	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	2610	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	2611	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	2612	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	2613	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	2614	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	2615	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	2616	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	2617	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	2618	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	2619	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	2620	/**
Kojto	110:165afa46840b	2621	* @}
Kojto	110:165afa46840b	2622	*/
Kojto	110:165afa46840b	2623
Kojto	110:165afa46840b	2624	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	2625	* @brief Force or release APB2 peripheral reset.
Kojto	122:f9eeca106725	2626	* @{
bogdanm	89:552587b429a1	2627	*/
Kojto	99:dbbf35b96557	2628	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	110:165afa46840b	2629	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	2630	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	2631	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	2632
Kojto	110:165afa46840b	2633	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	2634	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	2635	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	99:dbbf35b96557	2636	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	110:165afa46840b	2637	/**
Kojto	110:165afa46840b	2638	* @}
Kojto	110:165afa46840b	2639	*/
Kojto	110:165afa46840b	2640
Kojto	110:165afa46840b	2641	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2642	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	89:552587b429a1	2643	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	89:552587b429a1	2644	* power consumption.
bogdanm	89:552587b429a1	2645	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	89:552587b429a1	2646	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	2647	* @{
Kojto	110:165afa46840b	2648	*/
Kojto	110:165afa46840b	2649	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	2650	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	2651	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	2652	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	2653	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	2654	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	2655	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	2656	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	2657	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	2658	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	2659	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	2660	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	110:165afa46840b	2661	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	2662	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	2663	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	2664	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	2665
Kojto	110:165afa46840b	2666	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	2667	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	2668	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	2669	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	2670	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	99:dbbf35b96557	2671	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	2672	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	99:dbbf35b96557	2673	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	99:dbbf35b96557	2674	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	99:dbbf35b96557	2675	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	99:dbbf35b96557	2676	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	2677	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	110:165afa46840b	2678	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	2679	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	2680	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	2681	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	2682	/**
Kojto	110:165afa46840b	2683	* @}
Kojto	110:165afa46840b	2684	*/
Kojto	110:165afa46840b	2685
Kojto	110:165afa46840b	2686	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2687	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	89:552587b429a1	2688	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	89:552587b429a1	2689	* power consumption.
Kojto	110:165afa46840b	2690	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm	89:552587b429a1	2691	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	2692	* @{
Kojto	110:165afa46840b	2693	*/
Kojto	110:165afa46840b	2694	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	2695	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	2696
Kojto	110:165afa46840b	2697	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	2698	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	2699
bogdanm	92:4fc01daae5a5	2700	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2701	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	2702	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
bogdanm	92:4fc01daae5a5	2703	#endif /* STM32F407xx \|\| STM32F417xx */
bogdanm	89:552587b429a1	2704
bogdanm	92:4fc01daae5a5	2705	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	99:dbbf35b96557	2706	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	2707	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
bogdanm	89:552587b429a1	2708
Kojto	99:dbbf35b96557	2709	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	99:dbbf35b96557	2710	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
bogdanm	92:4fc01daae5a5	2711	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2712	/**
Kojto	110:165afa46840b	2713	* @}
Kojto	110:165afa46840b	2714	*/
Kojto	110:165afa46840b	2715
Kojto	110:165afa46840b	2716	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2717	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm	89:552587b429a1	2718	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	89:552587b429a1	2719	* power consumption.
bogdanm	89:552587b429a1	2720	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	89:552587b429a1	2721	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	2722	* @{
bogdanm	89:552587b429a1	2723	*/
Kojto	99:dbbf35b96557	2724	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
Kojto	99:dbbf35b96557	2725	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
Kojto	110:165afa46840b	2726	/**
Kojto	110:165afa46840b	2727	* @}
Kojto	110:165afa46840b	2728	*/
Kojto	110:165afa46840b	2729
Kojto	110:165afa46840b	2730	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2731	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	89:552587b429a1	2732	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	89:552587b429a1	2733	* power consumption.
bogdanm	89:552587b429a1	2734	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	89:552587b429a1	2735	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	2736	* @{
bogdanm	89:552587b429a1	2737	*/
Kojto	99:dbbf35b96557	2738	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	2739	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	2740	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	2741	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	2742	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	2743	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	2744	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	2745	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	2746	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	2747	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	2748	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	2749	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	2750	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	2751	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	2752	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	2753	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	2754
Kojto	110:165afa46840b	2755	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	2756	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	2757	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	2758	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	2759	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	99:dbbf35b96557	2760	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	2761	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	2762	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	2763	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	2764	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	99:dbbf35b96557	2765	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	2766	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	2767	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	2768	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	2769	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	2770	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	2771	/**
Kojto	110:165afa46840b	2772	* @}
Kojto	110:165afa46840b	2773	*/
Kojto	110:165afa46840b	2774
Kojto	110:165afa46840b	2775	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	2776	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	2777	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	2778	* power consumption.
Kojto	99:dbbf35b96557	2779	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	2780	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	2781	* @{
Kojto	122:f9eeca106725	2782	*/
Kojto	99:dbbf35b96557	2783	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	2784	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	2785	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	110:165afa46840b	2786	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	2787	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	2788	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	2789
Kojto	110:165afa46840b	2790	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	2791	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	2792	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	99:dbbf35b96557	2793	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	2794	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	2795	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	110:165afa46840b	2796	/**
Kojto	110:165afa46840b	2797	* @}
Kojto	110:165afa46840b	2798	*/
Kojto	99:dbbf35b96557	2799	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
Kojto	110:165afa46840b	2800	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	2801
Kojto	110:165afa46840b	2802	/------------------------- STM32F401xE/STM32F401xC --------------------------/
Kojto	110:165afa46840b	2803	#if defined(STM32F401xC) \|\| defined(STM32F401xE)
Kojto	110:165afa46840b	2804	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2805	* @brief Enable or disable the AHB1 peripheral clock.
Kojto	110:165afa46840b	2806	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2807	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2808	* using it.
Kojto	110:165afa46840b	2809	* @{
Kojto	110:165afa46840b	2810	*/
Kojto	122:f9eeca106725	2811	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2812	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2813	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	2814	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2815	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	2816	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2817	} while(0)
Kojto	122:f9eeca106725	2818	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2819	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2820	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	2821	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2822	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	2823	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2824	} while(0)
Kojto	122:f9eeca106725	2825	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2826	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2827	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	2828	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2829	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	2830	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2831	} while(0)
Kojto	122:f9eeca106725	2832	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2833	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2834	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	2835	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2836	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	2837	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2838	} while(0)
Kojto	110:165afa46840b	2839	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2840	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2841	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	2842	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2843	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	2844	UNUSED(tmpreg); \
Kojto	110:165afa46840b	2845	} while(0)
Kojto	110:165afa46840b	2846
Kojto	110:165afa46840b	2847	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	2848	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	110:165afa46840b	2849	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	110:165afa46840b	2850	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	2851	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	2852	/**
Kojto	110:165afa46840b	2853	* @}
Kojto	110:165afa46840b	2854	*/
Kojto	110:165afa46840b	2855
Kojto	122:f9eeca106725	2856	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2857	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	2858	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2859	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2860	* using it.
Kojto	122:f9eeca106725	2861	* @{
Kojto	122:f9eeca106725	2862	*/
Kojto	122:f9eeca106725	2863	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	2864	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	122:f9eeca106725	2865	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	2866	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Kojto	122:f9eeca106725	2867	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
Kojto	122:f9eeca106725	2868
Kojto	122:f9eeca106725	2869	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	2870	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	122:f9eeca106725	2871	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	2872	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
Kojto	122:f9eeca106725	2873	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
Kojto	122:f9eeca106725	2874	/**
Kojto	122:f9eeca106725	2875	* @}
Kojto	122:f9eeca106725	2876	*/
Kojto	122:f9eeca106725	2877
Kojto	110:165afa46840b	2878	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2879	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	110:165afa46840b	2880	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2881	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2882	* using it.
Kojto	110:165afa46840b	2883	* @{
Kojto	110:165afa46840b	2884	*/
Kojto	110:165afa46840b	2885	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	2886	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	110:165afa46840b	2887	}while(0)
Kojto	110:165afa46840b	2888
Kojto	122:f9eeca106725	2889	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	122:f9eeca106725	2890	/**
Kojto	122:f9eeca106725	2891	* @}
Kojto	122:f9eeca106725	2892	*/
Kojto	122:f9eeca106725	2893
Kojto	122:f9eeca106725	2894	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2895	* @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto	122:f9eeca106725	2896	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2897	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2898	* using it.
Kojto	122:f9eeca106725	2899	* @{
Kojto	122:f9eeca106725	2900	*/
Kojto	122:f9eeca106725	2901	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto	122:f9eeca106725	2902	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	122:f9eeca106725	2903	/**
Kojto	122:f9eeca106725	2904	* @}
Kojto	122:f9eeca106725	2905	*/
Kojto	122:f9eeca106725	2906
Kojto	110:165afa46840b	2907	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2908	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	110:165afa46840b	2909	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2910	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2911	* using it.
Kojto	110:165afa46840b	2912	* @{
Kojto	110:165afa46840b	2913	*/
Kojto	110:165afa46840b	2914	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2915	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2916	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	2917	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2918	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	2919	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2920	} while(0)
Kojto	110:165afa46840b	2921	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2922	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2923	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	2924	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2925	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	2926	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2927	} while(0)
Kojto	110:165afa46840b	2928	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2929	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2930	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	2931	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2932	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	2933	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2934	} while(0)
Kojto	110:165afa46840b	2935	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2936	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2937	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	2938	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2939	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	2940	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2941	} while(0)
Kojto	110:165afa46840b	2942	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2943	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2944	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	2945	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2946	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	2947	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2948	} while(0)
Kojto	110:165afa46840b	2949	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	2950	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	2951	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	2952	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	2953	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	110:165afa46840b	2954	/**
Kojto	110:165afa46840b	2955	* @}
Kojto	110:165afa46840b	2956	*/
Kojto	110:165afa46840b	2957
Kojto	122:f9eeca106725	2958	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	2959	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	2960	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	2961	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	2962	* using it.
Kojto	122:f9eeca106725	2963	* @{
Kojto	122:f9eeca106725	2964	*/
Kojto	122:f9eeca106725	2965	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	2966	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	122:f9eeca106725	2967	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	122:f9eeca106725	2968	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto	122:f9eeca106725	2969	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	122:f9eeca106725	2970
Kojto	122:f9eeca106725	2971	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	2972	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	122:f9eeca106725	2973	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	122:f9eeca106725	2974	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto	122:f9eeca106725	2975	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	122:f9eeca106725	2976	/**
Kojto	122:f9eeca106725	2977	* @}
Kojto	122:f9eeca106725	2978	*/
Kojto	122:f9eeca106725	2979
Kojto	122:f9eeca106725	2980	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	2981	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	110:165afa46840b	2982	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	2983	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	2984	* using it.
Kojto	110:165afa46840b	2985	* @{
Kojto	110:165afa46840b	2986	*/
Kojto	110:165afa46840b	2987	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2988	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2989	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	2990	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2991	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	2992	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	2993	} while(0)
Kojto	110:165afa46840b	2994	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	2995	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	2996	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	2997	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	2998	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	2999	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3000	} while(0)
Kojto	110:165afa46840b	3001	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3002	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3003	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	3004	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3005	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	3006	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3007	} while(0)
Kojto	110:165afa46840b	3008
Kojto	110:165afa46840b	3009	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	3010	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	3011	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	3012	/**
Kojto	110:165afa46840b	3013	* @}
Kojto	110:165afa46840b	3014	*/
Kojto	122:f9eeca106725	3015
Kojto	122:f9eeca106725	3016	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3017	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	3018	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3019	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3020	* using it.
Kojto	122:f9eeca106725	3021	* @{
Kojto	122:f9eeca106725	3022	*/
Kojto	122:f9eeca106725	3023	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
Kojto	122:f9eeca106725	3024	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto	122:f9eeca106725	3025	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto	122:f9eeca106725	3026	/**
Kojto	122:f9eeca106725	3027	* @}
Kojto	122:f9eeca106725	3028	*/
Kojto	110:165afa46840b	3029	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	3030	* @brief Force or release AHB1 peripheral reset.
Kojto	110:165afa46840b	3031	* @{
Kojto	110:165afa46840b	3032	*/
Kojto	122:f9eeca106725	3033	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	3034	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	3035	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	110:165afa46840b	3036	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3037
Kojto	122:f9eeca106725	3038	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
Kojto	110:165afa46840b	3039	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	3040	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	110:165afa46840b	3041	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3042	/**
Kojto	110:165afa46840b	3043	* @}
Kojto	110:165afa46840b	3044	*/
Kojto	110:165afa46840b	3045
Kojto	110:165afa46840b	3046	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	3047	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	3048	* @{
Kojto	110:165afa46840b	3049	*/
Kojto	122:f9eeca106725	3050	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	3051	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	3052
Kojto	122:f9eeca106725	3053	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto	110:165afa46840b	3054	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	3055	/**
Kojto	110:165afa46840b	3056	* @}
Kojto	110:165afa46840b	3057	*/
Kojto	110:165afa46840b	3058
Kojto	110:165afa46840b	3059	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	3060	* @brief Force or release APB1 peripheral reset.
Kojto	110:165afa46840b	3061	* @{
Kojto	110:165afa46840b	3062	*/
Kojto	122:f9eeca106725	3063	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	3064	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	3065	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	3066	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	3067	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	3068	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	3069
Kojto	122:f9eeca106725	3070	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
Kojto	110:165afa46840b	3071	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	3072	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	3073	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	3074	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	3075	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	3076	/**
Kojto	110:165afa46840b	3077	* @}
Kojto	110:165afa46840b	3078	*/
Kojto	110:165afa46840b	3079
Kojto	110:165afa46840b	3080	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	3081	* @brief Force or release APB2 peripheral reset.
Kojto	110:165afa46840b	3082	* @{
Kojto	110:165afa46840b	3083	*/
Kojto	122:f9eeca106725	3084	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	3085	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	3086	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	3087	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	3088
Kojto	122:f9eeca106725	3089	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
Kojto	110:165afa46840b	3090	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	3091	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	3092	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	3093	/**
Kojto	110:165afa46840b	3094	* @}
Kojto	110:165afa46840b	3095	*/
Kojto	110:165afa46840b	3096
Kojto	110:165afa46840b	3097	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	3098	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	3099	* @{
Kojto	110:165afa46840b	3100	*/
Kojto	122:f9eeca106725	3101	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	3102	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	110:165afa46840b	3103	/**
Kojto	110:165afa46840b	3104	* @}
Kojto	110:165afa46840b	3105	*/
Kojto	110:165afa46840b	3106
Kojto	110:165afa46840b	3107	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3108	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3109	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3110	* power consumption.
Kojto	110:165afa46840b	3111	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3112	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3113	* @{
Kojto	110:165afa46840b	3114	*/
Kojto	110:165afa46840b	3115	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	3116	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	110:165afa46840b	3117	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3118	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3119	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3120	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	3121
Kojto	110:165afa46840b	3122	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	3123	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	110:165afa46840b	3124	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3125	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3126	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3127	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	3128	/**
Kojto	110:165afa46840b	3129	* @}
Kojto	110:165afa46840b	3130	*/
Kojto	110:165afa46840b	3131
Kojto	110:165afa46840b	3132	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3133	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3134	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3135	* power consumption.
Kojto	110:165afa46840b	3136	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3137	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3138	* @{
Kojto	110:165afa46840b	3139	*/
Kojto	110:165afa46840b	3140	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	3141
Kojto	110:165afa46840b	3142	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	3143	/**
Kojto	110:165afa46840b	3144	* @}
Kojto	110:165afa46840b	3145	*/
Kojto	110:165afa46840b	3146
Kojto	110:165afa46840b	3147	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3148	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3149	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3150	* power consumption.
Kojto	110:165afa46840b	3151	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3152	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3153	* @{
Kojto	110:165afa46840b	3154	*/
Kojto	110:165afa46840b	3155	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	3156	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	3157	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	3158	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	3159	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	3160
Kojto	110:165afa46840b	3161	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	3162	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	3163	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	3164	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	3165	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	3166	/**
Kojto	110:165afa46840b	3167	* @}
Kojto	110:165afa46840b	3168	*/
Kojto	110:165afa46840b	3169
Kojto	110:165afa46840b	3170	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3171	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3172	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3173	* power consumption.
Kojto	110:165afa46840b	3174	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3175	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3176	* @{
Kojto	110:165afa46840b	3177	*/
Kojto	110:165afa46840b	3178	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	3179	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	3180	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	3181
Kojto	110:165afa46840b	3182	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	3183	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	3184	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	3185	/**
Kojto	110:165afa46840b	3186	* @}
Kojto	110:165afa46840b	3187	*/
Kojto	110:165afa46840b	3188	#endif /* STM32F401xC \|\| STM32F401xE*/
Kojto	110:165afa46840b	3189	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	3190
Kojto	110:165afa46840b	3191	/-------------------------------- STM32F410xx -------------------------------/
Kojto	110:165afa46840b	3192	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	3193	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3194	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	110:165afa46840b	3195	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	3196	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	3197	* using it.
Kojto	122:f9eeca106725	3198	* @{
Kojto	110:165afa46840b	3199	*/
Kojto	110:165afa46840b	3200	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3201	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3202	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3203	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3204	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3205	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3206	} while(0)
Kojto	110:165afa46840b	3207	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3208	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3209	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
Kojto	110:165afa46840b	3210	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3211	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
Kojto	110:165afa46840b	3212	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3213	} while(0)
Kojto	110:165afa46840b	3214	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	110:165afa46840b	3215	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
Kojto	110:165afa46840b	3216	/**
Kojto	110:165afa46840b	3217	* @}
Kojto	110:165afa46840b	3218	*/
Kojto	110:165afa46840b	3219
Kojto	122:f9eeca106725	3220	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3221	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	3222	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3223	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3224	* using it.
Kojto	122:f9eeca106725	3225	* @{
Kojto	122:f9eeca106725	3226	*/
Kojto	122:f9eeca106725	3227	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	3228	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
Kojto	122:f9eeca106725	3229	/**
Kojto	122:f9eeca106725	3230	* @}
Kojto	122:f9eeca106725	3231	*/
Kojto	122:f9eeca106725	3232
Kojto	110:165afa46840b	3233	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3234	* @brief Enable or disable the High Speed APB (APB1) peripheral clock.
Kojto	122:f9eeca106725	3235	* @{
Kojto	110:165afa46840b	3236	*/
Kojto	110:165afa46840b	3237	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3238	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3239	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	110:165afa46840b	3240	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3241	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	110:165afa46840b	3242	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3243	} while(0)
Kojto	110:165afa46840b	3244	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3245	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3246	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto	110:165afa46840b	3247	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3248	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto	110:165afa46840b	3249	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3250	} while(0)
Kojto	110:165afa46840b	3251	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3252	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3253	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
Kojto	110:165afa46840b	3254	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3255	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
Kojto	110:165afa46840b	3256	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3257	} while(0)
Kojto	110:165afa46840b	3258	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3259	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3260	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	110:165afa46840b	3261	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3262	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	110:165afa46840b	3263	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3264	} while(0)
Kojto	110:165afa46840b	3265	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3266	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3267	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	110:165afa46840b	3268	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3269	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	110:165afa46840b	3270	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3271	} while(0)
Kojto	110:165afa46840b	3272
Kojto	110:165afa46840b	3273	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	110:165afa46840b	3274	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
Kojto	110:165afa46840b	3275	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
Kojto	110:165afa46840b	3276	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto	110:165afa46840b	3277	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	110:165afa46840b	3278	/**
Kojto	110:165afa46840b	3279	* @}
Kojto	110:165afa46840b	3280	*/
Kojto	122:f9eeca106725	3281
Kojto	122:f9eeca106725	3282	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3283	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	3284	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3285	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3286	* using it.
Kojto	122:f9eeca106725	3287	* @{
Kojto	122:f9eeca106725	3288	*/
Kojto	122:f9eeca106725	3289	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	122:f9eeca106725	3290	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
Kojto	122:f9eeca106725	3291	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
Kojto	122:f9eeca106725	3292	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
Kojto	122:f9eeca106725	3293	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto	122:f9eeca106725	3294
Kojto	122:f9eeca106725	3295	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	122:f9eeca106725	3296	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
Kojto	122:f9eeca106725	3297	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
Kojto	122:f9eeca106725	3298	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
Kojto	122:f9eeca106725	3299	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto	122:f9eeca106725	3300	/**
Kojto	122:f9eeca106725	3301	* @}
Kojto	122:f9eeca106725	3302	*/
Kojto	122:f9eeca106725	3303
Kojto	110:165afa46840b	3304	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3305	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	122:f9eeca106725	3306	* @{
Kojto	122:f9eeca106725	3307	*/
Kojto	99:dbbf35b96557	3308	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3309	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	3310	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	3311	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3312	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	99:dbbf35b96557	3313	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3314	} while(0)
Kojto	110:165afa46840b	3315	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3316	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3317	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
Kojto	110:165afa46840b	3318	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3319	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
Kojto	110:165afa46840b	3320	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3321	} while(0)
Kojto	110:165afa46840b	3322	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	110:165afa46840b	3323	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
Kojto	110:165afa46840b	3324	/**
Kojto	110:165afa46840b	3325	* @}
Kojto	110:165afa46840b	3326	*/
Kojto	122:f9eeca106725	3327
Kojto	122:f9eeca106725	3328	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3329	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	3330	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3331	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3332	* using it.
Kojto	122:f9eeca106725	3333	* @{
Kojto	122:f9eeca106725	3334	*/
Kojto	122:f9eeca106725	3335	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
Kojto	122:f9eeca106725	3336	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
Kojto	122:f9eeca106725	3337
Kojto	122:f9eeca106725	3338	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
Kojto	122:f9eeca106725	3339	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
Kojto	122:f9eeca106725	3340	/**
Kojto	122:f9eeca106725	3341	* @}
Kojto	122:f9eeca106725	3342	*/
Kojto	122:f9eeca106725	3343
Kojto	110:165afa46840b	3344	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	3345	* @brief Force or release AHB1 peripheral reset.
Kojto	122:f9eeca106725	3346	* @{
Kojto	122:f9eeca106725	3347	*/
Kojto	110:165afa46840b	3348	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3349	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_RNGRST))
Kojto	110:165afa46840b	3350	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3351	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
Kojto	110:165afa46840b	3352	/**
Kojto	110:165afa46840b	3353	* @}
Kojto	110:165afa46840b	3354	*/
Kojto	110:165afa46840b	3355
Kojto	110:165afa46840b	3356	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	3357	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	3358	* @{
Kojto	110:165afa46840b	3359	*/
Kojto	110:165afa46840b	3360	#define __HAL_RCC_AHB2_FORCE_RESET()
Kojto	110:165afa46840b	3361	#define __HAL_RCC_AHB2_RELEASE_RESET()
Kojto	110:165afa46840b	3362	/**
Kojto	110:165afa46840b	3363	* @}
Kojto	110:165afa46840b	3364	*/
Kojto	110:165afa46840b	3365
Kojto	110:165afa46840b	3366	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	3367	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	3368	* @{
Kojto	99:dbbf35b96557	3369	*/
Kojto	110:165afa46840b	3370	#define __HAL_RCC_AHB3_FORCE_RESET()
Kojto	110:165afa46840b	3371	#define __HAL_RCC_AHB3_RELEASE_RESET()
Kojto	110:165afa46840b	3372	/**
Kojto	110:165afa46840b	3373	* @}
Kojto	110:165afa46840b	3374	*/
Kojto	110:165afa46840b	3375
Kojto	110:165afa46840b	3376	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	3377	* @brief Force or release APB1 peripheral reset.
Kojto	122:f9eeca106725	3378	* @{
Kojto	110:165afa46840b	3379	*/
Kojto	110:165afa46840b	3380	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	110:165afa46840b	3381	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
Kojto	110:165afa46840b	3382	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
Kojto	110:165afa46840b	3383	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	3384
Kojto	110:165afa46840b	3385	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	110:165afa46840b	3386	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
Kojto	110:165afa46840b	3387	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
Kojto	110:165afa46840b	3388	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	3389	/**
Kojto	110:165afa46840b	3390	* @}
Kojto	110:165afa46840b	3391	*/
Kojto	110:165afa46840b	3392
Kojto	110:165afa46840b	3393	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	3394	* @brief Force or release APB2 peripheral reset.
Kojto	122:f9eeca106725	3395	* @{
Kojto	110:165afa46840b	3396	*/
Kojto	110:165afa46840b	3397	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	110:165afa46840b	3398	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	110:165afa46840b	3399	/**
Kojto	110:165afa46840b	3400	* @}
Kojto	110:165afa46840b	3401	*/
Kojto	110:165afa46840b	3402
Kojto	110:165afa46840b	3403	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3404	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3405	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3406	* power consumption.
Kojto	110:165afa46840b	3407	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3408	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	3409	* @{
Kojto	110:165afa46840b	3410	*/
Kojto	110:165afa46840b	3411	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_RNGLPEN))
Kojto	110:165afa46840b	3412	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3413	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3414	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3415
Kojto	110:165afa46840b	3416	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
Kojto	110:165afa46840b	3417	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3418	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3419	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3420	/**
Kojto	110:165afa46840b	3421	* @}
Kojto	110:165afa46840b	3422	*/
Kojto	110:165afa46840b	3423
Kojto	110:165afa46840b	3424	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3425	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	3426	* @{
Kojto	122:f9eeca106725	3427	*/
Kojto	110:165afa46840b	3428	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	110:165afa46840b	3429	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
Kojto	110:165afa46840b	3430	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
Kojto	110:165afa46840b	3431	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	110:165afa46840b	3432	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	3433
Kojto	110:165afa46840b	3434	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	110:165afa46840b	3435	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
Kojto	110:165afa46840b	3436	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
Kojto	110:165afa46840b	3437	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	110:165afa46840b	3438	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	3439	/**
Kojto	110:165afa46840b	3440	* @}
Kojto	110:165afa46840b	3441	*/
Kojto	110:165afa46840b	3442
Kojto	110:165afa46840b	3443	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3444	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	3445	* @{
Kojto	122:f9eeca106725	3446	*/
Kojto	110:165afa46840b	3447	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	110:165afa46840b	3448	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
Kojto	110:165afa46840b	3449	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	110:165afa46840b	3450	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
Kojto	110:165afa46840b	3451	/**
Kojto	110:165afa46840b	3452	* @}
Kojto	110:165afa46840b	3453	*/
Kojto	110:165afa46840b	3454
Kojto	110:165afa46840b	3455	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	3456	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	3457
Kojto	110:165afa46840b	3458	/-------------------------------- STM32F411xx -------------------------------/
Kojto	110:165afa46840b	3459	#if defined(STM32F411xE)
Kojto	110:165afa46840b	3460	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3461	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	110:165afa46840b	3462	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	3463	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	3464	* using it.
Kojto	122:f9eeca106725	3465	* @{
Kojto	110:165afa46840b	3466	*/
Kojto	110:165afa46840b	3467	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3468	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3469	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	3470	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3471	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	3472	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3473	} while(0)
Kojto	110:165afa46840b	3474	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3475	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3476	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	3477	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3478	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	3479	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3480	} while(0)
Kojto	122:f9eeca106725	3481	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3482	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3483	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	3484	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3485	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	3486	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3487	} while(0)
Kojto	122:f9eeca106725	3488	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3489	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3490	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	3491	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3492	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	3493	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3494	} while(0)
Kojto	110:165afa46840b	3495	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3496	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3497	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3498	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3499	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3500	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3501	} while(0)
Kojto	110:165afa46840b	3502	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	3503	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	110:165afa46840b	3504	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	3505	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	3506	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	110:165afa46840b	3507	/**
Kojto	110:165afa46840b	3508	* @}
Kojto	110:165afa46840b	3509	*/
Kojto	110:165afa46840b	3510
Kojto	122:f9eeca106725	3511	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3512	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	3513	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3514	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3515	* using it.
Kojto	122:f9eeca106725	3516	* @{
Kojto	122:f9eeca106725	3517	*/
Kojto	122:f9eeca106725	3518	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	3519	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	122:f9eeca106725	3520	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Kojto	122:f9eeca106725	3521	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
Kojto	122:f9eeca106725	3522	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	3523
Kojto	122:f9eeca106725	3524	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	3525	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	122:f9eeca106725	3526	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
Kojto	122:f9eeca106725	3527	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
Kojto	122:f9eeca106725	3528	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	3529	/**
Kojto	122:f9eeca106725	3530	* @}
Kojto	122:f9eeca106725	3531	*/
Kojto	122:f9eeca106725	3532
Kojto	110:165afa46840b	3533	/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3534	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	99:dbbf35b96557	3535	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	3536	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	3537	* using it.
Kojto	110:165afa46840b	3538	* @{
Kojto	110:165afa46840b	3539	*/
Kojto	110:165afa46840b	3540	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	3541	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	110:165afa46840b	3542	}while(0)
Kojto	122:f9eeca106725	3543
Kojto	122:f9eeca106725	3544	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	122:f9eeca106725	3545	/**
Kojto	122:f9eeca106725	3546	* @}
Kojto	122:f9eeca106725	3547	*/
Kojto	122:f9eeca106725	3548
Kojto	122:f9eeca106725	3549	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3550	* @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto	122:f9eeca106725	3551	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3552	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3553	* using it.
Kojto	122:f9eeca106725	3554	* @{
Kojto	122:f9eeca106725	3555	*/
Kojto	122:f9eeca106725	3556	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto	122:f9eeca106725	3557	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	122:f9eeca106725	3558	/**
Kojto	122:f9eeca106725	3559	* @}
Kojto	122:f9eeca106725	3560	*/
Kojto	110:165afa46840b	3561
Kojto	110:165afa46840b	3562	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3563	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	110:165afa46840b	3564	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	3565	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	3566	* using it.
Kojto	122:f9eeca106725	3567	* @{
Kojto	110:165afa46840b	3568	*/
Kojto	110:165afa46840b	3569	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3570	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3571	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	3572	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3573	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	3574	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3575	} while(0)
Kojto	110:165afa46840b	3576	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3577	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3578	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	3579	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3580	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	3581	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3582	} while(0)
Kojto	110:165afa46840b	3583	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3584	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3585	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	3586	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3587	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	3588	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3589	} while(0)
Kojto	110:165afa46840b	3590	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3591	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3592	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	3593	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3594	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	3595	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3596	} while(0)
Kojto	110:165afa46840b	3597	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3598	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3599	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	3600	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3601	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	3602	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3603	} while(0)
Kojto	110:165afa46840b	3604	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	3605	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	3606	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	3607	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	3608	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	110:165afa46840b	3609	/**
Kojto	110:165afa46840b	3610	* @}
Kojto	110:165afa46840b	3611	*/
Kojto	122:f9eeca106725	3612
Kojto	122:f9eeca106725	3613	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3614	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	3615	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3616	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3617	* using it.
Kojto	122:f9eeca106725	3618	* @{
Kojto	122:f9eeca106725	3619	*/
Kojto	122:f9eeca106725	3620	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	3621	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	122:f9eeca106725	3622	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	122:f9eeca106725	3623	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto	122:f9eeca106725	3624	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	122:f9eeca106725	3625
Kojto	122:f9eeca106725	3626	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	3627	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	122:f9eeca106725	3628	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	122:f9eeca106725	3629	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto	122:f9eeca106725	3630	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	122:f9eeca106725	3631	/**
Kojto	122:f9eeca106725	3632	* @}
Kojto	122:f9eeca106725	3633	*/
Kojto	122:f9eeca106725	3634
Kojto	110:165afa46840b	3635	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3636	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	122:f9eeca106725	3637	* @{
Kojto	110:165afa46840b	3638	*/
Kojto	110:165afa46840b	3639	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3640	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3641	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	110:165afa46840b	3642	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3643	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	110:165afa46840b	3644	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3645	} while(0)
Kojto	110:165afa46840b	3646	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3647	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3648	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	3649	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3650	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	3651	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3652	} while(0)
Kojto	110:165afa46840b	3653	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3654	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3655	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	3656	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3657	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	3658	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3659	} while(0)
Kojto	110:165afa46840b	3660	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3661	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3662	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	3663	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3664	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	3665	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3666	} while(0)
Kojto	110:165afa46840b	3667	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	3668	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	3669	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	3670	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	110:165afa46840b	3671	/**
Kojto	110:165afa46840b	3672	* @}
Kojto	110:165afa46840b	3673	*/
Kojto	122:f9eeca106725	3674
Kojto	122:f9eeca106725	3675	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3676	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	3677	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3678	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3679	* using it.
Kojto	122:f9eeca106725	3680	* @{
Kojto	122:f9eeca106725	3681	*/
Kojto	122:f9eeca106725	3682	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
Kojto	122:f9eeca106725	3683	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto	122:f9eeca106725	3684	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
Kojto	122:f9eeca106725	3685	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
Kojto	122:f9eeca106725	3686
Kojto	122:f9eeca106725	3687	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
Kojto	122:f9eeca106725	3688	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto	122:f9eeca106725	3689	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto	122:f9eeca106725	3690	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
Kojto	122:f9eeca106725	3691	/**
Kojto	122:f9eeca106725	3692	* @}
Kojto	122:f9eeca106725	3693	*/
Kojto	122:f9eeca106725	3694
Kojto	110:165afa46840b	3695	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	3696	* @brief Force or release AHB1 peripheral reset.
Kojto	122:f9eeca106725	3697	* @{
Kojto	122:f9eeca106725	3698	*/
Kojto	110:165afa46840b	3699	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	3700	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	110:165afa46840b	3701	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3702
Kojto	110:165afa46840b	3703	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	3704	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	110:165afa46840b	3705	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	3706	/**
Kojto	110:165afa46840b	3707	* @}
Kojto	110:165afa46840b	3708	*/
Kojto	110:165afa46840b	3709
Kojto	110:165afa46840b	3710	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	3711	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	3712	* @{
Kojto	110:165afa46840b	3713	*/
Kojto	122:f9eeca106725	3714	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	3715	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	3716
Kojto	122:f9eeca106725	3717	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto	110:165afa46840b	3718	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	3719	/**
Kojto	110:165afa46840b	3720	* @}
Kojto	110:165afa46840b	3721	*/
Kojto	110:165afa46840b	3722
Kojto	110:165afa46840b	3723	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	3724	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	3725	* @{
Kojto	110:165afa46840b	3726	*/
Kojto	122:f9eeca106725	3727	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	3728	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	110:165afa46840b	3729	/**
Kojto	110:165afa46840b	3730	* @}
Kojto	110:165afa46840b	3731	*/
Kojto	110:165afa46840b	3732
Kojto	110:165afa46840b	3733	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	3734	* @brief Force or release APB1 peripheral reset.
Kojto	122:f9eeca106725	3735	* @{
Kojto	110:165afa46840b	3736	*/
Kojto	110:165afa46840b	3737	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	3738	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	3739	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	3740	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	3741	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	3742
Kojto	110:165afa46840b	3743	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	3744	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	3745	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	3746	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	3747	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	3748	/**
Kojto	110:165afa46840b	3749	* @}
Kojto	110:165afa46840b	3750	*/
Kojto	110:165afa46840b	3751
Kojto	110:165afa46840b	3752	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	3753	* @brief Force or release APB2 peripheral reset.
Kojto	122:f9eeca106725	3754	* @{
Kojto	110:165afa46840b	3755	*/
Kojto	110:165afa46840b	3756	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	110:165afa46840b	3757	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	3758	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	3759	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	3760
Kojto	110:165afa46840b	3761	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	3762	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	3763	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	3764	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	110:165afa46840b	3765	/**
Kojto	110:165afa46840b	3766	* @}
Kojto	110:165afa46840b	3767	*/
Kojto	110:165afa46840b	3768
Kojto	110:165afa46840b	3769	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3770	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3771	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3772	* power consumption.
Kojto	110:165afa46840b	3773	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3774	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	3775	* @{
Kojto	110:165afa46840b	3776	*/
Kojto	110:165afa46840b	3777	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	3778	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	110:165afa46840b	3779	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3780	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3781	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3782
Kojto	110:165afa46840b	3783	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	3784	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	110:165afa46840b	3785	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	3786	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	3787	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	3788	/**
Kojto	110:165afa46840b	3789	* @}
Kojto	110:165afa46840b	3790	*/
Kojto	110:165afa46840b	3791
Kojto	110:165afa46840b	3792	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3793	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	110:165afa46840b	3794	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	110:165afa46840b	3795	* power consumption.
Kojto	110:165afa46840b	3796	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	110:165afa46840b	3797	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	3798	* @{
Kojto	110:165afa46840b	3799	*/
Kojto	110:165afa46840b	3800	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	3801	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	3802	/**
Kojto	110:165afa46840b	3803	* @}
Kojto	110:165afa46840b	3804	*/
Kojto	110:165afa46840b	3805
Kojto	110:165afa46840b	3806	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3807	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	3808	* @{
Kojto	122:f9eeca106725	3809	*/
Kojto	110:165afa46840b	3810	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	3811	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	3812	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	3813	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	3814	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	3815
Kojto	110:165afa46840b	3816	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	3817	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	3818	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	3819	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	3820	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	3821	/**
Kojto	110:165afa46840b	3822	* @}
Kojto	110:165afa46840b	3823	*/
Kojto	110:165afa46840b	3824
Kojto	110:165afa46840b	3825	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	3826	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	3827	* @{
Kojto	122:f9eeca106725	3828	*/
Kojto	110:165afa46840b	3829	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	110:165afa46840b	3830	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	3831	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	3832	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	3833
Kojto	110:165afa46840b	3834	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	3835	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	3836	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	3837	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	110:165afa46840b	3838	/**
Kojto	110:165afa46840b	3839	* @}
Kojto	110:165afa46840b	3840	*/
Kojto	110:165afa46840b	3841	#endif /* STM32F411xE */
Kojto	110:165afa46840b	3842	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	3843
Kojto	110:165afa46840b	3844	/---------------------------------- STM32F446xx -----------------------------/
Kojto	110:165afa46840b	3845	#if defined(STM32F446xx)
Kojto	110:165afa46840b	3846	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3847	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	110:165afa46840b	3848	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	110:165afa46840b	3849	* is disabled and the application software has to enable this clock before
Kojto	110:165afa46840b	3850	* using it.
Kojto	122:f9eeca106725	3851	* @{
Kojto	110:165afa46840b	3852	*/
Kojto	110:165afa46840b	3853	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3854	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3855	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	3856	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3857	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	110:165afa46840b	3858	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3859	} while(0)
Kojto	110:165afa46840b	3860	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3861	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3862	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	3863	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3864	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	110:165afa46840b	3865	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3866	} while(0)
Kojto	110:165afa46840b	3867	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3868	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3869	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3870	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3871	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	110:165afa46840b	3872	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3873	} while(0)
Kojto	122:f9eeca106725	3874	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3875	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3876	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	3877	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3878	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	110:165afa46840b	3879	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3880	} while(0)
Kojto	122:f9eeca106725	3881	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3882	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3883	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	3884	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3885	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	110:165afa46840b	3886	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	3887	} while(0)
Kojto	99:dbbf35b96557	3888	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3889	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	3890	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	3891	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3892	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	99:dbbf35b96557	3893	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3894	} while(0)
Kojto	99:dbbf35b96557	3895	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3896	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	3897	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	3898	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3899	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	99:dbbf35b96557	3900	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3901	} while(0)
Kojto	99:dbbf35b96557	3902	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3903	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	3904	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	3905	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3906	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	99:dbbf35b96557	3907	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3908	} while(0)
Kojto	99:dbbf35b96557	3909	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3910	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	3911	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	3912	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3913	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	99:dbbf35b96557	3914	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3915	} while(0)
Kojto	110:165afa46840b	3916	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	110:165afa46840b	3917	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	99:dbbf35b96557	3918	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	99:dbbf35b96557	3919	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	99:dbbf35b96557	3920	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	99:dbbf35b96557	3921	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	110:165afa46840b	3922	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	110:165afa46840b	3923	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	110:165afa46840b	3924	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	110:165afa46840b	3925	/**
Kojto	110:165afa46840b	3926	* @}
Kojto	110:165afa46840b	3927	*/
Kojto	110:165afa46840b	3928
Kojto	122:f9eeca106725	3929	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3930	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	3931	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3932	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3933	* using it.
Kojto	122:f9eeca106725	3934	* @{
Kojto	122:f9eeca106725	3935	*/
Kojto	122:f9eeca106725	3936	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	3937	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	122:f9eeca106725	3938	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
Kojto	122:f9eeca106725	3939	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
Kojto	122:f9eeca106725	3940	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
Kojto	122:f9eeca106725	3941	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
Kojto	122:f9eeca106725	3942	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Kojto	122:f9eeca106725	3943	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
Kojto	122:f9eeca106725	3944	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	3945
Kojto	122:f9eeca106725	3946	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	3947	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	122:f9eeca106725	3948	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
Kojto	122:f9eeca106725	3949	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
Kojto	122:f9eeca106725	3950	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
Kojto	122:f9eeca106725	3951	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
Kojto	122:f9eeca106725	3952	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
Kojto	122:f9eeca106725	3953	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
Kojto	122:f9eeca106725	3954	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	3955	/**
Kojto	122:f9eeca106725	3956	* @}
Kojto	122:f9eeca106725	3957	*/
Kojto	122:f9eeca106725	3958
Kojto	110:165afa46840b	3959	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	3960	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	99:dbbf35b96557	3961	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	3962	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	3963	* using it.
Kojto	122:f9eeca106725	3964	* @{
Kojto	99:dbbf35b96557	3965	*/
Kojto	99:dbbf35b96557	3966	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3967	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	3968	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	3969	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	3970	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	99:dbbf35b96557	3971	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	3972	} while(0)
Kojto	99:dbbf35b96557	3973	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	110:165afa46840b	3974	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	110:165afa46840b	3975	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	110:165afa46840b	3976	}while(0)
Kojto	110:165afa46840b	3977
Kojto	122:f9eeca106725	3978	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	110:165afa46840b	3979
Kojto	110:165afa46840b	3980	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	3981	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	3982	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	3983	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	3984	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	110:165afa46840b	3985	UNUSED(tmpreg); \
Kojto	110:165afa46840b	3986	} while(0)
Kojto	110:165afa46840b	3987	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	110:165afa46840b	3988	/**
Kojto	110:165afa46840b	3989	* @}
Kojto	110:165afa46840b	3990	*/
Kojto	122:f9eeca106725	3991
Kojto	122:f9eeca106725	3992	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	3993	* @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto	122:f9eeca106725	3994	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	3995	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	3996	* using it.
Kojto	122:f9eeca106725	3997	* @{
Kojto	122:f9eeca106725	3998	*/
Kojto	122:f9eeca106725	3999	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
Kojto	122:f9eeca106725	4000	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
Kojto	122:f9eeca106725	4001
Kojto	122:f9eeca106725	4002	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto	122:f9eeca106725	4003	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	122:f9eeca106725	4004
Kojto	122:f9eeca106725	4005	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
Kojto	122:f9eeca106725	4006	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
Kojto	122:f9eeca106725	4007	/**
Kojto	122:f9eeca106725	4008	* @}
Kojto	122:f9eeca106725	4009	*/
Kojto	122:f9eeca106725	4010
Kojto	110:165afa46840b	4011	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	4012	* @brief Enables or disables the AHB3 peripheral clock.
Kojto	99:dbbf35b96557	4013	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	4014	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	4015	* using it.
Kojto	122:f9eeca106725	4016	* @{
Kojto	99:dbbf35b96557	4017	*/
Kojto	99:dbbf35b96557	4018	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4019	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4020	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	4021	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4022	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	99:dbbf35b96557	4023	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4024	} while(0)
Kojto	99:dbbf35b96557	4025	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4026	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4027	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	99:dbbf35b96557	4028	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4029	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	99:dbbf35b96557	4030	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4031	} while(0)
Kojto	99:dbbf35b96557	4032
Kojto	99:dbbf35b96557	4033	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	99:dbbf35b96557	4034	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto	110:165afa46840b	4035	/**
Kojto	110:165afa46840b	4036	* @}
Kojto	110:165afa46840b	4037	*/
Kojto	110:165afa46840b	4038
Kojto	122:f9eeca106725	4039	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4040	* @brief Get the enable or disable status of the AHB3 peripheral clock.
Kojto	122:f9eeca106725	4041	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4042	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4043	* using it.
Kojto	122:f9eeca106725	4044	* @{
Kojto	122:f9eeca106725	4045	*/
Kojto	122:f9eeca106725	4046	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
Kojto	122:f9eeca106725	4047	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
Kojto	122:f9eeca106725	4048
Kojto	122:f9eeca106725	4049	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
Kojto	122:f9eeca106725	4050	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
Kojto	122:f9eeca106725	4051	/**
Kojto	122:f9eeca106725	4052	* @}
Kojto	122:f9eeca106725	4053	*/
Kojto	122:f9eeca106725	4054
Kojto	110:165afa46840b	4055	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	4056	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	99:dbbf35b96557	4057	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	4058	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	4059	* using it.
Kojto	122:f9eeca106725	4060	* @{
Kojto	99:dbbf35b96557	4061	*/
Kojto	99:dbbf35b96557	4062	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4063	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4064	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	4065	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4066	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	99:dbbf35b96557	4067	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4068	} while(0)
Kojto	99:dbbf35b96557	4069	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4070	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4071	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	4072	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4073	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	99:dbbf35b96557	4074	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4075	} while(0)
Kojto	99:dbbf35b96557	4076	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4077	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4078	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	4079	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4080	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	99:dbbf35b96557	4081	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4082	} while(0)
Kojto	99:dbbf35b96557	4083	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4084	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4085	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	4086	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4087	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	99:dbbf35b96557	4088	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4089	} while(0)
Kojto	99:dbbf35b96557	4090	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4091	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4092	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	4093	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4094	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	99:dbbf35b96557	4095	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4096	} while(0)
Kojto	99:dbbf35b96557	4097	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4098	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4099	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	99:dbbf35b96557	4100	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4101	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	99:dbbf35b96557	4102	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4103	} while(0)
Kojto	99:dbbf35b96557	4104	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4105	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4106	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	4107	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4108	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	99:dbbf35b96557	4109	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4110	} while(0)
Kojto	99:dbbf35b96557	4111	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4112	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4113	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	4114	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4115	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	99:dbbf35b96557	4116	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4117	} while(0)
Kojto	99:dbbf35b96557	4118	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4119	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4120	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	4121	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4122	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	99:dbbf35b96557	4123	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4124	} while(0)
Kojto	99:dbbf35b96557	4125	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4126	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4127	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	99:dbbf35b96557	4128	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4129	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	99:dbbf35b96557	4130	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4131	} while(0)
Kojto	99:dbbf35b96557	4132	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4133	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4134	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	4135	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4136	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	99:dbbf35b96557	4137	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4138	} while(0)
Kojto	99:dbbf35b96557	4139	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4140	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4141	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	4142	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4143	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	99:dbbf35b96557	4144	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4145	} while(0)
Kojto	99:dbbf35b96557	4146	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4147	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4148	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	99:dbbf35b96557	4149	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4150	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	99:dbbf35b96557	4151	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4152	} while(0)
Kojto	99:dbbf35b96557	4153	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4154	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4155	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	4156	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4157	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	99:dbbf35b96557	4158	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4159	} while(0)
Kojto	110:165afa46840b	4160	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4161	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4162	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	4163	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4164	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	110:165afa46840b	4165	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4166	} while(0)
Kojto	110:165afa46840b	4167	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4168	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4169	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	4170	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4171	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	110:165afa46840b	4172	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4173	} while(0)
Kojto	110:165afa46840b	4174	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4175	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4176	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	4177	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4178	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	110:165afa46840b	4179	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4180	} while(0)
Kojto	110:165afa46840b	4181	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4182	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4183	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	4184	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4185	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	110:165afa46840b	4186	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4187	} while(0)
Kojto	110:165afa46840b	4188	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4189	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4190	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	4191	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4192	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	110:165afa46840b	4193	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4194	} while(0)
Kojto	110:165afa46840b	4195	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	110:165afa46840b	4196	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	110:165afa46840b	4197	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	110:165afa46840b	4198	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	110:165afa46840b	4199	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	99:dbbf35b96557	4200	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	99:dbbf35b96557	4201	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	99:dbbf35b96557	4202	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	99:dbbf35b96557	4203	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	99:dbbf35b96557	4204	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	99:dbbf35b96557	4205	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
Kojto	99:dbbf35b96557	4206	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	99:dbbf35b96557	4207	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	99:dbbf35b96557	4208	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	99:dbbf35b96557	4209	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto	99:dbbf35b96557	4210	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	99:dbbf35b96557	4211	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	99:dbbf35b96557	4212	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto	99:dbbf35b96557	4213	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	110:165afa46840b	4214	/**
Kojto	110:165afa46840b	4215	* @}
Kojto	110:165afa46840b	4216	*/
Kojto	110:165afa46840b	4217
Kojto	122:f9eeca106725	4218	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4219	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	4220	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4221	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4222	* using it.
Kojto	122:f9eeca106725	4223	* @{
Kojto	122:f9eeca106725	4224	*/
Kojto	122:f9eeca106725	4225	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	4226	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	122:f9eeca106725	4227	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	122:f9eeca106725	4228	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto	122:f9eeca106725	4229	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	122:f9eeca106725	4230	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	122:f9eeca106725	4231	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto	122:f9eeca106725	4232	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto	122:f9eeca106725	4233	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto	122:f9eeca106725	4234	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto	122:f9eeca106725	4235	#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
Kojto	122:f9eeca106725	4236	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto	122:f9eeca106725	4237	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto	122:f9eeca106725	4238	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto	122:f9eeca106725	4239	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
Kojto	122:f9eeca106725	4240	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto	122:f9eeca106725	4241	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
Kojto	122:f9eeca106725	4242	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
Kojto	122:f9eeca106725	4243	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto	122:f9eeca106725	4244
Kojto	122:f9eeca106725	4245	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	4246	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	122:f9eeca106725	4247	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	122:f9eeca106725	4248	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto	122:f9eeca106725	4249	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	122:f9eeca106725	4250	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	122:f9eeca106725	4251	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto	122:f9eeca106725	4252	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto	122:f9eeca106725	4253	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto	122:f9eeca106725	4254	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto	122:f9eeca106725	4255	#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
Kojto	122:f9eeca106725	4256	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto	122:f9eeca106725	4257	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto	122:f9eeca106725	4258	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto	122:f9eeca106725	4259	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
Kojto	122:f9eeca106725	4260	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto	122:f9eeca106725	4261	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Kojto	122:f9eeca106725	4262	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Kojto	122:f9eeca106725	4263	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto	122:f9eeca106725	4264	/**
Kojto	122:f9eeca106725	4265	* @}
Kojto	122:f9eeca106725	4266	*/
Kojto	122:f9eeca106725	4267
Kojto	110:165afa46840b	4268	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	110:165afa46840b	4269	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	99:dbbf35b96557	4270	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	4271	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	4272	* using it.
Kojto	122:f9eeca106725	4273	* @{
Kojto	99:dbbf35b96557	4274	*/
Kojto	99:dbbf35b96557	4275	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4276	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4277	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	4278	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4279	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	99:dbbf35b96557	4280	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4281	} while(0)
Kojto	99:dbbf35b96557	4282	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4283	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4284	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	4285	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4286	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	99:dbbf35b96557	4287	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4288	} while(0)
Kojto	99:dbbf35b96557	4289	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4290	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4291	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	4292	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4293	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	99:dbbf35b96557	4294	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4295	} while(0)
Kojto	99:dbbf35b96557	4296	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4297	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4298	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	4299	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4300	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	99:dbbf35b96557	4301	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4302	} while(0)
Kojto	99:dbbf35b96557	4303	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4304	__IO uint32_t tmpreg = 0x00U; \
Kojto	99:dbbf35b96557	4305	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	99:dbbf35b96557	4306	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	4307	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	99:dbbf35b96557	4308	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	4309	} while(0)
Kojto	110:165afa46840b	4310	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4311	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4312	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	4313	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4314	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	110:165afa46840b	4315	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4316	} while(0)
Kojto	110:165afa46840b	4317	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4318	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4319	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	4320	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4321	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	110:165afa46840b	4322	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4323	} while(0)
Kojto	110:165afa46840b	4324	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4325	__IO uint32_t tmpreg = 0x00U; \
Kojto	110:165afa46840b	4326	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	4327	/* Delay after an RCC peripheral clock enabling */ \
Kojto	110:165afa46840b	4328	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	110:165afa46840b	4329	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4330	} while(0)
Kojto	110:165afa46840b	4331	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	110:165afa46840b	4332	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	110:165afa46840b	4333	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	110:165afa46840b	4334	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	110:165afa46840b	4335	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	110:165afa46840b	4336	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	110:165afa46840b	4337	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	110:165afa46840b	4338	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
Kojto	110:165afa46840b	4339	/**
Kojto	110:165afa46840b	4340	* @}
Kojto	110:165afa46840b	4341	*/
Kojto	110:165afa46840b	4342
Kojto	122:f9eeca106725	4343	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4344	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	4345	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4346	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4347	* using it.
Kojto	122:f9eeca106725	4348	* @{
Kojto	122:f9eeca106725	4349	*/
Kojto	122:f9eeca106725	4350	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
Kojto	122:f9eeca106725	4351	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto	122:f9eeca106725	4352	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
Kojto	122:f9eeca106725	4353	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
Kojto	122:f9eeca106725	4354	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
Kojto	122:f9eeca106725	4355	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
Kojto	122:f9eeca106725	4356	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
Kojto	122:f9eeca106725	4357	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
Kojto	122:f9eeca106725	4358
Kojto	122:f9eeca106725	4359	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
Kojto	122:f9eeca106725	4360	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto	122:f9eeca106725	4361	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto	122:f9eeca106725	4362	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
Kojto	122:f9eeca106725	4363	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
Kojto	122:f9eeca106725	4364	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
Kojto	122:f9eeca106725	4365	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
Kojto	122:f9eeca106725	4366	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
Kojto	122:f9eeca106725	4367	/**
Kojto	122:f9eeca106725	4368	* @}
Kojto	122:f9eeca106725	4369	*/
Kojto	122:f9eeca106725	4370
Kojto	110:165afa46840b	4371	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	110:165afa46840b	4372	* @brief Force or release AHB1 peripheral reset.
Kojto	122:f9eeca106725	4373	* @{
Kojto	110:165afa46840b	4374	*/
Kojto	110:165afa46840b	4375	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	4376	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	4377	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	4378	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	4379	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	110:165afa46840b	4380	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	4381
Kojto	110:165afa46840b	4382	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	110:165afa46840b	4383	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	99:dbbf35b96557	4384	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	99:dbbf35b96557	4385	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	99:dbbf35b96557	4386	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	110:165afa46840b	4387	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	110:165afa46840b	4388	/**
Kojto	110:165afa46840b	4389	* @}
Kojto	110:165afa46840b	4390	*/
Kojto	110:165afa46840b	4391
Kojto	110:165afa46840b	4392	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	110:165afa46840b	4393	* @brief Force or release AHB2 peripheral reset.
Kojto	110:165afa46840b	4394	* @{
Kojto	110:165afa46840b	4395	*/
Kojto	122:f9eeca106725	4396	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto	110:165afa46840b	4397	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	4398	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	99:dbbf35b96557	4399	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	110:165afa46840b	4400
Kojto	122:f9eeca106725	4401	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto	110:165afa46840b	4402	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	110:165afa46840b	4403	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	99:dbbf35b96557	4404	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	110:165afa46840b	4405	/**
Kojto	110:165afa46840b	4406	* @}
Kojto	110:165afa46840b	4407	*/
Kojto	110:165afa46840b	4408
Kojto	110:165afa46840b	4409	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	110:165afa46840b	4410	* @brief Force or release AHB3 peripheral reset.
Kojto	110:165afa46840b	4411	* @{
Kojto	99:dbbf35b96557	4412	*/
Kojto	122:f9eeca106725	4413	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	4414	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	110:165afa46840b	4415
Kojto	99:dbbf35b96557	4416	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	99:dbbf35b96557	4417	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	99:dbbf35b96557	4418
Kojto	99:dbbf35b96557	4419	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	99:dbbf35b96557	4420	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	110:165afa46840b	4421	/**
Kojto	110:165afa46840b	4422	* @}
Kojto	110:165afa46840b	4423	*/
Kojto	110:165afa46840b	4424
Kojto	110:165afa46840b	4425	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	110:165afa46840b	4426	* @brief Force or release APB1 peripheral reset.
Kojto	122:f9eeca106725	4427	* @{
Kojto	122:f9eeca106725	4428	*/
Kojto	99:dbbf35b96557	4429	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	4430	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	4431	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	4432	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	4433	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	110:165afa46840b	4434	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
Kojto	99:dbbf35b96557	4435	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	4436	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	4437	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	4438	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
Kojto	99:dbbf35b96557	4439	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	4440	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	4441	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
Kojto	99:dbbf35b96557	4442	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	4443	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	4444	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	4445	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	4446	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	4447	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	110:165afa46840b	4448
Kojto	110:165afa46840b	4449	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	110:165afa46840b	4450	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	110:165afa46840b	4451	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	110:165afa46840b	4452	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	110:165afa46840b	4453	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	99:dbbf35b96557	4454	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	99:dbbf35b96557	4455	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	99:dbbf35b96557	4456	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	99:dbbf35b96557	4457	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	99:dbbf35b96557	4458	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	99:dbbf35b96557	4459	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
Kojto	99:dbbf35b96557	4460	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	99:dbbf35b96557	4461	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	99:dbbf35b96557	4462	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	99:dbbf35b96557	4463	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
Kojto	99:dbbf35b96557	4464	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	99:dbbf35b96557	4465	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	99:dbbf35b96557	4466	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto	99:dbbf35b96557	4467	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	110:165afa46840b	4468	/**
Kojto	110:165afa46840b	4469	* @}
Kojto	110:165afa46840b	4470	*/
Kojto	110:165afa46840b	4471
Kojto	110:165afa46840b	4472	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	110:165afa46840b	4473	* @brief Force or release APB2 peripheral reset.
Kojto	122:f9eeca106725	4474	* @{
Kojto	110:165afa46840b	4475	*/
Kojto	110:165afa46840b	4476	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	110:165afa46840b	4477	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	110:165afa46840b	4478	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
Kojto	110:165afa46840b	4479	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	4480	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	4481	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	4482
Kojto	110:165afa46840b	4483	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	110:165afa46840b	4484	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	110:165afa46840b	4485	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	110:165afa46840b	4486	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	110:165afa46840b	4487	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto	110:165afa46840b	4488	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
Kojto	110:165afa46840b	4489	/**
Kojto	110:165afa46840b	4490	* @}
Kojto	110:165afa46840b	4491	*/
Kojto	110:165afa46840b	4492
Kojto	110:165afa46840b	4493	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	4494	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	4495	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	4496	* power consumption.
Kojto	99:dbbf35b96557	4497	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	4498	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	4499	* @{
Kojto	110:165afa46840b	4500	*/
Kojto	110:165afa46840b	4501	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	4502	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	4503	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	4504	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	4505	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	4506	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	4507	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	110:165afa46840b	4508	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	4509	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	4510	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	4511	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	4512
Kojto	110:165afa46840b	4513	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	110:165afa46840b	4514	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	99:dbbf35b96557	4515	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	99:dbbf35b96557	4516	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	99:dbbf35b96557	4517	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	99:dbbf35b96557	4518	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	99:dbbf35b96557	4519	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	110:165afa46840b	4520	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	110:165afa46840b	4521	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	110:165afa46840b	4522	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	110:165afa46840b	4523	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	110:165afa46840b	4524	/**
Kojto	110:165afa46840b	4525	* @}
Kojto	110:165afa46840b	4526	*/
Kojto	110:165afa46840b	4527
Kojto	110:165afa46840b	4528	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	4529	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	4530	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	4531	* power consumption.
Kojto	110:165afa46840b	4532	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	4533	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	110:165afa46840b	4534	* @{
Kojto	110:165afa46840b	4535	*/
Kojto	110:165afa46840b	4536	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	4537	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	110:165afa46840b	4538
Kojto	110:165afa46840b	4539	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	4540	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	110:165afa46840b	4541
Kojto	99:dbbf35b96557	4542	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	99:dbbf35b96557	4543	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	110:165afa46840b	4544	/**
Kojto	110:165afa46840b	4545	* @}
Kojto	110:165afa46840b	4546	*/
Kojto	110:165afa46840b	4547
Kojto	110:165afa46840b	4548	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	4549	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	4550	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	4551	* power consumption.
Kojto	99:dbbf35b96557	4552	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	4553	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	4554	* @{
Kojto	99:dbbf35b96557	4555	*/
Kojto	99:dbbf35b96557	4556	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	99:dbbf35b96557	4557	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	99:dbbf35b96557	4558
Kojto	99:dbbf35b96557	4559	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto	99:dbbf35b96557	4560	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	110:165afa46840b	4561	/**
Kojto	110:165afa46840b	4562	* @}
Kojto	110:165afa46840b	4563	*/
Kojto	110:165afa46840b	4564
Kojto	110:165afa46840b	4565	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	4566	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	4567	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	4568	* power consumption.
Kojto	99:dbbf35b96557	4569	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	4570	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	4571	* @{
Kojto	122:f9eeca106725	4572	*/
Kojto	99:dbbf35b96557	4573	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	4574	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	4575	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	4576	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	4577	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	110:165afa46840b	4578	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	99:dbbf35b96557	4579	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	4580	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	4581	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	99:dbbf35b96557	4582	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	99:dbbf35b96557	4583	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	4584	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	4585	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
Kojto	99:dbbf35b96557	4586	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	4587	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	4588	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	4589	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	4590	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	4591	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	110:165afa46840b	4592
Kojto	110:165afa46840b	4593	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	110:165afa46840b	4594	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	110:165afa46840b	4595	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	110:165afa46840b	4596	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	110:165afa46840b	4597	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	99:dbbf35b96557	4598	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	99:dbbf35b96557	4599	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	99:dbbf35b96557	4600	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	99:dbbf35b96557	4601	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	99:dbbf35b96557	4602	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	110:165afa46840b	4603	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	99:dbbf35b96557	4604	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	99:dbbf35b96557	4605	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	99:dbbf35b96557	4606	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	110:165afa46840b	4607	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	99:dbbf35b96557	4608	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	99:dbbf35b96557	4609	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	99:dbbf35b96557	4610	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
Kojto	99:dbbf35b96557	4611	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	110:165afa46840b	4612	/**
Kojto	110:165afa46840b	4613	* @}
Kojto	110:165afa46840b	4614	*/
Kojto	110:165afa46840b	4615
Kojto	110:165afa46840b	4616	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	110:165afa46840b	4617	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	89:552587b429a1	4618	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	89:552587b429a1	4619	* power consumption.
bogdanm	89:552587b429a1	4620	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	89:552587b429a1	4621	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	4622	* @{
Kojto	122:f9eeca106725	4623	*/
Kojto	99:dbbf35b96557	4624	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	4625	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	4626	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	4627	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	99:dbbf35b96557	4628	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
Kojto	110:165afa46840b	4629	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	4630	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	4631	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	110:165afa46840b	4632
Kojto	110:165afa46840b	4633	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	110:165afa46840b	4634	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	110:165afa46840b	4635	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	99:dbbf35b96557	4636	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	99:dbbf35b96557	4637	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	99:dbbf35b96557	4638	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	99:dbbf35b96557	4639	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto	99:dbbf35b96557	4640	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
Kojto	110:165afa46840b	4641	/**
Kojto	110:165afa46840b	4642	* @}
Kojto	110:165afa46840b	4643	*/
Kojto	99:dbbf35b96557	4644
Kojto	99:dbbf35b96557	4645	#endif /* STM32F446xx */
Kojto	110:165afa46840b	4646	/----------------------------------------------------------------------------/
Kojto	122:f9eeca106725	4647
Kojto	122:f9eeca106725	4648	/----------STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx----------/
Kojto	122:f9eeca106725	4649	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	122:f9eeca106725	4650	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	122:f9eeca106725	4651	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	122:f9eeca106725	4652	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4653	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4654	* using it.
Kojto	122:f9eeca106725	4655	* @{
Kojto	122:f9eeca106725	4656	*/
Kojto	122:f9eeca106725	4657	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4658	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4659	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	122:f9eeca106725	4660	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4661	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	122:f9eeca106725	4662	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4663	} while(0)
Kojto	122:f9eeca106725	4664	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4665	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4666	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	122:f9eeca106725	4667	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4668	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	122:f9eeca106725	4669	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4670	} while(0)
Kojto	122:f9eeca106725	4671	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4672	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4673	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	122:f9eeca106725	4674	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4675	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	122:f9eeca106725	4676	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4677	} while(0)
Kojto	122:f9eeca106725	4678	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4679	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4680	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	122:f9eeca106725	4681	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4682	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	122:f9eeca106725	4683	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4684	} while(0)
Kojto	122:f9eeca106725	4685	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4686	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4687	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	122:f9eeca106725	4688	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4689	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	122:f9eeca106725	4690	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4691	} while(0)
Kojto	122:f9eeca106725	4692	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4693	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4694	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	122:f9eeca106725	4695	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4696	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	122:f9eeca106725	4697	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4698	} while(0)
Kojto	122:f9eeca106725	4699
Kojto	122:f9eeca106725	4700	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	122:f9eeca106725	4701	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	122:f9eeca106725	4702	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	122:f9eeca106725	4703	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	122:f9eeca106725	4704	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	122:f9eeca106725	4705	/**
Kojto	122:f9eeca106725	4706	* @}
Kojto	122:f9eeca106725	4707	*/
Kojto	122:f9eeca106725	4708
Kojto	122:f9eeca106725	4709	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4710	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	122:f9eeca106725	4711	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4712	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4713	* using it.
Kojto	122:f9eeca106725	4714	* @{
Kojto	122:f9eeca106725	4715	*/
Kojto	122:f9eeca106725	4716	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	122:f9eeca106725	4717	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	122:f9eeca106725	4718	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
Kojto	122:f9eeca106725	4719	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
Kojto	122:f9eeca106725	4720	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	122:f9eeca106725	4721
Kojto	122:f9eeca106725	4722	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	122:f9eeca106725	4723	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	122:f9eeca106725	4724	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
Kojto	122:f9eeca106725	4725	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
Kojto	122:f9eeca106725	4726	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	122:f9eeca106725	4727	/**
Kojto	122:f9eeca106725	4728	* @}
Kojto	122:f9eeca106725	4729	*/
Kojto	122:f9eeca106725	4730
Kojto	122:f9eeca106725	4731	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	122:f9eeca106725	4732	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	122:f9eeca106725	4733	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4734	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4735	* using it.
Kojto	122:f9eeca106725	4736	* @{
Kojto	122:f9eeca106725	4737	*/
Kojto	122:f9eeca106725	4738	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	122:f9eeca106725	4739	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	122:f9eeca106725	4740	}while(0)
Kojto	122:f9eeca106725	4741
Kojto	122:f9eeca106725	4742	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	122:f9eeca106725	4743
Kojto	122:f9eeca106725	4744	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4745	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4746	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	122:f9eeca106725	4747	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4748	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	122:f9eeca106725	4749	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4750	} while(0)
Kojto	122:f9eeca106725	4751	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	122:f9eeca106725	4752	/**
Kojto	122:f9eeca106725	4753	* @}
Kojto	122:f9eeca106725	4754	*/
Kojto	122:f9eeca106725	4755
Kojto	122:f9eeca106725	4756	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4757	* @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto	122:f9eeca106725	4758	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4759	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4760	* using it.
Kojto	122:f9eeca106725	4761	* @{
Kojto	122:f9eeca106725	4762	*/
Kojto	122:f9eeca106725	4763	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto	122:f9eeca106725	4764	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	122:f9eeca106725	4765
Kojto	122:f9eeca106725	4766	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
Kojto	122:f9eeca106725	4767	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
Kojto	122:f9eeca106725	4768	/**
Kojto	122:f9eeca106725	4769	* @}
Kojto	122:f9eeca106725	4770	*/
Kojto	122:f9eeca106725	4771
Kojto	122:f9eeca106725	4772	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	122:f9eeca106725	4773	* @brief Enables or disables the AHB3 peripheral clock.
Kojto	122:f9eeca106725	4774	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4775	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4776	* using it.
Kojto	122:f9eeca106725	4777	* @{
Kojto	122:f9eeca106725	4778	*/
Kojto	122:f9eeca106725	4779	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx)
Kojto	122:f9eeca106725	4780	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4781	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4782	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	122:f9eeca106725	4783	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4784	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	122:f9eeca106725	4785	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4786	} while(0)
Kojto	122:f9eeca106725	4787	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4788	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4789	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	122:f9eeca106725	4790	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4791	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	122:f9eeca106725	4792	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4793	} while(0)
Kojto	122:f9eeca106725	4794
Kojto	122:f9eeca106725	4795	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
Kojto	122:f9eeca106725	4796	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto	122:f9eeca106725	4797	#endif /* STM32F412Zx \|\| STM32F412Vx */
Kojto	122:f9eeca106725	4798	#if defined(STM32F412Rx)
Kojto	122:f9eeca106725	4799	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4800	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4801	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	122:f9eeca106725	4802	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4803	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	122:f9eeca106725	4804	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4805	} while(0)
Kojto	122:f9eeca106725	4806
Kojto	122:f9eeca106725	4807	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto	122:f9eeca106725	4808	#endif /* STM32F412Rx */
Kojto	122:f9eeca106725	4809	/**
Kojto	122:f9eeca106725	4810	* @}
Kojto	122:f9eeca106725	4811	*/
Kojto	122:f9eeca106725	4812
Kojto	122:f9eeca106725	4813	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4814	* @brief Get the enable or disable status of the AHB3 peripheral clock.
Kojto	122:f9eeca106725	4815	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4816	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4817	* using it.
Kojto	122:f9eeca106725	4818	* @{
Kojto	122:f9eeca106725	4819	*/
Kojto	122:f9eeca106725	4820	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx)
Kojto	122:f9eeca106725	4821	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
Kojto	122:f9eeca106725	4822	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
Kojto	122:f9eeca106725	4823
Kojto	122:f9eeca106725	4824	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
Kojto	122:f9eeca106725	4825	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
Kojto	122:f9eeca106725	4826	#endif /* STM32F412Zx \|\| STM32F412Vx */
Kojto	122:f9eeca106725	4827	#if defined(STM32F412Rx)
Kojto	122:f9eeca106725	4828	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
Kojto	122:f9eeca106725	4829	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
Kojto	122:f9eeca106725	4830	#endif /* STM32F412Rx */
Kojto	122:f9eeca106725	4831	/**
Kojto	122:f9eeca106725	4832	* @}
Kojto	122:f9eeca106725	4833	*/
Kojto	122:f9eeca106725	4834
Kojto	122:f9eeca106725	4835	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	122:f9eeca106725	4836	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	122:f9eeca106725	4837	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4838	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4839	* using it.
Kojto	122:f9eeca106725	4840	* @{
Kojto	122:f9eeca106725	4841	*/
Kojto	122:f9eeca106725	4842	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4843	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4844	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	122:f9eeca106725	4845	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4846	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	122:f9eeca106725	4847	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4848	} while(0)
Kojto	122:f9eeca106725	4849	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4850	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4851	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	122:f9eeca106725	4852	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4853	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	122:f9eeca106725	4854	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4855	} while(0)
Kojto	122:f9eeca106725	4856	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4857	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4858	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	122:f9eeca106725	4859	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4860	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	122:f9eeca106725	4861	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4862	} while(0)
Kojto	122:f9eeca106725	4863	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4864	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4865	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	122:f9eeca106725	4866	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4867	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	122:f9eeca106725	4868	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4869	} while(0)
Kojto	122:f9eeca106725	4870	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4871	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4872	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	122:f9eeca106725	4873	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4874	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	122:f9eeca106725	4875	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4876	} while(0)
Kojto	122:f9eeca106725	4877	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4878	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4879	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
Kojto	122:f9eeca106725	4880	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4881	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
Kojto	122:f9eeca106725	4882	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4883	} while(0)
Kojto	122:f9eeca106725	4884	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
Kojto	122:f9eeca106725	4885	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4886	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4887	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	122:f9eeca106725	4888	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4889	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	122:f9eeca106725	4890	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4891	} while(0)
Kojto	122:f9eeca106725	4892	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
Kojto	122:f9eeca106725	4893	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4894	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4895	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	122:f9eeca106725	4896	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4897	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	122:f9eeca106725	4898	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4899	} while(0)
Kojto	122:f9eeca106725	4900	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4901	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4902	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	122:f9eeca106725	4903	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4904	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	122:f9eeca106725	4905	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4906	} while(0)
Kojto	122:f9eeca106725	4907	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4908	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4909	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	122:f9eeca106725	4910	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4911	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	122:f9eeca106725	4912	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4913	} while(0)
Kojto	122:f9eeca106725	4914	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4915	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4916	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	122:f9eeca106725	4917	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4918	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	122:f9eeca106725	4919	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4920	} while(0)
Kojto	122:f9eeca106725	4921	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4922	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4923	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	122:f9eeca106725	4924	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4925	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	122:f9eeca106725	4926	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4927	} while(0)
Kojto	122:f9eeca106725	4928	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4929	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4930	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	122:f9eeca106725	4931	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4932	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	122:f9eeca106725	4933	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4934	} while(0)
Kojto	122:f9eeca106725	4935	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4936	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4937	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	122:f9eeca106725	4938	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4939	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	122:f9eeca106725	4940	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4941	} while(0)
Kojto	122:f9eeca106725	4942	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	4943	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	4944	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	122:f9eeca106725	4945	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	4946	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	122:f9eeca106725	4947	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	4948	} while(0)
Kojto	122:f9eeca106725	4949	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	122:f9eeca106725	4950	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	122:f9eeca106725	4951	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	122:f9eeca106725	4952	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	122:f9eeca106725	4953	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	122:f9eeca106725	4954	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	122:f9eeca106725	4955	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	122:f9eeca106725	4956	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	122:f9eeca106725	4957	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	122:f9eeca106725	4958	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	122:f9eeca106725	4959	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
Kojto	122:f9eeca106725	4960	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
Kojto	122:f9eeca106725	4961	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	122:f9eeca106725	4962	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
Kojto	122:f9eeca106725	4963	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto	122:f9eeca106725	4964	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	122:f9eeca106725	4965	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	122:f9eeca106725	4966	/**
Kojto	122:f9eeca106725	4967	* @}
Kojto	122:f9eeca106725	4968	*/
Kojto	122:f9eeca106725	4969
Kojto	122:f9eeca106725	4970	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	4971	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	122:f9eeca106725	4972	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	4973	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	4974	* using it.
Kojto	122:f9eeca106725	4975	* @{
Kojto	122:f9eeca106725	4976	*/
Kojto	122:f9eeca106725	4977	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	122:f9eeca106725	4978	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	122:f9eeca106725	4979	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	122:f9eeca106725	4980	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto	122:f9eeca106725	4981	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	122:f9eeca106725	4982	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	122:f9eeca106725	4983	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto	122:f9eeca106725	4984	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto	122:f9eeca106725	4985	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto	122:f9eeca106725	4986	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto	122:f9eeca106725	4987	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
Kojto	122:f9eeca106725	4988	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
Kojto	122:f9eeca106725	4989	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto	122:f9eeca106725	4990	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
Kojto	122:f9eeca106725	4991	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
Kojto	122:f9eeca106725	4992	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
Kojto	122:f9eeca106725	4993	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
Kojto	122:f9eeca106725	4994
Kojto	122:f9eeca106725	4995	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	122:f9eeca106725	4996	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	122:f9eeca106725	4997	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	122:f9eeca106725	4998	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto	122:f9eeca106725	4999	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	122:f9eeca106725	5000	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	122:f9eeca106725	5001	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto	122:f9eeca106725	5002	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto	122:f9eeca106725	5003	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto	122:f9eeca106725	5004	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto	122:f9eeca106725	5005	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
Kojto	122:f9eeca106725	5006	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
Kojto	122:f9eeca106725	5007	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto	122:f9eeca106725	5008	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
Kojto	122:f9eeca106725	5009	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
Kojto	122:f9eeca106725	5010	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto	122:f9eeca106725	5011	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Kojto	122:f9eeca106725	5012	/**
Kojto	122:f9eeca106725	5013	* @}
Kojto	122:f9eeca106725	5014	*/
Kojto	122:f9eeca106725	5015	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	122:f9eeca106725	5016	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	122:f9eeca106725	5017	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	5018	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	5019	* using it.
Kojto	122:f9eeca106725	5020	* @{
Kojto	122:f9eeca106725	5021	*/
Kojto	122:f9eeca106725	5022	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5023	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5024	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	122:f9eeca106725	5025	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5026	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	122:f9eeca106725	5027	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	5028	} while(0)
Kojto	122:f9eeca106725	5029	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5030	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5031	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	122:f9eeca106725	5032	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5033	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	122:f9eeca106725	5034	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	5035	} while(0)
Kojto	122:f9eeca106725	5036	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5037	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5038	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
Kojto	122:f9eeca106725	5039	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5040	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
Kojto	122:f9eeca106725	5041	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	5042	} while(0)
Kojto	122:f9eeca106725	5043	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5044	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5045	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
Kojto	122:f9eeca106725	5046	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5047	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
Kojto	122:f9eeca106725	5048	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	5049	} while(0)
Kojto	122:f9eeca106725	5050	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5051	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5052	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	122:f9eeca106725	5053	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5054	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	122:f9eeca106725	5055	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	5056	} while(0)
Kojto	122:f9eeca106725	5057	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5058	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5059	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	122:f9eeca106725	5060	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5061	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	122:f9eeca106725	5062	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	5063	} while(0)
Kojto	122:f9eeca106725	5064	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	122:f9eeca106725	5065	__IO uint32_t tmpreg = 0x00U; \
Kojto	122:f9eeca106725	5066	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	122:f9eeca106725	5067	/* Delay after an RCC peripheral clock enabling */ \
Kojto	122:f9eeca106725	5068	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	122:f9eeca106725	5069	UNUSED(tmpreg); \
Kojto	122:f9eeca106725	5070	} while(0)
Kojto	122:f9eeca106725	5071	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	122:f9eeca106725	5072	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	122:f9eeca106725	5073	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	122:f9eeca106725	5074	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	122:f9eeca106725	5075	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	122:f9eeca106725	5076	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
Kojto	122:f9eeca106725	5077	#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
Kojto	122:f9eeca106725	5078	/**
Kojto	122:f9eeca106725	5079	* @}
Kojto	122:f9eeca106725	5080	*/
Kojto	122:f9eeca106725	5081
Kojto	122:f9eeca106725	5082	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	122:f9eeca106725	5083	* @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	122:f9eeca106725	5084	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	122:f9eeca106725	5085	* is disabled and the application software has to enable this clock before
Kojto	122:f9eeca106725	5086	* using it.
Kojto	122:f9eeca106725	5087	* @{
Kojto	122:f9eeca106725	5088	*/
Kojto	122:f9eeca106725	5089	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
Kojto	122:f9eeca106725	5090	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto	122:f9eeca106725	5091	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
Kojto	122:f9eeca106725	5092	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
Kojto	122:f9eeca106725	5093	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
Kojto	122:f9eeca106725	5094	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
Kojto	122:f9eeca106725	5095	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
Kojto	122:f9eeca106725	5096
Kojto	122:f9eeca106725	5097	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
Kojto	122:f9eeca106725	5098	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto	122:f9eeca106725	5099	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto	122:f9eeca106725	5100	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
Kojto	122:f9eeca106725	5101	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
Kojto	122:f9eeca106725	5102	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
Kojto	122:f9eeca106725	5103	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
Kojto	122:f9eeca106725	5104	/**
Kojto	122:f9eeca106725	5105	* @}
Kojto	122:f9eeca106725	5106	*/
Kojto	122:f9eeca106725	5107
Kojto	122:f9eeca106725	5108	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	122:f9eeca106725	5109	* @brief Force or release AHB1 peripheral reset.
Kojto	122:f9eeca106725	5110	* @{
Kojto	122:f9eeca106725	5111	*/
Kojto	122:f9eeca106725	5112	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	122:f9eeca106725	5113	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	122:f9eeca106725	5114	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	122:f9eeca106725	5115	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	122:f9eeca106725	5116	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	122:f9eeca106725	5117
Kojto	122:f9eeca106725	5118	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	122:f9eeca106725	5119	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	122:f9eeca106725	5120	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	122:f9eeca106725	5121	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	122:f9eeca106725	5122	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	122:f9eeca106725	5123	/**
Kojto	122:f9eeca106725	5124	* @}
Kojto	122:f9eeca106725	5125	*/
Kojto	122:f9eeca106725	5126
Kojto	122:f9eeca106725	5127	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	122:f9eeca106725	5128	* @brief Force or release AHB2 peripheral reset.
Kojto	122:f9eeca106725	5129	* @{
Kojto	122:f9eeca106725	5130	*/
Kojto	122:f9eeca106725	5131	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	5132	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto	122:f9eeca106725	5133
Kojto	122:f9eeca106725	5134	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	122:f9eeca106725	5135	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	122:f9eeca106725	5136
Kojto	122:f9eeca106725	5137	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	122:f9eeca106725	5138	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	122:f9eeca106725	5139	/**
Kojto	122:f9eeca106725	5140	* @}
Kojto	122:f9eeca106725	5141	*/
Kojto	122:f9eeca106725	5142
Kojto	122:f9eeca106725	5143	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	122:f9eeca106725	5144	* @brief Force or release AHB3 peripheral reset.
Kojto	122:f9eeca106725	5145	* @{
Kojto	122:f9eeca106725	5146	*/
Kojto	122:f9eeca106725	5147	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx)
Kojto	122:f9eeca106725	5148	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	5149	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	122:f9eeca106725	5150
Kojto	122:f9eeca106725	5151	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
Kojto	122:f9eeca106725	5152	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	122:f9eeca106725	5153
Kojto	122:f9eeca106725	5154	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
Kojto	122:f9eeca106725	5155	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	122:f9eeca106725	5156	#endif /* STM32F412Zx \|\| STM32F412Vx */
Kojto	122:f9eeca106725	5157	#if defined(STM32F412Cx)
Kojto	122:f9eeca106725	5158	#define __HAL_RCC_AHB3_FORCE_RESET()
Kojto	122:f9eeca106725	5159	#define __HAL_RCC_AHB3_RELEASE_RESET()
Kojto	122:f9eeca106725	5160
Kojto	122:f9eeca106725	5161	#define __HAL_RCC_FSMC_FORCE_RESET()
Kojto	122:f9eeca106725	5162	#define __HAL_RCC_QSPI_FORCE_RESET()
Kojto	122:f9eeca106725	5163
Kojto	122:f9eeca106725	5164	#define __HAL_RCC_FSMC_RELEASE_RESET()
Kojto	122:f9eeca106725	5165	#define __HAL_RCC_QSPI_RELEASE_RESET()
Kojto	122:f9eeca106725	5166	#endif /* STM32F412Cx */
Kojto	122:f9eeca106725	5167	#if defined(STM32F412Rx)
Kojto	122:f9eeca106725	5168	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto	122:f9eeca106725	5169	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto	122:f9eeca106725	5170
Kojto	122:f9eeca106725	5171	#define __HAL_RCC_FSMC_FORCE_RESET()
Kojto	122:f9eeca106725	5172	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	122:f9eeca106725	5173
Kojto	122:f9eeca106725	5174	#define __HAL_RCC_FSMC_RELEASE_RESET()
Kojto	122:f9eeca106725	5175	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	122:f9eeca106725	5176	#endif /* STM32F412Rx */
Kojto	122:f9eeca106725	5177	/**
Kojto	122:f9eeca106725	5178	* @}
Kojto	122:f9eeca106725	5179	*/
Kojto	122:f9eeca106725	5180
Kojto	122:f9eeca106725	5181	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	122:f9eeca106725	5182	* @brief Force or release APB1 peripheral reset.
Kojto	122:f9eeca106725	5183	* @{
Kojto	122:f9eeca106725	5184	*/
Kojto	122:f9eeca106725	5185	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	122:f9eeca106725	5186	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	122:f9eeca106725	5187	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	122:f9eeca106725	5188	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	122:f9eeca106725	5189	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	122:f9eeca106725	5190	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
Kojto	122:f9eeca106725	5191	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	122:f9eeca106725	5192	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
Kojto	122:f9eeca106725	5193	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
Kojto	122:f9eeca106725	5194	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	122:f9eeca106725	5195	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	122:f9eeca106725	5196	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	122:f9eeca106725	5197	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	122:f9eeca106725	5198	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	122:f9eeca106725	5199	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	122:f9eeca106725	5200	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	122:f9eeca106725	5201
Kojto	122:f9eeca106725	5202	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	122:f9eeca106725	5203	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	122:f9eeca106725	5204	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	122:f9eeca106725	5205	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	122:f9eeca106725	5206	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	122:f9eeca106725	5207	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	122:f9eeca106725	5208	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	122:f9eeca106725	5209	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	122:f9eeca106725	5210	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	122:f9eeca106725	5211	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	122:f9eeca106725	5212	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
Kojto	122:f9eeca106725	5213	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	122:f9eeca106725	5214	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
Kojto	122:f9eeca106725	5215	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
Kojto	122:f9eeca106725	5216	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	122:f9eeca106725	5217	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	122:f9eeca106725	5218	/**
Kojto	122:f9eeca106725	5219	* @}
Kojto	122:f9eeca106725	5220	*/
Kojto	122:f9eeca106725	5221
Kojto	122:f9eeca106725	5222	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	122:f9eeca106725	5223	* @brief Force or release APB2 peripheral reset.
Kojto	122:f9eeca106725	5224	* @{
Kojto	122:f9eeca106725	5225	*/
Kojto	122:f9eeca106725	5226	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	122:f9eeca106725	5227	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	122:f9eeca106725	5228	#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM1RST))
Kojto	122:f9eeca106725	5229	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	122:f9eeca106725	5230	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	122:f9eeca106725	5231	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	122:f9eeca106725	5232
Kojto	122:f9eeca106725	5233	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	122:f9eeca106725	5234	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	122:f9eeca106725	5235	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	122:f9eeca106725	5236	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	122:f9eeca106725	5237	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	122:f9eeca106725	5238	#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
Kojto	122:f9eeca106725	5239	/**
Kojto	122:f9eeca106725	5240	* @}
Kojto	122:f9eeca106725	5241	*/
Kojto	122:f9eeca106725	5242
Kojto	122:f9eeca106725	5243	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	122:f9eeca106725	5244	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	5245	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	122:f9eeca106725	5246	* power consumption.
Kojto	122:f9eeca106725	5247	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	122:f9eeca106725	5248	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	5249	* @{
Kojto	122:f9eeca106725	5250	*/
Kojto	122:f9eeca106725	5251	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	122:f9eeca106725	5252	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	122:f9eeca106725	5253	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	122:f9eeca106725	5254	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	122:f9eeca106725	5255	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	122:f9eeca106725	5256	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	122:f9eeca106725	5257	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	122:f9eeca106725	5258
Kojto	122:f9eeca106725	5259	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	122:f9eeca106725	5260	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	122:f9eeca106725	5261	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	122:f9eeca106725	5262	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	122:f9eeca106725	5263	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	122:f9eeca106725	5264	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	122:f9eeca106725	5265	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	122:f9eeca106725	5266	/**
Kojto	122:f9eeca106725	5267	* @}
Kojto	122:f9eeca106725	5268	*/
Kojto	122:f9eeca106725	5269
Kojto	122:f9eeca106725	5270	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	122:f9eeca106725	5271	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	5272	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	122:f9eeca106725	5273	* power consumption.
Kojto	122:f9eeca106725	5274	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	122:f9eeca106725	5275	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	5276	* @{
Kojto	122:f9eeca106725	5277	*/
Kojto	122:f9eeca106725	5278	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	122:f9eeca106725	5279
Kojto	122:f9eeca106725	5280	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	122:f9eeca106725	5281
Kojto	122:f9eeca106725	5282	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	122:f9eeca106725	5283	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	122:f9eeca106725	5284	/**
Kojto	122:f9eeca106725	5285	* @}
Kojto	122:f9eeca106725	5286	*/
Kojto	122:f9eeca106725	5287
Kojto	122:f9eeca106725	5288	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	122:f9eeca106725	5289	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	5290	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	122:f9eeca106725	5291	* power consumption.
Kojto	122:f9eeca106725	5292	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	122:f9eeca106725	5293	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	5294	* @{
Kojto	122:f9eeca106725	5295	*/
Kojto	122:f9eeca106725	5296	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx)
Kojto	122:f9eeca106725	5297	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
Kojto	122:f9eeca106725	5298	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	122:f9eeca106725	5299
Kojto	122:f9eeca106725	5300	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
Kojto	122:f9eeca106725	5301	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	122:f9eeca106725	5302	#endif /* STM32F412Zx \|\| STM32F412Vx */
Kojto	122:f9eeca106725	5303
Kojto	122:f9eeca106725	5304	#if defined(STM32F412Rx)
Kojto	122:f9eeca106725	5305	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	122:f9eeca106725	5306	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	122:f9eeca106725	5307	#endif /* STM32F412Rx */
Kojto	122:f9eeca106725	5308	/**
Kojto	122:f9eeca106725	5309	* @}
Kojto	122:f9eeca106725	5310	*/
Kojto	122:f9eeca106725	5311
Kojto	122:f9eeca106725	5312	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	122:f9eeca106725	5313	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	5314	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	122:f9eeca106725	5315	* power consumption.
Kojto	122:f9eeca106725	5316	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	122:f9eeca106725	5317	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	5318	* @{
Kojto	122:f9eeca106725	5319	*/
Kojto	122:f9eeca106725	5320	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	122:f9eeca106725	5321	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	122:f9eeca106725	5322	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	122:f9eeca106725	5323	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	122:f9eeca106725	5324	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	122:f9eeca106725	5325	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
Kojto	122:f9eeca106725	5326	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
Kojto	122:f9eeca106725	5327	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	122:f9eeca106725	5328	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
Kojto	122:f9eeca106725	5329	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	122:f9eeca106725	5330	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	122:f9eeca106725	5331	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	122:f9eeca106725	5332	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	122:f9eeca106725	5333	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	122:f9eeca106725	5334	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	122:f9eeca106725	5335	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	122:f9eeca106725	5336	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	122:f9eeca106725	5337
Kojto	122:f9eeca106725	5338	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	122:f9eeca106725	5339	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	122:f9eeca106725	5340	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	122:f9eeca106725	5341	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	122:f9eeca106725	5342	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	122:f9eeca106725	5343	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	122:f9eeca106725	5344	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	122:f9eeca106725	5345	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	122:f9eeca106725	5346	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	122:f9eeca106725	5347	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	122:f9eeca106725	5348	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
Kojto	122:f9eeca106725	5349	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
Kojto	122:f9eeca106725	5350	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	122:f9eeca106725	5351	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
Kojto	122:f9eeca106725	5352	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	122:f9eeca106725	5353	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	122:f9eeca106725	5354	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	122:f9eeca106725	5355	/**
Kojto	122:f9eeca106725	5356	* @}
Kojto	122:f9eeca106725	5357	*/
Kojto	122:f9eeca106725	5358
Kojto	122:f9eeca106725	5359	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	122:f9eeca106725	5360	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	122:f9eeca106725	5361	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	122:f9eeca106725	5362	* power consumption.
Kojto	122:f9eeca106725	5363	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	122:f9eeca106725	5364	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	122:f9eeca106725	5365	* @{
Kojto	122:f9eeca106725	5366	*/
Kojto	122:f9eeca106725	5367	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	122:f9eeca106725	5368	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	122:f9eeca106725	5369	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
Kojto	122:f9eeca106725	5370	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM1LPEN))
Kojto	122:f9eeca106725	5371	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	122:f9eeca106725	5372	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	122:f9eeca106725	5373	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	122:f9eeca106725	5374
Kojto	122:f9eeca106725	5375	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	122:f9eeca106725	5376	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	122:f9eeca106725	5377	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	122:f9eeca106725	5378	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	122:f9eeca106725	5379	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	122:f9eeca106725	5380	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
Kojto	122:f9eeca106725	5381	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
Kojto	122:f9eeca106725	5382	/**
Kojto	122:f9eeca106725	5383	* @}
Kojto	122:f9eeca106725	5384	*/
Kojto	122:f9eeca106725	5385	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	122:f9eeca106725	5386	/----------------------------------------------------------------------------/
Kojto	122:f9eeca106725	5387
Kojto	110:165afa46840b	5388	/------------------------------- PLL Configuration --------------------------/
Kojto	110:165afa46840b	5389	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\|\
Kojto	122:f9eeca106725	5390	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
Kojto	122:f9eeca106725	5391	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	99:dbbf35b96557	5392	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	99:dbbf35b96557	5393	* @note This function must be used only when the main PLL is disabled.
Kojto	99:dbbf35b96557	5394	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	99:dbbf35b96557	5395	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5396	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	5397	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	5398	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	99:dbbf35b96557	5399	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	99:dbbf35b96557	5400	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	5401	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	5402	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	5403	* of 2 MHz to limit PLL jitter.
Kojto	99:dbbf35b96557	5404	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	122:f9eeca106725	5405	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	99:dbbf35b96557	5406	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5407	* output frequency is between 100 and 432 MHz.
Kojto	99:dbbf35b96557	5408	*
Kojto	99:dbbf35b96557	5409	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	99:dbbf35b96557	5410	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	5411	*
Kojto	99:dbbf35b96557	5412	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto	110:165afa46840b	5413	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	5414	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	99:dbbf35b96557	5415	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	99:dbbf35b96557	5416	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	99:dbbf35b96557	5417	* correctly.
Kojto	99:dbbf35b96557	5418	*
Kojto	99:dbbf35b96557	5419	* @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto	99:dbbf35b96557	5420	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	122:f9eeca106725	5421	* @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
Kojto	122:f9eeca106725	5422	STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
Kojto	99:dbbf35b96557	5423	*
Kojto	99:dbbf35b96557	5424	*/
Kojto	99:dbbf35b96557	5425	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
Kojto	99:dbbf35b96557	5426	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
Kojto	99:dbbf35b96557	5427	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
Kojto	99:dbbf35b96557	5428	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
Kojto	99:dbbf35b96557	5429	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
Kojto	99:dbbf35b96557	5430	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
Kojto	99:dbbf35b96557	5431	#else
Kojto	99:dbbf35b96557	5432	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	99:dbbf35b96557	5433	* @note This function must be used only when the main PLL is disabled.
Kojto	99:dbbf35b96557	5434	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	99:dbbf35b96557	5435	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5436	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	5437	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	5438	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	99:dbbf35b96557	5439	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	99:dbbf35b96557	5440	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	5441	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	5442	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	5443	* of 2 MHz to limit PLL jitter.
Kojto	99:dbbf35b96557	5444	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	122:f9eeca106725	5445	* This parameter must be a number between Min_Data = 50 and Max_Data = 432
Kojto	122:f9eeca106725	5446	* Except for STM32F411xE devices where Min_Data = 192.
Kojto	99:dbbf35b96557	5447	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5448	* output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
Kojto	122:f9eeca106725	5449	* where frequency is between 192 and 432 MHz.
Kojto	99:dbbf35b96557	5450	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	99:dbbf35b96557	5451	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	5452	*
Kojto	99:dbbf35b96557	5453	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto	110:165afa46840b	5454	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	5455	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	99:dbbf35b96557	5456	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	99:dbbf35b96557	5457	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	99:dbbf35b96557	5458	* correctly.
Kojto	99:dbbf35b96557	5459	*
Kojto	99:dbbf35b96557	5460	*/
Kojto	99:dbbf35b96557	5461	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
Kojto	122:f9eeca106725	5462	(RCC->PLLCFGR = (0x20000000U \| (__RCC_PLLSource__) \| (__PLLM__)\| \
Kojto	99:dbbf35b96557	5463	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
Kojto	99:dbbf35b96557	5464	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
Kojto	99:dbbf35b96557	5465	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
Kojto	122:f9eeca106725	5466	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	110:165afa46840b	5467	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	5468
Kojto	110:165afa46840b	5469	/----------------------------PLLI2S Configuration ---------------------------/
Kojto	110:165afa46840b	5470	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	5471	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	5472	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	122:f9eeca106725	5473	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
Kojto	122:f9eeca106725	5474	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	110:165afa46840b	5475
Kojto	110:165afa46840b	5476	/** @brief Macros to enable or disable the PLLI2S.
Kojto	110:165afa46840b	5477	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
Kojto	110:165afa46840b	5478	*/
Kojto	110:165afa46840b	5479	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
Kojto	110:165afa46840b	5480	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
Kojto	110:165afa46840b	5481
Kojto	110:165afa46840b	5482	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	122:f9eeca106725	5483	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
Kojto	122:f9eeca106725	5484	STM32F412Rx \|\| STM32F412Cx */
Kojto	99:dbbf35b96557	5485	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	5486	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	99:dbbf35b96557	5487	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	5488	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	5489	* HAL_RCC_ClockConfig() API).
Kojto	99:dbbf35b96557	5490	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	99:dbbf35b96557	5491	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	5492	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	5493	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	5494	* of 1 MHz to limit PLLI2S jitter.
Kojto	110:165afa46840b	5495	*
Kojto	99:dbbf35b96557	5496	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	122:f9eeca106725	5497	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	99:dbbf35b96557	5498	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5499	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	5500	*
Kojto	99:dbbf35b96557	5501	* @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
Kojto	99:dbbf35b96557	5502	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	5503	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
Kojto	99:dbbf35b96557	5504	*
Kojto	99:dbbf35b96557	5505	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	5506	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	5507	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	5508	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	5509	*
Kojto	99:dbbf35b96557	5510	* @param __PLLI2SQ__: specifies the division factor for SAI clock
Kojto	99:dbbf35b96557	5511	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	110:165afa46840b	5512	*/
Kojto	110:165afa46840b	5513	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
Kojto	110:165afa46840b	5514	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	110:165afa46840b	5515	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	110:165afa46840b	5516	((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
Kojto	110:165afa46840b	5517	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
Kojto	110:165afa46840b	5518	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	122:f9eeca106725	5519	#elif defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	122:f9eeca106725	5520	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	122:f9eeca106725	5521	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	122:f9eeca106725	5522	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	122:f9eeca106725	5523	* HAL_RCC_ClockConfig() API).
Kojto	122:f9eeca106725	5524	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	122:f9eeca106725	5525	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	122:f9eeca106725	5526	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	122:f9eeca106725	5527	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	122:f9eeca106725	5528	* of 1 MHz to limit PLLI2S jitter.
Kojto	122:f9eeca106725	5529	*
Kojto	122:f9eeca106725	5530	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	122:f9eeca106725	5531	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	122:f9eeca106725	5532	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5533	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	122:f9eeca106725	5534	*
Kojto	122:f9eeca106725	5535	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	122:f9eeca106725	5536	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	122:f9eeca106725	5537	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	122:f9eeca106725	5538	* on the I2S clock frequency.
Kojto	122:f9eeca106725	5539	*
Kojto	122:f9eeca106725	5540	* @param __PLLI2SQ__: specifies the division factor for SAI clock
Kojto	122:f9eeca106725	5541	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	122:f9eeca106725	5542	*/
Kojto	122:f9eeca106725	5543	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
Kojto	122:f9eeca106725	5544	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	122:f9eeca106725	5545	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	122:f9eeca106725	5546	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
Kojto	122:f9eeca106725	5547	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	99:dbbf35b96557	5548	#else
Kojto	99:dbbf35b96557	5549	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	99:dbbf35b96557	5550	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	5551	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	5552	* HAL_RCC_ClockConfig() API).
Kojto	99:dbbf35b96557	5553	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	122:f9eeca106725	5554	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	99:dbbf35b96557	5555	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5556	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	110:165afa46840b	5557	*
Kojto	99:dbbf35b96557	5558	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	5559	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	5560	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	5561	* on the I2S clock frequency.
Kojto	110:165afa46840b	5562	*
Kojto	110:165afa46840b	5563	*/
Kojto	110:165afa46840b	5564	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
Kojto	110:165afa46840b	5565	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	99:dbbf35b96557	5566	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	99:dbbf35b96557	5567	#endif /* STM32F446xx */
bogdanm	89:552587b429a1	5568
bogdanm	92:4fc01daae5a5	5569	#if defined(STM32F411xE)
Kojto	99:dbbf35b96557	5570	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	99:dbbf35b96557	5571	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	5572	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	5573	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	5574	* HAL_RCC_ClockConfig() API).
Kojto	99:dbbf35b96557	5575	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	99:dbbf35b96557	5576	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	110:165afa46840b	5577	* @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
Kojto	99:dbbf35b96557	5578	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	5579	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	5580	* of 2 MHz to limit PLLI2S jitter.
Kojto	99:dbbf35b96557	5581	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	99:dbbf35b96557	5582	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	99:dbbf35b96557	5583	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	99:dbbf35b96557	5584	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	5585	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	5586	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	5587	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	5588	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	5589	*/
Kojto	99:dbbf35b96557	5590	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	99:dbbf35b96557	5591	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	99:dbbf35b96557	5592	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	99:dbbf35b96557	5593	#endif /* STM32F411xE */
Kojto	99:dbbf35b96557	5594
Kojto	110:165afa46840b	5595	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	5596	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
Kojto	99:dbbf35b96557	5597	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	99:dbbf35b96557	5598	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	99:dbbf35b96557	5599	* HAL_RCC_ClockConfig() API)
Kojto	99:dbbf35b96557	5600	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	122:f9eeca106725	5601	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	99:dbbf35b96557	5602	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5603	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	5604	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
Kojto	99:dbbf35b96557	5605	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	110:165afa46840b	5606	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
Kojto	110:165afa46840b	5607	* Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
Kojto	99:dbbf35b96557	5608	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	99:dbbf35b96557	5609	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	5610	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	99:dbbf35b96557	5611	* on the I2S clock frequency.
Kojto	99:dbbf35b96557	5612	*/
Kojto	99:dbbf35b96557	5613	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) \|\
Kojto	99:dbbf35b96557	5614	((__PLLI2SQ__) << 24) \|\
Kojto	99:dbbf35b96557	5615	((__PLLI2SR__) << 28))
Kojto	110:165afa46840b	5616	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	5617	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	5618
Kojto	110:165afa46840b	5619	/------------------------------ PLLSAI Configuration ------------------------/
Kojto	110:165afa46840b	5620	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	5621	/** @brief Macros to Enable or Disable the PLLISAI.
Kojto	110:165afa46840b	5622	* @note The PLLSAI is only available with STM32F429x/439x Devices.
Kojto	99:dbbf35b96557	5623	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
Kojto	99:dbbf35b96557	5624	*/
Kojto	99:dbbf35b96557	5625	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
Kojto	99:dbbf35b96557	5626	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
Kojto	99:dbbf35b96557	5627
Kojto	99:dbbf35b96557	5628	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	5629	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	99:dbbf35b96557	5630	*
Kojto	99:dbbf35b96557	5631	* @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
Kojto	99:dbbf35b96557	5632	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	99:dbbf35b96557	5633	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
Kojto	99:dbbf35b96557	5634	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	99:dbbf35b96557	5635	* of 1 MHz to limit PLLI2S jitter.
Kojto	99:dbbf35b96557	5636	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
Kojto	99:dbbf35b96557	5637	*
Kojto	99:dbbf35b96557	5638	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	122:f9eeca106725	5639	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	99:dbbf35b96557	5640	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5641	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	5642	*
Kojto	99:dbbf35b96557	5643	* @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto	99:dbbf35b96557	5644	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	99:dbbf35b96557	5645	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
Kojto	99:dbbf35b96557	5646	*
Kojto	99:dbbf35b96557	5647	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	99:dbbf35b96557	5648	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	5649	*
Kojto	99:dbbf35b96557	5650	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	99:dbbf35b96557	5651	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	5652	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
Kojto	99:dbbf35b96557	5653	*/
Kojto	99:dbbf35b96557	5654	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	99:dbbf35b96557	5655	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
Kojto	99:dbbf35b96557	5656	((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
Kojto	99:dbbf35b96557	5657	((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \| \
Kojto	99:dbbf35b96557	5658	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
Kojto	99:dbbf35b96557	5659	#endif /* STM32F446xx */
Kojto	110:165afa46840b	5660
Kojto	110:165afa46840b	5661	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	5662	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	110:165afa46840b	5663	*
Kojto	110:165afa46840b	5664	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	122:f9eeca106725	5665	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	110:165afa46840b	5666	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5667	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	110:165afa46840b	5668	*
Kojto	110:165afa46840b	5669	* @param __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks.
Kojto	110:165afa46840b	5670	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	110:165afa46840b	5671	*
Kojto	110:165afa46840b	5672	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	110:165afa46840b	5673	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	110:165afa46840b	5674	*
Kojto	110:165afa46840b	5675	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	110:165afa46840b	5676	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	110:165afa46840b	5677	*/
Kojto	110:165afa46840b	5678	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	110:165afa46840b	5679	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \|\
Kojto	110:165afa46840b	5680	((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \|\
Kojto	110:165afa46840b	5681	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \|\
Kojto	110:165afa46840b	5682	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
Kojto	110:165afa46840b	5683	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	5684
Kojto	99:dbbf35b96557	5685	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	5686	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	99:dbbf35b96557	5687	*
Kojto	99:dbbf35b96557	5688	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	122:f9eeca106725	5689	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	99:dbbf35b96557	5690	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	122:f9eeca106725	5691	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	99:dbbf35b96557	5692	*
Kojto	99:dbbf35b96557	5693	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	99:dbbf35b96557	5694	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	99:dbbf35b96557	5695	*
Kojto	99:dbbf35b96557	5696	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	99:dbbf35b96557	5697	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	99:dbbf35b96557	5698	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
bogdanm	92:4fc01daae5a5	5699	*/
Kojto	99:dbbf35b96557	5700	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	99:dbbf35b96557	5701	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
Kojto	99:dbbf35b96557	5702	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \| \
Kojto	99:dbbf35b96557	5703	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
Kojto	99:dbbf35b96557	5704	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	5705
Kojto	110:165afa46840b	5706	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	5707	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	5708
Kojto	110:165afa46840b	5709	/------------------- PLLSAI/PLLI2S Dividers Configuration -------------------/
Kojto	110:165afa46840b	5710	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
Kojto	110:165afa46840b	5711	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	5712	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
Kojto	110:165afa46840b	5713	* @note This function must be called before enabling the PLLI2S.
Kojto	110:165afa46840b	5714	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock.
Kojto	99:dbbf35b96557	5715	* This parameter must be a number between 1 and 32.
Kojto	99:dbbf35b96557	5716	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
Kojto	99:dbbf35b96557	5717	*/
Kojto	99:dbbf35b96557	5718	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
Kojto	99:dbbf35b96557	5719
Kojto	99:dbbf35b96557	5720	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
Kojto	99:dbbf35b96557	5721	* @note This function must be called before enabling the PLLSAI.
Kojto	99:dbbf35b96557	5722	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
Kojto	99:dbbf35b96557	5723	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
Kojto	99:dbbf35b96557	5724	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
Kojto	99:dbbf35b96557	5725	*/
Kojto	99:dbbf35b96557	5726	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
Kojto	110:165afa46840b	5727	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	5728
Kojto	110:165afa46840b	5729	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	5730	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
Kojto	99:dbbf35b96557	5731	*
Kojto	110:165afa46840b	5732	* @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
Kojto	99:dbbf35b96557	5733	* @note This function must be called before enabling the PLLSAI.
Kojto	99:dbbf35b96557	5734	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
Kojto	99:dbbf35b96557	5735	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
Kojto	99:dbbf35b96557	5736	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
Kojto	110:165afa46840b	5737	*/
Kojto	99:dbbf35b96557	5738	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
Kojto	110:165afa46840b	5739	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	5740	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	5741
Kojto	110:165afa46840b	5742	/------------------------- Peripheral Clock selection -----------------------/
Kojto	99:dbbf35b96557	5743	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
Kojto	99:dbbf35b96557	5744	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	5745	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\|\
Kojto	110:165afa46840b	5746	defined(STM32F479xx)
Kojto	99:dbbf35b96557	5747	/** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto	99:dbbf35b96557	5748	* @note This function must be called before enabling the I2S APB clock.
Kojto	99:dbbf35b96557	5749	* @param __SOURCE__: specifies the I2S clock source.
Kojto	99:dbbf35b96557	5750	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5751	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
Kojto	99:dbbf35b96557	5752	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	99:dbbf35b96557	5753	* used as I2S clock source.
bogdanm	92:4fc01daae5a5	5754	*/
Kojto	99:dbbf35b96557	5755	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
Kojto	110:165afa46840b	5756	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	5757
Kojto	110:165afa46840b	5758	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	5759
Kojto	99:dbbf35b96557	5760	/** @brief Macro to configure SAI1BlockA clock source selection.
Kojto	110:165afa46840b	5761	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
Kojto	99:dbbf35b96557	5762	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	5763	* the SAI clock.
Kojto	99:dbbf35b96557	5764	* @param __SOURCE__: specifies the SAI Block A clock source.
Kojto	99:dbbf35b96557	5765	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5766	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	99:dbbf35b96557	5767	* as SAI1 Block A clock.
Kojto	99:dbbf35b96557	5768	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	99:dbbf35b96557	5769	* as SAI1 Block A clock.
Kojto	99:dbbf35b96557	5770	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto	99:dbbf35b96557	5771	* used as SAI1 Block A clock.
Kojto	99:dbbf35b96557	5772	*/
Kojto	99:dbbf35b96557	5773	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	5774
Kojto	99:dbbf35b96557	5775	/** @brief Macro to configure SAI1BlockB clock source selection.
Kojto	110:165afa46840b	5776	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
Kojto	99:dbbf35b96557	5777	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	5778	* the SAI clock.
Kojto	99:dbbf35b96557	5779	* @param __SOURCE__: specifies the SAI Block B clock source.
Kojto	99:dbbf35b96557	5780	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5781	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	99:dbbf35b96557	5782	* as SAI1 Block B clock.
Kojto	99:dbbf35b96557	5783	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	99:dbbf35b96557	5784	* as SAI1 Block B clock.
Kojto	99:dbbf35b96557	5785	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto	99:dbbf35b96557	5786	* used as SAI1 Block B clock.
Kojto	99:dbbf35b96557	5787	*/
Kojto	99:dbbf35b96557	5788	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
Kojto	110:165afa46840b	5789	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	5790
Kojto	99:dbbf35b96557	5791	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	5792	/** @brief Macro to configure SAI1 clock source selection.
Kojto	110:165afa46840b	5793	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	5794	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	5795	* the SAI clock.
Kojto	99:dbbf35b96557	5796	* @param __SOURCE__: specifies the SAI1 clock source.
Kojto	99:dbbf35b96557	5797	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5798	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	5799	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	5800	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	5801	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	5802	*/
Kojto	99:dbbf35b96557	5803	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	5804
Kojto	99:dbbf35b96557	5805	/** @brief Macro to Get SAI1 clock source selection.
Kojto	99:dbbf35b96557	5806	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	5807	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	5808	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	5809	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto	99:dbbf35b96557	5810	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	5811	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	5812	*/
Kojto	99:dbbf35b96557	5813	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
Kojto	99:dbbf35b96557	5814
Kojto	99:dbbf35b96557	5815	/** @brief Macro to configure SAI2 clock source selection.
Kojto	99:dbbf35b96557	5816	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	5817	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto	99:dbbf35b96557	5818	* the SAI clock.
Kojto	99:dbbf35b96557	5819	* @param __SOURCE__: specifies the SAI2 clock source.
Kojto	99:dbbf35b96557	5820	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5821	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	5822	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	5823	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto	99:dbbf35b96557	5824	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto	99:dbbf35b96557	5825	*/
Kojto	99:dbbf35b96557	5826	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
bogdanm	92:4fc01daae5a5	5827
Kojto	99:dbbf35b96557	5828	/** @brief Macro to Get SAI2 clock source selection.
Kojto	99:dbbf35b96557	5829	* @note This configuration is only available with STM32F446xx Devices.
Kojto	99:dbbf35b96557	5830	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	5831	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	5832	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto	99:dbbf35b96557	5833	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto	99:dbbf35b96557	5834	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto	99:dbbf35b96557	5835	*/
Kojto	99:dbbf35b96557	5836	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
Kojto	99:dbbf35b96557	5837
Kojto	99:dbbf35b96557	5838	/** @brief Macro to configure I2S APB1 clock source selection.
Kojto	99:dbbf35b96557	5839	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto	99:dbbf35b96557	5840	* @param __SOURCE__: specifies the I2S APB1 clock source.
Kojto	99:dbbf35b96557	5841	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5842	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	99:dbbf35b96557	5843	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	5844	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	5845	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	5846	*/
Kojto	99:dbbf35b96557	5847	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	5848
Kojto	99:dbbf35b96557	5849	/** @brief Macro to Get I2S APB1 clock source selection.
Kojto	99:dbbf35b96557	5850	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	5851	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	99:dbbf35b96557	5852	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	5853	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	5854	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	5855	*/
Kojto	99:dbbf35b96557	5856	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
Kojto	99:dbbf35b96557	5857
Kojto	99:dbbf35b96557	5858	/** @brief Macro to configure I2S APB2 clock source selection.
Kojto	99:dbbf35b96557	5859	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto	99:dbbf35b96557	5860	* @param __SOURCE__: specifies the SAI Block A clock source.
Kojto	99:dbbf35b96557	5861	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5862	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	99:dbbf35b96557	5863	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	5864	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	5865	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	5866	*/
Kojto	99:dbbf35b96557	5867	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
Kojto	99:dbbf35b96557	5868
Kojto	99:dbbf35b96557	5869	/** @brief Macro to Get I2S APB2 clock source selection.
Kojto	99:dbbf35b96557	5870	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	5871	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	99:dbbf35b96557	5872	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	99:dbbf35b96557	5873	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	99:dbbf35b96557	5874	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	99:dbbf35b96557	5875	*/
Kojto	99:dbbf35b96557	5876	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
Kojto	99:dbbf35b96557	5877
Kojto	99:dbbf35b96557	5878	/** @brief Macro to configure the CEC clock.
Kojto	99:dbbf35b96557	5879	* @param __SOURCE__: specifies the CEC clock source.
Kojto	99:dbbf35b96557	5880	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5881	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	99:dbbf35b96557	5882	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	99:dbbf35b96557	5883	*/
Kojto	99:dbbf35b96557	5884	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
bogdanm	89:552587b429a1	5885
Kojto	99:dbbf35b96557	5886	/** @brief Macro to Get the CEC clock.
Kojto	99:dbbf35b96557	5887	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	5888	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
Kojto	99:dbbf35b96557	5889	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	99:dbbf35b96557	5890	*/
Kojto	99:dbbf35b96557	5891	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
Kojto	110:165afa46840b	5892
Kojto	99:dbbf35b96557	5893	/** @brief Macro to configure the FMPI2C1 clock.
Kojto	99:dbbf35b96557	5894	* @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto	99:dbbf35b96557	5895	* This parameter can be one of the following values:
Kojto	110:165afa46840b	5896	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	110:165afa46840b	5897	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	110:165afa46840b	5898	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	99:dbbf35b96557	5899	*/
Kojto	99:dbbf35b96557	5900	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	5901
Kojto	99:dbbf35b96557	5902	/** @brief Macro to Get the FMPI2C1 clock.
Kojto	99:dbbf35b96557	5903	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	5904	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	110:165afa46840b	5905	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	110:165afa46840b	5906	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	99:dbbf35b96557	5907	*/
Kojto	99:dbbf35b96557	5908	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto	99:dbbf35b96557	5909
Kojto	99:dbbf35b96557	5910	/** @brief Macro to configure the CLK48 clock.
Kojto	122:f9eeca106725	5911	* @param __SOURCE__: specifies the CLK48 clock source.
Kojto	99:dbbf35b96557	5912	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	5913	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
Kojto	122:f9eeca106725	5914	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
Kojto	99:dbbf35b96557	5915	*/
Kojto	99:dbbf35b96557	5916	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	5917
Kojto	99:dbbf35b96557	5918	/** @brief Macro to Get the CLK48 clock.
Kojto	99:dbbf35b96557	5919	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	5920	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
Kojto	122:f9eeca106725	5921	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
Kojto	99:dbbf35b96557	5922	*/
Kojto	99:dbbf35b96557	5923	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
Kojto	99:dbbf35b96557	5924
Kojto	99:dbbf35b96557	5925	/** @brief Macro to configure the SDIO clock.
Kojto	99:dbbf35b96557	5926	* @param __SOURCE__: specifies the SDIO clock source.
Kojto	99:dbbf35b96557	5927	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	5928	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
Kojto	99:dbbf35b96557	5929	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	99:dbbf35b96557	5930	*/
Kojto	99:dbbf35b96557	5931	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	5932
Kojto	99:dbbf35b96557	5933	/** @brief Macro to Get the SDIO clock.
Kojto	99:dbbf35b96557	5934	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	5935	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
Kojto	99:dbbf35b96557	5936	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	99:dbbf35b96557	5937	*/
Kojto	99:dbbf35b96557	5938	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
Kojto	99:dbbf35b96557	5939
Kojto	99:dbbf35b96557	5940	/** @brief Macro to configure the SPDIFRX clock.
Kojto	99:dbbf35b96557	5941	* @param __SOURCE__: specifies the SPDIFRX clock source.
Kojto	99:dbbf35b96557	5942	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	5943	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto	99:dbbf35b96557	5944	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto	99:dbbf35b96557	5945	*/
Kojto	99:dbbf35b96557	5946	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
Kojto	99:dbbf35b96557	5947
Kojto	99:dbbf35b96557	5948	/** @brief Macro to Get the SPDIFRX clock.
Kojto	99:dbbf35b96557	5949	* @retval The clock source can be one of the following values:
Kojto	99:dbbf35b96557	5950	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto	99:dbbf35b96557	5951	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto	99:dbbf35b96557	5952	*/
Kojto	99:dbbf35b96557	5953	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
Kojto	99:dbbf35b96557	5954	#endif /* STM32F446xx */
Kojto	110:165afa46840b	5955
Kojto	110:165afa46840b	5956	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	5957
Kojto	110:165afa46840b	5958	/** @brief Macro to configure the CLK48 clock.
Kojto	122:f9eeca106725	5959	* @param __SOURCE__: specifies the CLK48 clock source.
Kojto	110:165afa46840b	5960	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	5961	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
Kojto	122:f9eeca106725	5962	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
Kojto	110:165afa46840b	5963	*/
Kojto	110:165afa46840b	5964	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	5965
Kojto	110:165afa46840b	5966	/** @brief Macro to Get the CLK48 clock.
Kojto	110:165afa46840b	5967	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	5968	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
Kojto	122:f9eeca106725	5969	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
Kojto	110:165afa46840b	5970	*/
Kojto	110:165afa46840b	5971	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
Kojto	110:165afa46840b	5972
Kojto	110:165afa46840b	5973	/** @brief Macro to configure the SDIO clock.
Kojto	110:165afa46840b	5974	* @param __SOURCE__: specifies the SDIO clock source.
Kojto	110:165afa46840b	5975	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	5976	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
Kojto	110:165afa46840b	5977	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	110:165afa46840b	5978	*/
Kojto	110:165afa46840b	5979	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	5980
Kojto	110:165afa46840b	5981	/** @brief Macro to Get the SDIO clock.
Kojto	110:165afa46840b	5982	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	5983	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
Kojto	110:165afa46840b	5984	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	110:165afa46840b	5985	*/
Kojto	110:165afa46840b	5986	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
Kojto	110:165afa46840b	5987
Kojto	110:165afa46840b	5988	/** @brief Macro to configure the DSI clock.
Kojto	110:165afa46840b	5989	* @param __SOURCE__: specifies the DSI clock source.
Kojto	110:165afa46840b	5990	* This parameter can be one of the following values:
Kojto	110:165afa46840b	5991	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
Kojto	110:165afa46840b	5992	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
Kojto	110:165afa46840b	5993	*/
Kojto	110:165afa46840b	5994	#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	5995
Kojto	110:165afa46840b	5996	/** @brief Macro to Get the DSI clock.
Kojto	110:165afa46840b	5997	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	5998	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
Kojto	110:165afa46840b	5999	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
Kojto	110:165afa46840b	6000	*/
Kojto	110:165afa46840b	6001	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
Kojto	110:165afa46840b	6002
Kojto	110:165afa46840b	6003	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	6004
Kojto	122:f9eeca106725	6005	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	122:f9eeca106725	6006	/** @brief Macro to configure the DFSDM1 clock.
Kojto	122:f9eeca106725	6007	* @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
Kojto	122:f9eeca106725	6008	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6009	* @arg RCC_DFSDM1CLKSOURCE_APB2: APB2 clock used as kernel clock.
Kojto	122:f9eeca106725	6010	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
Kojto	122:f9eeca106725	6011	* @retval None
Kojto	122:f9eeca106725	6012	*/
Kojto	122:f9eeca106725	6013	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
Kojto	122:f9eeca106725	6014
Kojto	122:f9eeca106725	6015	/** @brief Macro to get the DFSDM1 clock source.
Kojto	122:f9eeca106725	6016	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6017	* @arg RCC_DFSDM1CLKSOURCE_APB2: APB2 clock used as kernel clock.
Kojto	122:f9eeca106725	6018	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
Kojto	122:f9eeca106725	6019	*/
Kojto	122:f9eeca106725	6020	#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
Kojto	122:f9eeca106725	6021
Kojto	122:f9eeca106725	6022	/** @brief Macro to configure DFSDM1 Audio clock source selection.
Kojto	122:f9eeca106725	6023	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx Devices.
Kojto	122:f9eeca106725	6024	* @param __SOURCE__: specifies the DFSDM1 Audio clock source.
Kojto	122:f9eeca106725	6025	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6026	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: CK_I2S_APB1 selected as audio clock
Kojto	122:f9eeca106725	6027	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: CK_I2S_APB2 selected as audio clock
Kojto	122:f9eeca106725	6028	*/
Kojto	122:f9eeca106725	6029	#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
Kojto	122:f9eeca106725	6030
Kojto	122:f9eeca106725	6031	/** @brief Macro to Get DFSDM1 Audio clock source selection.
Kojto	122:f9eeca106725	6032	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx Devices.
Kojto	122:f9eeca106725	6033	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6034	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: CK_I2S_APB1 selected as audio clock
Kojto	122:f9eeca106725	6035	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: CK_I2S_APB2 selected as audio clock
Kojto	122:f9eeca106725	6036	*/
Kojto	122:f9eeca106725	6037	#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
Kojto	122:f9eeca106725	6038
Kojto	122:f9eeca106725	6039	/** @brief Macro to configure I2S APB1 clock source selection.
Kojto	122:f9eeca106725	6040	* @param __SOURCE__: specifies the I2S APB1 clock source.
Kojto	122:f9eeca106725	6041	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6042	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
Kojto	122:f9eeca106725	6043	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	122:f9eeca106725	6044	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
Kojto	122:f9eeca106725	6045	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	122:f9eeca106725	6046	*/
Kojto	122:f9eeca106725	6047	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
Kojto	122:f9eeca106725	6048
Kojto	122:f9eeca106725	6049	/** @brief Macro to Get I2S APB1 clock source selection.
Kojto	122:f9eeca106725	6050	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6051	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
Kojto	122:f9eeca106725	6052	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	122:f9eeca106725	6053	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
Kojto	122:f9eeca106725	6054	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	122:f9eeca106725	6055	*/
Kojto	122:f9eeca106725	6056	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
Kojto	122:f9eeca106725	6057
Kojto	122:f9eeca106725	6058	/** @brief Macro to configure I2S APB2 clock source selection.
Kojto	122:f9eeca106725	6059	* @param __SOURCE__: specifies the I2S APB2 clock source.
Kojto	122:f9eeca106725	6060	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6061	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
Kojto	122:f9eeca106725	6062	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	122:f9eeca106725	6063	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
Kojto	122:f9eeca106725	6064	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	122:f9eeca106725	6065	*/
Kojto	122:f9eeca106725	6066	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
Kojto	122:f9eeca106725	6067
Kojto	122:f9eeca106725	6068	/** @brief Macro to Get I2S APB2 clock source selection.
Kojto	122:f9eeca106725	6069	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6070	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
Kojto	122:f9eeca106725	6071	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	122:f9eeca106725	6072	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
Kojto	122:f9eeca106725	6073	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	122:f9eeca106725	6074	*/
Kojto	122:f9eeca106725	6075	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
Kojto	122:f9eeca106725	6076
Kojto	122:f9eeca106725	6077	/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK).
Kojto	122:f9eeca106725	6078	* @note This macro must be called before enabling the I2S APB clock.
Kojto	122:f9eeca106725	6079	* @param __SOURCE__: specifies the I2S clock source.
Kojto	122:f9eeca106725	6080	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6081	* @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	122:f9eeca106725	6082	* @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	122:f9eeca106725	6083	* used as I2S clock source.
Kojto	122:f9eeca106725	6084	*/
Kojto	122:f9eeca106725	6085	#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
Kojto	122:f9eeca106725	6086
Kojto	122:f9eeca106725	6087	/** @brief Macro to configure the FMPI2C1 clock.
Kojto	122:f9eeca106725	6088	* @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto	122:f9eeca106725	6089	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6090	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	122:f9eeca106725	6091	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	122:f9eeca106725	6092	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	122:f9eeca106725	6093	*/
Kojto	122:f9eeca106725	6094	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto	122:f9eeca106725	6095
Kojto	122:f9eeca106725	6096	/** @brief Macro to Get the FMPI2C1 clock.
Kojto	122:f9eeca106725	6097	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6098	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	122:f9eeca106725	6099	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	122:f9eeca106725	6100	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	122:f9eeca106725	6101	*/
Kojto	122:f9eeca106725	6102	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto	122:f9eeca106725	6103
Kojto	122:f9eeca106725	6104	/** @brief Macro to configure the CLK48 clock.
Kojto	122:f9eeca106725	6105	* @param __SOURCE__: specifies the CLK48 clock source.
Kojto	122:f9eeca106725	6106	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6107	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
Kojto	122:f9eeca106725	6108	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
Kojto	122:f9eeca106725	6109	*/
Kojto	122:f9eeca106725	6110	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto	122:f9eeca106725	6111
Kojto	122:f9eeca106725	6112	/** @brief Macro to Get the CLK48 clock.
Kojto	122:f9eeca106725	6113	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6114	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
Kojto	122:f9eeca106725	6115	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
Kojto	122:f9eeca106725	6116	*/
Kojto	122:f9eeca106725	6117	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
Kojto	122:f9eeca106725	6118
Kojto	122:f9eeca106725	6119	/** @brief Macro to configure the SDIO clock.
Kojto	122:f9eeca106725	6120	* @param __SOURCE__: specifies the SDIO clock source.
Kojto	122:f9eeca106725	6121	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	6122	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
Kojto	122:f9eeca106725	6123	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	122:f9eeca106725	6124	*/
Kojto	122:f9eeca106725	6125	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto	122:f9eeca106725	6126
Kojto	122:f9eeca106725	6127	/** @brief Macro to Get the SDIO clock.
Kojto	122:f9eeca106725	6128	* @retval The clock source can be one of the following values:
Kojto	122:f9eeca106725	6129	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
Kojto	122:f9eeca106725	6130	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	122:f9eeca106725	6131	*/
Kojto	122:f9eeca106725	6132	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
Kojto	122:f9eeca106725	6133
Kojto	122:f9eeca106725	6134	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	122:f9eeca106725	6135
Kojto	110:165afa46840b	6136	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	6137	/** @brief Macro to configure I2S clock source selection.
Kojto	110:165afa46840b	6138	* @param __SOURCE__: specifies the I2S clock source.
Kojto	110:165afa46840b	6139	* This parameter can be one of the following values:
Kojto	110:165afa46840b	6140	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
Kojto	110:165afa46840b	6141	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	110:165afa46840b	6142	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
Kojto	110:165afa46840b	6143	*/
Kojto	110:165afa46840b	6144	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
Kojto	110:165afa46840b	6145
Kojto	110:165afa46840b	6146	/** @brief Macro to Get I2S clock source selection.
Kojto	110:165afa46840b	6147	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	6148	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
Kojto	110:165afa46840b	6149	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	110:165afa46840b	6150	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
Kojto	110:165afa46840b	6151	*/
Kojto	110:165afa46840b	6152	#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
Kojto	110:165afa46840b	6153
Kojto	110:165afa46840b	6154	/** @brief Macro to configure the FMPI2C1 clock.
Kojto	110:165afa46840b	6155	* @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto	110:165afa46840b	6156	* This parameter can be one of the following values:
Kojto	110:165afa46840b	6157	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	110:165afa46840b	6158	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	110:165afa46840b	6159	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	110:165afa46840b	6160	*/
Kojto	110:165afa46840b	6161	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	6162
Kojto	110:165afa46840b	6163	/** @brief Macro to Get the FMPI2C1 clock.
Kojto	110:165afa46840b	6164	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	6165	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	110:165afa46840b	6166	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	110:165afa46840b	6167	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	110:165afa46840b	6168	*/
Kojto	110:165afa46840b	6169	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto	110:165afa46840b	6170
Kojto	110:165afa46840b	6171	/** @brief Macro to configure the LPTIM1 clock.
Kojto	110:165afa46840b	6172	* @param __SOURCE__: specifies the LPTIM1 clock source.
Kojto	110:165afa46840b	6173	* This parameter can be one of the following values:
Kojto	110:165afa46840b	6174	* @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
Kojto	110:165afa46840b	6175	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
Kojto	110:165afa46840b	6176	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto	110:165afa46840b	6177	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto	110:165afa46840b	6178	*/
Kojto	110:165afa46840b	6179	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
Kojto	110:165afa46840b	6180
Kojto	110:165afa46840b	6181	/** @brief Macro to Get the LPTIM1 clock.
Kojto	110:165afa46840b	6182	* @retval The clock source can be one of the following values:
Kojto	110:165afa46840b	6183	* @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
Kojto	110:165afa46840b	6184	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
Kojto	110:165afa46840b	6185	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto	110:165afa46840b	6186	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto	110:165afa46840b	6187	*/
Kojto	110:165afa46840b	6188	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
Kojto	110:165afa46840b	6189	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	6190
Kojto	110:165afa46840b	6191	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	6192	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
Kojto	110:165afa46840b	6193	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
Kojto	122:f9eeca106725	6194	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
Kojto	122:f9eeca106725	6195	defined(STM32F412Cx)
bogdanm	89:552587b429a1	6196	/** @brief Macro to configure the Timers clocks prescalers
bogdanm	89:552587b429a1	6197	* @note This feature is only available with STM32F429x/439x Devices.
bogdanm	89:552587b429a1	6198	* @param __PRESC__ : specifies the Timers clocks prescalers selection
bogdanm	89:552587b429a1	6199	* This parameter can be one of the following values:
bogdanm	89:552587b429a1	6200	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
bogdanm	89:552587b429a1	6201	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
bogdanm	89:552587b429a1	6202	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
bogdanm	89:552587b429a1	6203	* division by 4 or more.
bogdanm	89:552587b429a1	6204	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
bogdanm	89:552587b429a1	6205	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
bogdanm	89:552587b429a1	6206	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
bogdanm	89:552587b429a1	6207	* to division by 8 or more.
bogdanm	89:552587b429a1	6208	*/
Kojto	99:dbbf35b96557	6209	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
bogdanm	92:4fc01daae5a5	6210
Kojto	110:165afa46840b	6211	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\|\
Kojto	122:f9eeca106725	6212	STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	110:165afa46840b	6213
Kojto	110:165afa46840b	6214	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	6215
Kojto	110:165afa46840b	6216	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	89:552587b429a1	6217	/** @brief Enable PLLSAI_RDY interrupt.
bogdanm	89:552587b429a1	6218	*/
bogdanm	89:552587b429a1	6219	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
bogdanm	89:552587b429a1	6220
bogdanm	89:552587b429a1	6221	/** @brief Disable PLLSAI_RDY interrupt.
bogdanm	89:552587b429a1	6222	*/
bogdanm	89:552587b429a1	6223	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
bogdanm	89:552587b429a1	6224
bogdanm	89:552587b429a1	6225	/** @brief Clear the PLLSAI RDY interrupt pending bits.
bogdanm	89:552587b429a1	6226	*/
bogdanm	89:552587b429a1	6227	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
bogdanm	89:552587b429a1	6228
bogdanm	89:552587b429a1	6229	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
bogdanm	89:552587b429a1	6230	* @retval The new state (TRUE or FALSE).
bogdanm	89:552587b429a1	6231	*/
bogdanm	89:552587b429a1	6232	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
bogdanm	89:552587b429a1	6233
bogdanm	89:552587b429a1	6234	/** @brief Check PLLSAI RDY flag is set or not.
bogdanm	89:552587b429a1	6235	* @retval The new state (TRUE or FALSE).
bogdanm	89:552587b429a1	6236	*/
bogdanm	89:552587b429a1	6237	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
bogdanm	89:552587b429a1	6238
Kojto	110:165afa46840b	6239	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	6240
Kojto	110:165afa46840b	6241	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	122:f9eeca106725	6242	/** @brief Macros to enable or disable the RCC MCO1 feature.
Kojto	110:165afa46840b	6243	*/
Kojto	110:165afa46840b	6244	#define __HAL_RCC_MCO1_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = ENABLE)
Kojto	110:165afa46840b	6245	#define __HAL_RCC_MCO1_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = DISABLE)
Kojto	122:f9eeca106725	6246
Kojto	122:f9eeca106725	6247	/** @brief Macros to enable or disable the RCC MCO2 feature.
Kojto	110:165afa46840b	6248	*/
Kojto	110:165afa46840b	6249	#define __HAL_RCC_MCO2_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = ENABLE)
Kojto	110:165afa46840b	6250	#define __HAL_RCC_MCO2_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = DISABLE)
Kojto	122:f9eeca106725	6251
Kojto	110:165afa46840b	6252	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	6253
Kojto	99:dbbf35b96557	6254	/**
Kojto	99:dbbf35b96557	6255	* @}
Kojto	99:dbbf35b96557	6256	*/
bogdanm	89:552587b429a1	6257
bogdanm	89:552587b429a1	6258	/* Exported functions --------------------------------------------------------*/
Kojto	99:dbbf35b96557	6259	/** @addtogroup RCCEx_Exported_Functions
Kojto	99:dbbf35b96557	6260	* @{
Kojto	99:dbbf35b96557	6261	*/
Kojto	99:dbbf35b96557	6262
Kojto	99:dbbf35b96557	6263	/** @addtogroup RCCEx_Exported_Functions_Group1
Kojto	99:dbbf35b96557	6264	* @{
Kojto	99:dbbf35b96557	6265	*/
bogdanm	89:552587b429a1	6266	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	89:552587b429a1	6267	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	89:552587b429a1	6268
Kojto	99:dbbf35b96557	6269	#if defined(STM32F446xx)
Kojto	99:dbbf35b96557	6270	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto	99:dbbf35b96557	6271	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	6272
Kojto	110:165afa46840b	6273	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
Kojto	122:f9eeca106725	6274	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
Kojto	122:f9eeca106725	6275	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
bogdanm	92:4fc01daae5a5	6276	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
Kojto	122:f9eeca106725	6277	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
bogdanm	89:552587b429a1	6278	/**
bogdanm	89:552587b429a1	6279	* @}
bogdanm	89:552587b429a1	6280	*/
bogdanm	89:552587b429a1	6281
bogdanm	89:552587b429a1	6282	/**
bogdanm	89:552587b429a1	6283	* @}
bogdanm	89:552587b429a1	6284	*/
Kojto	99:dbbf35b96557	6285	/* Private types -------------------------------------------------------------*/
Kojto	99:dbbf35b96557	6286	/* Private variables ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	6287	/* Private constants ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	6288	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
Kojto	99:dbbf35b96557	6289	* @{
Kojto	99:dbbf35b96557	6290	*/
Kojto	99:dbbf35b96557	6291
Kojto	99:dbbf35b96557	6292	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto	99:dbbf35b96557	6293	* @brief RCC registers bit address in the alias region
Kojto	99:dbbf35b96557	6294	* @{
Kojto	99:dbbf35b96557	6295	*/
Kojto	99:dbbf35b96557	6296	/* --- CR Register ---*/
Kojto	110:165afa46840b	6297	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	6298	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	6299	/* Alias word address of PLLSAION bit */
Kojto	99:dbbf35b96557	6300	#define RCC_PLLSAION_BIT_NUMBER 0x1C
Kojto	99:dbbf35b96557	6301	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
Kojto	99:dbbf35b96557	6302
Kojto	122:f9eeca106725	6303	#define PLLSAI_TIMEOUT_VALUE ((uint32_t)2) /* Timeout value fixed to 2 ms */
Kojto	110:165afa46840b	6304	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	6305
Kojto	110:165afa46840b	6306	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	6307	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	6308	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	122:f9eeca106725	6309	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
Kojto	122:f9eeca106725	6310	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	110:165afa46840b	6311	/* Alias word address of PLLI2SON bit */
Kojto	110:165afa46840b	6312	#define RCC_PLLI2SON_BIT_NUMBER 0x1A
Kojto	110:165afa46840b	6313	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
Kojto	110:165afa46840b	6314	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	122:f9eeca106725	6315	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
Kojto	122:f9eeca106725	6316	STM32F412Rx \|\| STM32F412Cx */
Kojto	110:165afa46840b	6317
Kojto	99:dbbf35b96557	6318	/* --- DCKCFGR Register ---*/
Kojto	110:165afa46840b	6319	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	122:f9eeca106725	6320	defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F401xC) \|\|\
Kojto	122:f9eeca106725	6321	defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
Kojto	122:f9eeca106725	6322	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
Kojto	122:f9eeca106725	6323	defined(STM32F412Cx)
Kojto	99:dbbf35b96557	6324	/* Alias word address of TIMPRE bit */
Kojto	99:dbbf35b96557	6325	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
Kojto	99:dbbf35b96557	6326	#define RCC_TIMPRE_BIT_NUMBER 0x18
Kojto	99:dbbf35b96557	6327	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
Kojto	122:f9eeca106725	6328	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F410xx \|\| STM32F401xC \|\|\
Kojto	122:f9eeca106725	6329	STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
Kojto	122:f9eeca106725	6330	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	110:165afa46840b	6331
Kojto	110:165afa46840b	6332	/* --- CFGR Register ---*/
Kojto	122:f9eeca106725	6333	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
Kojto	110:165afa46840b	6334	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	6335	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	6336	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	122:f9eeca106725	6337	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	110:165afa46840b	6338	/* Alias word address of I2SSRC bit */
Kojto	110:165afa46840b	6339	#define RCC_I2SSRC_BIT_NUMBER 0x17
Kojto	110:165afa46840b	6340	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
Kojto	110:165afa46840b	6341
Kojto	122:f9eeca106725	6342	#define PLLI2S_TIMEOUT_VALUE ((uint32_t)2) /* Timeout value fixed to 2 ms */
Kojto	110:165afa46840b	6343	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	122:f9eeca106725	6344	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	6345
Kojto	122:f9eeca106725	6346	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	122:f9eeca106725	6347	/* --- PLLI2SCFGR Register ---*/
Kojto	122:f9eeca106725	6348	#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U)
Kojto	122:f9eeca106725	6349	/* Alias word address of PLLI2SSRC bit */
Kojto	122:f9eeca106725	6350	#define RCC_PLLI2SSRC_BIT_NUMBER 0x16
Kojto	122:f9eeca106725	6351	#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32) + (RCC_PLLI2SSRC_BIT_NUMBER * 4))
Kojto	122:f9eeca106725	6352
Kojto	122:f9eeca106725	6353	#define PLLI2S_TIMEOUT_VALUE ((uint32_t)2) /* Timeout value fixed to 2 ms */
Kojto	122:f9eeca106725	6354	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	110:165afa46840b	6355
Kojto	110:165afa46840b	6356	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	6357	/* Alias word address of MCO1EN bit */
Kojto	110:165afa46840b	6358	#define RCC_MCO1EN_BIT_NUMBER 0x8
Kojto	110:165afa46840b	6359	#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
Kojto	110:165afa46840b	6360
Kojto	110:165afa46840b	6361	/* Alias word address of MCO2EN bit */
Kojto	110:165afa46840b	6362	#define RCC_MCO2EN_BIT_NUMBER 0x9
Kojto	110:165afa46840b	6363	#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
Kojto	110:165afa46840b	6364	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	6365
Kojto	122:f9eeca106725	6366	#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
Kojto	99:dbbf35b96557	6367	/**
Kojto	99:dbbf35b96557	6368	* @}
Kojto	99:dbbf35b96557	6369	*/
Kojto	99:dbbf35b96557	6370
Kojto	99:dbbf35b96557	6371	/**
Kojto	99:dbbf35b96557	6372	* @}
Kojto	99:dbbf35b96557	6373	*/
Kojto	99:dbbf35b96557	6374
Kojto	99:dbbf35b96557	6375	/* Private macros ------------------------------------------------------------*/
Kojto	122:f9eeca106725	6376	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
Kojto	99:dbbf35b96557	6377	* @{
Kojto	99:dbbf35b96557	6378	*/
Kojto	99:dbbf35b96557	6379	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto	99:dbbf35b96557	6380	* @{
Kojto	99:dbbf35b96557	6381	*/
Kojto	122:f9eeca106725	6382	#if defined(STM32F411xE)
Kojto	122:f9eeca106725	6383	#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
Kojto	122:f9eeca106725	6384	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
Kojto	122:f9eeca106725	6385	#else /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\|
Kojto	122:f9eeca106725	6386	STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410Tx \|\| STM32F410Cx \|\|
Kojto	122:f9eeca106725	6387	STM32F410Rx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Cx \|\| STM32F412Rx \|\|
Kojto	122:f9eeca106725	6388	STM32F412Vx \|\| STM32F412Zx */
Kojto	122:f9eeca106725	6389	#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
Kojto	122:f9eeca106725	6390	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
Kojto	122:f9eeca106725	6391	#endif /* STM32F411xE */
Kojto	122:f9eeca106725	6392
Kojto	99:dbbf35b96557	6393	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
Kojto	122:f9eeca106725	6394	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
Kojto	99:dbbf35b96557	6395	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	6396
Kojto	122:f9eeca106725	6397	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	122:f9eeca106725	6398	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
Kojto	122:f9eeca106725	6399	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
Kojto	122:f9eeca106725	6400
Kojto	122:f9eeca106725	6401	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	122:f9eeca106725	6402	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
Kojto	122:f9eeca106725	6403	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	99:dbbf35b96557	6404
Kojto	110:165afa46840b	6405	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	122:f9eeca106725	6406	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
Kojto	110:165afa46840b	6407	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	110:165afa46840b	6408
Kojto	99:dbbf35b96557	6409	#if defined(STM32F446xx)
Kojto	122:f9eeca106725	6410	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
Kojto	99:dbbf35b96557	6411	#endif /* STM32F446xx */
Kojto	99:dbbf35b96557	6412
Kojto	122:f9eeca106725	6413	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	6414	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
Kojto	122:f9eeca106725	6415	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	122:f9eeca106725	6416
Kojto	122:f9eeca106725	6417	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	122:f9eeca106725	6418	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
Kojto	122:f9eeca106725	6419	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	122:f9eeca106725	6420
Kojto	122:f9eeca106725	6421	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
Kojto	99:dbbf35b96557	6422
Kojto	110:165afa46840b	6423	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	6424	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	6425	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
Kojto	122:f9eeca106725	6426
Kojto	122:f9eeca106725	6427	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
Kojto	122:f9eeca106725	6428
Kojto	122:f9eeca106725	6429	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
Kojto	122:f9eeca106725	6430
Kojto	122:f9eeca106725	6431	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
Kojto	122:f9eeca106725	6432
Kojto	122:f9eeca106725	6433	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
Kojto	122:f9eeca106725	6434
Kojto	122:f9eeca106725	6435	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
Kojto	99:dbbf35b96557	6436
Kojto	99:dbbf35b96557	6437	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
Kojto	99:dbbf35b96557	6438	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
Kojto	99:dbbf35b96557	6439	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
Kojto	99:dbbf35b96557	6440	((VALUE) == RCC_PLLSAIDIVR_16))
Kojto	110:165afa46840b	6441	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	6442
Kojto	122:f9eeca106725	6443	#if defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
Kojto	122:f9eeca106725	6444	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	122:f9eeca106725	6445	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63U)
Kojto	99:dbbf35b96557	6446
Kojto	99:dbbf35b96557	6447	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	99:dbbf35b96557	6448	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	122:f9eeca106725	6449	#endif /* STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	110:165afa46840b	6450
Kojto	110:165afa46840b	6451	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	122:f9eeca106725	6452	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
Kojto	110:165afa46840b	6453
Kojto	110:165afa46840b	6454	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	110:165afa46840b	6455	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	110:165afa46840b	6456
Kojto	110:165afa46840b	6457	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
Kojto	110:165afa46840b	6458	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
Kojto	110:165afa46840b	6459	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto	110:165afa46840b	6460
Kojto	110:165afa46840b	6461	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) \|\|\
Kojto	110:165afa46840b	6462	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
Kojto	110:165afa46840b	6463	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
Kojto	110:165afa46840b	6464	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
Kojto	110:165afa46840b	6465
Kojto	110:165afa46840b	6466	#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) \|\|\
Kojto	110:165afa46840b	6467	((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) \|\|\
Kojto	110:165afa46840b	6468	((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
Kojto	110:165afa46840b	6469	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	6470
Kojto	99:dbbf35b96557	6471	#if defined(STM32F446xx)
Kojto	122:f9eeca106725	6472	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
bogdanm	89:552587b429a1	6473
Kojto	99:dbbf35b96557	6474	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
Kojto	99:dbbf35b96557	6475	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
Kojto	99:dbbf35b96557	6476	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
Kojto	99:dbbf35b96557	6477	((VALUE) == RCC_PLLI2SP_DIV8))
Kojto	99:dbbf35b96557	6478
Kojto	122:f9eeca106725	6479	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U)
Kojto	99:dbbf35b96557	6480
Kojto	99:dbbf35b96557	6481	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
Kojto	99:dbbf35b96557	6482	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
Kojto	99:dbbf35b96557	6483	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
Kojto	99:dbbf35b96557	6484	((VALUE) == RCC_PLLSAIP_DIV8))
Kojto	99:dbbf35b96557	6485
Kojto	99:dbbf35b96557	6486	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
Kojto	99:dbbf35b96557	6487	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	6488	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	6489	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
Kojto	99:dbbf35b96557	6490
Kojto	99:dbbf35b96557	6491	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
Kojto	99:dbbf35b96557	6492	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	6493	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	6494	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
Kojto	99:dbbf35b96557	6495
Kojto	99:dbbf35b96557	6496	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	6497	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
Kojto	99:dbbf35b96557	6498	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	6499	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
Kojto	99:dbbf35b96557	6500
Kojto	99:dbbf35b96557	6501	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
Kojto	99:dbbf35b96557	6502	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
Kojto	99:dbbf35b96557	6503	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	6504	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
Kojto	99:dbbf35b96557	6505
Kojto	99:dbbf35b96557	6506	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
Kojto	99:dbbf35b96557	6507	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
Kojto	99:dbbf35b96557	6508	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto	99:dbbf35b96557	6509
Kojto	99:dbbf35b96557	6510	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
Kojto	99:dbbf35b96557	6511	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	99:dbbf35b96557	6512
Kojto	122:f9eeca106725	6513	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
Kojto	122:f9eeca106725	6514	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
Kojto	122:f9eeca106725	6515
Kojto	122:f9eeca106725	6516	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
Kojto	99:dbbf35b96557	6517	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto	99:dbbf35b96557	6518
Kojto	110:165afa46840b	6519	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
Kojto	99:dbbf35b96557	6520	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
Kojto	110:165afa46840b	6521	#endif /* STM32F446xx */
Kojto	110:165afa46840b	6522
Kojto	110:165afa46840b	6523	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	122:f9eeca106725	6524	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
Kojto	110:165afa46840b	6525
Kojto	110:165afa46840b	6526	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
Kojto	110:165afa46840b	6527	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
Kojto	110:165afa46840b	6528	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
Kojto	110:165afa46840b	6529	((VALUE) == RCC_PLLSAIP_DIV8))
Kojto	110:165afa46840b	6530
Kojto	122:f9eeca106725	6531	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
Kojto	122:f9eeca106725	6532	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
Kojto	122:f9eeca106725	6533
Kojto	122:f9eeca106725	6534	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
Kojto	110:165afa46840b	6535	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto	110:165afa46840b	6536
Kojto	110:165afa46840b	6537	#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) \|\|\
Kojto	110:165afa46840b	6538	((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
Kojto	110:165afa46840b	6539
Kojto	110:165afa46840b	6540	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	110:165afa46840b	6541	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	110:165afa46840b	6542	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	110:165afa46840b	6543
Kojto	122:f9eeca106725	6544	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
Kojto	122:f9eeca106725	6545	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
Kojto	122:f9eeca106725	6546
Kojto	122:f9eeca106725	6547	#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) \|\| \
Kojto	122:f9eeca106725	6548	((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
Kojto	122:f9eeca106725	6549
Kojto	122:f9eeca106725	6550	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
Kojto	122:f9eeca106725	6551	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
Kojto	122:f9eeca106725	6552	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
Kojto	122:f9eeca106725	6553	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
Kojto	122:f9eeca106725	6554
Kojto	122:f9eeca106725	6555	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
Kojto	122:f9eeca106725	6556	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
Kojto	122:f9eeca106725	6557	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
Kojto	122:f9eeca106725	6558	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
Kojto	122:f9eeca106725	6559
Kojto	122:f9eeca106725	6560	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
Kojto	122:f9eeca106725	6561	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
Kojto	122:f9eeca106725	6562	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto	122:f9eeca106725	6563
Kojto	122:f9eeca106725	6564	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
Kojto	122:f9eeca106725	6565	((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
Kojto	122:f9eeca106725	6566
Kojto	122:f9eeca106725	6567	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
Kojto	122:f9eeca106725	6568	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto	122:f9eeca106725	6569
Kojto	122:f9eeca106725	6570	#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_APB2) \|\| \
Kojto	122:f9eeca106725	6571	((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
Kojto	122:f9eeca106725	6572
Kojto	122:f9eeca106725	6573	#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) \|\| \
Kojto	122:f9eeca106725	6574	((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
Kojto	122:f9eeca106725	6575
Kojto	122:f9eeca106725	6576	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
Kojto	122:f9eeca106725	6577
Kojto	110:165afa46840b	6578	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	110:165afa46840b	6579	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	110:165afa46840b	6580	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	122:f9eeca106725	6581	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
Kojto	122:f9eeca106725	6582	defined(STM32F412Rx)
Kojto	110:165afa46840b	6583
Kojto	110:165afa46840b	6584	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
Kojto	110:165afa46840b	6585	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto	110:165afa46840b	6586
Kojto	110:165afa46840b	6587	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	122:f9eeca106725	6588	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| \
Kojto	122:f9eeca106725	6589	STM32F412Rx */
Kojto	110:165afa46840b	6590
Kojto	110:165afa46840b	6591	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	110:165afa46840b	6592	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)\|\| \
Kojto	110:165afa46840b	6593	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto	110:165afa46840b	6594	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	99:dbbf35b96557	6595	/**
Kojto	99:dbbf35b96557	6596	* @}
Kojto	99:dbbf35b96557	6597	*/
Kojto	99:dbbf35b96557	6598
Kojto	99:dbbf35b96557	6599	/**
Kojto	99:dbbf35b96557	6600	* @}
Kojto	99:dbbf35b96557	6601	*/
Kojto	99:dbbf35b96557	6602
Kojto	99:dbbf35b96557	6603	/**
Kojto	99:dbbf35b96557	6604	* @}
Kojto	99:dbbf35b96557	6605	*/
Kojto	99:dbbf35b96557	6606
Kojto	99:dbbf35b96557	6607	/**
Kojto	99:dbbf35b96557	6608	* @}
Kojto	99:dbbf35b96557	6609	*/
bogdanm	89:552587b429a1	6610	#ifdef __cplusplus
bogdanm	89:552587b429a1	6611	}
bogdanm	89:552587b429a1	6612	#endif
bogdanm	89:552587b429a1	6613
bogdanm	89:552587b429a1	6614	#endif /* __STM32F4xx_HAL_RCC_EX_H */
bogdanm	89:552587b429a1	6615
bogdanm	89:552587b429a1	6616	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/