mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F410RB/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
128:9bcdf88f62b0
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_eth.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.0
Kojto 122:f9eeca106725 6 * @date 06-May-2016
bogdanm 92:4fc01daae5a5 7 * @brief Header file of ETH HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_ETH_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_ETH_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
Kojto 110:165afa46840b 46 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
Kojto 110:165afa46840b 47 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
bogdanm 92:4fc01daae5a5 48 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 49 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 50
bogdanm 92:4fc01daae5a5 51 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 52 * @{
bogdanm 92:4fc01daae5a5 53 */
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 /** @addtogroup ETH
bogdanm 92:4fc01daae5a5 56 * @{
bogdanm 92:4fc01daae5a5 57 */
Kojto 99:dbbf35b96557 58
Kojto 99:dbbf35b96557 59 /** @addtogroup ETH_Private_Macros
Kojto 99:dbbf35b96557 60 * @{
Kojto 99:dbbf35b96557 61 */
Kojto 122:f9eeca106725 62 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
Kojto 99:dbbf35b96557 63 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
Kojto 99:dbbf35b96557 64 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
Kojto 99:dbbf35b96557 65 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
Kojto 99:dbbf35b96557 66 ((SPEED) == ETH_SPEED_100M))
Kojto 99:dbbf35b96557 67 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
Kojto 99:dbbf35b96557 68 ((MODE) == ETH_MODE_HALFDUPLEX))
Kojto 99:dbbf35b96557 69 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
Kojto 99:dbbf35b96557 70 ((MODE) == ETH_RXINTERRUPT_MODE))
Kojto 99:dbbf35b96557 71 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
Kojto 99:dbbf35b96557 72 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
Kojto 99:dbbf35b96557 73 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
Kojto 99:dbbf35b96557 74 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
Kojto 99:dbbf35b96557 75 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
Kojto 99:dbbf35b96557 76 ((CMD) == ETH_WATCHDOG_DISABLE))
Kojto 99:dbbf35b96557 77 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
Kojto 99:dbbf35b96557 78 ((CMD) == ETH_JABBER_DISABLE))
Kojto 99:dbbf35b96557 79 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
Kojto 99:dbbf35b96557 80 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
Kojto 99:dbbf35b96557 81 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
Kojto 99:dbbf35b96557 82 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
Kojto 99:dbbf35b96557 83 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
Kojto 99:dbbf35b96557 84 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
Kojto 99:dbbf35b96557 85 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
Kojto 99:dbbf35b96557 86 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
Kojto 99:dbbf35b96557 87 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
Kojto 99:dbbf35b96557 88 ((CMD) == ETH_CARRIERSENCE_DISABLE))
Kojto 99:dbbf35b96557 89 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
Kojto 99:dbbf35b96557 90 ((CMD) == ETH_RECEIVEOWN_DISABLE))
Kojto 99:dbbf35b96557 91 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
Kojto 99:dbbf35b96557 92 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
Kojto 99:dbbf35b96557 93 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
Kojto 99:dbbf35b96557 94 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
Kojto 99:dbbf35b96557 95 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
Kojto 99:dbbf35b96557 96 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
Kojto 99:dbbf35b96557 97 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
Kojto 99:dbbf35b96557 98 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
Kojto 99:dbbf35b96557 99 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
Kojto 99:dbbf35b96557 100 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
Kojto 99:dbbf35b96557 101 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
Kojto 99:dbbf35b96557 102 ((LIMIT) == ETH_BACKOFFLIMIT_1))
Kojto 99:dbbf35b96557 103 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
Kojto 99:dbbf35b96557 104 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
Kojto 99:dbbf35b96557 105 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
Kojto 99:dbbf35b96557 106 ((CMD) == ETH_RECEIVEAll_DISABLE))
Kojto 99:dbbf35b96557 107 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
Kojto 99:dbbf35b96557 108 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
Kojto 99:dbbf35b96557 109 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
Kojto 99:dbbf35b96557 110 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
Kojto 99:dbbf35b96557 111 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
Kojto 99:dbbf35b96557 112 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
Kojto 99:dbbf35b96557 113 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
Kojto 99:dbbf35b96557 114 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
Kojto 99:dbbf35b96557 115 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
Kojto 99:dbbf35b96557 116 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
Kojto 99:dbbf35b96557 117 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
Kojto 99:dbbf35b96557 118 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
Kojto 99:dbbf35b96557 119 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
Kojto 99:dbbf35b96557 120 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
Kojto 99:dbbf35b96557 121 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
Kojto 99:dbbf35b96557 122 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
Kojto 99:dbbf35b96557 123 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
Kojto 99:dbbf35b96557 124 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
Kojto 99:dbbf35b96557 125 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
Kojto 122:f9eeca106725 126 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
Kojto 99:dbbf35b96557 127 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
Kojto 99:dbbf35b96557 128 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
Kojto 99:dbbf35b96557 129 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
Kojto 99:dbbf35b96557 130 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
Kojto 99:dbbf35b96557 131 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
Kojto 99:dbbf35b96557 132 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
Kojto 99:dbbf35b96557 133 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
Kojto 99:dbbf35b96557 134 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
Kojto 99:dbbf35b96557 135 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
Kojto 99:dbbf35b96557 136 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
Kojto 99:dbbf35b96557 137 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
Kojto 99:dbbf35b96557 138 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
Kojto 99:dbbf35b96557 139 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
Kojto 99:dbbf35b96557 140 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
Kojto 122:f9eeca106725 141 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
Kojto 99:dbbf35b96557 142 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
Kojto 99:dbbf35b96557 143 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
Kojto 99:dbbf35b96557 144 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
Kojto 99:dbbf35b96557 145 ((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto 99:dbbf35b96557 146 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
Kojto 99:dbbf35b96557 147 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
Kojto 99:dbbf35b96557 148 ((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto 99:dbbf35b96557 149 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
Kojto 99:dbbf35b96557 150 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
Kojto 99:dbbf35b96557 151 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
Kojto 99:dbbf35b96557 152 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
Kojto 99:dbbf35b96557 153 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
Kojto 99:dbbf35b96557 154 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
Kojto 99:dbbf35b96557 155 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
Kojto 99:dbbf35b96557 156 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
Kojto 99:dbbf35b96557 157 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
Kojto 99:dbbf35b96557 158 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
Kojto 99:dbbf35b96557 159 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
Kojto 99:dbbf35b96557 160 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
Kojto 99:dbbf35b96557 161 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
Kojto 99:dbbf35b96557 162 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
Kojto 99:dbbf35b96557 163 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
Kojto 99:dbbf35b96557 164 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
Kojto 99:dbbf35b96557 165 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
Kojto 99:dbbf35b96557 166 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
Kojto 99:dbbf35b96557 167 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
Kojto 99:dbbf35b96557 168 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
Kojto 99:dbbf35b96557 169 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
Kojto 99:dbbf35b96557 170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
Kojto 99:dbbf35b96557 171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
Kojto 99:dbbf35b96557 172 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
Kojto 99:dbbf35b96557 173 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
Kojto 99:dbbf35b96557 174 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
Kojto 99:dbbf35b96557 175 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
Kojto 99:dbbf35b96557 176 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
Kojto 99:dbbf35b96557 177 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
Kojto 99:dbbf35b96557 178 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
Kojto 99:dbbf35b96557 179 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
Kojto 99:dbbf35b96557 180 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
Kojto 99:dbbf35b96557 181 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
Kojto 99:dbbf35b96557 182 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
Kojto 99:dbbf35b96557 183 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
Kojto 99:dbbf35b96557 184 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
Kojto 99:dbbf35b96557 185 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
Kojto 99:dbbf35b96557 186 ((CMD) == ETH_FIXEDBURST_DISABLE))
Kojto 99:dbbf35b96557 187 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
Kojto 99:dbbf35b96557 188 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
Kojto 99:dbbf35b96557 189 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
Kojto 99:dbbf35b96557 190 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
Kojto 99:dbbf35b96557 191 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
Kojto 99:dbbf35b96557 192 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
Kojto 99:dbbf35b96557 193 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
Kojto 99:dbbf35b96557 194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
Kojto 99:dbbf35b96557 195 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
Kojto 99:dbbf35b96557 196 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
Kojto 99:dbbf35b96557 197 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
Kojto 99:dbbf35b96557 198 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto 99:dbbf35b96557 199 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
Kojto 99:dbbf35b96557 200 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
Kojto 99:dbbf35b96557 201 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
Kojto 99:dbbf35b96557 202 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
Kojto 99:dbbf35b96557 203 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
Kojto 99:dbbf35b96557 204 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
Kojto 99:dbbf35b96557 205 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
Kojto 99:dbbf35b96557 206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
Kojto 99:dbbf35b96557 207 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
Kojto 99:dbbf35b96557 208 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
Kojto 99:dbbf35b96557 209 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
Kojto 99:dbbf35b96557 210 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto 122:f9eeca106725 211 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
Kojto 99:dbbf35b96557 212 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
Kojto 99:dbbf35b96557 213 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
Kojto 99:dbbf35b96557 214 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
Kojto 99:dbbf35b96557 215 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
Kojto 99:dbbf35b96557 216 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
Kojto 99:dbbf35b96557 217 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
Kojto 99:dbbf35b96557 218 ((FLAG) == ETH_DMATXDESC_IC) || \
Kojto 99:dbbf35b96557 219 ((FLAG) == ETH_DMATXDESC_LS) || \
Kojto 99:dbbf35b96557 220 ((FLAG) == ETH_DMATXDESC_FS) || \
Kojto 99:dbbf35b96557 221 ((FLAG) == ETH_DMATXDESC_DC) || \
Kojto 99:dbbf35b96557 222 ((FLAG) == ETH_DMATXDESC_DP) || \
Kojto 99:dbbf35b96557 223 ((FLAG) == ETH_DMATXDESC_TTSE) || \
Kojto 99:dbbf35b96557 224 ((FLAG) == ETH_DMATXDESC_TER) || \
Kojto 99:dbbf35b96557 225 ((FLAG) == ETH_DMATXDESC_TCH) || \
Kojto 99:dbbf35b96557 226 ((FLAG) == ETH_DMATXDESC_TTSS) || \
Kojto 99:dbbf35b96557 227 ((FLAG) == ETH_DMATXDESC_IHE) || \
Kojto 99:dbbf35b96557 228 ((FLAG) == ETH_DMATXDESC_ES) || \
Kojto 99:dbbf35b96557 229 ((FLAG) == ETH_DMATXDESC_JT) || \
Kojto 99:dbbf35b96557 230 ((FLAG) == ETH_DMATXDESC_FF) || \
Kojto 99:dbbf35b96557 231 ((FLAG) == ETH_DMATXDESC_PCE) || \
Kojto 99:dbbf35b96557 232 ((FLAG) == ETH_DMATXDESC_LCA) || \
Kojto 99:dbbf35b96557 233 ((FLAG) == ETH_DMATXDESC_NC) || \
Kojto 99:dbbf35b96557 234 ((FLAG) == ETH_DMATXDESC_LCO) || \
Kojto 99:dbbf35b96557 235 ((FLAG) == ETH_DMATXDESC_EC) || \
Kojto 99:dbbf35b96557 236 ((FLAG) == ETH_DMATXDESC_VF) || \
Kojto 99:dbbf35b96557 237 ((FLAG) == ETH_DMATXDESC_CC) || \
Kojto 99:dbbf35b96557 238 ((FLAG) == ETH_DMATXDESC_ED) || \
Kojto 99:dbbf35b96557 239 ((FLAG) == ETH_DMATXDESC_UF) || \
Kojto 99:dbbf35b96557 240 ((FLAG) == ETH_DMATXDESC_DB))
Kojto 99:dbbf35b96557 241 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
Kojto 99:dbbf35b96557 242 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
Kojto 99:dbbf35b96557 243 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
Kojto 99:dbbf35b96557 244 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
Kojto 99:dbbf35b96557 245 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
Kojto 99:dbbf35b96557 246 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
Kojto 122:f9eeca106725 247 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
Kojto 99:dbbf35b96557 248 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
Kojto 99:dbbf35b96557 249 ((FLAG) == ETH_DMARXDESC_AFM) || \
Kojto 99:dbbf35b96557 250 ((FLAG) == ETH_DMARXDESC_ES) || \
Kojto 99:dbbf35b96557 251 ((FLAG) == ETH_DMARXDESC_DE) || \
Kojto 99:dbbf35b96557 252 ((FLAG) == ETH_DMARXDESC_SAF) || \
Kojto 99:dbbf35b96557 253 ((FLAG) == ETH_DMARXDESC_LE) || \
Kojto 99:dbbf35b96557 254 ((FLAG) == ETH_DMARXDESC_OE) || \
Kojto 99:dbbf35b96557 255 ((FLAG) == ETH_DMARXDESC_VLAN) || \
Kojto 99:dbbf35b96557 256 ((FLAG) == ETH_DMARXDESC_FS) || \
Kojto 99:dbbf35b96557 257 ((FLAG) == ETH_DMARXDESC_LS) || \
Kojto 99:dbbf35b96557 258 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
Kojto 99:dbbf35b96557 259 ((FLAG) == ETH_DMARXDESC_LC) || \
Kojto 99:dbbf35b96557 260 ((FLAG) == ETH_DMARXDESC_FT) || \
Kojto 99:dbbf35b96557 261 ((FLAG) == ETH_DMARXDESC_RWT) || \
Kojto 99:dbbf35b96557 262 ((FLAG) == ETH_DMARXDESC_RE) || \
Kojto 99:dbbf35b96557 263 ((FLAG) == ETH_DMARXDESC_DBE) || \
Kojto 99:dbbf35b96557 264 ((FLAG) == ETH_DMARXDESC_CE) || \
Kojto 99:dbbf35b96557 265 ((FLAG) == ETH_DMARXDESC_MAMPCE))
Kojto 99:dbbf35b96557 266 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
Kojto 99:dbbf35b96557 267 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
Kojto 99:dbbf35b96557 268 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
Kojto 99:dbbf35b96557 269 ((FLAG) == ETH_PMT_FLAG_MPR))
Kojto 122:f9eeca106725 270 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
Kojto 99:dbbf35b96557 271 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
Kojto 99:dbbf35b96557 272 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
Kojto 99:dbbf35b96557 273 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
Kojto 99:dbbf35b96557 274 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
Kojto 99:dbbf35b96557 275 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
Kojto 99:dbbf35b96557 276 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
Kojto 99:dbbf35b96557 277 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
Kojto 99:dbbf35b96557 278 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
Kojto 99:dbbf35b96557 279 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
Kojto 99:dbbf35b96557 280 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
Kojto 99:dbbf35b96557 281 ((FLAG) == ETH_DMA_FLAG_T))
Kojto 122:f9eeca106725 282 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
Kojto 99:dbbf35b96557 283 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
Kojto 99:dbbf35b96557 284 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
Kojto 99:dbbf35b96557 285 ((IT) == ETH_MAC_IT_PMT))
Kojto 99:dbbf35b96557 286 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
Kojto 99:dbbf35b96557 287 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
Kojto 99:dbbf35b96557 288 ((FLAG) == ETH_MAC_FLAG_PMT))
Kojto 122:f9eeca106725 289 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
Kojto 99:dbbf35b96557 290 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
Kojto 99:dbbf35b96557 291 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
Kojto 99:dbbf35b96557 292 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
Kojto 99:dbbf35b96557 293 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
Kojto 99:dbbf35b96557 294 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
Kojto 99:dbbf35b96557 295 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
Kojto 99:dbbf35b96557 296 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
Kojto 99:dbbf35b96557 297 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
Kojto 99:dbbf35b96557 298 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
Kojto 99:dbbf35b96557 299 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
Kojto 99:dbbf35b96557 300 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
Kojto 122:f9eeca106725 301 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFFU) == 0x00U) || (((IT) & (uint32_t)0xEFFDFF9FU) == 0x00U)) && \
Kojto 122:f9eeca106725 302 ((IT) != 0x00U))
Kojto 99:dbbf35b96557 303 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
Kojto 99:dbbf35b96557 304 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
Kojto 99:dbbf35b96557 305 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
Kojto 99:dbbf35b96557 306 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
Kojto 99:dbbf35b96557 307 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
Kojto 99:dbbf35b96557 308
Kojto 99:dbbf35b96557 309 /**
Kojto 99:dbbf35b96557 310 * @}
Kojto 99:dbbf35b96557 311 */
Kojto 99:dbbf35b96557 312
Kojto 99:dbbf35b96557 313 /** @addtogroup ETH_Private_Defines
Kojto 99:dbbf35b96557 314 * @{
Kojto 99:dbbf35b96557 315 */
Kojto 99:dbbf35b96557 316 /* Delay to wait when writing to some Ethernet registers */
Kojto 122:f9eeca106725 317 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U)
Kojto 99:dbbf35b96557 318
Kojto 99:dbbf35b96557 319 /* ETHERNET Errors */
Kojto 122:f9eeca106725 320 #define ETH_SUCCESS ((uint32_t)0U)
Kojto 122:f9eeca106725 321 #define ETH_ERROR ((uint32_t)1U)
Kojto 99:dbbf35b96557 322
Kojto 99:dbbf35b96557 323 /* ETHERNET DMA Tx descriptors Collision Count Shift */
Kojto 122:f9eeca106725 324 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U)
Kojto 99:dbbf35b96557 325
Kojto 99:dbbf35b96557 326 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
Kojto 122:f9eeca106725 327 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)
Kojto 99:dbbf35b96557 328
Kojto 99:dbbf35b96557 329 /* ETHERNET DMA Rx descriptors Frame Length Shift */
Kojto 122:f9eeca106725 330 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U)
Kojto 99:dbbf35b96557 331
Kojto 99:dbbf35b96557 332 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
Kojto 122:f9eeca106725 333 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)
Kojto 99:dbbf35b96557 334
Kojto 99:dbbf35b96557 335 /* ETHERNET DMA Rx descriptors Frame length Shift */
Kojto 122:f9eeca106725 336 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16U)
Kojto 99:dbbf35b96557 337
Kojto 99:dbbf35b96557 338 /* ETHERNET MAC address offsets */
Kojto 122:f9eeca106725 339 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* ETHERNET MAC address high offset */
Kojto 122:f9eeca106725 340 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* ETHERNET MAC address low offset */
Kojto 99:dbbf35b96557 341
Kojto 99:dbbf35b96557 342 /* ETHERNET MACMIIAR register Mask */
Kojto 122:f9eeca106725 343 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U)
Kojto 99:dbbf35b96557 344
Kojto 99:dbbf35b96557 345 /* ETHERNET MACCR register Mask */
Kojto 122:f9eeca106725 346 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU)
Kojto 99:dbbf35b96557 347
Kojto 99:dbbf35b96557 348 /* ETHERNET MACFCR register Mask */
Kojto 122:f9eeca106725 349 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U)
Kojto 99:dbbf35b96557 350
Kojto 99:dbbf35b96557 351 /* ETHERNET DMAOMR register Mask */
Kojto 122:f9eeca106725 352 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U)
Kojto 99:dbbf35b96557 353
Kojto 99:dbbf35b96557 354 /* ETHERNET Remote Wake-up frame register length */
Kojto 99:dbbf35b96557 355 #define ETH_WAKEUP_REGISTER_LENGTH 8
Kojto 99:dbbf35b96557 356
Kojto 99:dbbf35b96557 357 /* ETHERNET Missed frames counter Shift */
Kojto 122:f9eeca106725 358 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
Kojto 99:dbbf35b96557 359 /**
Kojto 99:dbbf35b96557 360 * @}
Kojto 99:dbbf35b96557 361 */
bogdanm 92:4fc01daae5a5 362
bogdanm 92:4fc01daae5a5 363 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 364 /** @defgroup ETH_Exported_Types ETH Exported Types
Kojto 99:dbbf35b96557 365 * @{
Kojto 99:dbbf35b96557 366 */
bogdanm 92:4fc01daae5a5 367
bogdanm 92:4fc01daae5a5 368 /**
bogdanm 92:4fc01daae5a5 369 * @brief HAL State structures definition
bogdanm 92:4fc01daae5a5 370 */
bogdanm 92:4fc01daae5a5 371 typedef enum
bogdanm 92:4fc01daae5a5 372 {
Kojto 122:f9eeca106725 373 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
Kojto 122:f9eeca106725 374 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
Kojto 122:f9eeca106725 375 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
Kojto 122:f9eeca106725 376 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
Kojto 122:f9eeca106725 377 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
Kojto 122:f9eeca106725 378 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
Kojto 122:f9eeca106725 379 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
Kojto 122:f9eeca106725 380 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
Kojto 122:f9eeca106725 381 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
Kojto 122:f9eeca106725 382 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
bogdanm 92:4fc01daae5a5 383 }HAL_ETH_StateTypeDef;
bogdanm 92:4fc01daae5a5 384
bogdanm 92:4fc01daae5a5 385 /**
bogdanm 92:4fc01daae5a5 386 * @brief ETH Init Structure definition
bogdanm 92:4fc01daae5a5 387 */
bogdanm 92:4fc01daae5a5 388
bogdanm 92:4fc01daae5a5 389 typedef struct
bogdanm 92:4fc01daae5a5 390 {
bogdanm 92:4fc01daae5a5 391 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
bogdanm 92:4fc01daae5a5 392 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
bogdanm 92:4fc01daae5a5 393 and the mode (half/full-duplex).
bogdanm 92:4fc01daae5a5 394 This parameter can be a value of @ref ETH_AutoNegotiation */
bogdanm 92:4fc01daae5a5 395
bogdanm 92:4fc01daae5a5 396 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
bogdanm 92:4fc01daae5a5 397 This parameter can be a value of @ref ETH_Speed */
bogdanm 92:4fc01daae5a5 398
bogdanm 92:4fc01daae5a5 399 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
bogdanm 92:4fc01daae5a5 400 This parameter can be a value of @ref ETH_Duplex_Mode */
bogdanm 92:4fc01daae5a5 401
bogdanm 92:4fc01daae5a5 402 uint16_t PhyAddress; /*!< Ethernet PHY address.
bogdanm 92:4fc01daae5a5 403 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
bogdanm 92:4fc01daae5a5 404
bogdanm 92:4fc01daae5a5 405 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
bogdanm 92:4fc01daae5a5 406
bogdanm 92:4fc01daae5a5 407 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
bogdanm 92:4fc01daae5a5 408 This parameter can be a value of @ref ETH_Rx_Mode */
bogdanm 92:4fc01daae5a5 409
bogdanm 92:4fc01daae5a5 410 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
bogdanm 92:4fc01daae5a5 411 This parameter can be a value of @ref ETH_Checksum_Mode */
bogdanm 92:4fc01daae5a5 412
Kojto 122:f9eeca106725 413 uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
bogdanm 92:4fc01daae5a5 414 This parameter can be a value of @ref ETH_Media_Interface */
bogdanm 92:4fc01daae5a5 415
bogdanm 92:4fc01daae5a5 416 } ETH_InitTypeDef;
bogdanm 92:4fc01daae5a5 417
bogdanm 92:4fc01daae5a5 418
bogdanm 92:4fc01daae5a5 419 /**
bogdanm 92:4fc01daae5a5 420 * @brief ETH MAC Configuration Structure definition
bogdanm 92:4fc01daae5a5 421 */
bogdanm 92:4fc01daae5a5 422
bogdanm 92:4fc01daae5a5 423 typedef struct
bogdanm 92:4fc01daae5a5 424 {
bogdanm 92:4fc01daae5a5 425 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
bogdanm 92:4fc01daae5a5 426 When enabled, the MAC allows no more then 2048 bytes to be received.
bogdanm 92:4fc01daae5a5 427 When disabled, the MAC can receive up to 16384 bytes.
Kojto 99:dbbf35b96557 428 This parameter can be a value of @ref ETH_Watchdog */
bogdanm 92:4fc01daae5a5 429
bogdanm 92:4fc01daae5a5 430 uint32_t Jabber; /*!< Selects or not Jabber timer
bogdanm 92:4fc01daae5a5 431 When enabled, the MAC allows no more then 2048 bytes to be sent.
bogdanm 92:4fc01daae5a5 432 When disabled, the MAC can send up to 16384 bytes.
bogdanm 92:4fc01daae5a5 433 This parameter can be a value of @ref ETH_Jabber */
bogdanm 92:4fc01daae5a5 434
bogdanm 92:4fc01daae5a5 435 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
bogdanm 92:4fc01daae5a5 436 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
bogdanm 92:4fc01daae5a5 437
bogdanm 92:4fc01daae5a5 438 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
bogdanm 92:4fc01daae5a5 439 This parameter can be a value of @ref ETH_Carrier_Sense */
bogdanm 92:4fc01daae5a5 440
bogdanm 92:4fc01daae5a5 441 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
bogdanm 92:4fc01daae5a5 442 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
bogdanm 92:4fc01daae5a5 443 in Half-Duplex mode.
bogdanm 92:4fc01daae5a5 444 This parameter can be a value of @ref ETH_Receive_Own */
bogdanm 92:4fc01daae5a5 445
bogdanm 92:4fc01daae5a5 446 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
bogdanm 92:4fc01daae5a5 447 This parameter can be a value of @ref ETH_Loop_Back_Mode */
bogdanm 92:4fc01daae5a5 448
bogdanm 92:4fc01daae5a5 449 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
bogdanm 92:4fc01daae5a5 450 This parameter can be a value of @ref ETH_Checksum_Offload */
bogdanm 92:4fc01daae5a5 451
bogdanm 92:4fc01daae5a5 452 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
bogdanm 92:4fc01daae5a5 453 when a collision occurs (Half-Duplex mode).
bogdanm 92:4fc01daae5a5 454 This parameter can be a value of @ref ETH_Retry_Transmission */
bogdanm 92:4fc01daae5a5 455
bogdanm 92:4fc01daae5a5 456 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
bogdanm 92:4fc01daae5a5 457 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
bogdanm 92:4fc01daae5a5 458
bogdanm 92:4fc01daae5a5 459 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
bogdanm 92:4fc01daae5a5 460 This parameter can be a value of @ref ETH_Back_Off_Limit */
bogdanm 92:4fc01daae5a5 461
bogdanm 92:4fc01daae5a5 462 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
bogdanm 92:4fc01daae5a5 463 This parameter can be a value of @ref ETH_Deferral_Check */
bogdanm 92:4fc01daae5a5 464
bogdanm 92:4fc01daae5a5 465 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
bogdanm 92:4fc01daae5a5 466 This parameter can be a value of @ref ETH_Receive_All */
bogdanm 92:4fc01daae5a5 467
Kojto 122:f9eeca106725 468 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
Kojto 122:f9eeca106725 469 This parameter can be a value of @ref ETH_Source_Addr_Filter */
bogdanm 92:4fc01daae5a5 470
Kojto 122:f9eeca106725 471 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
bogdanm 92:4fc01daae5a5 472 This parameter can be a value of @ref ETH_Pass_Control_Frames */
bogdanm 92:4fc01daae5a5 473
bogdanm 92:4fc01daae5a5 474 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
bogdanm 92:4fc01daae5a5 475 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
bogdanm 92:4fc01daae5a5 476
bogdanm 92:4fc01daae5a5 477 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
bogdanm 92:4fc01daae5a5 478 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
bogdanm 92:4fc01daae5a5 479
bogdanm 92:4fc01daae5a5 480 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
bogdanm 92:4fc01daae5a5 481 This parameter can be a value of @ref ETH_Promiscuous_Mode */
bogdanm 92:4fc01daae5a5 482
bogdanm 92:4fc01daae5a5 483 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
bogdanm 92:4fc01daae5a5 484 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
bogdanm 92:4fc01daae5a5 485
bogdanm 92:4fc01daae5a5 486 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
bogdanm 92:4fc01daae5a5 487 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
bogdanm 92:4fc01daae5a5 488
bogdanm 92:4fc01daae5a5 489 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
Kojto 122:f9eeca106725 490 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
bogdanm 92:4fc01daae5a5 491
bogdanm 92:4fc01daae5a5 492 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
Kojto 122:f9eeca106725 493 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
bogdanm 92:4fc01daae5a5 494
bogdanm 92:4fc01daae5a5 495 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
Kojto 122:f9eeca106725 496 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
bogdanm 92:4fc01daae5a5 497
bogdanm 92:4fc01daae5a5 498 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
bogdanm 92:4fc01daae5a5 499 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
bogdanm 92:4fc01daae5a5 500
bogdanm 92:4fc01daae5a5 501 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
bogdanm 92:4fc01daae5a5 502 automatic retransmission of PAUSE Frame.
bogdanm 92:4fc01daae5a5 503 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
Kojto 122:f9eeca106725 504
bogdanm 92:4fc01daae5a5 505 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
bogdanm 92:4fc01daae5a5 506 unicast address and unique multicast address).
bogdanm 92:4fc01daae5a5 507 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
bogdanm 92:4fc01daae5a5 508
bogdanm 92:4fc01daae5a5 509 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
bogdanm 92:4fc01daae5a5 510 disable its transmitter for a specified time (Pause Time)
bogdanm 92:4fc01daae5a5 511 This parameter can be a value of @ref ETH_Receive_Flow_Control */
bogdanm 92:4fc01daae5a5 512
bogdanm 92:4fc01daae5a5 513 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
bogdanm 92:4fc01daae5a5 514 or the MAC back-pressure operation (Half-Duplex mode)
bogdanm 92:4fc01daae5a5 515 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
bogdanm 92:4fc01daae5a5 516
bogdanm 92:4fc01daae5a5 517 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
bogdanm 92:4fc01daae5a5 518 comparison and filtering.
bogdanm 92:4fc01daae5a5 519 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
bogdanm 92:4fc01daae5a5 520
bogdanm 92:4fc01daae5a5 521 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
bogdanm 92:4fc01daae5a5 522
bogdanm 92:4fc01daae5a5 523 } ETH_MACInitTypeDef;
bogdanm 92:4fc01daae5a5 524
bogdanm 92:4fc01daae5a5 525 /**
bogdanm 92:4fc01daae5a5 526 * @brief ETH DMA Configuration Structure definition
bogdanm 92:4fc01daae5a5 527 */
bogdanm 92:4fc01daae5a5 528
bogdanm 92:4fc01daae5a5 529 typedef struct
bogdanm 92:4fc01daae5a5 530 {
bogdanm 92:4fc01daae5a5 531 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
bogdanm 92:4fc01daae5a5 532 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
bogdanm 92:4fc01daae5a5 533
bogdanm 92:4fc01daae5a5 534 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
bogdanm 92:4fc01daae5a5 535 This parameter can be a value of @ref ETH_Receive_Store_Forward */
bogdanm 92:4fc01daae5a5 536
bogdanm 92:4fc01daae5a5 537 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
bogdanm 92:4fc01daae5a5 538 This parameter can be a value of @ref ETH_Flush_Received_Frame */
bogdanm 92:4fc01daae5a5 539
bogdanm 92:4fc01daae5a5 540 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
bogdanm 92:4fc01daae5a5 541 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
bogdanm 92:4fc01daae5a5 542
bogdanm 92:4fc01daae5a5 543 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
bogdanm 92:4fc01daae5a5 544 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
bogdanm 92:4fc01daae5a5 545
bogdanm 92:4fc01daae5a5 546 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
bogdanm 92:4fc01daae5a5 547 This parameter can be a value of @ref ETH_Forward_Error_Frames */
bogdanm 92:4fc01daae5a5 548
bogdanm 92:4fc01daae5a5 549 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
bogdanm 92:4fc01daae5a5 550 and length less than 64 bytes) including pad-bytes and CRC)
bogdanm 92:4fc01daae5a5 551 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
bogdanm 92:4fc01daae5a5 552
bogdanm 92:4fc01daae5a5 553 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
bogdanm 92:4fc01daae5a5 554 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
bogdanm 92:4fc01daae5a5 555
bogdanm 92:4fc01daae5a5 556 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
bogdanm 92:4fc01daae5a5 557 frame of Transmit data even before obtaining the status for the first frame.
bogdanm 92:4fc01daae5a5 558 This parameter can be a value of @ref ETH_Second_Frame_Operate */
bogdanm 92:4fc01daae5a5 559
bogdanm 92:4fc01daae5a5 560 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
bogdanm 92:4fc01daae5a5 561 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
bogdanm 92:4fc01daae5a5 562
bogdanm 92:4fc01daae5a5 563 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
bogdanm 92:4fc01daae5a5 564 This parameter can be a value of @ref ETH_Fixed_Burst */
bogdanm 92:4fc01daae5a5 565
bogdanm 92:4fc01daae5a5 566 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
bogdanm 92:4fc01daae5a5 567 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
bogdanm 92:4fc01daae5a5 568
bogdanm 92:4fc01daae5a5 569 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
bogdanm 92:4fc01daae5a5 570 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
bogdanm 92:4fc01daae5a5 571
bogdanm 92:4fc01daae5a5 572 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
bogdanm 92:4fc01daae5a5 573 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
bogdanm 92:4fc01daae5a5 574
bogdanm 92:4fc01daae5a5 575 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
Kojto 122:f9eeca106725 576 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
bogdanm 92:4fc01daae5a5 577
bogdanm 92:4fc01daae5a5 578 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
bogdanm 92:4fc01daae5a5 579 This parameter can be a value of @ref ETH_DMA_Arbitration */
bogdanm 92:4fc01daae5a5 580 } ETH_DMAInitTypeDef;
bogdanm 92:4fc01daae5a5 581
bogdanm 92:4fc01daae5a5 582
bogdanm 92:4fc01daae5a5 583 /**
bogdanm 92:4fc01daae5a5 584 * @brief ETH DMA Descriptors data structure definition
bogdanm 92:4fc01daae5a5 585 */
bogdanm 92:4fc01daae5a5 586
bogdanm 92:4fc01daae5a5 587 typedef struct
bogdanm 92:4fc01daae5a5 588 {
bogdanm 92:4fc01daae5a5 589 __IO uint32_t Status; /*!< Status */
bogdanm 92:4fc01daae5a5 590
bogdanm 92:4fc01daae5a5 591 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
bogdanm 92:4fc01daae5a5 592
bogdanm 92:4fc01daae5a5 593 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
bogdanm 92:4fc01daae5a5 594
bogdanm 92:4fc01daae5a5 595 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
bogdanm 92:4fc01daae5a5 596
bogdanm 92:4fc01daae5a5 597 /*!< Enhanced ETHERNET DMA PTP Descriptors */
bogdanm 92:4fc01daae5a5 598 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
bogdanm 92:4fc01daae5a5 599
bogdanm 92:4fc01daae5a5 600 uint32_t Reserved1; /*!< Reserved */
bogdanm 92:4fc01daae5a5 601
bogdanm 92:4fc01daae5a5 602 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
bogdanm 92:4fc01daae5a5 603
bogdanm 92:4fc01daae5a5 604 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
bogdanm 92:4fc01daae5a5 605
bogdanm 92:4fc01daae5a5 606 } ETH_DMADescTypeDef;
bogdanm 92:4fc01daae5a5 607
bogdanm 92:4fc01daae5a5 608 /**
bogdanm 92:4fc01daae5a5 609 * @brief Received Frame Informations structure definition
bogdanm 92:4fc01daae5a5 610 */
bogdanm 92:4fc01daae5a5 611 typedef struct
bogdanm 92:4fc01daae5a5 612 {
bogdanm 92:4fc01daae5a5 613 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
bogdanm 92:4fc01daae5a5 614
bogdanm 92:4fc01daae5a5 615 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
bogdanm 92:4fc01daae5a5 616
bogdanm 92:4fc01daae5a5 617 uint32_t SegCount; /*!< Segment count */
bogdanm 92:4fc01daae5a5 618
bogdanm 92:4fc01daae5a5 619 uint32_t length; /*!< Frame length */
bogdanm 92:4fc01daae5a5 620
bogdanm 92:4fc01daae5a5 621 uint32_t buffer; /*!< Frame buffer */
bogdanm 92:4fc01daae5a5 622
bogdanm 92:4fc01daae5a5 623 } ETH_DMARxFrameInfos;
bogdanm 92:4fc01daae5a5 624
bogdanm 92:4fc01daae5a5 625 /**
bogdanm 92:4fc01daae5a5 626 * @brief ETH Handle Structure definition
bogdanm 92:4fc01daae5a5 627 */
bogdanm 92:4fc01daae5a5 628
bogdanm 92:4fc01daae5a5 629 typedef struct
bogdanm 92:4fc01daae5a5 630 {
bogdanm 92:4fc01daae5a5 631 ETH_TypeDef *Instance; /*!< Register base address */
bogdanm 92:4fc01daae5a5 632
bogdanm 92:4fc01daae5a5 633 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
bogdanm 92:4fc01daae5a5 634
bogdanm 92:4fc01daae5a5 635 uint32_t LinkStatus; /*!< Ethernet link status */
bogdanm 92:4fc01daae5a5 636
bogdanm 92:4fc01daae5a5 637 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
bogdanm 92:4fc01daae5a5 638
bogdanm 92:4fc01daae5a5 639 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
bogdanm 92:4fc01daae5a5 640
bogdanm 92:4fc01daae5a5 641 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
bogdanm 92:4fc01daae5a5 642
bogdanm 92:4fc01daae5a5 643 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
bogdanm 92:4fc01daae5a5 644
bogdanm 92:4fc01daae5a5 645 HAL_LockTypeDef Lock; /*!< ETH Lock */
bogdanm 92:4fc01daae5a5 646
bogdanm 92:4fc01daae5a5 647 } ETH_HandleTypeDef;
bogdanm 92:4fc01daae5a5 648
Kojto 99:dbbf35b96557 649 /**
Kojto 99:dbbf35b96557 650 * @}
Kojto 99:dbbf35b96557 651 */
bogdanm 92:4fc01daae5a5 652
Kojto 99:dbbf35b96557 653 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 654 /** @defgroup ETH_Exported_Constants ETH Exported Constants
Kojto 99:dbbf35b96557 655 * @{
Kojto 99:dbbf35b96557 656 */
bogdanm 92:4fc01daae5a5 657
Kojto 99:dbbf35b96557 658 /** @defgroup ETH_Buffers_setting ETH Buffers setting
bogdanm 92:4fc01daae5a5 659 * @{
bogdanm 92:4fc01daae5a5 660 */
Kojto 122:f9eeca106725 661 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
Kojto 122:f9eeca106725 662 #define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
Kojto 122:f9eeca106725 663 #define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */
Kojto 122:f9eeca106725 664 #define ETH_EXTRA ((uint32_t)2U) /*!< Extra bytes in some cases */
Kojto 122:f9eeca106725 665 #define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */
Kojto 122:f9eeca106725 666 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */
Kojto 122:f9eeca106725 667 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */
Kojto 122:f9eeca106725 668 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */
bogdanm 92:4fc01daae5a5 669
bogdanm 92:4fc01daae5a5 670 /* Ethernet driver receive buffers are organized in a chained linked-list, when
bogdanm 92:4fc01daae5a5 671 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
bogdanm 92:4fc01daae5a5 672 to the driver receive buffers memory.
bogdanm 92:4fc01daae5a5 673
bogdanm 92:4fc01daae5a5 674 Depending on the size of the received ethernet packet and the size of
bogdanm 92:4fc01daae5a5 675 each ethernet driver receive buffer, the received packet can take one or more
bogdanm 92:4fc01daae5a5 676 ethernet driver receive buffer.
bogdanm 92:4fc01daae5a5 677
bogdanm 92:4fc01daae5a5 678 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
bogdanm 92:4fc01daae5a5 679 and the total count of the driver receive buffers ETH_RXBUFNB.
bogdanm 92:4fc01daae5a5 680
bogdanm 92:4fc01daae5a5 681 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
bogdanm 92:4fc01daae5a5 682 example, they can be reconfigured in the application layer to fit the application
bogdanm 92:4fc01daae5a5 683 needs */
bogdanm 92:4fc01daae5a5 684
bogdanm 92:4fc01daae5a5 685 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
bogdanm 92:4fc01daae5a5 686 packet */
bogdanm 92:4fc01daae5a5 687 #ifndef ETH_RX_BUF_SIZE
bogdanm 92:4fc01daae5a5 688 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
bogdanm 92:4fc01daae5a5 689 #endif
bogdanm 92:4fc01daae5a5 690
bogdanm 92:4fc01daae5a5 691 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
bogdanm 92:4fc01daae5a5 692 #ifndef ETH_RXBUFNB
Kojto 122:f9eeca106725 693 #define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
bogdanm 92:4fc01daae5a5 694 #endif
bogdanm 92:4fc01daae5a5 695
bogdanm 92:4fc01daae5a5 696
bogdanm 92:4fc01daae5a5 697 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
bogdanm 92:4fc01daae5a5 698 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
bogdanm 92:4fc01daae5a5 699 driver transmit buffers memory to the TxFIFO.
bogdanm 92:4fc01daae5a5 700
bogdanm 92:4fc01daae5a5 701 Depending on the size of the Ethernet packet to be transmitted and the size of
bogdanm 92:4fc01daae5a5 702 each ethernet driver transmit buffer, the packet to be transmitted can take
bogdanm 92:4fc01daae5a5 703 one or more ethernet driver transmit buffer.
bogdanm 92:4fc01daae5a5 704
bogdanm 92:4fc01daae5a5 705 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
bogdanm 92:4fc01daae5a5 706 and the total count of the driver transmit buffers ETH_TXBUFNB.
bogdanm 92:4fc01daae5a5 707
bogdanm 92:4fc01daae5a5 708 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
bogdanm 92:4fc01daae5a5 709 example, they can be reconfigured in the application layer to fit the application
bogdanm 92:4fc01daae5a5 710 needs */
bogdanm 92:4fc01daae5a5 711
bogdanm 92:4fc01daae5a5 712 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
bogdanm 92:4fc01daae5a5 713 packet */
bogdanm 92:4fc01daae5a5 714 #ifndef ETH_TX_BUF_SIZE
bogdanm 92:4fc01daae5a5 715 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
bogdanm 92:4fc01daae5a5 716 #endif
bogdanm 92:4fc01daae5a5 717
bogdanm 92:4fc01daae5a5 718 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
bogdanm 92:4fc01daae5a5 719 #ifndef ETH_TXBUFNB
Kojto 122:f9eeca106725 720 #define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
bogdanm 92:4fc01daae5a5 721 #endif
bogdanm 92:4fc01daae5a5 722
Kojto 99:dbbf35b96557 723 /**
Kojto 99:dbbf35b96557 724 * @}
Kojto 99:dbbf35b96557 725 */
Kojto 99:dbbf35b96557 726
Kojto 99:dbbf35b96557 727 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
Kojto 99:dbbf35b96557 728 * @{
Kojto 99:dbbf35b96557 729 */
bogdanm 92:4fc01daae5a5 730
bogdanm 92:4fc01daae5a5 731 /*
Kojto 99:dbbf35b96557 732 DMA Tx Descriptor
bogdanm 92:4fc01daae5a5 733 -----------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 734 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
bogdanm 92:4fc01daae5a5 735 -----------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 736 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
bogdanm 92:4fc01daae5a5 737 -----------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 738 TDES2 | Buffer1 Address [31:0] |
bogdanm 92:4fc01daae5a5 739 -----------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 740 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
bogdanm 92:4fc01daae5a5 741 -----------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 742 */
bogdanm 92:4fc01daae5a5 743
bogdanm 92:4fc01daae5a5 744 /**
bogdanm 92:4fc01daae5a5 745 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
bogdanm 92:4fc01daae5a5 746 */
Kojto 122:f9eeca106725 747 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
Kojto 122:f9eeca106725 748 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */
Kojto 122:f9eeca106725 749 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */
Kojto 122:f9eeca106725 750 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */
Kojto 122:f9eeca106725 751 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */
Kojto 122:f9eeca106725 752 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */
Kojto 122:f9eeca106725 753 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */
Kojto 122:f9eeca106725 754 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */
Kojto 122:f9eeca106725 755 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */
Kojto 122:f9eeca106725 756 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */
Kojto 122:f9eeca106725 757 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
Kojto 122:f9eeca106725 758 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
Kojto 122:f9eeca106725 759 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */
Kojto 122:f9eeca106725 760 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */
Kojto 122:f9eeca106725 761 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */
Kojto 122:f9eeca106725 762 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */
Kojto 122:f9eeca106725 763 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
Kojto 122:f9eeca106725 764 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */
Kojto 122:f9eeca106725 765 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
Kojto 122:f9eeca106725 766 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */
Kojto 122:f9eeca106725 767 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */
Kojto 122:f9eeca106725 768 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */
Kojto 122:f9eeca106725 769 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */
Kojto 122:f9eeca106725 770 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */
Kojto 122:f9eeca106725 771 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */
Kojto 122:f9eeca106725 772 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */
Kojto 122:f9eeca106725 773 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */
Kojto 122:f9eeca106725 774 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */
Kojto 122:f9eeca106725 775 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */
bogdanm 92:4fc01daae5a5 776
bogdanm 92:4fc01daae5a5 777 /**
bogdanm 92:4fc01daae5a5 778 * @brief Bit definition of TDES1 register
bogdanm 92:4fc01daae5a5 779 */
Kojto 122:f9eeca106725 780 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */
Kojto 122:f9eeca106725 781 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */
bogdanm 92:4fc01daae5a5 782
bogdanm 92:4fc01daae5a5 783 /**
bogdanm 92:4fc01daae5a5 784 * @brief Bit definition of TDES2 register
bogdanm 92:4fc01daae5a5 785 */
Kojto 122:f9eeca106725 786 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */
bogdanm 92:4fc01daae5a5 787
bogdanm 92:4fc01daae5a5 788 /**
bogdanm 92:4fc01daae5a5 789 * @brief Bit definition of TDES3 register
bogdanm 92:4fc01daae5a5 790 */
Kojto 122:f9eeca106725 791 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */
bogdanm 92:4fc01daae5a5 792
bogdanm 92:4fc01daae5a5 793 /*---------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 794 TDES6 | Transmit Time Stamp Low [31:0] |
bogdanm 92:4fc01daae5a5 795 -----------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 796 TDES7 | Transmit Time Stamp High [31:0] |
bogdanm 92:4fc01daae5a5 797 ----------------------------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 798
bogdanm 92:4fc01daae5a5 799 /* Bit definition of TDES6 register */
Kojto 122:f9eeca106725 800 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */
bogdanm 92:4fc01daae5a5 801
bogdanm 92:4fc01daae5a5 802 /* Bit definition of TDES7 register */
Kojto 122:f9eeca106725 803 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */
bogdanm 92:4fc01daae5a5 804
bogdanm 92:4fc01daae5a5 805 /**
bogdanm 92:4fc01daae5a5 806 * @}
bogdanm 92:4fc01daae5a5 807 */
Kojto 99:dbbf35b96557 808 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
bogdanm 92:4fc01daae5a5 809 * @{
bogdanm 92:4fc01daae5a5 810 */
bogdanm 92:4fc01daae5a5 811
bogdanm 92:4fc01daae5a5 812 /*
bogdanm 92:4fc01daae5a5 813 DMA Rx Descriptor
bogdanm 92:4fc01daae5a5 814 --------------------------------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 815 RDES0 | OWN(31) | Status [30:0] |
bogdanm 92:4fc01daae5a5 816 ---------------------------------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 817 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
bogdanm 92:4fc01daae5a5 818 ---------------------------------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 819 RDES2 | Buffer1 Address [31:0] |
bogdanm 92:4fc01daae5a5 820 ---------------------------------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 821 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
bogdanm 92:4fc01daae5a5 822 ---------------------------------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 823 */
bogdanm 92:4fc01daae5a5 824
bogdanm 92:4fc01daae5a5 825 /**
bogdanm 92:4fc01daae5a5 826 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
bogdanm 92:4fc01daae5a5 827 */
Kojto 122:f9eeca106725 828 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
Kojto 122:f9eeca106725 829 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */
Kojto 122:f9eeca106725 830 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */
Kojto 122:f9eeca106725 831 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
Kojto 122:f9eeca106725 832 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */
Kojto 122:f9eeca106725 833 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */
Kojto 122:f9eeca106725 834 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */
Kojto 122:f9eeca106725 835 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */
Kojto 122:f9eeca106725 836 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */
Kojto 122:f9eeca106725 837 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */
Kojto 122:f9eeca106725 838 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */
Kojto 122:f9eeca106725 839 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
Kojto 122:f9eeca106725 840 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */
Kojto 122:f9eeca106725 841 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */
Kojto 122:f9eeca106725 842 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
Kojto 122:f9eeca106725 843 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */
Kojto 122:f9eeca106725 844 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
Kojto 122:f9eeca106725 845 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */
Kojto 122:f9eeca106725 846 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
bogdanm 92:4fc01daae5a5 847
bogdanm 92:4fc01daae5a5 848 /**
bogdanm 92:4fc01daae5a5 849 * @brief Bit definition of RDES1 register
bogdanm 92:4fc01daae5a5 850 */
Kojto 122:f9eeca106725 851 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */
Kojto 122:f9eeca106725 852 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */
Kojto 122:f9eeca106725 853 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */
Kojto 122:f9eeca106725 854 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */
Kojto 122:f9eeca106725 855 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */
bogdanm 92:4fc01daae5a5 856
bogdanm 92:4fc01daae5a5 857 /**
bogdanm 92:4fc01daae5a5 858 * @brief Bit definition of RDES2 register
bogdanm 92:4fc01daae5a5 859 */
Kojto 122:f9eeca106725 860 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */
bogdanm 92:4fc01daae5a5 861
bogdanm 92:4fc01daae5a5 862 /**
bogdanm 92:4fc01daae5a5 863 * @brief Bit definition of RDES3 register
bogdanm 92:4fc01daae5a5 864 */
Kojto 122:f9eeca106725 865 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */
bogdanm 92:4fc01daae5a5 866
bogdanm 92:4fc01daae5a5 867 /*---------------------------------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 868 RDES4 | Reserved[31:15] | Extended Status [14:0] |
bogdanm 92:4fc01daae5a5 869 ---------------------------------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 870 RDES5 | Reserved[31:0] |
bogdanm 92:4fc01daae5a5 871 ---------------------------------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 872 RDES6 | Receive Time Stamp Low [31:0] |
bogdanm 92:4fc01daae5a5 873 ---------------------------------------------------------------------------------------------------------------------
bogdanm 92:4fc01daae5a5 874 RDES7 | Receive Time Stamp High [31:0] |
bogdanm 92:4fc01daae5a5 875 --------------------------------------------------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 876
bogdanm 92:4fc01daae5a5 877 /* Bit definition of RDES4 register */
Kojto 122:f9eeca106725 878 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */
Kojto 122:f9eeca106725 879 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */
Kojto 122:f9eeca106725 880 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */
Kojto 122:f9eeca106725 881 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */
Kojto 122:f9eeca106725 882 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */
Kojto 122:f9eeca106725 883 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */
Kojto 122:f9eeca106725 884 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */
Kojto 122:f9eeca106725 885 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
Kojto 122:f9eeca106725 886 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
Kojto 122:f9eeca106725 887 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
Kojto 122:f9eeca106725 888 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */
Kojto 122:f9eeca106725 889 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */
Kojto 122:f9eeca106725 890 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */
Kojto 122:f9eeca106725 891 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */
Kojto 122:f9eeca106725 892 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */
Kojto 122:f9eeca106725 893 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */
Kojto 122:f9eeca106725 894 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */
Kojto 122:f9eeca106725 895 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */
Kojto 122:f9eeca106725 896 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */
bogdanm 92:4fc01daae5a5 897
bogdanm 92:4fc01daae5a5 898 /* Bit definition of RDES6 register */
Kojto 122:f9eeca106725 899 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */
bogdanm 92:4fc01daae5a5 900
bogdanm 92:4fc01daae5a5 901 /* Bit definition of RDES7 register */
Kojto 122:f9eeca106725 902 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */
Kojto 99:dbbf35b96557 903 /**
Kojto 99:dbbf35b96557 904 * @}
Kojto 99:dbbf35b96557 905 */
Kojto 99:dbbf35b96557 906 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
bogdanm 92:4fc01daae5a5 907 * @{
bogdanm 92:4fc01daae5a5 908 */
Kojto 122:f9eeca106725 909 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 910 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U)
Kojto 99:dbbf35b96557 911
bogdanm 92:4fc01daae5a5 912 /**
bogdanm 92:4fc01daae5a5 913 * @}
bogdanm 92:4fc01daae5a5 914 */
Kojto 99:dbbf35b96557 915 /** @defgroup ETH_Speed ETH Speed
bogdanm 92:4fc01daae5a5 916 * @{
bogdanm 92:4fc01daae5a5 917 */
Kojto 122:f9eeca106725 918 #define ETH_SPEED_10M ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 919 #define ETH_SPEED_100M ((uint32_t)0x00004000U)
Kojto 99:dbbf35b96557 920
bogdanm 92:4fc01daae5a5 921 /**
bogdanm 92:4fc01daae5a5 922 * @}
bogdanm 92:4fc01daae5a5 923 */
Kojto 99:dbbf35b96557 924 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
bogdanm 92:4fc01daae5a5 925 * @{
bogdanm 92:4fc01daae5a5 926 */
Kojto 122:f9eeca106725 927 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 928 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 929 /**
bogdanm 92:4fc01daae5a5 930 * @}
bogdanm 92:4fc01daae5a5 931 */
Kojto 99:dbbf35b96557 932 /** @defgroup ETH_Rx_Mode ETH Rx Mode
bogdanm 92:4fc01daae5a5 933 * @{
bogdanm 92:4fc01daae5a5 934 */
Kojto 122:f9eeca106725 935 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 936 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U)
bogdanm 92:4fc01daae5a5 937 /**
bogdanm 92:4fc01daae5a5 938 * @}
bogdanm 92:4fc01daae5a5 939 */
bogdanm 92:4fc01daae5a5 940
Kojto 99:dbbf35b96557 941 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
bogdanm 92:4fc01daae5a5 942 * @{
bogdanm 92:4fc01daae5a5 943 */
Kojto 122:f9eeca106725 944 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 945 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U)
bogdanm 92:4fc01daae5a5 946 /**
bogdanm 92:4fc01daae5a5 947 * @}
bogdanm 92:4fc01daae5a5 948 */
bogdanm 92:4fc01daae5a5 949
Kojto 99:dbbf35b96557 950 /** @defgroup ETH_Media_Interface ETH Media Interface
bogdanm 92:4fc01daae5a5 951 * @{
bogdanm 92:4fc01daae5a5 952 */
Kojto 122:f9eeca106725 953 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 954 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
bogdanm 92:4fc01daae5a5 955 /**
bogdanm 92:4fc01daae5a5 956 * @}
bogdanm 92:4fc01daae5a5 957 */
bogdanm 92:4fc01daae5a5 958
Kojto 99:dbbf35b96557 959 /** @defgroup ETH_Watchdog ETH Watchdog
bogdanm 92:4fc01daae5a5 960 * @{
bogdanm 92:4fc01daae5a5 961 */
Kojto 122:f9eeca106725 962 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 963 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U)
bogdanm 92:4fc01daae5a5 964 /**
bogdanm 92:4fc01daae5a5 965 * @}
bogdanm 92:4fc01daae5a5 966 */
bogdanm 92:4fc01daae5a5 967
Kojto 99:dbbf35b96557 968 /** @defgroup ETH_Jabber ETH Jabber
bogdanm 92:4fc01daae5a5 969 * @{
bogdanm 92:4fc01daae5a5 970 */
Kojto 122:f9eeca106725 971 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 972 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000U)
bogdanm 92:4fc01daae5a5 973 /**
bogdanm 92:4fc01daae5a5 974 * @}
bogdanm 92:4fc01daae5a5 975 */
bogdanm 92:4fc01daae5a5 976
Kojto 99:dbbf35b96557 977 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
bogdanm 92:4fc01daae5a5 978 * @{
bogdanm 92:4fc01daae5a5 979 */
Kojto 122:f9eeca106725 980 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U) /*!< minimum IFG between frames during transmission is 96Bit */
Kojto 122:f9eeca106725 981 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U) /*!< minimum IFG between frames during transmission is 88Bit */
Kojto 122:f9eeca106725 982 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U) /*!< minimum IFG between frames during transmission is 80Bit */
Kojto 122:f9eeca106725 983 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U) /*!< minimum IFG between frames during transmission is 72Bit */
Kojto 122:f9eeca106725 984 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U) /*!< minimum IFG between frames during transmission is 64Bit */
Kojto 122:f9eeca106725 985 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U) /*!< minimum IFG between frames during transmission is 56Bit */
Kojto 122:f9eeca106725 986 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U) /*!< minimum IFG between frames during transmission is 48Bit */
Kojto 122:f9eeca106725 987 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U) /*!< minimum IFG between frames during transmission is 40Bit */
bogdanm 92:4fc01daae5a5 988 /**
bogdanm 92:4fc01daae5a5 989 * @}
bogdanm 92:4fc01daae5a5 990 */
bogdanm 92:4fc01daae5a5 991
Kojto 99:dbbf35b96557 992 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
bogdanm 92:4fc01daae5a5 993 * @{
bogdanm 92:4fc01daae5a5 994 */
Kojto 122:f9eeca106725 995 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 996 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U)
bogdanm 92:4fc01daae5a5 997 /**
bogdanm 92:4fc01daae5a5 998 * @}
bogdanm 92:4fc01daae5a5 999 */
bogdanm 92:4fc01daae5a5 1000
Kojto 99:dbbf35b96557 1001 /** @defgroup ETH_Receive_Own ETH Receive Own
bogdanm 92:4fc01daae5a5 1002 * @{
bogdanm 92:4fc01daae5a5 1003 */
Kojto 122:f9eeca106725 1004 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 1005 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U)
bogdanm 92:4fc01daae5a5 1006 /**
bogdanm 92:4fc01daae5a5 1007 * @}
bogdanm 92:4fc01daae5a5 1008 */
bogdanm 92:4fc01daae5a5 1009
Kojto 99:dbbf35b96557 1010 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
bogdanm 92:4fc01daae5a5 1011 * @{
bogdanm 92:4fc01daae5a5 1012 */
Kojto 122:f9eeca106725 1013 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 1014 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1015 /**
bogdanm 92:4fc01daae5a5 1016 * @}
bogdanm 92:4fc01daae5a5 1017 */
bogdanm 92:4fc01daae5a5 1018
Kojto 99:dbbf35b96557 1019 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
bogdanm 92:4fc01daae5a5 1020 * @{
bogdanm 92:4fc01daae5a5 1021 */
Kojto 122:f9eeca106725 1022 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 1023 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1024 /**
bogdanm 92:4fc01daae5a5 1025 * @}
bogdanm 92:4fc01daae5a5 1026 */
bogdanm 92:4fc01daae5a5 1027
Kojto 99:dbbf35b96557 1028 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
bogdanm 92:4fc01daae5a5 1029 * @{
bogdanm 92:4fc01daae5a5 1030 */
Kojto 122:f9eeca106725 1031 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 1032 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U)
bogdanm 92:4fc01daae5a5 1033 /**
bogdanm 92:4fc01daae5a5 1034 * @}
bogdanm 92:4fc01daae5a5 1035 */
bogdanm 92:4fc01daae5a5 1036
Kojto 99:dbbf35b96557 1037 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
bogdanm 92:4fc01daae5a5 1038 * @{
bogdanm 92:4fc01daae5a5 1039 */
Kojto 122:f9eeca106725 1040 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 1041 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1042 /**
bogdanm 92:4fc01daae5a5 1043 * @}
bogdanm 92:4fc01daae5a5 1044 */
bogdanm 92:4fc01daae5a5 1045
Kojto 99:dbbf35b96557 1046 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
bogdanm 92:4fc01daae5a5 1047 * @{
bogdanm 92:4fc01daae5a5 1048 */
Kojto 122:f9eeca106725 1049 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 1050 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 1051 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 1052 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U)
bogdanm 92:4fc01daae5a5 1053 /**
bogdanm 92:4fc01daae5a5 1054 * @}
bogdanm 92:4fc01daae5a5 1055 */
bogdanm 92:4fc01daae5a5 1056
Kojto 99:dbbf35b96557 1057 /** @defgroup ETH_Deferral_Check ETH Deferral Check
bogdanm 92:4fc01daae5a5 1058 * @{
bogdanm 92:4fc01daae5a5 1059 */
Kojto 122:f9eeca106725 1060 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 1061 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1062 /**
bogdanm 92:4fc01daae5a5 1063 * @}
bogdanm 92:4fc01daae5a5 1064 */
bogdanm 92:4fc01daae5a5 1065
Kojto 99:dbbf35b96557 1066 /** @defgroup ETH_Receive_All ETH Receive All
bogdanm 92:4fc01daae5a5 1067 * @{
bogdanm 92:4fc01daae5a5 1068 */
Kojto 122:f9eeca106725 1069 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U)
Kojto 122:f9eeca106725 1070 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1071 /**
bogdanm 92:4fc01daae5a5 1072 * @}
bogdanm 92:4fc01daae5a5 1073 */
bogdanm 92:4fc01daae5a5 1074
Kojto 99:dbbf35b96557 1075 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
bogdanm 92:4fc01daae5a5 1076 * @{
bogdanm 92:4fc01daae5a5 1077 */
Kojto 122:f9eeca106725 1078 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 1079 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U)
Kojto 122:f9eeca106725 1080 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1081 /**
bogdanm 92:4fc01daae5a5 1082 * @}
bogdanm 92:4fc01daae5a5 1083 */
bogdanm 92:4fc01daae5a5 1084
Kojto 99:dbbf35b96557 1085 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
bogdanm 92:4fc01daae5a5 1086 * @{
bogdanm 92:4fc01daae5a5 1087 */
Kojto 122:f9eeca106725 1088 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U) /*!< MAC filters all control frames from reaching the application */
Kojto 122:f9eeca106725 1089 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
Kojto 122:f9eeca106725 1090 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U) /*!< MAC forwards control frames that pass the Address Filter. */
bogdanm 92:4fc01daae5a5 1091 /**
bogdanm 92:4fc01daae5a5 1092 * @}
bogdanm 92:4fc01daae5a5 1093 */
bogdanm 92:4fc01daae5a5 1094
Kojto 99:dbbf35b96557 1095 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
bogdanm 92:4fc01daae5a5 1096 * @{
bogdanm 92:4fc01daae5a5 1097 */
Kojto 122:f9eeca106725 1098 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 1099 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U)
bogdanm 92:4fc01daae5a5 1100 /**
bogdanm 92:4fc01daae5a5 1101 * @}
bogdanm 92:4fc01daae5a5 1102 */
bogdanm 92:4fc01daae5a5 1103
Kojto 99:dbbf35b96557 1104 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
bogdanm 92:4fc01daae5a5 1105 * @{
bogdanm 92:4fc01daae5a5 1106 */
Kojto 122:f9eeca106725 1107 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 1108 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U)
bogdanm 92:4fc01daae5a5 1109 /**
bogdanm 92:4fc01daae5a5 1110 * @}
bogdanm 92:4fc01daae5a5 1111 */
bogdanm 92:4fc01daae5a5 1112
Kojto 99:dbbf35b96557 1113 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
bogdanm 92:4fc01daae5a5 1114 * @{
bogdanm 92:4fc01daae5a5 1115 */
Kojto 122:f9eeca106725 1116 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 1117 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1118 /**
bogdanm 92:4fc01daae5a5 1119 * @}
bogdanm 92:4fc01daae5a5 1120 */
bogdanm 92:4fc01daae5a5 1121
Kojto 99:dbbf35b96557 1122 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
bogdanm 92:4fc01daae5a5 1123 * @{
bogdanm 92:4fc01daae5a5 1124 */
Kojto 122:f9eeca106725 1125 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U)
Kojto 122:f9eeca106725 1126 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 1127 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 1128 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U)
bogdanm 92:4fc01daae5a5 1129 /**
bogdanm 92:4fc01daae5a5 1130 * @}
bogdanm 92:4fc01daae5a5 1131 */
bogdanm 92:4fc01daae5a5 1132
Kojto 99:dbbf35b96557 1133 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
bogdanm 92:4fc01daae5a5 1134 * @{
bogdanm 92:4fc01daae5a5 1135 */
Kojto 122:f9eeca106725 1136 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U)
Kojto 122:f9eeca106725 1137 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 1138 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1139 /**
bogdanm 92:4fc01daae5a5 1140 * @}
bogdanm 92:4fc01daae5a5 1141 */
bogdanm 92:4fc01daae5a5 1142
Kojto 99:dbbf35b96557 1143 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
bogdanm 92:4fc01daae5a5 1144 * @{
bogdanm 92:4fc01daae5a5 1145 */
Kojto 122:f9eeca106725 1146 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 1147 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U)
bogdanm 92:4fc01daae5a5 1148 /**
bogdanm 92:4fc01daae5a5 1149 * @}
bogdanm 92:4fc01daae5a5 1150 */
bogdanm 92:4fc01daae5a5 1151
Kojto 99:dbbf35b96557 1152 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
bogdanm 92:4fc01daae5a5 1153 * @{
bogdanm 92:4fc01daae5a5 1154 */
Kojto 122:f9eeca106725 1155 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U) /*!< Pause time minus 4 slot times */
Kojto 122:f9eeca106725 1156 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U) /*!< Pause time minus 28 slot times */
Kojto 122:f9eeca106725 1157 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U) /*!< Pause time minus 144 slot times */
Kojto 122:f9eeca106725 1158 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U) /*!< Pause time minus 256 slot times */
bogdanm 92:4fc01daae5a5 1159 /**
bogdanm 92:4fc01daae5a5 1160 * @}
bogdanm 92:4fc01daae5a5 1161 */
bogdanm 92:4fc01daae5a5 1162
Kojto 99:dbbf35b96557 1163 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
bogdanm 92:4fc01daae5a5 1164 * @{
bogdanm 92:4fc01daae5a5 1165 */
Kojto 122:f9eeca106725 1166 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 1167 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1168 /**
bogdanm 92:4fc01daae5a5 1169 * @}
bogdanm 92:4fc01daae5a5 1170 */
bogdanm 92:4fc01daae5a5 1171
Kojto 99:dbbf35b96557 1172 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
bogdanm 92:4fc01daae5a5 1173 * @{
bogdanm 92:4fc01daae5a5 1174 */
Kojto 122:f9eeca106725 1175 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 1176 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1177 /**
bogdanm 92:4fc01daae5a5 1178 * @}
bogdanm 92:4fc01daae5a5 1179 */
bogdanm 92:4fc01daae5a5 1180
Kojto 99:dbbf35b96557 1181 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
bogdanm 92:4fc01daae5a5 1182 * @{
bogdanm 92:4fc01daae5a5 1183 */
Kojto 122:f9eeca106725 1184 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 1185 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1186 /**
bogdanm 92:4fc01daae5a5 1187 * @}
bogdanm 92:4fc01daae5a5 1188 */
bogdanm 92:4fc01daae5a5 1189
Kojto 99:dbbf35b96557 1190 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
bogdanm 92:4fc01daae5a5 1191 * @{
bogdanm 92:4fc01daae5a5 1192 */
Kojto 122:f9eeca106725 1193 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 1194 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1195 /**
bogdanm 92:4fc01daae5a5 1196 * @}
bogdanm 92:4fc01daae5a5 1197 */
bogdanm 92:4fc01daae5a5 1198
Kojto 99:dbbf35b96557 1199 /** @defgroup ETH_MAC_addresses ETH MAC addresses
bogdanm 92:4fc01daae5a5 1200 * @{
bogdanm 92:4fc01daae5a5 1201 */
Kojto 122:f9eeca106725 1202 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 1203 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 1204 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 1205 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
bogdanm 92:4fc01daae5a5 1206 /**
bogdanm 92:4fc01daae5a5 1207 * @}
bogdanm 92:4fc01daae5a5 1208 */
bogdanm 92:4fc01daae5a5 1209
Kojto 99:dbbf35b96557 1210 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
bogdanm 92:4fc01daae5a5 1211 * @{
bogdanm 92:4fc01daae5a5 1212 */
Kojto 122:f9eeca106725 1213 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 1214 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U)
bogdanm 92:4fc01daae5a5 1215 /**
bogdanm 92:4fc01daae5a5 1216 * @}
bogdanm 92:4fc01daae5a5 1217 */
bogdanm 92:4fc01daae5a5 1218
Kojto 99:dbbf35b96557 1219 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
bogdanm 92:4fc01daae5a5 1220 * @{
bogdanm 92:4fc01daae5a5 1221 */
Kojto 122:f9eeca106725 1222 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U) /*!< Mask MAC Address high reg bits [15:8] */
Kojto 122:f9eeca106725 1223 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U) /*!< Mask MAC Address high reg bits [7:0] */
Kojto 122:f9eeca106725 1224 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U) /*!< Mask MAC Address low reg bits [31:24] */
Kojto 122:f9eeca106725 1225 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U) /*!< Mask MAC Address low reg bits [23:16] */
Kojto 122:f9eeca106725 1226 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U) /*!< Mask MAC Address low reg bits [15:8] */
Kojto 122:f9eeca106725 1227 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U) /*!< Mask MAC Address low reg bits [70] */
bogdanm 92:4fc01daae5a5 1228 /**
bogdanm 92:4fc01daae5a5 1229 * @}
bogdanm 92:4fc01daae5a5 1230 */
bogdanm 92:4fc01daae5a5 1231
Kojto 99:dbbf35b96557 1232 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
bogdanm 92:4fc01daae5a5 1233 * @{
bogdanm 92:4fc01daae5a5 1234 */
Kojto 122:f9eeca106725 1235 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 1236 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U)
bogdanm 92:4fc01daae5a5 1237 /**
bogdanm 92:4fc01daae5a5 1238 * @}
bogdanm 92:4fc01daae5a5 1239 */
bogdanm 92:4fc01daae5a5 1240
Kojto 99:dbbf35b96557 1241 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
bogdanm 92:4fc01daae5a5 1242 * @{
bogdanm 92:4fc01daae5a5 1243 */
Kojto 122:f9eeca106725 1244 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 1245 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1246 /**
bogdanm 92:4fc01daae5a5 1247 * @}
bogdanm 92:4fc01daae5a5 1248 */
bogdanm 92:4fc01daae5a5 1249
Kojto 99:dbbf35b96557 1250 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
bogdanm 92:4fc01daae5a5 1251 * @{
bogdanm 92:4fc01daae5a5 1252 */
Kojto 122:f9eeca106725 1253 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 1254 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U)
bogdanm 92:4fc01daae5a5 1255 /**
bogdanm 92:4fc01daae5a5 1256 * @}
bogdanm 92:4fc01daae5a5 1257 */
bogdanm 92:4fc01daae5a5 1258
Kojto 99:dbbf35b96557 1259 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
bogdanm 92:4fc01daae5a5 1260 * @{
bogdanm 92:4fc01daae5a5 1261 */
Kojto 122:f9eeca106725 1262 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 1263 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1264 /**
bogdanm 92:4fc01daae5a5 1265 * @}
bogdanm 92:4fc01daae5a5 1266 */
bogdanm 92:4fc01daae5a5 1267
Kojto 99:dbbf35b96557 1268 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
bogdanm 92:4fc01daae5a5 1269 * @{
bogdanm 92:4fc01daae5a5 1270 */
Kojto 122:f9eeca106725 1271 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
Kojto 122:f9eeca106725 1272 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
Kojto 122:f9eeca106725 1273 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
Kojto 122:f9eeca106725 1274 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
Kojto 122:f9eeca106725 1275 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
Kojto 122:f9eeca106725 1276 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
Kojto 122:f9eeca106725 1277 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
Kojto 122:f9eeca106725 1278 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
bogdanm 92:4fc01daae5a5 1279 /**
bogdanm 92:4fc01daae5a5 1280 * @}
bogdanm 92:4fc01daae5a5 1281 */
bogdanm 92:4fc01daae5a5 1282
Kojto 99:dbbf35b96557 1283 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
bogdanm 92:4fc01daae5a5 1284 * @{
bogdanm 92:4fc01daae5a5 1285 */
Kojto 122:f9eeca106725 1286 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 1287 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1288 /**
bogdanm 92:4fc01daae5a5 1289 * @}
bogdanm 92:4fc01daae5a5 1290 */
bogdanm 92:4fc01daae5a5 1291
Kojto 99:dbbf35b96557 1292 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
bogdanm 92:4fc01daae5a5 1293 * @{
bogdanm 92:4fc01daae5a5 1294 */
Kojto 122:f9eeca106725 1295 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 1296 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1297 /**
bogdanm 92:4fc01daae5a5 1298 * @}
bogdanm 92:4fc01daae5a5 1299 */
bogdanm 92:4fc01daae5a5 1300
Kojto 99:dbbf35b96557 1301 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
bogdanm 92:4fc01daae5a5 1302 * @{
bogdanm 92:4fc01daae5a5 1303 */
Kojto 122:f9eeca106725 1304 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
Kojto 122:f9eeca106725 1305 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
Kojto 122:f9eeca106725 1306 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
Kojto 122:f9eeca106725 1307 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
bogdanm 92:4fc01daae5a5 1308 /**
bogdanm 92:4fc01daae5a5 1309 * @}
bogdanm 92:4fc01daae5a5 1310 */
bogdanm 92:4fc01daae5a5 1311
Kojto 99:dbbf35b96557 1312 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
bogdanm 92:4fc01daae5a5 1313 * @{
bogdanm 92:4fc01daae5a5 1314 */
Kojto 122:f9eeca106725 1315 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 1316 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1317 /**
bogdanm 92:4fc01daae5a5 1318 * @}
bogdanm 92:4fc01daae5a5 1319 */
bogdanm 92:4fc01daae5a5 1320
Kojto 99:dbbf35b96557 1321 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
bogdanm 92:4fc01daae5a5 1322 * @{
bogdanm 92:4fc01daae5a5 1323 */
Kojto 122:f9eeca106725 1324 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 1325 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1326 /**
bogdanm 92:4fc01daae5a5 1327 * @}
bogdanm 92:4fc01daae5a5 1328 */
bogdanm 92:4fc01daae5a5 1329
Kojto 99:dbbf35b96557 1330 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
bogdanm 92:4fc01daae5a5 1331 * @{
bogdanm 92:4fc01daae5a5 1332 */
Kojto 122:f9eeca106725 1333 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 1334 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1335 /**
bogdanm 92:4fc01daae5a5 1336 * @}
bogdanm 92:4fc01daae5a5 1337 */
bogdanm 92:4fc01daae5a5 1338
Kojto 99:dbbf35b96557 1339 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
bogdanm 92:4fc01daae5a5 1340 * @{
bogdanm 92:4fc01daae5a5 1341 */
Kojto 122:f9eeca106725 1342 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
Kojto 122:f9eeca106725 1343 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
Kojto 122:f9eeca106725 1344 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto 122:f9eeca106725 1345 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto 122:f9eeca106725 1346 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto 122:f9eeca106725 1347 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto 122:f9eeca106725 1348 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto 122:f9eeca106725 1349 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto 122:f9eeca106725 1350 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto 122:f9eeca106725 1351 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto 122:f9eeca106725 1352 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
Kojto 122:f9eeca106725 1353 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
bogdanm 92:4fc01daae5a5 1354 /**
bogdanm 92:4fc01daae5a5 1355 * @}
bogdanm 92:4fc01daae5a5 1356 */
bogdanm 92:4fc01daae5a5 1357
Kojto 99:dbbf35b96557 1358 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
bogdanm 92:4fc01daae5a5 1359 * @{
bogdanm 92:4fc01daae5a5 1360 */
Kojto 122:f9eeca106725 1361 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
Kojto 122:f9eeca106725 1362 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
Kojto 122:f9eeca106725 1363 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto 122:f9eeca106725 1364 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto 122:f9eeca106725 1365 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto 122:f9eeca106725 1366 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto 122:f9eeca106725 1367 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto 122:f9eeca106725 1368 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto 122:f9eeca106725 1369 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto 122:f9eeca106725 1370 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto 122:f9eeca106725 1371 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
Kojto 122:f9eeca106725 1372 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
Kojto 99:dbbf35b96557 1373 /**
Kojto 99:dbbf35b96557 1374 * @}
Kojto 99:dbbf35b96557 1375 */
bogdanm 92:4fc01daae5a5 1376
Kojto 99:dbbf35b96557 1377 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
bogdanm 92:4fc01daae5a5 1378 * @{
bogdanm 92:4fc01daae5a5 1379 */
Kojto 122:f9eeca106725 1380 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 1381 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 1382 /**
bogdanm 92:4fc01daae5a5 1383 * @}
bogdanm 92:4fc01daae5a5 1384 */
bogdanm 92:4fc01daae5a5 1385
Kojto 99:dbbf35b96557 1386 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
bogdanm 92:4fc01daae5a5 1387 * @{
bogdanm 92:4fc01daae5a5 1388 */
Kojto 122:f9eeca106725 1389 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 1390 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 1391 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 1392 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U)
Kojto 122:f9eeca106725 1393 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U)
bogdanm 92:4fc01daae5a5 1394 /**
bogdanm 92:4fc01daae5a5 1395 * @}
bogdanm 92:4fc01daae5a5 1396 */
bogdanm 92:4fc01daae5a5 1397
Kojto 99:dbbf35b96557 1398 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
bogdanm 92:4fc01daae5a5 1399 * @{
bogdanm 92:4fc01daae5a5 1400 */
Kojto 122:f9eeca106725 1401 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U) /*!< Last Segment */
Kojto 122:f9eeca106725 1402 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U) /*!< First Segment */
bogdanm 92:4fc01daae5a5 1403 /**
bogdanm 92:4fc01daae5a5 1404 * @}
bogdanm 92:4fc01daae5a5 1405 */
bogdanm 92:4fc01daae5a5 1406
Kojto 99:dbbf35b96557 1407 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
bogdanm 92:4fc01daae5a5 1408 * @{
bogdanm 92:4fc01daae5a5 1409 */
Kojto 122:f9eeca106725 1410 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U) /*!< Checksum engine bypass */
Kojto 122:f9eeca106725 1411 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U) /*!< IPv4 header checksum insertion */
Kojto 122:f9eeca106725 1412 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
Kojto 122:f9eeca106725 1413 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
bogdanm 92:4fc01daae5a5 1414 /**
bogdanm 92:4fc01daae5a5 1415 * @}
bogdanm 92:4fc01daae5a5 1416 */
bogdanm 92:4fc01daae5a5 1417
Kojto 99:dbbf35b96557 1418 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
bogdanm 92:4fc01daae5a5 1419 * @{
bogdanm 92:4fc01daae5a5 1420 */
Kojto 122:f9eeca106725 1421 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U) /*!< DMA Rx Desc Buffer1 */
Kojto 122:f9eeca106725 1422 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U) /*!< DMA Rx Desc Buffer2 */
bogdanm 92:4fc01daae5a5 1423 /**
bogdanm 92:4fc01daae5a5 1424 * @}
bogdanm 92:4fc01daae5a5 1425 */
bogdanm 92:4fc01daae5a5 1426
Kojto 99:dbbf35b96557 1427 /** @defgroup ETH_PMT_Flags ETH PMT Flags
bogdanm 92:4fc01daae5a5 1428 * @{
bogdanm 92:4fc01daae5a5 1429 */
Kojto 122:f9eeca106725 1430 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U) /*!< Wake-Up Frame Filter Register Pointer Reset */
Kojto 122:f9eeca106725 1431 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U) /*!< Wake-Up Frame Received */
Kojto 122:f9eeca106725 1432 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U) /*!< Magic Packet Received */
bogdanm 92:4fc01daae5a5 1433 /**
bogdanm 92:4fc01daae5a5 1434 * @}
bogdanm 92:4fc01daae5a5 1435 */
bogdanm 92:4fc01daae5a5 1436
Kojto 99:dbbf35b96557 1437 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
bogdanm 92:4fc01daae5a5 1438 * @{
bogdanm 92:4fc01daae5a5 1439 */
Kojto 122:f9eeca106725 1440 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000U) /*!< When Tx good frame counter reaches half the maximum value */
Kojto 122:f9eeca106725 1441 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U) /*!< When Tx good multi col counter reaches half the maximum value */
Kojto 122:f9eeca106725 1442 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U) /*!< When Tx good single col counter reaches half the maximum value */
bogdanm 92:4fc01daae5a5 1443 /**
bogdanm 92:4fc01daae5a5 1444 * @}
bogdanm 92:4fc01daae5a5 1445 */
bogdanm 92:4fc01daae5a5 1446
Kojto 99:dbbf35b96557 1447 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
bogdanm 92:4fc01daae5a5 1448 * @{
bogdanm 92:4fc01daae5a5 1449 */
Kojto 122:f9eeca106725 1450 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U) /*!< When Rx good unicast frames counter reaches half the maximum value */
Kojto 122:f9eeca106725 1451 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U) /*!< When Rx alignment error counter reaches half the maximum value */
Kojto 122:f9eeca106725 1452 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U) /*!< When Rx crc error counter reaches half the maximum value */
bogdanm 92:4fc01daae5a5 1453 /**
bogdanm 92:4fc01daae5a5 1454 * @}
bogdanm 92:4fc01daae5a5 1455 */
bogdanm 92:4fc01daae5a5 1456
Kojto 99:dbbf35b96557 1457 /** @defgroup ETH_MAC_Flags ETH MAC Flags
bogdanm 92:4fc01daae5a5 1458 * @{
bogdanm 92:4fc01daae5a5 1459 */
Kojto 122:f9eeca106725 1460 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger flag (on MAC) */
Kojto 122:f9eeca106725 1461 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit flag */
Kojto 122:f9eeca106725 1462 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U) /*!< MMC receive flag */
Kojto 122:f9eeca106725 1463 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U) /*!< MMC flag (on MAC) */
Kojto 122:f9eeca106725 1464 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U) /*!< PMT flag (on MAC) */
bogdanm 92:4fc01daae5a5 1465 /**
bogdanm 92:4fc01daae5a5 1466 * @}
bogdanm 92:4fc01daae5a5 1467 */
bogdanm 92:4fc01daae5a5 1468
Kojto 99:dbbf35b96557 1469 /** @defgroup ETH_DMA_Flags ETH DMA Flags
bogdanm 92:4fc01daae5a5 1470 * @{
bogdanm 92:4fc01daae5a5 1471 */
Kojto 122:f9eeca106725 1472 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */
Kojto 122:f9eeca106725 1473 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */
Kojto 122:f9eeca106725 1474 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */
Kojto 122:f9eeca106725 1475 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
Kojto 122:f9eeca106725 1476 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U) /*!< Error bits 0-write transfer, 1-read transfer */
Kojto 122:f9eeca106725 1477 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U) /*!< Error bits 0-data buffer, 1-desc. access */
Kojto 122:f9eeca106725 1478 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary flag */
Kojto 122:f9eeca106725 1479 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary flag */
Kojto 122:f9eeca106725 1480 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U) /*!< Early receive flag */
Kojto 122:f9eeca106725 1481 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error flag */
Kojto 122:f9eeca106725 1482 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U) /*!< Early transmit flag */
Kojto 122:f9eeca106725 1483 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout flag */
Kojto 122:f9eeca106725 1484 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped flag */
Kojto 122:f9eeca106725 1485 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable flag */
Kojto 122:f9eeca106725 1486 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040U) /*!< Receive flag */
Kojto 122:f9eeca106725 1487 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U) /*!< Underflow flag */
Kojto 122:f9eeca106725 1488 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U) /*!< Overflow flag */
Kojto 122:f9eeca106725 1489 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout flag */
Kojto 122:f9eeca106725 1490 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable flag */
Kojto 122:f9eeca106725 1491 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped flag */
Kojto 122:f9eeca106725 1492 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001U) /*!< Transmit flag */
bogdanm 92:4fc01daae5a5 1493 /**
bogdanm 92:4fc01daae5a5 1494 * @}
bogdanm 92:4fc01daae5a5 1495 */
bogdanm 92:4fc01daae5a5 1496
Kojto 99:dbbf35b96557 1497 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
bogdanm 92:4fc01daae5a5 1498 * @{
bogdanm 92:4fc01daae5a5 1499 */
Kojto 122:f9eeca106725 1500 #define ETH_MAC_IT_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger interrupt (on MAC) */
Kojto 122:f9eeca106725 1501 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit interrupt */
Kojto 122:f9eeca106725 1502 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U) /*!< MMC receive interrupt */
Kojto 122:f9eeca106725 1503 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010U) /*!< MMC interrupt (on MAC) */
Kojto 122:f9eeca106725 1504 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008U) /*!< PMT interrupt (on MAC) */
bogdanm 92:4fc01daae5a5 1505 /**
bogdanm 92:4fc01daae5a5 1506 * @}
bogdanm 92:4fc01daae5a5 1507 */
bogdanm 92:4fc01daae5a5 1508
Kojto 99:dbbf35b96557 1509 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
bogdanm 92:4fc01daae5a5 1510 * @{
bogdanm 92:4fc01daae5a5 1511 */
Kojto 122:f9eeca106725 1512 #define ETH_DMA_IT_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */
Kojto 122:f9eeca106725 1513 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */
Kojto 122:f9eeca106725 1514 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */
Kojto 122:f9eeca106725 1515 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary */
Kojto 122:f9eeca106725 1516 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary */
Kojto 122:f9eeca106725 1517 #define ETH_DMA_IT_ER ((uint32_t)0x00004000U) /*!< Early receive interrupt */
Kojto 122:f9eeca106725 1518 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error interrupt */
Kojto 122:f9eeca106725 1519 #define ETH_DMA_IT_ET ((uint32_t)0x00000400U) /*!< Early transmit interrupt */
Kojto 122:f9eeca106725 1520 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout interrupt */
Kojto 122:f9eeca106725 1521 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped interrupt */
Kojto 122:f9eeca106725 1522 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable interrupt */
Kojto 122:f9eeca106725 1523 #define ETH_DMA_IT_R ((uint32_t)0x00000040U) /*!< Receive interrupt */
Kojto 122:f9eeca106725 1524 #define ETH_DMA_IT_TU ((uint32_t)0x00000020U) /*!< Underflow interrupt */
Kojto 122:f9eeca106725 1525 #define ETH_DMA_IT_RO ((uint32_t)0x00000010U) /*!< Overflow interrupt */
Kojto 122:f9eeca106725 1526 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout interrupt */
Kojto 122:f9eeca106725 1527 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable interrupt */
Kojto 122:f9eeca106725 1528 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped interrupt */
Kojto 122:f9eeca106725 1529 #define ETH_DMA_IT_T ((uint32_t)0x00000001U) /*!< Transmit interrupt */
bogdanm 92:4fc01daae5a5 1530 /**
bogdanm 92:4fc01daae5a5 1531 * @}
bogdanm 92:4fc01daae5a5 1532 */
bogdanm 92:4fc01daae5a5 1533
Kojto 99:dbbf35b96557 1534 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
bogdanm 92:4fc01daae5a5 1535 * @{
bogdanm 92:4fc01daae5a5 1536 */
Kojto 122:f9eeca106725 1537 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Tx Command issued */
Kojto 122:f9eeca106725 1538 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U) /*!< Running - fetching the Tx descriptor */
Kojto 122:f9eeca106725 1539 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U) /*!< Running - waiting for status */
Kojto 122:f9eeca106725 1540 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U) /*!< Running - reading the data from host memory */
Kojto 122:f9eeca106725 1541 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U) /*!< Suspended - Tx Descriptor unavailable */
Kojto 122:f9eeca106725 1542 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U) /*!< Running - closing Rx descriptor */
bogdanm 92:4fc01daae5a5 1543
bogdanm 92:4fc01daae5a5 1544 /**
bogdanm 92:4fc01daae5a5 1545 * @}
bogdanm 92:4fc01daae5a5 1546 */
bogdanm 92:4fc01daae5a5 1547
bogdanm 92:4fc01daae5a5 1548
Kojto 99:dbbf35b96557 1549 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
bogdanm 92:4fc01daae5a5 1550 * @{
bogdanm 92:4fc01daae5a5 1551 */
Kojto 122:f9eeca106725 1552 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Rx Command issued */
Kojto 122:f9eeca106725 1553 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U) /*!< Running - fetching the Rx descriptor */
Kojto 122:f9eeca106725 1554 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U) /*!< Running - waiting for packet */
Kojto 122:f9eeca106725 1555 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U) /*!< Suspended - Rx Descriptor unavailable */
Kojto 122:f9eeca106725 1556 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U) /*!< Running - closing descriptor */
Kojto 122:f9eeca106725 1557 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U) /*!< Running - queuing the receive frame into host memory */
bogdanm 92:4fc01daae5a5 1558
bogdanm 92:4fc01daae5a5 1559 /**
bogdanm 92:4fc01daae5a5 1560 * @}
bogdanm 92:4fc01daae5a5 1561 */
bogdanm 92:4fc01daae5a5 1562
Kojto 99:dbbf35b96557 1563 /** @defgroup ETH_DMA_overflow ETH DMA overflow
bogdanm 92:4fc01daae5a5 1564 * @{
bogdanm 92:4fc01daae5a5 1565 */
Kojto 122:f9eeca106725 1566 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U) /*!< Overflow bit for FIFO overflow counter */
Kojto 122:f9eeca106725 1567 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U) /*!< Overflow bit for missed frame counter */
bogdanm 92:4fc01daae5a5 1568 /**
bogdanm 92:4fc01daae5a5 1569 * @}
bogdanm 92:4fc01daae5a5 1570 */
bogdanm 92:4fc01daae5a5 1571
Kojto 99:dbbf35b96557 1572 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
Kojto 99:dbbf35b96557 1573 * @{
Kojto 99:dbbf35b96557 1574 */
Kojto 122:f9eeca106725 1575 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
bogdanm 92:4fc01daae5a5 1576
Kojto 99:dbbf35b96557 1577 /**
Kojto 99:dbbf35b96557 1578 * @}
Kojto 99:dbbf35b96557 1579 */
bogdanm 92:4fc01daae5a5 1580
bogdanm 92:4fc01daae5a5 1581 /**
bogdanm 92:4fc01daae5a5 1582 * @}
bogdanm 92:4fc01daae5a5 1583 */
bogdanm 92:4fc01daae5a5 1584
bogdanm 92:4fc01daae5a5 1585 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 1586 /** @defgroup ETH_Exported_Macros ETH Exported Macros
Kojto 99:dbbf35b96557 1587 * @brief macros to handle interrupts and specific clock configurations
Kojto 99:dbbf35b96557 1588 * @{
Kojto 99:dbbf35b96557 1589 */
Kojto 99:dbbf35b96557 1590
bogdanm 92:4fc01daae5a5 1591 /** @brief Reset ETH handle state
bogdanm 92:4fc01daae5a5 1592 * @param __HANDLE__: specifies the ETH handle.
bogdanm 92:4fc01daae5a5 1593 * @retval None
bogdanm 92:4fc01daae5a5 1594 */
bogdanm 92:4fc01daae5a5 1595 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
bogdanm 92:4fc01daae5a5 1596
bogdanm 92:4fc01daae5a5 1597 /**
bogdanm 92:4fc01daae5a5 1598 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
bogdanm 92:4fc01daae5a5 1599 * @param __HANDLE__: ETH Handle
Kojto 99:dbbf35b96557 1600 * @param __FLAG__: specifies the flag of TDES0 to check.
bogdanm 92:4fc01daae5a5 1601 * @retval the ETH_DMATxDescFlag (SET or RESET).
bogdanm 92:4fc01daae5a5 1602 */
bogdanm 92:4fc01daae5a5 1603 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
bogdanm 92:4fc01daae5a5 1604
bogdanm 92:4fc01daae5a5 1605 /**
bogdanm 92:4fc01daae5a5 1606 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
bogdanm 92:4fc01daae5a5 1607 * @param __HANDLE__: ETH Handle
Kojto 99:dbbf35b96557 1608 * @param __FLAG__: specifies the flag of RDES0 to check.
bogdanm 92:4fc01daae5a5 1609 * @retval the ETH_DMATxDescFlag (SET or RESET).
bogdanm 92:4fc01daae5a5 1610 */
bogdanm 92:4fc01daae5a5 1611 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
bogdanm 92:4fc01daae5a5 1612
bogdanm 92:4fc01daae5a5 1613 /**
bogdanm 92:4fc01daae5a5 1614 * @brief Enables the specified DMA Rx Desc receive interrupt.
bogdanm 92:4fc01daae5a5 1615 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1616 * @retval None
bogdanm 92:4fc01daae5a5 1617 */
bogdanm 92:4fc01daae5a5 1618 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
bogdanm 92:4fc01daae5a5 1619
bogdanm 92:4fc01daae5a5 1620 /**
bogdanm 92:4fc01daae5a5 1621 * @brief Disables the specified DMA Rx Desc receive interrupt.
bogdanm 92:4fc01daae5a5 1622 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1623 * @retval None
bogdanm 92:4fc01daae5a5 1624 */
bogdanm 92:4fc01daae5a5 1625 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
bogdanm 92:4fc01daae5a5 1626
bogdanm 92:4fc01daae5a5 1627 /**
bogdanm 92:4fc01daae5a5 1628 * @brief Set the specified DMA Rx Desc Own bit.
bogdanm 92:4fc01daae5a5 1629 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1630 * @retval None
bogdanm 92:4fc01daae5a5 1631 */
bogdanm 92:4fc01daae5a5 1632 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
bogdanm 92:4fc01daae5a5 1633
bogdanm 92:4fc01daae5a5 1634 /**
bogdanm 92:4fc01daae5a5 1635 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
bogdanm 92:4fc01daae5a5 1636 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1637 * @retval The Transmit descriptor collision counter value.
bogdanm 92:4fc01daae5a5 1638 */
bogdanm 92:4fc01daae5a5 1639 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
bogdanm 92:4fc01daae5a5 1640
bogdanm 92:4fc01daae5a5 1641 /**
bogdanm 92:4fc01daae5a5 1642 * @brief Set the specified DMA Tx Desc Own bit.
bogdanm 92:4fc01daae5a5 1643 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1644 * @retval None
bogdanm 92:4fc01daae5a5 1645 */
bogdanm 92:4fc01daae5a5 1646 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
bogdanm 92:4fc01daae5a5 1647
bogdanm 92:4fc01daae5a5 1648 /**
bogdanm 92:4fc01daae5a5 1649 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
bogdanm 92:4fc01daae5a5 1650 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1651 * @retval None
bogdanm 92:4fc01daae5a5 1652 */
bogdanm 92:4fc01daae5a5 1653 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
bogdanm 92:4fc01daae5a5 1654
bogdanm 92:4fc01daae5a5 1655 /**
bogdanm 92:4fc01daae5a5 1656 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
bogdanm 92:4fc01daae5a5 1657 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1658 * @retval None
bogdanm 92:4fc01daae5a5 1659 */
bogdanm 92:4fc01daae5a5 1660 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
bogdanm 92:4fc01daae5a5 1661
bogdanm 92:4fc01daae5a5 1662 /**
bogdanm 92:4fc01daae5a5 1663 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
bogdanm 92:4fc01daae5a5 1664 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1665 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
bogdanm 92:4fc01daae5a5 1666 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 1667 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
bogdanm 92:4fc01daae5a5 1668 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
bogdanm 92:4fc01daae5a5 1669 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
Kojto 122:f9eeca106725 1670 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
bogdanm 92:4fc01daae5a5 1671 * @retval None
bogdanm 92:4fc01daae5a5 1672 */
bogdanm 92:4fc01daae5a5 1673 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
bogdanm 92:4fc01daae5a5 1674
bogdanm 92:4fc01daae5a5 1675 /**
bogdanm 92:4fc01daae5a5 1676 * @brief Enables the DMA Tx Desc CRC.
bogdanm 92:4fc01daae5a5 1677 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1678 * @retval None
bogdanm 92:4fc01daae5a5 1679 */
bogdanm 92:4fc01daae5a5 1680 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
bogdanm 92:4fc01daae5a5 1681
bogdanm 92:4fc01daae5a5 1682 /**
bogdanm 92:4fc01daae5a5 1683 * @brief Disables the DMA Tx Desc CRC.
bogdanm 92:4fc01daae5a5 1684 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1685 * @retval None
bogdanm 92:4fc01daae5a5 1686 */
bogdanm 92:4fc01daae5a5 1687 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
bogdanm 92:4fc01daae5a5 1688
bogdanm 92:4fc01daae5a5 1689 /**
bogdanm 92:4fc01daae5a5 1690 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
bogdanm 92:4fc01daae5a5 1691 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1692 * @retval None
bogdanm 92:4fc01daae5a5 1693 */
bogdanm 92:4fc01daae5a5 1694 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
bogdanm 92:4fc01daae5a5 1695
bogdanm 92:4fc01daae5a5 1696 /**
bogdanm 92:4fc01daae5a5 1697 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
bogdanm 92:4fc01daae5a5 1698 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1699 * @retval None
bogdanm 92:4fc01daae5a5 1700 */
bogdanm 92:4fc01daae5a5 1701 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
bogdanm 92:4fc01daae5a5 1702
bogdanm 92:4fc01daae5a5 1703 /**
bogdanm 92:4fc01daae5a5 1704 * @brief Enables the specified ETHERNET MAC interrupts.
bogdanm 92:4fc01daae5a5 1705 * @param __HANDLE__ : ETH Handle
bogdanm 92:4fc01daae5a5 1706 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
bogdanm 92:4fc01daae5a5 1707 * enabled or disabled.
bogdanm 92:4fc01daae5a5 1708 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 1709 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
bogdanm 92:4fc01daae5a5 1710 * @arg ETH_MAC_IT_PMT : PMT interrupt
bogdanm 92:4fc01daae5a5 1711 * @retval None
bogdanm 92:4fc01daae5a5 1712 */
bogdanm 92:4fc01daae5a5 1713 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 1714
bogdanm 92:4fc01daae5a5 1715 /**
bogdanm 92:4fc01daae5a5 1716 * @brief Disables the specified ETHERNET MAC interrupts.
bogdanm 92:4fc01daae5a5 1717 * @param __HANDLE__ : ETH Handle
bogdanm 92:4fc01daae5a5 1718 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
bogdanm 92:4fc01daae5a5 1719 * enabled or disabled.
bogdanm 92:4fc01daae5a5 1720 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 1721 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
bogdanm 92:4fc01daae5a5 1722 * @arg ETH_MAC_IT_PMT : PMT interrupt
bogdanm 92:4fc01daae5a5 1723 * @retval None
bogdanm 92:4fc01daae5a5 1724 */
bogdanm 92:4fc01daae5a5 1725 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
bogdanm 92:4fc01daae5a5 1726
bogdanm 92:4fc01daae5a5 1727 /**
bogdanm 92:4fc01daae5a5 1728 * @brief Initiate a Pause Control Frame (Full-duplex only).
bogdanm 92:4fc01daae5a5 1729 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1730 * @retval None
bogdanm 92:4fc01daae5a5 1731 */
bogdanm 92:4fc01daae5a5 1732 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
bogdanm 92:4fc01daae5a5 1733
bogdanm 92:4fc01daae5a5 1734 /**
bogdanm 92:4fc01daae5a5 1735 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
bogdanm 92:4fc01daae5a5 1736 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1737 * @retval The new state of flow control busy status bit (SET or RESET).
bogdanm 92:4fc01daae5a5 1738 */
bogdanm 92:4fc01daae5a5 1739 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
bogdanm 92:4fc01daae5a5 1740
bogdanm 92:4fc01daae5a5 1741 /**
bogdanm 92:4fc01daae5a5 1742 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
bogdanm 92:4fc01daae5a5 1743 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1744 * @retval None
bogdanm 92:4fc01daae5a5 1745 */
bogdanm 92:4fc01daae5a5 1746 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
bogdanm 92:4fc01daae5a5 1747
bogdanm 92:4fc01daae5a5 1748 /**
bogdanm 92:4fc01daae5a5 1749 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
bogdanm 92:4fc01daae5a5 1750 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1751 * @retval None
bogdanm 92:4fc01daae5a5 1752 */
bogdanm 92:4fc01daae5a5 1753 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
bogdanm 92:4fc01daae5a5 1754
bogdanm 92:4fc01daae5a5 1755 /**
bogdanm 92:4fc01daae5a5 1756 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
bogdanm 92:4fc01daae5a5 1757 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1758 * @param __FLAG__: specifies the flag to check.
bogdanm 92:4fc01daae5a5 1759 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 1760 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
bogdanm 92:4fc01daae5a5 1761 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
bogdanm 92:4fc01daae5a5 1762 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
bogdanm 92:4fc01daae5a5 1763 * @arg ETH_MAC_FLAG_MMC : MMC flag
bogdanm 92:4fc01daae5a5 1764 * @arg ETH_MAC_FLAG_PMT : PMT flag
bogdanm 92:4fc01daae5a5 1765 * @retval The state of ETHERNET MAC flag.
bogdanm 92:4fc01daae5a5 1766 */
bogdanm 92:4fc01daae5a5 1767 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
bogdanm 92:4fc01daae5a5 1768
bogdanm 92:4fc01daae5a5 1769 /**
bogdanm 92:4fc01daae5a5 1770 * @brief Enables the specified ETHERNET DMA interrupts.
bogdanm 92:4fc01daae5a5 1771 * @param __HANDLE__ : ETH Handle
bogdanm 92:4fc01daae5a5 1772 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto 99:dbbf35b96557 1773 * enabled @ref ETH_DMA_Interrupts
bogdanm 92:4fc01daae5a5 1774 * @retval None
bogdanm 92:4fc01daae5a5 1775 */
bogdanm 92:4fc01daae5a5 1776 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 1777
bogdanm 92:4fc01daae5a5 1778 /**
bogdanm 92:4fc01daae5a5 1779 * @brief Disables the specified ETHERNET DMA interrupts.
bogdanm 92:4fc01daae5a5 1780 * @param __HANDLE__ : ETH Handle
bogdanm 92:4fc01daae5a5 1781 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto 99:dbbf35b96557 1782 * disabled. @ref ETH_DMA_Interrupts
bogdanm 92:4fc01daae5a5 1783 * @retval None
bogdanm 92:4fc01daae5a5 1784 */
bogdanm 92:4fc01daae5a5 1785 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
bogdanm 92:4fc01daae5a5 1786
bogdanm 92:4fc01daae5a5 1787 /**
bogdanm 92:4fc01daae5a5 1788 * @brief Clears the ETHERNET DMA IT pending bit.
bogdanm 92:4fc01daae5a5 1789 * @param __HANDLE__ : ETH Handle
Kojto 99:dbbf35b96557 1790 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
bogdanm 92:4fc01daae5a5 1791 * @retval None
bogdanm 92:4fc01daae5a5 1792 */
bogdanm 92:4fc01daae5a5 1793 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
bogdanm 92:4fc01daae5a5 1794
bogdanm 92:4fc01daae5a5 1795 /**
bogdanm 92:4fc01daae5a5 1796 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
bogdanm 92:4fc01daae5a5 1797 * @param __HANDLE__: ETH Handle
Kojto 99:dbbf35b96557 1798 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
bogdanm 92:4fc01daae5a5 1799 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
bogdanm 92:4fc01daae5a5 1800 */
bogdanm 92:4fc01daae5a5 1801 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
bogdanm 92:4fc01daae5a5 1802
bogdanm 92:4fc01daae5a5 1803 /**
bogdanm 92:4fc01daae5a5 1804 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
bogdanm 92:4fc01daae5a5 1805 * @param __HANDLE__: ETH Handle
Kojto 99:dbbf35b96557 1806 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
bogdanm 92:4fc01daae5a5 1807 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
bogdanm 92:4fc01daae5a5 1808 */
bogdanm 92:4fc01daae5a5 1809 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
bogdanm 92:4fc01daae5a5 1810
bogdanm 92:4fc01daae5a5 1811 /**
bogdanm 92:4fc01daae5a5 1812 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
bogdanm 92:4fc01daae5a5 1813 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1814 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
bogdanm 92:4fc01daae5a5 1815 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 1816 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
bogdanm 92:4fc01daae5a5 1817 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
bogdanm 92:4fc01daae5a5 1818 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
bogdanm 92:4fc01daae5a5 1819 */
bogdanm 92:4fc01daae5a5 1820 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
bogdanm 92:4fc01daae5a5 1821
bogdanm 92:4fc01daae5a5 1822 /**
bogdanm 92:4fc01daae5a5 1823 * @brief Set the DMA Receive status watchdog timer register value
bogdanm 92:4fc01daae5a5 1824 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1825 * @param __VALUE__: DMA Receive status watchdog timer register value
bogdanm 92:4fc01daae5a5 1826 * @retval None
bogdanm 92:4fc01daae5a5 1827 */
bogdanm 92:4fc01daae5a5 1828 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
bogdanm 92:4fc01daae5a5 1829
bogdanm 92:4fc01daae5a5 1830 /**
bogdanm 92:4fc01daae5a5 1831 * @brief Enables any unicast packet filtered by the MAC address
bogdanm 92:4fc01daae5a5 1832 * recognition to be a wake-up frame.
bogdanm 92:4fc01daae5a5 1833 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1834 * @retval None
bogdanm 92:4fc01daae5a5 1835 */
bogdanm 92:4fc01daae5a5 1836 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
bogdanm 92:4fc01daae5a5 1837
bogdanm 92:4fc01daae5a5 1838 /**
bogdanm 92:4fc01daae5a5 1839 * @brief Disables any unicast packet filtered by the MAC address
bogdanm 92:4fc01daae5a5 1840 * recognition to be a wake-up frame.
bogdanm 92:4fc01daae5a5 1841 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1842 * @retval None
bogdanm 92:4fc01daae5a5 1843 */
bogdanm 92:4fc01daae5a5 1844 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
bogdanm 92:4fc01daae5a5 1845
bogdanm 92:4fc01daae5a5 1846 /**
bogdanm 92:4fc01daae5a5 1847 * @brief Enables the MAC Wake-Up Frame Detection.
bogdanm 92:4fc01daae5a5 1848 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1849 * @retval None
bogdanm 92:4fc01daae5a5 1850 */
bogdanm 92:4fc01daae5a5 1851 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
bogdanm 92:4fc01daae5a5 1852
bogdanm 92:4fc01daae5a5 1853 /**
bogdanm 92:4fc01daae5a5 1854 * @brief Disables the MAC Wake-Up Frame Detection.
bogdanm 92:4fc01daae5a5 1855 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1856 * @retval None
bogdanm 92:4fc01daae5a5 1857 */
bogdanm 92:4fc01daae5a5 1858 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
bogdanm 92:4fc01daae5a5 1859
bogdanm 92:4fc01daae5a5 1860 /**
bogdanm 92:4fc01daae5a5 1861 * @brief Enables the MAC Magic Packet Detection.
bogdanm 92:4fc01daae5a5 1862 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1863 * @retval None
bogdanm 92:4fc01daae5a5 1864 */
bogdanm 92:4fc01daae5a5 1865 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
bogdanm 92:4fc01daae5a5 1866
bogdanm 92:4fc01daae5a5 1867 /**
bogdanm 92:4fc01daae5a5 1868 * @brief Disables the MAC Magic Packet Detection.
bogdanm 92:4fc01daae5a5 1869 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1870 * @retval None
bogdanm 92:4fc01daae5a5 1871 */
bogdanm 92:4fc01daae5a5 1872 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
bogdanm 92:4fc01daae5a5 1873
bogdanm 92:4fc01daae5a5 1874 /**
bogdanm 92:4fc01daae5a5 1875 * @brief Enables the MAC Power Down.
bogdanm 92:4fc01daae5a5 1876 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1877 * @retval None
bogdanm 92:4fc01daae5a5 1878 */
bogdanm 92:4fc01daae5a5 1879 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
bogdanm 92:4fc01daae5a5 1880
bogdanm 92:4fc01daae5a5 1881 /**
bogdanm 92:4fc01daae5a5 1882 * @brief Disables the MAC Power Down.
bogdanm 92:4fc01daae5a5 1883 * @param __HANDLE__: ETH Handle
bogdanm 92:4fc01daae5a5 1884 * @retval None
bogdanm 92:4fc01daae5a5 1885 */
bogdanm 92:4fc01daae5a5 1886 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
bogdanm 92:4fc01daae5a5 1887
bogdanm 92:4fc01daae5a5 1888 /**
bogdanm 92:4fc01daae5a5 1889 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
bogdanm 92:4fc01daae5a5 1890 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1891 * @param __FLAG__: specifies the flag to check.
bogdanm 92:4fc01daae5a5 1892 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 1893 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
bogdanm 92:4fc01daae5a5 1894 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
bogdanm 92:4fc01daae5a5 1895 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
bogdanm 92:4fc01daae5a5 1896 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
bogdanm 92:4fc01daae5a5 1897 */
bogdanm 92:4fc01daae5a5 1898 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
bogdanm 92:4fc01daae5a5 1899
bogdanm 92:4fc01daae5a5 1900 /**
bogdanm 92:4fc01daae5a5 1901 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
bogdanm 92:4fc01daae5a5 1902 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1903 * @retval None
bogdanm 92:4fc01daae5a5 1904 */
bogdanm 92:4fc01daae5a5 1905 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
bogdanm 92:4fc01daae5a5 1906
bogdanm 92:4fc01daae5a5 1907 /**
bogdanm 92:4fc01daae5a5 1908 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
bogdanm 92:4fc01daae5a5 1909 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1910 * @retval None
bogdanm 92:4fc01daae5a5 1911 */
bogdanm 92:4fc01daae5a5 1912 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
bogdanm 92:4fc01daae5a5 1913 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
bogdanm 92:4fc01daae5a5 1914
bogdanm 92:4fc01daae5a5 1915 /**
bogdanm 92:4fc01daae5a5 1916 * @brief Enables the MMC Counter Freeze.
bogdanm 92:4fc01daae5a5 1917 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1918 * @retval None
bogdanm 92:4fc01daae5a5 1919 */
bogdanm 92:4fc01daae5a5 1920 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
bogdanm 92:4fc01daae5a5 1921
bogdanm 92:4fc01daae5a5 1922 /**
bogdanm 92:4fc01daae5a5 1923 * @brief Disables the MMC Counter Freeze.
bogdanm 92:4fc01daae5a5 1924 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1925 * @retval None
bogdanm 92:4fc01daae5a5 1926 */
bogdanm 92:4fc01daae5a5 1927 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
bogdanm 92:4fc01daae5a5 1928
bogdanm 92:4fc01daae5a5 1929 /**
bogdanm 92:4fc01daae5a5 1930 * @brief Enables the MMC Reset On Read.
bogdanm 92:4fc01daae5a5 1931 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1932 * @retval None
bogdanm 92:4fc01daae5a5 1933 */
bogdanm 92:4fc01daae5a5 1934 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
bogdanm 92:4fc01daae5a5 1935
bogdanm 92:4fc01daae5a5 1936 /**
bogdanm 92:4fc01daae5a5 1937 * @brief Disables the MMC Reset On Read.
bogdanm 92:4fc01daae5a5 1938 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1939 * @retval None
bogdanm 92:4fc01daae5a5 1940 */
bogdanm 92:4fc01daae5a5 1941 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
bogdanm 92:4fc01daae5a5 1942
bogdanm 92:4fc01daae5a5 1943 /**
bogdanm 92:4fc01daae5a5 1944 * @brief Enables the MMC Counter Stop Rollover.
bogdanm 92:4fc01daae5a5 1945 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1946 * @retval None
bogdanm 92:4fc01daae5a5 1947 */
bogdanm 92:4fc01daae5a5 1948 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
bogdanm 92:4fc01daae5a5 1949
bogdanm 92:4fc01daae5a5 1950 /**
bogdanm 92:4fc01daae5a5 1951 * @brief Disables the MMC Counter Stop Rollover.
bogdanm 92:4fc01daae5a5 1952 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1953 * @retval None
bogdanm 92:4fc01daae5a5 1954 */
bogdanm 92:4fc01daae5a5 1955 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
bogdanm 92:4fc01daae5a5 1956
bogdanm 92:4fc01daae5a5 1957 /**
bogdanm 92:4fc01daae5a5 1958 * @brief Resets the MMC Counters.
bogdanm 92:4fc01daae5a5 1959 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1960 * @retval None
bogdanm 92:4fc01daae5a5 1961 */
bogdanm 92:4fc01daae5a5 1962 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
bogdanm 92:4fc01daae5a5 1963
bogdanm 92:4fc01daae5a5 1964 /**
bogdanm 92:4fc01daae5a5 1965 * @brief Enables the specified ETHERNET MMC Rx interrupts.
bogdanm 92:4fc01daae5a5 1966 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1967 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm 92:4fc01daae5a5 1968 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 1969 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
bogdanm 92:4fc01daae5a5 1970 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
bogdanm 92:4fc01daae5a5 1971 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
bogdanm 92:4fc01daae5a5 1972 * @retval None
bogdanm 92:4fc01daae5a5 1973 */
Kojto 122:f9eeca106725 1974 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
bogdanm 92:4fc01daae5a5 1975 /**
bogdanm 92:4fc01daae5a5 1976 * @brief Disables the specified ETHERNET MMC Rx interrupts.
bogdanm 92:4fc01daae5a5 1977 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1978 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm 92:4fc01daae5a5 1979 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 1980 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
bogdanm 92:4fc01daae5a5 1981 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
bogdanm 92:4fc01daae5a5 1982 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
bogdanm 92:4fc01daae5a5 1983 * @retval None
bogdanm 92:4fc01daae5a5 1984 */
Kojto 122:f9eeca106725 1985 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
bogdanm 92:4fc01daae5a5 1986 /**
bogdanm 92:4fc01daae5a5 1987 * @brief Enables the specified ETHERNET MMC Tx interrupts.
bogdanm 92:4fc01daae5a5 1988 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 1989 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm 92:4fc01daae5a5 1990 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 1991 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
bogdanm 92:4fc01daae5a5 1992 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
bogdanm 92:4fc01daae5a5 1993 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
bogdanm 92:4fc01daae5a5 1994 * @retval None
bogdanm 92:4fc01daae5a5 1995 */
bogdanm 92:4fc01daae5a5 1996 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 1997
bogdanm 92:4fc01daae5a5 1998 /**
bogdanm 92:4fc01daae5a5 1999 * @brief Disables the specified ETHERNET MMC Tx interrupts.
bogdanm 92:4fc01daae5a5 2000 * @param __HANDLE__: ETH Handle.
bogdanm 92:4fc01daae5a5 2001 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm 92:4fc01daae5a5 2002 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 2003 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
bogdanm 92:4fc01daae5a5 2004 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
bogdanm 92:4fc01daae5a5 2005 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
bogdanm 92:4fc01daae5a5 2006 * @retval None
bogdanm 92:4fc01daae5a5 2007 */
Kojto 99:dbbf35b96557 2008 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
Kojto 99:dbbf35b96557 2009
Kojto 99:dbbf35b96557 2010 /**
Kojto 99:dbbf35b96557 2011 * @brief Enables the ETH External interrupt line.
Kojto 99:dbbf35b96557 2012 * @retval None
Kojto 99:dbbf35b96557 2013 */
Kojto 99:dbbf35b96557 2014 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2015
Kojto 99:dbbf35b96557 2016 /**
Kojto 99:dbbf35b96557 2017 * @brief Disables the ETH External interrupt line.
Kojto 99:dbbf35b96557 2018 * @retval None
Kojto 99:dbbf35b96557 2019 */
Kojto 99:dbbf35b96557 2020 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2021
Kojto 99:dbbf35b96557 2022 /**
Kojto 99:dbbf35b96557 2023 * @brief Enable event on ETH External event line.
Kojto 99:dbbf35b96557 2024 * @retval None.
Kojto 99:dbbf35b96557 2025 */
Kojto 99:dbbf35b96557 2026 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2027
Kojto 99:dbbf35b96557 2028 /**
Kojto 99:dbbf35b96557 2029 * @brief Disable event on ETH External event line
Kojto 99:dbbf35b96557 2030 * @retval None.
Kojto 99:dbbf35b96557 2031 */
Kojto 99:dbbf35b96557 2032 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2033
Kojto 99:dbbf35b96557 2034 /**
Kojto 99:dbbf35b96557 2035 * @brief Get flag of the ETH External interrupt line.
Kojto 99:dbbf35b96557 2036 * @retval None
Kojto 99:dbbf35b96557 2037 */
Kojto 99:dbbf35b96557 2038 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2039
Kojto 99:dbbf35b96557 2040 /**
Kojto 99:dbbf35b96557 2041 * @brief Clear flag of the ETH External interrupt line.
Kojto 99:dbbf35b96557 2042 * @retval None
Kojto 99:dbbf35b96557 2043 */
Kojto 99:dbbf35b96557 2044 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
bogdanm 92:4fc01daae5a5 2045
Kojto 99:dbbf35b96557 2046 /**
Kojto 99:dbbf35b96557 2047 * @brief Enables rising edge trigger to the ETH External interrupt line.
Kojto 99:dbbf35b96557 2048 * @retval None
Kojto 99:dbbf35b96557 2049 */
Kojto 99:dbbf35b96557 2050 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
Kojto 99:dbbf35b96557 2051
Kojto 99:dbbf35b96557 2052 /**
Kojto 99:dbbf35b96557 2053 * @brief Disables the rising edge trigger to the ETH External interrupt line.
Kojto 99:dbbf35b96557 2054 * @retval None
Kojto 99:dbbf35b96557 2055 */
Kojto 122:f9eeca106725 2056 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2057
Kojto 99:dbbf35b96557 2058 /**
Kojto 99:dbbf35b96557 2059 * @brief Enables falling edge trigger to the ETH External interrupt line.
Kojto 99:dbbf35b96557 2060 * @retval None
Kojto 99:dbbf35b96557 2061 */
Kojto 99:dbbf35b96557 2062 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2063
Kojto 99:dbbf35b96557 2064 /**
Kojto 99:dbbf35b96557 2065 * @brief Disables falling edge trigger to the ETH External interrupt line.
Kojto 99:dbbf35b96557 2066 * @retval None
Kojto 99:dbbf35b96557 2067 */
Kojto 99:dbbf35b96557 2068 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 99:dbbf35b96557 2069
Kojto 99:dbbf35b96557 2070 /**
Kojto 99:dbbf35b96557 2071 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
Kojto 99:dbbf35b96557 2072 * @retval None
Kojto 99:dbbf35b96557 2073 */
Kojto 122:f9eeca106725 2074 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
Kojto 122:f9eeca106725 2075 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
Kojto 122:f9eeca106725 2076 }while(0)
Kojto 99:dbbf35b96557 2077
Kojto 99:dbbf35b96557 2078 /**
Kojto 99:dbbf35b96557 2079 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
Kojto 99:dbbf35b96557 2080 * @retval None
Kojto 99:dbbf35b96557 2081 */
Kojto 122:f9eeca106725 2082 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
Kojto 122:f9eeca106725 2083 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
Kojto 122:f9eeca106725 2084 }while(0)
Kojto 99:dbbf35b96557 2085
Kojto 99:dbbf35b96557 2086 /**
Kojto 99:dbbf35b96557 2087 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 99:dbbf35b96557 2088 * @retval None.
Kojto 99:dbbf35b96557 2089 */
Kojto 99:dbbf35b96557 2090 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
bogdanm 92:4fc01daae5a5 2091
bogdanm 92:4fc01daae5a5 2092 /**
bogdanm 92:4fc01daae5a5 2093 * @}
bogdanm 92:4fc01daae5a5 2094 */
bogdanm 92:4fc01daae5a5 2095 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 2096
Kojto 99:dbbf35b96557 2097 /** @addtogroup ETH_Exported_Functions
Kojto 99:dbbf35b96557 2098 * @{
Kojto 99:dbbf35b96557 2099 */
Kojto 99:dbbf35b96557 2100
bogdanm 92:4fc01daae5a5 2101 /* Initialization and de-initialization functions ****************************/
Kojto 99:dbbf35b96557 2102
Kojto 99:dbbf35b96557 2103 /** @addtogroup ETH_Exported_Functions_Group1
Kojto 99:dbbf35b96557 2104 * @{
Kojto 99:dbbf35b96557 2105 */
bogdanm 92:4fc01daae5a5 2106 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
bogdanm 92:4fc01daae5a5 2107 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
bogdanm 92:4fc01daae5a5 2108 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
bogdanm 92:4fc01daae5a5 2109 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
bogdanm 92:4fc01daae5a5 2110 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
bogdanm 92:4fc01daae5a5 2111 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
bogdanm 92:4fc01daae5a5 2112
Kojto 99:dbbf35b96557 2113 /**
Kojto 99:dbbf35b96557 2114 * @}
Kojto 99:dbbf35b96557 2115 */
bogdanm 92:4fc01daae5a5 2116 /* IO operation functions ****************************************************/
Kojto 99:dbbf35b96557 2117
Kojto 99:dbbf35b96557 2118 /** @addtogroup ETH_Exported_Functions_Group2
Kojto 99:dbbf35b96557 2119 * @{
Kojto 99:dbbf35b96557 2120 */
bogdanm 92:4fc01daae5a5 2121 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
bogdanm 92:4fc01daae5a5 2122 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
Kojto 99:dbbf35b96557 2123 /* Communication with PHY functions*/
Kojto 99:dbbf35b96557 2124 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
Kojto 99:dbbf35b96557 2125 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
Kojto 99:dbbf35b96557 2126 /* Non-Blocking mode: Interrupt */
bogdanm 92:4fc01daae5a5 2127 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
bogdanm 92:4fc01daae5a5 2128 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
Kojto 99:dbbf35b96557 2129 /* Callback in non blocking modes (Interrupt) */
bogdanm 92:4fc01daae5a5 2130 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
bogdanm 92:4fc01daae5a5 2131 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
bogdanm 92:4fc01daae5a5 2132 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
Kojto 99:dbbf35b96557 2133 /**
Kojto 99:dbbf35b96557 2134 * @}
Kojto 99:dbbf35b96557 2135 */
bogdanm 92:4fc01daae5a5 2136
bogdanm 92:4fc01daae5a5 2137 /* Peripheral Control functions **********************************************/
Kojto 99:dbbf35b96557 2138
Kojto 99:dbbf35b96557 2139 /** @addtogroup ETH_Exported_Functions_Group3
Kojto 99:dbbf35b96557 2140 * @{
Kojto 99:dbbf35b96557 2141 */
Kojto 99:dbbf35b96557 2142
bogdanm 92:4fc01daae5a5 2143 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
bogdanm 92:4fc01daae5a5 2144 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
bogdanm 92:4fc01daae5a5 2145 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
bogdanm 92:4fc01daae5a5 2146 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
bogdanm 92:4fc01daae5a5 2147 /**
bogdanm 92:4fc01daae5a5 2148 * @}
bogdanm 92:4fc01daae5a5 2149 */
bogdanm 92:4fc01daae5a5 2150
Kojto 99:dbbf35b96557 2151 /* Peripheral State functions ************************************************/
Kojto 99:dbbf35b96557 2152
Kojto 99:dbbf35b96557 2153 /** @addtogroup ETH_Exported_Functions_Group4
Kojto 99:dbbf35b96557 2154 * @{
Kojto 99:dbbf35b96557 2155 */
Kojto 99:dbbf35b96557 2156 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
Kojto 99:dbbf35b96557 2157 /**
Kojto 99:dbbf35b96557 2158 * @}
Kojto 99:dbbf35b96557 2159 */
Kojto 99:dbbf35b96557 2160
bogdanm 92:4fc01daae5a5 2161 /**
bogdanm 92:4fc01daae5a5 2162 * @}
Kojto 99:dbbf35b96557 2163 */
Kojto 99:dbbf35b96557 2164
Kojto 99:dbbf35b96557 2165 /**
Kojto 99:dbbf35b96557 2166 * @}
Kojto 99:dbbf35b96557 2167 */
Kojto 99:dbbf35b96557 2168
Kojto 99:dbbf35b96557 2169 /**
Kojto 99:dbbf35b96557 2170 * @}
Kojto 99:dbbf35b96557 2171 */
Kojto 99:dbbf35b96557 2172
Kojto 110:165afa46840b 2173 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
Kojto 110:165afa46840b 2174 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
bogdanm 92:4fc01daae5a5 2175
bogdanm 92:4fc01daae5a5 2176 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 2177 }
bogdanm 92:4fc01daae5a5 2178 #endif
bogdanm 92:4fc01daae5a5 2179
bogdanm 92:4fc01daae5a5 2180 #endif /* __STM32F4xx_HAL_ETH_H */
bogdanm 92:4fc01daae5a5 2181
bogdanm 92:4fc01daae5a5 2182
bogdanm 92:4fc01daae5a5 2183 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/