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TARGET_DISCO_F407VG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h@161:aa5281ff4a02, 2018-02-16 (annotated)
- Committer:
- AnnaBridge
- Date:
- Fri Feb 16 16:16:41 2018 +0000
- Revision:
- 161:aa5281ff4a02
- Child:
- 163:e59c8e839560
mbed library. Release version 159.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 161:aa5281ff4a02 | 1 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 2 | ****************************************************************************** |
| AnnaBridge | 161:aa5281ff4a02 | 3 | * @file stm32f4xx_hal_spi.h |
| AnnaBridge | 161:aa5281ff4a02 | 4 | * @author MCD Application Team |
| AnnaBridge | 161:aa5281ff4a02 | 5 | * @version V1.7.1 |
| AnnaBridge | 161:aa5281ff4a02 | 6 | * @date 14-April-2017 |
| AnnaBridge | 161:aa5281ff4a02 | 7 | * @brief Header file of SPI HAL module. |
| AnnaBridge | 161:aa5281ff4a02 | 8 | ****************************************************************************** |
| AnnaBridge | 161:aa5281ff4a02 | 9 | * @attention |
| AnnaBridge | 161:aa5281ff4a02 | 10 | * |
| AnnaBridge | 161:aa5281ff4a02 | 11 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 161:aa5281ff4a02 | 12 | * |
| AnnaBridge | 161:aa5281ff4a02 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 161:aa5281ff4a02 | 14 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 161:aa5281ff4a02 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 161:aa5281ff4a02 | 16 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 161:aa5281ff4a02 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 161:aa5281ff4a02 | 18 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 161:aa5281ff4a02 | 19 | * and/or other materials provided with the distribution. |
| AnnaBridge | 161:aa5281ff4a02 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 161:aa5281ff4a02 | 21 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 161:aa5281ff4a02 | 22 | * without specific prior written permission. |
| AnnaBridge | 161:aa5281ff4a02 | 23 | * |
| AnnaBridge | 161:aa5281ff4a02 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 161:aa5281ff4a02 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 161:aa5281ff4a02 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 161:aa5281ff4a02 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 161:aa5281ff4a02 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 161:aa5281ff4a02 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 161:aa5281ff4a02 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 161:aa5281ff4a02 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 161:aa5281ff4a02 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 161:aa5281ff4a02 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 161:aa5281ff4a02 | 34 | * |
| AnnaBridge | 161:aa5281ff4a02 | 35 | ****************************************************************************** |
| AnnaBridge | 161:aa5281ff4a02 | 36 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 37 | |
| AnnaBridge | 161:aa5281ff4a02 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 161:aa5281ff4a02 | 39 | #ifndef __STM32F4xx_HAL_SPI_H |
| AnnaBridge | 161:aa5281ff4a02 | 40 | #define __STM32F4xx_HAL_SPI_H |
| AnnaBridge | 161:aa5281ff4a02 | 41 | |
| AnnaBridge | 161:aa5281ff4a02 | 42 | #ifdef __cplusplus |
| AnnaBridge | 161:aa5281ff4a02 | 43 | extern "C" { |
| AnnaBridge | 161:aa5281ff4a02 | 44 | #endif |
| AnnaBridge | 161:aa5281ff4a02 | 45 | |
| AnnaBridge | 161:aa5281ff4a02 | 46 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 161:aa5281ff4a02 | 47 | #include "stm32f4xx_hal_def.h" |
| AnnaBridge | 161:aa5281ff4a02 | 48 | |
| AnnaBridge | 161:aa5281ff4a02 | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| AnnaBridge | 161:aa5281ff4a02 | 50 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 51 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 52 | |
| AnnaBridge | 161:aa5281ff4a02 | 53 | /** @addtogroup SPI |
| AnnaBridge | 161:aa5281ff4a02 | 54 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 55 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 56 | |
| AnnaBridge | 161:aa5281ff4a02 | 57 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 161:aa5281ff4a02 | 58 | /** @defgroup SPI_Exported_Types SPI Exported Types |
| AnnaBridge | 161:aa5281ff4a02 | 59 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 60 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 61 | |
| AnnaBridge | 161:aa5281ff4a02 | 62 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 63 | * @brief SPI Configuration Structure definition |
| AnnaBridge | 161:aa5281ff4a02 | 64 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 65 | typedef struct |
| AnnaBridge | 161:aa5281ff4a02 | 66 | { |
| AnnaBridge | 161:aa5281ff4a02 | 67 | uint32_t Mode; /*!< Specifies the SPI operating mode. |
| AnnaBridge | 161:aa5281ff4a02 | 68 | This parameter can be a value of @ref SPI_Mode */ |
| AnnaBridge | 161:aa5281ff4a02 | 69 | |
| AnnaBridge | 161:aa5281ff4a02 | 70 | uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. |
| AnnaBridge | 161:aa5281ff4a02 | 71 | This parameter can be a value of @ref SPI_Direction */ |
| AnnaBridge | 161:aa5281ff4a02 | 72 | |
| AnnaBridge | 161:aa5281ff4a02 | 73 | uint32_t DataSize; /*!< Specifies the SPI data size. |
| AnnaBridge | 161:aa5281ff4a02 | 74 | This parameter can be a value of @ref SPI_Data_Size */ |
| AnnaBridge | 161:aa5281ff4a02 | 75 | |
| AnnaBridge | 161:aa5281ff4a02 | 76 | uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. |
| AnnaBridge | 161:aa5281ff4a02 | 77 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
| AnnaBridge | 161:aa5281ff4a02 | 78 | |
| AnnaBridge | 161:aa5281ff4a02 | 79 | uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. |
| AnnaBridge | 161:aa5281ff4a02 | 80 | This parameter can be a value of @ref SPI_Clock_Phase */ |
| AnnaBridge | 161:aa5281ff4a02 | 81 | |
| AnnaBridge | 161:aa5281ff4a02 | 82 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by |
| AnnaBridge | 161:aa5281ff4a02 | 83 | hardware (NSS pin) or by software using the SSI bit. |
| AnnaBridge | 161:aa5281ff4a02 | 84 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
| AnnaBridge | 161:aa5281ff4a02 | 85 | |
| AnnaBridge | 161:aa5281ff4a02 | 86 | uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
| AnnaBridge | 161:aa5281ff4a02 | 87 | used to configure the transmit and receive SCK clock. |
| AnnaBridge | 161:aa5281ff4a02 | 88 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| AnnaBridge | 161:aa5281ff4a02 | 89 | @note The communication clock is derived from the master |
| AnnaBridge | 161:aa5281ff4a02 | 90 | clock. The slave clock does not need to be set. */ |
| AnnaBridge | 161:aa5281ff4a02 | 91 | |
| AnnaBridge | 161:aa5281ff4a02 | 92 | uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
| AnnaBridge | 161:aa5281ff4a02 | 93 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
| AnnaBridge | 161:aa5281ff4a02 | 94 | |
| AnnaBridge | 161:aa5281ff4a02 | 95 | uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. |
| AnnaBridge | 161:aa5281ff4a02 | 96 | This parameter can be a value of @ref SPI_TI_mode */ |
| AnnaBridge | 161:aa5281ff4a02 | 97 | |
| AnnaBridge | 161:aa5281ff4a02 | 98 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
| AnnaBridge | 161:aa5281ff4a02 | 99 | This parameter can be a value of @ref SPI_CRC_Calculation */ |
| AnnaBridge | 161:aa5281ff4a02 | 100 | |
| AnnaBridge | 161:aa5281ff4a02 | 101 | uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. |
| AnnaBridge | 161:aa5281ff4a02 | 102 | This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ |
| AnnaBridge | 161:aa5281ff4a02 | 103 | }SPI_InitTypeDef; |
| AnnaBridge | 161:aa5281ff4a02 | 104 | |
| AnnaBridge | 161:aa5281ff4a02 | 105 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 106 | * @brief HAL SPI State structure definition |
| AnnaBridge | 161:aa5281ff4a02 | 107 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 108 | typedef enum |
| AnnaBridge | 161:aa5281ff4a02 | 109 | { |
| AnnaBridge | 161:aa5281ff4a02 | 110 | HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ |
| AnnaBridge | 161:aa5281ff4a02 | 111 | HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
| AnnaBridge | 161:aa5281ff4a02 | 112 | HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ |
| AnnaBridge | 161:aa5281ff4a02 | 113 | HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ |
| AnnaBridge | 161:aa5281ff4a02 | 114 | HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ |
| AnnaBridge | 161:aa5281ff4a02 | 115 | HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ |
| AnnaBridge | 161:aa5281ff4a02 | 116 | HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */ |
| AnnaBridge | 161:aa5281ff4a02 | 117 | }HAL_SPI_StateTypeDef; |
| AnnaBridge | 161:aa5281ff4a02 | 118 | |
| AnnaBridge | 161:aa5281ff4a02 | 119 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 120 | * @brief SPI handle Structure definition |
| AnnaBridge | 161:aa5281ff4a02 | 121 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 122 | typedef struct __SPI_HandleTypeDef |
| AnnaBridge | 161:aa5281ff4a02 | 123 | { |
| AnnaBridge | 161:aa5281ff4a02 | 124 | SPI_TypeDef *Instance; /* SPI registers base address */ |
| AnnaBridge | 161:aa5281ff4a02 | 125 | |
| AnnaBridge | 161:aa5281ff4a02 | 126 | SPI_InitTypeDef Init; /* SPI communication parameters */ |
| AnnaBridge | 161:aa5281ff4a02 | 127 | |
| AnnaBridge | 161:aa5281ff4a02 | 128 | uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ |
| AnnaBridge | 161:aa5281ff4a02 | 129 | |
| AnnaBridge | 161:aa5281ff4a02 | 130 | uint16_t TxXferSize; /* SPI Tx Transfer size */ |
| AnnaBridge | 161:aa5281ff4a02 | 131 | |
| AnnaBridge | 161:aa5281ff4a02 | 132 | __IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */ |
| AnnaBridge | 161:aa5281ff4a02 | 133 | |
| AnnaBridge | 161:aa5281ff4a02 | 134 | uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ |
| AnnaBridge | 161:aa5281ff4a02 | 135 | |
| AnnaBridge | 161:aa5281ff4a02 | 136 | uint16_t RxXferSize; /* SPI Rx Transfer size */ |
| AnnaBridge | 161:aa5281ff4a02 | 137 | |
| AnnaBridge | 161:aa5281ff4a02 | 138 | __IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */ |
| AnnaBridge | 161:aa5281ff4a02 | 139 | |
| AnnaBridge | 161:aa5281ff4a02 | 140 | void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */ |
| AnnaBridge | 161:aa5281ff4a02 | 141 | |
| AnnaBridge | 161:aa5281ff4a02 | 142 | void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */ |
| AnnaBridge | 161:aa5281ff4a02 | 143 | |
| AnnaBridge | 161:aa5281ff4a02 | 144 | DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */ |
| AnnaBridge | 161:aa5281ff4a02 | 145 | |
| AnnaBridge | 161:aa5281ff4a02 | 146 | DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */ |
| AnnaBridge | 161:aa5281ff4a02 | 147 | |
| AnnaBridge | 161:aa5281ff4a02 | 148 | HAL_LockTypeDef Lock; /* Locking object */ |
| AnnaBridge | 161:aa5281ff4a02 | 149 | |
| AnnaBridge | 161:aa5281ff4a02 | 150 | __IO HAL_SPI_StateTypeDef State; /* SPI communication state */ |
| AnnaBridge | 161:aa5281ff4a02 | 151 | |
| AnnaBridge | 161:aa5281ff4a02 | 152 | __IO uint32_t ErrorCode; /* SPI Error code */ |
| AnnaBridge | 161:aa5281ff4a02 | 153 | |
| AnnaBridge | 161:aa5281ff4a02 | 154 | }SPI_HandleTypeDef; |
| AnnaBridge | 161:aa5281ff4a02 | 155 | |
| AnnaBridge | 161:aa5281ff4a02 | 156 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 157 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 158 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 159 | |
| AnnaBridge | 161:aa5281ff4a02 | 160 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 161:aa5281ff4a02 | 161 | /** @defgroup SPI_Exported_Constants SPI Exported Constants |
| AnnaBridge | 161:aa5281ff4a02 | 162 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 163 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 164 | |
| AnnaBridge | 161:aa5281ff4a02 | 165 | /** @defgroup SPI_Error_Code SPI Error Code |
| AnnaBridge | 161:aa5281ff4a02 | 166 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 167 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 168 | #define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */ |
| AnnaBridge | 161:aa5281ff4a02 | 169 | #define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */ |
| AnnaBridge | 161:aa5281ff4a02 | 170 | #define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */ |
| AnnaBridge | 161:aa5281ff4a02 | 171 | #define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */ |
| AnnaBridge | 161:aa5281ff4a02 | 172 | #define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */ |
| AnnaBridge | 161:aa5281ff4a02 | 173 | #define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */ |
| AnnaBridge | 161:aa5281ff4a02 | 174 | #define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */ |
| AnnaBridge | 161:aa5281ff4a02 | 175 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 176 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 177 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 178 | |
| AnnaBridge | 161:aa5281ff4a02 | 179 | /** @defgroup SPI_Mode SPI Mode |
| AnnaBridge | 161:aa5281ff4a02 | 180 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 181 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 182 | #define SPI_MODE_SLAVE 0x00000000U |
| AnnaBridge | 161:aa5281ff4a02 | 183 | #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
| AnnaBridge | 161:aa5281ff4a02 | 184 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 185 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 186 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 187 | |
| AnnaBridge | 161:aa5281ff4a02 | 188 | /** @defgroup SPI_Direction SPI Direction Mode |
| AnnaBridge | 161:aa5281ff4a02 | 189 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 190 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 191 | #define SPI_DIRECTION_2LINES 0x00000000U |
| AnnaBridge | 161:aa5281ff4a02 | 192 | #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
| AnnaBridge | 161:aa5281ff4a02 | 193 | #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
| AnnaBridge | 161:aa5281ff4a02 | 194 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 195 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 196 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 197 | |
| AnnaBridge | 161:aa5281ff4a02 | 198 | /** @defgroup SPI_Data_Size SPI Data Size |
| AnnaBridge | 161:aa5281ff4a02 | 199 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 200 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 201 | #define SPI_DATASIZE_8BIT 0x00000000U |
| AnnaBridge | 161:aa5281ff4a02 | 202 | #define SPI_DATASIZE_16BIT SPI_CR1_DFF |
| AnnaBridge | 161:aa5281ff4a02 | 203 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 204 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 205 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 206 | |
| AnnaBridge | 161:aa5281ff4a02 | 207 | /** @defgroup SPI_Clock_Polarity SPI Clock Polarity |
| AnnaBridge | 161:aa5281ff4a02 | 208 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 209 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 210 | #define SPI_POLARITY_LOW 0x00000000U |
| AnnaBridge | 161:aa5281ff4a02 | 211 | #define SPI_POLARITY_HIGH SPI_CR1_CPOL |
| AnnaBridge | 161:aa5281ff4a02 | 212 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 213 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 214 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 215 | |
| AnnaBridge | 161:aa5281ff4a02 | 216 | /** @defgroup SPI_Clock_Phase SPI Clock Phase |
| AnnaBridge | 161:aa5281ff4a02 | 217 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 218 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 219 | #define SPI_PHASE_1EDGE 0x00000000U |
| AnnaBridge | 161:aa5281ff4a02 | 220 | #define SPI_PHASE_2EDGE SPI_CR1_CPHA |
| AnnaBridge | 161:aa5281ff4a02 | 221 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 222 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 223 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 224 | |
| AnnaBridge | 161:aa5281ff4a02 | 225 | /** @defgroup SPI_Slave_Select_management SPI Slave Select Management |
| AnnaBridge | 161:aa5281ff4a02 | 226 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 227 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 228 | #define SPI_NSS_SOFT SPI_CR1_SSM |
| AnnaBridge | 161:aa5281ff4a02 | 229 | #define SPI_NSS_HARD_INPUT 0x00000000U |
| AnnaBridge | 161:aa5281ff4a02 | 230 | #define SPI_NSS_HARD_OUTPUT 0x00040000U |
| AnnaBridge | 161:aa5281ff4a02 | 231 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 232 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 233 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 234 | |
| AnnaBridge | 161:aa5281ff4a02 | 235 | /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler |
| AnnaBridge | 161:aa5281ff4a02 | 236 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 237 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 238 | #define SPI_BAUDRATEPRESCALER_2 0x00000000U |
| AnnaBridge | 161:aa5281ff4a02 | 239 | #define SPI_BAUDRATEPRESCALER_4 0x00000008U |
| AnnaBridge | 161:aa5281ff4a02 | 240 | #define SPI_BAUDRATEPRESCALER_8 0x00000010U |
| AnnaBridge | 161:aa5281ff4a02 | 241 | #define SPI_BAUDRATEPRESCALER_16 0x00000018U |
| AnnaBridge | 161:aa5281ff4a02 | 242 | #define SPI_BAUDRATEPRESCALER_32 0x00000020U |
| AnnaBridge | 161:aa5281ff4a02 | 243 | #define SPI_BAUDRATEPRESCALER_64 0x00000028U |
| AnnaBridge | 161:aa5281ff4a02 | 244 | #define SPI_BAUDRATEPRESCALER_128 0x00000030U |
| AnnaBridge | 161:aa5281ff4a02 | 245 | #define SPI_BAUDRATEPRESCALER_256 0x00000038U |
| AnnaBridge | 161:aa5281ff4a02 | 246 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 247 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 248 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 249 | |
| AnnaBridge | 161:aa5281ff4a02 | 250 | /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission |
| AnnaBridge | 161:aa5281ff4a02 | 251 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 252 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 253 | #define SPI_FIRSTBIT_MSB 0x00000000U |
| AnnaBridge | 161:aa5281ff4a02 | 254 | #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
| AnnaBridge | 161:aa5281ff4a02 | 255 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 256 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 257 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 258 | |
| AnnaBridge | 161:aa5281ff4a02 | 259 | /** @defgroup SPI_TI_mode SPI TI Mode |
| AnnaBridge | 161:aa5281ff4a02 | 260 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 261 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 262 | #define SPI_TIMODE_DISABLE 0x00000000U |
| AnnaBridge | 161:aa5281ff4a02 | 263 | #define SPI_TIMODE_ENABLE SPI_CR2_FRF |
| AnnaBridge | 161:aa5281ff4a02 | 264 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 265 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 266 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 267 | |
| AnnaBridge | 161:aa5281ff4a02 | 268 | /** @defgroup SPI_CRC_Calculation SPI CRC Calculation |
| AnnaBridge | 161:aa5281ff4a02 | 269 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 270 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 271 | #define SPI_CRCCALCULATION_DISABLE 0x00000000U |
| AnnaBridge | 161:aa5281ff4a02 | 272 | #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
| AnnaBridge | 161:aa5281ff4a02 | 273 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 274 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 275 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 276 | |
| AnnaBridge | 161:aa5281ff4a02 | 277 | /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition |
| AnnaBridge | 161:aa5281ff4a02 | 278 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 279 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 280 | #define SPI_IT_TXE SPI_CR2_TXEIE |
| AnnaBridge | 161:aa5281ff4a02 | 281 | #define SPI_IT_RXNE SPI_CR2_RXNEIE |
| AnnaBridge | 161:aa5281ff4a02 | 282 | #define SPI_IT_ERR SPI_CR2_ERRIE |
| AnnaBridge | 161:aa5281ff4a02 | 283 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 284 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 285 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 286 | |
| AnnaBridge | 161:aa5281ff4a02 | 287 | /** @defgroup SPI_Flags_definition SPI Flags Definition |
| AnnaBridge | 161:aa5281ff4a02 | 288 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 289 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 290 | #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ |
| AnnaBridge | 161:aa5281ff4a02 | 291 | #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ |
| AnnaBridge | 161:aa5281ff4a02 | 292 | #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ |
| AnnaBridge | 161:aa5281ff4a02 | 293 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ |
| AnnaBridge | 161:aa5281ff4a02 | 294 | #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ |
| AnnaBridge | 161:aa5281ff4a02 | 295 | #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ |
| AnnaBridge | 161:aa5281ff4a02 | 296 | #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ |
| AnnaBridge | 161:aa5281ff4a02 | 297 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 298 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 299 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 300 | |
| AnnaBridge | 161:aa5281ff4a02 | 301 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 302 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 303 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 304 | |
| AnnaBridge | 161:aa5281ff4a02 | 305 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 161:aa5281ff4a02 | 306 | /** @defgroup SPI_Exported_Macros SPI Exported Macros |
| AnnaBridge | 161:aa5281ff4a02 | 307 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 308 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 309 | |
| AnnaBridge | 161:aa5281ff4a02 | 310 | /** @brief Reset SPI handle state. |
| AnnaBridge | 161:aa5281ff4a02 | 311 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 312 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 313 | * @retval None |
| AnnaBridge | 161:aa5281ff4a02 | 314 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 315 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
| AnnaBridge | 161:aa5281ff4a02 | 316 | |
| AnnaBridge | 161:aa5281ff4a02 | 317 | /** @brief Enable or disable the specified SPI interrupts. |
| AnnaBridge | 161:aa5281ff4a02 | 318 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 319 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 320 | * @param __INTERRUPT__: specifies the interrupt source to enable or disable. |
| AnnaBridge | 161:aa5281ff4a02 | 321 | * This parameter can be one of the following values: |
| AnnaBridge | 161:aa5281ff4a02 | 322 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 161:aa5281ff4a02 | 323 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 161:aa5281ff4a02 | 324 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 161:aa5281ff4a02 | 325 | * @retval None |
| AnnaBridge | 161:aa5281ff4a02 | 326 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 327 | #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) |
| AnnaBridge | 161:aa5281ff4a02 | 328 | #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) |
| AnnaBridge | 161:aa5281ff4a02 | 329 | |
| AnnaBridge | 161:aa5281ff4a02 | 330 | /** @brief Check whether the specified SPI interrupt source is enabled or not. |
| AnnaBridge | 161:aa5281ff4a02 | 331 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 332 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 333 | * @param __INTERRUPT__: specifies the SPI interrupt source to check. |
| AnnaBridge | 161:aa5281ff4a02 | 334 | * This parameter can be one of the following values: |
| AnnaBridge | 161:aa5281ff4a02 | 335 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 161:aa5281ff4a02 | 336 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 161:aa5281ff4a02 | 337 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 161:aa5281ff4a02 | 338 | * @retval The new state of __IT__ (TRUE or FALSE). |
| AnnaBridge | 161:aa5281ff4a02 | 339 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 340 | #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| AnnaBridge | 161:aa5281ff4a02 | 341 | |
| AnnaBridge | 161:aa5281ff4a02 | 342 | /** @brief Check whether the specified SPI flag is set or not. |
| AnnaBridge | 161:aa5281ff4a02 | 343 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 344 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 345 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 161:aa5281ff4a02 | 346 | * This parameter can be one of the following values: |
| AnnaBridge | 161:aa5281ff4a02 | 347 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
| AnnaBridge | 161:aa5281ff4a02 | 348 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
| AnnaBridge | 161:aa5281ff4a02 | 349 | * @arg SPI_FLAG_CRCERR: CRC error flag |
| AnnaBridge | 161:aa5281ff4a02 | 350 | * @arg SPI_FLAG_MODF: Mode fault flag |
| AnnaBridge | 161:aa5281ff4a02 | 351 | * @arg SPI_FLAG_OVR: Overrun flag |
| AnnaBridge | 161:aa5281ff4a02 | 352 | * @arg SPI_FLAG_BSY: Busy flag |
| AnnaBridge | 161:aa5281ff4a02 | 353 | * @arg SPI_FLAG_FRE: Frame format error flag |
| AnnaBridge | 161:aa5281ff4a02 | 354 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 161:aa5281ff4a02 | 355 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 356 | #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 161:aa5281ff4a02 | 357 | |
| AnnaBridge | 161:aa5281ff4a02 | 358 | /** @brief Clear the SPI CRCERR pending flag. |
| AnnaBridge | 161:aa5281ff4a02 | 359 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 360 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 361 | * @retval None |
| AnnaBridge | 161:aa5281ff4a02 | 362 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 363 | #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) |
| AnnaBridge | 161:aa5281ff4a02 | 364 | |
| AnnaBridge | 161:aa5281ff4a02 | 365 | /** @brief Clear the SPI MODF pending flag. |
| AnnaBridge | 161:aa5281ff4a02 | 366 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 367 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 368 | * @retval None |
| AnnaBridge | 161:aa5281ff4a02 | 369 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 370 | #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
| AnnaBridge | 161:aa5281ff4a02 | 371 | do{ \ |
| AnnaBridge | 161:aa5281ff4a02 | 372 | __IO uint32_t tmpreg_modf = 0x00U; \ |
| AnnaBridge | 161:aa5281ff4a02 | 373 | tmpreg_modf = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 161:aa5281ff4a02 | 374 | (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ |
| AnnaBridge | 161:aa5281ff4a02 | 375 | UNUSED(tmpreg_modf); \ |
| AnnaBridge | 161:aa5281ff4a02 | 376 | } while(0U) |
| AnnaBridge | 161:aa5281ff4a02 | 377 | |
| AnnaBridge | 161:aa5281ff4a02 | 378 | /** @brief Clear the SPI OVR pending flag. |
| AnnaBridge | 161:aa5281ff4a02 | 379 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 380 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 381 | * @retval None |
| AnnaBridge | 161:aa5281ff4a02 | 382 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 383 | #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
| AnnaBridge | 161:aa5281ff4a02 | 384 | do{ \ |
| AnnaBridge | 161:aa5281ff4a02 | 385 | __IO uint32_t tmpreg_ovr = 0x00U; \ |
| AnnaBridge | 161:aa5281ff4a02 | 386 | tmpreg_ovr = (__HANDLE__)->Instance->DR; \ |
| AnnaBridge | 161:aa5281ff4a02 | 387 | tmpreg_ovr = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 161:aa5281ff4a02 | 388 | UNUSED(tmpreg_ovr); \ |
| AnnaBridge | 161:aa5281ff4a02 | 389 | } while(0U) |
| AnnaBridge | 161:aa5281ff4a02 | 390 | |
| AnnaBridge | 161:aa5281ff4a02 | 391 | /** @brief Clear the SPI FRE pending flag. |
| AnnaBridge | 161:aa5281ff4a02 | 392 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 393 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 394 | * @retval None |
| AnnaBridge | 161:aa5281ff4a02 | 395 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 396 | #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ |
| AnnaBridge | 161:aa5281ff4a02 | 397 | do{ \ |
| AnnaBridge | 161:aa5281ff4a02 | 398 | __IO uint32_t tmpreg_fre = 0x00U; \ |
| AnnaBridge | 161:aa5281ff4a02 | 399 | tmpreg_fre = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 161:aa5281ff4a02 | 400 | UNUSED(tmpreg_fre); \ |
| AnnaBridge | 161:aa5281ff4a02 | 401 | }while(0U) |
| AnnaBridge | 161:aa5281ff4a02 | 402 | |
| AnnaBridge | 161:aa5281ff4a02 | 403 | /** @brief Enable the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 404 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 405 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 406 | * @retval None |
| AnnaBridge | 161:aa5281ff4a02 | 407 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 408 | #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) |
| AnnaBridge | 161:aa5281ff4a02 | 409 | |
| AnnaBridge | 161:aa5281ff4a02 | 410 | /** @brief Disable the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 411 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 412 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 413 | * @retval None |
| AnnaBridge | 161:aa5281ff4a02 | 414 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 415 | #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE)) |
| AnnaBridge | 161:aa5281ff4a02 | 416 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 417 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 418 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 419 | |
| AnnaBridge | 161:aa5281ff4a02 | 420 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 161:aa5281ff4a02 | 421 | /** @addtogroup SPI_Exported_Functions |
| AnnaBridge | 161:aa5281ff4a02 | 422 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 423 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 424 | |
| AnnaBridge | 161:aa5281ff4a02 | 425 | /** @addtogroup SPI_Exported_Functions_Group1 |
| AnnaBridge | 161:aa5281ff4a02 | 426 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 427 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 428 | /* Initialization/de-initialization functions **********************************/ |
| AnnaBridge | 161:aa5281ff4a02 | 429 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 430 | HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 431 | void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 432 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 433 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 434 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 435 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 436 | |
| AnnaBridge | 161:aa5281ff4a02 | 437 | /** @addtogroup SPI_Exported_Functions_Group2 |
| AnnaBridge | 161:aa5281ff4a02 | 438 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 439 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 440 | /* I/O operation functions *****************************************************/ |
| AnnaBridge | 161:aa5281ff4a02 | 441 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 161:aa5281ff4a02 | 442 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 161:aa5281ff4a02 | 443 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 161:aa5281ff4a02 | 444 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 161:aa5281ff4a02 | 445 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 161:aa5281ff4a02 | 446 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
| AnnaBridge | 161:aa5281ff4a02 | 447 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 161:aa5281ff4a02 | 448 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 161:aa5281ff4a02 | 449 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
| AnnaBridge | 161:aa5281ff4a02 | 450 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 451 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 452 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 453 | /* Transfer Abort functions */ |
| AnnaBridge | 161:aa5281ff4a02 | 454 | HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 455 | HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 456 | |
| AnnaBridge | 161:aa5281ff4a02 | 457 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 458 | void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 459 | void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 460 | void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 461 | void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 462 | void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 463 | void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 464 | void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 465 | void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 466 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 467 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 468 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 469 | |
| AnnaBridge | 161:aa5281ff4a02 | 470 | /** @addtogroup SPI_Exported_Functions_Group3 |
| AnnaBridge | 161:aa5281ff4a02 | 471 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 472 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 473 | /* Peripheral State and Error functions ***************************************/ |
| AnnaBridge | 161:aa5281ff4a02 | 474 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 475 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 161:aa5281ff4a02 | 476 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 477 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 478 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 479 | |
| AnnaBridge | 161:aa5281ff4a02 | 480 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 481 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 482 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 483 | |
| AnnaBridge | 161:aa5281ff4a02 | 484 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 161:aa5281ff4a02 | 485 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 161:aa5281ff4a02 | 486 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 161:aa5281ff4a02 | 487 | |
| AnnaBridge | 161:aa5281ff4a02 | 488 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 161:aa5281ff4a02 | 489 | /** @defgroup SPI_Private_Macros SPI Private Macros |
| AnnaBridge | 161:aa5281ff4a02 | 490 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 491 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 492 | |
| AnnaBridge | 161:aa5281ff4a02 | 493 | /** @brief Set the SPI transmit-only mode. |
| AnnaBridge | 161:aa5281ff4a02 | 494 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 495 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 496 | * @retval None |
| AnnaBridge | 161:aa5281ff4a02 | 497 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 498 | #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) |
| AnnaBridge | 161:aa5281ff4a02 | 499 | |
| AnnaBridge | 161:aa5281ff4a02 | 500 | /** @brief Set the SPI receive-only mode. |
| AnnaBridge | 161:aa5281ff4a02 | 501 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 502 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 503 | * @retval None |
| AnnaBridge | 161:aa5281ff4a02 | 504 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 505 | #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) |
| AnnaBridge | 161:aa5281ff4a02 | 506 | |
| AnnaBridge | 161:aa5281ff4a02 | 507 | /** @brief Reset the CRC calculation of the SPI. |
| AnnaBridge | 161:aa5281ff4a02 | 508 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 161:aa5281ff4a02 | 509 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 161:aa5281ff4a02 | 510 | * @retval None |
| AnnaBridge | 161:aa5281ff4a02 | 511 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 512 | #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\ |
| AnnaBridge | 161:aa5281ff4a02 | 513 | (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U) |
| AnnaBridge | 161:aa5281ff4a02 | 514 | |
| AnnaBridge | 161:aa5281ff4a02 | 515 | #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 516 | ((MODE) == SPI_MODE_MASTER)) |
| AnnaBridge | 161:aa5281ff4a02 | 517 | |
| AnnaBridge | 161:aa5281ff4a02 | 518 | #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 519 | ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 520 | ((MODE) == SPI_DIRECTION_1LINE)) |
| AnnaBridge | 161:aa5281ff4a02 | 521 | |
| AnnaBridge | 161:aa5281ff4a02 | 522 | #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) |
| AnnaBridge | 161:aa5281ff4a02 | 523 | |
| AnnaBridge | 161:aa5281ff4a02 | 524 | #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 525 | ((MODE) == SPI_DIRECTION_1LINE)) |
| AnnaBridge | 161:aa5281ff4a02 | 526 | |
| AnnaBridge | 161:aa5281ff4a02 | 527 | #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 528 | ((DATASIZE) == SPI_DATASIZE_8BIT)) |
| AnnaBridge | 161:aa5281ff4a02 | 529 | |
| AnnaBridge | 161:aa5281ff4a02 | 530 | #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 531 | ((CPOL) == SPI_POLARITY_HIGH)) |
| AnnaBridge | 161:aa5281ff4a02 | 532 | |
| AnnaBridge | 161:aa5281ff4a02 | 533 | #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 534 | ((CPHA) == SPI_PHASE_2EDGE)) |
| AnnaBridge | 161:aa5281ff4a02 | 535 | |
| AnnaBridge | 161:aa5281ff4a02 | 536 | #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 537 | ((NSS) == SPI_NSS_HARD_INPUT) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 538 | ((NSS) == SPI_NSS_HARD_OUTPUT)) |
| AnnaBridge | 161:aa5281ff4a02 | 539 | |
| AnnaBridge | 161:aa5281ff4a02 | 540 | #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 541 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 542 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 543 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 544 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 545 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 546 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 547 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) |
| AnnaBridge | 161:aa5281ff4a02 | 548 | |
| AnnaBridge | 161:aa5281ff4a02 | 549 | #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 550 | ((BIT) == SPI_FIRSTBIT_LSB)) |
| AnnaBridge | 161:aa5281ff4a02 | 551 | |
| AnnaBridge | 161:aa5281ff4a02 | 552 | #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 553 | ((MODE) == SPI_TIMODE_ENABLE)) |
| AnnaBridge | 161:aa5281ff4a02 | 554 | |
| AnnaBridge | 161:aa5281ff4a02 | 555 | #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ |
| AnnaBridge | 161:aa5281ff4a02 | 556 | ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) |
| AnnaBridge | 161:aa5281ff4a02 | 557 | |
| AnnaBridge | 161:aa5281ff4a02 | 558 | #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU)) |
| AnnaBridge | 161:aa5281ff4a02 | 559 | |
| AnnaBridge | 161:aa5281ff4a02 | 560 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 561 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 562 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 563 | |
| AnnaBridge | 161:aa5281ff4a02 | 564 | /* Private functions ---------------------------------------------------------*/ |
| AnnaBridge | 161:aa5281ff4a02 | 565 | /** @defgroup SPI_Private_Functions SPI Private Functions |
| AnnaBridge | 161:aa5281ff4a02 | 566 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 567 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 568 | |
| AnnaBridge | 161:aa5281ff4a02 | 569 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 570 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 571 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 572 | |
| AnnaBridge | 161:aa5281ff4a02 | 573 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 574 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 575 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 576 | |
| AnnaBridge | 161:aa5281ff4a02 | 577 | /** |
| AnnaBridge | 161:aa5281ff4a02 | 578 | * @} |
| AnnaBridge | 161:aa5281ff4a02 | 579 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 580 | |
| AnnaBridge | 161:aa5281ff4a02 | 581 | #ifdef __cplusplus |
| AnnaBridge | 161:aa5281ff4a02 | 582 | } |
| AnnaBridge | 161:aa5281ff4a02 | 583 | #endif |
| AnnaBridge | 161:aa5281ff4a02 | 584 | |
| AnnaBridge | 161:aa5281ff4a02 | 585 | #endif /* __STM32F4xx_HAL_SPI_H */ |
| AnnaBridge | 161:aa5281ff4a02 | 586 | |
| AnnaBridge | 161:aa5281ff4a02 | 587 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
