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TARGET_DISCO_F407VG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h@161:aa5281ff4a02, 2018-02-16 (annotated)

Committer:: AnnaBridge
Date:: Fri Feb 16 16:16:41 2018 +0000
Revision:: 161:aa5281ff4a02
Child:: 163:e59c8e839560

mbed library. Release version 159.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	161:aa5281ff4a02	1	/**
AnnaBridge	161:aa5281ff4a02	2	******************************************************************************
AnnaBridge	161:aa5281ff4a02	3	* @file stm32f4xx_hal_eth.h
AnnaBridge	161:aa5281ff4a02	4	* @author MCD Application Team
AnnaBridge	161:aa5281ff4a02	5	* @version V1.7.1
AnnaBridge	161:aa5281ff4a02	6	* @date 14-April-2017
AnnaBridge	161:aa5281ff4a02	7	* @brief Header file of ETH HAL module.
AnnaBridge	161:aa5281ff4a02	8	******************************************************************************
AnnaBridge	161:aa5281ff4a02	9	* @attention
AnnaBridge	161:aa5281ff4a02	10	*
AnnaBridge	161:aa5281ff4a02	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	161:aa5281ff4a02	12	*
AnnaBridge	161:aa5281ff4a02	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	161:aa5281ff4a02	14	* are permitted provided that the following conditions are met:
AnnaBridge	161:aa5281ff4a02	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	161:aa5281ff4a02	16	* this list of conditions and the following disclaimer.
AnnaBridge	161:aa5281ff4a02	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	161:aa5281ff4a02	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	161:aa5281ff4a02	19	* and/or other materials provided with the distribution.
AnnaBridge	161:aa5281ff4a02	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	161:aa5281ff4a02	21	* may be used to endorse or promote products derived from this software
AnnaBridge	161:aa5281ff4a02	22	* without specific prior written permission.
AnnaBridge	161:aa5281ff4a02	23	*
AnnaBridge	161:aa5281ff4a02	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	161:aa5281ff4a02	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	161:aa5281ff4a02	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	161:aa5281ff4a02	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	161:aa5281ff4a02	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	161:aa5281ff4a02	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	161:aa5281ff4a02	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	161:aa5281ff4a02	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	161:aa5281ff4a02	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	161:aa5281ff4a02	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	161:aa5281ff4a02	34	*
AnnaBridge	161:aa5281ff4a02	35	******************************************************************************
AnnaBridge	161:aa5281ff4a02	36	*/
AnnaBridge	161:aa5281ff4a02	37
AnnaBridge	161:aa5281ff4a02	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	161:aa5281ff4a02	39	#ifndef __STM32F4xx_HAL_ETH_H
AnnaBridge	161:aa5281ff4a02	40	#define __STM32F4xx_HAL_ETH_H
AnnaBridge	161:aa5281ff4a02	41
AnnaBridge	161:aa5281ff4a02	42	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	43	extern "C" {
AnnaBridge	161:aa5281ff4a02	44	#endif
AnnaBridge	161:aa5281ff4a02	45
AnnaBridge	161:aa5281ff4a02	46	#if defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\|\
AnnaBridge	161:aa5281ff4a02	47	defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	161:aa5281ff4a02	48	/* Includes ------------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	49	#include "stm32f4xx_hal_def.h"
AnnaBridge	161:aa5281ff4a02	50
AnnaBridge	161:aa5281ff4a02	51	/** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge	161:aa5281ff4a02	52	* @{
AnnaBridge	161:aa5281ff4a02	53	*/
AnnaBridge	161:aa5281ff4a02	54
AnnaBridge	161:aa5281ff4a02	55	/** @addtogroup ETH
AnnaBridge	161:aa5281ff4a02	56	* @{
AnnaBridge	161:aa5281ff4a02	57	*/
AnnaBridge	161:aa5281ff4a02	58
AnnaBridge	161:aa5281ff4a02	59	/** @addtogroup ETH_Private_Macros
AnnaBridge	161:aa5281ff4a02	60	* @{
AnnaBridge	161:aa5281ff4a02	61	*/
AnnaBridge	161:aa5281ff4a02	62	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
AnnaBridge	161:aa5281ff4a02	63	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	64	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
AnnaBridge	161:aa5281ff4a02	65	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
AnnaBridge	161:aa5281ff4a02	66	((SPEED) == ETH_SPEED_100M))
AnnaBridge	161:aa5281ff4a02	67	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
AnnaBridge	161:aa5281ff4a02	68	((MODE) == ETH_MODE_HALFDUPLEX))
AnnaBridge	161:aa5281ff4a02	69	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
AnnaBridge	161:aa5281ff4a02	70	((MODE) == ETH_RXINTERRUPT_MODE))
AnnaBridge	161:aa5281ff4a02	71	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
AnnaBridge	161:aa5281ff4a02	72	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
AnnaBridge	161:aa5281ff4a02	73	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
AnnaBridge	161:aa5281ff4a02	74	((MODE) == ETH_MEDIA_INTERFACE_RMII))
AnnaBridge	161:aa5281ff4a02	75	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	76	((CMD) == ETH_WATCHDOG_DISABLE))
AnnaBridge	161:aa5281ff4a02	77	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	78	((CMD) == ETH_JABBER_DISABLE))
AnnaBridge	161:aa5281ff4a02	79	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
AnnaBridge	161:aa5281ff4a02	80	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
AnnaBridge	161:aa5281ff4a02	81	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
AnnaBridge	161:aa5281ff4a02	82	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
AnnaBridge	161:aa5281ff4a02	83	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
AnnaBridge	161:aa5281ff4a02	84	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
AnnaBridge	161:aa5281ff4a02	85	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
AnnaBridge	161:aa5281ff4a02	86	((GAP) == ETH_INTERFRAMEGAP_40BIT))
AnnaBridge	161:aa5281ff4a02	87	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	88	((CMD) == ETH_CARRIERSENCE_DISABLE))
AnnaBridge	161:aa5281ff4a02	89	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	90	((CMD) == ETH_RECEIVEOWN_DISABLE))
AnnaBridge	161:aa5281ff4a02	91	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	92	((CMD) == ETH_LOOPBACKMODE_DISABLE))
AnnaBridge	161:aa5281ff4a02	93	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	94	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
AnnaBridge	161:aa5281ff4a02	95	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	96	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
AnnaBridge	161:aa5281ff4a02	97	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	98	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
AnnaBridge	161:aa5281ff4a02	99	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
AnnaBridge	161:aa5281ff4a02	100	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
AnnaBridge	161:aa5281ff4a02	101	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
AnnaBridge	161:aa5281ff4a02	102	((LIMIT) == ETH_BACKOFFLIMIT_1))
AnnaBridge	161:aa5281ff4a02	103	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	104	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
AnnaBridge	161:aa5281ff4a02	105	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	106	((CMD) == ETH_RECEIVEAll_DISABLE))
AnnaBridge	161:aa5281ff4a02	107	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	108	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	109	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
AnnaBridge	161:aa5281ff4a02	110	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
AnnaBridge	161:aa5281ff4a02	111	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
AnnaBridge	161:aa5281ff4a02	112	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
AnnaBridge	161:aa5281ff4a02	113	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	114	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
AnnaBridge	161:aa5281ff4a02	115	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
AnnaBridge	161:aa5281ff4a02	116	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
AnnaBridge	161:aa5281ff4a02	117	#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	118	((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
AnnaBridge	161:aa5281ff4a02	119	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	120	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	121	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
AnnaBridge	161:aa5281ff4a02	122	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
AnnaBridge	161:aa5281ff4a02	123	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	124	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	125	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
AnnaBridge	161:aa5281ff4a02	126	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
AnnaBridge	161:aa5281ff4a02	127	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	128	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
AnnaBridge	161:aa5281ff4a02	129	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
AnnaBridge	161:aa5281ff4a02	130	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
AnnaBridge	161:aa5281ff4a02	131	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
AnnaBridge	161:aa5281ff4a02	132	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
AnnaBridge	161:aa5281ff4a02	133	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	134	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
AnnaBridge	161:aa5281ff4a02	135	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	136	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
AnnaBridge	161:aa5281ff4a02	137	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	138	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
AnnaBridge	161:aa5281ff4a02	139	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
AnnaBridge	161:aa5281ff4a02	140	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
AnnaBridge	161:aa5281ff4a02	141	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
AnnaBridge	161:aa5281ff4a02	142	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
AnnaBridge	161:aa5281ff4a02	143	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
AnnaBridge	161:aa5281ff4a02	144	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
AnnaBridge	161:aa5281ff4a02	145	((ADDRESS) == ETH_MAC_ADDRESS3))
AnnaBridge	161:aa5281ff4a02	146	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
AnnaBridge	161:aa5281ff4a02	147	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
AnnaBridge	161:aa5281ff4a02	148	((ADDRESS) == ETH_MAC_ADDRESS3))
AnnaBridge	161:aa5281ff4a02	149	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
AnnaBridge	161:aa5281ff4a02	150	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
AnnaBridge	161:aa5281ff4a02	151	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
AnnaBridge	161:aa5281ff4a02	152	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
AnnaBridge	161:aa5281ff4a02	153	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
AnnaBridge	161:aa5281ff4a02	154	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
AnnaBridge	161:aa5281ff4a02	155	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
AnnaBridge	161:aa5281ff4a02	156	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
AnnaBridge	161:aa5281ff4a02	157	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	158	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
AnnaBridge	161:aa5281ff4a02	159	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	160	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
AnnaBridge	161:aa5281ff4a02	161	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	162	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
AnnaBridge	161:aa5281ff4a02	163	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	164	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
AnnaBridge	161:aa5281ff4a02	165	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
AnnaBridge	161:aa5281ff4a02	166	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
AnnaBridge	161:aa5281ff4a02	167	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
AnnaBridge	161:aa5281ff4a02	168	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
AnnaBridge	161:aa5281ff4a02	169	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
AnnaBridge	161:aa5281ff4a02	170	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
AnnaBridge	161:aa5281ff4a02	171	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
AnnaBridge	161:aa5281ff4a02	172	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
AnnaBridge	161:aa5281ff4a02	173	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	174	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
AnnaBridge	161:aa5281ff4a02	175	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	176	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
AnnaBridge	161:aa5281ff4a02	177	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
AnnaBridge	161:aa5281ff4a02	178	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
AnnaBridge	161:aa5281ff4a02	179	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
AnnaBridge	161:aa5281ff4a02	180	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
AnnaBridge	161:aa5281ff4a02	181	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	182	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
AnnaBridge	161:aa5281ff4a02	183	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	184	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
AnnaBridge	161:aa5281ff4a02	185	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	186	((CMD) == ETH_FIXEDBURST_DISABLE))
AnnaBridge	161:aa5281ff4a02	187	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	188	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	189	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	190	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	191	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	192	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	193	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	194	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	195	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	196	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	197	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	198	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
AnnaBridge	161:aa5281ff4a02	199	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	200	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	201	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	202	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	203	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	204	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	205	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	206	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	207	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	208	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	209	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
AnnaBridge	161:aa5281ff4a02	210	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
AnnaBridge	161:aa5281ff4a02	211	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
AnnaBridge	161:aa5281ff4a02	212	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
AnnaBridge	161:aa5281ff4a02	213	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
AnnaBridge	161:aa5281ff4a02	214	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
AnnaBridge	161:aa5281ff4a02	215	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
AnnaBridge	161:aa5281ff4a02	216	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
AnnaBridge	161:aa5281ff4a02	217	#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) \|\| \
AnnaBridge	161:aa5281ff4a02	218	((FLAG) == ETH_DMATXDESC_IC) \|\| \
AnnaBridge	161:aa5281ff4a02	219	((FLAG) == ETH_DMATXDESC_LS) \|\| \
AnnaBridge	161:aa5281ff4a02	220	((FLAG) == ETH_DMATXDESC_FS) \|\| \
AnnaBridge	161:aa5281ff4a02	221	((FLAG) == ETH_DMATXDESC_DC) \|\| \
AnnaBridge	161:aa5281ff4a02	222	((FLAG) == ETH_DMATXDESC_DP) \|\| \
AnnaBridge	161:aa5281ff4a02	223	((FLAG) == ETH_DMATXDESC_TTSE) \|\| \
AnnaBridge	161:aa5281ff4a02	224	((FLAG) == ETH_DMATXDESC_TER) \|\| \
AnnaBridge	161:aa5281ff4a02	225	((FLAG) == ETH_DMATXDESC_TCH) \|\| \
AnnaBridge	161:aa5281ff4a02	226	((FLAG) == ETH_DMATXDESC_TTSS) \|\| \
AnnaBridge	161:aa5281ff4a02	227	((FLAG) == ETH_DMATXDESC_IHE) \|\| \
AnnaBridge	161:aa5281ff4a02	228	((FLAG) == ETH_DMATXDESC_ES) \|\| \
AnnaBridge	161:aa5281ff4a02	229	((FLAG) == ETH_DMATXDESC_JT) \|\| \
AnnaBridge	161:aa5281ff4a02	230	((FLAG) == ETH_DMATXDESC_FF) \|\| \
AnnaBridge	161:aa5281ff4a02	231	((FLAG) == ETH_DMATXDESC_PCE) \|\| \
AnnaBridge	161:aa5281ff4a02	232	((FLAG) == ETH_DMATXDESC_LCA) \|\| \
AnnaBridge	161:aa5281ff4a02	233	((FLAG) == ETH_DMATXDESC_NC) \|\| \
AnnaBridge	161:aa5281ff4a02	234	((FLAG) == ETH_DMATXDESC_LCO) \|\| \
AnnaBridge	161:aa5281ff4a02	235	((FLAG) == ETH_DMATXDESC_EC) \|\| \
AnnaBridge	161:aa5281ff4a02	236	((FLAG) == ETH_DMATXDESC_VF) \|\| \
AnnaBridge	161:aa5281ff4a02	237	((FLAG) == ETH_DMATXDESC_CC) \|\| \
AnnaBridge	161:aa5281ff4a02	238	((FLAG) == ETH_DMATXDESC_ED) \|\| \
AnnaBridge	161:aa5281ff4a02	239	((FLAG) == ETH_DMATXDESC_UF) \|\| \
AnnaBridge	161:aa5281ff4a02	240	((FLAG) == ETH_DMATXDESC_DB))
AnnaBridge	161:aa5281ff4a02	241	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
AnnaBridge	161:aa5281ff4a02	242	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
AnnaBridge	161:aa5281ff4a02	243	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
AnnaBridge	161:aa5281ff4a02	244	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
AnnaBridge	161:aa5281ff4a02	245	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
AnnaBridge	161:aa5281ff4a02	246	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
AnnaBridge	161:aa5281ff4a02	247	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
AnnaBridge	161:aa5281ff4a02	248	#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) \|\| \
AnnaBridge	161:aa5281ff4a02	249	((FLAG) == ETH_DMARXDESC_AFM) \|\| \
AnnaBridge	161:aa5281ff4a02	250	((FLAG) == ETH_DMARXDESC_ES) \|\| \
AnnaBridge	161:aa5281ff4a02	251	((FLAG) == ETH_DMARXDESC_DE) \|\| \
AnnaBridge	161:aa5281ff4a02	252	((FLAG) == ETH_DMARXDESC_SAF) \|\| \
AnnaBridge	161:aa5281ff4a02	253	((FLAG) == ETH_DMARXDESC_LE) \|\| \
AnnaBridge	161:aa5281ff4a02	254	((FLAG) == ETH_DMARXDESC_OE) \|\| \
AnnaBridge	161:aa5281ff4a02	255	((FLAG) == ETH_DMARXDESC_VLAN) \|\| \
AnnaBridge	161:aa5281ff4a02	256	((FLAG) == ETH_DMARXDESC_FS) \|\| \
AnnaBridge	161:aa5281ff4a02	257	((FLAG) == ETH_DMARXDESC_LS) \|\| \
AnnaBridge	161:aa5281ff4a02	258	((FLAG) == ETH_DMARXDESC_IPV4HCE) \|\| \
AnnaBridge	161:aa5281ff4a02	259	((FLAG) == ETH_DMARXDESC_LC) \|\| \
AnnaBridge	161:aa5281ff4a02	260	((FLAG) == ETH_DMARXDESC_FT) \|\| \
AnnaBridge	161:aa5281ff4a02	261	((FLAG) == ETH_DMARXDESC_RWT) \|\| \
AnnaBridge	161:aa5281ff4a02	262	((FLAG) == ETH_DMARXDESC_RE) \|\| \
AnnaBridge	161:aa5281ff4a02	263	((FLAG) == ETH_DMARXDESC_DBE) \|\| \
AnnaBridge	161:aa5281ff4a02	264	((FLAG) == ETH_DMARXDESC_CE) \|\| \
AnnaBridge	161:aa5281ff4a02	265	((FLAG) == ETH_DMARXDESC_MAMPCE))
AnnaBridge	161:aa5281ff4a02	266	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
AnnaBridge	161:aa5281ff4a02	267	((BUFFER) == ETH_DMARXDESC_BUFFER2))
AnnaBridge	161:aa5281ff4a02	268	#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) \|\| \
AnnaBridge	161:aa5281ff4a02	269	((FLAG) == ETH_PMT_FLAG_MPR))
AnnaBridge	161:aa5281ff4a02	270	#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
AnnaBridge	161:aa5281ff4a02	271	#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) \|\| ((FLAG) == ETH_DMA_FLAG_PMT) \|\| \
AnnaBridge	161:aa5281ff4a02	272	((FLAG) == ETH_DMA_FLAG_MMC) \|\| ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) \|\| \
AnnaBridge	161:aa5281ff4a02	273	((FLAG) == ETH_DMA_FLAG_READWRITEERROR) \|\| ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) \|\| \
AnnaBridge	161:aa5281ff4a02	274	((FLAG) == ETH_DMA_FLAG_NIS) \|\| ((FLAG) == ETH_DMA_FLAG_AIS) \|\| \
AnnaBridge	161:aa5281ff4a02	275	((FLAG) == ETH_DMA_FLAG_ER) \|\| ((FLAG) == ETH_DMA_FLAG_FBE) \|\| \
AnnaBridge	161:aa5281ff4a02	276	((FLAG) == ETH_DMA_FLAG_ET) \|\| ((FLAG) == ETH_DMA_FLAG_RWT) \|\| \
AnnaBridge	161:aa5281ff4a02	277	((FLAG) == ETH_DMA_FLAG_RPS) \|\| ((FLAG) == ETH_DMA_FLAG_RBU) \|\| \
AnnaBridge	161:aa5281ff4a02	278	((FLAG) == ETH_DMA_FLAG_R) \|\| ((FLAG) == ETH_DMA_FLAG_TU) \|\| \
AnnaBridge	161:aa5281ff4a02	279	((FLAG) == ETH_DMA_FLAG_RO) \|\| ((FLAG) == ETH_DMA_FLAG_TJT) \|\| \
AnnaBridge	161:aa5281ff4a02	280	((FLAG) == ETH_DMA_FLAG_TBU) \|\| ((FLAG) == ETH_DMA_FLAG_TPS) \|\| \
AnnaBridge	161:aa5281ff4a02	281	((FLAG) == ETH_DMA_FLAG_T))
AnnaBridge	161:aa5281ff4a02	282	#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
AnnaBridge	161:aa5281ff4a02	283	#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) \|\| ((IT) == ETH_MAC_IT_MMCT) \|\| \
AnnaBridge	161:aa5281ff4a02	284	((IT) == ETH_MAC_IT_MMCR) \|\| ((IT) == ETH_MAC_IT_MMC) \|\| \
AnnaBridge	161:aa5281ff4a02	285	((IT) == ETH_MAC_IT_PMT))
AnnaBridge	161:aa5281ff4a02	286	#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) \|\| ((FLAG) == ETH_MAC_FLAG_MMCT) \|\| \
AnnaBridge	161:aa5281ff4a02	287	((FLAG) == ETH_MAC_FLAG_MMCR) \|\| ((FLAG) == ETH_MAC_FLAG_MMC) \|\| \
AnnaBridge	161:aa5281ff4a02	288	((FLAG) == ETH_MAC_FLAG_PMT))
AnnaBridge	161:aa5281ff4a02	289	#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
AnnaBridge	161:aa5281ff4a02	290	#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) \|\| ((IT) == ETH_DMA_IT_PMT) \|\| \
AnnaBridge	161:aa5281ff4a02	291	((IT) == ETH_DMA_IT_MMC) \|\| ((IT) == ETH_DMA_IT_NIS) \|\| \
AnnaBridge	161:aa5281ff4a02	292	((IT) == ETH_DMA_IT_AIS) \|\| ((IT) == ETH_DMA_IT_ER) \|\| \
AnnaBridge	161:aa5281ff4a02	293	((IT) == ETH_DMA_IT_FBE) \|\| ((IT) == ETH_DMA_IT_ET) \|\| \
AnnaBridge	161:aa5281ff4a02	294	((IT) == ETH_DMA_IT_RWT) \|\| ((IT) == ETH_DMA_IT_RPS) \|\| \
AnnaBridge	161:aa5281ff4a02	295	((IT) == ETH_DMA_IT_RBU) \|\| ((IT) == ETH_DMA_IT_R) \|\| \
AnnaBridge	161:aa5281ff4a02	296	((IT) == ETH_DMA_IT_TU) \|\| ((IT) == ETH_DMA_IT_RO) \|\| \
AnnaBridge	161:aa5281ff4a02	297	((IT) == ETH_DMA_IT_TJT) \|\| ((IT) == ETH_DMA_IT_TBU) \|\| \
AnnaBridge	161:aa5281ff4a02	298	((IT) == ETH_DMA_IT_TPS) \|\| ((IT) == ETH_DMA_IT_T))
AnnaBridge	161:aa5281ff4a02	299	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
AnnaBridge	161:aa5281ff4a02	300	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
AnnaBridge	161:aa5281ff4a02	301	#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) \|\| (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
AnnaBridge	161:aa5281ff4a02	302	((IT) != 0x00U))
AnnaBridge	161:aa5281ff4a02	303	#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) \|\| ((IT) == ETH_MMC_IT_TGFMSC) \|\| \
AnnaBridge	161:aa5281ff4a02	304	((IT) == ETH_MMC_IT_TGFSC) \|\| ((IT) == ETH_MMC_IT_RGUF) \|\| \
AnnaBridge	161:aa5281ff4a02	305	((IT) == ETH_MMC_IT_RFAE) \|\| ((IT) == ETH_MMC_IT_RFCE))
AnnaBridge	161:aa5281ff4a02	306	#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	307	((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
AnnaBridge	161:aa5281ff4a02	308
AnnaBridge	161:aa5281ff4a02	309	/**
AnnaBridge	161:aa5281ff4a02	310	* @}
AnnaBridge	161:aa5281ff4a02	311	*/
AnnaBridge	161:aa5281ff4a02	312
AnnaBridge	161:aa5281ff4a02	313	/** @addtogroup ETH_Private_Defines
AnnaBridge	161:aa5281ff4a02	314	* @{
AnnaBridge	161:aa5281ff4a02	315	*/
AnnaBridge	161:aa5281ff4a02	316	/* Delay to wait when writing to some Ethernet registers */
AnnaBridge	161:aa5281ff4a02	317	#define ETH_REG_WRITE_DELAY 0x00000001U
AnnaBridge	161:aa5281ff4a02	318
AnnaBridge	161:aa5281ff4a02	319	/* ETHERNET Errors */
AnnaBridge	161:aa5281ff4a02	320	#define ETH_SUCCESS 0U
AnnaBridge	161:aa5281ff4a02	321	#define ETH_ERROR 1U
AnnaBridge	161:aa5281ff4a02	322
AnnaBridge	161:aa5281ff4a02	323	/* ETHERNET DMA Tx descriptors Collision Count Shift */
AnnaBridge	161:aa5281ff4a02	324	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
AnnaBridge	161:aa5281ff4a02	325
AnnaBridge	161:aa5281ff4a02	326	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
AnnaBridge	161:aa5281ff4a02	327	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
AnnaBridge	161:aa5281ff4a02	328
AnnaBridge	161:aa5281ff4a02	329	/* ETHERNET DMA Rx descriptors Frame Length Shift */
AnnaBridge	161:aa5281ff4a02	330	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
AnnaBridge	161:aa5281ff4a02	331
AnnaBridge	161:aa5281ff4a02	332	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
AnnaBridge	161:aa5281ff4a02	333	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
AnnaBridge	161:aa5281ff4a02	334
AnnaBridge	161:aa5281ff4a02	335	/* ETHERNET DMA Rx descriptors Frame length Shift */
AnnaBridge	161:aa5281ff4a02	336	#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
AnnaBridge	161:aa5281ff4a02	337
AnnaBridge	161:aa5281ff4a02	338	/* ETHERNET MAC address offsets */
AnnaBridge	161:aa5281ff4a02	339	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
AnnaBridge	161:aa5281ff4a02	340	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
AnnaBridge	161:aa5281ff4a02	341
AnnaBridge	161:aa5281ff4a02	342	/* ETHERNET MACMIIAR register Mask */
AnnaBridge	161:aa5281ff4a02	343	#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
AnnaBridge	161:aa5281ff4a02	344
AnnaBridge	161:aa5281ff4a02	345	/* ETHERNET MACCR register Mask */
AnnaBridge	161:aa5281ff4a02	346	#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
AnnaBridge	161:aa5281ff4a02	347
AnnaBridge	161:aa5281ff4a02	348	/* ETHERNET MACFCR register Mask */
AnnaBridge	161:aa5281ff4a02	349	#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
AnnaBridge	161:aa5281ff4a02	350
AnnaBridge	161:aa5281ff4a02	351	/* ETHERNET DMAOMR register Mask */
AnnaBridge	161:aa5281ff4a02	352	#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
AnnaBridge	161:aa5281ff4a02	353
AnnaBridge	161:aa5281ff4a02	354	/* ETHERNET Remote Wake-up frame register length */
AnnaBridge	161:aa5281ff4a02	355	#define ETH_WAKEUP_REGISTER_LENGTH 8U
AnnaBridge	161:aa5281ff4a02	356
AnnaBridge	161:aa5281ff4a02	357	/* ETHERNET Missed frames counter Shift */
AnnaBridge	161:aa5281ff4a02	358	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
AnnaBridge	161:aa5281ff4a02	359	/**
AnnaBridge	161:aa5281ff4a02	360	* @}
AnnaBridge	161:aa5281ff4a02	361	*/
AnnaBridge	161:aa5281ff4a02	362
AnnaBridge	161:aa5281ff4a02	363	/* Exported types ------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	364	/** @defgroup ETH_Exported_Types ETH Exported Types
AnnaBridge	161:aa5281ff4a02	365	* @{
AnnaBridge	161:aa5281ff4a02	366	*/
AnnaBridge	161:aa5281ff4a02	367
AnnaBridge	161:aa5281ff4a02	368	/**
AnnaBridge	161:aa5281ff4a02	369	* @brief HAL State structures definition
AnnaBridge	161:aa5281ff4a02	370	*/
AnnaBridge	161:aa5281ff4a02	371	typedef enum
AnnaBridge	161:aa5281ff4a02	372	{
AnnaBridge	161:aa5281ff4a02	373	HAL_ETH_STATE_RESET = 0x00U, /!< Peripheral not yet Initialized or disabled /
AnnaBridge	161:aa5281ff4a02	374	HAL_ETH_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
AnnaBridge	161:aa5281ff4a02	375	HAL_ETH_STATE_BUSY = 0x02U, /!< an internal process is ongoing /
AnnaBridge	161:aa5281ff4a02	376	HAL_ETH_STATE_BUSY_TX = 0x12U, /!< Data Transmission process is ongoing /
AnnaBridge	161:aa5281ff4a02	377	HAL_ETH_STATE_BUSY_RX = 0x22U, /!< Data Reception process is ongoing /
AnnaBridge	161:aa5281ff4a02	378	HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /!< Data Transmission and Reception process is ongoing /
AnnaBridge	161:aa5281ff4a02	379	HAL_ETH_STATE_BUSY_WR = 0x42U, /!< Write process is ongoing /
AnnaBridge	161:aa5281ff4a02	380	HAL_ETH_STATE_BUSY_RD = 0x82U, /!< Read process is ongoing /
AnnaBridge	161:aa5281ff4a02	381	HAL_ETH_STATE_TIMEOUT = 0x03U, /!< Timeout state /
AnnaBridge	161:aa5281ff4a02	382	HAL_ETH_STATE_ERROR = 0x04U /!< Reception process is ongoing /
AnnaBridge	161:aa5281ff4a02	383	}HAL_ETH_StateTypeDef;
AnnaBridge	161:aa5281ff4a02	384
AnnaBridge	161:aa5281ff4a02	385	/**
AnnaBridge	161:aa5281ff4a02	386	* @brief ETH Init Structure definition
AnnaBridge	161:aa5281ff4a02	387	*/
AnnaBridge	161:aa5281ff4a02	388
AnnaBridge	161:aa5281ff4a02	389	typedef struct
AnnaBridge	161:aa5281ff4a02	390	{
AnnaBridge	161:aa5281ff4a02	391	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
AnnaBridge	161:aa5281ff4a02	392	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
AnnaBridge	161:aa5281ff4a02	393	and the mode (half/full-duplex).
AnnaBridge	161:aa5281ff4a02	394	This parameter can be a value of @ref ETH_AutoNegotiation */
AnnaBridge	161:aa5281ff4a02	395
AnnaBridge	161:aa5281ff4a02	396	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
AnnaBridge	161:aa5281ff4a02	397	This parameter can be a value of @ref ETH_Speed */
AnnaBridge	161:aa5281ff4a02	398
AnnaBridge	161:aa5281ff4a02	399	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
AnnaBridge	161:aa5281ff4a02	400	This parameter can be a value of @ref ETH_Duplex_Mode */
AnnaBridge	161:aa5281ff4a02	401
AnnaBridge	161:aa5281ff4a02	402	uint16_t PhyAddress; /*!< Ethernet PHY address.
AnnaBridge	161:aa5281ff4a02	403	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
AnnaBridge	161:aa5281ff4a02	404
AnnaBridge	161:aa5281ff4a02	405	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
AnnaBridge	161:aa5281ff4a02	406
AnnaBridge	161:aa5281ff4a02	407	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
AnnaBridge	161:aa5281ff4a02	408	This parameter can be a value of @ref ETH_Rx_Mode */
AnnaBridge	161:aa5281ff4a02	409
AnnaBridge	161:aa5281ff4a02	410	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
AnnaBridge	161:aa5281ff4a02	411	This parameter can be a value of @ref ETH_Checksum_Mode */
AnnaBridge	161:aa5281ff4a02	412
AnnaBridge	161:aa5281ff4a02	413	uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
AnnaBridge	161:aa5281ff4a02	414	This parameter can be a value of @ref ETH_Media_Interface */
AnnaBridge	161:aa5281ff4a02	415
AnnaBridge	161:aa5281ff4a02	416	} ETH_InitTypeDef;
AnnaBridge	161:aa5281ff4a02	417
AnnaBridge	161:aa5281ff4a02	418
AnnaBridge	161:aa5281ff4a02	419	/**
AnnaBridge	161:aa5281ff4a02	420	* @brief ETH MAC Configuration Structure definition
AnnaBridge	161:aa5281ff4a02	421	*/
AnnaBridge	161:aa5281ff4a02	422
AnnaBridge	161:aa5281ff4a02	423	typedef struct
AnnaBridge	161:aa5281ff4a02	424	{
AnnaBridge	161:aa5281ff4a02	425	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
AnnaBridge	161:aa5281ff4a02	426	When enabled, the MAC allows no more then 2048 bytes to be received.
AnnaBridge	161:aa5281ff4a02	427	When disabled, the MAC can receive up to 16384 bytes.
AnnaBridge	161:aa5281ff4a02	428	This parameter can be a value of @ref ETH_Watchdog */
AnnaBridge	161:aa5281ff4a02	429
AnnaBridge	161:aa5281ff4a02	430	uint32_t Jabber; /*!< Selects or not Jabber timer
AnnaBridge	161:aa5281ff4a02	431	When enabled, the MAC allows no more then 2048 bytes to be sent.
AnnaBridge	161:aa5281ff4a02	432	When disabled, the MAC can send up to 16384 bytes.
AnnaBridge	161:aa5281ff4a02	433	This parameter can be a value of @ref ETH_Jabber */
AnnaBridge	161:aa5281ff4a02	434
AnnaBridge	161:aa5281ff4a02	435	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
AnnaBridge	161:aa5281ff4a02	436	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
AnnaBridge	161:aa5281ff4a02	437
AnnaBridge	161:aa5281ff4a02	438	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
AnnaBridge	161:aa5281ff4a02	439	This parameter can be a value of @ref ETH_Carrier_Sense */
AnnaBridge	161:aa5281ff4a02	440
AnnaBridge	161:aa5281ff4a02	441	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
AnnaBridge	161:aa5281ff4a02	442	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
AnnaBridge	161:aa5281ff4a02	443	in Half-Duplex mode.
AnnaBridge	161:aa5281ff4a02	444	This parameter can be a value of @ref ETH_Receive_Own */
AnnaBridge	161:aa5281ff4a02	445
AnnaBridge	161:aa5281ff4a02	446	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
AnnaBridge	161:aa5281ff4a02	447	This parameter can be a value of @ref ETH_Loop_Back_Mode */
AnnaBridge	161:aa5281ff4a02	448
AnnaBridge	161:aa5281ff4a02	449	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
AnnaBridge	161:aa5281ff4a02	450	This parameter can be a value of @ref ETH_Checksum_Offload */
AnnaBridge	161:aa5281ff4a02	451
AnnaBridge	161:aa5281ff4a02	452	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
AnnaBridge	161:aa5281ff4a02	453	when a collision occurs (Half-Duplex mode).
AnnaBridge	161:aa5281ff4a02	454	This parameter can be a value of @ref ETH_Retry_Transmission */
AnnaBridge	161:aa5281ff4a02	455
AnnaBridge	161:aa5281ff4a02	456	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
AnnaBridge	161:aa5281ff4a02	457	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
AnnaBridge	161:aa5281ff4a02	458
AnnaBridge	161:aa5281ff4a02	459	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
AnnaBridge	161:aa5281ff4a02	460	This parameter can be a value of @ref ETH_Back_Off_Limit */
AnnaBridge	161:aa5281ff4a02	461
AnnaBridge	161:aa5281ff4a02	462	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
AnnaBridge	161:aa5281ff4a02	463	This parameter can be a value of @ref ETH_Deferral_Check */
AnnaBridge	161:aa5281ff4a02	464
AnnaBridge	161:aa5281ff4a02	465	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
AnnaBridge	161:aa5281ff4a02	466	This parameter can be a value of @ref ETH_Receive_All */
AnnaBridge	161:aa5281ff4a02	467
AnnaBridge	161:aa5281ff4a02	468	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
AnnaBridge	161:aa5281ff4a02	469	This parameter can be a value of @ref ETH_Source_Addr_Filter */
AnnaBridge	161:aa5281ff4a02	470
AnnaBridge	161:aa5281ff4a02	471	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
AnnaBridge	161:aa5281ff4a02	472	This parameter can be a value of @ref ETH_Pass_Control_Frames */
AnnaBridge	161:aa5281ff4a02	473
AnnaBridge	161:aa5281ff4a02	474	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
AnnaBridge	161:aa5281ff4a02	475	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
AnnaBridge	161:aa5281ff4a02	476
AnnaBridge	161:aa5281ff4a02	477	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
AnnaBridge	161:aa5281ff4a02	478	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
AnnaBridge	161:aa5281ff4a02	479
AnnaBridge	161:aa5281ff4a02	480	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
AnnaBridge	161:aa5281ff4a02	481	This parameter can be a value of @ref ETH_Promiscuous_Mode */
AnnaBridge	161:aa5281ff4a02	482
AnnaBridge	161:aa5281ff4a02	483	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
AnnaBridge	161:aa5281ff4a02	484	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
AnnaBridge	161:aa5281ff4a02	485
AnnaBridge	161:aa5281ff4a02	486	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
AnnaBridge	161:aa5281ff4a02	487	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
AnnaBridge	161:aa5281ff4a02	488
AnnaBridge	161:aa5281ff4a02	489	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
AnnaBridge	161:aa5281ff4a02	490	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
AnnaBridge	161:aa5281ff4a02	491
AnnaBridge	161:aa5281ff4a02	492	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
AnnaBridge	161:aa5281ff4a02	493	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
AnnaBridge	161:aa5281ff4a02	494
AnnaBridge	161:aa5281ff4a02	495	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
AnnaBridge	161:aa5281ff4a02	496	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
AnnaBridge	161:aa5281ff4a02	497
AnnaBridge	161:aa5281ff4a02	498	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
AnnaBridge	161:aa5281ff4a02	499	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
AnnaBridge	161:aa5281ff4a02	500
AnnaBridge	161:aa5281ff4a02	501	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
AnnaBridge	161:aa5281ff4a02	502	automatic retransmission of PAUSE Frame.
AnnaBridge	161:aa5281ff4a02	503	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
AnnaBridge	161:aa5281ff4a02	504
AnnaBridge	161:aa5281ff4a02	505	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
AnnaBridge	161:aa5281ff4a02	506	unicast address and unique multicast address).
AnnaBridge	161:aa5281ff4a02	507	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
AnnaBridge	161:aa5281ff4a02	508
AnnaBridge	161:aa5281ff4a02	509	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
AnnaBridge	161:aa5281ff4a02	510	disable its transmitter for a specified time (Pause Time)
AnnaBridge	161:aa5281ff4a02	511	This parameter can be a value of @ref ETH_Receive_Flow_Control */
AnnaBridge	161:aa5281ff4a02	512
AnnaBridge	161:aa5281ff4a02	513	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
AnnaBridge	161:aa5281ff4a02	514	or the MAC back-pressure operation (Half-Duplex mode)
AnnaBridge	161:aa5281ff4a02	515	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
AnnaBridge	161:aa5281ff4a02	516
AnnaBridge	161:aa5281ff4a02	517	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
AnnaBridge	161:aa5281ff4a02	518	comparison and filtering.
AnnaBridge	161:aa5281ff4a02	519	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
AnnaBridge	161:aa5281ff4a02	520
AnnaBridge	161:aa5281ff4a02	521	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
AnnaBridge	161:aa5281ff4a02	522
AnnaBridge	161:aa5281ff4a02	523	} ETH_MACInitTypeDef;
AnnaBridge	161:aa5281ff4a02	524
AnnaBridge	161:aa5281ff4a02	525	/**
AnnaBridge	161:aa5281ff4a02	526	* @brief ETH DMA Configuration Structure definition
AnnaBridge	161:aa5281ff4a02	527	*/
AnnaBridge	161:aa5281ff4a02	528
AnnaBridge	161:aa5281ff4a02	529	typedef struct
AnnaBridge	161:aa5281ff4a02	530	{
AnnaBridge	161:aa5281ff4a02	531	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
AnnaBridge	161:aa5281ff4a02	532	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
AnnaBridge	161:aa5281ff4a02	533
AnnaBridge	161:aa5281ff4a02	534	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
AnnaBridge	161:aa5281ff4a02	535	This parameter can be a value of @ref ETH_Receive_Store_Forward */
AnnaBridge	161:aa5281ff4a02	536
AnnaBridge	161:aa5281ff4a02	537	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
AnnaBridge	161:aa5281ff4a02	538	This parameter can be a value of @ref ETH_Flush_Received_Frame */
AnnaBridge	161:aa5281ff4a02	539
AnnaBridge	161:aa5281ff4a02	540	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
AnnaBridge	161:aa5281ff4a02	541	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
AnnaBridge	161:aa5281ff4a02	542
AnnaBridge	161:aa5281ff4a02	543	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
AnnaBridge	161:aa5281ff4a02	544	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
AnnaBridge	161:aa5281ff4a02	545
AnnaBridge	161:aa5281ff4a02	546	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
AnnaBridge	161:aa5281ff4a02	547	This parameter can be a value of @ref ETH_Forward_Error_Frames */
AnnaBridge	161:aa5281ff4a02	548
AnnaBridge	161:aa5281ff4a02	549	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
AnnaBridge	161:aa5281ff4a02	550	and length less than 64 bytes) including pad-bytes and CRC)
AnnaBridge	161:aa5281ff4a02	551	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
AnnaBridge	161:aa5281ff4a02	552
AnnaBridge	161:aa5281ff4a02	553	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
AnnaBridge	161:aa5281ff4a02	554	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
AnnaBridge	161:aa5281ff4a02	555
AnnaBridge	161:aa5281ff4a02	556	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
AnnaBridge	161:aa5281ff4a02	557	frame of Transmit data even before obtaining the status for the first frame.
AnnaBridge	161:aa5281ff4a02	558	This parameter can be a value of @ref ETH_Second_Frame_Operate */
AnnaBridge	161:aa5281ff4a02	559
AnnaBridge	161:aa5281ff4a02	560	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
AnnaBridge	161:aa5281ff4a02	561	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
AnnaBridge	161:aa5281ff4a02	562
AnnaBridge	161:aa5281ff4a02	563	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
AnnaBridge	161:aa5281ff4a02	564	This parameter can be a value of @ref ETH_Fixed_Burst */
AnnaBridge	161:aa5281ff4a02	565
AnnaBridge	161:aa5281ff4a02	566	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
AnnaBridge	161:aa5281ff4a02	567	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
AnnaBridge	161:aa5281ff4a02	568
AnnaBridge	161:aa5281ff4a02	569	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
AnnaBridge	161:aa5281ff4a02	570	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
AnnaBridge	161:aa5281ff4a02	571
AnnaBridge	161:aa5281ff4a02	572	uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
AnnaBridge	161:aa5281ff4a02	573	This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
AnnaBridge	161:aa5281ff4a02	574
AnnaBridge	161:aa5281ff4a02	575	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
AnnaBridge	161:aa5281ff4a02	576	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
AnnaBridge	161:aa5281ff4a02	577
AnnaBridge	161:aa5281ff4a02	578	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
AnnaBridge	161:aa5281ff4a02	579	This parameter can be a value of @ref ETH_DMA_Arbitration */
AnnaBridge	161:aa5281ff4a02	580	} ETH_DMAInitTypeDef;
AnnaBridge	161:aa5281ff4a02	581
AnnaBridge	161:aa5281ff4a02	582
AnnaBridge	161:aa5281ff4a02	583	/**
AnnaBridge	161:aa5281ff4a02	584	* @brief ETH DMA Descriptors data structure definition
AnnaBridge	161:aa5281ff4a02	585	*/
AnnaBridge	161:aa5281ff4a02	586
AnnaBridge	161:aa5281ff4a02	587	typedef struct
AnnaBridge	161:aa5281ff4a02	588	{
AnnaBridge	161:aa5281ff4a02	589	__IO uint32_t Status; /!< Status /
AnnaBridge	161:aa5281ff4a02	590
AnnaBridge	161:aa5281ff4a02	591	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
AnnaBridge	161:aa5281ff4a02	592
AnnaBridge	161:aa5281ff4a02	593	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
AnnaBridge	161:aa5281ff4a02	594
AnnaBridge	161:aa5281ff4a02	595	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
AnnaBridge	161:aa5281ff4a02	596
AnnaBridge	161:aa5281ff4a02	597	/!< Enhanced ETHERNET DMA PTP Descriptors /
AnnaBridge	161:aa5281ff4a02	598	uint32_t ExtendedStatus; /!< Extended status for PTP receive descriptor /
AnnaBridge	161:aa5281ff4a02	599
AnnaBridge	161:aa5281ff4a02	600	uint32_t Reserved1; /!< Reserved /
AnnaBridge	161:aa5281ff4a02	601
AnnaBridge	161:aa5281ff4a02	602	uint32_t TimeStampLow; /!< Time Stamp Low value for transmit and receive /
AnnaBridge	161:aa5281ff4a02	603
AnnaBridge	161:aa5281ff4a02	604	uint32_t TimeStampHigh; /!< Time Stamp High value for transmit and receive /
AnnaBridge	161:aa5281ff4a02	605
AnnaBridge	161:aa5281ff4a02	606	} ETH_DMADescTypeDef;
AnnaBridge	161:aa5281ff4a02	607
AnnaBridge	161:aa5281ff4a02	608	/**
AnnaBridge	161:aa5281ff4a02	609	* @brief Received Frame Informations structure definition
AnnaBridge	161:aa5281ff4a02	610	*/
AnnaBridge	161:aa5281ff4a02	611	typedef struct
AnnaBridge	161:aa5281ff4a02	612	{
AnnaBridge	161:aa5281ff4a02	613	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
AnnaBridge	161:aa5281ff4a02	614
AnnaBridge	161:aa5281ff4a02	615	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
AnnaBridge	161:aa5281ff4a02	616
AnnaBridge	161:aa5281ff4a02	617	uint32_t SegCount; /!< Segment count /
AnnaBridge	161:aa5281ff4a02	618
AnnaBridge	161:aa5281ff4a02	619	uint32_t length; /!< Frame length /
AnnaBridge	161:aa5281ff4a02	620
AnnaBridge	161:aa5281ff4a02	621	uint32_t buffer; /!< Frame buffer /
AnnaBridge	161:aa5281ff4a02	622
AnnaBridge	161:aa5281ff4a02	623	} ETH_DMARxFrameInfos;
AnnaBridge	161:aa5281ff4a02	624
AnnaBridge	161:aa5281ff4a02	625	/**
AnnaBridge	161:aa5281ff4a02	626	* @brief ETH Handle Structure definition
AnnaBridge	161:aa5281ff4a02	627	*/
AnnaBridge	161:aa5281ff4a02	628
AnnaBridge	161:aa5281ff4a02	629	typedef struct
AnnaBridge	161:aa5281ff4a02	630	{
AnnaBridge	161:aa5281ff4a02	631	ETH_TypeDef Instance; /!< Register base address */
AnnaBridge	161:aa5281ff4a02	632
AnnaBridge	161:aa5281ff4a02	633	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
AnnaBridge	161:aa5281ff4a02	634
AnnaBridge	161:aa5281ff4a02	635	uint32_t LinkStatus; /!< Ethernet link status /
AnnaBridge	161:aa5281ff4a02	636
AnnaBridge	161:aa5281ff4a02	637	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
AnnaBridge	161:aa5281ff4a02	638
AnnaBridge	161:aa5281ff4a02	639	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
AnnaBridge	161:aa5281ff4a02	640
AnnaBridge	161:aa5281ff4a02	641	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
AnnaBridge	161:aa5281ff4a02	642
AnnaBridge	161:aa5281ff4a02	643	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
AnnaBridge	161:aa5281ff4a02	644
AnnaBridge	161:aa5281ff4a02	645	HAL_LockTypeDef Lock; /!< ETH Lock /
AnnaBridge	161:aa5281ff4a02	646
AnnaBridge	161:aa5281ff4a02	647	} ETH_HandleTypeDef;
AnnaBridge	161:aa5281ff4a02	648
AnnaBridge	161:aa5281ff4a02	649	/**
AnnaBridge	161:aa5281ff4a02	650	* @}
AnnaBridge	161:aa5281ff4a02	651	*/
AnnaBridge	161:aa5281ff4a02	652
AnnaBridge	161:aa5281ff4a02	653	/* Exported constants --------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	654	/** @defgroup ETH_Exported_Constants ETH Exported Constants
AnnaBridge	161:aa5281ff4a02	655	* @{
AnnaBridge	161:aa5281ff4a02	656	*/
AnnaBridge	161:aa5281ff4a02	657
AnnaBridge	161:aa5281ff4a02	658	/** @defgroup ETH_Buffers_setting ETH Buffers setting
AnnaBridge	161:aa5281ff4a02	659	* @{
AnnaBridge	161:aa5281ff4a02	660	*/
AnnaBridge	161:aa5281ff4a02	661	#define ETH_MAX_PACKET_SIZE 1524U /!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC /
AnnaBridge	161:aa5281ff4a02	662	#define ETH_HEADER 14U /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
AnnaBridge	161:aa5281ff4a02	663	#define ETH_CRC 4U /!< Ethernet CRC /
AnnaBridge	161:aa5281ff4a02	664	#define ETH_EXTRA 2U /!< Extra bytes in some cases /
AnnaBridge	161:aa5281ff4a02	665	#define ETH_VLAN_TAG 4U /!< optional 802.1q VLAN Tag /
AnnaBridge	161:aa5281ff4a02	666	#define ETH_MIN_ETH_PAYLOAD 46U /!< Minimum Ethernet payload size /
AnnaBridge	161:aa5281ff4a02	667	#define ETH_MAX_ETH_PAYLOAD 1500U /!< Maximum Ethernet payload size /
AnnaBridge	161:aa5281ff4a02	668	#define ETH_JUMBO_FRAME_PAYLOAD 9000U /!< Jumbo frame payload size /
AnnaBridge	161:aa5281ff4a02	669
AnnaBridge	161:aa5281ff4a02	670	/* Ethernet driver receive buffers are organized in a chained linked-list, when
AnnaBridge	161:aa5281ff4a02	671	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
AnnaBridge	161:aa5281ff4a02	672	to the driver receive buffers memory.
AnnaBridge	161:aa5281ff4a02	673
AnnaBridge	161:aa5281ff4a02	674	Depending on the size of the received ethernet packet and the size of
AnnaBridge	161:aa5281ff4a02	675	each ethernet driver receive buffer, the received packet can take one or more
AnnaBridge	161:aa5281ff4a02	676	ethernet driver receive buffer.
AnnaBridge	161:aa5281ff4a02	677
AnnaBridge	161:aa5281ff4a02	678	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
AnnaBridge	161:aa5281ff4a02	679	and the total count of the driver receive buffers ETH_RXBUFNB.
AnnaBridge	161:aa5281ff4a02	680
AnnaBridge	161:aa5281ff4a02	681	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
AnnaBridge	161:aa5281ff4a02	682	example, they can be reconfigured in the application layer to fit the application
AnnaBridge	161:aa5281ff4a02	683	needs */
AnnaBridge	161:aa5281ff4a02	684
AnnaBridge	161:aa5281ff4a02	685	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
AnnaBridge	161:aa5281ff4a02	686	packet */
AnnaBridge	161:aa5281ff4a02	687	#ifndef ETH_RX_BUF_SIZE
AnnaBridge	161:aa5281ff4a02	688	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
AnnaBridge	161:aa5281ff4a02	689	#endif
AnnaBridge	161:aa5281ff4a02	690
AnnaBridge	161:aa5281ff4a02	691	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
AnnaBridge	161:aa5281ff4a02	692	#ifndef ETH_RXBUFNB
AnnaBridge	161:aa5281ff4a02	693	#define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
AnnaBridge	161:aa5281ff4a02	694	#endif
AnnaBridge	161:aa5281ff4a02	695
AnnaBridge	161:aa5281ff4a02	696
AnnaBridge	161:aa5281ff4a02	697	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
AnnaBridge	161:aa5281ff4a02	698	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
AnnaBridge	161:aa5281ff4a02	699	driver transmit buffers memory to the TxFIFO.
AnnaBridge	161:aa5281ff4a02	700
AnnaBridge	161:aa5281ff4a02	701	Depending on the size of the Ethernet packet to be transmitted and the size of
AnnaBridge	161:aa5281ff4a02	702	each ethernet driver transmit buffer, the packet to be transmitted can take
AnnaBridge	161:aa5281ff4a02	703	one or more ethernet driver transmit buffer.
AnnaBridge	161:aa5281ff4a02	704
AnnaBridge	161:aa5281ff4a02	705	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
AnnaBridge	161:aa5281ff4a02	706	and the total count of the driver transmit buffers ETH_TXBUFNB.
AnnaBridge	161:aa5281ff4a02	707
AnnaBridge	161:aa5281ff4a02	708	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
AnnaBridge	161:aa5281ff4a02	709	example, they can be reconfigured in the application layer to fit the application
AnnaBridge	161:aa5281ff4a02	710	needs */
AnnaBridge	161:aa5281ff4a02	711
AnnaBridge	161:aa5281ff4a02	712	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
AnnaBridge	161:aa5281ff4a02	713	packet */
AnnaBridge	161:aa5281ff4a02	714	#ifndef ETH_TX_BUF_SIZE
AnnaBridge	161:aa5281ff4a02	715	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
AnnaBridge	161:aa5281ff4a02	716	#endif
AnnaBridge	161:aa5281ff4a02	717
AnnaBridge	161:aa5281ff4a02	718	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
AnnaBridge	161:aa5281ff4a02	719	#ifndef ETH_TXBUFNB
AnnaBridge	161:aa5281ff4a02	720	#define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
AnnaBridge	161:aa5281ff4a02	721	#endif
AnnaBridge	161:aa5281ff4a02	722
AnnaBridge	161:aa5281ff4a02	723	/**
AnnaBridge	161:aa5281ff4a02	724	* @}
AnnaBridge	161:aa5281ff4a02	725	*/
AnnaBridge	161:aa5281ff4a02	726
AnnaBridge	161:aa5281ff4a02	727	/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
AnnaBridge	161:aa5281ff4a02	728	* @{
AnnaBridge	161:aa5281ff4a02	729	*/
AnnaBridge	161:aa5281ff4a02	730
AnnaBridge	161:aa5281ff4a02	731	/*
AnnaBridge	161:aa5281ff4a02	732	DMA Tx Descriptor
AnnaBridge	161:aa5281ff4a02	733	-----------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	734	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
AnnaBridge	161:aa5281ff4a02	735	-----------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	736	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
AnnaBridge	161:aa5281ff4a02	737	-----------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	738	TDES2 \| Buffer1 Address [31:0] \|
AnnaBridge	161:aa5281ff4a02	739	-----------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	740	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
AnnaBridge	161:aa5281ff4a02	741	-----------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	742	*/
AnnaBridge	161:aa5281ff4a02	743
AnnaBridge	161:aa5281ff4a02	744	/**
AnnaBridge	161:aa5281ff4a02	745	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
AnnaBridge	161:aa5281ff4a02	746	*/
AnnaBridge	161:aa5281ff4a02	747	#define ETH_DMATXDESC_OWN 0x80000000U /!< OWN bit: descriptor is owned by DMA engine /
AnnaBridge	161:aa5281ff4a02	748	#define ETH_DMATXDESC_IC 0x40000000U /!< Interrupt on Completion /
AnnaBridge	161:aa5281ff4a02	749	#define ETH_DMATXDESC_LS 0x20000000U /!< Last Segment /
AnnaBridge	161:aa5281ff4a02	750	#define ETH_DMATXDESC_FS 0x10000000U /!< First Segment /
AnnaBridge	161:aa5281ff4a02	751	#define ETH_DMATXDESC_DC 0x08000000U /!< Disable CRC /
AnnaBridge	161:aa5281ff4a02	752	#define ETH_DMATXDESC_DP 0x04000000U /!< Disable Padding /
AnnaBridge	161:aa5281ff4a02	753	#define ETH_DMATXDESC_TTSE 0x02000000U /!< Transmit Time Stamp Enable /
AnnaBridge	161:aa5281ff4a02	754	#define ETH_DMATXDESC_CIC 0x00C00000U /!< Checksum Insertion Control: 4 cases /
AnnaBridge	161:aa5281ff4a02	755	#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /!< Do Nothing: Checksum Engine is bypassed /
AnnaBridge	161:aa5281ff4a02	756	#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /!< IPV4 header Checksum Insertion /
AnnaBridge	161:aa5281ff4a02	757	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
AnnaBridge	161:aa5281ff4a02	758	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
AnnaBridge	161:aa5281ff4a02	759	#define ETH_DMATXDESC_TER 0x00200000U /!< Transmit End of Ring /
AnnaBridge	161:aa5281ff4a02	760	#define ETH_DMATXDESC_TCH 0x00100000U /!< Second Address Chained /
AnnaBridge	161:aa5281ff4a02	761	#define ETH_DMATXDESC_TTSS 0x00020000U /!< Tx Time Stamp Status /
AnnaBridge	161:aa5281ff4a02	762	#define ETH_DMATXDESC_IHE 0x00010000U /!< IP Header Error /
AnnaBridge	161:aa5281ff4a02	763	#define ETH_DMATXDESC_ES 0x00008000U /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
AnnaBridge	161:aa5281ff4a02	764	#define ETH_DMATXDESC_JT 0x00004000U /!< Jabber Timeout /
AnnaBridge	161:aa5281ff4a02	765	#define ETH_DMATXDESC_FF 0x00002000U /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
AnnaBridge	161:aa5281ff4a02	766	#define ETH_DMATXDESC_PCE 0x00001000U /!< Payload Checksum Error /
AnnaBridge	161:aa5281ff4a02	767	#define ETH_DMATXDESC_LCA 0x00000800U /!< Loss of Carrier: carrier lost during transmission /
AnnaBridge	161:aa5281ff4a02	768	#define ETH_DMATXDESC_NC 0x00000400U /!< No Carrier: no carrier signal from the transceiver /
AnnaBridge	161:aa5281ff4a02	769	#define ETH_DMATXDESC_LCO 0x00000200U /!< Late Collision: transmission aborted due to collision /
AnnaBridge	161:aa5281ff4a02	770	#define ETH_DMATXDESC_EC 0x00000100U /!< Excessive Collision: transmission aborted after 16 collisions /
AnnaBridge	161:aa5281ff4a02	771	#define ETH_DMATXDESC_VF 0x00000080U /!< VLAN Frame /
AnnaBridge	161:aa5281ff4a02	772	#define ETH_DMATXDESC_CC 0x00000078U /!< Collision Count /
AnnaBridge	161:aa5281ff4a02	773	#define ETH_DMATXDESC_ED 0x00000004U /!< Excessive Deferral /
AnnaBridge	161:aa5281ff4a02	774	#define ETH_DMATXDESC_UF 0x00000002U /!< Underflow Error: late data arrival from the memory /
AnnaBridge	161:aa5281ff4a02	775	#define ETH_DMATXDESC_DB 0x00000001U /!< Deferred Bit /
AnnaBridge	161:aa5281ff4a02	776
AnnaBridge	161:aa5281ff4a02	777	/**
AnnaBridge	161:aa5281ff4a02	778	* @brief Bit definition of TDES1 register
AnnaBridge	161:aa5281ff4a02	779	*/
AnnaBridge	161:aa5281ff4a02	780	#define ETH_DMATXDESC_TBS2 0x1FFF0000U /!< Transmit Buffer2 Size /
AnnaBridge	161:aa5281ff4a02	781	#define ETH_DMATXDESC_TBS1 0x00001FFFU /!< Transmit Buffer1 Size /
AnnaBridge	161:aa5281ff4a02	782
AnnaBridge	161:aa5281ff4a02	783	/**
AnnaBridge	161:aa5281ff4a02	784	* @brief Bit definition of TDES2 register
AnnaBridge	161:aa5281ff4a02	785	*/
AnnaBridge	161:aa5281ff4a02	786	#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /!< Buffer1 Address Pointer /
AnnaBridge	161:aa5281ff4a02	787
AnnaBridge	161:aa5281ff4a02	788	/**
AnnaBridge	161:aa5281ff4a02	789	* @brief Bit definition of TDES3 register
AnnaBridge	161:aa5281ff4a02	790	*/
AnnaBridge	161:aa5281ff4a02	791	#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /!< Buffer2 Address Pointer /
AnnaBridge	161:aa5281ff4a02	792
AnnaBridge	161:aa5281ff4a02	793	/*---------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	794	TDES6 \| Transmit Time Stamp Low [31:0] \|
AnnaBridge	161:aa5281ff4a02	795	-----------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	796	TDES7 \| Transmit Time Stamp High [31:0] \|
AnnaBridge	161:aa5281ff4a02	797	----------------------------------------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	798
AnnaBridge	161:aa5281ff4a02	799	/* Bit definition of TDES6 register */
AnnaBridge	161:aa5281ff4a02	800	#define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
AnnaBridge	161:aa5281ff4a02	801
AnnaBridge	161:aa5281ff4a02	802	/* Bit definition of TDES7 register */
AnnaBridge	161:aa5281ff4a02	803	#define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
AnnaBridge	161:aa5281ff4a02	804
AnnaBridge	161:aa5281ff4a02	805	/**
AnnaBridge	161:aa5281ff4a02	806	* @}
AnnaBridge	161:aa5281ff4a02	807	*/
AnnaBridge	161:aa5281ff4a02	808	/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
AnnaBridge	161:aa5281ff4a02	809	* @{
AnnaBridge	161:aa5281ff4a02	810	*/
AnnaBridge	161:aa5281ff4a02	811
AnnaBridge	161:aa5281ff4a02	812	/*
AnnaBridge	161:aa5281ff4a02	813	DMA Rx Descriptor
AnnaBridge	161:aa5281ff4a02	814	--------------------------------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	815	RDES0 \| OWN(31) \| Status [30:0] \|
AnnaBridge	161:aa5281ff4a02	816	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	817	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
AnnaBridge	161:aa5281ff4a02	818	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	819	RDES2 \| Buffer1 Address [31:0] \|
AnnaBridge	161:aa5281ff4a02	820	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	821	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
AnnaBridge	161:aa5281ff4a02	822	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	823	*/
AnnaBridge	161:aa5281ff4a02	824
AnnaBridge	161:aa5281ff4a02	825	/**
AnnaBridge	161:aa5281ff4a02	826	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
AnnaBridge	161:aa5281ff4a02	827	*/
AnnaBridge	161:aa5281ff4a02	828	#define ETH_DMARXDESC_OWN 0x80000000U /!< OWN bit: descriptor is owned by DMA engine /
AnnaBridge	161:aa5281ff4a02	829	#define ETH_DMARXDESC_AFM 0x40000000U /!< DA Filter Fail for the rx frame /
AnnaBridge	161:aa5281ff4a02	830	#define ETH_DMARXDESC_FL 0x3FFF0000U /!< Receive descriptor frame length /
AnnaBridge	161:aa5281ff4a02	831	#define ETH_DMARXDESC_ES 0x00008000U /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
AnnaBridge	161:aa5281ff4a02	832	#define ETH_DMARXDESC_DE 0x00004000U /!< Descriptor error: no more descriptors for receive frame /
AnnaBridge	161:aa5281ff4a02	833	#define ETH_DMARXDESC_SAF 0x00002000U /!< SA Filter Fail for the received frame /
AnnaBridge	161:aa5281ff4a02	834	#define ETH_DMARXDESC_LE 0x00001000U /!< Frame size not matching with length field /
AnnaBridge	161:aa5281ff4a02	835	#define ETH_DMARXDESC_OE 0x00000800U /!< Overflow Error: Frame was damaged due to buffer overflow /
AnnaBridge	161:aa5281ff4a02	836	#define ETH_DMARXDESC_VLAN 0x00000400U /!< VLAN Tag: received frame is a VLAN frame /
AnnaBridge	161:aa5281ff4a02	837	#define ETH_DMARXDESC_FS 0x00000200U /!< First descriptor of the frame /
AnnaBridge	161:aa5281ff4a02	838	#define ETH_DMARXDESC_LS 0x00000100U /!< Last descriptor of the frame /
AnnaBridge	161:aa5281ff4a02	839	#define ETH_DMARXDESC_IPV4HCE 0x00000080U /!< IPC Checksum Error: Rx Ipv4 header checksum error /
AnnaBridge	161:aa5281ff4a02	840	#define ETH_DMARXDESC_LC 0x00000040U /!< Late collision occurred during reception /
AnnaBridge	161:aa5281ff4a02	841	#define ETH_DMARXDESC_FT 0x00000020U /!< Frame type - Ethernet, otherwise 802.3 /
AnnaBridge	161:aa5281ff4a02	842	#define ETH_DMARXDESC_RWT 0x00000010U /!< Receive Watchdog Timeout: watchdog timer expired during reception /
AnnaBridge	161:aa5281ff4a02	843	#define ETH_DMARXDESC_RE 0x00000008U /!< Receive error: error reported by MII interface /
AnnaBridge	161:aa5281ff4a02	844	#define ETH_DMARXDESC_DBE 0x00000004U /!< Dribble bit error: frame contains non int multiple of 8 bits /
AnnaBridge	161:aa5281ff4a02	845	#define ETH_DMARXDESC_CE 0x00000002U /!< CRC error /
AnnaBridge	161:aa5281ff4a02	846	#define ETH_DMARXDESC_MAMPCE 0x00000001U /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
AnnaBridge	161:aa5281ff4a02	847
AnnaBridge	161:aa5281ff4a02	848	/**
AnnaBridge	161:aa5281ff4a02	849	* @brief Bit definition of RDES1 register
AnnaBridge	161:aa5281ff4a02	850	*/
AnnaBridge	161:aa5281ff4a02	851	#define ETH_DMARXDESC_DIC 0x80000000U /!< Disable Interrupt on Completion /
AnnaBridge	161:aa5281ff4a02	852	#define ETH_DMARXDESC_RBS2 0x1FFF0000U /!< Receive Buffer2 Size /
AnnaBridge	161:aa5281ff4a02	853	#define ETH_DMARXDESC_RER 0x00008000U /!< Receive End of Ring /
AnnaBridge	161:aa5281ff4a02	854	#define ETH_DMARXDESC_RCH 0x00004000U /!< Second Address Chained /
AnnaBridge	161:aa5281ff4a02	855	#define ETH_DMARXDESC_RBS1 0x00001FFFU /!< Receive Buffer1 Size /
AnnaBridge	161:aa5281ff4a02	856
AnnaBridge	161:aa5281ff4a02	857	/**
AnnaBridge	161:aa5281ff4a02	858	* @brief Bit definition of RDES2 register
AnnaBridge	161:aa5281ff4a02	859	*/
AnnaBridge	161:aa5281ff4a02	860	#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /!< Buffer1 Address Pointer /
AnnaBridge	161:aa5281ff4a02	861
AnnaBridge	161:aa5281ff4a02	862	/**
AnnaBridge	161:aa5281ff4a02	863	* @brief Bit definition of RDES3 register
AnnaBridge	161:aa5281ff4a02	864	*/
AnnaBridge	161:aa5281ff4a02	865	#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /!< Buffer2 Address Pointer /
AnnaBridge	161:aa5281ff4a02	866
AnnaBridge	161:aa5281ff4a02	867	/*---------------------------------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	868	RDES4 \| Reserved[31:15] \| Extended Status [14:0] \|
AnnaBridge	161:aa5281ff4a02	869	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	870	RDES5 \| Reserved[31:0] \|
AnnaBridge	161:aa5281ff4a02	871	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	872	RDES6 \| Receive Time Stamp Low [31:0] \|
AnnaBridge	161:aa5281ff4a02	873	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	161:aa5281ff4a02	874	RDES7 \| Receive Time Stamp High [31:0] \|
AnnaBridge	161:aa5281ff4a02	875	--------------------------------------------------------------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	876
AnnaBridge	161:aa5281ff4a02	877	/* Bit definition of RDES4 register */
AnnaBridge	161:aa5281ff4a02	878	#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
AnnaBridge	161:aa5281ff4a02	879	#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
AnnaBridge	161:aa5281ff4a02	880	#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
AnnaBridge	161:aa5281ff4a02	881	#define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
AnnaBridge	161:aa5281ff4a02	882	#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
AnnaBridge	161:aa5281ff4a02	883	#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
AnnaBridge	161:aa5281ff4a02	884	#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
AnnaBridge	161:aa5281ff4a02	885	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
AnnaBridge	161:aa5281ff4a02	886	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
AnnaBridge	161:aa5281ff4a02	887	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
AnnaBridge	161:aa5281ff4a02	888	#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
AnnaBridge	161:aa5281ff4a02	889	#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
AnnaBridge	161:aa5281ff4a02	890	#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
AnnaBridge	161:aa5281ff4a02	891	#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
AnnaBridge	161:aa5281ff4a02	892	#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
AnnaBridge	161:aa5281ff4a02	893	#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
AnnaBridge	161:aa5281ff4a02	894	#define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
AnnaBridge	161:aa5281ff4a02	895	#define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
AnnaBridge	161:aa5281ff4a02	896	#define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
AnnaBridge	161:aa5281ff4a02	897
AnnaBridge	161:aa5281ff4a02	898	/* Bit definition of RDES6 register */
AnnaBridge	161:aa5281ff4a02	899	#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
AnnaBridge	161:aa5281ff4a02	900
AnnaBridge	161:aa5281ff4a02	901	/* Bit definition of RDES7 register */
AnnaBridge	161:aa5281ff4a02	902	#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
AnnaBridge	161:aa5281ff4a02	903	/**
AnnaBridge	161:aa5281ff4a02	904	* @}
AnnaBridge	161:aa5281ff4a02	905	*/
AnnaBridge	161:aa5281ff4a02	906	/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
AnnaBridge	161:aa5281ff4a02	907	* @{
AnnaBridge	161:aa5281ff4a02	908	*/
AnnaBridge	161:aa5281ff4a02	909	#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
AnnaBridge	161:aa5281ff4a02	910	#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	911
AnnaBridge	161:aa5281ff4a02	912	/**
AnnaBridge	161:aa5281ff4a02	913	* @}
AnnaBridge	161:aa5281ff4a02	914	*/
AnnaBridge	161:aa5281ff4a02	915	/** @defgroup ETH_Speed ETH Speed
AnnaBridge	161:aa5281ff4a02	916	* @{
AnnaBridge	161:aa5281ff4a02	917	*/
AnnaBridge	161:aa5281ff4a02	918	#define ETH_SPEED_10M 0x00000000U
AnnaBridge	161:aa5281ff4a02	919	#define ETH_SPEED_100M 0x00004000U
AnnaBridge	161:aa5281ff4a02	920
AnnaBridge	161:aa5281ff4a02	921	/**
AnnaBridge	161:aa5281ff4a02	922	* @}
AnnaBridge	161:aa5281ff4a02	923	*/
AnnaBridge	161:aa5281ff4a02	924	/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
AnnaBridge	161:aa5281ff4a02	925	* @{
AnnaBridge	161:aa5281ff4a02	926	*/
AnnaBridge	161:aa5281ff4a02	927	#define ETH_MODE_FULLDUPLEX 0x00000800U
AnnaBridge	161:aa5281ff4a02	928	#define ETH_MODE_HALFDUPLEX 0x00000000U
AnnaBridge	161:aa5281ff4a02	929	/**
AnnaBridge	161:aa5281ff4a02	930	* @}
AnnaBridge	161:aa5281ff4a02	931	*/
AnnaBridge	161:aa5281ff4a02	932	/** @defgroup ETH_Rx_Mode ETH Rx Mode
AnnaBridge	161:aa5281ff4a02	933	* @{
AnnaBridge	161:aa5281ff4a02	934	*/
AnnaBridge	161:aa5281ff4a02	935	#define ETH_RXPOLLING_MODE 0x00000000U
AnnaBridge	161:aa5281ff4a02	936	#define ETH_RXINTERRUPT_MODE 0x00000001U
AnnaBridge	161:aa5281ff4a02	937	/**
AnnaBridge	161:aa5281ff4a02	938	* @}
AnnaBridge	161:aa5281ff4a02	939	*/
AnnaBridge	161:aa5281ff4a02	940
AnnaBridge	161:aa5281ff4a02	941	/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
AnnaBridge	161:aa5281ff4a02	942	* @{
AnnaBridge	161:aa5281ff4a02	943	*/
AnnaBridge	161:aa5281ff4a02	944	#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
AnnaBridge	161:aa5281ff4a02	945	#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
AnnaBridge	161:aa5281ff4a02	946	/**
AnnaBridge	161:aa5281ff4a02	947	* @}
AnnaBridge	161:aa5281ff4a02	948	*/
AnnaBridge	161:aa5281ff4a02	949
AnnaBridge	161:aa5281ff4a02	950	/** @defgroup ETH_Media_Interface ETH Media Interface
AnnaBridge	161:aa5281ff4a02	951	* @{
AnnaBridge	161:aa5281ff4a02	952	*/
AnnaBridge	161:aa5281ff4a02	953	#define ETH_MEDIA_INTERFACE_MII 0x00000000U
AnnaBridge	161:aa5281ff4a02	954	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
AnnaBridge	161:aa5281ff4a02	955	/**
AnnaBridge	161:aa5281ff4a02	956	* @}
AnnaBridge	161:aa5281ff4a02	957	*/
AnnaBridge	161:aa5281ff4a02	958
AnnaBridge	161:aa5281ff4a02	959	/** @defgroup ETH_Watchdog ETH Watchdog
AnnaBridge	161:aa5281ff4a02	960	* @{
AnnaBridge	161:aa5281ff4a02	961	*/
AnnaBridge	161:aa5281ff4a02	962	#define ETH_WATCHDOG_ENABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	963	#define ETH_WATCHDOG_DISABLE 0x00800000U
AnnaBridge	161:aa5281ff4a02	964	/**
AnnaBridge	161:aa5281ff4a02	965	* @}
AnnaBridge	161:aa5281ff4a02	966	*/
AnnaBridge	161:aa5281ff4a02	967
AnnaBridge	161:aa5281ff4a02	968	/** @defgroup ETH_Jabber ETH Jabber
AnnaBridge	161:aa5281ff4a02	969	* @{
AnnaBridge	161:aa5281ff4a02	970	*/
AnnaBridge	161:aa5281ff4a02	971	#define ETH_JABBER_ENABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	972	#define ETH_JABBER_DISABLE 0x00400000U
AnnaBridge	161:aa5281ff4a02	973	/**
AnnaBridge	161:aa5281ff4a02	974	* @}
AnnaBridge	161:aa5281ff4a02	975	*/
AnnaBridge	161:aa5281ff4a02	976
AnnaBridge	161:aa5281ff4a02	977	/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
AnnaBridge	161:aa5281ff4a02	978	* @{
AnnaBridge	161:aa5281ff4a02	979	*/
AnnaBridge	161:aa5281ff4a02	980	#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /!< minimum IFG between frames during transmission is 96Bit /
AnnaBridge	161:aa5281ff4a02	981	#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /!< minimum IFG between frames during transmission is 88Bit /
AnnaBridge	161:aa5281ff4a02	982	#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /!< minimum IFG between frames during transmission is 80Bit /
AnnaBridge	161:aa5281ff4a02	983	#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /!< minimum IFG between frames during transmission is 72Bit /
AnnaBridge	161:aa5281ff4a02	984	#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /!< minimum IFG between frames during transmission is 64Bit /
AnnaBridge	161:aa5281ff4a02	985	#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /!< minimum IFG between frames during transmission is 56Bit /
AnnaBridge	161:aa5281ff4a02	986	#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /!< minimum IFG between frames during transmission is 48Bit /
AnnaBridge	161:aa5281ff4a02	987	#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /!< minimum IFG between frames during transmission is 40Bit /
AnnaBridge	161:aa5281ff4a02	988	/**
AnnaBridge	161:aa5281ff4a02	989	* @}
AnnaBridge	161:aa5281ff4a02	990	*/
AnnaBridge	161:aa5281ff4a02	991
AnnaBridge	161:aa5281ff4a02	992	/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
AnnaBridge	161:aa5281ff4a02	993	* @{
AnnaBridge	161:aa5281ff4a02	994	*/
AnnaBridge	161:aa5281ff4a02	995	#define ETH_CARRIERSENCE_ENABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	996	#define ETH_CARRIERSENCE_DISABLE 0x00010000U
AnnaBridge	161:aa5281ff4a02	997	/**
AnnaBridge	161:aa5281ff4a02	998	* @}
AnnaBridge	161:aa5281ff4a02	999	*/
AnnaBridge	161:aa5281ff4a02	1000
AnnaBridge	161:aa5281ff4a02	1001	/** @defgroup ETH_Receive_Own ETH Receive Own
AnnaBridge	161:aa5281ff4a02	1002	* @{
AnnaBridge	161:aa5281ff4a02	1003	*/
AnnaBridge	161:aa5281ff4a02	1004	#define ETH_RECEIVEOWN_ENABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1005	#define ETH_RECEIVEOWN_DISABLE 0x00002000U
AnnaBridge	161:aa5281ff4a02	1006	/**
AnnaBridge	161:aa5281ff4a02	1007	* @}
AnnaBridge	161:aa5281ff4a02	1008	*/
AnnaBridge	161:aa5281ff4a02	1009
AnnaBridge	161:aa5281ff4a02	1010	/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
AnnaBridge	161:aa5281ff4a02	1011	* @{
AnnaBridge	161:aa5281ff4a02	1012	*/
AnnaBridge	161:aa5281ff4a02	1013	#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
AnnaBridge	161:aa5281ff4a02	1014	#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1015	/**
AnnaBridge	161:aa5281ff4a02	1016	* @}
AnnaBridge	161:aa5281ff4a02	1017	*/
AnnaBridge	161:aa5281ff4a02	1018
AnnaBridge	161:aa5281ff4a02	1019	/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
AnnaBridge	161:aa5281ff4a02	1020	* @{
AnnaBridge	161:aa5281ff4a02	1021	*/
AnnaBridge	161:aa5281ff4a02	1022	#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
AnnaBridge	161:aa5281ff4a02	1023	#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1024	/**
AnnaBridge	161:aa5281ff4a02	1025	* @}
AnnaBridge	161:aa5281ff4a02	1026	*/
AnnaBridge	161:aa5281ff4a02	1027
AnnaBridge	161:aa5281ff4a02	1028	/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
AnnaBridge	161:aa5281ff4a02	1029	* @{
AnnaBridge	161:aa5281ff4a02	1030	*/
AnnaBridge	161:aa5281ff4a02	1031	#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1032	#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
AnnaBridge	161:aa5281ff4a02	1033	/**
AnnaBridge	161:aa5281ff4a02	1034	* @}
AnnaBridge	161:aa5281ff4a02	1035	*/
AnnaBridge	161:aa5281ff4a02	1036
AnnaBridge	161:aa5281ff4a02	1037	/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
AnnaBridge	161:aa5281ff4a02	1038	* @{
AnnaBridge	161:aa5281ff4a02	1039	*/
AnnaBridge	161:aa5281ff4a02	1040	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
AnnaBridge	161:aa5281ff4a02	1041	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1042	/**
AnnaBridge	161:aa5281ff4a02	1043	* @}
AnnaBridge	161:aa5281ff4a02	1044	*/
AnnaBridge	161:aa5281ff4a02	1045
AnnaBridge	161:aa5281ff4a02	1046	/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
AnnaBridge	161:aa5281ff4a02	1047	* @{
AnnaBridge	161:aa5281ff4a02	1048	*/
AnnaBridge	161:aa5281ff4a02	1049	#define ETH_BACKOFFLIMIT_10 0x00000000U
AnnaBridge	161:aa5281ff4a02	1050	#define ETH_BACKOFFLIMIT_8 0x00000020U
AnnaBridge	161:aa5281ff4a02	1051	#define ETH_BACKOFFLIMIT_4 0x00000040U
AnnaBridge	161:aa5281ff4a02	1052	#define ETH_BACKOFFLIMIT_1 0x00000060U
AnnaBridge	161:aa5281ff4a02	1053	/**
AnnaBridge	161:aa5281ff4a02	1054	* @}
AnnaBridge	161:aa5281ff4a02	1055	*/
AnnaBridge	161:aa5281ff4a02	1056
AnnaBridge	161:aa5281ff4a02	1057	/** @defgroup ETH_Deferral_Check ETH Deferral Check
AnnaBridge	161:aa5281ff4a02	1058	* @{
AnnaBridge	161:aa5281ff4a02	1059	*/
AnnaBridge	161:aa5281ff4a02	1060	#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
AnnaBridge	161:aa5281ff4a02	1061	#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1062	/**
AnnaBridge	161:aa5281ff4a02	1063	* @}
AnnaBridge	161:aa5281ff4a02	1064	*/
AnnaBridge	161:aa5281ff4a02	1065
AnnaBridge	161:aa5281ff4a02	1066	/** @defgroup ETH_Receive_All ETH Receive All
AnnaBridge	161:aa5281ff4a02	1067	* @{
AnnaBridge	161:aa5281ff4a02	1068	*/
AnnaBridge	161:aa5281ff4a02	1069	#define ETH_RECEIVEALL_ENABLE 0x80000000U
AnnaBridge	161:aa5281ff4a02	1070	#define ETH_RECEIVEAll_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1071	/**
AnnaBridge	161:aa5281ff4a02	1072	* @}
AnnaBridge	161:aa5281ff4a02	1073	*/
AnnaBridge	161:aa5281ff4a02	1074
AnnaBridge	161:aa5281ff4a02	1075	/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
AnnaBridge	161:aa5281ff4a02	1076	* @{
AnnaBridge	161:aa5281ff4a02	1077	*/
AnnaBridge	161:aa5281ff4a02	1078	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
AnnaBridge	161:aa5281ff4a02	1079	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
AnnaBridge	161:aa5281ff4a02	1080	#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1081	/**
AnnaBridge	161:aa5281ff4a02	1082	* @}
AnnaBridge	161:aa5281ff4a02	1083	*/
AnnaBridge	161:aa5281ff4a02	1084
AnnaBridge	161:aa5281ff4a02	1085	/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
AnnaBridge	161:aa5281ff4a02	1086	* @{
AnnaBridge	161:aa5281ff4a02	1087	*/
AnnaBridge	161:aa5281ff4a02	1088	#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /!< MAC filters all control frames from reaching the application /
AnnaBridge	161:aa5281ff4a02	1089	#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /!< MAC forwards all control frames to application even if they fail the Address Filter /
AnnaBridge	161:aa5281ff4a02	1090	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /!< MAC forwards control frames that pass the Address Filter. /
AnnaBridge	161:aa5281ff4a02	1091	/**
AnnaBridge	161:aa5281ff4a02	1092	* @}
AnnaBridge	161:aa5281ff4a02	1093	*/
AnnaBridge	161:aa5281ff4a02	1094
AnnaBridge	161:aa5281ff4a02	1095	/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
AnnaBridge	161:aa5281ff4a02	1096	* @{
AnnaBridge	161:aa5281ff4a02	1097	*/
AnnaBridge	161:aa5281ff4a02	1098	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1099	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
AnnaBridge	161:aa5281ff4a02	1100	/**
AnnaBridge	161:aa5281ff4a02	1101	* @}
AnnaBridge	161:aa5281ff4a02	1102	*/
AnnaBridge	161:aa5281ff4a02	1103
AnnaBridge	161:aa5281ff4a02	1104	/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
AnnaBridge	161:aa5281ff4a02	1105	* @{
AnnaBridge	161:aa5281ff4a02	1106	*/
AnnaBridge	161:aa5281ff4a02	1107	#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
AnnaBridge	161:aa5281ff4a02	1108	#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
AnnaBridge	161:aa5281ff4a02	1109	/**
AnnaBridge	161:aa5281ff4a02	1110	* @}
AnnaBridge	161:aa5281ff4a02	1111	*/
AnnaBridge	161:aa5281ff4a02	1112
AnnaBridge	161:aa5281ff4a02	1113	/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
AnnaBridge	161:aa5281ff4a02	1114	* @{
AnnaBridge	161:aa5281ff4a02	1115	*/
AnnaBridge	161:aa5281ff4a02	1116	#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
AnnaBridge	161:aa5281ff4a02	1117	#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1118	/**
AnnaBridge	161:aa5281ff4a02	1119	* @}
AnnaBridge	161:aa5281ff4a02	1120	*/
AnnaBridge	161:aa5281ff4a02	1121
AnnaBridge	161:aa5281ff4a02	1122	/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
AnnaBridge	161:aa5281ff4a02	1123	* @{
AnnaBridge	161:aa5281ff4a02	1124	*/
AnnaBridge	161:aa5281ff4a02	1125	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
AnnaBridge	161:aa5281ff4a02	1126	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
AnnaBridge	161:aa5281ff4a02	1127	#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
AnnaBridge	161:aa5281ff4a02	1128	#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
AnnaBridge	161:aa5281ff4a02	1129	/**
AnnaBridge	161:aa5281ff4a02	1130	* @}
AnnaBridge	161:aa5281ff4a02	1131	*/
AnnaBridge	161:aa5281ff4a02	1132
AnnaBridge	161:aa5281ff4a02	1133	/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
AnnaBridge	161:aa5281ff4a02	1134	* @{
AnnaBridge	161:aa5281ff4a02	1135	*/
AnnaBridge	161:aa5281ff4a02	1136	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
AnnaBridge	161:aa5281ff4a02	1137	#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
AnnaBridge	161:aa5281ff4a02	1138	#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
AnnaBridge	161:aa5281ff4a02	1139	/**
AnnaBridge	161:aa5281ff4a02	1140	* @}
AnnaBridge	161:aa5281ff4a02	1141	*/
AnnaBridge	161:aa5281ff4a02	1142
AnnaBridge	161:aa5281ff4a02	1143	/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
AnnaBridge	161:aa5281ff4a02	1144	* @{
AnnaBridge	161:aa5281ff4a02	1145	*/
AnnaBridge	161:aa5281ff4a02	1146	#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1147	#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
AnnaBridge	161:aa5281ff4a02	1148	/**
AnnaBridge	161:aa5281ff4a02	1149	* @}
AnnaBridge	161:aa5281ff4a02	1150	*/
AnnaBridge	161:aa5281ff4a02	1151
AnnaBridge	161:aa5281ff4a02	1152	/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
AnnaBridge	161:aa5281ff4a02	1153	* @{
AnnaBridge	161:aa5281ff4a02	1154	*/
AnnaBridge	161:aa5281ff4a02	1155	#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /!< Pause time minus 4 slot times /
AnnaBridge	161:aa5281ff4a02	1156	#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /!< Pause time minus 28 slot times /
AnnaBridge	161:aa5281ff4a02	1157	#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /!< Pause time minus 144 slot times /
AnnaBridge	161:aa5281ff4a02	1158	#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /!< Pause time minus 256 slot times /
AnnaBridge	161:aa5281ff4a02	1159	/**
AnnaBridge	161:aa5281ff4a02	1160	* @}
AnnaBridge	161:aa5281ff4a02	1161	*/
AnnaBridge	161:aa5281ff4a02	1162
AnnaBridge	161:aa5281ff4a02	1163	/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
AnnaBridge	161:aa5281ff4a02	1164	* @{
AnnaBridge	161:aa5281ff4a02	1165	*/
AnnaBridge	161:aa5281ff4a02	1166	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
AnnaBridge	161:aa5281ff4a02	1167	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1168	/**
AnnaBridge	161:aa5281ff4a02	1169	* @}
AnnaBridge	161:aa5281ff4a02	1170	*/
AnnaBridge	161:aa5281ff4a02	1171
AnnaBridge	161:aa5281ff4a02	1172	/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
AnnaBridge	161:aa5281ff4a02	1173	* @{
AnnaBridge	161:aa5281ff4a02	1174	*/
AnnaBridge	161:aa5281ff4a02	1175	#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
AnnaBridge	161:aa5281ff4a02	1176	#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1177	/**
AnnaBridge	161:aa5281ff4a02	1178	* @}
AnnaBridge	161:aa5281ff4a02	1179	*/
AnnaBridge	161:aa5281ff4a02	1180
AnnaBridge	161:aa5281ff4a02	1181	/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
AnnaBridge	161:aa5281ff4a02	1182	* @{
AnnaBridge	161:aa5281ff4a02	1183	*/
AnnaBridge	161:aa5281ff4a02	1184	#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
AnnaBridge	161:aa5281ff4a02	1185	#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1186	/**
AnnaBridge	161:aa5281ff4a02	1187	* @}
AnnaBridge	161:aa5281ff4a02	1188	*/
AnnaBridge	161:aa5281ff4a02	1189
AnnaBridge	161:aa5281ff4a02	1190	/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
AnnaBridge	161:aa5281ff4a02	1191	* @{
AnnaBridge	161:aa5281ff4a02	1192	*/
AnnaBridge	161:aa5281ff4a02	1193	#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
AnnaBridge	161:aa5281ff4a02	1194	#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
AnnaBridge	161:aa5281ff4a02	1195	/**
AnnaBridge	161:aa5281ff4a02	1196	* @}
AnnaBridge	161:aa5281ff4a02	1197	*/
AnnaBridge	161:aa5281ff4a02	1198
AnnaBridge	161:aa5281ff4a02	1199	/** @defgroup ETH_MAC_addresses ETH MAC addresses
AnnaBridge	161:aa5281ff4a02	1200	* @{
AnnaBridge	161:aa5281ff4a02	1201	*/
AnnaBridge	161:aa5281ff4a02	1202	#define ETH_MAC_ADDRESS0 0x00000000U
AnnaBridge	161:aa5281ff4a02	1203	#define ETH_MAC_ADDRESS1 0x00000008U
AnnaBridge	161:aa5281ff4a02	1204	#define ETH_MAC_ADDRESS2 0x00000010U
AnnaBridge	161:aa5281ff4a02	1205	#define ETH_MAC_ADDRESS3 0x00000018U
AnnaBridge	161:aa5281ff4a02	1206	/**
AnnaBridge	161:aa5281ff4a02	1207	* @}
AnnaBridge	161:aa5281ff4a02	1208	*/
AnnaBridge	161:aa5281ff4a02	1209
AnnaBridge	161:aa5281ff4a02	1210	/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
AnnaBridge	161:aa5281ff4a02	1211	* @{
AnnaBridge	161:aa5281ff4a02	1212	*/
AnnaBridge	161:aa5281ff4a02	1213	#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
AnnaBridge	161:aa5281ff4a02	1214	#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
AnnaBridge	161:aa5281ff4a02	1215	/**
AnnaBridge	161:aa5281ff4a02	1216	* @}
AnnaBridge	161:aa5281ff4a02	1217	*/
AnnaBridge	161:aa5281ff4a02	1218
AnnaBridge	161:aa5281ff4a02	1219	/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
AnnaBridge	161:aa5281ff4a02	1220	* @{
AnnaBridge	161:aa5281ff4a02	1221	*/
AnnaBridge	161:aa5281ff4a02	1222	#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /!< Mask MAC Address high reg bits [15:8] /
AnnaBridge	161:aa5281ff4a02	1223	#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /!< Mask MAC Address high reg bits [7:0] /
AnnaBridge	161:aa5281ff4a02	1224	#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /!< Mask MAC Address low reg bits [31:24] /
AnnaBridge	161:aa5281ff4a02	1225	#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /!< Mask MAC Address low reg bits [23:16] /
AnnaBridge	161:aa5281ff4a02	1226	#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /!< Mask MAC Address low reg bits [15:8] /
AnnaBridge	161:aa5281ff4a02	1227	#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /!< Mask MAC Address low reg bits [70] /
AnnaBridge	161:aa5281ff4a02	1228	/**
AnnaBridge	161:aa5281ff4a02	1229	* @}
AnnaBridge	161:aa5281ff4a02	1230	*/
AnnaBridge	161:aa5281ff4a02	1231
AnnaBridge	161:aa5281ff4a02	1232	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
AnnaBridge	161:aa5281ff4a02	1233	* @{
AnnaBridge	161:aa5281ff4a02	1234	*/
AnnaBridge	161:aa5281ff4a02	1235	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1236	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
AnnaBridge	161:aa5281ff4a02	1237	/**
AnnaBridge	161:aa5281ff4a02	1238	* @}
AnnaBridge	161:aa5281ff4a02	1239	*/
AnnaBridge	161:aa5281ff4a02	1240
AnnaBridge	161:aa5281ff4a02	1241	/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
AnnaBridge	161:aa5281ff4a02	1242	* @{
AnnaBridge	161:aa5281ff4a02	1243	*/
AnnaBridge	161:aa5281ff4a02	1244	#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
AnnaBridge	161:aa5281ff4a02	1245	#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1246	/**
AnnaBridge	161:aa5281ff4a02	1247	* @}
AnnaBridge	161:aa5281ff4a02	1248	*/
AnnaBridge	161:aa5281ff4a02	1249
AnnaBridge	161:aa5281ff4a02	1250	/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
AnnaBridge	161:aa5281ff4a02	1251	* @{
AnnaBridge	161:aa5281ff4a02	1252	*/
AnnaBridge	161:aa5281ff4a02	1253	#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1254	#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
AnnaBridge	161:aa5281ff4a02	1255	/**
AnnaBridge	161:aa5281ff4a02	1256	* @}
AnnaBridge	161:aa5281ff4a02	1257	*/
AnnaBridge	161:aa5281ff4a02	1258
AnnaBridge	161:aa5281ff4a02	1259	/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
AnnaBridge	161:aa5281ff4a02	1260	* @{
AnnaBridge	161:aa5281ff4a02	1261	*/
AnnaBridge	161:aa5281ff4a02	1262	#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
AnnaBridge	161:aa5281ff4a02	1263	#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1264	/**
AnnaBridge	161:aa5281ff4a02	1265	* @}
AnnaBridge	161:aa5281ff4a02	1266	*/
AnnaBridge	161:aa5281ff4a02	1267
AnnaBridge	161:aa5281ff4a02	1268	/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
AnnaBridge	161:aa5281ff4a02	1269	* @{
AnnaBridge	161:aa5281ff4a02	1270	*/
AnnaBridge	161:aa5281ff4a02	1271	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
AnnaBridge	161:aa5281ff4a02	1272	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
AnnaBridge	161:aa5281ff4a02	1273	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
AnnaBridge	161:aa5281ff4a02	1274	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
AnnaBridge	161:aa5281ff4a02	1275	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
AnnaBridge	161:aa5281ff4a02	1276	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
AnnaBridge	161:aa5281ff4a02	1277	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
AnnaBridge	161:aa5281ff4a02	1278	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
AnnaBridge	161:aa5281ff4a02	1279	/**
AnnaBridge	161:aa5281ff4a02	1280	* @}
AnnaBridge	161:aa5281ff4a02	1281	*/
AnnaBridge	161:aa5281ff4a02	1282
AnnaBridge	161:aa5281ff4a02	1283	/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
AnnaBridge	161:aa5281ff4a02	1284	* @{
AnnaBridge	161:aa5281ff4a02	1285	*/
AnnaBridge	161:aa5281ff4a02	1286	#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
AnnaBridge	161:aa5281ff4a02	1287	#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1288	/**
AnnaBridge	161:aa5281ff4a02	1289	* @}
AnnaBridge	161:aa5281ff4a02	1290	*/
AnnaBridge	161:aa5281ff4a02	1291
AnnaBridge	161:aa5281ff4a02	1292	/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
AnnaBridge	161:aa5281ff4a02	1293	* @{
AnnaBridge	161:aa5281ff4a02	1294	*/
AnnaBridge	161:aa5281ff4a02	1295	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
AnnaBridge	161:aa5281ff4a02	1296	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1297	/**
AnnaBridge	161:aa5281ff4a02	1298	* @}
AnnaBridge	161:aa5281ff4a02	1299	*/
AnnaBridge	161:aa5281ff4a02	1300
AnnaBridge	161:aa5281ff4a02	1301	/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
AnnaBridge	161:aa5281ff4a02	1302	* @{
AnnaBridge	161:aa5281ff4a02	1303	*/
AnnaBridge	161:aa5281ff4a02	1304	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /!< threshold level of the MTL Receive FIFO is 64 Bytes /
AnnaBridge	161:aa5281ff4a02	1305	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /!< threshold level of the MTL Receive FIFO is 32 Bytes /
AnnaBridge	161:aa5281ff4a02	1306	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /!< threshold level of the MTL Receive FIFO is 96 Bytes /
AnnaBridge	161:aa5281ff4a02	1307	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /!< threshold level of the MTL Receive FIFO is 128 Bytes /
AnnaBridge	161:aa5281ff4a02	1308	/**
AnnaBridge	161:aa5281ff4a02	1309	* @}
AnnaBridge	161:aa5281ff4a02	1310	*/
AnnaBridge	161:aa5281ff4a02	1311
AnnaBridge	161:aa5281ff4a02	1312	/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
AnnaBridge	161:aa5281ff4a02	1313	* @{
AnnaBridge	161:aa5281ff4a02	1314	*/
AnnaBridge	161:aa5281ff4a02	1315	#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
AnnaBridge	161:aa5281ff4a02	1316	#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1317	/**
AnnaBridge	161:aa5281ff4a02	1318	* @}
AnnaBridge	161:aa5281ff4a02	1319	*/
AnnaBridge	161:aa5281ff4a02	1320
AnnaBridge	161:aa5281ff4a02	1321	/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
AnnaBridge	161:aa5281ff4a02	1322	* @{
AnnaBridge	161:aa5281ff4a02	1323	*/
AnnaBridge	161:aa5281ff4a02	1324	#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
AnnaBridge	161:aa5281ff4a02	1325	#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1326	/**
AnnaBridge	161:aa5281ff4a02	1327	* @}
AnnaBridge	161:aa5281ff4a02	1328	*/
AnnaBridge	161:aa5281ff4a02	1329
AnnaBridge	161:aa5281ff4a02	1330	/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
AnnaBridge	161:aa5281ff4a02	1331	* @{
AnnaBridge	161:aa5281ff4a02	1332	*/
AnnaBridge	161:aa5281ff4a02	1333	#define ETH_FIXEDBURST_ENABLE 0x00010000U
AnnaBridge	161:aa5281ff4a02	1334	#define ETH_FIXEDBURST_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1335	/**
AnnaBridge	161:aa5281ff4a02	1336	* @}
AnnaBridge	161:aa5281ff4a02	1337	*/
AnnaBridge	161:aa5281ff4a02	1338
AnnaBridge	161:aa5281ff4a02	1339	/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
AnnaBridge	161:aa5281ff4a02	1340	* @{
AnnaBridge	161:aa5281ff4a02	1341	*/
AnnaBridge	161:aa5281ff4a02	1342	#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
AnnaBridge	161:aa5281ff4a02	1343	#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
AnnaBridge	161:aa5281ff4a02	1344	#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
AnnaBridge	161:aa5281ff4a02	1345	#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
AnnaBridge	161:aa5281ff4a02	1346	#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
AnnaBridge	161:aa5281ff4a02	1347	#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
AnnaBridge	161:aa5281ff4a02	1348	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
AnnaBridge	161:aa5281ff4a02	1349	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
AnnaBridge	161:aa5281ff4a02	1350	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
AnnaBridge	161:aa5281ff4a02	1351	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
AnnaBridge	161:aa5281ff4a02	1352	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
AnnaBridge	161:aa5281ff4a02	1353	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
AnnaBridge	161:aa5281ff4a02	1354	/**
AnnaBridge	161:aa5281ff4a02	1355	* @}
AnnaBridge	161:aa5281ff4a02	1356	*/
AnnaBridge	161:aa5281ff4a02	1357
AnnaBridge	161:aa5281ff4a02	1358	/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
AnnaBridge	161:aa5281ff4a02	1359	* @{
AnnaBridge	161:aa5281ff4a02	1360	*/
AnnaBridge	161:aa5281ff4a02	1361	#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
AnnaBridge	161:aa5281ff4a02	1362	#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
AnnaBridge	161:aa5281ff4a02	1363	#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
AnnaBridge	161:aa5281ff4a02	1364	#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
AnnaBridge	161:aa5281ff4a02	1365	#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
AnnaBridge	161:aa5281ff4a02	1366	#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
AnnaBridge	161:aa5281ff4a02	1367	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
AnnaBridge	161:aa5281ff4a02	1368	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
AnnaBridge	161:aa5281ff4a02	1369	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
AnnaBridge	161:aa5281ff4a02	1370	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
AnnaBridge	161:aa5281ff4a02	1371	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
AnnaBridge	161:aa5281ff4a02	1372	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
AnnaBridge	161:aa5281ff4a02	1373	/**
AnnaBridge	161:aa5281ff4a02	1374	* @}
AnnaBridge	161:aa5281ff4a02	1375	*/
AnnaBridge	161:aa5281ff4a02	1376
AnnaBridge	161:aa5281ff4a02	1377	/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
AnnaBridge	161:aa5281ff4a02	1378	* @{
AnnaBridge	161:aa5281ff4a02	1379	*/
AnnaBridge	161:aa5281ff4a02	1380	#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U
AnnaBridge	161:aa5281ff4a02	1381	#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	1382	/**
AnnaBridge	161:aa5281ff4a02	1383	* @}
AnnaBridge	161:aa5281ff4a02	1384	*/
AnnaBridge	161:aa5281ff4a02	1385
AnnaBridge	161:aa5281ff4a02	1386	/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
AnnaBridge	161:aa5281ff4a02	1387	* @{
AnnaBridge	161:aa5281ff4a02	1388	*/
AnnaBridge	161:aa5281ff4a02	1389	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
AnnaBridge	161:aa5281ff4a02	1390	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
AnnaBridge	161:aa5281ff4a02	1391	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
AnnaBridge	161:aa5281ff4a02	1392	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
AnnaBridge	161:aa5281ff4a02	1393	#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
AnnaBridge	161:aa5281ff4a02	1394	/**
AnnaBridge	161:aa5281ff4a02	1395	* @}
AnnaBridge	161:aa5281ff4a02	1396	*/
AnnaBridge	161:aa5281ff4a02	1397
AnnaBridge	161:aa5281ff4a02	1398	/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
AnnaBridge	161:aa5281ff4a02	1399	* @{
AnnaBridge	161:aa5281ff4a02	1400	*/
AnnaBridge	161:aa5281ff4a02	1401	#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /!< Last Segment /
AnnaBridge	161:aa5281ff4a02	1402	#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /!< First Segment /
AnnaBridge	161:aa5281ff4a02	1403	/**
AnnaBridge	161:aa5281ff4a02	1404	* @}
AnnaBridge	161:aa5281ff4a02	1405	*/
AnnaBridge	161:aa5281ff4a02	1406
AnnaBridge	161:aa5281ff4a02	1407	/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
AnnaBridge	161:aa5281ff4a02	1408	* @{
AnnaBridge	161:aa5281ff4a02	1409	*/
AnnaBridge	161:aa5281ff4a02	1410	#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /!< Checksum engine bypass /
AnnaBridge	161:aa5281ff4a02	1411	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /!< IPv4 header checksum insertion /
AnnaBridge	161:aa5281ff4a02	1412	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
AnnaBridge	161:aa5281ff4a02	1413	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
AnnaBridge	161:aa5281ff4a02	1414	/**
AnnaBridge	161:aa5281ff4a02	1415	* @}
AnnaBridge	161:aa5281ff4a02	1416	*/
AnnaBridge	161:aa5281ff4a02	1417
AnnaBridge	161:aa5281ff4a02	1418	/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
AnnaBridge	161:aa5281ff4a02	1419	* @{
AnnaBridge	161:aa5281ff4a02	1420	*/
AnnaBridge	161:aa5281ff4a02	1421	#define ETH_DMARXDESC_BUFFER1 0x00000000U /!< DMA Rx Desc Buffer1 /
AnnaBridge	161:aa5281ff4a02	1422	#define ETH_DMARXDESC_BUFFER2 0x00000001U /!< DMA Rx Desc Buffer2 /
AnnaBridge	161:aa5281ff4a02	1423	/**
AnnaBridge	161:aa5281ff4a02	1424	* @}
AnnaBridge	161:aa5281ff4a02	1425	*/
AnnaBridge	161:aa5281ff4a02	1426
AnnaBridge	161:aa5281ff4a02	1427	/** @defgroup ETH_PMT_Flags ETH PMT Flags
AnnaBridge	161:aa5281ff4a02	1428	* @{
AnnaBridge	161:aa5281ff4a02	1429	*/
AnnaBridge	161:aa5281ff4a02	1430	#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /!< Wake-Up Frame Filter Register Pointer Reset /
AnnaBridge	161:aa5281ff4a02	1431	#define ETH_PMT_FLAG_WUFR 0x00000040U /!< Wake-Up Frame Received /
AnnaBridge	161:aa5281ff4a02	1432	#define ETH_PMT_FLAG_MPR 0x00000020U /!< Magic Packet Received /
AnnaBridge	161:aa5281ff4a02	1433	/**
AnnaBridge	161:aa5281ff4a02	1434	* @}
AnnaBridge	161:aa5281ff4a02	1435	*/
AnnaBridge	161:aa5281ff4a02	1436
AnnaBridge	161:aa5281ff4a02	1437	/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
AnnaBridge	161:aa5281ff4a02	1438	* @{
AnnaBridge	161:aa5281ff4a02	1439	*/
AnnaBridge	161:aa5281ff4a02	1440	#define ETH_MMC_IT_TGF 0x00200000U /!< When Tx good frame counter reaches half the maximum value /
AnnaBridge	161:aa5281ff4a02	1441	#define ETH_MMC_IT_TGFMSC 0x00008000U /!< When Tx good multi col counter reaches half the maximum value /
AnnaBridge	161:aa5281ff4a02	1442	#define ETH_MMC_IT_TGFSC 0x00004000U /!< When Tx good single col counter reaches half the maximum value /
AnnaBridge	161:aa5281ff4a02	1443	/**
AnnaBridge	161:aa5281ff4a02	1444	* @}
AnnaBridge	161:aa5281ff4a02	1445	*/
AnnaBridge	161:aa5281ff4a02	1446
AnnaBridge	161:aa5281ff4a02	1447	/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
AnnaBridge	161:aa5281ff4a02	1448	* @{
AnnaBridge	161:aa5281ff4a02	1449	*/
AnnaBridge	161:aa5281ff4a02	1450	#define ETH_MMC_IT_RGUF 0x10020000U /!< When Rx good unicast frames counter reaches half the maximum value /
AnnaBridge	161:aa5281ff4a02	1451	#define ETH_MMC_IT_RFAE 0x10000040U /!< When Rx alignment error counter reaches half the maximum value /
AnnaBridge	161:aa5281ff4a02	1452	#define ETH_MMC_IT_RFCE 0x10000020U /!< When Rx crc error counter reaches half the maximum value /
AnnaBridge	161:aa5281ff4a02	1453	/**
AnnaBridge	161:aa5281ff4a02	1454	* @}
AnnaBridge	161:aa5281ff4a02	1455	*/
AnnaBridge	161:aa5281ff4a02	1456
AnnaBridge	161:aa5281ff4a02	1457	/** @defgroup ETH_MAC_Flags ETH MAC Flags
AnnaBridge	161:aa5281ff4a02	1458	* @{
AnnaBridge	161:aa5281ff4a02	1459	*/
AnnaBridge	161:aa5281ff4a02	1460	#define ETH_MAC_FLAG_TST 0x00000200U /!< Time stamp trigger flag (on MAC) /
AnnaBridge	161:aa5281ff4a02	1461	#define ETH_MAC_FLAG_MMCT 0x00000040U /!< MMC transmit flag /
AnnaBridge	161:aa5281ff4a02	1462	#define ETH_MAC_FLAG_MMCR 0x00000020U /!< MMC receive flag /
AnnaBridge	161:aa5281ff4a02	1463	#define ETH_MAC_FLAG_MMC 0x00000010U /!< MMC flag (on MAC) /
AnnaBridge	161:aa5281ff4a02	1464	#define ETH_MAC_FLAG_PMT 0x00000008U /!< PMT flag (on MAC) /
AnnaBridge	161:aa5281ff4a02	1465	/**
AnnaBridge	161:aa5281ff4a02	1466	* @}
AnnaBridge	161:aa5281ff4a02	1467	*/
AnnaBridge	161:aa5281ff4a02	1468
AnnaBridge	161:aa5281ff4a02	1469	/** @defgroup ETH_DMA_Flags ETH DMA Flags
AnnaBridge	161:aa5281ff4a02	1470	* @{
AnnaBridge	161:aa5281ff4a02	1471	*/
AnnaBridge	161:aa5281ff4a02	1472	#define ETH_DMA_FLAG_TST 0x20000000U /!< Time-stamp trigger interrupt (on DMA) /
AnnaBridge	161:aa5281ff4a02	1473	#define ETH_DMA_FLAG_PMT 0x10000000U /!< PMT interrupt (on DMA) /
AnnaBridge	161:aa5281ff4a02	1474	#define ETH_DMA_FLAG_MMC 0x08000000U /!< MMC interrupt (on DMA) /
AnnaBridge	161:aa5281ff4a02	1475	#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /!< Error bits 0-Rx DMA, 1-Tx DMA /
AnnaBridge	161:aa5281ff4a02	1476	#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /!< Error bits 0-write transfer, 1-read transfer /
AnnaBridge	161:aa5281ff4a02	1477	#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /!< Error bits 0-data buffer, 1-desc. access /
AnnaBridge	161:aa5281ff4a02	1478	#define ETH_DMA_FLAG_NIS 0x00010000U /!< Normal interrupt summary flag /
AnnaBridge	161:aa5281ff4a02	1479	#define ETH_DMA_FLAG_AIS 0x00008000U /!< Abnormal interrupt summary flag /
AnnaBridge	161:aa5281ff4a02	1480	#define ETH_DMA_FLAG_ER 0x00004000U /!< Early receive flag /
AnnaBridge	161:aa5281ff4a02	1481	#define ETH_DMA_FLAG_FBE 0x00002000U /!< Fatal bus error flag /
AnnaBridge	161:aa5281ff4a02	1482	#define ETH_DMA_FLAG_ET 0x00000400U /!< Early transmit flag /
AnnaBridge	161:aa5281ff4a02	1483	#define ETH_DMA_FLAG_RWT 0x00000200U /!< Receive watchdog timeout flag /
AnnaBridge	161:aa5281ff4a02	1484	#define ETH_DMA_FLAG_RPS 0x00000100U /!< Receive process stopped flag /
AnnaBridge	161:aa5281ff4a02	1485	#define ETH_DMA_FLAG_RBU 0x00000080U /!< Receive buffer unavailable flag /
AnnaBridge	161:aa5281ff4a02	1486	#define ETH_DMA_FLAG_R 0x00000040U /!< Receive flag /
AnnaBridge	161:aa5281ff4a02	1487	#define ETH_DMA_FLAG_TU 0x00000020U /!< Underflow flag /
AnnaBridge	161:aa5281ff4a02	1488	#define ETH_DMA_FLAG_RO 0x00000010U /!< Overflow flag /
AnnaBridge	161:aa5281ff4a02	1489	#define ETH_DMA_FLAG_TJT 0x00000008U /!< Transmit jabber timeout flag /
AnnaBridge	161:aa5281ff4a02	1490	#define ETH_DMA_FLAG_TBU 0x00000004U /!< Transmit buffer unavailable flag /
AnnaBridge	161:aa5281ff4a02	1491	#define ETH_DMA_FLAG_TPS 0x00000002U /!< Transmit process stopped flag /
AnnaBridge	161:aa5281ff4a02	1492	#define ETH_DMA_FLAG_T 0x00000001U /!< Transmit flag /
AnnaBridge	161:aa5281ff4a02	1493	/**
AnnaBridge	161:aa5281ff4a02	1494	* @}
AnnaBridge	161:aa5281ff4a02	1495	*/
AnnaBridge	161:aa5281ff4a02	1496
AnnaBridge	161:aa5281ff4a02	1497	/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
AnnaBridge	161:aa5281ff4a02	1498	* @{
AnnaBridge	161:aa5281ff4a02	1499	*/
AnnaBridge	161:aa5281ff4a02	1500	#define ETH_MAC_IT_TST 0x00000200U /!< Time stamp trigger interrupt (on MAC) /
AnnaBridge	161:aa5281ff4a02	1501	#define ETH_MAC_IT_MMCT 0x00000040U /!< MMC transmit interrupt /
AnnaBridge	161:aa5281ff4a02	1502	#define ETH_MAC_IT_MMCR 0x00000020U /!< MMC receive interrupt /
AnnaBridge	161:aa5281ff4a02	1503	#define ETH_MAC_IT_MMC 0x00000010U /!< MMC interrupt (on MAC) /
AnnaBridge	161:aa5281ff4a02	1504	#define ETH_MAC_IT_PMT 0x00000008U /!< PMT interrupt (on MAC) /
AnnaBridge	161:aa5281ff4a02	1505	/**
AnnaBridge	161:aa5281ff4a02	1506	* @}
AnnaBridge	161:aa5281ff4a02	1507	*/
AnnaBridge	161:aa5281ff4a02	1508
AnnaBridge	161:aa5281ff4a02	1509	/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
AnnaBridge	161:aa5281ff4a02	1510	* @{
AnnaBridge	161:aa5281ff4a02	1511	*/
AnnaBridge	161:aa5281ff4a02	1512	#define ETH_DMA_IT_TST 0x20000000U /!< Time-stamp trigger interrupt (on DMA) /
AnnaBridge	161:aa5281ff4a02	1513	#define ETH_DMA_IT_PMT 0x10000000U /!< PMT interrupt (on DMA) /
AnnaBridge	161:aa5281ff4a02	1514	#define ETH_DMA_IT_MMC 0x08000000U /!< MMC interrupt (on DMA) /
AnnaBridge	161:aa5281ff4a02	1515	#define ETH_DMA_IT_NIS 0x00010000U /!< Normal interrupt summary /
AnnaBridge	161:aa5281ff4a02	1516	#define ETH_DMA_IT_AIS 0x00008000U /!< Abnormal interrupt summary /
AnnaBridge	161:aa5281ff4a02	1517	#define ETH_DMA_IT_ER 0x00004000U /!< Early receive interrupt /
AnnaBridge	161:aa5281ff4a02	1518	#define ETH_DMA_IT_FBE 0x00002000U /!< Fatal bus error interrupt /
AnnaBridge	161:aa5281ff4a02	1519	#define ETH_DMA_IT_ET 0x00000400U /!< Early transmit interrupt /
AnnaBridge	161:aa5281ff4a02	1520	#define ETH_DMA_IT_RWT 0x00000200U /!< Receive watchdog timeout interrupt /
AnnaBridge	161:aa5281ff4a02	1521	#define ETH_DMA_IT_RPS 0x00000100U /!< Receive process stopped interrupt /
AnnaBridge	161:aa5281ff4a02	1522	#define ETH_DMA_IT_RBU 0x00000080U /!< Receive buffer unavailable interrupt /
AnnaBridge	161:aa5281ff4a02	1523	#define ETH_DMA_IT_R 0x00000040U /!< Receive interrupt /
AnnaBridge	161:aa5281ff4a02	1524	#define ETH_DMA_IT_TU 0x00000020U /!< Underflow interrupt /
AnnaBridge	161:aa5281ff4a02	1525	#define ETH_DMA_IT_RO 0x00000010U /!< Overflow interrupt /
AnnaBridge	161:aa5281ff4a02	1526	#define ETH_DMA_IT_TJT 0x00000008U /!< Transmit jabber timeout interrupt /
AnnaBridge	161:aa5281ff4a02	1527	#define ETH_DMA_IT_TBU 0x00000004U /!< Transmit buffer unavailable interrupt /
AnnaBridge	161:aa5281ff4a02	1528	#define ETH_DMA_IT_TPS 0x00000002U /!< Transmit process stopped interrupt /
AnnaBridge	161:aa5281ff4a02	1529	#define ETH_DMA_IT_T 0x00000001U /!< Transmit interrupt /
AnnaBridge	161:aa5281ff4a02	1530	/**
AnnaBridge	161:aa5281ff4a02	1531	* @}
AnnaBridge	161:aa5281ff4a02	1532	*/
AnnaBridge	161:aa5281ff4a02	1533
AnnaBridge	161:aa5281ff4a02	1534	/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
AnnaBridge	161:aa5281ff4a02	1535	* @{
AnnaBridge	161:aa5281ff4a02	1536	*/
AnnaBridge	161:aa5281ff4a02	1537	#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /!< Stopped - Reset or Stop Tx Command issued /
AnnaBridge	161:aa5281ff4a02	1538	#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /!< Running - fetching the Tx descriptor /
AnnaBridge	161:aa5281ff4a02	1539	#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /!< Running - waiting for status /
AnnaBridge	161:aa5281ff4a02	1540	#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /!< Running - reading the data from host memory /
AnnaBridge	161:aa5281ff4a02	1541	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /!< Suspended - Tx Descriptor unavailable /
AnnaBridge	161:aa5281ff4a02	1542	#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /!< Running - closing Rx descriptor /
AnnaBridge	161:aa5281ff4a02	1543
AnnaBridge	161:aa5281ff4a02	1544	/**
AnnaBridge	161:aa5281ff4a02	1545	* @}
AnnaBridge	161:aa5281ff4a02	1546	*/
AnnaBridge	161:aa5281ff4a02	1547
AnnaBridge	161:aa5281ff4a02	1548
AnnaBridge	161:aa5281ff4a02	1549	/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
AnnaBridge	161:aa5281ff4a02	1550	* @{
AnnaBridge	161:aa5281ff4a02	1551	*/
AnnaBridge	161:aa5281ff4a02	1552	#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /!< Stopped - Reset or Stop Rx Command issued /
AnnaBridge	161:aa5281ff4a02	1553	#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /!< Running - fetching the Rx descriptor /
AnnaBridge	161:aa5281ff4a02	1554	#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /!< Running - waiting for packet /
AnnaBridge	161:aa5281ff4a02	1555	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /!< Suspended - Rx Descriptor unavailable /
AnnaBridge	161:aa5281ff4a02	1556	#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /!< Running - closing descriptor /
AnnaBridge	161:aa5281ff4a02	1557	#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /!< Running - queuing the receive frame into host memory /
AnnaBridge	161:aa5281ff4a02	1558
AnnaBridge	161:aa5281ff4a02	1559	/**
AnnaBridge	161:aa5281ff4a02	1560	* @}
AnnaBridge	161:aa5281ff4a02	1561	*/
AnnaBridge	161:aa5281ff4a02	1562
AnnaBridge	161:aa5281ff4a02	1563	/** @defgroup ETH_DMA_overflow ETH DMA overflow
AnnaBridge	161:aa5281ff4a02	1564	* @{
AnnaBridge	161:aa5281ff4a02	1565	*/
AnnaBridge	161:aa5281ff4a02	1566	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /!< Overflow bit for FIFO overflow counter /
AnnaBridge	161:aa5281ff4a02	1567	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /!< Overflow bit for missed frame counter /
AnnaBridge	161:aa5281ff4a02	1568	/**
AnnaBridge	161:aa5281ff4a02	1569	* @}
AnnaBridge	161:aa5281ff4a02	1570	*/
AnnaBridge	161:aa5281ff4a02	1571
AnnaBridge	161:aa5281ff4a02	1572	/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
AnnaBridge	161:aa5281ff4a02	1573	* @{
AnnaBridge	161:aa5281ff4a02	1574	*/
AnnaBridge	161:aa5281ff4a02	1575	#define ETH_EXTI_LINE_WAKEUP 0x00080000U /!< External interrupt line 19 Connected to the ETH EXTI Line /
AnnaBridge	161:aa5281ff4a02	1576
AnnaBridge	161:aa5281ff4a02	1577	/**
AnnaBridge	161:aa5281ff4a02	1578	* @}
AnnaBridge	161:aa5281ff4a02	1579	*/
AnnaBridge	161:aa5281ff4a02	1580
AnnaBridge	161:aa5281ff4a02	1581	/**
AnnaBridge	161:aa5281ff4a02	1582	* @}
AnnaBridge	161:aa5281ff4a02	1583	*/
AnnaBridge	161:aa5281ff4a02	1584
AnnaBridge	161:aa5281ff4a02	1585	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	1586	/** @defgroup ETH_Exported_Macros ETH Exported Macros
AnnaBridge	161:aa5281ff4a02	1587	* @brief macros to handle interrupts and specific clock configurations
AnnaBridge	161:aa5281ff4a02	1588	* @{
AnnaBridge	161:aa5281ff4a02	1589	*/
AnnaBridge	161:aa5281ff4a02	1590
AnnaBridge	161:aa5281ff4a02	1591	/** @brief Reset ETH handle state
AnnaBridge	161:aa5281ff4a02	1592	* @param __HANDLE__: specifies the ETH handle.
AnnaBridge	161:aa5281ff4a02	1593	* @retval None
AnnaBridge	161:aa5281ff4a02	1594	*/
AnnaBridge	161:aa5281ff4a02	1595	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
AnnaBridge	161:aa5281ff4a02	1596
AnnaBridge	161:aa5281ff4a02	1597	/**
AnnaBridge	161:aa5281ff4a02	1598	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
AnnaBridge	161:aa5281ff4a02	1599	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1600	* @param __FLAG__: specifies the flag of TDES0 to check.
AnnaBridge	161:aa5281ff4a02	1601	* @retval the ETH_DMATxDescFlag (SET or RESET).
AnnaBridge	161:aa5281ff4a02	1602	*/
AnnaBridge	161:aa5281ff4a02	1603	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
AnnaBridge	161:aa5281ff4a02	1604
AnnaBridge	161:aa5281ff4a02	1605	/**
AnnaBridge	161:aa5281ff4a02	1606	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
AnnaBridge	161:aa5281ff4a02	1607	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1608	* @param __FLAG__: specifies the flag of RDES0 to check.
AnnaBridge	161:aa5281ff4a02	1609	* @retval the ETH_DMATxDescFlag (SET or RESET).
AnnaBridge	161:aa5281ff4a02	1610	*/
AnnaBridge	161:aa5281ff4a02	1611	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
AnnaBridge	161:aa5281ff4a02	1612
AnnaBridge	161:aa5281ff4a02	1613	/**
AnnaBridge	161:aa5281ff4a02	1614	* @brief Enables the specified DMA Rx Desc receive interrupt.
AnnaBridge	161:aa5281ff4a02	1615	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1616	* @retval None
AnnaBridge	161:aa5281ff4a02	1617	*/
AnnaBridge	161:aa5281ff4a02	1618	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
AnnaBridge	161:aa5281ff4a02	1619
AnnaBridge	161:aa5281ff4a02	1620	/**
AnnaBridge	161:aa5281ff4a02	1621	* @brief Disables the specified DMA Rx Desc receive interrupt.
AnnaBridge	161:aa5281ff4a02	1622	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1623	* @retval None
AnnaBridge	161:aa5281ff4a02	1624	*/
AnnaBridge	161:aa5281ff4a02	1625	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
AnnaBridge	161:aa5281ff4a02	1626
AnnaBridge	161:aa5281ff4a02	1627	/**
AnnaBridge	161:aa5281ff4a02	1628	* @brief Set the specified DMA Rx Desc Own bit.
AnnaBridge	161:aa5281ff4a02	1629	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1630	* @retval None
AnnaBridge	161:aa5281ff4a02	1631	*/
AnnaBridge	161:aa5281ff4a02	1632	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
AnnaBridge	161:aa5281ff4a02	1633
AnnaBridge	161:aa5281ff4a02	1634	/**
AnnaBridge	161:aa5281ff4a02	1635	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
AnnaBridge	161:aa5281ff4a02	1636	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1637	* @retval The Transmit descriptor collision counter value.
AnnaBridge	161:aa5281ff4a02	1638	*/
AnnaBridge	161:aa5281ff4a02	1639	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
AnnaBridge	161:aa5281ff4a02	1640
AnnaBridge	161:aa5281ff4a02	1641	/**
AnnaBridge	161:aa5281ff4a02	1642	* @brief Set the specified DMA Tx Desc Own bit.
AnnaBridge	161:aa5281ff4a02	1643	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1644	* @retval None
AnnaBridge	161:aa5281ff4a02	1645	*/
AnnaBridge	161:aa5281ff4a02	1646	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
AnnaBridge	161:aa5281ff4a02	1647
AnnaBridge	161:aa5281ff4a02	1648	/**
AnnaBridge	161:aa5281ff4a02	1649	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
AnnaBridge	161:aa5281ff4a02	1650	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1651	* @retval None
AnnaBridge	161:aa5281ff4a02	1652	*/
AnnaBridge	161:aa5281ff4a02	1653	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
AnnaBridge	161:aa5281ff4a02	1654
AnnaBridge	161:aa5281ff4a02	1655	/**
AnnaBridge	161:aa5281ff4a02	1656	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
AnnaBridge	161:aa5281ff4a02	1657	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1658	* @retval None
AnnaBridge	161:aa5281ff4a02	1659	*/
AnnaBridge	161:aa5281ff4a02	1660	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
AnnaBridge	161:aa5281ff4a02	1661
AnnaBridge	161:aa5281ff4a02	1662	/**
AnnaBridge	161:aa5281ff4a02	1663	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
AnnaBridge	161:aa5281ff4a02	1664	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1665	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
AnnaBridge	161:aa5281ff4a02	1666	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	1667	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
AnnaBridge	161:aa5281ff4a02	1668	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
AnnaBridge	161:aa5281ff4a02	1669	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
AnnaBridge	161:aa5281ff4a02	1670	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
AnnaBridge	161:aa5281ff4a02	1671	* @retval None
AnnaBridge	161:aa5281ff4a02	1672	*/
AnnaBridge	161:aa5281ff4a02	1673	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
AnnaBridge	161:aa5281ff4a02	1674
AnnaBridge	161:aa5281ff4a02	1675	/**
AnnaBridge	161:aa5281ff4a02	1676	* @brief Enables the DMA Tx Desc CRC.
AnnaBridge	161:aa5281ff4a02	1677	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1678	* @retval None
AnnaBridge	161:aa5281ff4a02	1679	*/
AnnaBridge	161:aa5281ff4a02	1680	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
AnnaBridge	161:aa5281ff4a02	1681
AnnaBridge	161:aa5281ff4a02	1682	/**
AnnaBridge	161:aa5281ff4a02	1683	* @brief Disables the DMA Tx Desc CRC.
AnnaBridge	161:aa5281ff4a02	1684	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1685	* @retval None
AnnaBridge	161:aa5281ff4a02	1686	*/
AnnaBridge	161:aa5281ff4a02	1687	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
AnnaBridge	161:aa5281ff4a02	1688
AnnaBridge	161:aa5281ff4a02	1689	/**
AnnaBridge	161:aa5281ff4a02	1690	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
AnnaBridge	161:aa5281ff4a02	1691	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1692	* @retval None
AnnaBridge	161:aa5281ff4a02	1693	*/
AnnaBridge	161:aa5281ff4a02	1694	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
AnnaBridge	161:aa5281ff4a02	1695
AnnaBridge	161:aa5281ff4a02	1696	/**
AnnaBridge	161:aa5281ff4a02	1697	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
AnnaBridge	161:aa5281ff4a02	1698	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1699	* @retval None
AnnaBridge	161:aa5281ff4a02	1700	*/
AnnaBridge	161:aa5281ff4a02	1701	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
AnnaBridge	161:aa5281ff4a02	1702
AnnaBridge	161:aa5281ff4a02	1703	/**
AnnaBridge	161:aa5281ff4a02	1704	* @brief Enables the specified ETHERNET MAC interrupts.
AnnaBridge	161:aa5281ff4a02	1705	* @param __HANDLE__ : ETH Handle
AnnaBridge	161:aa5281ff4a02	1706	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
AnnaBridge	161:aa5281ff4a02	1707	* enabled or disabled.
AnnaBridge	161:aa5281ff4a02	1708	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	1709	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
AnnaBridge	161:aa5281ff4a02	1710	* @arg ETH_MAC_IT_PMT : PMT interrupt
AnnaBridge	161:aa5281ff4a02	1711	* @retval None
AnnaBridge	161:aa5281ff4a02	1712	*/
AnnaBridge	161:aa5281ff4a02	1713	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1714
AnnaBridge	161:aa5281ff4a02	1715	/**
AnnaBridge	161:aa5281ff4a02	1716	* @brief Disables the specified ETHERNET MAC interrupts.
AnnaBridge	161:aa5281ff4a02	1717	* @param __HANDLE__ : ETH Handle
AnnaBridge	161:aa5281ff4a02	1718	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
AnnaBridge	161:aa5281ff4a02	1719	* enabled or disabled.
AnnaBridge	161:aa5281ff4a02	1720	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	1721	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
AnnaBridge	161:aa5281ff4a02	1722	* @arg ETH_MAC_IT_PMT : PMT interrupt
AnnaBridge	161:aa5281ff4a02	1723	* @retval None
AnnaBridge	161:aa5281ff4a02	1724	*/
AnnaBridge	161:aa5281ff4a02	1725	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1726
AnnaBridge	161:aa5281ff4a02	1727	/**
AnnaBridge	161:aa5281ff4a02	1728	* @brief Initiate a Pause Control Frame (Full-duplex only).
AnnaBridge	161:aa5281ff4a02	1729	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1730	* @retval None
AnnaBridge	161:aa5281ff4a02	1731	*/
AnnaBridge	161:aa5281ff4a02	1732	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
AnnaBridge	161:aa5281ff4a02	1733
AnnaBridge	161:aa5281ff4a02	1734	/**
AnnaBridge	161:aa5281ff4a02	1735	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
AnnaBridge	161:aa5281ff4a02	1736	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1737	* @retval The new state of flow control busy status bit (SET or RESET).
AnnaBridge	161:aa5281ff4a02	1738	*/
AnnaBridge	161:aa5281ff4a02	1739	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
AnnaBridge	161:aa5281ff4a02	1740
AnnaBridge	161:aa5281ff4a02	1741	/**
AnnaBridge	161:aa5281ff4a02	1742	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
AnnaBridge	161:aa5281ff4a02	1743	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1744	* @retval None
AnnaBridge	161:aa5281ff4a02	1745	*/
AnnaBridge	161:aa5281ff4a02	1746	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
AnnaBridge	161:aa5281ff4a02	1747
AnnaBridge	161:aa5281ff4a02	1748	/**
AnnaBridge	161:aa5281ff4a02	1749	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
AnnaBridge	161:aa5281ff4a02	1750	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1751	* @retval None
AnnaBridge	161:aa5281ff4a02	1752	*/
AnnaBridge	161:aa5281ff4a02	1753	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
AnnaBridge	161:aa5281ff4a02	1754
AnnaBridge	161:aa5281ff4a02	1755	/**
AnnaBridge	161:aa5281ff4a02	1756	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
AnnaBridge	161:aa5281ff4a02	1757	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1758	* @param __FLAG__: specifies the flag to check.
AnnaBridge	161:aa5281ff4a02	1759	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	1760	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
AnnaBridge	161:aa5281ff4a02	1761	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
AnnaBridge	161:aa5281ff4a02	1762	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
AnnaBridge	161:aa5281ff4a02	1763	* @arg ETH_MAC_FLAG_MMC : MMC flag
AnnaBridge	161:aa5281ff4a02	1764	* @arg ETH_MAC_FLAG_PMT : PMT flag
AnnaBridge	161:aa5281ff4a02	1765	* @retval The state of ETHERNET MAC flag.
AnnaBridge	161:aa5281ff4a02	1766	*/
AnnaBridge	161:aa5281ff4a02	1767	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
AnnaBridge	161:aa5281ff4a02	1768
AnnaBridge	161:aa5281ff4a02	1769	/**
AnnaBridge	161:aa5281ff4a02	1770	* @brief Enables the specified ETHERNET DMA interrupts.
AnnaBridge	161:aa5281ff4a02	1771	* @param __HANDLE__ : ETH Handle
AnnaBridge	161:aa5281ff4a02	1772	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
AnnaBridge	161:aa5281ff4a02	1773	* enabled @ref ETH_DMA_Interrupts
AnnaBridge	161:aa5281ff4a02	1774	* @retval None
AnnaBridge	161:aa5281ff4a02	1775	*/
AnnaBridge	161:aa5281ff4a02	1776	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1777
AnnaBridge	161:aa5281ff4a02	1778	/**
AnnaBridge	161:aa5281ff4a02	1779	* @brief Disables the specified ETHERNET DMA interrupts.
AnnaBridge	161:aa5281ff4a02	1780	* @param __HANDLE__ : ETH Handle
AnnaBridge	161:aa5281ff4a02	1781	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
AnnaBridge	161:aa5281ff4a02	1782	* disabled. @ref ETH_DMA_Interrupts
AnnaBridge	161:aa5281ff4a02	1783	* @retval None
AnnaBridge	161:aa5281ff4a02	1784	*/
AnnaBridge	161:aa5281ff4a02	1785	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1786
AnnaBridge	161:aa5281ff4a02	1787	/**
AnnaBridge	161:aa5281ff4a02	1788	* @brief Clears the ETHERNET DMA IT pending bit.
AnnaBridge	161:aa5281ff4a02	1789	* @param __HANDLE__ : ETH Handle
AnnaBridge	161:aa5281ff4a02	1790	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
AnnaBridge	161:aa5281ff4a02	1791	* @retval None
AnnaBridge	161:aa5281ff4a02	1792	*/
AnnaBridge	161:aa5281ff4a02	1793	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1794
AnnaBridge	161:aa5281ff4a02	1795	/**
AnnaBridge	161:aa5281ff4a02	1796	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
AnnaBridge	161:aa5281ff4a02	1797	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1798	* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
AnnaBridge	161:aa5281ff4a02	1799	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
AnnaBridge	161:aa5281ff4a02	1800	*/
AnnaBridge	161:aa5281ff4a02	1801	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
AnnaBridge	161:aa5281ff4a02	1802
AnnaBridge	161:aa5281ff4a02	1803	/**
AnnaBridge	161:aa5281ff4a02	1804	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
AnnaBridge	161:aa5281ff4a02	1805	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1806	* @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
AnnaBridge	161:aa5281ff4a02	1807	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
AnnaBridge	161:aa5281ff4a02	1808	*/
AnnaBridge	161:aa5281ff4a02	1809	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
AnnaBridge	161:aa5281ff4a02	1810
AnnaBridge	161:aa5281ff4a02	1811	/**
AnnaBridge	161:aa5281ff4a02	1812	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
AnnaBridge	161:aa5281ff4a02	1813	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1814	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
AnnaBridge	161:aa5281ff4a02	1815	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	1816	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
AnnaBridge	161:aa5281ff4a02	1817	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
AnnaBridge	161:aa5281ff4a02	1818	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
AnnaBridge	161:aa5281ff4a02	1819	*/
AnnaBridge	161:aa5281ff4a02	1820	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
AnnaBridge	161:aa5281ff4a02	1821
AnnaBridge	161:aa5281ff4a02	1822	/**
AnnaBridge	161:aa5281ff4a02	1823	* @brief Set the DMA Receive status watchdog timer register value
AnnaBridge	161:aa5281ff4a02	1824	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1825	* @param __VALUE__: DMA Receive status watchdog timer register value
AnnaBridge	161:aa5281ff4a02	1826	* @retval None
AnnaBridge	161:aa5281ff4a02	1827	*/
AnnaBridge	161:aa5281ff4a02	1828	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
AnnaBridge	161:aa5281ff4a02	1829
AnnaBridge	161:aa5281ff4a02	1830	/**
AnnaBridge	161:aa5281ff4a02	1831	* @brief Enables any unicast packet filtered by the MAC address
AnnaBridge	161:aa5281ff4a02	1832	* recognition to be a wake-up frame.
AnnaBridge	161:aa5281ff4a02	1833	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1834	* @retval None
AnnaBridge	161:aa5281ff4a02	1835	*/
AnnaBridge	161:aa5281ff4a02	1836	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
AnnaBridge	161:aa5281ff4a02	1837
AnnaBridge	161:aa5281ff4a02	1838	/**
AnnaBridge	161:aa5281ff4a02	1839	* @brief Disables any unicast packet filtered by the MAC address
AnnaBridge	161:aa5281ff4a02	1840	* recognition to be a wake-up frame.
AnnaBridge	161:aa5281ff4a02	1841	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1842	* @retval None
AnnaBridge	161:aa5281ff4a02	1843	*/
AnnaBridge	161:aa5281ff4a02	1844	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
AnnaBridge	161:aa5281ff4a02	1845
AnnaBridge	161:aa5281ff4a02	1846	/**
AnnaBridge	161:aa5281ff4a02	1847	* @brief Enables the MAC Wake-Up Frame Detection.
AnnaBridge	161:aa5281ff4a02	1848	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1849	* @retval None
AnnaBridge	161:aa5281ff4a02	1850	*/
AnnaBridge	161:aa5281ff4a02	1851	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
AnnaBridge	161:aa5281ff4a02	1852
AnnaBridge	161:aa5281ff4a02	1853	/**
AnnaBridge	161:aa5281ff4a02	1854	* @brief Disables the MAC Wake-Up Frame Detection.
AnnaBridge	161:aa5281ff4a02	1855	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1856	* @retval None
AnnaBridge	161:aa5281ff4a02	1857	*/
AnnaBridge	161:aa5281ff4a02	1858	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
AnnaBridge	161:aa5281ff4a02	1859
AnnaBridge	161:aa5281ff4a02	1860	/**
AnnaBridge	161:aa5281ff4a02	1861	* @brief Enables the MAC Magic Packet Detection.
AnnaBridge	161:aa5281ff4a02	1862	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1863	* @retval None
AnnaBridge	161:aa5281ff4a02	1864	*/
AnnaBridge	161:aa5281ff4a02	1865	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
AnnaBridge	161:aa5281ff4a02	1866
AnnaBridge	161:aa5281ff4a02	1867	/**
AnnaBridge	161:aa5281ff4a02	1868	* @brief Disables the MAC Magic Packet Detection.
AnnaBridge	161:aa5281ff4a02	1869	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1870	* @retval None
AnnaBridge	161:aa5281ff4a02	1871	*/
AnnaBridge	161:aa5281ff4a02	1872	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
AnnaBridge	161:aa5281ff4a02	1873
AnnaBridge	161:aa5281ff4a02	1874	/**
AnnaBridge	161:aa5281ff4a02	1875	* @brief Enables the MAC Power Down.
AnnaBridge	161:aa5281ff4a02	1876	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1877	* @retval None
AnnaBridge	161:aa5281ff4a02	1878	*/
AnnaBridge	161:aa5281ff4a02	1879	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
AnnaBridge	161:aa5281ff4a02	1880
AnnaBridge	161:aa5281ff4a02	1881	/**
AnnaBridge	161:aa5281ff4a02	1882	* @brief Disables the MAC Power Down.
AnnaBridge	161:aa5281ff4a02	1883	* @param __HANDLE__: ETH Handle
AnnaBridge	161:aa5281ff4a02	1884	* @retval None
AnnaBridge	161:aa5281ff4a02	1885	*/
AnnaBridge	161:aa5281ff4a02	1886	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
AnnaBridge	161:aa5281ff4a02	1887
AnnaBridge	161:aa5281ff4a02	1888	/**
AnnaBridge	161:aa5281ff4a02	1889	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
AnnaBridge	161:aa5281ff4a02	1890	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1891	* @param __FLAG__: specifies the flag to check.
AnnaBridge	161:aa5281ff4a02	1892	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	1893	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
AnnaBridge	161:aa5281ff4a02	1894	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
AnnaBridge	161:aa5281ff4a02	1895	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
AnnaBridge	161:aa5281ff4a02	1896	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
AnnaBridge	161:aa5281ff4a02	1897	*/
AnnaBridge	161:aa5281ff4a02	1898	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
AnnaBridge	161:aa5281ff4a02	1899
AnnaBridge	161:aa5281ff4a02	1900	/**
AnnaBridge	161:aa5281ff4a02	1901	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
AnnaBridge	161:aa5281ff4a02	1902	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1903	* @retval None
AnnaBridge	161:aa5281ff4a02	1904	*/
AnnaBridge	161:aa5281ff4a02	1905	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
AnnaBridge	161:aa5281ff4a02	1906
AnnaBridge	161:aa5281ff4a02	1907	/**
AnnaBridge	161:aa5281ff4a02	1908	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
AnnaBridge	161:aa5281ff4a02	1909	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1910	* @retval None
AnnaBridge	161:aa5281ff4a02	1911	*/
AnnaBridge	161:aa5281ff4a02	1912	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
AnnaBridge	161:aa5281ff4a02	1913	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
AnnaBridge	161:aa5281ff4a02	1914
AnnaBridge	161:aa5281ff4a02	1915	/**
AnnaBridge	161:aa5281ff4a02	1916	* @brief Enables the MMC Counter Freeze.
AnnaBridge	161:aa5281ff4a02	1917	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1918	* @retval None
AnnaBridge	161:aa5281ff4a02	1919	*/
AnnaBridge	161:aa5281ff4a02	1920	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
AnnaBridge	161:aa5281ff4a02	1921
AnnaBridge	161:aa5281ff4a02	1922	/**
AnnaBridge	161:aa5281ff4a02	1923	* @brief Disables the MMC Counter Freeze.
AnnaBridge	161:aa5281ff4a02	1924	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1925	* @retval None
AnnaBridge	161:aa5281ff4a02	1926	*/
AnnaBridge	161:aa5281ff4a02	1927	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
AnnaBridge	161:aa5281ff4a02	1928
AnnaBridge	161:aa5281ff4a02	1929	/**
AnnaBridge	161:aa5281ff4a02	1930	* @brief Enables the MMC Reset On Read.
AnnaBridge	161:aa5281ff4a02	1931	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1932	* @retval None
AnnaBridge	161:aa5281ff4a02	1933	*/
AnnaBridge	161:aa5281ff4a02	1934	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
AnnaBridge	161:aa5281ff4a02	1935
AnnaBridge	161:aa5281ff4a02	1936	/**
AnnaBridge	161:aa5281ff4a02	1937	* @brief Disables the MMC Reset On Read.
AnnaBridge	161:aa5281ff4a02	1938	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1939	* @retval None
AnnaBridge	161:aa5281ff4a02	1940	*/
AnnaBridge	161:aa5281ff4a02	1941	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
AnnaBridge	161:aa5281ff4a02	1942
AnnaBridge	161:aa5281ff4a02	1943	/**
AnnaBridge	161:aa5281ff4a02	1944	* @brief Enables the MMC Counter Stop Rollover.
AnnaBridge	161:aa5281ff4a02	1945	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1946	* @retval None
AnnaBridge	161:aa5281ff4a02	1947	*/
AnnaBridge	161:aa5281ff4a02	1948	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
AnnaBridge	161:aa5281ff4a02	1949
AnnaBridge	161:aa5281ff4a02	1950	/**
AnnaBridge	161:aa5281ff4a02	1951	* @brief Disables the MMC Counter Stop Rollover.
AnnaBridge	161:aa5281ff4a02	1952	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1953	* @retval None
AnnaBridge	161:aa5281ff4a02	1954	*/
AnnaBridge	161:aa5281ff4a02	1955	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
AnnaBridge	161:aa5281ff4a02	1956
AnnaBridge	161:aa5281ff4a02	1957	/**
AnnaBridge	161:aa5281ff4a02	1958	* @brief Resets the MMC Counters.
AnnaBridge	161:aa5281ff4a02	1959	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1960	* @retval None
AnnaBridge	161:aa5281ff4a02	1961	*/
AnnaBridge	161:aa5281ff4a02	1962	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
AnnaBridge	161:aa5281ff4a02	1963
AnnaBridge	161:aa5281ff4a02	1964	/**
AnnaBridge	161:aa5281ff4a02	1965	* @brief Enables the specified ETHERNET MMC Rx interrupts.
AnnaBridge	161:aa5281ff4a02	1966	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1967	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
AnnaBridge	161:aa5281ff4a02	1968	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	1969	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
AnnaBridge	161:aa5281ff4a02	1970	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
AnnaBridge	161:aa5281ff4a02	1971	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
AnnaBridge	161:aa5281ff4a02	1972	* @retval None
AnnaBridge	161:aa5281ff4a02	1973	*/
AnnaBridge	161:aa5281ff4a02	1974	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
AnnaBridge	161:aa5281ff4a02	1975	/**
AnnaBridge	161:aa5281ff4a02	1976	* @brief Disables the specified ETHERNET MMC Rx interrupts.
AnnaBridge	161:aa5281ff4a02	1977	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1978	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
AnnaBridge	161:aa5281ff4a02	1979	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	1980	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
AnnaBridge	161:aa5281ff4a02	1981	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
AnnaBridge	161:aa5281ff4a02	1982	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
AnnaBridge	161:aa5281ff4a02	1983	* @retval None
AnnaBridge	161:aa5281ff4a02	1984	*/
AnnaBridge	161:aa5281ff4a02	1985	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFFU)
AnnaBridge	161:aa5281ff4a02	1986	/**
AnnaBridge	161:aa5281ff4a02	1987	* @brief Enables the specified ETHERNET MMC Tx interrupts.
AnnaBridge	161:aa5281ff4a02	1988	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	1989	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
AnnaBridge	161:aa5281ff4a02	1990	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	1991	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
AnnaBridge	161:aa5281ff4a02	1992	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
AnnaBridge	161:aa5281ff4a02	1993	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
AnnaBridge	161:aa5281ff4a02	1994	* @retval None
AnnaBridge	161:aa5281ff4a02	1995	*/
AnnaBridge	161:aa5281ff4a02	1996	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1997
AnnaBridge	161:aa5281ff4a02	1998	/**
AnnaBridge	161:aa5281ff4a02	1999	* @brief Disables the specified ETHERNET MMC Tx interrupts.
AnnaBridge	161:aa5281ff4a02	2000	* @param __HANDLE__: ETH Handle.
AnnaBridge	161:aa5281ff4a02	2001	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
AnnaBridge	161:aa5281ff4a02	2002	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	2003	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
AnnaBridge	161:aa5281ff4a02	2004	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
AnnaBridge	161:aa5281ff4a02	2005	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
AnnaBridge	161:aa5281ff4a02	2006	* @retval None
AnnaBridge	161:aa5281ff4a02	2007	*/
AnnaBridge	161:aa5281ff4a02	2008	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	2009
AnnaBridge	161:aa5281ff4a02	2010	/**
AnnaBridge	161:aa5281ff4a02	2011	* @brief Enables the ETH External interrupt line.
AnnaBridge	161:aa5281ff4a02	2012	* @retval None
AnnaBridge	161:aa5281ff4a02	2013	*/
AnnaBridge	161:aa5281ff4a02	2014	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
AnnaBridge	161:aa5281ff4a02	2015
AnnaBridge	161:aa5281ff4a02	2016	/**
AnnaBridge	161:aa5281ff4a02	2017	* @brief Disables the ETH External interrupt line.
AnnaBridge	161:aa5281ff4a02	2018	* @retval None
AnnaBridge	161:aa5281ff4a02	2019	*/
AnnaBridge	161:aa5281ff4a02	2020	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
AnnaBridge	161:aa5281ff4a02	2021
AnnaBridge	161:aa5281ff4a02	2022	/**
AnnaBridge	161:aa5281ff4a02	2023	* @brief Enable event on ETH External event line.
AnnaBridge	161:aa5281ff4a02	2024	* @retval None.
AnnaBridge	161:aa5281ff4a02	2025	*/
AnnaBridge	161:aa5281ff4a02	2026	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR \|= (ETH_EXTI_LINE_WAKEUP)
AnnaBridge	161:aa5281ff4a02	2027
AnnaBridge	161:aa5281ff4a02	2028	/**
AnnaBridge	161:aa5281ff4a02	2029	* @brief Disable event on ETH External event line
AnnaBridge	161:aa5281ff4a02	2030	* @retval None.
AnnaBridge	161:aa5281ff4a02	2031	*/
AnnaBridge	161:aa5281ff4a02	2032	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
AnnaBridge	161:aa5281ff4a02	2033
AnnaBridge	161:aa5281ff4a02	2034	/**
AnnaBridge	161:aa5281ff4a02	2035	* @brief Get flag of the ETH External interrupt line.
AnnaBridge	161:aa5281ff4a02	2036	* @retval None
AnnaBridge	161:aa5281ff4a02	2037	*/
AnnaBridge	161:aa5281ff4a02	2038	#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
AnnaBridge	161:aa5281ff4a02	2039
AnnaBridge	161:aa5281ff4a02	2040	/**
AnnaBridge	161:aa5281ff4a02	2041	* @brief Clear flag of the ETH External interrupt line.
AnnaBridge	161:aa5281ff4a02	2042	* @retval None
AnnaBridge	161:aa5281ff4a02	2043	*/
AnnaBridge	161:aa5281ff4a02	2044	#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
AnnaBridge	161:aa5281ff4a02	2045
AnnaBridge	161:aa5281ff4a02	2046	/**
AnnaBridge	161:aa5281ff4a02	2047	* @brief Enables rising edge trigger to the ETH External interrupt line.
AnnaBridge	161:aa5281ff4a02	2048	* @retval None
AnnaBridge	161:aa5281ff4a02	2049	*/
AnnaBridge	161:aa5281ff4a02	2050	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
AnnaBridge	161:aa5281ff4a02	2051
AnnaBridge	161:aa5281ff4a02	2052	/**
AnnaBridge	161:aa5281ff4a02	2053	* @brief Disables the rising edge trigger to the ETH External interrupt line.
AnnaBridge	161:aa5281ff4a02	2054	* @retval None
AnnaBridge	161:aa5281ff4a02	2055	*/
AnnaBridge	161:aa5281ff4a02	2056	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
AnnaBridge	161:aa5281ff4a02	2057
AnnaBridge	161:aa5281ff4a02	2058	/**
AnnaBridge	161:aa5281ff4a02	2059	* @brief Enables falling edge trigger to the ETH External interrupt line.
AnnaBridge	161:aa5281ff4a02	2060	* @retval None
AnnaBridge	161:aa5281ff4a02	2061	*/
AnnaBridge	161:aa5281ff4a02	2062	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP)
AnnaBridge	161:aa5281ff4a02	2063
AnnaBridge	161:aa5281ff4a02	2064	/**
AnnaBridge	161:aa5281ff4a02	2065	* @brief Disables falling edge trigger to the ETH External interrupt line.
AnnaBridge	161:aa5281ff4a02	2066	* @retval None
AnnaBridge	161:aa5281ff4a02	2067	*/
AnnaBridge	161:aa5281ff4a02	2068	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
AnnaBridge	161:aa5281ff4a02	2069
AnnaBridge	161:aa5281ff4a02	2070	/**
AnnaBridge	161:aa5281ff4a02	2071	* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
AnnaBridge	161:aa5281ff4a02	2072	* @retval None
AnnaBridge	161:aa5281ff4a02	2073	*/
AnnaBridge	161:aa5281ff4a02	2074	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP;\
AnnaBridge	161:aa5281ff4a02	2075	EXTI->FTSR \|= ETH_EXTI_LINE_WAKEUP;\
AnnaBridge	161:aa5281ff4a02	2076	}while(0U)
AnnaBridge	161:aa5281ff4a02	2077
AnnaBridge	161:aa5281ff4a02	2078	/**
AnnaBridge	161:aa5281ff4a02	2079	* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
AnnaBridge	161:aa5281ff4a02	2080	* @retval None
AnnaBridge	161:aa5281ff4a02	2081	*/
AnnaBridge	161:aa5281ff4a02	2082	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
AnnaBridge	161:aa5281ff4a02	2083	EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
AnnaBridge	161:aa5281ff4a02	2084	}while(0U)
AnnaBridge	161:aa5281ff4a02	2085
AnnaBridge	161:aa5281ff4a02	2086	/**
AnnaBridge	161:aa5281ff4a02	2087	* @brief Generate a Software interrupt on selected EXTI line.
AnnaBridge	161:aa5281ff4a02	2088	* @retval None.
AnnaBridge	161:aa5281ff4a02	2089	*/
AnnaBridge	161:aa5281ff4a02	2090	#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER\|= ETH_EXTI_LINE_WAKEUP
AnnaBridge	161:aa5281ff4a02	2091
AnnaBridge	161:aa5281ff4a02	2092	/**
AnnaBridge	161:aa5281ff4a02	2093	* @}
AnnaBridge	161:aa5281ff4a02	2094	*/
AnnaBridge	161:aa5281ff4a02	2095	/* Exported functions --------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	2096
AnnaBridge	161:aa5281ff4a02	2097	/** @addtogroup ETH_Exported_Functions
AnnaBridge	161:aa5281ff4a02	2098	* @{
AnnaBridge	161:aa5281ff4a02	2099	*/
AnnaBridge	161:aa5281ff4a02	2100
AnnaBridge	161:aa5281ff4a02	2101	/* Initialization and de-initialization functions ****************************/
AnnaBridge	161:aa5281ff4a02	2102
AnnaBridge	161:aa5281ff4a02	2103	/** @addtogroup ETH_Exported_Functions_Group1
AnnaBridge	161:aa5281ff4a02	2104	* @{
AnnaBridge	161:aa5281ff4a02	2105	*/
AnnaBridge	161:aa5281ff4a02	2106	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2107	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2108	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2109	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2110	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
AnnaBridge	161:aa5281ff4a02	2111	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
AnnaBridge	161:aa5281ff4a02	2112
AnnaBridge	161:aa5281ff4a02	2113	/**
AnnaBridge	161:aa5281ff4a02	2114	* @}
AnnaBridge	161:aa5281ff4a02	2115	*/
AnnaBridge	161:aa5281ff4a02	2116	/* IO operation functions ****************************************************/
AnnaBridge	161:aa5281ff4a02	2117
AnnaBridge	161:aa5281ff4a02	2118	/** @addtogroup ETH_Exported_Functions_Group2
AnnaBridge	161:aa5281ff4a02	2119	* @{
AnnaBridge	161:aa5281ff4a02	2120	*/
AnnaBridge	161:aa5281ff4a02	2121	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
AnnaBridge	161:aa5281ff4a02	2122	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2123	/* Communication with PHY functions*/
AnnaBridge	161:aa5281ff4a02	2124	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
AnnaBridge	161:aa5281ff4a02	2125	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
AnnaBridge	161:aa5281ff4a02	2126	/* Non-Blocking mode: Interrupt */
AnnaBridge	161:aa5281ff4a02	2127	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2128	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2129	/* Callback in non blocking modes (Interrupt) */
AnnaBridge	161:aa5281ff4a02	2130	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2131	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2132	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2133	/**
AnnaBridge	161:aa5281ff4a02	2134	* @}
AnnaBridge	161:aa5281ff4a02	2135	*/
AnnaBridge	161:aa5281ff4a02	2136
AnnaBridge	161:aa5281ff4a02	2137	/* Peripheral Control functions **********************************************/
AnnaBridge	161:aa5281ff4a02	2138
AnnaBridge	161:aa5281ff4a02	2139	/** @addtogroup ETH_Exported_Functions_Group3
AnnaBridge	161:aa5281ff4a02	2140	* @{
AnnaBridge	161:aa5281ff4a02	2141	*/
AnnaBridge	161:aa5281ff4a02	2142
AnnaBridge	161:aa5281ff4a02	2143	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2144	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2145	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
AnnaBridge	161:aa5281ff4a02	2146	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
AnnaBridge	161:aa5281ff4a02	2147	/**
AnnaBridge	161:aa5281ff4a02	2148	* @}
AnnaBridge	161:aa5281ff4a02	2149	*/
AnnaBridge	161:aa5281ff4a02	2150
AnnaBridge	161:aa5281ff4a02	2151	/* Peripheral State functions ************************************************/
AnnaBridge	161:aa5281ff4a02	2152
AnnaBridge	161:aa5281ff4a02	2153	/** @addtogroup ETH_Exported_Functions_Group4
AnnaBridge	161:aa5281ff4a02	2154	* @{
AnnaBridge	161:aa5281ff4a02	2155	*/
AnnaBridge	161:aa5281ff4a02	2156	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
AnnaBridge	161:aa5281ff4a02	2157	/**
AnnaBridge	161:aa5281ff4a02	2158	* @}
AnnaBridge	161:aa5281ff4a02	2159	*/
AnnaBridge	161:aa5281ff4a02	2160
AnnaBridge	161:aa5281ff4a02	2161	/**
AnnaBridge	161:aa5281ff4a02	2162	* @}
AnnaBridge	161:aa5281ff4a02	2163	*/
AnnaBridge	161:aa5281ff4a02	2164
AnnaBridge	161:aa5281ff4a02	2165	/**
AnnaBridge	161:aa5281ff4a02	2166	* @}
AnnaBridge	161:aa5281ff4a02	2167	*/
AnnaBridge	161:aa5281ff4a02	2168
AnnaBridge	161:aa5281ff4a02	2169	/**
AnnaBridge	161:aa5281ff4a02	2170	* @}
AnnaBridge	161:aa5281ff4a02	2171	*/
AnnaBridge	161:aa5281ff4a02	2172
AnnaBridge	161:aa5281ff4a02	2173	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\|\
AnnaBridge	161:aa5281ff4a02	2174	STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	161:aa5281ff4a02	2175
AnnaBridge	161:aa5281ff4a02	2176	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	2177	}
AnnaBridge	161:aa5281ff4a02	2178	#endif
AnnaBridge	161:aa5281ff4a02	2179
AnnaBridge	161:aa5281ff4a02	2180	#endif /* __STM32F4xx_HAL_ETH_H */
AnnaBridge	161:aa5281ff4a02	2181
AnnaBridge	161:aa5281ff4a02	2182
AnnaBridge	161:aa5281ff4a02	2183	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/