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TARGET_NUCLEO_F411RE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h@147:a97add6d7e64, 2017-07-19 (annotated)

Committer:
Kojto
Date:
Wed Jul 19 16:46:19 2017 +0100
Revision:
147:a97add6d7e64
Parent:
145:64910690c574 
Release 147 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**
Kojto 122:f9eeca106725 2 ******************************************************************************
Kojto 122:f9eeca106725 3 * @file stm32f4xx_hal_dma.h
Kojto 122:f9eeca106725 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @version V1.7.1
AnnaBridge 145:64910690c574 6 * @date 14-April-2017
Kojto 122:f9eeca106725 7 * @brief Header file of DMA HAL module.
Kojto 122:f9eeca106725 8 ******************************************************************************
Kojto 122:f9eeca106725 9 * @attention
Kojto 122:f9eeca106725 10 *
AnnaBridge 145:64910690c574 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Kojto 122:f9eeca106725 12 *
Kojto 122:f9eeca106725 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 14 * are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 122:f9eeca106725 16 * this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 122:f9eeca106725 18 * this list of conditions and the following disclaimer in the documentation
Kojto 122:f9eeca106725 19 * and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 122:f9eeca106725 21 * may be used to endorse or promote products derived from this software
Kojto 122:f9eeca106725 22 * without specific prior written permission.
Kojto 122:f9eeca106725 23 *
Kojto 122:f9eeca106725 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 122:f9eeca106725 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 122:f9eeca106725 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 122:f9eeca106725 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 122:f9eeca106725 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 122:f9eeca106725 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 122:f9eeca106725 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 34 *
Kojto 122:f9eeca106725 35 ******************************************************************************
Kojto 122:f9eeca106725 36 */
Kojto 122:f9eeca106725 37
Kojto 122:f9eeca106725 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 122:f9eeca106725 39 #ifndef __STM32F4xx_HAL_DMA_H
Kojto 122:f9eeca106725 40 #define __STM32F4xx_HAL_DMA_H
Kojto 122:f9eeca106725 41
Kojto 122:f9eeca106725 42 #ifdef __cplusplus
Kojto 122:f9eeca106725 43 extern "C" {
Kojto 122:f9eeca106725 44 #endif
Kojto 122:f9eeca106725 45
Kojto 122:f9eeca106725 46 /* Includes ------------------------------------------------------------------*/
Kojto 122:f9eeca106725 47 #include "stm32f4xx_hal_def.h"
Kojto 122:f9eeca106725 48
Kojto 122:f9eeca106725 49 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 122:f9eeca106725 50 * @{
Kojto 122:f9eeca106725 51 */
Kojto 122:f9eeca106725 52
Kojto 122:f9eeca106725 53 /** @addtogroup DMA
Kojto 122:f9eeca106725 54 * @{
Kojto 122:f9eeca106725 55 */
Kojto 122:f9eeca106725 56
Kojto 122:f9eeca106725 57 /* Exported types ------------------------------------------------------------*/
Kojto 122:f9eeca106725 58
Kojto 122:f9eeca106725 59 /** @defgroup DMA_Exported_Types DMA Exported Types
Kojto 122:f9eeca106725 60 * @brief DMA Exported Types
Kojto 122:f9eeca106725 61 * @{
Kojto 122:f9eeca106725 62 */
Kojto 122:f9eeca106725 63
Kojto 122:f9eeca106725 64 /**
Kojto 122:f9eeca106725 65 * @brief DMA Configuration Structure definition
Kojto 122:f9eeca106725 66 */
Kojto 122:f9eeca106725 67 typedef struct
Kojto 122:f9eeca106725 68 {
Kojto 122:f9eeca106725 69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
Kojto 122:f9eeca106725 70 This parameter can be a value of @ref DMA_Channel_selection */
Kojto 122:f9eeca106725 71
Kojto 122:f9eeca106725 72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
Kojto 122:f9eeca106725 73 from memory to memory or from peripheral to memory.
Kojto 122:f9eeca106725 74 This parameter can be a value of @ref DMA_Data_transfer_direction */
Kojto 122:f9eeca106725 75
Kojto 122:f9eeca106725 76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
Kojto 122:f9eeca106725 77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
Kojto 122:f9eeca106725 78
Kojto 122:f9eeca106725 79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
Kojto 122:f9eeca106725 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
Kojto 122:f9eeca106725 81
Kojto 122:f9eeca106725 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
Kojto 122:f9eeca106725 83 This parameter can be a value of @ref DMA_Peripheral_data_size */
Kojto 122:f9eeca106725 84
Kojto 122:f9eeca106725 85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
Kojto 122:f9eeca106725 86 This parameter can be a value of @ref DMA_Memory_data_size */
Kojto 122:f9eeca106725 87
Kojto 122:f9eeca106725 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
Kojto 122:f9eeca106725 89 This parameter can be a value of @ref DMA_mode
Kojto 122:f9eeca106725 90 @note The circular buffer mode cannot be used if the memory-to-memory
Kojto 122:f9eeca106725 91 data transfer is configured on the selected Stream */
Kojto 122:f9eeca106725 92
Kojto 122:f9eeca106725 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
Kojto 122:f9eeca106725 94 This parameter can be a value of @ref DMA_Priority_level */
Kojto 122:f9eeca106725 95
Kojto 122:f9eeca106725 96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
Kojto 122:f9eeca106725 97 This parameter can be a value of @ref DMA_FIFO_direct_mode
Kojto 122:f9eeca106725 98 @note The Direct mode (FIFO mode disabled) cannot be used if the
Kojto 122:f9eeca106725 99 memory-to-memory data transfer is configured on the selected stream */
Kojto 122:f9eeca106725 100
Kojto 122:f9eeca106725 101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
Kojto 122:f9eeca106725 102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
Kojto 122:f9eeca106725 103
Kojto 122:f9eeca106725 104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
Kojto 122:f9eeca106725 105 It specifies the amount of data to be transferred in a single non interruptible
Kojto 122:f9eeca106725 106 transaction.
Kojto 122:f9eeca106725 107 This parameter can be a value of @ref DMA_Memory_burst
Kojto 122:f9eeca106725 108 @note The burst mode is possible only if the address Increment mode is enabled. */
Kojto 122:f9eeca106725 109
Kojto 122:f9eeca106725 110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
Kojto 122:f9eeca106725 111 It specifies the amount of data to be transferred in a single non interruptible
Kojto 122:f9eeca106725 112 transaction.
Kojto 122:f9eeca106725 113 This parameter can be a value of @ref DMA_Peripheral_burst
Kojto 122:f9eeca106725 114 @note The burst mode is possible only if the address Increment mode is enabled. */
Kojto 122:f9eeca106725 115 }DMA_InitTypeDef;
Kojto 122:f9eeca106725 116
Kojto 122:f9eeca106725 117
Kojto 122:f9eeca106725 118 /**
Kojto 122:f9eeca106725 119 * @brief HAL DMA State structures definition
Kojto 122:f9eeca106725 120 */
Kojto 122:f9eeca106725 121 typedef enum
Kojto 122:f9eeca106725 122 {
Kojto 122:f9eeca106725 123 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
Kojto 122:f9eeca106725 124 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
Kojto 122:f9eeca106725 125 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
Kojto 122:f9eeca106725 126 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
Kojto 122:f9eeca106725 127 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
Kojto 122:f9eeca106725 128 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
Kojto 122:f9eeca106725 129 }HAL_DMA_StateTypeDef;
Kojto 122:f9eeca106725 130
Kojto 122:f9eeca106725 131 /**
Kojto 122:f9eeca106725 132 * @brief HAL DMA Error Code structure definition
Kojto 122:f9eeca106725 133 */
Kojto 122:f9eeca106725 134 typedef enum
Kojto 122:f9eeca106725 135 {
AnnaBridge 145:64910690c574 136 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
AnnaBridge 145:64910690c574 137 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
Kojto 122:f9eeca106725 138 }HAL_DMA_LevelCompleteTypeDef;
Kojto 122:f9eeca106725 139
Kojto 122:f9eeca106725 140 /**
Kojto 122:f9eeca106725 141 * @brief HAL DMA Error Code structure definition
Kojto 122:f9eeca106725 142 */
Kojto 122:f9eeca106725 143 typedef enum
Kojto 122:f9eeca106725 144 {
AnnaBridge 145:64910690c574 145 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
AnnaBridge 145:64910690c574 146 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
AnnaBridge 145:64910690c574 147 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
AnnaBridge 145:64910690c574 148 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
AnnaBridge 145:64910690c574 149 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
AnnaBridge 145:64910690c574 150 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
AnnaBridge 145:64910690c574 151 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
Kojto 122:f9eeca106725 152 }HAL_DMA_CallbackIDTypeDef;
Kojto 122:f9eeca106725 153
Kojto 122:f9eeca106725 154 /**
Kojto 122:f9eeca106725 155 * @brief DMA handle Structure definition
Kojto 122:f9eeca106725 156 */
Kojto 122:f9eeca106725 157 typedef struct __DMA_HandleTypeDef
Kojto 122:f9eeca106725 158 {
AnnaBridge 145:64910690c574 159 DMA_Stream_TypeDef *Instance; /*!< Register base address */
Kojto 122:f9eeca106725 160
AnnaBridge 145:64910690c574 161 DMA_InitTypeDef Init; /*!< DMA communication parameters */
Kojto 122:f9eeca106725 162
AnnaBridge 145:64910690c574 163 HAL_LockTypeDef Lock; /*!< DMA locking object */
Kojto 122:f9eeca106725 164
AnnaBridge 145:64910690c574 165 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
Kojto 122:f9eeca106725 166
AnnaBridge 145:64910690c574 167 void *Parent; /*!< Parent object state */
Kojto 122:f9eeca106725 168
AnnaBridge 145:64910690c574 169 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
Kojto 122:f9eeca106725 170
AnnaBridge 145:64910690c574 171 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
Kojto 122:f9eeca106725 172
AnnaBridge 145:64910690c574 173 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
Kojto 122:f9eeca106725 174
Kojto 122:f9eeca106725 175 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
Kojto 122:f9eeca106725 176
AnnaBridge 145:64910690c574 177 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
Kojto 122:f9eeca106725 178
AnnaBridge 145:64910690c574 179 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
Kojto 122:f9eeca106725 180
AnnaBridge 145:64910690c574 181 __IO uint32_t ErrorCode; /*!< DMA Error code */
Kojto 122:f9eeca106725 182
AnnaBridge 145:64910690c574 183 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
Kojto 122:f9eeca106725 184
AnnaBridge 145:64910690c574 185 uint32_t StreamIndex; /*!< DMA Stream Index */
Kojto 122:f9eeca106725 186
Kojto 122:f9eeca106725 187 }DMA_HandleTypeDef;
Kojto 122:f9eeca106725 188
Kojto 122:f9eeca106725 189 /**
Kojto 122:f9eeca106725 190 * @}
Kojto 122:f9eeca106725 191 */
Kojto 122:f9eeca106725 192
Kojto 122:f9eeca106725 193 /* Exported constants --------------------------------------------------------*/
Kojto 122:f9eeca106725 194
Kojto 122:f9eeca106725 195 /** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto 122:f9eeca106725 196 * @brief DMA Exported constants
Kojto 122:f9eeca106725 197 * @{
Kojto 122:f9eeca106725 198 */
Kojto 122:f9eeca106725 199
Kojto 122:f9eeca106725 200 /** @defgroup DMA_Error_Code DMA Error Code
Kojto 122:f9eeca106725 201 * @brief DMA Error Code
Kojto 122:f9eeca106725 202 * @{
Kojto 122:f9eeca106725 203 */
AnnaBridge 145:64910690c574 204 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 145:64910690c574 205 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
AnnaBridge 145:64910690c574 206 #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
AnnaBridge 145:64910690c574 207 #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
AnnaBridge 145:64910690c574 208 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
AnnaBridge 145:64910690c574 209 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
AnnaBridge 145:64910690c574 210 #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
AnnaBridge 145:64910690c574 211 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
Kojto 122:f9eeca106725 212 /**
Kojto 122:f9eeca106725 213 * @}
Kojto 122:f9eeca106725 214 */
Kojto 122:f9eeca106725 215
Kojto 122:f9eeca106725 216 /** @defgroup DMA_Channel_selection DMA Channel selection
Kojto 122:f9eeca106725 217 * @brief DMA channel selection
Kojto 122:f9eeca106725 218 * @{
Kojto 122:f9eeca106725 219 */
AnnaBridge 145:64910690c574 220 #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
AnnaBridge 145:64910690c574 221 #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
AnnaBridge 145:64910690c574 222 #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
AnnaBridge 145:64910690c574 223 #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
AnnaBridge 145:64910690c574 224 #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
AnnaBridge 145:64910690c574 225 #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
AnnaBridge 145:64910690c574 226 #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
AnnaBridge 145:64910690c574 227 #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
AnnaBridge 145:64910690c574 228 #if defined (DMA_SxCR_CHSEL_3)
AnnaBridge 145:64910690c574 229 #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */
AnnaBridge 145:64910690c574 230 #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */
AnnaBridge 145:64910690c574 231 #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */
AnnaBridge 145:64910690c574 232 #define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */
AnnaBridge 145:64910690c574 233 #define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */
AnnaBridge 145:64910690c574 234 #define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */
AnnaBridge 145:64910690c574 235 #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */
AnnaBridge 145:64910690c574 236 #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */
AnnaBridge 145:64910690c574 237 #endif /* DMA_SxCR_CHSEL_3 */
Kojto 122:f9eeca106725 238 /**
Kojto 122:f9eeca106725 239 * @}
Kojto 122:f9eeca106725 240 */
Kojto 122:f9eeca106725 241
Kojto 122:f9eeca106725 242 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
Kojto 122:f9eeca106725 243 * @brief DMA data transfer direction
Kojto 122:f9eeca106725 244 * @{
Kojto 122:f9eeca106725 245 */
AnnaBridge 145:64910690c574 246 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
AnnaBridge 145:64910690c574 247 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
AnnaBridge 145:64910690c574 248 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
Kojto 122:f9eeca106725 249 /**
Kojto 122:f9eeca106725 250 * @}
Kojto 122:f9eeca106725 251 */
Kojto 122:f9eeca106725 252
Kojto 122:f9eeca106725 253 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
Kojto 122:f9eeca106725 254 * @brief DMA peripheral incremented mode
Kojto 122:f9eeca106725 255 * @{
Kojto 122:f9eeca106725 256 */
AnnaBridge 145:64910690c574 257 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
AnnaBridge 145:64910690c574 258 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
Kojto 122:f9eeca106725 259 /**
Kojto 122:f9eeca106725 260 * @}
Kojto 122:f9eeca106725 261 */
Kojto 122:f9eeca106725 262
Kojto 122:f9eeca106725 263 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
Kojto 122:f9eeca106725 264 * @brief DMA memory incremented mode
Kojto 122:f9eeca106725 265 * @{
Kojto 122:f9eeca106725 266 */
AnnaBridge 145:64910690c574 267 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
AnnaBridge 145:64910690c574 268 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
Kojto 122:f9eeca106725 269 /**
Kojto 122:f9eeca106725 270 * @}
Kojto 122:f9eeca106725 271 */
Kojto 122:f9eeca106725 272
Kojto 122:f9eeca106725 273 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
Kojto 122:f9eeca106725 274 * @brief DMA peripheral data size
Kojto 122:f9eeca106725 275 * @{
Kojto 122:f9eeca106725 276 */
AnnaBridge 145:64910690c574 277 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
AnnaBridge 145:64910690c574 278 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
AnnaBridge 145:64910690c574 279 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
Kojto 122:f9eeca106725 280 /**
Kojto 122:f9eeca106725 281 * @}
Kojto 122:f9eeca106725 282 */
Kojto 122:f9eeca106725 283
Kojto 122:f9eeca106725 284 /** @defgroup DMA_Memory_data_size DMA Memory data size
Kojto 122:f9eeca106725 285 * @brief DMA memory data size
Kojto 122:f9eeca106725 286 * @{
Kojto 122:f9eeca106725 287 */
AnnaBridge 145:64910690c574 288 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
AnnaBridge 145:64910690c574 289 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
AnnaBridge 145:64910690c574 290 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
Kojto 122:f9eeca106725 291 /**
Kojto 122:f9eeca106725 292 * @}
Kojto 122:f9eeca106725 293 */
Kojto 122:f9eeca106725 294
Kojto 122:f9eeca106725 295 /** @defgroup DMA_mode DMA mode
Kojto 122:f9eeca106725 296 * @brief DMA mode
Kojto 122:f9eeca106725 297 * @{
Kojto 122:f9eeca106725 298 */
AnnaBridge 145:64910690c574 299 #define DMA_NORMAL 0x00000000U /*!< Normal mode */
AnnaBridge 145:64910690c574 300 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
AnnaBridge 145:64910690c574 301 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
Kojto 122:f9eeca106725 302 /**
Kojto 122:f9eeca106725 303 * @}
Kojto 122:f9eeca106725 304 */
Kojto 122:f9eeca106725 305
Kojto 122:f9eeca106725 306 /** @defgroup DMA_Priority_level DMA Priority level
Kojto 122:f9eeca106725 307 * @brief DMA priority levels
Kojto 122:f9eeca106725 308 * @{
Kojto 122:f9eeca106725 309 */
AnnaBridge 145:64910690c574 310 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
AnnaBridge 145:64910690c574 311 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
AnnaBridge 145:64910690c574 312 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
AnnaBridge 145:64910690c574 313 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
Kojto 122:f9eeca106725 314 /**
Kojto 122:f9eeca106725 315 * @}
Kojto 122:f9eeca106725 316 */
Kojto 122:f9eeca106725 317
Kojto 122:f9eeca106725 318 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
Kojto 122:f9eeca106725 319 * @brief DMA FIFO direct mode
Kojto 122:f9eeca106725 320 * @{
Kojto 122:f9eeca106725 321 */
AnnaBridge 145:64910690c574 322 #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
AnnaBridge 145:64910690c574 323 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
Kojto 122:f9eeca106725 324 /**
Kojto 122:f9eeca106725 325 * @}
Kojto 122:f9eeca106725 326 */
Kojto 122:f9eeca106725 327
Kojto 122:f9eeca106725 328 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
Kojto 122:f9eeca106725 329 * @brief DMA FIFO level
Kojto 122:f9eeca106725 330 * @{
Kojto 122:f9eeca106725 331 */
AnnaBridge 145:64910690c574 332 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
Kojto 122:f9eeca106725 333 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
Kojto 122:f9eeca106725 334 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
Kojto 122:f9eeca106725 335 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
Kojto 122:f9eeca106725 336 /**
Kojto 122:f9eeca106725 337 * @}
Kojto 122:f9eeca106725 338 */
Kojto 122:f9eeca106725 339
Kojto 122:f9eeca106725 340 /** @defgroup DMA_Memory_burst DMA Memory burst
Kojto 122:f9eeca106725 341 * @brief DMA memory burst
Kojto 122:f9eeca106725 342 * @{
Kojto 122:f9eeca106725 343 */
AnnaBridge 145:64910690c574 344 #define DMA_MBURST_SINGLE 0x00000000U
AnnaBridge 145:64910690c574 345 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
AnnaBridge 145:64910690c574 346 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
AnnaBridge 145:64910690c574 347 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
Kojto 122:f9eeca106725 348 /**
Kojto 122:f9eeca106725 349 * @}
Kojto 122:f9eeca106725 350 */
Kojto 122:f9eeca106725 351
Kojto 122:f9eeca106725 352 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
Kojto 122:f9eeca106725 353 * @brief DMA peripheral burst
Kojto 122:f9eeca106725 354 * @{
Kojto 122:f9eeca106725 355 */
AnnaBridge 145:64910690c574 356 #define DMA_PBURST_SINGLE 0x00000000U
AnnaBridge 145:64910690c574 357 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
AnnaBridge 145:64910690c574 358 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
AnnaBridge 145:64910690c574 359 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
Kojto 122:f9eeca106725 360 /**
Kojto 122:f9eeca106725 361 * @}
Kojto 122:f9eeca106725 362 */
Kojto 122:f9eeca106725 363
Kojto 122:f9eeca106725 364 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
Kojto 122:f9eeca106725 365 * @brief DMA interrupts definition
Kojto 122:f9eeca106725 366 * @{
Kojto 122:f9eeca106725 367 */
AnnaBridge 145:64910690c574 368 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
AnnaBridge 145:64910690c574 369 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
AnnaBridge 145:64910690c574 370 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
AnnaBridge 145:64910690c574 371 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
AnnaBridge 145:64910690c574 372 #define DMA_IT_FE 0x00000080U
Kojto 122:f9eeca106725 373 /**
Kojto 122:f9eeca106725 374 * @}
Kojto 122:f9eeca106725 375 */
Kojto 122:f9eeca106725 376
Kojto 122:f9eeca106725 377 /** @defgroup DMA_flag_definitions DMA flag definitions
Kojto 122:f9eeca106725 378 * @brief DMA flag definitions
Kojto 122:f9eeca106725 379 * @{
Kojto 122:f9eeca106725 380 */
AnnaBridge 145:64910690c574 381 #define DMA_FLAG_FEIF0_4 0x00800001U
AnnaBridge 145:64910690c574 382 #define DMA_FLAG_DMEIF0_4 0x00800004U
AnnaBridge 145:64910690c574 383 #define DMA_FLAG_TEIF0_4 0x00000008U
AnnaBridge 145:64910690c574 384 #define DMA_FLAG_HTIF0_4 0x00000010U
AnnaBridge 145:64910690c574 385 #define DMA_FLAG_TCIF0_4 0x00000020U
AnnaBridge 145:64910690c574 386 #define DMA_FLAG_FEIF1_5 0x00000040U
AnnaBridge 145:64910690c574 387 #define DMA_FLAG_DMEIF1_5 0x00000100U
AnnaBridge 145:64910690c574 388 #define DMA_FLAG_TEIF1_5 0x00000200U
AnnaBridge 145:64910690c574 389 #define DMA_FLAG_HTIF1_5 0x00000400U
AnnaBridge 145:64910690c574 390 #define DMA_FLAG_TCIF1_5 0x00000800U
AnnaBridge 145:64910690c574 391 #define DMA_FLAG_FEIF2_6 0x00010000U
AnnaBridge 145:64910690c574 392 #define DMA_FLAG_DMEIF2_6 0x00040000U
AnnaBridge 145:64910690c574 393 #define DMA_FLAG_TEIF2_6 0x00080000U
AnnaBridge 145:64910690c574 394 #define DMA_FLAG_HTIF2_6 0x00100000U
AnnaBridge 145:64910690c574 395 #define DMA_FLAG_TCIF2_6 0x00200000U
AnnaBridge 145:64910690c574 396 #define DMA_FLAG_FEIF3_7 0x00400000U
AnnaBridge 145:64910690c574 397 #define DMA_FLAG_DMEIF3_7 0x01000000U
AnnaBridge 145:64910690c574 398 #define DMA_FLAG_TEIF3_7 0x02000000U
AnnaBridge 145:64910690c574 399 #define DMA_FLAG_HTIF3_7 0x04000000U
AnnaBridge 145:64910690c574 400 #define DMA_FLAG_TCIF3_7 0x08000000U
Kojto 122:f9eeca106725 401 /**
Kojto 122:f9eeca106725 402 * @}
Kojto 122:f9eeca106725 403 */
Kojto 122:f9eeca106725 404
Kojto 122:f9eeca106725 405 /**
Kojto 122:f9eeca106725 406 * @}
Kojto 122:f9eeca106725 407 */
Kojto 122:f9eeca106725 408
Kojto 122:f9eeca106725 409 /* Exported macro ------------------------------------------------------------*/
Kojto 122:f9eeca106725 410
Kojto 122:f9eeca106725 411 /** @brief Reset DMA handle state
Kojto 122:f9eeca106725 412 * @param __HANDLE__: specifies the DMA handle.
Kojto 122:f9eeca106725 413 * @retval None
Kojto 122:f9eeca106725 414 */
Kojto 122:f9eeca106725 415 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Kojto 122:f9eeca106725 416
Kojto 122:f9eeca106725 417 /**
Kojto 122:f9eeca106725 418 * @brief Return the current DMA Stream FIFO filled level.
Kojto 122:f9eeca106725 419 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 420 * @retval The FIFO filling state.
Kojto 122:f9eeca106725 421 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
Kojto 122:f9eeca106725 422 * and not empty.
Kojto 122:f9eeca106725 423 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
Kojto 122:f9eeca106725 424 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
Kojto 122:f9eeca106725 425 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
Kojto 122:f9eeca106725 426 * - DMA_FIFOStatus_Empty: when FIFO is empty
Kojto 122:f9eeca106725 427 * - DMA_FIFOStatus_Full: when FIFO is full
Kojto 122:f9eeca106725 428 */
Kojto 122:f9eeca106725 429 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
Kojto 122:f9eeca106725 430
Kojto 122:f9eeca106725 431 /**
Kojto 122:f9eeca106725 432 * @brief Enable the specified DMA Stream.
Kojto 122:f9eeca106725 433 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 434 * @retval None
Kojto 122:f9eeca106725 435 */
Kojto 122:f9eeca106725 436 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
Kojto 122:f9eeca106725 437
Kojto 122:f9eeca106725 438 /**
Kojto 122:f9eeca106725 439 * @brief Disable the specified DMA Stream.
Kojto 122:f9eeca106725 440 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 441 * @retval None
Kojto 122:f9eeca106725 442 */
Kojto 122:f9eeca106725 443 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
Kojto 122:f9eeca106725 444
Kojto 122:f9eeca106725 445 /* Interrupt & Flag management */
Kojto 122:f9eeca106725 446
Kojto 122:f9eeca106725 447 /**
Kojto 122:f9eeca106725 448 * @brief Return the current DMA Stream transfer complete flag.
Kojto 122:f9eeca106725 449 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 450 * @retval The specified transfer complete flag index.
Kojto 122:f9eeca106725 451 */
Kojto 122:f9eeca106725 452 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
Kojto 122:f9eeca106725 453 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
Kojto 122:f9eeca106725 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
Kojto 122:f9eeca106725 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
Kojto 122:f9eeca106725 456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
Kojto 122:f9eeca106725 457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
Kojto 122:f9eeca106725 458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
Kojto 122:f9eeca106725 459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
Kojto 122:f9eeca106725 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
Kojto 122:f9eeca106725 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
Kojto 122:f9eeca106725 462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
Kojto 122:f9eeca106725 463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
Kojto 122:f9eeca106725 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
Kojto 122:f9eeca106725 465 DMA_FLAG_TCIF3_7)
Kojto 122:f9eeca106725 466
Kojto 122:f9eeca106725 467 /**
Kojto 122:f9eeca106725 468 * @brief Return the current DMA Stream half transfer complete flag.
Kojto 122:f9eeca106725 469 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 470 * @retval The specified half transfer complete flag index.
Kojto 122:f9eeca106725 471 */
Kojto 122:f9eeca106725 472 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
Kojto 122:f9eeca106725 473 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
Kojto 122:f9eeca106725 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
Kojto 122:f9eeca106725 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
Kojto 122:f9eeca106725 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
Kojto 122:f9eeca106725 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
Kojto 122:f9eeca106725 478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
Kojto 122:f9eeca106725 479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
Kojto 122:f9eeca106725 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
Kojto 122:f9eeca106725 481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
Kojto 122:f9eeca106725 482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
Kojto 122:f9eeca106725 483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
Kojto 122:f9eeca106725 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
Kojto 122:f9eeca106725 485 DMA_FLAG_HTIF3_7)
Kojto 122:f9eeca106725 486
Kojto 122:f9eeca106725 487 /**
Kojto 122:f9eeca106725 488 * @brief Return the current DMA Stream transfer error flag.
Kojto 122:f9eeca106725 489 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 490 * @retval The specified transfer error flag index.
Kojto 122:f9eeca106725 491 */
Kojto 122:f9eeca106725 492 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
Kojto 122:f9eeca106725 493 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
Kojto 122:f9eeca106725 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
Kojto 122:f9eeca106725 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
Kojto 122:f9eeca106725 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
Kojto 122:f9eeca106725 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
Kojto 122:f9eeca106725 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
Kojto 122:f9eeca106725 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
Kojto 122:f9eeca106725 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
Kojto 122:f9eeca106725 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
Kojto 122:f9eeca106725 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
Kojto 122:f9eeca106725 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
Kojto 122:f9eeca106725 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
Kojto 122:f9eeca106725 505 DMA_FLAG_TEIF3_7)
Kojto 122:f9eeca106725 506
Kojto 122:f9eeca106725 507 /**
Kojto 122:f9eeca106725 508 * @brief Return the current DMA Stream FIFO error flag.
Kojto 122:f9eeca106725 509 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 510 * @retval The specified FIFO error flag index.
Kojto 122:f9eeca106725 511 */
Kojto 122:f9eeca106725 512 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
Kojto 122:f9eeca106725 513 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
Kojto 122:f9eeca106725 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
Kojto 122:f9eeca106725 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
Kojto 122:f9eeca106725 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
Kojto 122:f9eeca106725 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
Kojto 122:f9eeca106725 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
Kojto 122:f9eeca106725 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
Kojto 122:f9eeca106725 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
Kojto 122:f9eeca106725 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
Kojto 122:f9eeca106725 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
Kojto 122:f9eeca106725 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
Kojto 122:f9eeca106725 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
Kojto 122:f9eeca106725 525 DMA_FLAG_FEIF3_7)
Kojto 122:f9eeca106725 526
Kojto 122:f9eeca106725 527 /**
Kojto 122:f9eeca106725 528 * @brief Return the current DMA Stream direct mode error flag.
Kojto 122:f9eeca106725 529 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 530 * @retval The specified direct mode error flag index.
Kojto 122:f9eeca106725 531 */
Kojto 122:f9eeca106725 532 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
Kojto 122:f9eeca106725 533 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
Kojto 122:f9eeca106725 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
Kojto 122:f9eeca106725 535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
Kojto 122:f9eeca106725 536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
Kojto 122:f9eeca106725 537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
Kojto 122:f9eeca106725 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
Kojto 122:f9eeca106725 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
Kojto 122:f9eeca106725 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
Kojto 122:f9eeca106725 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
Kojto 122:f9eeca106725 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
Kojto 122:f9eeca106725 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
Kojto 122:f9eeca106725 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
Kojto 122:f9eeca106725 545 DMA_FLAG_DMEIF3_7)
Kojto 122:f9eeca106725 546
Kojto 122:f9eeca106725 547 /**
Kojto 122:f9eeca106725 548 * @brief Get the DMA Stream pending flags.
Kojto 122:f9eeca106725 549 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 550 * @param __FLAG__: Get the specified flag.
Kojto 122:f9eeca106725 551 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 552 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
Kojto 122:f9eeca106725 553 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
Kojto 122:f9eeca106725 554 * @arg DMA_FLAG_TEIFx: Transfer error flag.
Kojto 122:f9eeca106725 555 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
Kojto 122:f9eeca106725 556 * @arg DMA_FLAG_FEIFx: FIFO error flag.
Kojto 122:f9eeca106725 557 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Kojto 122:f9eeca106725 558 * @retval The state of FLAG (SET or RESET).
Kojto 122:f9eeca106725 559 */
Kojto 122:f9eeca106725 560 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
Kojto 122:f9eeca106725 561 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
Kojto 122:f9eeca106725 562 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
Kojto 122:f9eeca106725 563 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
Kojto 122:f9eeca106725 564
Kojto 122:f9eeca106725 565 /**
Kojto 122:f9eeca106725 566 * @brief Clear the DMA Stream pending flags.
Kojto 122:f9eeca106725 567 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 568 * @param __FLAG__: specifies the flag to clear.
Kojto 122:f9eeca106725 569 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 570 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
Kojto 122:f9eeca106725 571 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
Kojto 122:f9eeca106725 572 * @arg DMA_FLAG_TEIFx: Transfer error flag.
Kojto 122:f9eeca106725 573 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
Kojto 122:f9eeca106725 574 * @arg DMA_FLAG_FEIFx: FIFO error flag.
Kojto 122:f9eeca106725 575 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
Kojto 122:f9eeca106725 576 * @retval None
Kojto 122:f9eeca106725 577 */
Kojto 122:f9eeca106725 578 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
Kojto 122:f9eeca106725 579 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
Kojto 122:f9eeca106725 580 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
Kojto 122:f9eeca106725 581 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
Kojto 122:f9eeca106725 582
Kojto 122:f9eeca106725 583 /**
Kojto 122:f9eeca106725 584 * @brief Enable the specified DMA Stream interrupts.
Kojto 122:f9eeca106725 585 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 586 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 122:f9eeca106725 587 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 588 * @arg DMA_IT_TC: Transfer complete interrupt mask.
Kojto 122:f9eeca106725 589 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
Kojto 122:f9eeca106725 590 * @arg DMA_IT_TE: Transfer error interrupt mask.
Kojto 122:f9eeca106725 591 * @arg DMA_IT_FE: FIFO error interrupt mask.
Kojto 122:f9eeca106725 592 * @arg DMA_IT_DME: Direct mode error interrupt.
Kojto 122:f9eeca106725 593 * @retval None
Kojto 122:f9eeca106725 594 */
Kojto 122:f9eeca106725 595 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
Kojto 122:f9eeca106725 596 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
Kojto 122:f9eeca106725 597
Kojto 122:f9eeca106725 598 /**
Kojto 122:f9eeca106725 599 * @brief Disable the specified DMA Stream interrupts.
Kojto 122:f9eeca106725 600 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 601 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 122:f9eeca106725 602 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 603 * @arg DMA_IT_TC: Transfer complete interrupt mask.
Kojto 122:f9eeca106725 604 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
Kojto 122:f9eeca106725 605 * @arg DMA_IT_TE: Transfer error interrupt mask.
Kojto 122:f9eeca106725 606 * @arg DMA_IT_FE: FIFO error interrupt mask.
Kojto 122:f9eeca106725 607 * @arg DMA_IT_DME: Direct mode error interrupt.
Kojto 122:f9eeca106725 608 * @retval None
Kojto 122:f9eeca106725 609 */
Kojto 122:f9eeca106725 610 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
Kojto 122:f9eeca106725 611 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
Kojto 122:f9eeca106725 612
Kojto 122:f9eeca106725 613 /**
Kojto 122:f9eeca106725 614 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
Kojto 122:f9eeca106725 615 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 616 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
Kojto 122:f9eeca106725 617 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 618 * @arg DMA_IT_TC: Transfer complete interrupt mask.
Kojto 122:f9eeca106725 619 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
Kojto 122:f9eeca106725 620 * @arg DMA_IT_TE: Transfer error interrupt mask.
Kojto 122:f9eeca106725 621 * @arg DMA_IT_FE: FIFO error interrupt mask.
Kojto 122:f9eeca106725 622 * @arg DMA_IT_DME: Direct mode error interrupt.
Kojto 122:f9eeca106725 623 * @retval The state of DMA_IT.
Kojto 122:f9eeca106725 624 */
Kojto 122:f9eeca106725 625 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
Kojto 122:f9eeca106725 626 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
Kojto 122:f9eeca106725 627 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
Kojto 122:f9eeca106725 628
Kojto 122:f9eeca106725 629 /**
Kojto 122:f9eeca106725 630 * @brief Writes the number of data units to be transferred on the DMA Stream.
Kojto 122:f9eeca106725 631 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 632 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
Kojto 122:f9eeca106725 633 * Number of data items depends only on the Peripheral data format.
Kojto 122:f9eeca106725 634 *
Kojto 122:f9eeca106725 635 * @note If Peripheral data format is Bytes: number of data units is equal
Kojto 122:f9eeca106725 636 * to total number of bytes to be transferred.
Kojto 122:f9eeca106725 637 *
Kojto 122:f9eeca106725 638 * @note If Peripheral data format is Half-Word: number of data units is
Kojto 122:f9eeca106725 639 * equal to total number of bytes to be transferred / 2.
Kojto 122:f9eeca106725 640 *
Kojto 122:f9eeca106725 641 * @note If Peripheral data format is Word: number of data units is equal
Kojto 122:f9eeca106725 642 * to total number of bytes to be transferred / 4.
Kojto 122:f9eeca106725 643 *
Kojto 122:f9eeca106725 644 * @retval The number of remaining data units in the current DMAy Streamx transfer.
Kojto 122:f9eeca106725 645 */
Kojto 122:f9eeca106725 646 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
Kojto 122:f9eeca106725 647
Kojto 122:f9eeca106725 648 /**
Kojto 122:f9eeca106725 649 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
Kojto 122:f9eeca106725 650 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 651 *
Kojto 122:f9eeca106725 652 * @retval The number of remaining data units in the current DMA Stream transfer.
Kojto 122:f9eeca106725 653 */
Kojto 122:f9eeca106725 654 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
Kojto 122:f9eeca106725 655
Kojto 122:f9eeca106725 656
Kojto 122:f9eeca106725 657 /* Include DMA HAL Extension module */
Kojto 122:f9eeca106725 658 #include "stm32f4xx_hal_dma_ex.h"
Kojto 122:f9eeca106725 659
Kojto 122:f9eeca106725 660 /* Exported functions --------------------------------------------------------*/
Kojto 122:f9eeca106725 661
Kojto 122:f9eeca106725 662 /** @defgroup DMA_Exported_Functions DMA Exported Functions
Kojto 122:f9eeca106725 663 * @brief DMA Exported functions
Kojto 122:f9eeca106725 664 * @{
Kojto 122:f9eeca106725 665 */
Kojto 122:f9eeca106725 666
Kojto 122:f9eeca106725 667 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 122:f9eeca106725 668 * @brief Initialization and de-initialization functions
Kojto 122:f9eeca106725 669 * @{
Kojto 122:f9eeca106725 670 */
Kojto 122:f9eeca106725 671 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 672 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 673 /**
Kojto 122:f9eeca106725 674 * @}
Kojto 122:f9eeca106725 675 */
Kojto 122:f9eeca106725 676
Kojto 122:f9eeca106725 677 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
Kojto 122:f9eeca106725 678 * @brief I/O operation functions
Kojto 122:f9eeca106725 679 * @{
Kojto 122:f9eeca106725 680 */
Kojto 122:f9eeca106725 681 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 122:f9eeca106725 682 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 122:f9eeca106725 683 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 684 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 685 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
Kojto 122:f9eeca106725 686 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 687 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 688 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
Kojto 122:f9eeca106725 689 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
Kojto 122:f9eeca106725 690
Kojto 122:f9eeca106725 691 /**
Kojto 122:f9eeca106725 692 * @}
Kojto 122:f9eeca106725 693 */
Kojto 122:f9eeca106725 694
Kojto 122:f9eeca106725 695 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
Kojto 122:f9eeca106725 696 * @brief Peripheral State functions
Kojto 122:f9eeca106725 697 * @{
Kojto 122:f9eeca106725 698 */
Kojto 122:f9eeca106725 699 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 700 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 701 /**
Kojto 122:f9eeca106725 702 * @}
Kojto 122:f9eeca106725 703 */
Kojto 122:f9eeca106725 704 /**
Kojto 122:f9eeca106725 705 * @}
Kojto 122:f9eeca106725 706 */
Kojto 122:f9eeca106725 707 /* Private Constants -------------------------------------------------------------*/
Kojto 122:f9eeca106725 708 /** @defgroup DMA_Private_Constants DMA Private Constants
Kojto 122:f9eeca106725 709 * @brief DMA private defines and constants
Kojto 122:f9eeca106725 710 * @{
Kojto 122:f9eeca106725 711 */
Kojto 122:f9eeca106725 712 /**
Kojto 122:f9eeca106725 713 * @}
Kojto 122:f9eeca106725 714 */
Kojto 122:f9eeca106725 715
Kojto 122:f9eeca106725 716 /* Private macros ------------------------------------------------------------*/
Kojto 122:f9eeca106725 717 /** @defgroup DMA_Private_Macros DMA Private Macros
Kojto 122:f9eeca106725 718 * @brief DMA private macros
Kojto 122:f9eeca106725 719 * @{
Kojto 122:f9eeca106725 720 */
AnnaBridge 145:64910690c574 721 #if defined (DMA_SxCR_CHSEL_3)
AnnaBridge 145:64910690c574 722 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
AnnaBridge 145:64910690c574 723 ((CHANNEL) == DMA_CHANNEL_1) || \
AnnaBridge 145:64910690c574 724 ((CHANNEL) == DMA_CHANNEL_2) || \
AnnaBridge 145:64910690c574 725 ((CHANNEL) == DMA_CHANNEL_3) || \
AnnaBridge 145:64910690c574 726 ((CHANNEL) == DMA_CHANNEL_4) || \
AnnaBridge 145:64910690c574 727 ((CHANNEL) == DMA_CHANNEL_5) || \
AnnaBridge 145:64910690c574 728 ((CHANNEL) == DMA_CHANNEL_6) || \
AnnaBridge 145:64910690c574 729 ((CHANNEL) == DMA_CHANNEL_7) || \
AnnaBridge 145:64910690c574 730 ((CHANNEL) == DMA_CHANNEL_8) || \
AnnaBridge 145:64910690c574 731 ((CHANNEL) == DMA_CHANNEL_9) || \
AnnaBridge 145:64910690c574 732 ((CHANNEL) == DMA_CHANNEL_10)|| \
AnnaBridge 145:64910690c574 733 ((CHANNEL) == DMA_CHANNEL_11)|| \
AnnaBridge 145:64910690c574 734 ((CHANNEL) == DMA_CHANNEL_12)|| \
AnnaBridge 145:64910690c574 735 ((CHANNEL) == DMA_CHANNEL_13)|| \
AnnaBridge 145:64910690c574 736 ((CHANNEL) == DMA_CHANNEL_14)|| \
AnnaBridge 145:64910690c574 737 ((CHANNEL) == DMA_CHANNEL_15))
AnnaBridge 145:64910690c574 738 #else
Kojto 122:f9eeca106725 739 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
Kojto 122:f9eeca106725 740 ((CHANNEL) == DMA_CHANNEL_1) || \
Kojto 122:f9eeca106725 741 ((CHANNEL) == DMA_CHANNEL_2) || \
Kojto 122:f9eeca106725 742 ((CHANNEL) == DMA_CHANNEL_3) || \
Kojto 122:f9eeca106725 743 ((CHANNEL) == DMA_CHANNEL_4) || \
Kojto 122:f9eeca106725 744 ((CHANNEL) == DMA_CHANNEL_5) || \
Kojto 122:f9eeca106725 745 ((CHANNEL) == DMA_CHANNEL_6) || \
Kojto 122:f9eeca106725 746 ((CHANNEL) == DMA_CHANNEL_7))
AnnaBridge 145:64910690c574 747 #endif /* DMA_SxCR_CHSEL_3 */
Kojto 122:f9eeca106725 748
Kojto 122:f9eeca106725 749 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
Kojto 122:f9eeca106725 750 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
Kojto 122:f9eeca106725 751 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto 122:f9eeca106725 752
Kojto 122:f9eeca106725 753 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
Kojto 122:f9eeca106725 754
Kojto 122:f9eeca106725 755 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
Kojto 122:f9eeca106725 756 ((STATE) == DMA_PINC_DISABLE))
Kojto 122:f9eeca106725 757
Kojto 122:f9eeca106725 758 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
Kojto 122:f9eeca106725 759 ((STATE) == DMA_MINC_DISABLE))
Kojto 122:f9eeca106725 760
Kojto 122:f9eeca106725 761 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
Kojto 122:f9eeca106725 762 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
Kojto 122:f9eeca106725 763 ((SIZE) == DMA_PDATAALIGN_WORD))
Kojto 122:f9eeca106725 764
Kojto 122:f9eeca106725 765 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
Kojto 122:f9eeca106725 766 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
Kojto 122:f9eeca106725 767 ((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto 122:f9eeca106725 768
Kojto 122:f9eeca106725 769 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
Kojto 122:f9eeca106725 770 ((MODE) == DMA_CIRCULAR) || \
Kojto 122:f9eeca106725 771 ((MODE) == DMA_PFCTRL))
Kojto 122:f9eeca106725 772
Kojto 122:f9eeca106725 773 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
Kojto 122:f9eeca106725 774 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
Kojto 122:f9eeca106725 775 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
Kojto 122:f9eeca106725 776 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto 122:f9eeca106725 777
Kojto 122:f9eeca106725 778 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
Kojto 122:f9eeca106725 779 ((STATE) == DMA_FIFOMODE_ENABLE))
Kojto 122:f9eeca106725 780
Kojto 122:f9eeca106725 781 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
Kojto 122:f9eeca106725 782 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
Kojto 122:f9eeca106725 783 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
Kojto 122:f9eeca106725 784 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
Kojto 122:f9eeca106725 785
Kojto 122:f9eeca106725 786 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
Kojto 122:f9eeca106725 787 ((BURST) == DMA_MBURST_INC4) || \
Kojto 122:f9eeca106725 788 ((BURST) == DMA_MBURST_INC8) || \
Kojto 122:f9eeca106725 789 ((BURST) == DMA_MBURST_INC16))
Kojto 122:f9eeca106725 790
Kojto 122:f9eeca106725 791 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
Kojto 122:f9eeca106725 792 ((BURST) == DMA_PBURST_INC4) || \
Kojto 122:f9eeca106725 793 ((BURST) == DMA_PBURST_INC8) || \
Kojto 122:f9eeca106725 794 ((BURST) == DMA_PBURST_INC16))
Kojto 122:f9eeca106725 795 /**
Kojto 122:f9eeca106725 796 * @}
Kojto 122:f9eeca106725 797 */
Kojto 122:f9eeca106725 798
Kojto 122:f9eeca106725 799 /* Private functions ---------------------------------------------------------*/
Kojto 122:f9eeca106725 800 /** @defgroup DMA_Private_Functions DMA Private Functions
Kojto 122:f9eeca106725 801 * @brief DMA private functions
Kojto 122:f9eeca106725 802 * @{
Kojto 122:f9eeca106725 803 */
Kojto 122:f9eeca106725 804 /**
Kojto 122:f9eeca106725 805 * @}
Kojto 122:f9eeca106725 806 */
Kojto 122:f9eeca106725 807
Kojto 122:f9eeca106725 808 /**
Kojto 122:f9eeca106725 809 * @}
Kojto 122:f9eeca106725 810 */
Kojto 122:f9eeca106725 811
Kojto 122:f9eeca106725 812 /**
Kojto 122:f9eeca106725 813 * @}
Kojto 122:f9eeca106725 814 */
Kojto 122:f9eeca106725 815
Kojto 122:f9eeca106725 816 #ifdef __cplusplus
Kojto 122:f9eeca106725 817 }
Kojto 122:f9eeca106725 818 #endif
Kojto 122:f9eeca106725 819
Kojto 122:f9eeca106725 820 #endif /* __STM32F4xx_HAL_DMA_H */
Kojto 122:f9eeca106725 821
Kojto 122:f9eeca106725 822 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/