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TARGET_WIZWIKI_W7500ECO/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
109:9296ab0bfc11 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 109:9296ab0bfc11 1 /**
Kojto 109:9296ab0bfc11 2 ******************************************************************************
Kojto 109:9296ab0bfc11 3 * @file
Kojto 109:9296ab0bfc11 4 * @author
Kojto 109:9296ab0bfc11 5 * @version
Kojto 109:9296ab0bfc11 6 * @date
Kojto 109:9296ab0bfc11 7 * @brief This file contains all the functions prototypes for the UART
Kojto 109:9296ab0bfc11 8 * firmware library.
Kojto 109:9296ab0bfc11 9 ******************************************************************************
Kojto 109:9296ab0bfc11 10 *
Kojto 109:9296ab0bfc11 11 ******************************************************************************
Kojto 109:9296ab0bfc11 12 */
Kojto 109:9296ab0bfc11 13
Kojto 109:9296ab0bfc11 14 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 109:9296ab0bfc11 15 #ifndef __W7500X_PWM_H
Kojto 109:9296ab0bfc11 16 #define __W7500X_PWM_H
Kojto 109:9296ab0bfc11 17
Kojto 109:9296ab0bfc11 18 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 19 extern "C" {
Kojto 109:9296ab0bfc11 20 #endif
Kojto 109:9296ab0bfc11 21
Kojto 109:9296ab0bfc11 22 /* Includes ------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 23 #include "W7500x.h"
Kojto 109:9296ab0bfc11 24
Kojto 109:9296ab0bfc11 25 /**********************************************************************************************/
Kojto 109:9296ab0bfc11 26 /**********************************************************************************************/
Kojto 109:9296ab0bfc11 27 // This structure and define must be in W7500x.h
Kojto 109:9296ab0bfc11 28 /**********************************************************************************************/
Kojto 109:9296ab0bfc11 29 /**********************************************************************************************/
Kojto 109:9296ab0bfc11 30
Kojto 109:9296ab0bfc11 31 typedef struct
Kojto 109:9296ab0bfc11 32 {
Kojto 109:9296ab0bfc11 33 uint32_t PWM_CHn_PEEER;
Kojto 109:9296ab0bfc11 34 }PWM_CtrlPWMOutputTypeDef;
Kojto 109:9296ab0bfc11 35
Kojto 109:9296ab0bfc11 36 typedef struct
Kojto 109:9296ab0bfc11 37 {
Kojto 109:9296ab0bfc11 38 uint32_t PWM_CHn_PR;
Kojto 109:9296ab0bfc11 39 uint32_t PWM_CHn_MR;
Kojto 109:9296ab0bfc11 40 uint32_t PWM_CHn_LR;
Kojto 109:9296ab0bfc11 41 uint32_t PWM_CHn_UDMR;
Kojto 109:9296ab0bfc11 42 uint32_t PWM_CHn_PDMR;
Kojto 109:9296ab0bfc11 43 uint32_t PWM_CHn_DZCR;
Kojto 109:9296ab0bfc11 44 }PWM_DeadzoneModeInitTypDef;
Kojto 109:9296ab0bfc11 45
Kojto 109:9296ab0bfc11 46 #define IS_PWM_ALL_CH(CHn) ((CHn == PWM_CH0) || \
Kojto 109:9296ab0bfc11 47 (CHn == PWM_CH1) || \
Kojto 109:9296ab0bfc11 48 (CHn == PWM_CH2) || \
Kojto 109:9296ab0bfc11 49 (CHn == PWM_CH3) || \
Kojto 109:9296ab0bfc11 50 (CHn == PWM_CH4) || \
Kojto 109:9296ab0bfc11 51 (CHn == PWM_CH5) || \
Kojto 109:9296ab0bfc11 52 (CHn == PWM_CH6) || \
Kojto 109:9296ab0bfc11 53 (CHn == PWM_CH7))
Kojto 109:9296ab0bfc11 54
Kojto 109:9296ab0bfc11 55 #define PWM_IER_IE0_Enable (0x1ul << 0)
Kojto 109:9296ab0bfc11 56 #define PWM_IER_IE1_Enable (0x1ul << 1)
Kojto 109:9296ab0bfc11 57 #define PWM_IER_IE2_Enable (0x1ul << 2)
Kojto 109:9296ab0bfc11 58 #define PWM_IER_IE3_Enable (0x1ul << 3)
Kojto 109:9296ab0bfc11 59 #define PWM_IER_IE4_Enable (0x1ul << 4)
Kojto 109:9296ab0bfc11 60 #define PWM_IER_IE5_Enable (0x1ul << 5)
Kojto 109:9296ab0bfc11 61 #define PWM_IER_IE6_Enable (0x1ul << 6)
Kojto 109:9296ab0bfc11 62 #define PWM_IER_IE7_Enable (0x1ul << 7)
Kojto 109:9296ab0bfc11 63
Kojto 109:9296ab0bfc11 64 #define PWM_IER_IE0_Disable ~PWM_IER_IE0_Enable
Kojto 109:9296ab0bfc11 65 #define PWM_IER_IE1_Disable ~PWM_IER_IE1_Enable
Kojto 109:9296ab0bfc11 66 #define PWM_IER_IE2_Disable ~PWM_IER_IE2_Enable
Kojto 109:9296ab0bfc11 67 #define PWM_IER_IE3_Disable ~PWM_IER_IE3_Enable
Kojto 109:9296ab0bfc11 68 #define PWM_IER_IE4_Disable ~PWM_IER_IE4_Enable
Kojto 109:9296ab0bfc11 69 #define PWM_IER_IE5_Disable ~PWM_IER_IE5_Enable
Kojto 109:9296ab0bfc11 70 #define PWM_IER_IE6_Disable ~PWM_IER_IE6_Enable
Kojto 109:9296ab0bfc11 71 #define PWM_IER_IE7_Disable ~PWM_IER_IE7_Enable
Kojto 109:9296ab0bfc11 72
Kojto 109:9296ab0bfc11 73 #define PWM_SSR_SS0_Start (0x1ul << 0)
Kojto 109:9296ab0bfc11 74 #define PWM_SSR_SS1_Start (0x1ul << 1)
Kojto 109:9296ab0bfc11 75 #define PWM_SSR_SS2_Start (0x1ul << 2)
Kojto 109:9296ab0bfc11 76 #define PWM_SSR_SS3_Start (0x1ul << 3)
Kojto 109:9296ab0bfc11 77 #define PWM_SSR_SS4_Start (0x1ul << 4)
Kojto 109:9296ab0bfc11 78 #define PWM_SSR_SS5_Start (0x1ul << 5)
Kojto 109:9296ab0bfc11 79 #define PWM_SSR_SS6_Start (0x1ul << 6)
Kojto 109:9296ab0bfc11 80 #define PWM_SSR_SS7_Start (0x1ul << 7)
Kojto 109:9296ab0bfc11 81
Kojto 109:9296ab0bfc11 82 #define PWM_SSR_SS0_Stop ~PWM_SSR_SS0_Start
Kojto 109:9296ab0bfc11 83 #define PWM_SSR_SS1_Stop ~PWM_SSR_SS1_Start
Kojto 109:9296ab0bfc11 84 #define PWM_SSR_SS2_Stop ~PWM_SSR_SS2_Start
Kojto 109:9296ab0bfc11 85 #define PWM_SSR_SS3_Stop ~PWM_SSR_SS3_Start
Kojto 109:9296ab0bfc11 86 #define PWM_SSR_SS4_Stop ~PWM_SSR_SS4_Start
Kojto 109:9296ab0bfc11 87 #define PWM_SSR_SS5_Stop ~PWM_SSR_SS5_Start
Kojto 109:9296ab0bfc11 88 #define PWM_SSR_SS6_Stop ~PWM_SSR_SS6_Start
Kojto 109:9296ab0bfc11 89 #define PWM_SSR_SS7_Stop ~PWM_SSR_SS7_Start
Kojto 109:9296ab0bfc11 90
Kojto 109:9296ab0bfc11 91 #define IS_SSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
Kojto 109:9296ab0bfc11 92
Kojto 109:9296ab0bfc11 93 #define PWM_PSR_PS0_Pause (0x1ul << 0)
Kojto 109:9296ab0bfc11 94 #define PWM_PSR_PS1_Pause (0x1ul << 1)
Kojto 109:9296ab0bfc11 95 #define PWM_PSR_PS2_Pause (0x1ul << 2)
Kojto 109:9296ab0bfc11 96 #define PWM_PSR_PS3_Pause (0x1ul << 3)
Kojto 109:9296ab0bfc11 97 #define PWM_PSR_PS4_Pause (0x1ul << 4)
Kojto 109:9296ab0bfc11 98 #define PWM_PSR_PS5_Pause (0x1ul << 5)
Kojto 109:9296ab0bfc11 99 #define PWM_PSR_PS6_Pause (0x1ul << 6)
Kojto 109:9296ab0bfc11 100 #define PWM_PSR_PS7_Pause (0x1ul << 7)
Kojto 109:9296ab0bfc11 101
Kojto 109:9296ab0bfc11 102 #define PWM_PSR_PS0_Restart ~PWM_PSR_PS0_Pause
Kojto 109:9296ab0bfc11 103 #define PWM_PSR_PS1_Restart ~PWM_PSR_PS1_Pause
Kojto 109:9296ab0bfc11 104 #define PWM_PSR_PS2_Restart ~PWM_PSR_PS2_Pause
Kojto 109:9296ab0bfc11 105 #define PWM_PSR_PS3_Restart ~PWM_PSR_PS3_Pause
Kojto 109:9296ab0bfc11 106 #define PWM_PSR_PS4_Restart ~PWM_PSR_PS4_Pause
Kojto 109:9296ab0bfc11 107 #define PWM_PSR_PS5_Restart ~PWM_PSR_PS5_Pause
Kojto 109:9296ab0bfc11 108 #define PWM_PSR_PS6_Restart ~PWM_PSR_PS6_Pause
Kojto 109:9296ab0bfc11 109 #define PWM_PSR_PS7_Restart ~PWM_PSR_PS7_Pause
Kojto 109:9296ab0bfc11 110
Kojto 109:9296ab0bfc11 111 #define IS_PWM_PSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
Kojto 109:9296ab0bfc11 112
Kojto 109:9296ab0bfc11 113 #define PWM_CHn_IER_MIE (0x1ul << 0) ///< Match Interrupt Enable
Kojto 109:9296ab0bfc11 114 #define PWM_CHn_IER_OIE (0x1ul << 1) ///< Overflow Interrupt Enable
Kojto 109:9296ab0bfc11 115 #define PWM_CHn_IER_CIE (0x1ul << 2) ///< Capture Interrupt Enable
Kojto 109:9296ab0bfc11 116 #define IS_PWM_CHn_IER(FLAG) (FLAG <= 0x7)
Kojto 109:9296ab0bfc11 117
Kojto 109:9296ab0bfc11 118 #define PWM_CHn_IER_MI_Msk (0x1ul << 0) ///< Match Interrupt Enable Mask
Kojto 109:9296ab0bfc11 119 #define PWM_CHn_IER_OI_Msk (0x1ul << 1) ///< Overflow Interrupt Enable Mask
Kojto 109:9296ab0bfc11 120 #define PWM_CHn_IER_CI_Msk (0x1ul << 2) ///< Capture Interrupt Enable Mask
Kojto 109:9296ab0bfc11 121
Kojto 109:9296ab0bfc11 122 #define PWM_CHn_ICR_MatchInterruptClear (0x1ul << 0)
Kojto 109:9296ab0bfc11 123 #define PWM_CHn_ICR_OverflowInterruptClear (0x1ul << 1)
Kojto 109:9296ab0bfc11 124 #define PWM_CHn_ICR_CaptureInterruptClear (0x1ul << 2)
Kojto 109:9296ab0bfc11 125 #define IS_PWM_CHn_IntClearFlag(FLAG) FLAG <= 0x7
Kojto 109:9296ab0bfc11 126
Kojto 109:9296ab0bfc11 127 /*
Kojto 109:9296ab0bfc11 128 #define IS_PWM_STOP(CHn) (((CHn == PWM_CH0) && (PWM->SSR & PWM_SSR_SS0)) || \
Kojto 109:9296ab0bfc11 129 ((CHn == PWM_CH1) && (PWM->SSR & PWM_SSR_SS1)) || \
Kojto 109:9296ab0bfc11 130 ((CHn == PWM_CH2) && (PWM->SSR & PWM_SSR_SS2)) || \
Kojto 109:9296ab0bfc11 131 ((CHn == PWM_CH3) && (PWM->SSR & PWM_SSR_SS3)) || \
Kojto 109:9296ab0bfc11 132 ((CHn == PWM_CH4) && (PWM->SSR & PWM_SSR_SS4)) || \
Kojto 109:9296ab0bfc11 133 ((CHn == PWM_CH5) && (PWM->SSR & PWM_SSR_SS5)) || \
Kojto 109:9296ab0bfc11 134 ((CHn == PWM_CH6) && (PWM->SSR & PWM_SSR_SS6)) || \
Kojto 109:9296ab0bfc11 135 ((CHn == PWM_CH7) && (PWM->SSR & PWM_SSR_SS7)))
Kojto 109:9296ab0bfc11 136 */
Kojto 109:9296ab0bfc11 137
Kojto 109:9296ab0bfc11 138
Kojto 109:9296ab0bfc11 139 #define IS_PWM_PR_FILTER(MAXVAL) (MAXVAL <= 0x1F)
Kojto 109:9296ab0bfc11 140
Kojto 109:9296ab0bfc11 141
Kojto 109:9296ab0bfc11 142 #define PWM_CHn_UDMR_UpCount (0x0ul)
Kojto 109:9296ab0bfc11 143 #define PWM_CHn_UDMR_DownCount (0x1ul)
Kojto 109:9296ab0bfc11 144 #define IS_PWM_CHn_UDMR(MODE) ((MODE == PWM_CHn_UDMR_UpCount) || \
Kojto 109:9296ab0bfc11 145 (MODE == PWM_CHn_UDMR_DownCount))
Kojto 109:9296ab0bfc11 146
Kojto 109:9296ab0bfc11 147 #define PWM_CHn_TCMR_TimerMode (0x0ul)
Kojto 109:9296ab0bfc11 148 #define PWM_CHn_TCMR_RisingCounterMode (0x1ul)
Kojto 109:9296ab0bfc11 149 #define PWM_CHn_TCMR_FallingCounterMode (0x2ul)
Kojto 109:9296ab0bfc11 150 #define PWM_CHn_TCMR_BothCounterMode (0x3ul)
Kojto 109:9296ab0bfc11 151 #define IS_PWM_CHn_TCMR(MODE) ((MODE == PWM_CHn_TCMR_RisingCounterMode) || \
Kojto 109:9296ab0bfc11 152 (MODE == PWM_CHn_TCMR_FallingCounterMode) || \
Kojto 109:9296ab0bfc11 153 (MODE == PWM_CHn_TCMR_BothCounterMode))
Kojto 109:9296ab0bfc11 154
Kojto 109:9296ab0bfc11 155 #define PWM_CHn_PEEER_Disable (0x0ul)
Kojto 109:9296ab0bfc11 156 #define PWM_CHn_PEEER_ExtEnable (0x1ul)
Kojto 109:9296ab0bfc11 157 #define PWM_CHn_PEEER_PWMEnable (0x2ul)
Kojto 109:9296ab0bfc11 158 #define IS_PWM_CHn_PEEER(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
Kojto 109:9296ab0bfc11 159 (ENABLE == PWM_CHn_PEEER_ExtEnable) || \
Kojto 109:9296ab0bfc11 160 (ENABLE == PWM_CHn_PEEER_PWMEnable))
Kojto 109:9296ab0bfc11 161
Kojto 109:9296ab0bfc11 162 #define IS_PWM_Output(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
Kojto 109:9296ab0bfc11 163 (ENABLE == PWM_CHn_PEEER_PWMEnable))
Kojto 109:9296ab0bfc11 164
Kojto 109:9296ab0bfc11 165 #define PWM_CHn_CMR_RisingEdge 0x0ul
Kojto 109:9296ab0bfc11 166 #define PWM_CHn_CMR_FallingEdge 0x1ul
Kojto 109:9296ab0bfc11 167 #define IS_PWM_CHn_CMR(MODE) ((MODE == PWM_CHn_CMR_RisingEdge) || \
Kojto 109:9296ab0bfc11 168 (MODE == PWM_CHn_CMR_FallingEdge))
Kojto 109:9296ab0bfc11 169
Kojto 109:9296ab0bfc11 170 #define PWM_CHn_PDMR_Oneshot (0x0ul)
Kojto 109:9296ab0bfc11 171 #define PWM_CHn_PDMR_Periodic (0x1ul)
Kojto 109:9296ab0bfc11 172 #define IS_PWM_CHn_PDMR(MODE) ((MODE == PWM_CHn_PDMR_Periodic) || \
Kojto 109:9296ab0bfc11 173 (MODE == PWM_CHn_PDMR_Oneshot))
Kojto 109:9296ab0bfc11 174
Kojto 109:9296ab0bfc11 175 #define PWM_CHn_DZER_Enable (0x1ul)
Kojto 109:9296ab0bfc11 176 #define PWM_CHn_DZER_Disable (0x0ul)
Kojto 109:9296ab0bfc11 177 #define PWM_CHn_DZER(ENABLE) ((ENABLE == PWM_CHn_DZER_Enable) || \
Kojto 109:9296ab0bfc11 178 (ENABLE == PWM_CHn_DZER_Disable))
Kojto 109:9296ab0bfc11 179
Kojto 109:9296ab0bfc11 180 #define IS_PWM_Deadznoe(CHn) (((CHn == PWM_CH0) && (PWM_CH1->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 109:9296ab0bfc11 181 ((CHn == PWM_CH1) && (PWM_CH0->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 109:9296ab0bfc11 182 ((CHn == PWM_CH2) && (PWM_CH3->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 109:9296ab0bfc11 183 ((CHn == PWM_CH3) && (PWM_CH2->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 109:9296ab0bfc11 184 ((CHn == PWM_CH4) && (PWM_CH5->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 109:9296ab0bfc11 185 ((CHn == PWM_CH5) && (PWM_CH4->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 109:9296ab0bfc11 186 ((CHn == PWM_CH6) && (PWM_CH7->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 109:9296ab0bfc11 187 ((CHn == PWM_CH7) && (PWM_CH6->DZER == PWM_CHn_DZER_Disable)))
Kojto 109:9296ab0bfc11 188
Kojto 109:9296ab0bfc11 189 #define IS_PWM_CHn_DZCR_FILTER(MAXVAL) (MAXVAL <= 0x3FF)
Kojto 109:9296ab0bfc11 190
Kojto 109:9296ab0bfc11 191
Kojto 109:9296ab0bfc11 192
Kojto 109:9296ab0bfc11 193
Kojto 109:9296ab0bfc11 194
Kojto 109:9296ab0bfc11 195
Kojto 109:9296ab0bfc11 196 void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 197 void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct);
Kojto 109:9296ab0bfc11 198 void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct);
Kojto 109:9296ab0bfc11 199 void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct);
Kojto 109:9296ab0bfc11 200 void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct);
Kojto 109:9296ab0bfc11 201 void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable );
Kojto 109:9296ab0bfc11 202 void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) ;
Kojto 109:9296ab0bfc11 203 void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) ;
Kojto 109:9296ab0bfc11 204 void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state);
Kojto 109:9296ab0bfc11 205 FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 206 void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state);
Kojto 109:9296ab0bfc11 207 void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 208 void PWM_Multi_Start(uint32_t ssr_bit_flag);
Kojto 109:9296ab0bfc11 209 void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 210 void PWM_Multi_Stop(uint32_t ssr_bit_flag);
Kojto 109:9296ab0bfc11 211 void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 212 void PWM_Multi_Pause(uint32_t psr_bit_flag);
Kojto 109:9296ab0bfc11 213 void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 214 void PWM_Multi_Restart(uint32_t psr_bit_flag);
Kojto 109:9296ab0bfc11 215 uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 216 uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 217 void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR);
Kojto 109:9296ab0bfc11 218 uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 219 uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 220 uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 221 void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR);
Kojto 109:9296ab0bfc11 222 uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 223 void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR);
Kojto 109:9296ab0bfc11 224 uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 225 void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR);
Kojto 109:9296ab0bfc11 226 uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 227 void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR);
Kojto 109:9296ab0bfc11 228 uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 229 void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR);
Kojto 109:9296ab0bfc11 230 uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 231 void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER);
Kojto 109:9296ab0bfc11 232 uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 233 void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR);
Kojto 109:9296ab0bfc11 234 uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 235 uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 236 void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR);
Kojto 109:9296ab0bfc11 237 void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER);
Kojto 109:9296ab0bfc11 238 uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 109:9296ab0bfc11 239 void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR);
Kojto 109:9296ab0bfc11 240 void PWM_CH0_ClearMatchInt(void);
Kojto 109:9296ab0bfc11 241 void PWM_CH0_ClearOverflowInt(void);
Kojto 109:9296ab0bfc11 242 void PWM_CH0_ClearCaptureInt(void);
Kojto 109:9296ab0bfc11 243 void PWM_CH1_ClearMatchInt(void);
Kojto 109:9296ab0bfc11 244 void PWM_CH1_ClearOverflowInt(void);
Kojto 109:9296ab0bfc11 245 void PWM_CH1_ClearCaptureInt(void);
Kojto 109:9296ab0bfc11 246 void PWM_CH2_ClearMatchInt(void);
Kojto 109:9296ab0bfc11 247 void PWM_CH2_ClearOverflowInt(void);
Kojto 109:9296ab0bfc11 248 void PWM_CH2_ClearCaptureInt(void);
Kojto 109:9296ab0bfc11 249 void PWM_CH3_ClearMatchInt(void);
Kojto 109:9296ab0bfc11 250 void PWM_CH3_ClearOverflowInt(void);
Kojto 109:9296ab0bfc11 251 void PWM_CH3_ClearCaptureInt(void);
Kojto 109:9296ab0bfc11 252 void PWM_CH4_ClearMatchInt(void);
Kojto 109:9296ab0bfc11 253 void PWM_CH4_ClearOverflowInt(void);
Kojto 109:9296ab0bfc11 254 void PWM_CH4_ClearCaptureInt(void);
Kojto 109:9296ab0bfc11 255 void PWM_CH5_ClearMatchInt(void);
Kojto 109:9296ab0bfc11 256 void PWM_CH5_ClearOverflowInt(void);
Kojto 109:9296ab0bfc11 257 void PWM_CH5_ClearCaptureInt(void);
Kojto 109:9296ab0bfc11 258 void PWM_CH6_ClearMatchInt(void);
Kojto 109:9296ab0bfc11 259 void PWM_CH6_ClearOverflowInt(void);
Kojto 109:9296ab0bfc11 260 void PWM_CH6_ClearCaptureInt(void);
Kojto 109:9296ab0bfc11 261 void PWM_CH7_ClearMatchInt(void);
Kojto 109:9296ab0bfc11 262 void PWM_CH7_ClearOverflowInt(void);
Kojto 109:9296ab0bfc11 263 void PWM_CH7_ClearCaptureInt(void);
Kojto 109:9296ab0bfc11 264
Kojto 109:9296ab0bfc11 265
Kojto 109:9296ab0bfc11 266 void PWM0_Handler(void);
Kojto 109:9296ab0bfc11 267 void PWM1_Handler(void);
Kojto 109:9296ab0bfc11 268 void PWM2_Handler(void);
Kojto 109:9296ab0bfc11 269 void PWM3_Handler(void);
Kojto 109:9296ab0bfc11 270 void PWM4_Handler(void);
Kojto 109:9296ab0bfc11 271 void PWM5_Handler(void);
Kojto 109:9296ab0bfc11 272 void PWM6_Handler(void);
Kojto 109:9296ab0bfc11 273 void PWM7_Handler(void);
Kojto 109:9296ab0bfc11 274
Kojto 109:9296ab0bfc11 275
Kojto 109:9296ab0bfc11 276
Kojto 109:9296ab0bfc11 277
Kojto 109:9296ab0bfc11 278 //Temporary macro=======
Kojto 109:9296ab0bfc11 279 #define PWM_CH(N) ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + (N * 0x100UL)))
Kojto 109:9296ab0bfc11 280 //======================
Kojto 109:9296ab0bfc11 281
Kojto 109:9296ab0bfc11 282
Kojto 109:9296ab0bfc11 283 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 284 }
Kojto 109:9296ab0bfc11 285 #endif
Kojto 109:9296ab0bfc11 286
Kojto 109:9296ab0bfc11 287
Kojto 109:9296ab0bfc11 288 #endif //__W7500X_PWM_H
Kojto 109:9296ab0bfc11 289