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TARGET_VK_RZ_A1H/irq_ctrl.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
165:d1b4690b3f8b 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 165:d1b4690b3f8b 1 /**************************************************************************//**
AnnaBridge 165:d1b4690b3f8b 2 * @file irq_ctrl.h
AnnaBridge 165:d1b4690b3f8b 3 * @brief Interrupt Controller API header file
AnnaBridge 165:d1b4690b3f8b 4 * @version V1.0.0
AnnaBridge 165:d1b4690b3f8b 5 * @date 23. June 2017
AnnaBridge 165:d1b4690b3f8b 6 ******************************************************************************/
AnnaBridge 165:d1b4690b3f8b 7 /*
AnnaBridge 165:d1b4690b3f8b 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
AnnaBridge 165:d1b4690b3f8b 9 *
AnnaBridge 165:d1b4690b3f8b 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 165:d1b4690b3f8b 11 *
AnnaBridge 165:d1b4690b3f8b 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 165:d1b4690b3f8b 13 * not use this file except in compliance with the License.
AnnaBridge 165:d1b4690b3f8b 14 * You may obtain a copy of the License at
AnnaBridge 165:d1b4690b3f8b 15 *
AnnaBridge 165:d1b4690b3f8b 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 165:d1b4690b3f8b 17 *
AnnaBridge 165:d1b4690b3f8b 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 165:d1b4690b3f8b 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 165:d1b4690b3f8b 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 165:d1b4690b3f8b 21 * See the License for the specific language governing permissions and
AnnaBridge 165:d1b4690b3f8b 22 * limitations under the License.
AnnaBridge 165:d1b4690b3f8b 23 */
AnnaBridge 165:d1b4690b3f8b 24
Anna Bridge 169:a7c7b631e539 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
Anna Bridge 169:a7c7b631e539 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 169:a7c7b631e539 29 #endif
Anna Bridge 169:a7c7b631e539 30
AnnaBridge 165:d1b4690b3f8b 31 #ifndef IRQ_CTRL_H_
AnnaBridge 165:d1b4690b3f8b 32 #define IRQ_CTRL_H_
AnnaBridge 165:d1b4690b3f8b 33
AnnaBridge 165:d1b4690b3f8b 34 #include <stdint.h>
AnnaBridge 165:d1b4690b3f8b 35
AnnaBridge 165:d1b4690b3f8b 36 #ifndef IRQHANDLER_T
AnnaBridge 165:d1b4690b3f8b 37 #define IRQHANDLER_T
AnnaBridge 165:d1b4690b3f8b 38 /// Interrupt handler data type
AnnaBridge 165:d1b4690b3f8b 39 typedef void (*IRQHandler_t) (void);
AnnaBridge 165:d1b4690b3f8b 40 #endif
AnnaBridge 165:d1b4690b3f8b 41
AnnaBridge 165:d1b4690b3f8b 42 #ifndef IRQN_ID_T
AnnaBridge 165:d1b4690b3f8b 43 #define IRQN_ID_T
AnnaBridge 165:d1b4690b3f8b 44 /// Interrupt ID number data type
AnnaBridge 165:d1b4690b3f8b 45 typedef int32_t IRQn_ID_t;
AnnaBridge 165:d1b4690b3f8b 46 #endif
AnnaBridge 165:d1b4690b3f8b 47
AnnaBridge 165:d1b4690b3f8b 48 /* Interrupt mode bit-masks */
AnnaBridge 165:d1b4690b3f8b 49 #define IRQ_MODE_TRIG_Pos (0U)
AnnaBridge 165:d1b4690b3f8b 50 #define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
AnnaBridge 165:d1b4690b3f8b 51 #define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
AnnaBridge 165:d1b4690b3f8b 52 #define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
AnnaBridge 165:d1b4690b3f8b 53 #define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
AnnaBridge 165:d1b4690b3f8b 54 #define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
AnnaBridge 165:d1b4690b3f8b 55 #define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
AnnaBridge 165:d1b4690b3f8b 56 #define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
AnnaBridge 165:d1b4690b3f8b 57 #define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
AnnaBridge 165:d1b4690b3f8b 58
AnnaBridge 165:d1b4690b3f8b 59 #define IRQ_MODE_TYPE_Pos (3U)
AnnaBridge 165:d1b4690b3f8b 60 #define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)
AnnaBridge 165:d1b4690b3f8b 61 #define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line
AnnaBridge 165:d1b4690b3f8b 62 #define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line
AnnaBridge 165:d1b4690b3f8b 63
AnnaBridge 165:d1b4690b3f8b 64 #define IRQ_MODE_DOMAIN_Pos (4U)
AnnaBridge 165:d1b4690b3f8b 65 #define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)
AnnaBridge 165:d1b4690b3f8b 66 #define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain
AnnaBridge 165:d1b4690b3f8b 67 #define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain
AnnaBridge 165:d1b4690b3f8b 68
AnnaBridge 165:d1b4690b3f8b 69 #define IRQ_MODE_CPU_Pos (5U)
AnnaBridge 165:d1b4690b3f8b 70 #define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)
AnnaBridge 165:d1b4690b3f8b 71 #define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs
AnnaBridge 165:d1b4690b3f8b 72 #define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0
AnnaBridge 165:d1b4690b3f8b 73 #define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1
AnnaBridge 165:d1b4690b3f8b 74 #define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2
AnnaBridge 165:d1b4690b3f8b 75 #define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3
AnnaBridge 165:d1b4690b3f8b 76 #define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4
AnnaBridge 165:d1b4690b3f8b 77 #define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5
AnnaBridge 165:d1b4690b3f8b 78 #define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6
AnnaBridge 165:d1b4690b3f8b 79 #define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7
AnnaBridge 165:d1b4690b3f8b 80
AnnaBridge 165:d1b4690b3f8b 81 #define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error
AnnaBridge 165:d1b4690b3f8b 82
AnnaBridge 165:d1b4690b3f8b 83 /* Interrupt priority bit-masks */
AnnaBridge 165:d1b4690b3f8b 84 #define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask
AnnaBridge 165:d1b4690b3f8b 85 #define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error
AnnaBridge 165:d1b4690b3f8b 86
AnnaBridge 165:d1b4690b3f8b 87 /// Initialize interrupt controller.
AnnaBridge 165:d1b4690b3f8b 88 /// \return 0 on success, -1 on error.
AnnaBridge 165:d1b4690b3f8b 89 int32_t IRQ_Initialize (void);
AnnaBridge 165:d1b4690b3f8b 90
AnnaBridge 165:d1b4690b3f8b 91 /// Register interrupt handler.
AnnaBridge 165:d1b4690b3f8b 92 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 93 /// \param[in] handler interrupt handler function address
AnnaBridge 165:d1b4690b3f8b 94 /// \return 0 on success, -1 on error.
AnnaBridge 165:d1b4690b3f8b 95 int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
AnnaBridge 165:d1b4690b3f8b 96
AnnaBridge 165:d1b4690b3f8b 97 /// Get the registered interrupt handler.
AnnaBridge 165:d1b4690b3f8b 98 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 99 /// \return registered interrupt handler function address.
AnnaBridge 165:d1b4690b3f8b 100 IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
AnnaBridge 165:d1b4690b3f8b 101
AnnaBridge 165:d1b4690b3f8b 102 /// Enable interrupt.
AnnaBridge 165:d1b4690b3f8b 103 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 104 /// \return 0 on success, -1 on error.
AnnaBridge 165:d1b4690b3f8b 105 int32_t IRQ_Enable (IRQn_ID_t irqn);
AnnaBridge 165:d1b4690b3f8b 106
AnnaBridge 165:d1b4690b3f8b 107 /// Disable interrupt.
AnnaBridge 165:d1b4690b3f8b 108 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 109 /// \return 0 on success, -1 on error.
AnnaBridge 165:d1b4690b3f8b 110 int32_t IRQ_Disable (IRQn_ID_t irqn);
AnnaBridge 165:d1b4690b3f8b 111
AnnaBridge 165:d1b4690b3f8b 112 /// Get interrupt enable state.
AnnaBridge 165:d1b4690b3f8b 113 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 114 /// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
AnnaBridge 165:d1b4690b3f8b 115 uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
AnnaBridge 165:d1b4690b3f8b 116
AnnaBridge 165:d1b4690b3f8b 117 /// Configure interrupt request mode.
AnnaBridge 165:d1b4690b3f8b 118 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 119 /// \param[in] mode mode configuration
AnnaBridge 165:d1b4690b3f8b 120 /// \return 0 on success, -1 on error.
AnnaBridge 165:d1b4690b3f8b 121 int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
AnnaBridge 165:d1b4690b3f8b 122
AnnaBridge 165:d1b4690b3f8b 123 /// Get interrupt mode configuration.
AnnaBridge 165:d1b4690b3f8b 124 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 125 /// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
AnnaBridge 165:d1b4690b3f8b 126 uint32_t IRQ_GetMode (IRQn_ID_t irqn);
AnnaBridge 165:d1b4690b3f8b 127
AnnaBridge 165:d1b4690b3f8b 128 /// Get ID number of current interrupt request (IRQ).
AnnaBridge 165:d1b4690b3f8b 129 /// \return interrupt ID number.
AnnaBridge 165:d1b4690b3f8b 130 IRQn_ID_t IRQ_GetActiveIRQ (void);
AnnaBridge 165:d1b4690b3f8b 131
AnnaBridge 165:d1b4690b3f8b 132 /// Get ID number of current fast interrupt request (FIQ).
AnnaBridge 165:d1b4690b3f8b 133 /// \return interrupt ID number.
AnnaBridge 165:d1b4690b3f8b 134 IRQn_ID_t IRQ_GetActiveFIQ (void);
AnnaBridge 165:d1b4690b3f8b 135
AnnaBridge 165:d1b4690b3f8b 136 /// Signal end of interrupt processing.
AnnaBridge 165:d1b4690b3f8b 137 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 138 /// \return 0 on success, -1 on error.
AnnaBridge 165:d1b4690b3f8b 139 int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
AnnaBridge 165:d1b4690b3f8b 140
AnnaBridge 165:d1b4690b3f8b 141 /// Set interrupt pending flag.
AnnaBridge 165:d1b4690b3f8b 142 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 143 /// \return 0 on success, -1 on error.
AnnaBridge 165:d1b4690b3f8b 144 int32_t IRQ_SetPending (IRQn_ID_t irqn);
AnnaBridge 165:d1b4690b3f8b 145
AnnaBridge 165:d1b4690b3f8b 146 /// Get interrupt pending flag.
AnnaBridge 165:d1b4690b3f8b 147 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 148 /// \return 0 - interrupt is not pending, 1 - interrupt is pending.
AnnaBridge 165:d1b4690b3f8b 149 uint32_t IRQ_GetPending (IRQn_ID_t irqn);
AnnaBridge 165:d1b4690b3f8b 150
AnnaBridge 165:d1b4690b3f8b 151 /// Clear interrupt pending flag.
AnnaBridge 165:d1b4690b3f8b 152 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 153 /// \return 0 on success, -1 on error.
AnnaBridge 165:d1b4690b3f8b 154 int32_t IRQ_ClearPending (IRQn_ID_t irqn);
AnnaBridge 165:d1b4690b3f8b 155
AnnaBridge 165:d1b4690b3f8b 156 /// Set interrupt priority value.
AnnaBridge 165:d1b4690b3f8b 157 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 158 /// \param[in] priority interrupt priority value
AnnaBridge 165:d1b4690b3f8b 159 /// \return 0 on success, -1 on error.
AnnaBridge 165:d1b4690b3f8b 160 int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
AnnaBridge 165:d1b4690b3f8b 161
AnnaBridge 165:d1b4690b3f8b 162 /// Get interrupt priority.
AnnaBridge 165:d1b4690b3f8b 163 /// \param[in] irqn interrupt ID number
AnnaBridge 165:d1b4690b3f8b 164 /// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
AnnaBridge 165:d1b4690b3f8b 165 uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
AnnaBridge 165:d1b4690b3f8b 166
AnnaBridge 165:d1b4690b3f8b 167 /// Set priority masking threshold.
AnnaBridge 165:d1b4690b3f8b 168 /// \param[in] priority priority masking threshold value
AnnaBridge 165:d1b4690b3f8b 169 /// \return 0 on success, -1 on error.
AnnaBridge 165:d1b4690b3f8b 170 int32_t IRQ_SetPriorityMask (uint32_t priority);
AnnaBridge 165:d1b4690b3f8b 171
AnnaBridge 165:d1b4690b3f8b 172 /// Get priority masking threshold
AnnaBridge 165:d1b4690b3f8b 173 /// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
AnnaBridge 165:d1b4690b3f8b 174 uint32_t IRQ_GetPriorityMask (void);
AnnaBridge 165:d1b4690b3f8b 175
AnnaBridge 165:d1b4690b3f8b 176 /// Set priority grouping field split point
AnnaBridge 165:d1b4690b3f8b 177 /// \param[in] bits number of MSB bits included in the group priority field comparison
AnnaBridge 165:d1b4690b3f8b 178 /// \return 0 on success, -1 on error.
AnnaBridge 165:d1b4690b3f8b 179 int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
AnnaBridge 165:d1b4690b3f8b 180
AnnaBridge 165:d1b4690b3f8b 181 /// Get priority grouping field split point
AnnaBridge 165:d1b4690b3f8b 182 /// \return current number of MSB bits included in the group priority field comparison with
AnnaBridge 165:d1b4690b3f8b 183 /// optional IRQ_PRIORITY_ERROR bit set.
AnnaBridge 165:d1b4690b3f8b 184 uint32_t IRQ_GetPriorityGroupBits (void);
AnnaBridge 165:d1b4690b3f8b 185
AnnaBridge 165:d1b4690b3f8b 186 #endif // IRQ_CTRL_H_