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TARGET_USI_WM_BN_BM_22/core_cm0.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
167:84c0a372a020 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /**************************************************************************//**
AnnaBridge 167:84c0a372a020 2 * @file core_cm0.h
AnnaBridge 167:84c0a372a020 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.3
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
AnnaBridge 167:84c0a372a020 6 ******************************************************************************/
AnnaBridge 167:84c0a372a020 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 167:84c0a372a020 9 *
AnnaBridge 167:84c0a372a020 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 167:84c0a372a020 11 *
AnnaBridge 167:84c0a372a020 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 167:84c0a372a020 13 * not use this file except in compliance with the License.
AnnaBridge 167:84c0a372a020 14 * You may obtain a copy of the License at
AnnaBridge 167:84c0a372a020 15 *
AnnaBridge 167:84c0a372a020 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 167:84c0a372a020 17 *
AnnaBridge 167:84c0a372a020 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:84c0a372a020 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 167:84c0a372a020 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:84c0a372a020 21 * See the License for the specific language governing permissions and
AnnaBridge 167:84c0a372a020 22 * limitations under the License.
AnnaBridge 167:84c0a372a020 23 */
AnnaBridge 167:84c0a372a020 24
AnnaBridge 167:84c0a372a020 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
AnnaBridge 167:84c0a372a020 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 167:84c0a372a020 29 #endif
AnnaBridge 167:84c0a372a020 30
AnnaBridge 167:84c0a372a020 31 #ifndef __CORE_CM0_H_GENERIC
AnnaBridge 167:84c0a372a020 32 #define __CORE_CM0_H_GENERIC
AnnaBridge 167:84c0a372a020 33
AnnaBridge 167:84c0a372a020 34 #include <stdint.h>
AnnaBridge 167:84c0a372a020 35
AnnaBridge 167:84c0a372a020 36 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 37 extern "C" {
AnnaBridge 167:84c0a372a020 38 #endif
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 /**
AnnaBridge 167:84c0a372a020 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 167:84c0a372a020 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 167:84c0a372a020 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 167:84c0a372a020 46
AnnaBridge 167:84c0a372a020 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 167:84c0a372a020 48 Unions are used for effective representation of core registers.
AnnaBridge 167:84c0a372a020 49
AnnaBridge 167:84c0a372a020 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 167:84c0a372a020 51 Function-like macros are used to allow more efficient code.
AnnaBridge 167:84c0a372a020 52 */
AnnaBridge 167:84c0a372a020 53
AnnaBridge 167:84c0a372a020 54
AnnaBridge 167:84c0a372a020 55 /*******************************************************************************
AnnaBridge 167:84c0a372a020 56 * CMSIS definitions
AnnaBridge 167:84c0a372a020 57 ******************************************************************************/
AnnaBridge 167:84c0a372a020 58 /**
AnnaBridge 167:84c0a372a020 59 \ingroup Cortex_M0
AnnaBridge 167:84c0a372a020 60 @{
AnnaBridge 167:84c0a372a020 61 */
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 #include "cmsis_version.h"
AnnaBridge 167:84c0a372a020 64
AnnaBridge 167:84c0a372a020 65 /* CMSIS CM0 definitions */
AnnaBridge 167:84c0a372a020 66 #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
AnnaBridge 167:84c0a372a020 67 #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 167:84c0a372a020 68 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 167:84c0a372a020 69 __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 167:84c0a372a020 70
AnnaBridge 167:84c0a372a020 71 #define __CORTEX_M (0U) /*!< Cortex-M Core */
AnnaBridge 167:84c0a372a020 72
AnnaBridge 167:84c0a372a020 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 167:84c0a372a020 74 This core does not support an FPU at all
AnnaBridge 167:84c0a372a020 75 */
AnnaBridge 167:84c0a372a020 76 #define __FPU_USED 0U
AnnaBridge 167:84c0a372a020 77
AnnaBridge 167:84c0a372a020 78 #if defined ( __CC_ARM )
AnnaBridge 167:84c0a372a020 79 #if defined __TARGET_FPU_VFP
AnnaBridge 167:84c0a372a020 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 81 #endif
AnnaBridge 167:84c0a372a020 82
AnnaBridge 167:84c0a372a020 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 167:84c0a372a020 84 #if defined __ARM_PCS_VFP
AnnaBridge 167:84c0a372a020 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 86 #endif
AnnaBridge 167:84c0a372a020 87
AnnaBridge 167:84c0a372a020 88 #elif defined ( __GNUC__ )
AnnaBridge 167:84c0a372a020 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 167:84c0a372a020 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 91 #endif
AnnaBridge 167:84c0a372a020 92
AnnaBridge 167:84c0a372a020 93 #elif defined ( __ICCARM__ )
AnnaBridge 167:84c0a372a020 94 #if defined __ARMVFP__
AnnaBridge 167:84c0a372a020 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 96 #endif
AnnaBridge 167:84c0a372a020 97
AnnaBridge 167:84c0a372a020 98 #elif defined ( __TI_ARM__ )
AnnaBridge 167:84c0a372a020 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 167:84c0a372a020 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 101 #endif
AnnaBridge 167:84c0a372a020 102
AnnaBridge 167:84c0a372a020 103 #elif defined ( __TASKING__ )
AnnaBridge 167:84c0a372a020 104 #if defined __FPU_VFP__
AnnaBridge 167:84c0a372a020 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 106 #endif
AnnaBridge 167:84c0a372a020 107
AnnaBridge 167:84c0a372a020 108 #elif defined ( __CSMC__ )
AnnaBridge 167:84c0a372a020 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 167:84c0a372a020 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 111 #endif
AnnaBridge 167:84c0a372a020 112
AnnaBridge 167:84c0a372a020 113 #endif
AnnaBridge 167:84c0a372a020 114
AnnaBridge 167:84c0a372a020 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 167:84c0a372a020 116
AnnaBridge 167:84c0a372a020 117
AnnaBridge 167:84c0a372a020 118 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 119 }
AnnaBridge 167:84c0a372a020 120 #endif
AnnaBridge 167:84c0a372a020 121
AnnaBridge 167:84c0a372a020 122 #endif /* __CORE_CM0_H_GENERIC */
AnnaBridge 167:84c0a372a020 123
AnnaBridge 167:84c0a372a020 124 #ifndef __CMSIS_GENERIC
AnnaBridge 167:84c0a372a020 125
AnnaBridge 167:84c0a372a020 126 #ifndef __CORE_CM0_H_DEPENDANT
AnnaBridge 167:84c0a372a020 127 #define __CORE_CM0_H_DEPENDANT
AnnaBridge 167:84c0a372a020 128
AnnaBridge 167:84c0a372a020 129 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 130 extern "C" {
AnnaBridge 167:84c0a372a020 131 #endif
AnnaBridge 167:84c0a372a020 132
AnnaBridge 167:84c0a372a020 133 /* check device defines and use defaults */
AnnaBridge 167:84c0a372a020 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 167:84c0a372a020 135 #ifndef __CM0_REV
AnnaBridge 167:84c0a372a020 136 #define __CM0_REV 0x0000U
AnnaBridge 167:84c0a372a020 137 #warning "__CM0_REV not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 138 #endif
AnnaBridge 167:84c0a372a020 139
AnnaBridge 167:84c0a372a020 140 #ifndef __NVIC_PRIO_BITS
AnnaBridge 167:84c0a372a020 141 #define __NVIC_PRIO_BITS 2U
AnnaBridge 167:84c0a372a020 142 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 143 #endif
AnnaBridge 167:84c0a372a020 144
AnnaBridge 167:84c0a372a020 145 #ifndef __Vendor_SysTickConfig
AnnaBridge 167:84c0a372a020 146 #define __Vendor_SysTickConfig 0U
AnnaBridge 167:84c0a372a020 147 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 148 #endif
AnnaBridge 167:84c0a372a020 149 #endif
AnnaBridge 167:84c0a372a020 150
AnnaBridge 167:84c0a372a020 151 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 167:84c0a372a020 152 /**
AnnaBridge 167:84c0a372a020 153 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 167:84c0a372a020 154
AnnaBridge 167:84c0a372a020 155 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 167:84c0a372a020 156 \li to specify the access to peripheral variables.
AnnaBridge 167:84c0a372a020 157 \li for automatic generation of peripheral register debug information.
AnnaBridge 167:84c0a372a020 158 */
AnnaBridge 167:84c0a372a020 159 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 160 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 167:84c0a372a020 161 #else
AnnaBridge 167:84c0a372a020 162 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 167:84c0a372a020 163 #endif
AnnaBridge 167:84c0a372a020 164 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 167:84c0a372a020 165 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 167:84c0a372a020 166
AnnaBridge 167:84c0a372a020 167 /* following defines should be used for structure members */
AnnaBridge 167:84c0a372a020 168 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 167:84c0a372a020 169 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 167:84c0a372a020 170 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 167:84c0a372a020 171
AnnaBridge 167:84c0a372a020 172 /*@} end of group Cortex_M0 */
AnnaBridge 167:84c0a372a020 173
AnnaBridge 167:84c0a372a020 174
AnnaBridge 167:84c0a372a020 175
AnnaBridge 167:84c0a372a020 176 /*******************************************************************************
AnnaBridge 167:84c0a372a020 177 * Register Abstraction
AnnaBridge 167:84c0a372a020 178 Core Register contain:
AnnaBridge 167:84c0a372a020 179 - Core Register
AnnaBridge 167:84c0a372a020 180 - Core NVIC Register
AnnaBridge 167:84c0a372a020 181 - Core SCB Register
AnnaBridge 167:84c0a372a020 182 - Core SysTick Register
AnnaBridge 167:84c0a372a020 183 ******************************************************************************/
AnnaBridge 167:84c0a372a020 184 /**
AnnaBridge 167:84c0a372a020 185 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 167:84c0a372a020 186 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 167:84c0a372a020 187 */
AnnaBridge 167:84c0a372a020 188
AnnaBridge 167:84c0a372a020 189 /**
AnnaBridge 167:84c0a372a020 190 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 191 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 167:84c0a372a020 192 \brief Core Register type definitions.
AnnaBridge 167:84c0a372a020 193 @{
AnnaBridge 167:84c0a372a020 194 */
AnnaBridge 167:84c0a372a020 195
AnnaBridge 167:84c0a372a020 196 /**
AnnaBridge 167:84c0a372a020 197 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 167:84c0a372a020 198 */
AnnaBridge 167:84c0a372a020 199 typedef union
AnnaBridge 167:84c0a372a020 200 {
AnnaBridge 167:84c0a372a020 201 struct
AnnaBridge 167:84c0a372a020 202 {
AnnaBridge 167:84c0a372a020 203 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 167:84c0a372a020 204 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:84c0a372a020 205 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:84c0a372a020 206 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:84c0a372a020 207 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:84c0a372a020 208 } b; /*!< Structure used for bit access */
AnnaBridge 167:84c0a372a020 209 uint32_t w; /*!< Type used for word access */
AnnaBridge 167:84c0a372a020 210 } APSR_Type;
AnnaBridge 167:84c0a372a020 211
AnnaBridge 167:84c0a372a020 212 /* APSR Register Definitions */
AnnaBridge 167:84c0a372a020 213 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 167:84c0a372a020 214 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 167:84c0a372a020 215
AnnaBridge 167:84c0a372a020 216 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 167:84c0a372a020 217 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 167:84c0a372a020 218
AnnaBridge 167:84c0a372a020 219 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 167:84c0a372a020 220 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 167:84c0a372a020 221
AnnaBridge 167:84c0a372a020 222 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 167:84c0a372a020 223 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 167:84c0a372a020 224
AnnaBridge 167:84c0a372a020 225
AnnaBridge 167:84c0a372a020 226 /**
AnnaBridge 167:84c0a372a020 227 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 167:84c0a372a020 228 */
AnnaBridge 167:84c0a372a020 229 typedef union
AnnaBridge 167:84c0a372a020 230 {
AnnaBridge 167:84c0a372a020 231 struct
AnnaBridge 167:84c0a372a020 232 {
AnnaBridge 167:84c0a372a020 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:84c0a372a020 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 167:84c0a372a020 235 } b; /*!< Structure used for bit access */
AnnaBridge 167:84c0a372a020 236 uint32_t w; /*!< Type used for word access */
AnnaBridge 167:84c0a372a020 237 } IPSR_Type;
AnnaBridge 167:84c0a372a020 238
AnnaBridge 167:84c0a372a020 239 /* IPSR Register Definitions */
AnnaBridge 167:84c0a372a020 240 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 167:84c0a372a020 241 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 167:84c0a372a020 242
AnnaBridge 167:84c0a372a020 243
AnnaBridge 167:84c0a372a020 244 /**
AnnaBridge 167:84c0a372a020 245 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 167:84c0a372a020 246 */
AnnaBridge 167:84c0a372a020 247 typedef union
AnnaBridge 167:84c0a372a020 248 {
AnnaBridge 167:84c0a372a020 249 struct
AnnaBridge 167:84c0a372a020 250 {
AnnaBridge 167:84c0a372a020 251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:84c0a372a020 252 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 167:84c0a372a020 253 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 167:84c0a372a020 254 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 167:84c0a372a020 255 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:84c0a372a020 256 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:84c0a372a020 257 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:84c0a372a020 258 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:84c0a372a020 259 } b; /*!< Structure used for bit access */
AnnaBridge 167:84c0a372a020 260 uint32_t w; /*!< Type used for word access */
AnnaBridge 167:84c0a372a020 261 } xPSR_Type;
AnnaBridge 167:84c0a372a020 262
AnnaBridge 167:84c0a372a020 263 /* xPSR Register Definitions */
AnnaBridge 167:84c0a372a020 264 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 167:84c0a372a020 265 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 167:84c0a372a020 266
AnnaBridge 167:84c0a372a020 267 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 167:84c0a372a020 268 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 167:84c0a372a020 269
AnnaBridge 167:84c0a372a020 270 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 167:84c0a372a020 271 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 167:84c0a372a020 272
AnnaBridge 167:84c0a372a020 273 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 167:84c0a372a020 274 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 167:84c0a372a020 275
AnnaBridge 167:84c0a372a020 276 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 167:84c0a372a020 277 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 167:84c0a372a020 278
AnnaBridge 167:84c0a372a020 279 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 167:84c0a372a020 280 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 167:84c0a372a020 281
AnnaBridge 167:84c0a372a020 282
AnnaBridge 167:84c0a372a020 283 /**
AnnaBridge 167:84c0a372a020 284 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 167:84c0a372a020 285 */
AnnaBridge 167:84c0a372a020 286 typedef union
AnnaBridge 167:84c0a372a020 287 {
AnnaBridge 167:84c0a372a020 288 struct
AnnaBridge 167:84c0a372a020 289 {
AnnaBridge 167:84c0a372a020 290 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 167:84c0a372a020 291 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 167:84c0a372a020 292 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 167:84c0a372a020 293 } b; /*!< Structure used for bit access */
AnnaBridge 167:84c0a372a020 294 uint32_t w; /*!< Type used for word access */
AnnaBridge 167:84c0a372a020 295 } CONTROL_Type;
AnnaBridge 167:84c0a372a020 296
AnnaBridge 167:84c0a372a020 297 /* CONTROL Register Definitions */
AnnaBridge 167:84c0a372a020 298 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 167:84c0a372a020 299 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 167:84c0a372a020 300
AnnaBridge 167:84c0a372a020 301 /*@} end of group CMSIS_CORE */
AnnaBridge 167:84c0a372a020 302
AnnaBridge 167:84c0a372a020 303
AnnaBridge 167:84c0a372a020 304 /**
AnnaBridge 167:84c0a372a020 305 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 306 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 167:84c0a372a020 307 \brief Type definitions for the NVIC Registers
AnnaBridge 167:84c0a372a020 308 @{
AnnaBridge 167:84c0a372a020 309 */
AnnaBridge 167:84c0a372a020 310
AnnaBridge 167:84c0a372a020 311 /**
AnnaBridge 167:84c0a372a020 312 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 167:84c0a372a020 313 */
AnnaBridge 167:84c0a372a020 314 typedef struct
AnnaBridge 167:84c0a372a020 315 {
AnnaBridge 167:84c0a372a020 316 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 167:84c0a372a020 317 uint32_t RESERVED0[31U];
AnnaBridge 167:84c0a372a020 318 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 167:84c0a372a020 319 uint32_t RSERVED1[31U];
AnnaBridge 167:84c0a372a020 320 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 167:84c0a372a020 321 uint32_t RESERVED2[31U];
AnnaBridge 167:84c0a372a020 322 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 167:84c0a372a020 323 uint32_t RESERVED3[31U];
AnnaBridge 167:84c0a372a020 324 uint32_t RESERVED4[64U];
AnnaBridge 167:84c0a372a020 325 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 167:84c0a372a020 326 } NVIC_Type;
AnnaBridge 167:84c0a372a020 327
AnnaBridge 167:84c0a372a020 328 /*@} end of group CMSIS_NVIC */
AnnaBridge 167:84c0a372a020 329
AnnaBridge 167:84c0a372a020 330
AnnaBridge 167:84c0a372a020 331 /**
AnnaBridge 167:84c0a372a020 332 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 333 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 167:84c0a372a020 334 \brief Type definitions for the System Control Block Registers
AnnaBridge 167:84c0a372a020 335 @{
AnnaBridge 167:84c0a372a020 336 */
AnnaBridge 167:84c0a372a020 337
AnnaBridge 167:84c0a372a020 338 /**
AnnaBridge 167:84c0a372a020 339 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 167:84c0a372a020 340 */
AnnaBridge 167:84c0a372a020 341 typedef struct
AnnaBridge 167:84c0a372a020 342 {
AnnaBridge 167:84c0a372a020 343 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 167:84c0a372a020 344 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 167:84c0a372a020 345 uint32_t RESERVED0;
AnnaBridge 167:84c0a372a020 346 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 167:84c0a372a020 347 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 167:84c0a372a020 348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 167:84c0a372a020 349 uint32_t RESERVED1;
AnnaBridge 167:84c0a372a020 350 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 167:84c0a372a020 351 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 167:84c0a372a020 352 } SCB_Type;
AnnaBridge 167:84c0a372a020 353
AnnaBridge 167:84c0a372a020 354 /* SCB CPUID Register Definitions */
AnnaBridge 167:84c0a372a020 355 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 167:84c0a372a020 356 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 167:84c0a372a020 357
AnnaBridge 167:84c0a372a020 358 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 167:84c0a372a020 359 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 167:84c0a372a020 360
AnnaBridge 167:84c0a372a020 361 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 167:84c0a372a020 362 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 167:84c0a372a020 363
AnnaBridge 167:84c0a372a020 364 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 167:84c0a372a020 365 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 167:84c0a372a020 366
AnnaBridge 167:84c0a372a020 367 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 167:84c0a372a020 368 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 167:84c0a372a020 369
AnnaBridge 167:84c0a372a020 370 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 167:84c0a372a020 371 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 167:84c0a372a020 372 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 167:84c0a372a020 373
AnnaBridge 167:84c0a372a020 374 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 167:84c0a372a020 375 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 167:84c0a372a020 376
AnnaBridge 167:84c0a372a020 377 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 167:84c0a372a020 378 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 167:84c0a372a020 379
AnnaBridge 167:84c0a372a020 380 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 167:84c0a372a020 381 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 167:84c0a372a020 382
AnnaBridge 167:84c0a372a020 383 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 167:84c0a372a020 384 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 167:84c0a372a020 385
AnnaBridge 167:84c0a372a020 386 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 167:84c0a372a020 387 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 167:84c0a372a020 388
AnnaBridge 167:84c0a372a020 389 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 167:84c0a372a020 390 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 167:84c0a372a020 391
AnnaBridge 167:84c0a372a020 392 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 167:84c0a372a020 393 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 167:84c0a372a020 394
AnnaBridge 167:84c0a372a020 395 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 167:84c0a372a020 396 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 167:84c0a372a020 397
AnnaBridge 167:84c0a372a020 398 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 167:84c0a372a020 399 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 167:84c0a372a020 400 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 167:84c0a372a020 401
AnnaBridge 167:84c0a372a020 402 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 167:84c0a372a020 403 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 167:84c0a372a020 404
AnnaBridge 167:84c0a372a020 405 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 167:84c0a372a020 406 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 167:84c0a372a020 407
AnnaBridge 167:84c0a372a020 408 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 167:84c0a372a020 409 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 167:84c0a372a020 410
AnnaBridge 167:84c0a372a020 411 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 167:84c0a372a020 412 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 167:84c0a372a020 413
AnnaBridge 167:84c0a372a020 414 /* SCB System Control Register Definitions */
AnnaBridge 167:84c0a372a020 415 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 167:84c0a372a020 416 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 167:84c0a372a020 417
AnnaBridge 167:84c0a372a020 418 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 167:84c0a372a020 419 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 167:84c0a372a020 420
AnnaBridge 167:84c0a372a020 421 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 167:84c0a372a020 422 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 167:84c0a372a020 423
AnnaBridge 167:84c0a372a020 424 /* SCB Configuration Control Register Definitions */
AnnaBridge 167:84c0a372a020 425 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 167:84c0a372a020 426 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 167:84c0a372a020 427
AnnaBridge 167:84c0a372a020 428 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 167:84c0a372a020 429 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 167:84c0a372a020 430
AnnaBridge 167:84c0a372a020 431 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 167:84c0a372a020 432 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 167:84c0a372a020 433 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 167:84c0a372a020 434
AnnaBridge 167:84c0a372a020 435 /*@} end of group CMSIS_SCB */
AnnaBridge 167:84c0a372a020 436
AnnaBridge 167:84c0a372a020 437
AnnaBridge 167:84c0a372a020 438 /**
AnnaBridge 167:84c0a372a020 439 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 440 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 167:84c0a372a020 441 \brief Type definitions for the System Timer Registers.
AnnaBridge 167:84c0a372a020 442 @{
AnnaBridge 167:84c0a372a020 443 */
AnnaBridge 167:84c0a372a020 444
AnnaBridge 167:84c0a372a020 445 /**
AnnaBridge 167:84c0a372a020 446 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 167:84c0a372a020 447 */
AnnaBridge 167:84c0a372a020 448 typedef struct
AnnaBridge 167:84c0a372a020 449 {
AnnaBridge 167:84c0a372a020 450 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 167:84c0a372a020 451 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 167:84c0a372a020 452 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 167:84c0a372a020 453 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 167:84c0a372a020 454 } SysTick_Type;
AnnaBridge 167:84c0a372a020 455
AnnaBridge 167:84c0a372a020 456 /* SysTick Control / Status Register Definitions */
AnnaBridge 167:84c0a372a020 457 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 167:84c0a372a020 458 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 167:84c0a372a020 459
AnnaBridge 167:84c0a372a020 460 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 167:84c0a372a020 461 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 167:84c0a372a020 462
AnnaBridge 167:84c0a372a020 463 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 167:84c0a372a020 464 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 167:84c0a372a020 465
AnnaBridge 167:84c0a372a020 466 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 167:84c0a372a020 467 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 167:84c0a372a020 468
AnnaBridge 167:84c0a372a020 469 /* SysTick Reload Register Definitions */
AnnaBridge 167:84c0a372a020 470 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 167:84c0a372a020 471 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 167:84c0a372a020 472
AnnaBridge 167:84c0a372a020 473 /* SysTick Current Register Definitions */
AnnaBridge 167:84c0a372a020 474 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 167:84c0a372a020 475 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 167:84c0a372a020 476
AnnaBridge 167:84c0a372a020 477 /* SysTick Calibration Register Definitions */
AnnaBridge 167:84c0a372a020 478 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 167:84c0a372a020 479 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 167:84c0a372a020 480
AnnaBridge 167:84c0a372a020 481 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 167:84c0a372a020 482 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 167:84c0a372a020 483
AnnaBridge 167:84c0a372a020 484 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 167:84c0a372a020 485 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 167:84c0a372a020 486
AnnaBridge 167:84c0a372a020 487 /*@} end of group CMSIS_SysTick */
AnnaBridge 167:84c0a372a020 488
AnnaBridge 167:84c0a372a020 489
AnnaBridge 167:84c0a372a020 490 /**
AnnaBridge 167:84c0a372a020 491 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 492 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 167:84c0a372a020 493 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 167:84c0a372a020 494 Therefore they are not covered by the Cortex-M0 header file.
AnnaBridge 167:84c0a372a020 495 @{
AnnaBridge 167:84c0a372a020 496 */
AnnaBridge 167:84c0a372a020 497 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 167:84c0a372a020 498
AnnaBridge 167:84c0a372a020 499
AnnaBridge 167:84c0a372a020 500 /**
AnnaBridge 167:84c0a372a020 501 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 502 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 167:84c0a372a020 503 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 167:84c0a372a020 504 @{
AnnaBridge 167:84c0a372a020 505 */
AnnaBridge 167:84c0a372a020 506
AnnaBridge 167:84c0a372a020 507 /**
AnnaBridge 167:84c0a372a020 508 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 167:84c0a372a020 509 \param[in] field Name of the register bit field.
AnnaBridge 167:84c0a372a020 510 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:84c0a372a020 511 \return Masked and shifted value.
AnnaBridge 167:84c0a372a020 512 */
AnnaBridge 167:84c0a372a020 513 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 167:84c0a372a020 514
AnnaBridge 167:84c0a372a020 515 /**
AnnaBridge 167:84c0a372a020 516 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 167:84c0a372a020 517 \param[in] field Name of the register bit field.
AnnaBridge 167:84c0a372a020 518 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:84c0a372a020 519 \return Masked and shifted bit field value.
AnnaBridge 167:84c0a372a020 520 */
AnnaBridge 167:84c0a372a020 521 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 167:84c0a372a020 522
AnnaBridge 167:84c0a372a020 523 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 167:84c0a372a020 524
AnnaBridge 167:84c0a372a020 525
AnnaBridge 167:84c0a372a020 526 /**
AnnaBridge 167:84c0a372a020 527 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 528 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 167:84c0a372a020 529 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 167:84c0a372a020 530 @{
AnnaBridge 167:84c0a372a020 531 */
AnnaBridge 167:84c0a372a020 532
AnnaBridge 167:84c0a372a020 533 /* Memory mapping of Core Hardware */
AnnaBridge 167:84c0a372a020 534 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 167:84c0a372a020 535 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 167:84c0a372a020 536 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 167:84c0a372a020 537 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 167:84c0a372a020 538
AnnaBridge 167:84c0a372a020 539 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 167:84c0a372a020 540 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 167:84c0a372a020 541 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 167:84c0a372a020 542
AnnaBridge 167:84c0a372a020 543
AnnaBridge 167:84c0a372a020 544 /*@} */
AnnaBridge 167:84c0a372a020 545
AnnaBridge 167:84c0a372a020 546
AnnaBridge 167:84c0a372a020 547
AnnaBridge 167:84c0a372a020 548 /*******************************************************************************
AnnaBridge 167:84c0a372a020 549 * Hardware Abstraction Layer
AnnaBridge 167:84c0a372a020 550 Core Function Interface contains:
AnnaBridge 167:84c0a372a020 551 - Core NVIC Functions
AnnaBridge 167:84c0a372a020 552 - Core SysTick Functions
AnnaBridge 167:84c0a372a020 553 - Core Register Access Functions
AnnaBridge 167:84c0a372a020 554 ******************************************************************************/
AnnaBridge 167:84c0a372a020 555 /**
AnnaBridge 167:84c0a372a020 556 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 167:84c0a372a020 557 */
AnnaBridge 167:84c0a372a020 558
AnnaBridge 167:84c0a372a020 559
AnnaBridge 167:84c0a372a020 560
AnnaBridge 167:84c0a372a020 561 /* ########################## NVIC functions #################################### */
AnnaBridge 167:84c0a372a020 562 /**
AnnaBridge 167:84c0a372a020 563 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:84c0a372a020 564 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 167:84c0a372a020 565 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 167:84c0a372a020 566 @{
AnnaBridge 167:84c0a372a020 567 */
AnnaBridge 167:84c0a372a020 568
AnnaBridge 167:84c0a372a020 569 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 167:84c0a372a020 570 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 167:84c0a372a020 571 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 167:84c0a372a020 572 #endif
AnnaBridge 167:84c0a372a020 573 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 167:84c0a372a020 574 #else
AnnaBridge 167:84c0a372a020 575 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 167:84c0a372a020 576 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 167:84c0a372a020 577 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 167:84c0a372a020 578 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 167:84c0a372a020 579 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 167:84c0a372a020 580 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 167:84c0a372a020 581 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 167:84c0a372a020 582 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 167:84c0a372a020 583 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
AnnaBridge 167:84c0a372a020 584 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 167:84c0a372a020 585 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 167:84c0a372a020 586 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 167:84c0a372a020 587 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 167:84c0a372a020 588
AnnaBridge 167:84c0a372a020 589 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 167:84c0a372a020 590 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 167:84c0a372a020 591 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 167:84c0a372a020 592 #endif
AnnaBridge 167:84c0a372a020 593 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 167:84c0a372a020 594 #else
AnnaBridge 167:84c0a372a020 595 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 167:84c0a372a020 596 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 167:84c0a372a020 597 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 167:84c0a372a020 598
AnnaBridge 167:84c0a372a020 599 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 167:84c0a372a020 600
AnnaBridge 167:84c0a372a020 601
Anna Bridge 169:a7c7b631e539 602 /* Interrupt Priorities are WORD accessible only under Armv6-M */
AnnaBridge 167:84c0a372a020 603 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 167:84c0a372a020 604 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 167:84c0a372a020 605 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 167:84c0a372a020 606 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 167:84c0a372a020 607
AnnaBridge 167:84c0a372a020 608
AnnaBridge 167:84c0a372a020 609 /**
AnnaBridge 167:84c0a372a020 610 \brief Enable Interrupt
AnnaBridge 167:84c0a372a020 611 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:84c0a372a020 612 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 613 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 614 */
AnnaBridge 167:84c0a372a020 615 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 616 {
AnnaBridge 167:84c0a372a020 617 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 618 {
Anna Bridge 169:a7c7b631e539 619 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 620 }
AnnaBridge 167:84c0a372a020 621 }
AnnaBridge 167:84c0a372a020 622
AnnaBridge 167:84c0a372a020 623
AnnaBridge 167:84c0a372a020 624 /**
AnnaBridge 167:84c0a372a020 625 \brief Get Interrupt Enable status
AnnaBridge 167:84c0a372a020 626 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 167:84c0a372a020 627 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 628 \return 0 Interrupt is not enabled.
AnnaBridge 167:84c0a372a020 629 \return 1 Interrupt is enabled.
AnnaBridge 167:84c0a372a020 630 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 631 */
AnnaBridge 167:84c0a372a020 632 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 633 {
AnnaBridge 167:84c0a372a020 634 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 635 {
Anna Bridge 169:a7c7b631e539 636 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 637 }
AnnaBridge 167:84c0a372a020 638 else
AnnaBridge 167:84c0a372a020 639 {
AnnaBridge 167:84c0a372a020 640 return(0U);
AnnaBridge 167:84c0a372a020 641 }
AnnaBridge 167:84c0a372a020 642 }
AnnaBridge 167:84c0a372a020 643
AnnaBridge 167:84c0a372a020 644
AnnaBridge 167:84c0a372a020 645 /**
AnnaBridge 167:84c0a372a020 646 \brief Disable Interrupt
AnnaBridge 167:84c0a372a020 647 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:84c0a372a020 648 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 649 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 650 */
AnnaBridge 167:84c0a372a020 651 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 652 {
AnnaBridge 167:84c0a372a020 653 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 654 {
Anna Bridge 169:a7c7b631e539 655 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 656 __DSB();
AnnaBridge 167:84c0a372a020 657 __ISB();
AnnaBridge 167:84c0a372a020 658 }
AnnaBridge 167:84c0a372a020 659 }
AnnaBridge 167:84c0a372a020 660
AnnaBridge 167:84c0a372a020 661
AnnaBridge 167:84c0a372a020 662 /**
AnnaBridge 167:84c0a372a020 663 \brief Get Pending Interrupt
AnnaBridge 167:84c0a372a020 664 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 167:84c0a372a020 665 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 666 \return 0 Interrupt status is not pending.
AnnaBridge 167:84c0a372a020 667 \return 1 Interrupt status is pending.
AnnaBridge 167:84c0a372a020 668 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 669 */
AnnaBridge 167:84c0a372a020 670 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 671 {
AnnaBridge 167:84c0a372a020 672 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 673 {
Anna Bridge 169:a7c7b631e539 674 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 675 }
AnnaBridge 167:84c0a372a020 676 else
AnnaBridge 167:84c0a372a020 677 {
AnnaBridge 167:84c0a372a020 678 return(0U);
AnnaBridge 167:84c0a372a020 679 }
AnnaBridge 167:84c0a372a020 680 }
AnnaBridge 167:84c0a372a020 681
AnnaBridge 167:84c0a372a020 682
AnnaBridge 167:84c0a372a020 683 /**
AnnaBridge 167:84c0a372a020 684 \brief Set Pending Interrupt
AnnaBridge 167:84c0a372a020 685 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:84c0a372a020 686 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 687 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 688 */
AnnaBridge 167:84c0a372a020 689 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 690 {
AnnaBridge 167:84c0a372a020 691 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 692 {
Anna Bridge 169:a7c7b631e539 693 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 694 }
AnnaBridge 167:84c0a372a020 695 }
AnnaBridge 167:84c0a372a020 696
AnnaBridge 167:84c0a372a020 697
AnnaBridge 167:84c0a372a020 698 /**
AnnaBridge 167:84c0a372a020 699 \brief Clear Pending Interrupt
AnnaBridge 167:84c0a372a020 700 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:84c0a372a020 701 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 702 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 703 */
AnnaBridge 167:84c0a372a020 704 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 705 {
AnnaBridge 167:84c0a372a020 706 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 707 {
Anna Bridge 169:a7c7b631e539 708 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 709 }
AnnaBridge 167:84c0a372a020 710 }
AnnaBridge 167:84c0a372a020 711
AnnaBridge 167:84c0a372a020 712
AnnaBridge 167:84c0a372a020 713 /**
AnnaBridge 167:84c0a372a020 714 \brief Set Interrupt Priority
AnnaBridge 167:84c0a372a020 715 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:84c0a372a020 716 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 717 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 718 \param [in] IRQn Interrupt number.
AnnaBridge 167:84c0a372a020 719 \param [in] priority Priority to set.
AnnaBridge 167:84c0a372a020 720 \note The priority cannot be set for every processor exception.
AnnaBridge 167:84c0a372a020 721 */
AnnaBridge 167:84c0a372a020 722 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 167:84c0a372a020 723 {
AnnaBridge 167:84c0a372a020 724 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 725 {
AnnaBridge 167:84c0a372a020 726 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 167:84c0a372a020 727 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 167:84c0a372a020 728 }
AnnaBridge 167:84c0a372a020 729 else
AnnaBridge 167:84c0a372a020 730 {
AnnaBridge 167:84c0a372a020 731 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 167:84c0a372a020 732 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 167:84c0a372a020 733 }
AnnaBridge 167:84c0a372a020 734 }
AnnaBridge 167:84c0a372a020 735
AnnaBridge 167:84c0a372a020 736
AnnaBridge 167:84c0a372a020 737 /**
AnnaBridge 167:84c0a372a020 738 \brief Get Interrupt Priority
AnnaBridge 167:84c0a372a020 739 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:84c0a372a020 740 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 741 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 742 \param [in] IRQn Interrupt number.
AnnaBridge 167:84c0a372a020 743 \return Interrupt Priority.
AnnaBridge 167:84c0a372a020 744 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 167:84c0a372a020 745 */
AnnaBridge 167:84c0a372a020 746 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 747 {
AnnaBridge 167:84c0a372a020 748
AnnaBridge 167:84c0a372a020 749 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 750 {
AnnaBridge 167:84c0a372a020 751 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 167:84c0a372a020 752 }
AnnaBridge 167:84c0a372a020 753 else
AnnaBridge 167:84c0a372a020 754 {
AnnaBridge 167:84c0a372a020 755 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 167:84c0a372a020 756 }
AnnaBridge 167:84c0a372a020 757 }
AnnaBridge 167:84c0a372a020 758
AnnaBridge 167:84c0a372a020 759
AnnaBridge 167:84c0a372a020 760 /**
AnnaBridge 167:84c0a372a020 761 \brief Set Interrupt Vector
AnnaBridge 167:84c0a372a020 762 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 167:84c0a372a020 763 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 764 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 765 Address 0 must be mapped to SRAM.
AnnaBridge 167:84c0a372a020 766 \param [in] IRQn Interrupt number
AnnaBridge 167:84c0a372a020 767 \param [in] vector Address of interrupt handler function
AnnaBridge 167:84c0a372a020 768 */
AnnaBridge 167:84c0a372a020 769 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 167:84c0a372a020 770 {
AnnaBridge 167:84c0a372a020 771 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 167:84c0a372a020 772 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 167:84c0a372a020 773 }
AnnaBridge 167:84c0a372a020 774
AnnaBridge 167:84c0a372a020 775
AnnaBridge 167:84c0a372a020 776 /**
AnnaBridge 167:84c0a372a020 777 \brief Get Interrupt Vector
AnnaBridge 167:84c0a372a020 778 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 167:84c0a372a020 779 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 780 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 781 \param [in] IRQn Interrupt number.
AnnaBridge 167:84c0a372a020 782 \return Address of interrupt handler function
AnnaBridge 167:84c0a372a020 783 */
AnnaBridge 167:84c0a372a020 784 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 785 {
AnnaBridge 167:84c0a372a020 786 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 167:84c0a372a020 787 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 167:84c0a372a020 788 }
AnnaBridge 167:84c0a372a020 789
AnnaBridge 167:84c0a372a020 790
AnnaBridge 167:84c0a372a020 791 /**
AnnaBridge 167:84c0a372a020 792 \brief System Reset
AnnaBridge 167:84c0a372a020 793 \details Initiates a system reset request to reset the MCU.
AnnaBridge 167:84c0a372a020 794 */
AnnaBridge 167:84c0a372a020 795 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 167:84c0a372a020 796 {
AnnaBridge 167:84c0a372a020 797 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 167:84c0a372a020 798 buffered write are completed before reset */
AnnaBridge 167:84c0a372a020 799 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 167:84c0a372a020 800 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 167:84c0a372a020 801 __DSB(); /* Ensure completion of memory access */
AnnaBridge 167:84c0a372a020 802
AnnaBridge 167:84c0a372a020 803 for(;;) /* wait until reset */
AnnaBridge 167:84c0a372a020 804 {
AnnaBridge 167:84c0a372a020 805 __NOP();
AnnaBridge 167:84c0a372a020 806 }
AnnaBridge 167:84c0a372a020 807 }
AnnaBridge 167:84c0a372a020 808
AnnaBridge 167:84c0a372a020 809 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 167:84c0a372a020 810
AnnaBridge 167:84c0a372a020 811
AnnaBridge 167:84c0a372a020 812 /* ########################## FPU functions #################################### */
AnnaBridge 167:84c0a372a020 813 /**
AnnaBridge 167:84c0a372a020 814 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:84c0a372a020 815 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 167:84c0a372a020 816 \brief Function that provides FPU type.
AnnaBridge 167:84c0a372a020 817 @{
AnnaBridge 167:84c0a372a020 818 */
AnnaBridge 167:84c0a372a020 819
AnnaBridge 167:84c0a372a020 820 /**
AnnaBridge 167:84c0a372a020 821 \brief get FPU type
AnnaBridge 167:84c0a372a020 822 \details returns the FPU type
AnnaBridge 167:84c0a372a020 823 \returns
AnnaBridge 167:84c0a372a020 824 - \b 0: No FPU
AnnaBridge 167:84c0a372a020 825 - \b 1: Single precision FPU
AnnaBridge 167:84c0a372a020 826 - \b 2: Double + Single precision FPU
AnnaBridge 167:84c0a372a020 827 */
AnnaBridge 167:84c0a372a020 828 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 167:84c0a372a020 829 {
AnnaBridge 167:84c0a372a020 830 return 0U; /* No FPU */
AnnaBridge 167:84c0a372a020 831 }
AnnaBridge 167:84c0a372a020 832
AnnaBridge 167:84c0a372a020 833
AnnaBridge 167:84c0a372a020 834 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 167:84c0a372a020 835
AnnaBridge 167:84c0a372a020 836
AnnaBridge 167:84c0a372a020 837
AnnaBridge 167:84c0a372a020 838 /* ################################## SysTick function ############################################ */
AnnaBridge 167:84c0a372a020 839 /**
AnnaBridge 167:84c0a372a020 840 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:84c0a372a020 841 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 167:84c0a372a020 842 \brief Functions that configure the System.
AnnaBridge 167:84c0a372a020 843 @{
AnnaBridge 167:84c0a372a020 844 */
AnnaBridge 167:84c0a372a020 845
AnnaBridge 167:84c0a372a020 846 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 167:84c0a372a020 847
AnnaBridge 167:84c0a372a020 848 /**
AnnaBridge 167:84c0a372a020 849 \brief System Tick Configuration
AnnaBridge 167:84c0a372a020 850 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 167:84c0a372a020 851 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 167:84c0a372a020 852 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 167:84c0a372a020 853 \return 0 Function succeeded.
AnnaBridge 167:84c0a372a020 854 \return 1 Function failed.
AnnaBridge 167:84c0a372a020 855 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 167:84c0a372a020 856 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 167:84c0a372a020 857 must contain a vendor-specific implementation of this function.
AnnaBridge 167:84c0a372a020 858 */
AnnaBridge 167:84c0a372a020 859 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 167:84c0a372a020 860 {
AnnaBridge 167:84c0a372a020 861 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 167:84c0a372a020 862 {
AnnaBridge 167:84c0a372a020 863 return (1UL); /* Reload value impossible */
AnnaBridge 167:84c0a372a020 864 }
AnnaBridge 167:84c0a372a020 865
AnnaBridge 167:84c0a372a020 866 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 167:84c0a372a020 867 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 167:84c0a372a020 868 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 167:84c0a372a020 869 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 167:84c0a372a020 870 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 167:84c0a372a020 871 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 167:84c0a372a020 872 return (0UL); /* Function successful */
AnnaBridge 167:84c0a372a020 873 }
AnnaBridge 167:84c0a372a020 874
AnnaBridge 167:84c0a372a020 875 #endif
AnnaBridge 167:84c0a372a020 876
AnnaBridge 167:84c0a372a020 877 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 167:84c0a372a020 878
AnnaBridge 167:84c0a372a020 879
AnnaBridge 167:84c0a372a020 880
AnnaBridge 167:84c0a372a020 881
AnnaBridge 167:84c0a372a020 882 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 883 }
AnnaBridge 167:84c0a372a020 884 #endif
AnnaBridge 167:84c0a372a020 885
AnnaBridge 167:84c0a372a020 886 #endif /* __CORE_CM0_H_DEPENDANT */
AnnaBridge 167:84c0a372a020 887
AnnaBridge 167:84c0a372a020 888 #endif /* __CMSIS_GENERIC */