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Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
167:84c0a372a020
mbed library. Release version 162

Who changed what in which revision?

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AnnaBridge 167:84c0a372a020 1 /**************************************************************************//**
AnnaBridge 167:84c0a372a020 2 * @file core_armv8mbl.h
Anna Bridge 169:a7c7b631e539 3 * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.4
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
AnnaBridge 167:84c0a372a020 6 ******************************************************************************/
AnnaBridge 167:84c0a372a020 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 167:84c0a372a020 9 *
AnnaBridge 167:84c0a372a020 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 167:84c0a372a020 11 *
AnnaBridge 167:84c0a372a020 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 167:84c0a372a020 13 * not use this file except in compliance with the License.
AnnaBridge 167:84c0a372a020 14 * You may obtain a copy of the License at
AnnaBridge 167:84c0a372a020 15 *
AnnaBridge 167:84c0a372a020 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 167:84c0a372a020 17 *
AnnaBridge 167:84c0a372a020 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:84c0a372a020 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 167:84c0a372a020 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:84c0a372a020 21 * See the License for the specific language governing permissions and
AnnaBridge 167:84c0a372a020 22 * limitations under the License.
AnnaBridge 167:84c0a372a020 23 */
AnnaBridge 167:84c0a372a020 24
AnnaBridge 167:84c0a372a020 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
AnnaBridge 167:84c0a372a020 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 167:84c0a372a020 29 #endif
AnnaBridge 167:84c0a372a020 30
AnnaBridge 167:84c0a372a020 31 #ifndef __CORE_ARMV8MBL_H_GENERIC
AnnaBridge 167:84c0a372a020 32 #define __CORE_ARMV8MBL_H_GENERIC
AnnaBridge 167:84c0a372a020 33
AnnaBridge 167:84c0a372a020 34 #include <stdint.h>
AnnaBridge 167:84c0a372a020 35
AnnaBridge 167:84c0a372a020 36 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 37 extern "C" {
AnnaBridge 167:84c0a372a020 38 #endif
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 /**
AnnaBridge 167:84c0a372a020 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 167:84c0a372a020 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 167:84c0a372a020 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 167:84c0a372a020 46
AnnaBridge 167:84c0a372a020 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 167:84c0a372a020 48 Unions are used for effective representation of core registers.
AnnaBridge 167:84c0a372a020 49
AnnaBridge 167:84c0a372a020 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 167:84c0a372a020 51 Function-like macros are used to allow more efficient code.
AnnaBridge 167:84c0a372a020 52 */
AnnaBridge 167:84c0a372a020 53
AnnaBridge 167:84c0a372a020 54
AnnaBridge 167:84c0a372a020 55 /*******************************************************************************
AnnaBridge 167:84c0a372a020 56 * CMSIS definitions
AnnaBridge 167:84c0a372a020 57 ******************************************************************************/
AnnaBridge 167:84c0a372a020 58 /**
AnnaBridge 167:84c0a372a020 59 \ingroup Cortex_ARMv8MBL
AnnaBridge 167:84c0a372a020 60 @{
AnnaBridge 167:84c0a372a020 61 */
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 #include "cmsis_version.h"
AnnaBridge 167:84c0a372a020 64
AnnaBridge 167:84c0a372a020 65 /* CMSIS definitions */
AnnaBridge 167:84c0a372a020 66 #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
AnnaBridge 167:84c0a372a020 67 #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 167:84c0a372a020 68 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 167:84c0a372a020 69 __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 167:84c0a372a020 70
AnnaBridge 167:84c0a372a020 71 #define __CORTEX_M ( 2U) /*!< Cortex-M Core */
AnnaBridge 167:84c0a372a020 72
AnnaBridge 167:84c0a372a020 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 167:84c0a372a020 74 This core does not support an FPU at all
AnnaBridge 167:84c0a372a020 75 */
AnnaBridge 167:84c0a372a020 76 #define __FPU_USED 0U
AnnaBridge 167:84c0a372a020 77
AnnaBridge 167:84c0a372a020 78 #if defined ( __CC_ARM )
AnnaBridge 167:84c0a372a020 79 #if defined __TARGET_FPU_VFP
AnnaBridge 167:84c0a372a020 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 81 #endif
AnnaBridge 167:84c0a372a020 82
AnnaBridge 167:84c0a372a020 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 167:84c0a372a020 84 #if defined __ARM_PCS_VFP
AnnaBridge 167:84c0a372a020 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 86 #endif
AnnaBridge 167:84c0a372a020 87
AnnaBridge 167:84c0a372a020 88 #elif defined ( __GNUC__ )
AnnaBridge 167:84c0a372a020 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 167:84c0a372a020 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 91 #endif
AnnaBridge 167:84c0a372a020 92
AnnaBridge 167:84c0a372a020 93 #elif defined ( __ICCARM__ )
AnnaBridge 167:84c0a372a020 94 #if defined __ARMVFP__
AnnaBridge 167:84c0a372a020 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 96 #endif
AnnaBridge 167:84c0a372a020 97
AnnaBridge 167:84c0a372a020 98 #elif defined ( __TI_ARM__ )
AnnaBridge 167:84c0a372a020 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 167:84c0a372a020 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 101 #endif
AnnaBridge 167:84c0a372a020 102
AnnaBridge 167:84c0a372a020 103 #elif defined ( __TASKING__ )
AnnaBridge 167:84c0a372a020 104 #if defined __FPU_VFP__
AnnaBridge 167:84c0a372a020 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 106 #endif
AnnaBridge 167:84c0a372a020 107
AnnaBridge 167:84c0a372a020 108 #elif defined ( __CSMC__ )
AnnaBridge 167:84c0a372a020 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 167:84c0a372a020 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 111 #endif
AnnaBridge 167:84c0a372a020 112
AnnaBridge 167:84c0a372a020 113 #endif
AnnaBridge 167:84c0a372a020 114
AnnaBridge 167:84c0a372a020 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 167:84c0a372a020 116
AnnaBridge 167:84c0a372a020 117
AnnaBridge 167:84c0a372a020 118 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 119 }
AnnaBridge 167:84c0a372a020 120 #endif
AnnaBridge 167:84c0a372a020 121
AnnaBridge 167:84c0a372a020 122 #endif /* __CORE_ARMV8MBL_H_GENERIC */
AnnaBridge 167:84c0a372a020 123
AnnaBridge 167:84c0a372a020 124 #ifndef __CMSIS_GENERIC
AnnaBridge 167:84c0a372a020 125
AnnaBridge 167:84c0a372a020 126 #ifndef __CORE_ARMV8MBL_H_DEPENDANT
AnnaBridge 167:84c0a372a020 127 #define __CORE_ARMV8MBL_H_DEPENDANT
AnnaBridge 167:84c0a372a020 128
AnnaBridge 167:84c0a372a020 129 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 130 extern "C" {
AnnaBridge 167:84c0a372a020 131 #endif
AnnaBridge 167:84c0a372a020 132
AnnaBridge 167:84c0a372a020 133 /* check device defines and use defaults */
AnnaBridge 167:84c0a372a020 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 167:84c0a372a020 135 #ifndef __ARMv8MBL_REV
AnnaBridge 167:84c0a372a020 136 #define __ARMv8MBL_REV 0x0000U
AnnaBridge 167:84c0a372a020 137 #warning "__ARMv8MBL_REV not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 138 #endif
AnnaBridge 167:84c0a372a020 139
AnnaBridge 167:84c0a372a020 140 #ifndef __FPU_PRESENT
AnnaBridge 167:84c0a372a020 141 #define __FPU_PRESENT 0U
AnnaBridge 167:84c0a372a020 142 #warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 143 #endif
AnnaBridge 167:84c0a372a020 144
AnnaBridge 167:84c0a372a020 145 #ifndef __MPU_PRESENT
AnnaBridge 167:84c0a372a020 146 #define __MPU_PRESENT 0U
AnnaBridge 167:84c0a372a020 147 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 148 #endif
AnnaBridge 167:84c0a372a020 149
AnnaBridge 167:84c0a372a020 150 #ifndef __SAUREGION_PRESENT
AnnaBridge 167:84c0a372a020 151 #define __SAUREGION_PRESENT 0U
AnnaBridge 167:84c0a372a020 152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 153 #endif
AnnaBridge 167:84c0a372a020 154
AnnaBridge 167:84c0a372a020 155 #ifndef __VTOR_PRESENT
AnnaBridge 167:84c0a372a020 156 #define __VTOR_PRESENT 0U
AnnaBridge 167:84c0a372a020 157 #warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 158 #endif
AnnaBridge 167:84c0a372a020 159
AnnaBridge 167:84c0a372a020 160 #ifndef __NVIC_PRIO_BITS
AnnaBridge 167:84c0a372a020 161 #define __NVIC_PRIO_BITS 2U
AnnaBridge 167:84c0a372a020 162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 163 #endif
AnnaBridge 167:84c0a372a020 164
AnnaBridge 167:84c0a372a020 165 #ifndef __Vendor_SysTickConfig
AnnaBridge 167:84c0a372a020 166 #define __Vendor_SysTickConfig 0U
AnnaBridge 167:84c0a372a020 167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 168 #endif
AnnaBridge 167:84c0a372a020 169
AnnaBridge 167:84c0a372a020 170 #ifndef __ETM_PRESENT
AnnaBridge 167:84c0a372a020 171 #define __ETM_PRESENT 0U
AnnaBridge 167:84c0a372a020 172 #warning "__ETM_PRESENT not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 173 #endif
AnnaBridge 167:84c0a372a020 174
AnnaBridge 167:84c0a372a020 175 #ifndef __MTB_PRESENT
AnnaBridge 167:84c0a372a020 176 #define __MTB_PRESENT 0U
AnnaBridge 167:84c0a372a020 177 #warning "__MTB_PRESENT not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 178 #endif
AnnaBridge 167:84c0a372a020 179
AnnaBridge 167:84c0a372a020 180 #endif
AnnaBridge 167:84c0a372a020 181
AnnaBridge 167:84c0a372a020 182 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 167:84c0a372a020 183 /**
AnnaBridge 167:84c0a372a020 184 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 167:84c0a372a020 185
AnnaBridge 167:84c0a372a020 186 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 167:84c0a372a020 187 \li to specify the access to peripheral variables.
AnnaBridge 167:84c0a372a020 188 \li for automatic generation of peripheral register debug information.
AnnaBridge 167:84c0a372a020 189 */
AnnaBridge 167:84c0a372a020 190 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 191 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 167:84c0a372a020 192 #else
AnnaBridge 167:84c0a372a020 193 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 167:84c0a372a020 194 #endif
AnnaBridge 167:84c0a372a020 195 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 167:84c0a372a020 196 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 167:84c0a372a020 197
AnnaBridge 167:84c0a372a020 198 /* following defines should be used for structure members */
AnnaBridge 167:84c0a372a020 199 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 167:84c0a372a020 200 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 167:84c0a372a020 201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 167:84c0a372a020 202
AnnaBridge 167:84c0a372a020 203 /*@} end of group ARMv8MBL */
AnnaBridge 167:84c0a372a020 204
AnnaBridge 167:84c0a372a020 205
AnnaBridge 167:84c0a372a020 206
AnnaBridge 167:84c0a372a020 207 /*******************************************************************************
AnnaBridge 167:84c0a372a020 208 * Register Abstraction
AnnaBridge 167:84c0a372a020 209 Core Register contain:
AnnaBridge 167:84c0a372a020 210 - Core Register
AnnaBridge 167:84c0a372a020 211 - Core NVIC Register
AnnaBridge 167:84c0a372a020 212 - Core SCB Register
AnnaBridge 167:84c0a372a020 213 - Core SysTick Register
AnnaBridge 167:84c0a372a020 214 - Core Debug Register
AnnaBridge 167:84c0a372a020 215 - Core MPU Register
AnnaBridge 167:84c0a372a020 216 - Core SAU Register
AnnaBridge 167:84c0a372a020 217 ******************************************************************************/
AnnaBridge 167:84c0a372a020 218 /**
AnnaBridge 167:84c0a372a020 219 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 167:84c0a372a020 220 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 167:84c0a372a020 221 */
AnnaBridge 167:84c0a372a020 222
AnnaBridge 167:84c0a372a020 223 /**
AnnaBridge 167:84c0a372a020 224 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 225 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 167:84c0a372a020 226 \brief Core Register type definitions.
AnnaBridge 167:84c0a372a020 227 @{
AnnaBridge 167:84c0a372a020 228 */
AnnaBridge 167:84c0a372a020 229
AnnaBridge 167:84c0a372a020 230 /**
AnnaBridge 167:84c0a372a020 231 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 167:84c0a372a020 232 */
AnnaBridge 167:84c0a372a020 233 typedef union
AnnaBridge 167:84c0a372a020 234 {
AnnaBridge 167:84c0a372a020 235 struct
AnnaBridge 167:84c0a372a020 236 {
AnnaBridge 167:84c0a372a020 237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 167:84c0a372a020 238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:84c0a372a020 239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:84c0a372a020 240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:84c0a372a020 241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:84c0a372a020 242 } b; /*!< Structure used for bit access */
AnnaBridge 167:84c0a372a020 243 uint32_t w; /*!< Type used for word access */
AnnaBridge 167:84c0a372a020 244 } APSR_Type;
AnnaBridge 167:84c0a372a020 245
AnnaBridge 167:84c0a372a020 246 /* APSR Register Definitions */
AnnaBridge 167:84c0a372a020 247 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 167:84c0a372a020 248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 167:84c0a372a020 249
AnnaBridge 167:84c0a372a020 250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 167:84c0a372a020 251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 167:84c0a372a020 252
AnnaBridge 167:84c0a372a020 253 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 167:84c0a372a020 254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 167:84c0a372a020 255
AnnaBridge 167:84c0a372a020 256 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 167:84c0a372a020 257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 167:84c0a372a020 258
AnnaBridge 167:84c0a372a020 259
AnnaBridge 167:84c0a372a020 260 /**
AnnaBridge 167:84c0a372a020 261 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 167:84c0a372a020 262 */
AnnaBridge 167:84c0a372a020 263 typedef union
AnnaBridge 167:84c0a372a020 264 {
AnnaBridge 167:84c0a372a020 265 struct
AnnaBridge 167:84c0a372a020 266 {
AnnaBridge 167:84c0a372a020 267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:84c0a372a020 268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 167:84c0a372a020 269 } b; /*!< Structure used for bit access */
AnnaBridge 167:84c0a372a020 270 uint32_t w; /*!< Type used for word access */
AnnaBridge 167:84c0a372a020 271 } IPSR_Type;
AnnaBridge 167:84c0a372a020 272
AnnaBridge 167:84c0a372a020 273 /* IPSR Register Definitions */
AnnaBridge 167:84c0a372a020 274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 167:84c0a372a020 275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 167:84c0a372a020 276
AnnaBridge 167:84c0a372a020 277
AnnaBridge 167:84c0a372a020 278 /**
AnnaBridge 167:84c0a372a020 279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 167:84c0a372a020 280 */
AnnaBridge 167:84c0a372a020 281 typedef union
AnnaBridge 167:84c0a372a020 282 {
AnnaBridge 167:84c0a372a020 283 struct
AnnaBridge 167:84c0a372a020 284 {
AnnaBridge 167:84c0a372a020 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:84c0a372a020 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 167:84c0a372a020 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 167:84c0a372a020 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 167:84c0a372a020 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:84c0a372a020 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:84c0a372a020 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:84c0a372a020 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:84c0a372a020 293 } b; /*!< Structure used for bit access */
AnnaBridge 167:84c0a372a020 294 uint32_t w; /*!< Type used for word access */
AnnaBridge 167:84c0a372a020 295 } xPSR_Type;
AnnaBridge 167:84c0a372a020 296
AnnaBridge 167:84c0a372a020 297 /* xPSR Register Definitions */
AnnaBridge 167:84c0a372a020 298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 167:84c0a372a020 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 167:84c0a372a020 300
AnnaBridge 167:84c0a372a020 301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 167:84c0a372a020 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 167:84c0a372a020 303
AnnaBridge 167:84c0a372a020 304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 167:84c0a372a020 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 167:84c0a372a020 306
AnnaBridge 167:84c0a372a020 307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 167:84c0a372a020 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 167:84c0a372a020 309
AnnaBridge 167:84c0a372a020 310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 167:84c0a372a020 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 167:84c0a372a020 312
AnnaBridge 167:84c0a372a020 313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 167:84c0a372a020 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 167:84c0a372a020 315
AnnaBridge 167:84c0a372a020 316
AnnaBridge 167:84c0a372a020 317 /**
AnnaBridge 167:84c0a372a020 318 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 167:84c0a372a020 319 */
AnnaBridge 167:84c0a372a020 320 typedef union
AnnaBridge 167:84c0a372a020 321 {
AnnaBridge 167:84c0a372a020 322 struct
AnnaBridge 167:84c0a372a020 323 {
AnnaBridge 167:84c0a372a020 324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 167:84c0a372a020 325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
AnnaBridge 167:84c0a372a020 326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 167:84c0a372a020 327 } b; /*!< Structure used for bit access */
AnnaBridge 167:84c0a372a020 328 uint32_t w; /*!< Type used for word access */
AnnaBridge 167:84c0a372a020 329 } CONTROL_Type;
AnnaBridge 167:84c0a372a020 330
AnnaBridge 167:84c0a372a020 331 /* CONTROL Register Definitions */
AnnaBridge 167:84c0a372a020 332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 167:84c0a372a020 333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 167:84c0a372a020 334
AnnaBridge 167:84c0a372a020 335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 167:84c0a372a020 336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 167:84c0a372a020 337
AnnaBridge 167:84c0a372a020 338 /*@} end of group CMSIS_CORE */
AnnaBridge 167:84c0a372a020 339
AnnaBridge 167:84c0a372a020 340
AnnaBridge 167:84c0a372a020 341 /**
AnnaBridge 167:84c0a372a020 342 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 167:84c0a372a020 344 \brief Type definitions for the NVIC Registers
AnnaBridge 167:84c0a372a020 345 @{
AnnaBridge 167:84c0a372a020 346 */
AnnaBridge 167:84c0a372a020 347
AnnaBridge 167:84c0a372a020 348 /**
AnnaBridge 167:84c0a372a020 349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 167:84c0a372a020 350 */
AnnaBridge 167:84c0a372a020 351 typedef struct
AnnaBridge 167:84c0a372a020 352 {
AnnaBridge 167:84c0a372a020 353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 167:84c0a372a020 354 uint32_t RESERVED0[16U];
AnnaBridge 167:84c0a372a020 355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 167:84c0a372a020 356 uint32_t RSERVED1[16U];
AnnaBridge 167:84c0a372a020 357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 167:84c0a372a020 358 uint32_t RESERVED2[16U];
AnnaBridge 167:84c0a372a020 359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 167:84c0a372a020 360 uint32_t RESERVED3[16U];
AnnaBridge 167:84c0a372a020 361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 167:84c0a372a020 362 uint32_t RESERVED4[16U];
AnnaBridge 167:84c0a372a020 363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
AnnaBridge 167:84c0a372a020 364 uint32_t RESERVED5[16U];
AnnaBridge 167:84c0a372a020 365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 167:84c0a372a020 366 } NVIC_Type;
AnnaBridge 167:84c0a372a020 367
AnnaBridge 167:84c0a372a020 368 /*@} end of group CMSIS_NVIC */
AnnaBridge 167:84c0a372a020 369
AnnaBridge 167:84c0a372a020 370
AnnaBridge 167:84c0a372a020 371 /**
AnnaBridge 167:84c0a372a020 372 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 373 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 167:84c0a372a020 374 \brief Type definitions for the System Control Block Registers
AnnaBridge 167:84c0a372a020 375 @{
AnnaBridge 167:84c0a372a020 376 */
AnnaBridge 167:84c0a372a020 377
AnnaBridge 167:84c0a372a020 378 /**
AnnaBridge 167:84c0a372a020 379 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 167:84c0a372a020 380 */
AnnaBridge 167:84c0a372a020 381 typedef struct
AnnaBridge 167:84c0a372a020 382 {
AnnaBridge 167:84c0a372a020 383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 167:84c0a372a020 384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 167:84c0a372a020 385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 167:84c0a372a020 386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 167:84c0a372a020 387 #else
AnnaBridge 167:84c0a372a020 388 uint32_t RESERVED0;
AnnaBridge 167:84c0a372a020 389 #endif
AnnaBridge 167:84c0a372a020 390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 167:84c0a372a020 391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 167:84c0a372a020 392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 167:84c0a372a020 393 uint32_t RESERVED1;
AnnaBridge 167:84c0a372a020 394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 167:84c0a372a020 395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 167:84c0a372a020 396 } SCB_Type;
AnnaBridge 167:84c0a372a020 397
AnnaBridge 167:84c0a372a020 398 /* SCB CPUID Register Definitions */
AnnaBridge 167:84c0a372a020 399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 167:84c0a372a020 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 167:84c0a372a020 401
AnnaBridge 167:84c0a372a020 402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 167:84c0a372a020 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 167:84c0a372a020 404
AnnaBridge 167:84c0a372a020 405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 167:84c0a372a020 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 167:84c0a372a020 407
AnnaBridge 167:84c0a372a020 408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 167:84c0a372a020 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 167:84c0a372a020 410
AnnaBridge 167:84c0a372a020 411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 167:84c0a372a020 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 167:84c0a372a020 413
AnnaBridge 167:84c0a372a020 414 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 167:84c0a372a020 415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
AnnaBridge 167:84c0a372a020 416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
AnnaBridge 167:84c0a372a020 417
AnnaBridge 167:84c0a372a020 418 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
AnnaBridge 167:84c0a372a020 419 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
AnnaBridge 167:84c0a372a020 420
AnnaBridge 167:84c0a372a020 421 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 167:84c0a372a020 422 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 167:84c0a372a020 423
AnnaBridge 167:84c0a372a020 424 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 167:84c0a372a020 425 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 167:84c0a372a020 426
AnnaBridge 167:84c0a372a020 427 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 167:84c0a372a020 428 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 167:84c0a372a020 429
AnnaBridge 167:84c0a372a020 430 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 167:84c0a372a020 431 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 167:84c0a372a020 432
AnnaBridge 167:84c0a372a020 433 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
AnnaBridge 167:84c0a372a020 434 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
AnnaBridge 167:84c0a372a020 435
AnnaBridge 167:84c0a372a020 436 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 167:84c0a372a020 437 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 167:84c0a372a020 438
AnnaBridge 167:84c0a372a020 439 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 167:84c0a372a020 440 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 167:84c0a372a020 441
AnnaBridge 167:84c0a372a020 442 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 167:84c0a372a020 443 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 167:84c0a372a020 444
AnnaBridge 167:84c0a372a020 445 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 167:84c0a372a020 446 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 167:84c0a372a020 447
AnnaBridge 167:84c0a372a020 448 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 167:84c0a372a020 449 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 167:84c0a372a020 450
AnnaBridge 167:84c0a372a020 451 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 167:84c0a372a020 452 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 167:84c0a372a020 453 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 167:84c0a372a020 454 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 167:84c0a372a020 455 #endif
AnnaBridge 167:84c0a372a020 456
AnnaBridge 167:84c0a372a020 457 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 167:84c0a372a020 458 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 167:84c0a372a020 459 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 167:84c0a372a020 460
AnnaBridge 167:84c0a372a020 461 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 167:84c0a372a020 462 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 167:84c0a372a020 463
AnnaBridge 167:84c0a372a020 464 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 167:84c0a372a020 465 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 167:84c0a372a020 466
AnnaBridge 167:84c0a372a020 467 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
AnnaBridge 167:84c0a372a020 468 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
AnnaBridge 167:84c0a372a020 469
AnnaBridge 167:84c0a372a020 470 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
AnnaBridge 167:84c0a372a020 471 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
AnnaBridge 167:84c0a372a020 472
AnnaBridge 167:84c0a372a020 473 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
AnnaBridge 167:84c0a372a020 474 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
AnnaBridge 167:84c0a372a020 475
AnnaBridge 167:84c0a372a020 476 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 167:84c0a372a020 477 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 167:84c0a372a020 478
AnnaBridge 167:84c0a372a020 479 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 167:84c0a372a020 480 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 167:84c0a372a020 481
AnnaBridge 167:84c0a372a020 482 /* SCB System Control Register Definitions */
AnnaBridge 167:84c0a372a020 483 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 167:84c0a372a020 484 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 167:84c0a372a020 485
AnnaBridge 167:84c0a372a020 486 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
AnnaBridge 167:84c0a372a020 487 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
AnnaBridge 167:84c0a372a020 488
AnnaBridge 167:84c0a372a020 489 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 167:84c0a372a020 490 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 167:84c0a372a020 491
AnnaBridge 167:84c0a372a020 492 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 167:84c0a372a020 493 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 167:84c0a372a020 494
AnnaBridge 167:84c0a372a020 495 /* SCB Configuration Control Register Definitions */
AnnaBridge 167:84c0a372a020 496 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
AnnaBridge 167:84c0a372a020 497 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
AnnaBridge 167:84c0a372a020 498
AnnaBridge 167:84c0a372a020 499 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
AnnaBridge 167:84c0a372a020 500 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
AnnaBridge 167:84c0a372a020 501
AnnaBridge 167:84c0a372a020 502 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
AnnaBridge 167:84c0a372a020 503 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
AnnaBridge 167:84c0a372a020 504
AnnaBridge 167:84c0a372a020 505 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
AnnaBridge 167:84c0a372a020 506 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
AnnaBridge 167:84c0a372a020 507
AnnaBridge 167:84c0a372a020 508 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 167:84c0a372a020 509 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 167:84c0a372a020 510
AnnaBridge 167:84c0a372a020 511 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 167:84c0a372a020 512 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 167:84c0a372a020 513
AnnaBridge 167:84c0a372a020 514 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 167:84c0a372a020 515 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 167:84c0a372a020 516
AnnaBridge 167:84c0a372a020 517 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 167:84c0a372a020 518 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 167:84c0a372a020 519
AnnaBridge 167:84c0a372a020 520 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 167:84c0a372a020 521 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
AnnaBridge 167:84c0a372a020 522 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
AnnaBridge 167:84c0a372a020 523
AnnaBridge 167:84c0a372a020 524 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 167:84c0a372a020 525 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 167:84c0a372a020 526
AnnaBridge 167:84c0a372a020 527 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 167:84c0a372a020 528 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 167:84c0a372a020 529
AnnaBridge 167:84c0a372a020 530 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 167:84c0a372a020 531 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 167:84c0a372a020 532
AnnaBridge 167:84c0a372a020 533 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 167:84c0a372a020 534 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 167:84c0a372a020 535
AnnaBridge 167:84c0a372a020 536 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
AnnaBridge 167:84c0a372a020 537 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
AnnaBridge 167:84c0a372a020 538
AnnaBridge 167:84c0a372a020 539 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
AnnaBridge 167:84c0a372a020 540 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
AnnaBridge 167:84c0a372a020 541
AnnaBridge 167:84c0a372a020 542 /*@} end of group CMSIS_SCB */
AnnaBridge 167:84c0a372a020 543
AnnaBridge 167:84c0a372a020 544
AnnaBridge 167:84c0a372a020 545 /**
AnnaBridge 167:84c0a372a020 546 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 547 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 167:84c0a372a020 548 \brief Type definitions for the System Timer Registers.
AnnaBridge 167:84c0a372a020 549 @{
AnnaBridge 167:84c0a372a020 550 */
AnnaBridge 167:84c0a372a020 551
AnnaBridge 167:84c0a372a020 552 /**
AnnaBridge 167:84c0a372a020 553 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 167:84c0a372a020 554 */
AnnaBridge 167:84c0a372a020 555 typedef struct
AnnaBridge 167:84c0a372a020 556 {
AnnaBridge 167:84c0a372a020 557 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 167:84c0a372a020 558 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 167:84c0a372a020 559 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 167:84c0a372a020 560 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 167:84c0a372a020 561 } SysTick_Type;
AnnaBridge 167:84c0a372a020 562
AnnaBridge 167:84c0a372a020 563 /* SysTick Control / Status Register Definitions */
AnnaBridge 167:84c0a372a020 564 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 167:84c0a372a020 565 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 167:84c0a372a020 566
AnnaBridge 167:84c0a372a020 567 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 167:84c0a372a020 568 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 167:84c0a372a020 569
AnnaBridge 167:84c0a372a020 570 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 167:84c0a372a020 571 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 167:84c0a372a020 572
AnnaBridge 167:84c0a372a020 573 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 167:84c0a372a020 574 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 167:84c0a372a020 575
AnnaBridge 167:84c0a372a020 576 /* SysTick Reload Register Definitions */
AnnaBridge 167:84c0a372a020 577 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 167:84c0a372a020 578 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 167:84c0a372a020 579
AnnaBridge 167:84c0a372a020 580 /* SysTick Current Register Definitions */
AnnaBridge 167:84c0a372a020 581 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 167:84c0a372a020 582 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 167:84c0a372a020 583
AnnaBridge 167:84c0a372a020 584 /* SysTick Calibration Register Definitions */
AnnaBridge 167:84c0a372a020 585 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 167:84c0a372a020 586 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 167:84c0a372a020 587
AnnaBridge 167:84c0a372a020 588 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 167:84c0a372a020 589 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 167:84c0a372a020 590
AnnaBridge 167:84c0a372a020 591 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 167:84c0a372a020 592 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 167:84c0a372a020 593
AnnaBridge 167:84c0a372a020 594 /*@} end of group CMSIS_SysTick */
AnnaBridge 167:84c0a372a020 595
AnnaBridge 167:84c0a372a020 596
AnnaBridge 167:84c0a372a020 597 /**
AnnaBridge 167:84c0a372a020 598 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 599 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 167:84c0a372a020 600 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 167:84c0a372a020 601 @{
AnnaBridge 167:84c0a372a020 602 */
AnnaBridge 167:84c0a372a020 603
AnnaBridge 167:84c0a372a020 604 /**
AnnaBridge 167:84c0a372a020 605 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 167:84c0a372a020 606 */
AnnaBridge 167:84c0a372a020 607 typedef struct
AnnaBridge 167:84c0a372a020 608 {
AnnaBridge 167:84c0a372a020 609 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 167:84c0a372a020 610 uint32_t RESERVED0[6U];
AnnaBridge 167:84c0a372a020 611 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 167:84c0a372a020 612 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 167:84c0a372a020 613 uint32_t RESERVED1[1U];
AnnaBridge 167:84c0a372a020 614 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 167:84c0a372a020 615 uint32_t RESERVED2[1U];
AnnaBridge 167:84c0a372a020 616 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 167:84c0a372a020 617 uint32_t RESERVED3[1U];
AnnaBridge 167:84c0a372a020 618 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 167:84c0a372a020 619 uint32_t RESERVED4[1U];
AnnaBridge 167:84c0a372a020 620 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 167:84c0a372a020 621 uint32_t RESERVED5[1U];
AnnaBridge 167:84c0a372a020 622 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 167:84c0a372a020 623 uint32_t RESERVED6[1U];
AnnaBridge 167:84c0a372a020 624 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 167:84c0a372a020 625 uint32_t RESERVED7[1U];
AnnaBridge 167:84c0a372a020 626 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 167:84c0a372a020 627 uint32_t RESERVED8[1U];
AnnaBridge 167:84c0a372a020 628 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
AnnaBridge 167:84c0a372a020 629 uint32_t RESERVED9[1U];
AnnaBridge 167:84c0a372a020 630 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
AnnaBridge 167:84c0a372a020 631 uint32_t RESERVED10[1U];
AnnaBridge 167:84c0a372a020 632 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
AnnaBridge 167:84c0a372a020 633 uint32_t RESERVED11[1U];
AnnaBridge 167:84c0a372a020 634 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
AnnaBridge 167:84c0a372a020 635 uint32_t RESERVED12[1U];
AnnaBridge 167:84c0a372a020 636 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
AnnaBridge 167:84c0a372a020 637 uint32_t RESERVED13[1U];
AnnaBridge 167:84c0a372a020 638 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
AnnaBridge 167:84c0a372a020 639 uint32_t RESERVED14[1U];
AnnaBridge 167:84c0a372a020 640 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
AnnaBridge 167:84c0a372a020 641 uint32_t RESERVED15[1U];
AnnaBridge 167:84c0a372a020 642 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
AnnaBridge 167:84c0a372a020 643 uint32_t RESERVED16[1U];
AnnaBridge 167:84c0a372a020 644 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
AnnaBridge 167:84c0a372a020 645 uint32_t RESERVED17[1U];
AnnaBridge 167:84c0a372a020 646 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
AnnaBridge 167:84c0a372a020 647 uint32_t RESERVED18[1U];
AnnaBridge 167:84c0a372a020 648 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
AnnaBridge 167:84c0a372a020 649 uint32_t RESERVED19[1U];
AnnaBridge 167:84c0a372a020 650 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
AnnaBridge 167:84c0a372a020 651 uint32_t RESERVED20[1U];
AnnaBridge 167:84c0a372a020 652 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
AnnaBridge 167:84c0a372a020 653 uint32_t RESERVED21[1U];
AnnaBridge 167:84c0a372a020 654 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
AnnaBridge 167:84c0a372a020 655 uint32_t RESERVED22[1U];
AnnaBridge 167:84c0a372a020 656 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
AnnaBridge 167:84c0a372a020 657 uint32_t RESERVED23[1U];
AnnaBridge 167:84c0a372a020 658 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
AnnaBridge 167:84c0a372a020 659 uint32_t RESERVED24[1U];
AnnaBridge 167:84c0a372a020 660 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
AnnaBridge 167:84c0a372a020 661 uint32_t RESERVED25[1U];
AnnaBridge 167:84c0a372a020 662 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
AnnaBridge 167:84c0a372a020 663 uint32_t RESERVED26[1U];
AnnaBridge 167:84c0a372a020 664 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
AnnaBridge 167:84c0a372a020 665 uint32_t RESERVED27[1U];
AnnaBridge 167:84c0a372a020 666 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
AnnaBridge 167:84c0a372a020 667 uint32_t RESERVED28[1U];
AnnaBridge 167:84c0a372a020 668 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
AnnaBridge 167:84c0a372a020 669 uint32_t RESERVED29[1U];
AnnaBridge 167:84c0a372a020 670 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
AnnaBridge 167:84c0a372a020 671 uint32_t RESERVED30[1U];
AnnaBridge 167:84c0a372a020 672 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
AnnaBridge 167:84c0a372a020 673 uint32_t RESERVED31[1U];
AnnaBridge 167:84c0a372a020 674 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
AnnaBridge 167:84c0a372a020 675 } DWT_Type;
AnnaBridge 167:84c0a372a020 676
AnnaBridge 167:84c0a372a020 677 /* DWT Control Register Definitions */
AnnaBridge 167:84c0a372a020 678 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 167:84c0a372a020 679 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 167:84c0a372a020 680
AnnaBridge 167:84c0a372a020 681 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 167:84c0a372a020 682 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 167:84c0a372a020 683
AnnaBridge 167:84c0a372a020 684 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 167:84c0a372a020 685 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 167:84c0a372a020 686
AnnaBridge 167:84c0a372a020 687 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 167:84c0a372a020 688 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 167:84c0a372a020 689
AnnaBridge 167:84c0a372a020 690 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 167:84c0a372a020 691 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 167:84c0a372a020 692
AnnaBridge 167:84c0a372a020 693 /* DWT Comparator Function Register Definitions */
AnnaBridge 167:84c0a372a020 694 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
AnnaBridge 167:84c0a372a020 695 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
AnnaBridge 167:84c0a372a020 696
AnnaBridge 167:84c0a372a020 697 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 167:84c0a372a020 698 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 167:84c0a372a020 699
AnnaBridge 167:84c0a372a020 700 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 167:84c0a372a020 701 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 167:84c0a372a020 702
AnnaBridge 167:84c0a372a020 703 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
AnnaBridge 167:84c0a372a020 704 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
AnnaBridge 167:84c0a372a020 705
AnnaBridge 167:84c0a372a020 706 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
AnnaBridge 167:84c0a372a020 707 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
AnnaBridge 167:84c0a372a020 708
AnnaBridge 167:84c0a372a020 709 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 167:84c0a372a020 710
AnnaBridge 167:84c0a372a020 711
AnnaBridge 167:84c0a372a020 712 /**
AnnaBridge 167:84c0a372a020 713 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 714 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 167:84c0a372a020 715 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 167:84c0a372a020 716 @{
AnnaBridge 167:84c0a372a020 717 */
AnnaBridge 167:84c0a372a020 718
AnnaBridge 167:84c0a372a020 719 /**
AnnaBridge 167:84c0a372a020 720 \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 167:84c0a372a020 721 */
AnnaBridge 167:84c0a372a020 722 typedef struct
AnnaBridge 167:84c0a372a020 723 {
AnnaBridge 167:84c0a372a020 724 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 167:84c0a372a020 725 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 167:84c0a372a020 726 uint32_t RESERVED0[2U];
AnnaBridge 167:84c0a372a020 727 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 167:84c0a372a020 728 uint32_t RESERVED1[55U];
AnnaBridge 167:84c0a372a020 729 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 167:84c0a372a020 730 uint32_t RESERVED2[131U];
AnnaBridge 167:84c0a372a020 731 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 167:84c0a372a020 732 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 167:84c0a372a020 733 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 167:84c0a372a020 734 uint32_t RESERVED3[759U];
AnnaBridge 167:84c0a372a020 735 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 167:84c0a372a020 736 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 167:84c0a372a020 737 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 167:84c0a372a020 738 uint32_t RESERVED4[1U];
AnnaBridge 167:84c0a372a020 739 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 167:84c0a372a020 740 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 167:84c0a372a020 741 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 167:84c0a372a020 742 uint32_t RESERVED5[39U];
AnnaBridge 167:84c0a372a020 743 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 167:84c0a372a020 744 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 167:84c0a372a020 745 uint32_t RESERVED7[8U];
AnnaBridge 167:84c0a372a020 746 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 167:84c0a372a020 747 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
AnnaBridge 167:84c0a372a020 748 } TPI_Type;
AnnaBridge 167:84c0a372a020 749
AnnaBridge 167:84c0a372a020 750 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 167:84c0a372a020 751 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
AnnaBridge 167:84c0a372a020 752 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
AnnaBridge 167:84c0a372a020 753
AnnaBridge 167:84c0a372a020 754 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 167:84c0a372a020 755 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
AnnaBridge 167:84c0a372a020 756 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 167:84c0a372a020 757
AnnaBridge 167:84c0a372a020 758 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 167:84c0a372a020 759 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 167:84c0a372a020 760 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 167:84c0a372a020 761
AnnaBridge 167:84c0a372a020 762 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
AnnaBridge 167:84c0a372a020 763 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 167:84c0a372a020 764
AnnaBridge 167:84c0a372a020 765 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
AnnaBridge 167:84c0a372a020 766 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 167:84c0a372a020 767
AnnaBridge 167:84c0a372a020 768 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
AnnaBridge 167:84c0a372a020 769 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 167:84c0a372a020 770
AnnaBridge 167:84c0a372a020 771 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 167:84c0a372a020 772 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
AnnaBridge 167:84c0a372a020 773 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 167:84c0a372a020 774
AnnaBridge 167:84c0a372a020 775 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
AnnaBridge 167:84c0a372a020 776 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 167:84c0a372a020 777
AnnaBridge 167:84c0a372a020 778 /* TPI TRIGGER Register Definitions */
AnnaBridge 167:84c0a372a020 779 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
AnnaBridge 167:84c0a372a020 780 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
AnnaBridge 167:84c0a372a020 781
AnnaBridge 167:84c0a372a020 782 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 167:84c0a372a020 783 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
AnnaBridge 167:84c0a372a020 784 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
AnnaBridge 167:84c0a372a020 785
AnnaBridge 167:84c0a372a020 786 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
AnnaBridge 167:84c0a372a020 787 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
AnnaBridge 167:84c0a372a020 788
AnnaBridge 167:84c0a372a020 789 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
AnnaBridge 167:84c0a372a020 790 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
AnnaBridge 167:84c0a372a020 791
AnnaBridge 167:84c0a372a020 792 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
AnnaBridge 167:84c0a372a020 793 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
AnnaBridge 167:84c0a372a020 794
AnnaBridge 167:84c0a372a020 795 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
AnnaBridge 167:84c0a372a020 796 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
AnnaBridge 167:84c0a372a020 797
AnnaBridge 167:84c0a372a020 798 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
AnnaBridge 167:84c0a372a020 799 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
AnnaBridge 167:84c0a372a020 800
AnnaBridge 167:84c0a372a020 801 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
AnnaBridge 167:84c0a372a020 802 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
AnnaBridge 167:84c0a372a020 803
AnnaBridge 167:84c0a372a020 804 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 167:84c0a372a020 805 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
AnnaBridge 167:84c0a372a020 806 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
AnnaBridge 167:84c0a372a020 807
AnnaBridge 167:84c0a372a020 808 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 167:84c0a372a020 809 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
AnnaBridge 167:84c0a372a020 810 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
AnnaBridge 167:84c0a372a020 811
AnnaBridge 167:84c0a372a020 812 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
AnnaBridge 167:84c0a372a020 813 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
AnnaBridge 167:84c0a372a020 814
AnnaBridge 167:84c0a372a020 815 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
AnnaBridge 167:84c0a372a020 816 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
AnnaBridge 167:84c0a372a020 817
AnnaBridge 167:84c0a372a020 818 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
AnnaBridge 167:84c0a372a020 819 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
AnnaBridge 167:84c0a372a020 820
AnnaBridge 167:84c0a372a020 821 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
AnnaBridge 167:84c0a372a020 822 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
AnnaBridge 167:84c0a372a020 823
AnnaBridge 167:84c0a372a020 824 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
AnnaBridge 167:84c0a372a020 825 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
AnnaBridge 167:84c0a372a020 826
AnnaBridge 167:84c0a372a020 827 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
AnnaBridge 167:84c0a372a020 828 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
AnnaBridge 167:84c0a372a020 829
AnnaBridge 167:84c0a372a020 830 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 167:84c0a372a020 831 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
AnnaBridge 167:84c0a372a020 832 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
AnnaBridge 167:84c0a372a020 833
AnnaBridge 167:84c0a372a020 834 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 167:84c0a372a020 835 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
AnnaBridge 167:84c0a372a020 836 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
AnnaBridge 167:84c0a372a020 837
AnnaBridge 167:84c0a372a020 838 /* TPI DEVID Register Definitions */
AnnaBridge 167:84c0a372a020 839 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 167:84c0a372a020 840 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 167:84c0a372a020 841
AnnaBridge 167:84c0a372a020 842 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 167:84c0a372a020 843 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 167:84c0a372a020 844
AnnaBridge 167:84c0a372a020 845 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 167:84c0a372a020 846 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 167:84c0a372a020 847
AnnaBridge 167:84c0a372a020 848 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
AnnaBridge 167:84c0a372a020 849 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
AnnaBridge 167:84c0a372a020 850
AnnaBridge 167:84c0a372a020 851 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
AnnaBridge 167:84c0a372a020 852 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
AnnaBridge 167:84c0a372a020 853
AnnaBridge 167:84c0a372a020 854 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 167:84c0a372a020 855 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
AnnaBridge 167:84c0a372a020 856
AnnaBridge 167:84c0a372a020 857 /* TPI DEVTYPE Register Definitions */
AnnaBridge 167:84c0a372a020 858 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 167:84c0a372a020 859 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 167:84c0a372a020 860
AnnaBridge 167:84c0a372a020 861 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 167:84c0a372a020 862 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 167:84c0a372a020 863
AnnaBridge 167:84c0a372a020 864 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 167:84c0a372a020 865
AnnaBridge 167:84c0a372a020 866
AnnaBridge 167:84c0a372a020 867 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 167:84c0a372a020 868 /**
AnnaBridge 167:84c0a372a020 869 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 870 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 167:84c0a372a020 871 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 167:84c0a372a020 872 @{
AnnaBridge 167:84c0a372a020 873 */
AnnaBridge 167:84c0a372a020 874
AnnaBridge 167:84c0a372a020 875 /**
AnnaBridge 167:84c0a372a020 876 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 167:84c0a372a020 877 */
AnnaBridge 167:84c0a372a020 878 typedef struct
AnnaBridge 167:84c0a372a020 879 {
AnnaBridge 167:84c0a372a020 880 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 167:84c0a372a020 881 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 167:84c0a372a020 882 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
AnnaBridge 167:84c0a372a020 883 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 167:84c0a372a020 884 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
AnnaBridge 167:84c0a372a020 885 uint32_t RESERVED0[7U];
AnnaBridge 167:84c0a372a020 886 union {
AnnaBridge 167:84c0a372a020 887 __IOM uint32_t MAIR[2];
AnnaBridge 167:84c0a372a020 888 struct {
AnnaBridge 167:84c0a372a020 889 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
AnnaBridge 167:84c0a372a020 890 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
AnnaBridge 167:84c0a372a020 891 };
AnnaBridge 167:84c0a372a020 892 };
AnnaBridge 167:84c0a372a020 893 } MPU_Type;
AnnaBridge 167:84c0a372a020 894
AnnaBridge 167:84c0a372a020 895 #define MPU_TYPE_RALIASES 1U
AnnaBridge 167:84c0a372a020 896
AnnaBridge 167:84c0a372a020 897 /* MPU Type Register Definitions */
AnnaBridge 167:84c0a372a020 898 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 167:84c0a372a020 899 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 167:84c0a372a020 900
AnnaBridge 167:84c0a372a020 901 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 167:84c0a372a020 902 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 167:84c0a372a020 903
AnnaBridge 167:84c0a372a020 904 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 167:84c0a372a020 905 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 167:84c0a372a020 906
AnnaBridge 167:84c0a372a020 907 /* MPU Control Register Definitions */
AnnaBridge 167:84c0a372a020 908 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 167:84c0a372a020 909 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 167:84c0a372a020 910
AnnaBridge 167:84c0a372a020 911 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 167:84c0a372a020 912 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 167:84c0a372a020 913
AnnaBridge 167:84c0a372a020 914 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 167:84c0a372a020 915 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 167:84c0a372a020 916
AnnaBridge 167:84c0a372a020 917 /* MPU Region Number Register Definitions */
AnnaBridge 167:84c0a372a020 918 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 167:84c0a372a020 919 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 167:84c0a372a020 920
AnnaBridge 167:84c0a372a020 921 /* MPU Region Base Address Register Definitions */
AnnaBridge 167:84c0a372a020 922 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
AnnaBridge 167:84c0a372a020 923 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
AnnaBridge 167:84c0a372a020 924
AnnaBridge 167:84c0a372a020 925 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
AnnaBridge 167:84c0a372a020 926 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
AnnaBridge 167:84c0a372a020 927
AnnaBridge 167:84c0a372a020 928 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
AnnaBridge 167:84c0a372a020 929 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
AnnaBridge 167:84c0a372a020 930
AnnaBridge 167:84c0a372a020 931 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
AnnaBridge 167:84c0a372a020 932 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
AnnaBridge 167:84c0a372a020 933
AnnaBridge 167:84c0a372a020 934 /* MPU Region Limit Address Register Definitions */
AnnaBridge 167:84c0a372a020 935 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
AnnaBridge 167:84c0a372a020 936 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
AnnaBridge 167:84c0a372a020 937
AnnaBridge 167:84c0a372a020 938 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
AnnaBridge 167:84c0a372a020 939 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
AnnaBridge 167:84c0a372a020 940
AnnaBridge 167:84c0a372a020 941 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
AnnaBridge 167:84c0a372a020 942 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
AnnaBridge 167:84c0a372a020 943
AnnaBridge 167:84c0a372a020 944 /* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge 167:84c0a372a020 945 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
AnnaBridge 167:84c0a372a020 946 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
AnnaBridge 167:84c0a372a020 947
AnnaBridge 167:84c0a372a020 948 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
AnnaBridge 167:84c0a372a020 949 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
AnnaBridge 167:84c0a372a020 950
AnnaBridge 167:84c0a372a020 951 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
AnnaBridge 167:84c0a372a020 952 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
AnnaBridge 167:84c0a372a020 953
AnnaBridge 167:84c0a372a020 954 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
AnnaBridge 167:84c0a372a020 955 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
AnnaBridge 167:84c0a372a020 956
AnnaBridge 167:84c0a372a020 957 /* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge 167:84c0a372a020 958 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
AnnaBridge 167:84c0a372a020 959 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
AnnaBridge 167:84c0a372a020 960
AnnaBridge 167:84c0a372a020 961 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
AnnaBridge 167:84c0a372a020 962 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
AnnaBridge 167:84c0a372a020 963
AnnaBridge 167:84c0a372a020 964 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
AnnaBridge 167:84c0a372a020 965 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
AnnaBridge 167:84c0a372a020 966
AnnaBridge 167:84c0a372a020 967 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
AnnaBridge 167:84c0a372a020 968 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
AnnaBridge 167:84c0a372a020 969
AnnaBridge 167:84c0a372a020 970 /*@} end of group CMSIS_MPU */
AnnaBridge 167:84c0a372a020 971 #endif
AnnaBridge 167:84c0a372a020 972
AnnaBridge 167:84c0a372a020 973
AnnaBridge 167:84c0a372a020 974 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 167:84c0a372a020 975 /**
AnnaBridge 167:84c0a372a020 976 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 977 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge 167:84c0a372a020 978 \brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge 167:84c0a372a020 979 @{
AnnaBridge 167:84c0a372a020 980 */
AnnaBridge 167:84c0a372a020 981
AnnaBridge 167:84c0a372a020 982 /**
AnnaBridge 167:84c0a372a020 983 \brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge 167:84c0a372a020 984 */
AnnaBridge 167:84c0a372a020 985 typedef struct
AnnaBridge 167:84c0a372a020 986 {
AnnaBridge 167:84c0a372a020 987 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
AnnaBridge 167:84c0a372a020 988 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
AnnaBridge 167:84c0a372a020 989 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge 167:84c0a372a020 990 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
AnnaBridge 167:84c0a372a020 991 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
AnnaBridge 167:84c0a372a020 992 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
AnnaBridge 167:84c0a372a020 993 #endif
AnnaBridge 167:84c0a372a020 994 } SAU_Type;
AnnaBridge 167:84c0a372a020 995
AnnaBridge 167:84c0a372a020 996 /* SAU Control Register Definitions */
AnnaBridge 167:84c0a372a020 997 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
AnnaBridge 167:84c0a372a020 998 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
AnnaBridge 167:84c0a372a020 999
AnnaBridge 167:84c0a372a020 1000 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
AnnaBridge 167:84c0a372a020 1001 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
AnnaBridge 167:84c0a372a020 1002
AnnaBridge 167:84c0a372a020 1003 /* SAU Type Register Definitions */
AnnaBridge 167:84c0a372a020 1004 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
AnnaBridge 167:84c0a372a020 1005 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
AnnaBridge 167:84c0a372a020 1006
AnnaBridge 167:84c0a372a020 1007 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge 167:84c0a372a020 1008 /* SAU Region Number Register Definitions */
AnnaBridge 167:84c0a372a020 1009 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
AnnaBridge 167:84c0a372a020 1010 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
AnnaBridge 167:84c0a372a020 1011
AnnaBridge 167:84c0a372a020 1012 /* SAU Region Base Address Register Definitions */
AnnaBridge 167:84c0a372a020 1013 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
AnnaBridge 167:84c0a372a020 1014 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
AnnaBridge 167:84c0a372a020 1015
AnnaBridge 167:84c0a372a020 1016 /* SAU Region Limit Address Register Definitions */
AnnaBridge 167:84c0a372a020 1017 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
AnnaBridge 167:84c0a372a020 1018 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
AnnaBridge 167:84c0a372a020 1019
AnnaBridge 167:84c0a372a020 1020 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
AnnaBridge 167:84c0a372a020 1021 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
AnnaBridge 167:84c0a372a020 1022
AnnaBridge 167:84c0a372a020 1023 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
AnnaBridge 167:84c0a372a020 1024 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
AnnaBridge 167:84c0a372a020 1025
AnnaBridge 167:84c0a372a020 1026 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge 167:84c0a372a020 1027
AnnaBridge 167:84c0a372a020 1028 /*@} end of group CMSIS_SAU */
AnnaBridge 167:84c0a372a020 1029 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 167:84c0a372a020 1030
AnnaBridge 167:84c0a372a020 1031
AnnaBridge 167:84c0a372a020 1032 /**
AnnaBridge 167:84c0a372a020 1033 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 1034 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 167:84c0a372a020 1035 \brief Type definitions for the Core Debug Registers
AnnaBridge 167:84c0a372a020 1036 @{
AnnaBridge 167:84c0a372a020 1037 */
AnnaBridge 167:84c0a372a020 1038
AnnaBridge 167:84c0a372a020 1039 /**
AnnaBridge 167:84c0a372a020 1040 \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 167:84c0a372a020 1041 */
AnnaBridge 167:84c0a372a020 1042 typedef struct
AnnaBridge 167:84c0a372a020 1043 {
AnnaBridge 167:84c0a372a020 1044 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 167:84c0a372a020 1045 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 167:84c0a372a020 1046 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 167:84c0a372a020 1047 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 167:84c0a372a020 1048 uint32_t RESERVED4[1U];
AnnaBridge 167:84c0a372a020 1049 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
AnnaBridge 167:84c0a372a020 1050 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
AnnaBridge 167:84c0a372a020 1051 } CoreDebug_Type;
AnnaBridge 167:84c0a372a020 1052
AnnaBridge 167:84c0a372a020 1053 /* Debug Halting Control and Status Register Definitions */
AnnaBridge 167:84c0a372a020 1054 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 167:84c0a372a020 1055 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 167:84c0a372a020 1056
AnnaBridge 167:84c0a372a020 1057 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
AnnaBridge 167:84c0a372a020 1058 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
AnnaBridge 167:84c0a372a020 1059
AnnaBridge 167:84c0a372a020 1060 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 167:84c0a372a020 1061 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 167:84c0a372a020 1062
AnnaBridge 167:84c0a372a020 1063 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 167:84c0a372a020 1064 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 167:84c0a372a020 1065
AnnaBridge 167:84c0a372a020 1066 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 167:84c0a372a020 1067 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 167:84c0a372a020 1068
AnnaBridge 167:84c0a372a020 1069 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 167:84c0a372a020 1070 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 167:84c0a372a020 1071
AnnaBridge 167:84c0a372a020 1072 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 167:84c0a372a020 1073 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 167:84c0a372a020 1074
AnnaBridge 167:84c0a372a020 1075 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 167:84c0a372a020 1076 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 167:84c0a372a020 1077
AnnaBridge 167:84c0a372a020 1078 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 167:84c0a372a020 1079 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 167:84c0a372a020 1080
AnnaBridge 167:84c0a372a020 1081 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 167:84c0a372a020 1082 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 167:84c0a372a020 1083
AnnaBridge 167:84c0a372a020 1084 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 167:84c0a372a020 1085 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 167:84c0a372a020 1086
AnnaBridge 167:84c0a372a020 1087 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 167:84c0a372a020 1088 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 167:84c0a372a020 1089
AnnaBridge 167:84c0a372a020 1090 /* Debug Core Register Selector Register Definitions */
AnnaBridge 167:84c0a372a020 1091 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 167:84c0a372a020 1092 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 167:84c0a372a020 1093
AnnaBridge 167:84c0a372a020 1094 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 167:84c0a372a020 1095 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 167:84c0a372a020 1096
AnnaBridge 167:84c0a372a020 1097 /* Debug Exception and Monitor Control Register */
AnnaBridge 167:84c0a372a020 1098 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
AnnaBridge 167:84c0a372a020 1099 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
AnnaBridge 167:84c0a372a020 1100
AnnaBridge 167:84c0a372a020 1101 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 167:84c0a372a020 1102 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 167:84c0a372a020 1103
AnnaBridge 167:84c0a372a020 1104 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 167:84c0a372a020 1105 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 167:84c0a372a020 1106
AnnaBridge 167:84c0a372a020 1107 /* Debug Authentication Control Register Definitions */
AnnaBridge 167:84c0a372a020 1108 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
AnnaBridge 167:84c0a372a020 1109 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
AnnaBridge 167:84c0a372a020 1110
AnnaBridge 167:84c0a372a020 1111 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
AnnaBridge 167:84c0a372a020 1112 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
AnnaBridge 167:84c0a372a020 1113
AnnaBridge 167:84c0a372a020 1114 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
AnnaBridge 167:84c0a372a020 1115 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
AnnaBridge 167:84c0a372a020 1116
AnnaBridge 167:84c0a372a020 1117 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
AnnaBridge 167:84c0a372a020 1118 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
AnnaBridge 167:84c0a372a020 1119
AnnaBridge 167:84c0a372a020 1120 /* Debug Security Control and Status Register Definitions */
AnnaBridge 167:84c0a372a020 1121 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
AnnaBridge 167:84c0a372a020 1122 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
AnnaBridge 167:84c0a372a020 1123
AnnaBridge 167:84c0a372a020 1124 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
AnnaBridge 167:84c0a372a020 1125 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
AnnaBridge 167:84c0a372a020 1126
AnnaBridge 167:84c0a372a020 1127 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
AnnaBridge 167:84c0a372a020 1128 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
AnnaBridge 167:84c0a372a020 1129
AnnaBridge 167:84c0a372a020 1130 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 167:84c0a372a020 1131
AnnaBridge 167:84c0a372a020 1132
AnnaBridge 167:84c0a372a020 1133 /**
AnnaBridge 167:84c0a372a020 1134 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 1135 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 167:84c0a372a020 1136 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 167:84c0a372a020 1137 @{
AnnaBridge 167:84c0a372a020 1138 */
AnnaBridge 167:84c0a372a020 1139
AnnaBridge 167:84c0a372a020 1140 /**
AnnaBridge 167:84c0a372a020 1141 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 167:84c0a372a020 1142 \param[in] field Name of the register bit field.
AnnaBridge 167:84c0a372a020 1143 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:84c0a372a020 1144 \return Masked and shifted value.
AnnaBridge 167:84c0a372a020 1145 */
AnnaBridge 167:84c0a372a020 1146 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 167:84c0a372a020 1147
AnnaBridge 167:84c0a372a020 1148 /**
AnnaBridge 167:84c0a372a020 1149 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 167:84c0a372a020 1150 \param[in] field Name of the register bit field.
AnnaBridge 167:84c0a372a020 1151 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:84c0a372a020 1152 \return Masked and shifted bit field value.
AnnaBridge 167:84c0a372a020 1153 */
AnnaBridge 167:84c0a372a020 1154 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 167:84c0a372a020 1155
AnnaBridge 167:84c0a372a020 1156 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 167:84c0a372a020 1157
AnnaBridge 167:84c0a372a020 1158
AnnaBridge 167:84c0a372a020 1159 /**
AnnaBridge 167:84c0a372a020 1160 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 1161 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 167:84c0a372a020 1162 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 167:84c0a372a020 1163 @{
AnnaBridge 167:84c0a372a020 1164 */
AnnaBridge 167:84c0a372a020 1165
AnnaBridge 167:84c0a372a020 1166 /* Memory mapping of Core Hardware */
AnnaBridge 167:84c0a372a020 1167 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 167:84c0a372a020 1168 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 167:84c0a372a020 1169 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 167:84c0a372a020 1170 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 167:84c0a372a020 1171 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 167:84c0a372a020 1172 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 167:84c0a372a020 1173 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 167:84c0a372a020 1174
AnnaBridge 167:84c0a372a020 1175
AnnaBridge 167:84c0a372a020 1176 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 167:84c0a372a020 1177 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 167:84c0a372a020 1178 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 167:84c0a372a020 1179 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 167:84c0a372a020 1180 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 167:84c0a372a020 1181 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
AnnaBridge 167:84c0a372a020 1182
AnnaBridge 167:84c0a372a020 1183 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 167:84c0a372a020 1184 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 167:84c0a372a020 1185 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 167:84c0a372a020 1186 #endif
AnnaBridge 167:84c0a372a020 1187
AnnaBridge 167:84c0a372a020 1188 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 167:84c0a372a020 1189 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
AnnaBridge 167:84c0a372a020 1190 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
AnnaBridge 167:84c0a372a020 1191 #endif
AnnaBridge 167:84c0a372a020 1192
AnnaBridge 167:84c0a372a020 1193 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 167:84c0a372a020 1194 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
AnnaBridge 167:84c0a372a020 1195 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
AnnaBridge 167:84c0a372a020 1196 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
AnnaBridge 167:84c0a372a020 1197 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
AnnaBridge 167:84c0a372a020 1198 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
AnnaBridge 167:84c0a372a020 1199
AnnaBridge 167:84c0a372a020 1200 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
AnnaBridge 167:84c0a372a020 1201 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
AnnaBridge 167:84c0a372a020 1202 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
AnnaBridge 167:84c0a372a020 1203 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
AnnaBridge 167:84c0a372a020 1204
AnnaBridge 167:84c0a372a020 1205 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 167:84c0a372a020 1206 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
AnnaBridge 167:84c0a372a020 1207 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
AnnaBridge 167:84c0a372a020 1208 #endif
AnnaBridge 167:84c0a372a020 1209
AnnaBridge 167:84c0a372a020 1210 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 167:84c0a372a020 1211 /*@} */
AnnaBridge 167:84c0a372a020 1212
AnnaBridge 167:84c0a372a020 1213
AnnaBridge 167:84c0a372a020 1214
AnnaBridge 167:84c0a372a020 1215 /*******************************************************************************
AnnaBridge 167:84c0a372a020 1216 * Hardware Abstraction Layer
AnnaBridge 167:84c0a372a020 1217 Core Function Interface contains:
AnnaBridge 167:84c0a372a020 1218 - Core NVIC Functions
AnnaBridge 167:84c0a372a020 1219 - Core SysTick Functions
AnnaBridge 167:84c0a372a020 1220 - Core Register Access Functions
AnnaBridge 167:84c0a372a020 1221 ******************************************************************************/
AnnaBridge 167:84c0a372a020 1222 /**
AnnaBridge 167:84c0a372a020 1223 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 167:84c0a372a020 1224 */
AnnaBridge 167:84c0a372a020 1225
AnnaBridge 167:84c0a372a020 1226
AnnaBridge 167:84c0a372a020 1227
AnnaBridge 167:84c0a372a020 1228 /* ########################## NVIC functions #################################### */
AnnaBridge 167:84c0a372a020 1229 /**
AnnaBridge 167:84c0a372a020 1230 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:84c0a372a020 1231 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 167:84c0a372a020 1232 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 167:84c0a372a020 1233 @{
AnnaBridge 167:84c0a372a020 1234 */
AnnaBridge 167:84c0a372a020 1235
AnnaBridge 167:84c0a372a020 1236 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 167:84c0a372a020 1237 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 167:84c0a372a020 1238 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 167:84c0a372a020 1239 #endif
AnnaBridge 167:84c0a372a020 1240 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 167:84c0a372a020 1241 #else
Anna Bridge 169:a7c7b631e539 1242 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */
Anna Bridge 169:a7c7b631e539 1243 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */
AnnaBridge 167:84c0a372a020 1244 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 167:84c0a372a020 1245 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 167:84c0a372a020 1246 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 167:84c0a372a020 1247 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 167:84c0a372a020 1248 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 167:84c0a372a020 1249 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 167:84c0a372a020 1250 #define NVIC_GetActive __NVIC_GetActive
AnnaBridge 167:84c0a372a020 1251 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 167:84c0a372a020 1252 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 167:84c0a372a020 1253 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 167:84c0a372a020 1254 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 167:84c0a372a020 1255
AnnaBridge 167:84c0a372a020 1256 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 167:84c0a372a020 1257 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 167:84c0a372a020 1258 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 167:84c0a372a020 1259 #endif
AnnaBridge 167:84c0a372a020 1260 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 167:84c0a372a020 1261 #else
AnnaBridge 167:84c0a372a020 1262 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 167:84c0a372a020 1263 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 167:84c0a372a020 1264 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 167:84c0a372a020 1265
AnnaBridge 167:84c0a372a020 1266 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 167:84c0a372a020 1267
AnnaBridge 167:84c0a372a020 1268
Anna Bridge 169:a7c7b631e539 1269 /* Interrupt Priorities are WORD accessible only under Armv6-M */
AnnaBridge 167:84c0a372a020 1270 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 167:84c0a372a020 1271 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 167:84c0a372a020 1272 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 167:84c0a372a020 1273 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 167:84c0a372a020 1274
AnnaBridge 167:84c0a372a020 1275
AnnaBridge 167:84c0a372a020 1276 /**
AnnaBridge 167:84c0a372a020 1277 \brief Enable Interrupt
AnnaBridge 167:84c0a372a020 1278 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:84c0a372a020 1279 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1280 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1281 */
AnnaBridge 167:84c0a372a020 1282 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1283 {
AnnaBridge 167:84c0a372a020 1284 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1285 {
Anna Bridge 169:a7c7b631e539 1286 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 1287 }
AnnaBridge 167:84c0a372a020 1288 }
AnnaBridge 167:84c0a372a020 1289
AnnaBridge 167:84c0a372a020 1290
AnnaBridge 167:84c0a372a020 1291 /**
AnnaBridge 167:84c0a372a020 1292 \brief Get Interrupt Enable status
AnnaBridge 167:84c0a372a020 1293 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 167:84c0a372a020 1294 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1295 \return 0 Interrupt is not enabled.
AnnaBridge 167:84c0a372a020 1296 \return 1 Interrupt is enabled.
AnnaBridge 167:84c0a372a020 1297 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1298 */
AnnaBridge 167:84c0a372a020 1299 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1300 {
AnnaBridge 167:84c0a372a020 1301 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1302 {
Anna Bridge 169:a7c7b631e539 1303 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 1304 }
AnnaBridge 167:84c0a372a020 1305 else
AnnaBridge 167:84c0a372a020 1306 {
AnnaBridge 167:84c0a372a020 1307 return(0U);
AnnaBridge 167:84c0a372a020 1308 }
AnnaBridge 167:84c0a372a020 1309 }
AnnaBridge 167:84c0a372a020 1310
AnnaBridge 167:84c0a372a020 1311
AnnaBridge 167:84c0a372a020 1312 /**
AnnaBridge 167:84c0a372a020 1313 \brief Disable Interrupt
AnnaBridge 167:84c0a372a020 1314 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:84c0a372a020 1315 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1316 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1317 */
AnnaBridge 167:84c0a372a020 1318 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1319 {
AnnaBridge 167:84c0a372a020 1320 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1321 {
Anna Bridge 169:a7c7b631e539 1322 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 1323 __DSB();
AnnaBridge 167:84c0a372a020 1324 __ISB();
AnnaBridge 167:84c0a372a020 1325 }
AnnaBridge 167:84c0a372a020 1326 }
AnnaBridge 167:84c0a372a020 1327
AnnaBridge 167:84c0a372a020 1328
AnnaBridge 167:84c0a372a020 1329 /**
AnnaBridge 167:84c0a372a020 1330 \brief Get Pending Interrupt
AnnaBridge 167:84c0a372a020 1331 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 167:84c0a372a020 1332 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1333 \return 0 Interrupt status is not pending.
AnnaBridge 167:84c0a372a020 1334 \return 1 Interrupt status is pending.
AnnaBridge 167:84c0a372a020 1335 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1336 */
AnnaBridge 167:84c0a372a020 1337 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1338 {
AnnaBridge 167:84c0a372a020 1339 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1340 {
Anna Bridge 169:a7c7b631e539 1341 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 1342 }
AnnaBridge 167:84c0a372a020 1343 else
AnnaBridge 167:84c0a372a020 1344 {
AnnaBridge 167:84c0a372a020 1345 return(0U);
AnnaBridge 167:84c0a372a020 1346 }
AnnaBridge 167:84c0a372a020 1347 }
AnnaBridge 167:84c0a372a020 1348
AnnaBridge 167:84c0a372a020 1349
AnnaBridge 167:84c0a372a020 1350 /**
AnnaBridge 167:84c0a372a020 1351 \brief Set Pending Interrupt
AnnaBridge 167:84c0a372a020 1352 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:84c0a372a020 1353 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1354 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1355 */
AnnaBridge 167:84c0a372a020 1356 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1357 {
AnnaBridge 167:84c0a372a020 1358 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1359 {
Anna Bridge 169:a7c7b631e539 1360 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 1361 }
AnnaBridge 167:84c0a372a020 1362 }
AnnaBridge 167:84c0a372a020 1363
AnnaBridge 167:84c0a372a020 1364
AnnaBridge 167:84c0a372a020 1365 /**
AnnaBridge 167:84c0a372a020 1366 \brief Clear Pending Interrupt
AnnaBridge 167:84c0a372a020 1367 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:84c0a372a020 1368 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1369 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1370 */
AnnaBridge 167:84c0a372a020 1371 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1372 {
AnnaBridge 167:84c0a372a020 1373 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1374 {
Anna Bridge 169:a7c7b631e539 1375 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 1376 }
AnnaBridge 167:84c0a372a020 1377 }
AnnaBridge 167:84c0a372a020 1378
AnnaBridge 167:84c0a372a020 1379
AnnaBridge 167:84c0a372a020 1380 /**
AnnaBridge 167:84c0a372a020 1381 \brief Get Active Interrupt
AnnaBridge 167:84c0a372a020 1382 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge 167:84c0a372a020 1383 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1384 \return 0 Interrupt status is not active.
AnnaBridge 167:84c0a372a020 1385 \return 1 Interrupt status is active.
AnnaBridge 167:84c0a372a020 1386 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1387 */
AnnaBridge 167:84c0a372a020 1388 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1389 {
AnnaBridge 167:84c0a372a020 1390 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1391 {
Anna Bridge 169:a7c7b631e539 1392 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 1393 }
AnnaBridge 167:84c0a372a020 1394 else
AnnaBridge 167:84c0a372a020 1395 {
AnnaBridge 167:84c0a372a020 1396 return(0U);
AnnaBridge 167:84c0a372a020 1397 }
AnnaBridge 167:84c0a372a020 1398 }
AnnaBridge 167:84c0a372a020 1399
AnnaBridge 167:84c0a372a020 1400
AnnaBridge 167:84c0a372a020 1401 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 167:84c0a372a020 1402 /**
AnnaBridge 167:84c0a372a020 1403 \brief Get Interrupt Target State
AnnaBridge 167:84c0a372a020 1404 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 167:84c0a372a020 1405 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1406 \return 0 if interrupt is assigned to Secure
AnnaBridge 167:84c0a372a020 1407 \return 1 if interrupt is assigned to Non Secure
AnnaBridge 167:84c0a372a020 1408 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1409 */
AnnaBridge 167:84c0a372a020 1410 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1411 {
AnnaBridge 167:84c0a372a020 1412 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1413 {
Anna Bridge 169:a7c7b631e539 1414 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 1415 }
AnnaBridge 167:84c0a372a020 1416 else
AnnaBridge 167:84c0a372a020 1417 {
AnnaBridge 167:84c0a372a020 1418 return(0U);
AnnaBridge 167:84c0a372a020 1419 }
AnnaBridge 167:84c0a372a020 1420 }
AnnaBridge 167:84c0a372a020 1421
AnnaBridge 167:84c0a372a020 1422
AnnaBridge 167:84c0a372a020 1423 /**
AnnaBridge 167:84c0a372a020 1424 \brief Set Interrupt Target State
AnnaBridge 167:84c0a372a020 1425 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 167:84c0a372a020 1426 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1427 \return 0 if interrupt is assigned to Secure
AnnaBridge 167:84c0a372a020 1428 1 if interrupt is assigned to Non Secure
AnnaBridge 167:84c0a372a020 1429 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1430 */
AnnaBridge 167:84c0a372a020 1431 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1432 {
AnnaBridge 167:84c0a372a020 1433 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1434 {
Anna Bridge 169:a7c7b631e539 1435 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge 169:a7c7b631e539 1436 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 1437 }
AnnaBridge 167:84c0a372a020 1438 else
AnnaBridge 167:84c0a372a020 1439 {
AnnaBridge 167:84c0a372a020 1440 return(0U);
AnnaBridge 167:84c0a372a020 1441 }
AnnaBridge 167:84c0a372a020 1442 }
AnnaBridge 167:84c0a372a020 1443
AnnaBridge 167:84c0a372a020 1444
AnnaBridge 167:84c0a372a020 1445 /**
AnnaBridge 167:84c0a372a020 1446 \brief Clear Interrupt Target State
AnnaBridge 167:84c0a372a020 1447 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 167:84c0a372a020 1448 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1449 \return 0 if interrupt is assigned to Secure
AnnaBridge 167:84c0a372a020 1450 1 if interrupt is assigned to Non Secure
AnnaBridge 167:84c0a372a020 1451 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1452 */
AnnaBridge 167:84c0a372a020 1453 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1454 {
AnnaBridge 167:84c0a372a020 1455 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1456 {
Anna Bridge 169:a7c7b631e539 1457 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge 169:a7c7b631e539 1458 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 1459 }
AnnaBridge 167:84c0a372a020 1460 else
AnnaBridge 167:84c0a372a020 1461 {
AnnaBridge 167:84c0a372a020 1462 return(0U);
AnnaBridge 167:84c0a372a020 1463 }
AnnaBridge 167:84c0a372a020 1464 }
AnnaBridge 167:84c0a372a020 1465 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 167:84c0a372a020 1466
AnnaBridge 167:84c0a372a020 1467
AnnaBridge 167:84c0a372a020 1468 /**
AnnaBridge 167:84c0a372a020 1469 \brief Set Interrupt Priority
AnnaBridge 167:84c0a372a020 1470 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:84c0a372a020 1471 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 1472 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 1473 \param [in] IRQn Interrupt number.
AnnaBridge 167:84c0a372a020 1474 \param [in] priority Priority to set.
AnnaBridge 167:84c0a372a020 1475 \note The priority cannot be set for every processor exception.
AnnaBridge 167:84c0a372a020 1476 */
AnnaBridge 167:84c0a372a020 1477 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 167:84c0a372a020 1478 {
AnnaBridge 167:84c0a372a020 1479 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1480 {
AnnaBridge 167:84c0a372a020 1481 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 167:84c0a372a020 1482 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 167:84c0a372a020 1483 }
AnnaBridge 167:84c0a372a020 1484 else
AnnaBridge 167:84c0a372a020 1485 {
AnnaBridge 167:84c0a372a020 1486 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 167:84c0a372a020 1487 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 167:84c0a372a020 1488 }
AnnaBridge 167:84c0a372a020 1489 }
AnnaBridge 167:84c0a372a020 1490
AnnaBridge 167:84c0a372a020 1491
AnnaBridge 167:84c0a372a020 1492 /**
AnnaBridge 167:84c0a372a020 1493 \brief Get Interrupt Priority
AnnaBridge 167:84c0a372a020 1494 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:84c0a372a020 1495 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 1496 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 1497 \param [in] IRQn Interrupt number.
AnnaBridge 167:84c0a372a020 1498 \return Interrupt Priority.
AnnaBridge 167:84c0a372a020 1499 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 167:84c0a372a020 1500 */
AnnaBridge 167:84c0a372a020 1501 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1502 {
AnnaBridge 167:84c0a372a020 1503
AnnaBridge 167:84c0a372a020 1504 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1505 {
AnnaBridge 167:84c0a372a020 1506 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 167:84c0a372a020 1507 }
AnnaBridge 167:84c0a372a020 1508 else
AnnaBridge 167:84c0a372a020 1509 {
AnnaBridge 167:84c0a372a020 1510 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 167:84c0a372a020 1511 }
AnnaBridge 167:84c0a372a020 1512 }
AnnaBridge 167:84c0a372a020 1513
AnnaBridge 167:84c0a372a020 1514
AnnaBridge 167:84c0a372a020 1515 /**
AnnaBridge 167:84c0a372a020 1516 \brief Set Interrupt Vector
AnnaBridge 167:84c0a372a020 1517 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 167:84c0a372a020 1518 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 1519 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 1520 VTOR must been relocated to SRAM before.
AnnaBridge 167:84c0a372a020 1521 If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge 167:84c0a372a020 1522 \param [in] IRQn Interrupt number
AnnaBridge 167:84c0a372a020 1523 \param [in] vector Address of interrupt handler function
AnnaBridge 167:84c0a372a020 1524 */
AnnaBridge 167:84c0a372a020 1525 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 167:84c0a372a020 1526 {
AnnaBridge 167:84c0a372a020 1527 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 167:84c0a372a020 1528 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 167:84c0a372a020 1529 #else
AnnaBridge 167:84c0a372a020 1530 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 167:84c0a372a020 1531 #endif
AnnaBridge 167:84c0a372a020 1532 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 167:84c0a372a020 1533 }
AnnaBridge 167:84c0a372a020 1534
AnnaBridge 167:84c0a372a020 1535
AnnaBridge 167:84c0a372a020 1536 /**
AnnaBridge 167:84c0a372a020 1537 \brief Get Interrupt Vector
AnnaBridge 167:84c0a372a020 1538 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 167:84c0a372a020 1539 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 1540 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 1541 \param [in] IRQn Interrupt number.
AnnaBridge 167:84c0a372a020 1542 \return Address of interrupt handler function
AnnaBridge 167:84c0a372a020 1543 */
AnnaBridge 167:84c0a372a020 1544 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1545 {
AnnaBridge 167:84c0a372a020 1546 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 167:84c0a372a020 1547 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 167:84c0a372a020 1548 #else
AnnaBridge 167:84c0a372a020 1549 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 167:84c0a372a020 1550 #endif
AnnaBridge 167:84c0a372a020 1551 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 167:84c0a372a020 1552 }
AnnaBridge 167:84c0a372a020 1553
AnnaBridge 167:84c0a372a020 1554
AnnaBridge 167:84c0a372a020 1555 /**
AnnaBridge 167:84c0a372a020 1556 \brief System Reset
AnnaBridge 167:84c0a372a020 1557 \details Initiates a system reset request to reset the MCU.
AnnaBridge 167:84c0a372a020 1558 */
AnnaBridge 167:84c0a372a020 1559 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 167:84c0a372a020 1560 {
AnnaBridge 167:84c0a372a020 1561 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 167:84c0a372a020 1562 buffered write are completed before reset */
AnnaBridge 167:84c0a372a020 1563 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 167:84c0a372a020 1564 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 167:84c0a372a020 1565 __DSB(); /* Ensure completion of memory access */
AnnaBridge 167:84c0a372a020 1566
AnnaBridge 167:84c0a372a020 1567 for(;;) /* wait until reset */
AnnaBridge 167:84c0a372a020 1568 {
AnnaBridge 167:84c0a372a020 1569 __NOP();
AnnaBridge 167:84c0a372a020 1570 }
AnnaBridge 167:84c0a372a020 1571 }
AnnaBridge 167:84c0a372a020 1572
AnnaBridge 167:84c0a372a020 1573 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 167:84c0a372a020 1574 /**
AnnaBridge 167:84c0a372a020 1575 \brief Enable Interrupt (non-secure)
AnnaBridge 167:84c0a372a020 1576 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 167:84c0a372a020 1577 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1578 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1579 */
AnnaBridge 167:84c0a372a020 1580 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1581 {
AnnaBridge 167:84c0a372a020 1582 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1583 {
Anna Bridge 169:a7c7b631e539 1584 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 1585 }
AnnaBridge 167:84c0a372a020 1586 }
AnnaBridge 167:84c0a372a020 1587
AnnaBridge 167:84c0a372a020 1588
AnnaBridge 167:84c0a372a020 1589 /**
AnnaBridge 167:84c0a372a020 1590 \brief Get Interrupt Enable status (non-secure)
AnnaBridge 167:84c0a372a020 1591 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 167:84c0a372a020 1592 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1593 \return 0 Interrupt is not enabled.
AnnaBridge 167:84c0a372a020 1594 \return 1 Interrupt is enabled.
AnnaBridge 167:84c0a372a020 1595 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1596 */
AnnaBridge 167:84c0a372a020 1597 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1598 {
AnnaBridge 167:84c0a372a020 1599 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1600 {
Anna Bridge 169:a7c7b631e539 1601 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 1602 }
AnnaBridge 167:84c0a372a020 1603 else
AnnaBridge 167:84c0a372a020 1604 {
AnnaBridge 167:84c0a372a020 1605 return(0U);
AnnaBridge 167:84c0a372a020 1606 }
AnnaBridge 167:84c0a372a020 1607 }
AnnaBridge 167:84c0a372a020 1608
AnnaBridge 167:84c0a372a020 1609
AnnaBridge 167:84c0a372a020 1610 /**
AnnaBridge 167:84c0a372a020 1611 \brief Disable Interrupt (non-secure)
AnnaBridge 167:84c0a372a020 1612 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 167:84c0a372a020 1613 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1614 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1615 */
AnnaBridge 167:84c0a372a020 1616 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1617 {
AnnaBridge 167:84c0a372a020 1618 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1619 {
Anna Bridge 169:a7c7b631e539 1620 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 1621 }
AnnaBridge 167:84c0a372a020 1622 }
AnnaBridge 167:84c0a372a020 1623
AnnaBridge 167:84c0a372a020 1624
AnnaBridge 167:84c0a372a020 1625 /**
AnnaBridge 167:84c0a372a020 1626 \brief Get Pending Interrupt (non-secure)
AnnaBridge 167:84c0a372a020 1627 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge 167:84c0a372a020 1628 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1629 \return 0 Interrupt status is not pending.
AnnaBridge 167:84c0a372a020 1630 \return 1 Interrupt status is pending.
AnnaBridge 167:84c0a372a020 1631 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1632 */
AnnaBridge 167:84c0a372a020 1633 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1634 {
AnnaBridge 167:84c0a372a020 1635 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1636 {
Anna Bridge 169:a7c7b631e539 1637 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 1638 }
AnnaBridge 167:84c0a372a020 1639 else
AnnaBridge 167:84c0a372a020 1640 {
AnnaBridge 167:84c0a372a020 1641 return(0U);
AnnaBridge 167:84c0a372a020 1642 }
AnnaBridge 167:84c0a372a020 1643 }
AnnaBridge 167:84c0a372a020 1644
AnnaBridge 167:84c0a372a020 1645
AnnaBridge 167:84c0a372a020 1646 /**
AnnaBridge 167:84c0a372a020 1647 \brief Set Pending Interrupt (non-secure)
AnnaBridge 167:84c0a372a020 1648 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge 167:84c0a372a020 1649 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1650 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1651 */
AnnaBridge 167:84c0a372a020 1652 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1653 {
AnnaBridge 167:84c0a372a020 1654 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1655 {
Anna Bridge 169:a7c7b631e539 1656 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 1657 }
AnnaBridge 167:84c0a372a020 1658 }
AnnaBridge 167:84c0a372a020 1659
AnnaBridge 167:84c0a372a020 1660
AnnaBridge 167:84c0a372a020 1661 /**
AnnaBridge 167:84c0a372a020 1662 \brief Clear Pending Interrupt (non-secure)
AnnaBridge 167:84c0a372a020 1663 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge 167:84c0a372a020 1664 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1665 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1666 */
AnnaBridge 167:84c0a372a020 1667 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1668 {
AnnaBridge 167:84c0a372a020 1669 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1670 {
Anna Bridge 169:a7c7b631e539 1671 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 1672 }
AnnaBridge 167:84c0a372a020 1673 }
AnnaBridge 167:84c0a372a020 1674
AnnaBridge 167:84c0a372a020 1675
AnnaBridge 167:84c0a372a020 1676 /**
AnnaBridge 167:84c0a372a020 1677 \brief Get Active Interrupt (non-secure)
AnnaBridge 167:84c0a372a020 1678 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge 167:84c0a372a020 1679 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 1680 \return 0 Interrupt status is not active.
AnnaBridge 167:84c0a372a020 1681 \return 1 Interrupt status is active.
AnnaBridge 167:84c0a372a020 1682 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 1683 */
AnnaBridge 167:84c0a372a020 1684 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1685 {
AnnaBridge 167:84c0a372a020 1686 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1687 {
Anna Bridge 169:a7c7b631e539 1688 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 1689 }
AnnaBridge 167:84c0a372a020 1690 else
AnnaBridge 167:84c0a372a020 1691 {
AnnaBridge 167:84c0a372a020 1692 return(0U);
AnnaBridge 167:84c0a372a020 1693 }
AnnaBridge 167:84c0a372a020 1694 }
AnnaBridge 167:84c0a372a020 1695
AnnaBridge 167:84c0a372a020 1696
AnnaBridge 167:84c0a372a020 1697 /**
AnnaBridge 167:84c0a372a020 1698 \brief Set Interrupt Priority (non-secure)
AnnaBridge 167:84c0a372a020 1699 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge 167:84c0a372a020 1700 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 1701 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 1702 \param [in] IRQn Interrupt number.
AnnaBridge 167:84c0a372a020 1703 \param [in] priority Priority to set.
AnnaBridge 167:84c0a372a020 1704 \note The priority cannot be set for every non-secure processor exception.
AnnaBridge 167:84c0a372a020 1705 */
AnnaBridge 167:84c0a372a020 1706 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 167:84c0a372a020 1707 {
AnnaBridge 167:84c0a372a020 1708 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1709 {
AnnaBridge 167:84c0a372a020 1710 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 167:84c0a372a020 1711 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 167:84c0a372a020 1712 }
AnnaBridge 167:84c0a372a020 1713 else
AnnaBridge 167:84c0a372a020 1714 {
AnnaBridge 167:84c0a372a020 1715 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 167:84c0a372a020 1716 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 167:84c0a372a020 1717 }
AnnaBridge 167:84c0a372a020 1718 }
AnnaBridge 167:84c0a372a020 1719
AnnaBridge 167:84c0a372a020 1720
AnnaBridge 167:84c0a372a020 1721 /**
AnnaBridge 167:84c0a372a020 1722 \brief Get Interrupt Priority (non-secure)
AnnaBridge 167:84c0a372a020 1723 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge 167:84c0a372a020 1724 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 1725 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 1726 \param [in] IRQn Interrupt number.
AnnaBridge 167:84c0a372a020 1727 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 167:84c0a372a020 1728 */
AnnaBridge 167:84c0a372a020 1729 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 1730 {
AnnaBridge 167:84c0a372a020 1731
AnnaBridge 167:84c0a372a020 1732 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 1733 {
AnnaBridge 167:84c0a372a020 1734 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 167:84c0a372a020 1735 }
AnnaBridge 167:84c0a372a020 1736 else
AnnaBridge 167:84c0a372a020 1737 {
AnnaBridge 167:84c0a372a020 1738 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 167:84c0a372a020 1739 }
AnnaBridge 167:84c0a372a020 1740 }
AnnaBridge 167:84c0a372a020 1741 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 167:84c0a372a020 1742
AnnaBridge 167:84c0a372a020 1743 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 167:84c0a372a020 1744
AnnaBridge 167:84c0a372a020 1745 /* ########################## MPU functions #################################### */
AnnaBridge 167:84c0a372a020 1746
AnnaBridge 167:84c0a372a020 1747 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 167:84c0a372a020 1748
AnnaBridge 167:84c0a372a020 1749 #include "mpu_armv8.h"
AnnaBridge 167:84c0a372a020 1750
AnnaBridge 167:84c0a372a020 1751 #endif
AnnaBridge 167:84c0a372a020 1752
AnnaBridge 167:84c0a372a020 1753 /* ########################## FPU functions #################################### */
AnnaBridge 167:84c0a372a020 1754 /**
AnnaBridge 167:84c0a372a020 1755 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:84c0a372a020 1756 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 167:84c0a372a020 1757 \brief Function that provides FPU type.
AnnaBridge 167:84c0a372a020 1758 @{
AnnaBridge 167:84c0a372a020 1759 */
AnnaBridge 167:84c0a372a020 1760
AnnaBridge 167:84c0a372a020 1761 /**
AnnaBridge 167:84c0a372a020 1762 \brief get FPU type
AnnaBridge 167:84c0a372a020 1763 \details returns the FPU type
AnnaBridge 167:84c0a372a020 1764 \returns
AnnaBridge 167:84c0a372a020 1765 - \b 0: No FPU
AnnaBridge 167:84c0a372a020 1766 - \b 1: Single precision FPU
AnnaBridge 167:84c0a372a020 1767 - \b 2: Double + Single precision FPU
AnnaBridge 167:84c0a372a020 1768 */
AnnaBridge 167:84c0a372a020 1769 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 167:84c0a372a020 1770 {
AnnaBridge 167:84c0a372a020 1771 return 0U; /* No FPU */
AnnaBridge 167:84c0a372a020 1772 }
AnnaBridge 167:84c0a372a020 1773
AnnaBridge 167:84c0a372a020 1774
AnnaBridge 167:84c0a372a020 1775 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 167:84c0a372a020 1776
AnnaBridge 167:84c0a372a020 1777
AnnaBridge 167:84c0a372a020 1778
AnnaBridge 167:84c0a372a020 1779 /* ########################## SAU functions #################################### */
AnnaBridge 167:84c0a372a020 1780 /**
AnnaBridge 167:84c0a372a020 1781 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:84c0a372a020 1782 \defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge 167:84c0a372a020 1783 \brief Functions that configure the SAU.
AnnaBridge 167:84c0a372a020 1784 @{
AnnaBridge 167:84c0a372a020 1785 */
AnnaBridge 167:84c0a372a020 1786
AnnaBridge 167:84c0a372a020 1787 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 167:84c0a372a020 1788
AnnaBridge 167:84c0a372a020 1789 /**
AnnaBridge 167:84c0a372a020 1790 \brief Enable SAU
AnnaBridge 167:84c0a372a020 1791 \details Enables the Security Attribution Unit (SAU).
AnnaBridge 167:84c0a372a020 1792 */
AnnaBridge 167:84c0a372a020 1793 __STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge 167:84c0a372a020 1794 {
AnnaBridge 167:84c0a372a020 1795 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
AnnaBridge 167:84c0a372a020 1796 }
AnnaBridge 167:84c0a372a020 1797
AnnaBridge 167:84c0a372a020 1798
AnnaBridge 167:84c0a372a020 1799
AnnaBridge 167:84c0a372a020 1800 /**
AnnaBridge 167:84c0a372a020 1801 \brief Disable SAU
AnnaBridge 167:84c0a372a020 1802 \details Disables the Security Attribution Unit (SAU).
AnnaBridge 167:84c0a372a020 1803 */
AnnaBridge 167:84c0a372a020 1804 __STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge 167:84c0a372a020 1805 {
AnnaBridge 167:84c0a372a020 1806 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge 167:84c0a372a020 1807 }
AnnaBridge 167:84c0a372a020 1808
AnnaBridge 167:84c0a372a020 1809 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 167:84c0a372a020 1810
AnnaBridge 167:84c0a372a020 1811 /*@} end of CMSIS_Core_SAUFunctions */
AnnaBridge 167:84c0a372a020 1812
AnnaBridge 167:84c0a372a020 1813
AnnaBridge 167:84c0a372a020 1814
AnnaBridge 167:84c0a372a020 1815
AnnaBridge 167:84c0a372a020 1816 /* ################################## SysTick function ############################################ */
AnnaBridge 167:84c0a372a020 1817 /**
AnnaBridge 167:84c0a372a020 1818 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:84c0a372a020 1819 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 167:84c0a372a020 1820 \brief Functions that configure the System.
AnnaBridge 167:84c0a372a020 1821 @{
AnnaBridge 167:84c0a372a020 1822 */
AnnaBridge 167:84c0a372a020 1823
AnnaBridge 167:84c0a372a020 1824 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 167:84c0a372a020 1825
AnnaBridge 167:84c0a372a020 1826 /**
AnnaBridge 167:84c0a372a020 1827 \brief System Tick Configuration
AnnaBridge 167:84c0a372a020 1828 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 167:84c0a372a020 1829 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 167:84c0a372a020 1830 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 167:84c0a372a020 1831 \return 0 Function succeeded.
AnnaBridge 167:84c0a372a020 1832 \return 1 Function failed.
AnnaBridge 167:84c0a372a020 1833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 167:84c0a372a020 1834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 167:84c0a372a020 1835 must contain a vendor-specific implementation of this function.
AnnaBridge 167:84c0a372a020 1836 */
AnnaBridge 167:84c0a372a020 1837 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 167:84c0a372a020 1838 {
AnnaBridge 167:84c0a372a020 1839 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 167:84c0a372a020 1840 {
AnnaBridge 167:84c0a372a020 1841 return (1UL); /* Reload value impossible */
AnnaBridge 167:84c0a372a020 1842 }
AnnaBridge 167:84c0a372a020 1843
AnnaBridge 167:84c0a372a020 1844 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 167:84c0a372a020 1845 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 167:84c0a372a020 1846 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 167:84c0a372a020 1847 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 167:84c0a372a020 1848 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 167:84c0a372a020 1849 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 167:84c0a372a020 1850 return (0UL); /* Function successful */
AnnaBridge 167:84c0a372a020 1851 }
AnnaBridge 167:84c0a372a020 1852
AnnaBridge 167:84c0a372a020 1853 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 167:84c0a372a020 1854 /**
AnnaBridge 167:84c0a372a020 1855 \brief System Tick Configuration (non-secure)
AnnaBridge 167:84c0a372a020 1856 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge 167:84c0a372a020 1857 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 167:84c0a372a020 1858 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 167:84c0a372a020 1859 \return 0 Function succeeded.
AnnaBridge 167:84c0a372a020 1860 \return 1 Function failed.
AnnaBridge 167:84c0a372a020 1861 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 167:84c0a372a020 1862 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 167:84c0a372a020 1863 must contain a vendor-specific implementation of this function.
AnnaBridge 167:84c0a372a020 1864
AnnaBridge 167:84c0a372a020 1865 */
AnnaBridge 167:84c0a372a020 1866 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge 167:84c0a372a020 1867 {
AnnaBridge 167:84c0a372a020 1868 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 167:84c0a372a020 1869 {
AnnaBridge 167:84c0a372a020 1870 return (1UL); /* Reload value impossible */
AnnaBridge 167:84c0a372a020 1871 }
AnnaBridge 167:84c0a372a020 1872
AnnaBridge 167:84c0a372a020 1873 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 167:84c0a372a020 1874 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 167:84c0a372a020 1875 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 167:84c0a372a020 1876 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 167:84c0a372a020 1877 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 167:84c0a372a020 1878 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 167:84c0a372a020 1879 return (0UL); /* Function successful */
AnnaBridge 167:84c0a372a020 1880 }
AnnaBridge 167:84c0a372a020 1881 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 167:84c0a372a020 1882
AnnaBridge 167:84c0a372a020 1883 #endif
AnnaBridge 167:84c0a372a020 1884
AnnaBridge 167:84c0a372a020 1885 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 167:84c0a372a020 1886
AnnaBridge 167:84c0a372a020 1887
AnnaBridge 167:84c0a372a020 1888
AnnaBridge 167:84c0a372a020 1889
AnnaBridge 167:84c0a372a020 1890 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 1891 }
AnnaBridge 167:84c0a372a020 1892 #endif
AnnaBridge 167:84c0a372a020 1893
AnnaBridge 167:84c0a372a020 1894 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */
AnnaBridge 167:84c0a372a020 1895
AnnaBridge 167:84c0a372a020 1896 #endif /* __CMSIS_GENERIC */