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TARGET_NUCLEO_F413ZH/core_cm23.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
160:5571c4ff569f 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 160:5571c4ff569f 1 /**************************************************************************//**
Anna Bridge 160:5571c4ff569f 2 * @file core_cm23.h
Anna Bridge 160:5571c4ff569f 3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.4
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
Anna Bridge 160:5571c4ff569f 6 ******************************************************************************/
Anna Bridge 160:5571c4ff569f 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Anna Bridge 160:5571c4ff569f 9 *
Anna Bridge 160:5571c4ff569f 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 160:5571c4ff569f 11 *
Anna Bridge 160:5571c4ff569f 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 160:5571c4ff569f 13 * not use this file except in compliance with the License.
Anna Bridge 160:5571c4ff569f 14 * You may obtain a copy of the License at
Anna Bridge 160:5571c4ff569f 15 *
Anna Bridge 160:5571c4ff569f 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 160:5571c4ff569f 17 *
Anna Bridge 160:5571c4ff569f 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 160:5571c4ff569f 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 160:5571c4ff569f 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 160:5571c4ff569f 21 * See the License for the specific language governing permissions and
Anna Bridge 160:5571c4ff569f 22 * limitations under the License.
Anna Bridge 160:5571c4ff569f 23 */
Anna Bridge 160:5571c4ff569f 24
Anna Bridge 160:5571c4ff569f 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
Anna Bridge 160:5571c4ff569f 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 160:5571c4ff569f 29 #endif
Anna Bridge 160:5571c4ff569f 30
Anna Bridge 160:5571c4ff569f 31 #ifndef __CORE_CM23_H_GENERIC
Anna Bridge 160:5571c4ff569f 32 #define __CORE_CM23_H_GENERIC
Anna Bridge 160:5571c4ff569f 33
Anna Bridge 160:5571c4ff569f 34 #include <stdint.h>
Anna Bridge 160:5571c4ff569f 35
Anna Bridge 160:5571c4ff569f 36 #ifdef __cplusplus
Anna Bridge 160:5571c4ff569f 37 extern "C" {
Anna Bridge 160:5571c4ff569f 38 #endif
Anna Bridge 160:5571c4ff569f 39
Anna Bridge 160:5571c4ff569f 40 /**
Anna Bridge 160:5571c4ff569f 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge 160:5571c4ff569f 42 CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge 160:5571c4ff569f 43
Anna Bridge 160:5571c4ff569f 44 \li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge 160:5571c4ff569f 45 Function definitions in header files are used to allow 'inlining'.
Anna Bridge 160:5571c4ff569f 46
Anna Bridge 160:5571c4ff569f 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge 160:5571c4ff569f 48 Unions are used for effective representation of core registers.
Anna Bridge 160:5571c4ff569f 49
Anna Bridge 160:5571c4ff569f 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge 160:5571c4ff569f 51 Function-like macros are used to allow more efficient code.
Anna Bridge 160:5571c4ff569f 52 */
Anna Bridge 160:5571c4ff569f 53
Anna Bridge 160:5571c4ff569f 54
Anna Bridge 160:5571c4ff569f 55 /*******************************************************************************
Anna Bridge 160:5571c4ff569f 56 * CMSIS definitions
Anna Bridge 160:5571c4ff569f 57 ******************************************************************************/
Anna Bridge 160:5571c4ff569f 58 /**
Anna Bridge 160:5571c4ff569f 59 \ingroup Cortex_M23
Anna Bridge 160:5571c4ff569f 60 @{
Anna Bridge 160:5571c4ff569f 61 */
Anna Bridge 160:5571c4ff569f 62
Anna Bridge 160:5571c4ff569f 63 #include "cmsis_version.h"
Anna Bridge 160:5571c4ff569f 64
Anna Bridge 160:5571c4ff569f 65 /* CMSIS definitions */
Anna Bridge 160:5571c4ff569f 66 #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 160:5571c4ff569f 67 #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
Anna Bridge 160:5571c4ff569f 68 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 160:5571c4ff569f 69 __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
Anna Bridge 160:5571c4ff569f 70
Anna Bridge 160:5571c4ff569f 71 #define __CORTEX_M (23U) /*!< Cortex-M Core */
Anna Bridge 160:5571c4ff569f 72
Anna Bridge 160:5571c4ff569f 73 /** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge 160:5571c4ff569f 74 This core does not support an FPU at all
Anna Bridge 160:5571c4ff569f 75 */
Anna Bridge 160:5571c4ff569f 76 #define __FPU_USED 0U
Anna Bridge 160:5571c4ff569f 77
Anna Bridge 160:5571c4ff569f 78 #if defined ( __CC_ARM )
Anna Bridge 160:5571c4ff569f 79 #if defined __TARGET_FPU_VFP
Anna Bridge 160:5571c4ff569f 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 81 #endif
Anna Bridge 160:5571c4ff569f 82
Anna Bridge 160:5571c4ff569f 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Anna Bridge 160:5571c4ff569f 84 #if defined __ARM_PCS_VFP
Anna Bridge 160:5571c4ff569f 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 86 #endif
Anna Bridge 160:5571c4ff569f 87
Anna Bridge 160:5571c4ff569f 88 #elif defined ( __GNUC__ )
Anna Bridge 160:5571c4ff569f 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge 160:5571c4ff569f 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 91 #endif
Anna Bridge 160:5571c4ff569f 92
Anna Bridge 160:5571c4ff569f 93 #elif defined ( __ICCARM__ )
Anna Bridge 160:5571c4ff569f 94 #if defined __ARMVFP__
Anna Bridge 160:5571c4ff569f 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 96 #endif
Anna Bridge 160:5571c4ff569f 97
Anna Bridge 160:5571c4ff569f 98 #elif defined ( __TI_ARM__ )
Anna Bridge 160:5571c4ff569f 99 #if defined __TI_VFP_SUPPORT__
Anna Bridge 160:5571c4ff569f 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 101 #endif
Anna Bridge 160:5571c4ff569f 102
Anna Bridge 160:5571c4ff569f 103 #elif defined ( __TASKING__ )
Anna Bridge 160:5571c4ff569f 104 #if defined __FPU_VFP__
Anna Bridge 160:5571c4ff569f 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 106 #endif
Anna Bridge 160:5571c4ff569f 107
Anna Bridge 160:5571c4ff569f 108 #elif defined ( __CSMC__ )
Anna Bridge 160:5571c4ff569f 109 #if ( __CSMC__ & 0x400U)
Anna Bridge 160:5571c4ff569f 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 160:5571c4ff569f 111 #endif
Anna Bridge 160:5571c4ff569f 112
Anna Bridge 160:5571c4ff569f 113 #endif
Anna Bridge 160:5571c4ff569f 114
Anna Bridge 160:5571c4ff569f 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge 160:5571c4ff569f 116
Anna Bridge 160:5571c4ff569f 117
Anna Bridge 160:5571c4ff569f 118 #ifdef __cplusplus
Anna Bridge 160:5571c4ff569f 119 }
Anna Bridge 160:5571c4ff569f 120 #endif
Anna Bridge 160:5571c4ff569f 121
Anna Bridge 160:5571c4ff569f 122 #endif /* __CORE_CM23_H_GENERIC */
Anna Bridge 160:5571c4ff569f 123
Anna Bridge 160:5571c4ff569f 124 #ifndef __CMSIS_GENERIC
Anna Bridge 160:5571c4ff569f 125
Anna Bridge 160:5571c4ff569f 126 #ifndef __CORE_CM23_H_DEPENDANT
Anna Bridge 160:5571c4ff569f 127 #define __CORE_CM23_H_DEPENDANT
Anna Bridge 160:5571c4ff569f 128
Anna Bridge 160:5571c4ff569f 129 #ifdef __cplusplus
Anna Bridge 160:5571c4ff569f 130 extern "C" {
Anna Bridge 160:5571c4ff569f 131 #endif
Anna Bridge 160:5571c4ff569f 132
Anna Bridge 160:5571c4ff569f 133 /* check device defines and use defaults */
Anna Bridge 160:5571c4ff569f 134 #if defined __CHECK_DEVICE_DEFINES
Anna Bridge 160:5571c4ff569f 135 #ifndef __CM23_REV
Anna Bridge 160:5571c4ff569f 136 #define __CM23_REV 0x0000U
Anna Bridge 160:5571c4ff569f 137 #warning "__CM23_REV not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 138 #endif
Anna Bridge 160:5571c4ff569f 139
Anna Bridge 160:5571c4ff569f 140 #ifndef __FPU_PRESENT
Anna Bridge 160:5571c4ff569f 141 #define __FPU_PRESENT 0U
Anna Bridge 160:5571c4ff569f 142 #warning "__FPU_PRESENT not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 143 #endif
Anna Bridge 160:5571c4ff569f 144
Anna Bridge 160:5571c4ff569f 145 #ifndef __MPU_PRESENT
Anna Bridge 160:5571c4ff569f 146 #define __MPU_PRESENT 0U
Anna Bridge 160:5571c4ff569f 147 #warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 148 #endif
Anna Bridge 160:5571c4ff569f 149
Anna Bridge 160:5571c4ff569f 150 #ifndef __SAUREGION_PRESENT
Anna Bridge 160:5571c4ff569f 151 #define __SAUREGION_PRESENT 0U
Anna Bridge 160:5571c4ff569f 152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 153 #endif
Anna Bridge 160:5571c4ff569f 154
Anna Bridge 160:5571c4ff569f 155 #ifndef __VTOR_PRESENT
Anna Bridge 160:5571c4ff569f 156 #define __VTOR_PRESENT 0U
Anna Bridge 160:5571c4ff569f 157 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 158 #endif
Anna Bridge 160:5571c4ff569f 159
Anna Bridge 160:5571c4ff569f 160 #ifndef __NVIC_PRIO_BITS
Anna Bridge 160:5571c4ff569f 161 #define __NVIC_PRIO_BITS 2U
Anna Bridge 160:5571c4ff569f 162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 163 #endif
Anna Bridge 160:5571c4ff569f 164
Anna Bridge 160:5571c4ff569f 165 #ifndef __Vendor_SysTickConfig
Anna Bridge 160:5571c4ff569f 166 #define __Vendor_SysTickConfig 0U
Anna Bridge 160:5571c4ff569f 167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 168 #endif
Anna Bridge 160:5571c4ff569f 169
Anna Bridge 160:5571c4ff569f 170 #ifndef __ETM_PRESENT
Anna Bridge 160:5571c4ff569f 171 #define __ETM_PRESENT 0U
Anna Bridge 160:5571c4ff569f 172 #warning "__ETM_PRESENT not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 173 #endif
Anna Bridge 160:5571c4ff569f 174
Anna Bridge 160:5571c4ff569f 175 #ifndef __MTB_PRESENT
Anna Bridge 160:5571c4ff569f 176 #define __MTB_PRESENT 0U
Anna Bridge 160:5571c4ff569f 177 #warning "__MTB_PRESENT not defined in device header file; using default!"
Anna Bridge 160:5571c4ff569f 178 #endif
Anna Bridge 160:5571c4ff569f 179
Anna Bridge 160:5571c4ff569f 180 #endif
Anna Bridge 160:5571c4ff569f 181
Anna Bridge 160:5571c4ff569f 182 /* IO definitions (access restrictions to peripheral registers) */
Anna Bridge 160:5571c4ff569f 183 /**
Anna Bridge 160:5571c4ff569f 184 \defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge 160:5571c4ff569f 185
Anna Bridge 160:5571c4ff569f 186 <strong>IO Type Qualifiers</strong> are used
Anna Bridge 160:5571c4ff569f 187 \li to specify the access to peripheral variables.
Anna Bridge 160:5571c4ff569f 188 \li for automatic generation of peripheral register debug information.
Anna Bridge 160:5571c4ff569f 189 */
Anna Bridge 160:5571c4ff569f 190 #ifdef __cplusplus
Anna Bridge 160:5571c4ff569f 191 #define __I volatile /*!< Defines 'read only' permissions */
Anna Bridge 160:5571c4ff569f 192 #else
Anna Bridge 160:5571c4ff569f 193 #define __I volatile const /*!< Defines 'read only' permissions */
Anna Bridge 160:5571c4ff569f 194 #endif
Anna Bridge 160:5571c4ff569f 195 #define __O volatile /*!< Defines 'write only' permissions */
Anna Bridge 160:5571c4ff569f 196 #define __IO volatile /*!< Defines 'read / write' permissions */
Anna Bridge 160:5571c4ff569f 197
Anna Bridge 160:5571c4ff569f 198 /* following defines should be used for structure members */
Anna Bridge 160:5571c4ff569f 199 #define __IM volatile const /*! Defines 'read only' structure member permissions */
Anna Bridge 160:5571c4ff569f 200 #define __OM volatile /*! Defines 'write only' structure member permissions */
Anna Bridge 160:5571c4ff569f 201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
Anna Bridge 160:5571c4ff569f 202
Anna Bridge 160:5571c4ff569f 203 /*@} end of group Cortex_M23 */
Anna Bridge 160:5571c4ff569f 204
Anna Bridge 160:5571c4ff569f 205
Anna Bridge 160:5571c4ff569f 206
Anna Bridge 160:5571c4ff569f 207 /*******************************************************************************
Anna Bridge 160:5571c4ff569f 208 * Register Abstraction
Anna Bridge 160:5571c4ff569f 209 Core Register contain:
Anna Bridge 160:5571c4ff569f 210 - Core Register
Anna Bridge 160:5571c4ff569f 211 - Core NVIC Register
Anna Bridge 160:5571c4ff569f 212 - Core SCB Register
Anna Bridge 160:5571c4ff569f 213 - Core SysTick Register
Anna Bridge 160:5571c4ff569f 214 - Core Debug Register
Anna Bridge 160:5571c4ff569f 215 - Core MPU Register
Anna Bridge 160:5571c4ff569f 216 - Core SAU Register
Anna Bridge 160:5571c4ff569f 217 ******************************************************************************/
Anna Bridge 160:5571c4ff569f 218 /**
Anna Bridge 160:5571c4ff569f 219 \defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge 160:5571c4ff569f 220 \brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge 160:5571c4ff569f 221 */
Anna Bridge 160:5571c4ff569f 222
Anna Bridge 160:5571c4ff569f 223 /**
Anna Bridge 160:5571c4ff569f 224 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 225 \defgroup CMSIS_CORE Status and Control Registers
Anna Bridge 160:5571c4ff569f 226 \brief Core Register type definitions.
Anna Bridge 160:5571c4ff569f 227 @{
Anna Bridge 160:5571c4ff569f 228 */
Anna Bridge 160:5571c4ff569f 229
Anna Bridge 160:5571c4ff569f 230 /**
Anna Bridge 160:5571c4ff569f 231 \brief Union type to access the Application Program Status Register (APSR).
Anna Bridge 160:5571c4ff569f 232 */
Anna Bridge 160:5571c4ff569f 233 typedef union
Anna Bridge 160:5571c4ff569f 234 {
Anna Bridge 160:5571c4ff569f 235 struct
Anna Bridge 160:5571c4ff569f 236 {
Anna Bridge 160:5571c4ff569f 237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Anna Bridge 160:5571c4ff569f 238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 160:5571c4ff569f 239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 160:5571c4ff569f 240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 160:5571c4ff569f 241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 160:5571c4ff569f 242 } b; /*!< Structure used for bit access */
Anna Bridge 160:5571c4ff569f 243 uint32_t w; /*!< Type used for word access */
Anna Bridge 160:5571c4ff569f 244 } APSR_Type;
Anna Bridge 160:5571c4ff569f 245
Anna Bridge 160:5571c4ff569f 246 /* APSR Register Definitions */
Anna Bridge 160:5571c4ff569f 247 #define APSR_N_Pos 31U /*!< APSR: N Position */
Anna Bridge 160:5571c4ff569f 248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Anna Bridge 160:5571c4ff569f 249
Anna Bridge 160:5571c4ff569f 250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Anna Bridge 160:5571c4ff569f 251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Anna Bridge 160:5571c4ff569f 252
Anna Bridge 160:5571c4ff569f 253 #define APSR_C_Pos 29U /*!< APSR: C Position */
Anna Bridge 160:5571c4ff569f 254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Anna Bridge 160:5571c4ff569f 255
Anna Bridge 160:5571c4ff569f 256 #define APSR_V_Pos 28U /*!< APSR: V Position */
Anna Bridge 160:5571c4ff569f 257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Anna Bridge 160:5571c4ff569f 258
Anna Bridge 160:5571c4ff569f 259
Anna Bridge 160:5571c4ff569f 260 /**
Anna Bridge 160:5571c4ff569f 261 \brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge 160:5571c4ff569f 262 */
Anna Bridge 160:5571c4ff569f 263 typedef union
Anna Bridge 160:5571c4ff569f 264 {
Anna Bridge 160:5571c4ff569f 265 struct
Anna Bridge 160:5571c4ff569f 266 {
Anna Bridge 160:5571c4ff569f 267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 160:5571c4ff569f 268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Anna Bridge 160:5571c4ff569f 269 } b; /*!< Structure used for bit access */
Anna Bridge 160:5571c4ff569f 270 uint32_t w; /*!< Type used for word access */
Anna Bridge 160:5571c4ff569f 271 } IPSR_Type;
Anna Bridge 160:5571c4ff569f 272
Anna Bridge 160:5571c4ff569f 273 /* IPSR Register Definitions */
Anna Bridge 160:5571c4ff569f 274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Anna Bridge 160:5571c4ff569f 275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Anna Bridge 160:5571c4ff569f 276
Anna Bridge 160:5571c4ff569f 277
Anna Bridge 160:5571c4ff569f 278 /**
Anna Bridge 160:5571c4ff569f 279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge 160:5571c4ff569f 280 */
Anna Bridge 160:5571c4ff569f 281 typedef union
Anna Bridge 160:5571c4ff569f 282 {
Anna Bridge 160:5571c4ff569f 283 struct
Anna Bridge 160:5571c4ff569f 284 {
Anna Bridge 160:5571c4ff569f 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 160:5571c4ff569f 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Anna Bridge 160:5571c4ff569f 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Anna Bridge 160:5571c4ff569f 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Anna Bridge 160:5571c4ff569f 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 160:5571c4ff569f 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 160:5571c4ff569f 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 160:5571c4ff569f 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 160:5571c4ff569f 293 } b; /*!< Structure used for bit access */
Anna Bridge 160:5571c4ff569f 294 uint32_t w; /*!< Type used for word access */
Anna Bridge 160:5571c4ff569f 295 } xPSR_Type;
Anna Bridge 160:5571c4ff569f 296
Anna Bridge 160:5571c4ff569f 297 /* xPSR Register Definitions */
Anna Bridge 160:5571c4ff569f 298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Anna Bridge 160:5571c4ff569f 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Anna Bridge 160:5571c4ff569f 300
Anna Bridge 160:5571c4ff569f 301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Anna Bridge 160:5571c4ff569f 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Anna Bridge 160:5571c4ff569f 303
Anna Bridge 160:5571c4ff569f 304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Anna Bridge 160:5571c4ff569f 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Anna Bridge 160:5571c4ff569f 306
Anna Bridge 160:5571c4ff569f 307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Anna Bridge 160:5571c4ff569f 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Anna Bridge 160:5571c4ff569f 309
Anna Bridge 160:5571c4ff569f 310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Anna Bridge 160:5571c4ff569f 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Anna Bridge 160:5571c4ff569f 312
Anna Bridge 160:5571c4ff569f 313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Anna Bridge 160:5571c4ff569f 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Anna Bridge 160:5571c4ff569f 315
Anna Bridge 160:5571c4ff569f 316
Anna Bridge 160:5571c4ff569f 317 /**
Anna Bridge 160:5571c4ff569f 318 \brief Union type to access the Control Registers (CONTROL).
Anna Bridge 160:5571c4ff569f 319 */
Anna Bridge 160:5571c4ff569f 320 typedef union
Anna Bridge 160:5571c4ff569f 321 {
Anna Bridge 160:5571c4ff569f 322 struct
Anna Bridge 160:5571c4ff569f 323 {
Anna Bridge 160:5571c4ff569f 324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Anna Bridge 160:5571c4ff569f 325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
Anna Bridge 160:5571c4ff569f 326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Anna Bridge 160:5571c4ff569f 327 } b; /*!< Structure used for bit access */
Anna Bridge 160:5571c4ff569f 328 uint32_t w; /*!< Type used for word access */
Anna Bridge 160:5571c4ff569f 329 } CONTROL_Type;
Anna Bridge 160:5571c4ff569f 330
Anna Bridge 160:5571c4ff569f 331 /* CONTROL Register Definitions */
Anna Bridge 160:5571c4ff569f 332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Anna Bridge 160:5571c4ff569f 333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Anna Bridge 160:5571c4ff569f 334
Anna Bridge 160:5571c4ff569f 335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
Anna Bridge 160:5571c4ff569f 336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Anna Bridge 160:5571c4ff569f 337
Anna Bridge 160:5571c4ff569f 338 /*@} end of group CMSIS_CORE */
Anna Bridge 160:5571c4ff569f 339
Anna Bridge 160:5571c4ff569f 340
Anna Bridge 160:5571c4ff569f 341 /**
Anna Bridge 160:5571c4ff569f 342 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge 160:5571c4ff569f 344 \brief Type definitions for the NVIC Registers
Anna Bridge 160:5571c4ff569f 345 @{
Anna Bridge 160:5571c4ff569f 346 */
Anna Bridge 160:5571c4ff569f 347
Anna Bridge 160:5571c4ff569f 348 /**
Anna Bridge 160:5571c4ff569f 349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge 160:5571c4ff569f 350 */
Anna Bridge 160:5571c4ff569f 351 typedef struct
Anna Bridge 160:5571c4ff569f 352 {
Anna Bridge 160:5571c4ff569f 353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Anna Bridge 160:5571c4ff569f 354 uint32_t RESERVED0[16U];
Anna Bridge 160:5571c4ff569f 355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Anna Bridge 160:5571c4ff569f 356 uint32_t RSERVED1[16U];
Anna Bridge 160:5571c4ff569f 357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Anna Bridge 160:5571c4ff569f 358 uint32_t RESERVED2[16U];
Anna Bridge 160:5571c4ff569f 359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Anna Bridge 160:5571c4ff569f 360 uint32_t RESERVED3[16U];
Anna Bridge 160:5571c4ff569f 361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Anna Bridge 160:5571c4ff569f 362 uint32_t RESERVED4[16U];
Anna Bridge 160:5571c4ff569f 363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
Anna Bridge 160:5571c4ff569f 364 uint32_t RESERVED5[16U];
Anna Bridge 160:5571c4ff569f 365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Anna Bridge 160:5571c4ff569f 366 } NVIC_Type;
Anna Bridge 160:5571c4ff569f 367
Anna Bridge 160:5571c4ff569f 368 /*@} end of group CMSIS_NVIC */
Anna Bridge 160:5571c4ff569f 369
Anna Bridge 160:5571c4ff569f 370
Anna Bridge 160:5571c4ff569f 371 /**
Anna Bridge 160:5571c4ff569f 372 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 373 \defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge 160:5571c4ff569f 374 \brief Type definitions for the System Control Block Registers
Anna Bridge 160:5571c4ff569f 375 @{
Anna Bridge 160:5571c4ff569f 376 */
Anna Bridge 160:5571c4ff569f 377
Anna Bridge 160:5571c4ff569f 378 /**
Anna Bridge 160:5571c4ff569f 379 \brief Structure type to access the System Control Block (SCB).
Anna Bridge 160:5571c4ff569f 380 */
Anna Bridge 160:5571c4ff569f 381 typedef struct
Anna Bridge 160:5571c4ff569f 382 {
Anna Bridge 160:5571c4ff569f 383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Anna Bridge 160:5571c4ff569f 384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Anna Bridge 160:5571c4ff569f 385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Anna Bridge 160:5571c4ff569f 387 #else
Anna Bridge 160:5571c4ff569f 388 uint32_t RESERVED0;
Anna Bridge 160:5571c4ff569f 389 #endif
Anna Bridge 160:5571c4ff569f 390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Anna Bridge 160:5571c4ff569f 391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Anna Bridge 160:5571c4ff569f 392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Anna Bridge 160:5571c4ff569f 393 uint32_t RESERVED1;
Anna Bridge 160:5571c4ff569f 394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Anna Bridge 160:5571c4ff569f 395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Anna Bridge 160:5571c4ff569f 396 } SCB_Type;
Anna Bridge 160:5571c4ff569f 397
Anna Bridge 160:5571c4ff569f 398 /* SCB CPUID Register Definitions */
Anna Bridge 160:5571c4ff569f 399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
Anna Bridge 160:5571c4ff569f 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Anna Bridge 160:5571c4ff569f 401
Anna Bridge 160:5571c4ff569f 402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
Anna Bridge 160:5571c4ff569f 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Anna Bridge 160:5571c4ff569f 404
Anna Bridge 160:5571c4ff569f 405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
Anna Bridge 160:5571c4ff569f 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Anna Bridge 160:5571c4ff569f 407
Anna Bridge 160:5571c4ff569f 408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
Anna Bridge 160:5571c4ff569f 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Anna Bridge 160:5571c4ff569f 410
Anna Bridge 160:5571c4ff569f 411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Anna Bridge 160:5571c4ff569f 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Anna Bridge 160:5571c4ff569f 413
Anna Bridge 160:5571c4ff569f 414 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 160:5571c4ff569f 415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
Anna Bridge 160:5571c4ff569f 416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
Anna Bridge 160:5571c4ff569f 417
Anna Bridge 160:5571c4ff569f 418 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
Anna Bridge 160:5571c4ff569f 419 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
Anna Bridge 160:5571c4ff569f 420
Anna Bridge 160:5571c4ff569f 421 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
Anna Bridge 160:5571c4ff569f 422 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Anna Bridge 160:5571c4ff569f 423
Anna Bridge 160:5571c4ff569f 424 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
Anna Bridge 160:5571c4ff569f 425 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Anna Bridge 160:5571c4ff569f 426
Anna Bridge 160:5571c4ff569f 427 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
Anna Bridge 160:5571c4ff569f 428 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Anna Bridge 160:5571c4ff569f 429
Anna Bridge 160:5571c4ff569f 430 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
Anna Bridge 160:5571c4ff569f 431 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Anna Bridge 160:5571c4ff569f 432
Anna Bridge 160:5571c4ff569f 433 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
Anna Bridge 160:5571c4ff569f 434 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
Anna Bridge 160:5571c4ff569f 435
Anna Bridge 160:5571c4ff569f 436 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
Anna Bridge 160:5571c4ff569f 437 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Anna Bridge 160:5571c4ff569f 438
Anna Bridge 160:5571c4ff569f 439 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
Anna Bridge 160:5571c4ff569f 440 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Anna Bridge 160:5571c4ff569f 441
Anna Bridge 160:5571c4ff569f 442 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
Anna Bridge 160:5571c4ff569f 443 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Anna Bridge 160:5571c4ff569f 444
Anna Bridge 160:5571c4ff569f 445 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
Anna Bridge 160:5571c4ff569f 446 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Anna Bridge 160:5571c4ff569f 447
Anna Bridge 160:5571c4ff569f 448 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Anna Bridge 160:5571c4ff569f 449 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Anna Bridge 160:5571c4ff569f 450
Anna Bridge 160:5571c4ff569f 451 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 452 /* SCB Vector Table Offset Register Definitions */
Anna Bridge 160:5571c4ff569f 453 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
Anna Bridge 160:5571c4ff569f 454 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Anna Bridge 160:5571c4ff569f 455 #endif
Anna Bridge 160:5571c4ff569f 456
Anna Bridge 160:5571c4ff569f 457 /* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge 160:5571c4ff569f 458 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
Anna Bridge 160:5571c4ff569f 459 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Anna Bridge 160:5571c4ff569f 460
Anna Bridge 160:5571c4ff569f 461 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
Anna Bridge 160:5571c4ff569f 462 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Anna Bridge 160:5571c4ff569f 463
Anna Bridge 160:5571c4ff569f 464 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
Anna Bridge 160:5571c4ff569f 465 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Anna Bridge 160:5571c4ff569f 466
Anna Bridge 160:5571c4ff569f 467 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
Anna Bridge 160:5571c4ff569f 468 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
Anna Bridge 160:5571c4ff569f 469
Anna Bridge 160:5571c4ff569f 470 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
Anna Bridge 160:5571c4ff569f 471 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
Anna Bridge 160:5571c4ff569f 472
Anna Bridge 160:5571c4ff569f 473 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
Anna Bridge 160:5571c4ff569f 474 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
Anna Bridge 160:5571c4ff569f 475
Anna Bridge 160:5571c4ff569f 476 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
Anna Bridge 160:5571c4ff569f 477 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Anna Bridge 160:5571c4ff569f 478
Anna Bridge 160:5571c4ff569f 479 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
Anna Bridge 160:5571c4ff569f 480 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Anna Bridge 160:5571c4ff569f 481
Anna Bridge 160:5571c4ff569f 482 /* SCB System Control Register Definitions */
Anna Bridge 160:5571c4ff569f 483 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
Anna Bridge 160:5571c4ff569f 484 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Anna Bridge 160:5571c4ff569f 485
Anna Bridge 160:5571c4ff569f 486 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
Anna Bridge 160:5571c4ff569f 487 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
Anna Bridge 160:5571c4ff569f 488
Anna Bridge 160:5571c4ff569f 489 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
Anna Bridge 160:5571c4ff569f 490 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Anna Bridge 160:5571c4ff569f 491
Anna Bridge 160:5571c4ff569f 492 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
Anna Bridge 160:5571c4ff569f 493 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Anna Bridge 160:5571c4ff569f 494
Anna Bridge 160:5571c4ff569f 495 /* SCB Configuration Control Register Definitions */
Anna Bridge 160:5571c4ff569f 496 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
Anna Bridge 160:5571c4ff569f 497 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
Anna Bridge 160:5571c4ff569f 498
Anna Bridge 160:5571c4ff569f 499 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
Anna Bridge 160:5571c4ff569f 500 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
Anna Bridge 160:5571c4ff569f 501
Anna Bridge 160:5571c4ff569f 502 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
Anna Bridge 160:5571c4ff569f 503 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
Anna Bridge 160:5571c4ff569f 504
Anna Bridge 160:5571c4ff569f 505 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
Anna Bridge 160:5571c4ff569f 506 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
Anna Bridge 160:5571c4ff569f 507
Anna Bridge 160:5571c4ff569f 508 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
Anna Bridge 160:5571c4ff569f 509 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Anna Bridge 160:5571c4ff569f 510
Anna Bridge 160:5571c4ff569f 511 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
Anna Bridge 160:5571c4ff569f 512 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Anna Bridge 160:5571c4ff569f 513
Anna Bridge 160:5571c4ff569f 514 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
Anna Bridge 160:5571c4ff569f 515 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Anna Bridge 160:5571c4ff569f 516
Anna Bridge 160:5571c4ff569f 517 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
Anna Bridge 160:5571c4ff569f 518 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Anna Bridge 160:5571c4ff569f 519
Anna Bridge 160:5571c4ff569f 520 /* SCB System Handler Control and State Register Definitions */
Anna Bridge 160:5571c4ff569f 521 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
Anna Bridge 160:5571c4ff569f 522 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
Anna Bridge 160:5571c4ff569f 523
Anna Bridge 160:5571c4ff569f 524 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
Anna Bridge 160:5571c4ff569f 525 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Anna Bridge 160:5571c4ff569f 526
Anna Bridge 160:5571c4ff569f 527 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
Anna Bridge 160:5571c4ff569f 528 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Anna Bridge 160:5571c4ff569f 529
Anna Bridge 160:5571c4ff569f 530 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
Anna Bridge 160:5571c4ff569f 531 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Anna Bridge 160:5571c4ff569f 532
Anna Bridge 160:5571c4ff569f 533 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
Anna Bridge 160:5571c4ff569f 534 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Anna Bridge 160:5571c4ff569f 535
Anna Bridge 160:5571c4ff569f 536 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
Anna Bridge 160:5571c4ff569f 537 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
Anna Bridge 160:5571c4ff569f 538
Anna Bridge 160:5571c4ff569f 539 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
Anna Bridge 160:5571c4ff569f 540 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
Anna Bridge 160:5571c4ff569f 541
Anna Bridge 160:5571c4ff569f 542 /*@} end of group CMSIS_SCB */
Anna Bridge 160:5571c4ff569f 543
Anna Bridge 160:5571c4ff569f 544
Anna Bridge 160:5571c4ff569f 545 /**
Anna Bridge 160:5571c4ff569f 546 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 547 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge 160:5571c4ff569f 548 \brief Type definitions for the System Timer Registers.
Anna Bridge 160:5571c4ff569f 549 @{
Anna Bridge 160:5571c4ff569f 550 */
Anna Bridge 160:5571c4ff569f 551
Anna Bridge 160:5571c4ff569f 552 /**
Anna Bridge 160:5571c4ff569f 553 \brief Structure type to access the System Timer (SysTick).
Anna Bridge 160:5571c4ff569f 554 */
Anna Bridge 160:5571c4ff569f 555 typedef struct
Anna Bridge 160:5571c4ff569f 556 {
Anna Bridge 160:5571c4ff569f 557 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Anna Bridge 160:5571c4ff569f 558 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Anna Bridge 160:5571c4ff569f 559 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Anna Bridge 160:5571c4ff569f 560 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Anna Bridge 160:5571c4ff569f 561 } SysTick_Type;
Anna Bridge 160:5571c4ff569f 562
Anna Bridge 160:5571c4ff569f 563 /* SysTick Control / Status Register Definitions */
Anna Bridge 160:5571c4ff569f 564 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
Anna Bridge 160:5571c4ff569f 565 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Anna Bridge 160:5571c4ff569f 566
Anna Bridge 160:5571c4ff569f 567 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
Anna Bridge 160:5571c4ff569f 568 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Anna Bridge 160:5571c4ff569f 569
Anna Bridge 160:5571c4ff569f 570 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
Anna Bridge 160:5571c4ff569f 571 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Anna Bridge 160:5571c4ff569f 572
Anna Bridge 160:5571c4ff569f 573 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Anna Bridge 160:5571c4ff569f 574 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Anna Bridge 160:5571c4ff569f 575
Anna Bridge 160:5571c4ff569f 576 /* SysTick Reload Register Definitions */
Anna Bridge 160:5571c4ff569f 577 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Anna Bridge 160:5571c4ff569f 578 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Anna Bridge 160:5571c4ff569f 579
Anna Bridge 160:5571c4ff569f 580 /* SysTick Current Register Definitions */
Anna Bridge 160:5571c4ff569f 581 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Anna Bridge 160:5571c4ff569f 582 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Anna Bridge 160:5571c4ff569f 583
Anna Bridge 160:5571c4ff569f 584 /* SysTick Calibration Register Definitions */
Anna Bridge 160:5571c4ff569f 585 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
Anna Bridge 160:5571c4ff569f 586 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Anna Bridge 160:5571c4ff569f 587
Anna Bridge 160:5571c4ff569f 588 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
Anna Bridge 160:5571c4ff569f 589 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Anna Bridge 160:5571c4ff569f 590
Anna Bridge 160:5571c4ff569f 591 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Anna Bridge 160:5571c4ff569f 592 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Anna Bridge 160:5571c4ff569f 593
Anna Bridge 160:5571c4ff569f 594 /*@} end of group CMSIS_SysTick */
Anna Bridge 160:5571c4ff569f 595
Anna Bridge 160:5571c4ff569f 596
Anna Bridge 160:5571c4ff569f 597 /**
Anna Bridge 160:5571c4ff569f 598 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 599 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Anna Bridge 160:5571c4ff569f 600 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Anna Bridge 160:5571c4ff569f 601 @{
Anna Bridge 160:5571c4ff569f 602 */
Anna Bridge 160:5571c4ff569f 603
Anna Bridge 160:5571c4ff569f 604 /**
Anna Bridge 160:5571c4ff569f 605 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Anna Bridge 160:5571c4ff569f 606 */
Anna Bridge 160:5571c4ff569f 607 typedef struct
Anna Bridge 160:5571c4ff569f 608 {
Anna Bridge 160:5571c4ff569f 609 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Anna Bridge 160:5571c4ff569f 610 uint32_t RESERVED0[6U];
Anna Bridge 160:5571c4ff569f 611 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Anna Bridge 160:5571c4ff569f 612 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Anna Bridge 160:5571c4ff569f 613 uint32_t RESERVED1[1U];
Anna Bridge 160:5571c4ff569f 614 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Anna Bridge 160:5571c4ff569f 615 uint32_t RESERVED2[1U];
Anna Bridge 160:5571c4ff569f 616 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Anna Bridge 160:5571c4ff569f 617 uint32_t RESERVED3[1U];
Anna Bridge 160:5571c4ff569f 618 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Anna Bridge 160:5571c4ff569f 619 uint32_t RESERVED4[1U];
Anna Bridge 160:5571c4ff569f 620 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Anna Bridge 160:5571c4ff569f 621 uint32_t RESERVED5[1U];
Anna Bridge 160:5571c4ff569f 622 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Anna Bridge 160:5571c4ff569f 623 uint32_t RESERVED6[1U];
Anna Bridge 160:5571c4ff569f 624 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Anna Bridge 160:5571c4ff569f 625 uint32_t RESERVED7[1U];
Anna Bridge 160:5571c4ff569f 626 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Anna Bridge 160:5571c4ff569f 627 uint32_t RESERVED8[1U];
Anna Bridge 160:5571c4ff569f 628 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
Anna Bridge 160:5571c4ff569f 629 uint32_t RESERVED9[1U];
Anna Bridge 160:5571c4ff569f 630 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
Anna Bridge 160:5571c4ff569f 631 uint32_t RESERVED10[1U];
Anna Bridge 160:5571c4ff569f 632 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
Anna Bridge 160:5571c4ff569f 633 uint32_t RESERVED11[1U];
Anna Bridge 160:5571c4ff569f 634 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
Anna Bridge 160:5571c4ff569f 635 uint32_t RESERVED12[1U];
Anna Bridge 160:5571c4ff569f 636 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
Anna Bridge 160:5571c4ff569f 637 uint32_t RESERVED13[1U];
Anna Bridge 160:5571c4ff569f 638 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
Anna Bridge 160:5571c4ff569f 639 uint32_t RESERVED14[1U];
Anna Bridge 160:5571c4ff569f 640 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
Anna Bridge 160:5571c4ff569f 641 uint32_t RESERVED15[1U];
Anna Bridge 160:5571c4ff569f 642 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
Anna Bridge 160:5571c4ff569f 643 uint32_t RESERVED16[1U];
Anna Bridge 160:5571c4ff569f 644 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
Anna Bridge 160:5571c4ff569f 645 uint32_t RESERVED17[1U];
Anna Bridge 160:5571c4ff569f 646 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
Anna Bridge 160:5571c4ff569f 647 uint32_t RESERVED18[1U];
Anna Bridge 160:5571c4ff569f 648 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
Anna Bridge 160:5571c4ff569f 649 uint32_t RESERVED19[1U];
Anna Bridge 160:5571c4ff569f 650 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
Anna Bridge 160:5571c4ff569f 651 uint32_t RESERVED20[1U];
Anna Bridge 160:5571c4ff569f 652 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
Anna Bridge 160:5571c4ff569f 653 uint32_t RESERVED21[1U];
Anna Bridge 160:5571c4ff569f 654 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
Anna Bridge 160:5571c4ff569f 655 uint32_t RESERVED22[1U];
Anna Bridge 160:5571c4ff569f 656 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
Anna Bridge 160:5571c4ff569f 657 uint32_t RESERVED23[1U];
Anna Bridge 160:5571c4ff569f 658 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
Anna Bridge 160:5571c4ff569f 659 uint32_t RESERVED24[1U];
Anna Bridge 160:5571c4ff569f 660 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
Anna Bridge 160:5571c4ff569f 661 uint32_t RESERVED25[1U];
Anna Bridge 160:5571c4ff569f 662 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
Anna Bridge 160:5571c4ff569f 663 uint32_t RESERVED26[1U];
Anna Bridge 160:5571c4ff569f 664 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
Anna Bridge 160:5571c4ff569f 665 uint32_t RESERVED27[1U];
Anna Bridge 160:5571c4ff569f 666 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
Anna Bridge 160:5571c4ff569f 667 uint32_t RESERVED28[1U];
Anna Bridge 160:5571c4ff569f 668 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
Anna Bridge 160:5571c4ff569f 669 uint32_t RESERVED29[1U];
Anna Bridge 160:5571c4ff569f 670 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
Anna Bridge 160:5571c4ff569f 671 uint32_t RESERVED30[1U];
Anna Bridge 160:5571c4ff569f 672 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
Anna Bridge 160:5571c4ff569f 673 uint32_t RESERVED31[1U];
Anna Bridge 160:5571c4ff569f 674 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
Anna Bridge 160:5571c4ff569f 675 } DWT_Type;
Anna Bridge 160:5571c4ff569f 676
Anna Bridge 160:5571c4ff569f 677 /* DWT Control Register Definitions */
Anna Bridge 160:5571c4ff569f 678 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
Anna Bridge 160:5571c4ff569f 679 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Anna Bridge 160:5571c4ff569f 680
Anna Bridge 160:5571c4ff569f 681 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
Anna Bridge 160:5571c4ff569f 682 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Anna Bridge 160:5571c4ff569f 683
Anna Bridge 160:5571c4ff569f 684 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
Anna Bridge 160:5571c4ff569f 685 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Anna Bridge 160:5571c4ff569f 686
Anna Bridge 160:5571c4ff569f 687 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
Anna Bridge 160:5571c4ff569f 688 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Anna Bridge 160:5571c4ff569f 689
Anna Bridge 160:5571c4ff569f 690 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
Anna Bridge 160:5571c4ff569f 691 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Anna Bridge 160:5571c4ff569f 692
Anna Bridge 160:5571c4ff569f 693 /* DWT Comparator Function Register Definitions */
Anna Bridge 160:5571c4ff569f 694 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
Anna Bridge 160:5571c4ff569f 695 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
Anna Bridge 160:5571c4ff569f 696
Anna Bridge 160:5571c4ff569f 697 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
Anna Bridge 160:5571c4ff569f 698 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Anna Bridge 160:5571c4ff569f 699
Anna Bridge 160:5571c4ff569f 700 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
Anna Bridge 160:5571c4ff569f 701 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Anna Bridge 160:5571c4ff569f 702
Anna Bridge 160:5571c4ff569f 703 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
Anna Bridge 160:5571c4ff569f 704 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
Anna Bridge 160:5571c4ff569f 705
Anna Bridge 160:5571c4ff569f 706 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
Anna Bridge 160:5571c4ff569f 707 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
Anna Bridge 160:5571c4ff569f 708
Anna Bridge 160:5571c4ff569f 709 /*@}*/ /* end of group CMSIS_DWT */
Anna Bridge 160:5571c4ff569f 710
Anna Bridge 160:5571c4ff569f 711
Anna Bridge 160:5571c4ff569f 712 /**
Anna Bridge 160:5571c4ff569f 713 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 714 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Anna Bridge 160:5571c4ff569f 715 \brief Type definitions for the Trace Port Interface (TPI)
Anna Bridge 160:5571c4ff569f 716 @{
Anna Bridge 160:5571c4ff569f 717 */
Anna Bridge 160:5571c4ff569f 718
Anna Bridge 160:5571c4ff569f 719 /**
Anna Bridge 160:5571c4ff569f 720 \brief Structure type to access the Trace Port Interface Register (TPI).
Anna Bridge 160:5571c4ff569f 721 */
Anna Bridge 160:5571c4ff569f 722 typedef struct
Anna Bridge 160:5571c4ff569f 723 {
Anna Bridge 160:5571c4ff569f 724 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Anna Bridge 160:5571c4ff569f 725 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Anna Bridge 160:5571c4ff569f 726 uint32_t RESERVED0[2U];
Anna Bridge 160:5571c4ff569f 727 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Anna Bridge 160:5571c4ff569f 728 uint32_t RESERVED1[55U];
Anna Bridge 160:5571c4ff569f 729 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Anna Bridge 160:5571c4ff569f 730 uint32_t RESERVED2[131U];
Anna Bridge 160:5571c4ff569f 731 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Anna Bridge 160:5571c4ff569f 732 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Anna Bridge 160:5571c4ff569f 733 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Anna Bridge 160:5571c4ff569f 734 uint32_t RESERVED3[759U];
Anna Bridge 160:5571c4ff569f 735 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Anna Bridge 160:5571c4ff569f 736 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Anna Bridge 160:5571c4ff569f 737 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Anna Bridge 160:5571c4ff569f 738 uint32_t RESERVED4[1U];
Anna Bridge 160:5571c4ff569f 739 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Anna Bridge 160:5571c4ff569f 740 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Anna Bridge 160:5571c4ff569f 741 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Anna Bridge 160:5571c4ff569f 742 uint32_t RESERVED5[39U];
Anna Bridge 160:5571c4ff569f 743 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Anna Bridge 160:5571c4ff569f 744 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Anna Bridge 160:5571c4ff569f 745 uint32_t RESERVED7[8U];
Anna Bridge 160:5571c4ff569f 746 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Anna Bridge 160:5571c4ff569f 747 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Anna Bridge 160:5571c4ff569f 748 } TPI_Type;
Anna Bridge 160:5571c4ff569f 749
Anna Bridge 160:5571c4ff569f 750 /* TPI Asynchronous Clock Prescaler Register Definitions */
Anna Bridge 169:a7c7b631e539 751 #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
Anna Bridge 169:a7c7b631e539 752 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
Anna Bridge 169:a7c7b631e539 753
Anna Bridge 169:a7c7b631e539 754 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
Anna Bridge 169:a7c7b631e539 755 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
Anna Bridge 160:5571c4ff569f 756
Anna Bridge 160:5571c4ff569f 757 /* TPI Selected Pin Protocol Register Definitions */
Anna Bridge 160:5571c4ff569f 758 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
Anna Bridge 160:5571c4ff569f 759 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Anna Bridge 160:5571c4ff569f 760
Anna Bridge 160:5571c4ff569f 761 /* TPI Formatter and Flush Status Register Definitions */
Anna Bridge 160:5571c4ff569f 762 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
Anna Bridge 160:5571c4ff569f 763 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Anna Bridge 160:5571c4ff569f 764
Anna Bridge 160:5571c4ff569f 765 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
Anna Bridge 160:5571c4ff569f 766 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Anna Bridge 160:5571c4ff569f 767
Anna Bridge 160:5571c4ff569f 768 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
Anna Bridge 160:5571c4ff569f 769 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Anna Bridge 160:5571c4ff569f 770
Anna Bridge 160:5571c4ff569f 771 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
Anna Bridge 160:5571c4ff569f 772 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Anna Bridge 160:5571c4ff569f 773
Anna Bridge 160:5571c4ff569f 774 /* TPI Formatter and Flush Control Register Definitions */
Anna Bridge 160:5571c4ff569f 775 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
Anna Bridge 160:5571c4ff569f 776 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Anna Bridge 160:5571c4ff569f 777
Anna Bridge 160:5571c4ff569f 778 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
Anna Bridge 160:5571c4ff569f 779 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Anna Bridge 160:5571c4ff569f 780
Anna Bridge 160:5571c4ff569f 781 /* TPI TRIGGER Register Definitions */
Anna Bridge 160:5571c4ff569f 782 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
Anna Bridge 160:5571c4ff569f 783 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Anna Bridge 160:5571c4ff569f 784
Anna Bridge 160:5571c4ff569f 785 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Anna Bridge 160:5571c4ff569f 786 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
Anna Bridge 160:5571c4ff569f 787 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Anna Bridge 160:5571c4ff569f 788
Anna Bridge 160:5571c4ff569f 789 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
Anna Bridge 160:5571c4ff569f 790 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Anna Bridge 160:5571c4ff569f 791
Anna Bridge 160:5571c4ff569f 792 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
Anna Bridge 160:5571c4ff569f 793 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Anna Bridge 160:5571c4ff569f 794
Anna Bridge 160:5571c4ff569f 795 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
Anna Bridge 160:5571c4ff569f 796 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Anna Bridge 160:5571c4ff569f 797
Anna Bridge 160:5571c4ff569f 798 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
Anna Bridge 160:5571c4ff569f 799 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Anna Bridge 160:5571c4ff569f 800
Anna Bridge 160:5571c4ff569f 801 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
Anna Bridge 160:5571c4ff569f 802 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Anna Bridge 160:5571c4ff569f 803
Anna Bridge 160:5571c4ff569f 804 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
Anna Bridge 160:5571c4ff569f 805 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Anna Bridge 160:5571c4ff569f 806
Anna Bridge 160:5571c4ff569f 807 /* TPI ITATBCTR2 Register Definitions */
Anna Bridge 160:5571c4ff569f 808 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
Anna Bridge 160:5571c4ff569f 809 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Anna Bridge 160:5571c4ff569f 810
Anna Bridge 160:5571c4ff569f 811 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Anna Bridge 160:5571c4ff569f 812 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
Anna Bridge 160:5571c4ff569f 813 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Anna Bridge 160:5571c4ff569f 814
Anna Bridge 160:5571c4ff569f 815 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
Anna Bridge 160:5571c4ff569f 816 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Anna Bridge 160:5571c4ff569f 817
Anna Bridge 160:5571c4ff569f 818 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
Anna Bridge 160:5571c4ff569f 819 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Anna Bridge 160:5571c4ff569f 820
Anna Bridge 160:5571c4ff569f 821 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
Anna Bridge 160:5571c4ff569f 822 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Anna Bridge 160:5571c4ff569f 823
Anna Bridge 160:5571c4ff569f 824 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
Anna Bridge 160:5571c4ff569f 825 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Anna Bridge 160:5571c4ff569f 826
Anna Bridge 160:5571c4ff569f 827 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
Anna Bridge 160:5571c4ff569f 828 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Anna Bridge 160:5571c4ff569f 829
Anna Bridge 160:5571c4ff569f 830 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
Anna Bridge 160:5571c4ff569f 831 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Anna Bridge 160:5571c4ff569f 832
Anna Bridge 160:5571c4ff569f 833 /* TPI ITATBCTR0 Register Definitions */
Anna Bridge 160:5571c4ff569f 834 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
Anna Bridge 160:5571c4ff569f 835 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Anna Bridge 160:5571c4ff569f 836
Anna Bridge 160:5571c4ff569f 837 /* TPI Integration Mode Control Register Definitions */
Anna Bridge 160:5571c4ff569f 838 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
Anna Bridge 160:5571c4ff569f 839 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Anna Bridge 160:5571c4ff569f 840
Anna Bridge 160:5571c4ff569f 841 /* TPI DEVID Register Definitions */
Anna Bridge 160:5571c4ff569f 842 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
Anna Bridge 160:5571c4ff569f 843 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Anna Bridge 160:5571c4ff569f 844
Anna Bridge 160:5571c4ff569f 845 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
Anna Bridge 160:5571c4ff569f 846 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Anna Bridge 160:5571c4ff569f 847
Anna Bridge 160:5571c4ff569f 848 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
Anna Bridge 160:5571c4ff569f 849 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Anna Bridge 160:5571c4ff569f 850
Anna Bridge 160:5571c4ff569f 851 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
Anna Bridge 160:5571c4ff569f 852 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Anna Bridge 160:5571c4ff569f 853
Anna Bridge 160:5571c4ff569f 854 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
Anna Bridge 160:5571c4ff569f 855 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Anna Bridge 160:5571c4ff569f 856
Anna Bridge 160:5571c4ff569f 857 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
Anna Bridge 160:5571c4ff569f 858 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Anna Bridge 160:5571c4ff569f 859
Anna Bridge 160:5571c4ff569f 860 /* TPI DEVTYPE Register Definitions */
Anna Bridge 160:5571c4ff569f 861 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
Anna Bridge 160:5571c4ff569f 862 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Anna Bridge 160:5571c4ff569f 863
Anna Bridge 160:5571c4ff569f 864 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
Anna Bridge 160:5571c4ff569f 865 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Anna Bridge 160:5571c4ff569f 866
Anna Bridge 160:5571c4ff569f 867 /*@}*/ /* end of group CMSIS_TPI */
Anna Bridge 160:5571c4ff569f 868
Anna Bridge 160:5571c4ff569f 869
Anna Bridge 160:5571c4ff569f 870 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 871 /**
Anna Bridge 160:5571c4ff569f 872 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 873 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge 160:5571c4ff569f 874 \brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge 160:5571c4ff569f 875 @{
Anna Bridge 160:5571c4ff569f 876 */
Anna Bridge 160:5571c4ff569f 877
Anna Bridge 160:5571c4ff569f 878 /**
Anna Bridge 160:5571c4ff569f 879 \brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge 160:5571c4ff569f 880 */
Anna Bridge 160:5571c4ff569f 881 typedef struct
Anna Bridge 160:5571c4ff569f 882 {
Anna Bridge 160:5571c4ff569f 883 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Anna Bridge 160:5571c4ff569f 884 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Anna Bridge 160:5571c4ff569f 885 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
Anna Bridge 160:5571c4ff569f 886 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Anna Bridge 160:5571c4ff569f 887 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
Anna Bridge 160:5571c4ff569f 888 uint32_t RESERVED0[7U];
Anna Bridge 160:5571c4ff569f 889 union {
Anna Bridge 160:5571c4ff569f 890 __IOM uint32_t MAIR[2];
Anna Bridge 160:5571c4ff569f 891 struct {
Anna Bridge 160:5571c4ff569f 892 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
Anna Bridge 160:5571c4ff569f 893 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
Anna Bridge 160:5571c4ff569f 894 };
Anna Bridge 160:5571c4ff569f 895 };
Anna Bridge 160:5571c4ff569f 896 } MPU_Type;
Anna Bridge 160:5571c4ff569f 897
Anna Bridge 160:5571c4ff569f 898 #define MPU_TYPE_RALIASES 1U
Anna Bridge 160:5571c4ff569f 899
Anna Bridge 160:5571c4ff569f 900 /* MPU Type Register Definitions */
Anna Bridge 160:5571c4ff569f 901 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
Anna Bridge 160:5571c4ff569f 902 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Anna Bridge 160:5571c4ff569f 903
Anna Bridge 160:5571c4ff569f 904 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
Anna Bridge 160:5571c4ff569f 905 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Anna Bridge 160:5571c4ff569f 906
Anna Bridge 160:5571c4ff569f 907 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Anna Bridge 160:5571c4ff569f 908 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Anna Bridge 160:5571c4ff569f 909
Anna Bridge 160:5571c4ff569f 910 /* MPU Control Register Definitions */
Anna Bridge 160:5571c4ff569f 911 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
Anna Bridge 160:5571c4ff569f 912 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Anna Bridge 160:5571c4ff569f 913
Anna Bridge 160:5571c4ff569f 914 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
Anna Bridge 160:5571c4ff569f 915 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Anna Bridge 160:5571c4ff569f 916
Anna Bridge 160:5571c4ff569f 917 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Anna Bridge 160:5571c4ff569f 918 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Anna Bridge 160:5571c4ff569f 919
Anna Bridge 160:5571c4ff569f 920 /* MPU Region Number Register Definitions */
Anna Bridge 160:5571c4ff569f 921 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Anna Bridge 160:5571c4ff569f 922 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Anna Bridge 160:5571c4ff569f 923
Anna Bridge 160:5571c4ff569f 924 /* MPU Region Base Address Register Definitions */
Anna Bridge 160:5571c4ff569f 925 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
Anna Bridge 160:5571c4ff569f 926 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
Anna Bridge 160:5571c4ff569f 927
Anna Bridge 160:5571c4ff569f 928 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
Anna Bridge 160:5571c4ff569f 929 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
Anna Bridge 160:5571c4ff569f 930
Anna Bridge 160:5571c4ff569f 931 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
Anna Bridge 160:5571c4ff569f 932 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
Anna Bridge 160:5571c4ff569f 933
Anna Bridge 160:5571c4ff569f 934 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
Anna Bridge 160:5571c4ff569f 935 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
Anna Bridge 160:5571c4ff569f 936
Anna Bridge 160:5571c4ff569f 937 /* MPU Region Limit Address Register Definitions */
Anna Bridge 160:5571c4ff569f 938 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
Anna Bridge 160:5571c4ff569f 939 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
Anna Bridge 160:5571c4ff569f 940
Anna Bridge 160:5571c4ff569f 941 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
Anna Bridge 160:5571c4ff569f 942 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
Anna Bridge 160:5571c4ff569f 943
Anna Bridge 160:5571c4ff569f 944 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
Anna Bridge 160:5571c4ff569f 945 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
Anna Bridge 160:5571c4ff569f 946
Anna Bridge 160:5571c4ff569f 947 /* MPU Memory Attribute Indirection Register 0 Definitions */
Anna Bridge 160:5571c4ff569f 948 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
Anna Bridge 160:5571c4ff569f 949 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
Anna Bridge 160:5571c4ff569f 950
Anna Bridge 160:5571c4ff569f 951 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
Anna Bridge 160:5571c4ff569f 952 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
Anna Bridge 160:5571c4ff569f 953
Anna Bridge 160:5571c4ff569f 954 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
Anna Bridge 160:5571c4ff569f 955 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
Anna Bridge 160:5571c4ff569f 956
Anna Bridge 160:5571c4ff569f 957 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
Anna Bridge 160:5571c4ff569f 958 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
Anna Bridge 160:5571c4ff569f 959
Anna Bridge 160:5571c4ff569f 960 /* MPU Memory Attribute Indirection Register 1 Definitions */
Anna Bridge 160:5571c4ff569f 961 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
Anna Bridge 160:5571c4ff569f 962 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
Anna Bridge 160:5571c4ff569f 963
Anna Bridge 160:5571c4ff569f 964 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
Anna Bridge 160:5571c4ff569f 965 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
Anna Bridge 160:5571c4ff569f 966
Anna Bridge 160:5571c4ff569f 967 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
Anna Bridge 160:5571c4ff569f 968 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
Anna Bridge 160:5571c4ff569f 969
Anna Bridge 160:5571c4ff569f 970 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
Anna Bridge 160:5571c4ff569f 971 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
Anna Bridge 160:5571c4ff569f 972
Anna Bridge 160:5571c4ff569f 973 /*@} end of group CMSIS_MPU */
Anna Bridge 160:5571c4ff569f 974 #endif
Anna Bridge 160:5571c4ff569f 975
Anna Bridge 160:5571c4ff569f 976
Anna Bridge 160:5571c4ff569f 977 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 160:5571c4ff569f 978 /**
Anna Bridge 160:5571c4ff569f 979 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 980 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
Anna Bridge 160:5571c4ff569f 981 \brief Type definitions for the Security Attribution Unit (SAU)
Anna Bridge 160:5571c4ff569f 982 @{
Anna Bridge 160:5571c4ff569f 983 */
Anna Bridge 160:5571c4ff569f 984
Anna Bridge 160:5571c4ff569f 985 /**
Anna Bridge 160:5571c4ff569f 986 \brief Structure type to access the Security Attribution Unit (SAU).
Anna Bridge 160:5571c4ff569f 987 */
Anna Bridge 160:5571c4ff569f 988 typedef struct
Anna Bridge 160:5571c4ff569f 989 {
Anna Bridge 160:5571c4ff569f 990 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
Anna Bridge 160:5571c4ff569f 991 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
Anna Bridge 160:5571c4ff569f 992 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 993 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
Anna Bridge 160:5571c4ff569f 994 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
Anna Bridge 160:5571c4ff569f 995 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
Anna Bridge 160:5571c4ff569f 996 #endif
Anna Bridge 160:5571c4ff569f 997 } SAU_Type;
Anna Bridge 160:5571c4ff569f 998
Anna Bridge 160:5571c4ff569f 999 /* SAU Control Register Definitions */
Anna Bridge 160:5571c4ff569f 1000 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
Anna Bridge 160:5571c4ff569f 1001 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
Anna Bridge 160:5571c4ff569f 1002
Anna Bridge 160:5571c4ff569f 1003 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
Anna Bridge 160:5571c4ff569f 1004 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
Anna Bridge 160:5571c4ff569f 1005
Anna Bridge 160:5571c4ff569f 1006 /* SAU Type Register Definitions */
Anna Bridge 160:5571c4ff569f 1007 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
Anna Bridge 160:5571c4ff569f 1008 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
Anna Bridge 160:5571c4ff569f 1009
Anna Bridge 160:5571c4ff569f 1010 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 1011 /* SAU Region Number Register Definitions */
Anna Bridge 160:5571c4ff569f 1012 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
Anna Bridge 160:5571c4ff569f 1013 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
Anna Bridge 160:5571c4ff569f 1014
Anna Bridge 160:5571c4ff569f 1015 /* SAU Region Base Address Register Definitions */
Anna Bridge 160:5571c4ff569f 1016 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
Anna Bridge 160:5571c4ff569f 1017 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
Anna Bridge 160:5571c4ff569f 1018
Anna Bridge 160:5571c4ff569f 1019 /* SAU Region Limit Address Register Definitions */
Anna Bridge 160:5571c4ff569f 1020 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
Anna Bridge 160:5571c4ff569f 1021 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
Anna Bridge 160:5571c4ff569f 1022
Anna Bridge 160:5571c4ff569f 1023 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
Anna Bridge 160:5571c4ff569f 1024 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
Anna Bridge 160:5571c4ff569f 1025
Anna Bridge 160:5571c4ff569f 1026 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
Anna Bridge 160:5571c4ff569f 1027 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
Anna Bridge 160:5571c4ff569f 1028
Anna Bridge 160:5571c4ff569f 1029 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
Anna Bridge 160:5571c4ff569f 1030
Anna Bridge 160:5571c4ff569f 1031 /*@} end of group CMSIS_SAU */
Anna Bridge 160:5571c4ff569f 1032 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 160:5571c4ff569f 1033
Anna Bridge 160:5571c4ff569f 1034
Anna Bridge 160:5571c4ff569f 1035 /**
Anna Bridge 160:5571c4ff569f 1036 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 1037 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge 160:5571c4ff569f 1038 \brief Type definitions for the Core Debug Registers
Anna Bridge 160:5571c4ff569f 1039 @{
Anna Bridge 160:5571c4ff569f 1040 */
Anna Bridge 160:5571c4ff569f 1041
Anna Bridge 160:5571c4ff569f 1042 /**
Anna Bridge 160:5571c4ff569f 1043 \brief Structure type to access the Core Debug Register (CoreDebug).
Anna Bridge 160:5571c4ff569f 1044 */
Anna Bridge 160:5571c4ff569f 1045 typedef struct
Anna Bridge 160:5571c4ff569f 1046 {
Anna Bridge 160:5571c4ff569f 1047 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Anna Bridge 160:5571c4ff569f 1048 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Anna Bridge 160:5571c4ff569f 1049 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Anna Bridge 160:5571c4ff569f 1050 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Anna Bridge 160:5571c4ff569f 1051 uint32_t RESERVED4[1U];
Anna Bridge 160:5571c4ff569f 1052 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
Anna Bridge 160:5571c4ff569f 1053 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
Anna Bridge 160:5571c4ff569f 1054 } CoreDebug_Type;
Anna Bridge 160:5571c4ff569f 1055
Anna Bridge 160:5571c4ff569f 1056 /* Debug Halting Control and Status Register Definitions */
Anna Bridge 160:5571c4ff569f 1057 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
Anna Bridge 160:5571c4ff569f 1058 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Anna Bridge 160:5571c4ff569f 1059
Anna Bridge 160:5571c4ff569f 1060 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
Anna Bridge 160:5571c4ff569f 1061 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
Anna Bridge 160:5571c4ff569f 1062
Anna Bridge 160:5571c4ff569f 1063 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
Anna Bridge 160:5571c4ff569f 1064 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Anna Bridge 160:5571c4ff569f 1065
Anna Bridge 160:5571c4ff569f 1066 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Anna Bridge 160:5571c4ff569f 1067 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Anna Bridge 160:5571c4ff569f 1068
Anna Bridge 160:5571c4ff569f 1069 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
Anna Bridge 160:5571c4ff569f 1070 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Anna Bridge 160:5571c4ff569f 1071
Anna Bridge 160:5571c4ff569f 1072 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
Anna Bridge 160:5571c4ff569f 1073 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Anna Bridge 160:5571c4ff569f 1074
Anna Bridge 160:5571c4ff569f 1075 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
Anna Bridge 160:5571c4ff569f 1076 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Anna Bridge 160:5571c4ff569f 1077
Anna Bridge 160:5571c4ff569f 1078 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
Anna Bridge 160:5571c4ff569f 1079 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Anna Bridge 160:5571c4ff569f 1080
Anna Bridge 160:5571c4ff569f 1081 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
Anna Bridge 160:5571c4ff569f 1082 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Anna Bridge 160:5571c4ff569f 1083
Anna Bridge 160:5571c4ff569f 1084 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
Anna Bridge 160:5571c4ff569f 1085 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Anna Bridge 160:5571c4ff569f 1086
Anna Bridge 160:5571c4ff569f 1087 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
Anna Bridge 160:5571c4ff569f 1088 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Anna Bridge 160:5571c4ff569f 1089
Anna Bridge 160:5571c4ff569f 1090 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Anna Bridge 160:5571c4ff569f 1091 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Anna Bridge 160:5571c4ff569f 1092
Anna Bridge 160:5571c4ff569f 1093 /* Debug Core Register Selector Register Definitions */
Anna Bridge 160:5571c4ff569f 1094 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
Anna Bridge 160:5571c4ff569f 1095 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Anna Bridge 160:5571c4ff569f 1096
Anna Bridge 160:5571c4ff569f 1097 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
Anna Bridge 160:5571c4ff569f 1098 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Anna Bridge 160:5571c4ff569f 1099
Anna Bridge 160:5571c4ff569f 1100 /* Debug Exception and Monitor Control Register */
Anna Bridge 160:5571c4ff569f 1101 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
Anna Bridge 160:5571c4ff569f 1102 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
Anna Bridge 160:5571c4ff569f 1103
Anna Bridge 160:5571c4ff569f 1104 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
Anna Bridge 160:5571c4ff569f 1105 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Anna Bridge 160:5571c4ff569f 1106
Anna Bridge 160:5571c4ff569f 1107 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
Anna Bridge 160:5571c4ff569f 1108 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Anna Bridge 160:5571c4ff569f 1109
Anna Bridge 160:5571c4ff569f 1110 /* Debug Authentication Control Register Definitions */
Anna Bridge 160:5571c4ff569f 1111 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
Anna Bridge 160:5571c4ff569f 1112 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
Anna Bridge 160:5571c4ff569f 1113
Anna Bridge 160:5571c4ff569f 1114 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
Anna Bridge 160:5571c4ff569f 1115 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
Anna Bridge 160:5571c4ff569f 1116
Anna Bridge 160:5571c4ff569f 1117 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
Anna Bridge 160:5571c4ff569f 1118 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
Anna Bridge 160:5571c4ff569f 1119
Anna Bridge 160:5571c4ff569f 1120 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
Anna Bridge 160:5571c4ff569f 1121 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
Anna Bridge 160:5571c4ff569f 1122
Anna Bridge 160:5571c4ff569f 1123 /* Debug Security Control and Status Register Definitions */
Anna Bridge 160:5571c4ff569f 1124 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
Anna Bridge 160:5571c4ff569f 1125 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
Anna Bridge 160:5571c4ff569f 1126
Anna Bridge 160:5571c4ff569f 1127 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
Anna Bridge 160:5571c4ff569f 1128 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
Anna Bridge 160:5571c4ff569f 1129
Anna Bridge 160:5571c4ff569f 1130 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
Anna Bridge 160:5571c4ff569f 1131 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
Anna Bridge 160:5571c4ff569f 1132
Anna Bridge 160:5571c4ff569f 1133 /*@} end of group CMSIS_CoreDebug */
Anna Bridge 160:5571c4ff569f 1134
Anna Bridge 160:5571c4ff569f 1135
Anna Bridge 160:5571c4ff569f 1136 /**
Anna Bridge 160:5571c4ff569f 1137 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 1138 \defgroup CMSIS_core_bitfield Core register bit field macros
Anna Bridge 160:5571c4ff569f 1139 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge 160:5571c4ff569f 1140 @{
Anna Bridge 160:5571c4ff569f 1141 */
Anna Bridge 160:5571c4ff569f 1142
Anna Bridge 160:5571c4ff569f 1143 /**
Anna Bridge 160:5571c4ff569f 1144 \brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge 160:5571c4ff569f 1145 \param[in] field Name of the register bit field.
Anna Bridge 160:5571c4ff569f 1146 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge 160:5571c4ff569f 1147 \return Masked and shifted value.
Anna Bridge 160:5571c4ff569f 1148 */
Anna Bridge 160:5571c4ff569f 1149 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge 160:5571c4ff569f 1150
Anna Bridge 160:5571c4ff569f 1151 /**
Anna Bridge 160:5571c4ff569f 1152 \brief Mask and shift a register value to extract a bit filed value.
Anna Bridge 160:5571c4ff569f 1153 \param[in] field Name of the register bit field.
Anna Bridge 160:5571c4ff569f 1154 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge 160:5571c4ff569f 1155 \return Masked and shifted bit field value.
Anna Bridge 160:5571c4ff569f 1156 */
Anna Bridge 160:5571c4ff569f 1157 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge 160:5571c4ff569f 1158
Anna Bridge 160:5571c4ff569f 1159 /*@} end of group CMSIS_core_bitfield */
Anna Bridge 160:5571c4ff569f 1160
Anna Bridge 160:5571c4ff569f 1161
Anna Bridge 160:5571c4ff569f 1162 /**
Anna Bridge 160:5571c4ff569f 1163 \ingroup CMSIS_core_register
Anna Bridge 160:5571c4ff569f 1164 \defgroup CMSIS_core_base Core Definitions
Anna Bridge 160:5571c4ff569f 1165 \brief Definitions for base addresses, unions, and structures.
Anna Bridge 160:5571c4ff569f 1166 @{
Anna Bridge 160:5571c4ff569f 1167 */
Anna Bridge 160:5571c4ff569f 1168
Anna Bridge 160:5571c4ff569f 1169 /* Memory mapping of Core Hardware */
Anna Bridge 160:5571c4ff569f 1170 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Anna Bridge 160:5571c4ff569f 1171 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Anna Bridge 160:5571c4ff569f 1172 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Anna Bridge 160:5571c4ff569f 1173 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Anna Bridge 160:5571c4ff569f 1174 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Anna Bridge 160:5571c4ff569f 1175 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Anna Bridge 160:5571c4ff569f 1176 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Anna Bridge 160:5571c4ff569f 1177
Anna Bridge 160:5571c4ff569f 1178
Anna Bridge 160:5571c4ff569f 1179 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Anna Bridge 160:5571c4ff569f 1180 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Anna Bridge 160:5571c4ff569f 1181 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Anna Bridge 160:5571c4ff569f 1182 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Anna Bridge 160:5571c4ff569f 1183 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Anna Bridge 160:5571c4ff569f 1184 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
Anna Bridge 160:5571c4ff569f 1185
Anna Bridge 160:5571c4ff569f 1186 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 1187 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Anna Bridge 160:5571c4ff569f 1188 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Anna Bridge 160:5571c4ff569f 1189 #endif
Anna Bridge 160:5571c4ff569f 1190
Anna Bridge 160:5571c4ff569f 1191 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 160:5571c4ff569f 1192 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
Anna Bridge 160:5571c4ff569f 1193 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
Anna Bridge 160:5571c4ff569f 1194 #endif
Anna Bridge 160:5571c4ff569f 1195
Anna Bridge 160:5571c4ff569f 1196 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 160:5571c4ff569f 1197 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
Anna Bridge 160:5571c4ff569f 1198 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
Anna Bridge 160:5571c4ff569f 1199 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
Anna Bridge 160:5571c4ff569f 1200 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
Anna Bridge 160:5571c4ff569f 1201 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
Anna Bridge 160:5571c4ff569f 1202
Anna Bridge 160:5571c4ff569f 1203 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
Anna Bridge 160:5571c4ff569f 1204 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
Anna Bridge 160:5571c4ff569f 1205 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
Anna Bridge 160:5571c4ff569f 1206 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
Anna Bridge 160:5571c4ff569f 1207
Anna Bridge 160:5571c4ff569f 1208 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 1209 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
Anna Bridge 160:5571c4ff569f 1210 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
Anna Bridge 160:5571c4ff569f 1211 #endif
Anna Bridge 160:5571c4ff569f 1212
Anna Bridge 160:5571c4ff569f 1213 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 160:5571c4ff569f 1214 /*@} */
Anna Bridge 160:5571c4ff569f 1215
Anna Bridge 160:5571c4ff569f 1216
Anna Bridge 160:5571c4ff569f 1217
Anna Bridge 160:5571c4ff569f 1218 /*******************************************************************************
Anna Bridge 160:5571c4ff569f 1219 * Hardware Abstraction Layer
Anna Bridge 160:5571c4ff569f 1220 Core Function Interface contains:
Anna Bridge 160:5571c4ff569f 1221 - Core NVIC Functions
Anna Bridge 160:5571c4ff569f 1222 - Core SysTick Functions
Anna Bridge 160:5571c4ff569f 1223 - Core Register Access Functions
Anna Bridge 160:5571c4ff569f 1224 ******************************************************************************/
Anna Bridge 160:5571c4ff569f 1225 /**
Anna Bridge 160:5571c4ff569f 1226 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge 160:5571c4ff569f 1227 */
Anna Bridge 160:5571c4ff569f 1228
Anna Bridge 160:5571c4ff569f 1229
Anna Bridge 160:5571c4ff569f 1230
Anna Bridge 160:5571c4ff569f 1231 /* ########################## NVIC functions #################################### */
Anna Bridge 160:5571c4ff569f 1232 /**
Anna Bridge 160:5571c4ff569f 1233 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 160:5571c4ff569f 1234 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge 160:5571c4ff569f 1235 \brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge 160:5571c4ff569f 1236 @{
Anna Bridge 160:5571c4ff569f 1237 */
Anna Bridge 160:5571c4ff569f 1238
Anna Bridge 160:5571c4ff569f 1239 #ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge 160:5571c4ff569f 1240 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 160:5571c4ff569f 1241 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge 160:5571c4ff569f 1242 #endif
Anna Bridge 160:5571c4ff569f 1243 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 160:5571c4ff569f 1244 #else
Anna Bridge 160:5571c4ff569f 1245 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
Anna Bridge 160:5571c4ff569f 1246 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
Anna Bridge 160:5571c4ff569f 1247 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge 160:5571c4ff569f 1248 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Anna Bridge 160:5571c4ff569f 1249 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge 160:5571c4ff569f 1250 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge 160:5571c4ff569f 1251 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge 160:5571c4ff569f 1252 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge 160:5571c4ff569f 1253 #define NVIC_GetActive __NVIC_GetActive
Anna Bridge 160:5571c4ff569f 1254 #define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge 160:5571c4ff569f 1255 #define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge 160:5571c4ff569f 1256 #define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge 160:5571c4ff569f 1257 #endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge 160:5571c4ff569f 1258
Anna Bridge 160:5571c4ff569f 1259 #ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge 160:5571c4ff569f 1260 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 160:5571c4ff569f 1261 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge 160:5571c4ff569f 1262 #endif
Anna Bridge 160:5571c4ff569f 1263 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 160:5571c4ff569f 1264 #else
Anna Bridge 160:5571c4ff569f 1265 #define NVIC_SetVector __NVIC_SetVector
Anna Bridge 160:5571c4ff569f 1266 #define NVIC_GetVector __NVIC_GetVector
Anna Bridge 160:5571c4ff569f 1267 #endif /* (CMSIS_VECTAB_VIRTUAL) */
Anna Bridge 160:5571c4ff569f 1268
Anna Bridge 160:5571c4ff569f 1269 #define NVIC_USER_IRQ_OFFSET 16
Anna Bridge 160:5571c4ff569f 1270
Anna Bridge 160:5571c4ff569f 1271
Anna Bridge 169:a7c7b631e539 1272 /* Interrupt Priorities are WORD accessible only under Armv6-M */
Anna Bridge 160:5571c4ff569f 1273 /* The following MACROS handle generation of the register offset and byte masks */
Anna Bridge 160:5571c4ff569f 1274 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Anna Bridge 160:5571c4ff569f 1275 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Anna Bridge 160:5571c4ff569f 1276 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Anna Bridge 160:5571c4ff569f 1277
Anna Bridge 160:5571c4ff569f 1278
Anna Bridge 160:5571c4ff569f 1279 /**
Anna Bridge 160:5571c4ff569f 1280 \brief Enable Interrupt
Anna Bridge 160:5571c4ff569f 1281 \details Enables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 160:5571c4ff569f 1282 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1283 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1284 */
Anna Bridge 160:5571c4ff569f 1285 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1286 {
Anna Bridge 160:5571c4ff569f 1287 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1288 {
Anna Bridge 169:a7c7b631e539 1289 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 160:5571c4ff569f 1290 }
Anna Bridge 160:5571c4ff569f 1291 }
Anna Bridge 160:5571c4ff569f 1292
Anna Bridge 160:5571c4ff569f 1293
Anna Bridge 160:5571c4ff569f 1294 /**
Anna Bridge 160:5571c4ff569f 1295 \brief Get Interrupt Enable status
Anna Bridge 160:5571c4ff569f 1296 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Anna Bridge 160:5571c4ff569f 1297 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1298 \return 0 Interrupt is not enabled.
Anna Bridge 160:5571c4ff569f 1299 \return 1 Interrupt is enabled.
Anna Bridge 160:5571c4ff569f 1300 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1301 */
Anna Bridge 160:5571c4ff569f 1302 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1303 {
Anna Bridge 160:5571c4ff569f 1304 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1305 {
Anna Bridge 169:a7c7b631e539 1306 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 160:5571c4ff569f 1307 }
Anna Bridge 160:5571c4ff569f 1308 else
Anna Bridge 160:5571c4ff569f 1309 {
Anna Bridge 160:5571c4ff569f 1310 return(0U);
Anna Bridge 160:5571c4ff569f 1311 }
Anna Bridge 160:5571c4ff569f 1312 }
Anna Bridge 160:5571c4ff569f 1313
Anna Bridge 160:5571c4ff569f 1314
Anna Bridge 160:5571c4ff569f 1315 /**
Anna Bridge 160:5571c4ff569f 1316 \brief Disable Interrupt
Anna Bridge 160:5571c4ff569f 1317 \details Disables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 160:5571c4ff569f 1318 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1319 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1320 */
Anna Bridge 160:5571c4ff569f 1321 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1322 {
Anna Bridge 160:5571c4ff569f 1323 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1324 {
Anna Bridge 169:a7c7b631e539 1325 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 160:5571c4ff569f 1326 __DSB();
Anna Bridge 160:5571c4ff569f 1327 __ISB();
Anna Bridge 160:5571c4ff569f 1328 }
Anna Bridge 160:5571c4ff569f 1329 }
Anna Bridge 160:5571c4ff569f 1330
Anna Bridge 160:5571c4ff569f 1331
Anna Bridge 160:5571c4ff569f 1332 /**
Anna Bridge 160:5571c4ff569f 1333 \brief Get Pending Interrupt
Anna Bridge 160:5571c4ff569f 1334 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Anna Bridge 160:5571c4ff569f 1335 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1336 \return 0 Interrupt status is not pending.
Anna Bridge 160:5571c4ff569f 1337 \return 1 Interrupt status is pending.
Anna Bridge 160:5571c4ff569f 1338 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1339 */
Anna Bridge 160:5571c4ff569f 1340 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1341 {
Anna Bridge 160:5571c4ff569f 1342 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1343 {
Anna Bridge 169:a7c7b631e539 1344 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 160:5571c4ff569f 1345 }
Anna Bridge 160:5571c4ff569f 1346 else
Anna Bridge 160:5571c4ff569f 1347 {
Anna Bridge 160:5571c4ff569f 1348 return(0U);
Anna Bridge 160:5571c4ff569f 1349 }
Anna Bridge 160:5571c4ff569f 1350 }
Anna Bridge 160:5571c4ff569f 1351
Anna Bridge 160:5571c4ff569f 1352
Anna Bridge 160:5571c4ff569f 1353 /**
Anna Bridge 160:5571c4ff569f 1354 \brief Set Pending Interrupt
Anna Bridge 160:5571c4ff569f 1355 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 160:5571c4ff569f 1356 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1357 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1358 */
Anna Bridge 160:5571c4ff569f 1359 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1360 {
Anna Bridge 160:5571c4ff569f 1361 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1362 {
Anna Bridge 169:a7c7b631e539 1363 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 160:5571c4ff569f 1364 }
Anna Bridge 160:5571c4ff569f 1365 }
Anna Bridge 160:5571c4ff569f 1366
Anna Bridge 160:5571c4ff569f 1367
Anna Bridge 160:5571c4ff569f 1368 /**
Anna Bridge 160:5571c4ff569f 1369 \brief Clear Pending Interrupt
Anna Bridge 160:5571c4ff569f 1370 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 160:5571c4ff569f 1371 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1372 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1373 */
Anna Bridge 160:5571c4ff569f 1374 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1375 {
Anna Bridge 160:5571c4ff569f 1376 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1377 {
Anna Bridge 169:a7c7b631e539 1378 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 160:5571c4ff569f 1379 }
Anna Bridge 160:5571c4ff569f 1380 }
Anna Bridge 160:5571c4ff569f 1381
Anna Bridge 160:5571c4ff569f 1382
Anna Bridge 160:5571c4ff569f 1383 /**
Anna Bridge 160:5571c4ff569f 1384 \brief Get Active Interrupt
Anna Bridge 160:5571c4ff569f 1385 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
Anna Bridge 160:5571c4ff569f 1386 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1387 \return 0 Interrupt status is not active.
Anna Bridge 160:5571c4ff569f 1388 \return 1 Interrupt status is active.
Anna Bridge 160:5571c4ff569f 1389 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1390 */
Anna Bridge 160:5571c4ff569f 1391 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1392 {
Anna Bridge 160:5571c4ff569f 1393 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1394 {
Anna Bridge 169:a7c7b631e539 1395 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 160:5571c4ff569f 1396 }
Anna Bridge 160:5571c4ff569f 1397 else
Anna Bridge 160:5571c4ff569f 1398 {
Anna Bridge 160:5571c4ff569f 1399 return(0U);
Anna Bridge 160:5571c4ff569f 1400 }
Anna Bridge 160:5571c4ff569f 1401 }
Anna Bridge 160:5571c4ff569f 1402
Anna Bridge 160:5571c4ff569f 1403
Anna Bridge 160:5571c4ff569f 1404 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 160:5571c4ff569f 1405 /**
Anna Bridge 160:5571c4ff569f 1406 \brief Get Interrupt Target State
Anna Bridge 160:5571c4ff569f 1407 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge 160:5571c4ff569f 1408 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1409 \return 0 if interrupt is assigned to Secure
Anna Bridge 160:5571c4ff569f 1410 \return 1 if interrupt is assigned to Non Secure
Anna Bridge 160:5571c4ff569f 1411 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1412 */
Anna Bridge 160:5571c4ff569f 1413 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1414 {
Anna Bridge 160:5571c4ff569f 1415 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1416 {
Anna Bridge 169:a7c7b631e539 1417 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 160:5571c4ff569f 1418 }
Anna Bridge 160:5571c4ff569f 1419 else
Anna Bridge 160:5571c4ff569f 1420 {
Anna Bridge 160:5571c4ff569f 1421 return(0U);
Anna Bridge 160:5571c4ff569f 1422 }
Anna Bridge 160:5571c4ff569f 1423 }
Anna Bridge 160:5571c4ff569f 1424
Anna Bridge 160:5571c4ff569f 1425
Anna Bridge 160:5571c4ff569f 1426 /**
Anna Bridge 160:5571c4ff569f 1427 \brief Set Interrupt Target State
Anna Bridge 160:5571c4ff569f 1428 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge 160:5571c4ff569f 1429 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1430 \return 0 if interrupt is assigned to Secure
Anna Bridge 160:5571c4ff569f 1431 1 if interrupt is assigned to Non Secure
Anna Bridge 160:5571c4ff569f 1432 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1433 */
Anna Bridge 160:5571c4ff569f 1434 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1435 {
Anna Bridge 160:5571c4ff569f 1436 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1437 {
Anna Bridge 169:a7c7b631e539 1438 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge 169:a7c7b631e539 1439 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 160:5571c4ff569f 1440 }
Anna Bridge 160:5571c4ff569f 1441 else
Anna Bridge 160:5571c4ff569f 1442 {
Anna Bridge 160:5571c4ff569f 1443 return(0U);
Anna Bridge 160:5571c4ff569f 1444 }
Anna Bridge 160:5571c4ff569f 1445 }
Anna Bridge 160:5571c4ff569f 1446
Anna Bridge 160:5571c4ff569f 1447
Anna Bridge 160:5571c4ff569f 1448 /**
Anna Bridge 160:5571c4ff569f 1449 \brief Clear Interrupt Target State
Anna Bridge 160:5571c4ff569f 1450 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge 160:5571c4ff569f 1451 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1452 \return 0 if interrupt is assigned to Secure
Anna Bridge 160:5571c4ff569f 1453 1 if interrupt is assigned to Non Secure
Anna Bridge 160:5571c4ff569f 1454 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1455 */
Anna Bridge 160:5571c4ff569f 1456 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1457 {
Anna Bridge 160:5571c4ff569f 1458 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1459 {
Anna Bridge 169:a7c7b631e539 1460 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge 169:a7c7b631e539 1461 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 160:5571c4ff569f 1462 }
Anna Bridge 160:5571c4ff569f 1463 else
Anna Bridge 160:5571c4ff569f 1464 {
Anna Bridge 160:5571c4ff569f 1465 return(0U);
Anna Bridge 160:5571c4ff569f 1466 }
Anna Bridge 160:5571c4ff569f 1467 }
Anna Bridge 160:5571c4ff569f 1468 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 160:5571c4ff569f 1469
Anna Bridge 160:5571c4ff569f 1470
Anna Bridge 160:5571c4ff569f 1471 /**
Anna Bridge 160:5571c4ff569f 1472 \brief Set Interrupt Priority
Anna Bridge 160:5571c4ff569f 1473 \details Sets the priority of a device specific interrupt or a processor exception.
Anna Bridge 160:5571c4ff569f 1474 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 160:5571c4ff569f 1475 or negative to specify a processor exception.
Anna Bridge 160:5571c4ff569f 1476 \param [in] IRQn Interrupt number.
Anna Bridge 160:5571c4ff569f 1477 \param [in] priority Priority to set.
Anna Bridge 160:5571c4ff569f 1478 \note The priority cannot be set for every processor exception.
Anna Bridge 160:5571c4ff569f 1479 */
Anna Bridge 160:5571c4ff569f 1480 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 160:5571c4ff569f 1481 {
Anna Bridge 160:5571c4ff569f 1482 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1483 {
Anna Bridge 160:5571c4ff569f 1484 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 160:5571c4ff569f 1485 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 160:5571c4ff569f 1486 }
Anna Bridge 160:5571c4ff569f 1487 else
Anna Bridge 160:5571c4ff569f 1488 {
Anna Bridge 160:5571c4ff569f 1489 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 160:5571c4ff569f 1490 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 160:5571c4ff569f 1491 }
Anna Bridge 160:5571c4ff569f 1492 }
Anna Bridge 160:5571c4ff569f 1493
Anna Bridge 160:5571c4ff569f 1494
Anna Bridge 160:5571c4ff569f 1495 /**
Anna Bridge 160:5571c4ff569f 1496 \brief Get Interrupt Priority
Anna Bridge 160:5571c4ff569f 1497 \details Reads the priority of a device specific interrupt or a processor exception.
Anna Bridge 160:5571c4ff569f 1498 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 160:5571c4ff569f 1499 or negative to specify a processor exception.
Anna Bridge 160:5571c4ff569f 1500 \param [in] IRQn Interrupt number.
Anna Bridge 160:5571c4ff569f 1501 \return Interrupt Priority.
Anna Bridge 160:5571c4ff569f 1502 Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge 160:5571c4ff569f 1503 */
Anna Bridge 160:5571c4ff569f 1504 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1505 {
Anna Bridge 160:5571c4ff569f 1506
Anna Bridge 160:5571c4ff569f 1507 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1508 {
Anna Bridge 160:5571c4ff569f 1509 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 160:5571c4ff569f 1510 }
Anna Bridge 160:5571c4ff569f 1511 else
Anna Bridge 160:5571c4ff569f 1512 {
Anna Bridge 160:5571c4ff569f 1513 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 160:5571c4ff569f 1514 }
Anna Bridge 160:5571c4ff569f 1515 }
Anna Bridge 160:5571c4ff569f 1516
Anna Bridge 160:5571c4ff569f 1517
Anna Bridge 160:5571c4ff569f 1518 /**
Anna Bridge 160:5571c4ff569f 1519 \brief Set Interrupt Vector
Anna Bridge 160:5571c4ff569f 1520 \details Sets an interrupt vector in SRAM based interrupt vector table.
Anna Bridge 160:5571c4ff569f 1521 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 160:5571c4ff569f 1522 or negative to specify a processor exception.
Anna Bridge 160:5571c4ff569f 1523 VTOR must been relocated to SRAM before.
Anna Bridge 160:5571c4ff569f 1524 If VTOR is not present address 0 must be mapped to SRAM.
Anna Bridge 160:5571c4ff569f 1525 \param [in] IRQn Interrupt number
Anna Bridge 160:5571c4ff569f 1526 \param [in] vector Address of interrupt handler function
Anna Bridge 160:5571c4ff569f 1527 */
Anna Bridge 160:5571c4ff569f 1528 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge 160:5571c4ff569f 1529 {
Anna Bridge 160:5571c4ff569f 1530 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 1531 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 160:5571c4ff569f 1532 #else
Anna Bridge 160:5571c4ff569f 1533 uint32_t *vectors = (uint32_t *)0x0U;
Anna Bridge 160:5571c4ff569f 1534 #endif
Anna Bridge 160:5571c4ff569f 1535 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Anna Bridge 160:5571c4ff569f 1536 }
Anna Bridge 160:5571c4ff569f 1537
Anna Bridge 160:5571c4ff569f 1538
Anna Bridge 160:5571c4ff569f 1539 /**
Anna Bridge 160:5571c4ff569f 1540 \brief Get Interrupt Vector
Anna Bridge 160:5571c4ff569f 1541 \details Reads an interrupt vector from interrupt vector table.
Anna Bridge 160:5571c4ff569f 1542 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 160:5571c4ff569f 1543 or negative to specify a processor exception.
Anna Bridge 160:5571c4ff569f 1544 \param [in] IRQn Interrupt number.
Anna Bridge 160:5571c4ff569f 1545 \return Address of interrupt handler function
Anna Bridge 160:5571c4ff569f 1546 */
Anna Bridge 160:5571c4ff569f 1547 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1548 {
Anna Bridge 160:5571c4ff569f 1549 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 1550 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 160:5571c4ff569f 1551 #else
Anna Bridge 160:5571c4ff569f 1552 uint32_t *vectors = (uint32_t *)0x0U;
Anna Bridge 160:5571c4ff569f 1553 #endif
Anna Bridge 160:5571c4ff569f 1554 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Anna Bridge 160:5571c4ff569f 1555 }
Anna Bridge 160:5571c4ff569f 1556
Anna Bridge 160:5571c4ff569f 1557
Anna Bridge 160:5571c4ff569f 1558 /**
Anna Bridge 160:5571c4ff569f 1559 \brief System Reset
Anna Bridge 160:5571c4ff569f 1560 \details Initiates a system reset request to reset the MCU.
Anna Bridge 160:5571c4ff569f 1561 */
Anna Bridge 160:5571c4ff569f 1562 __STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge 160:5571c4ff569f 1563 {
Anna Bridge 160:5571c4ff569f 1564 __DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge 160:5571c4ff569f 1565 buffered write are completed before reset */
Anna Bridge 160:5571c4ff569f 1566 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 160:5571c4ff569f 1567 SCB_AIRCR_SYSRESETREQ_Msk);
Anna Bridge 160:5571c4ff569f 1568 __DSB(); /* Ensure completion of memory access */
Anna Bridge 160:5571c4ff569f 1569
Anna Bridge 160:5571c4ff569f 1570 for(;;) /* wait until reset */
Anna Bridge 160:5571c4ff569f 1571 {
Anna Bridge 160:5571c4ff569f 1572 __NOP();
Anna Bridge 160:5571c4ff569f 1573 }
Anna Bridge 160:5571c4ff569f 1574 }
Anna Bridge 160:5571c4ff569f 1575
Anna Bridge 160:5571c4ff569f 1576 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 160:5571c4ff569f 1577 /**
Anna Bridge 160:5571c4ff569f 1578 \brief Enable Interrupt (non-secure)
Anna Bridge 160:5571c4ff569f 1579 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Anna Bridge 160:5571c4ff569f 1580 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1581 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1582 */
Anna Bridge 160:5571c4ff569f 1583 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1584 {
Anna Bridge 160:5571c4ff569f 1585 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1586 {
Anna Bridge 169:a7c7b631e539 1587 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 160:5571c4ff569f 1588 }
Anna Bridge 160:5571c4ff569f 1589 }
Anna Bridge 160:5571c4ff569f 1590
Anna Bridge 160:5571c4ff569f 1591
Anna Bridge 160:5571c4ff569f 1592 /**
Anna Bridge 160:5571c4ff569f 1593 \brief Get Interrupt Enable status (non-secure)
Anna Bridge 160:5571c4ff569f 1594 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
Anna Bridge 160:5571c4ff569f 1595 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1596 \return 0 Interrupt is not enabled.
Anna Bridge 160:5571c4ff569f 1597 \return 1 Interrupt is enabled.
Anna Bridge 160:5571c4ff569f 1598 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1599 */
Anna Bridge 160:5571c4ff569f 1600 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1601 {
Anna Bridge 160:5571c4ff569f 1602 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1603 {
Anna Bridge 169:a7c7b631e539 1604 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 160:5571c4ff569f 1605 }
Anna Bridge 160:5571c4ff569f 1606 else
Anna Bridge 160:5571c4ff569f 1607 {
Anna Bridge 160:5571c4ff569f 1608 return(0U);
Anna Bridge 160:5571c4ff569f 1609 }
Anna Bridge 160:5571c4ff569f 1610 }
Anna Bridge 160:5571c4ff569f 1611
Anna Bridge 160:5571c4ff569f 1612
Anna Bridge 160:5571c4ff569f 1613 /**
Anna Bridge 160:5571c4ff569f 1614 \brief Disable Interrupt (non-secure)
Anna Bridge 160:5571c4ff569f 1615 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Anna Bridge 160:5571c4ff569f 1616 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1617 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1618 */
Anna Bridge 160:5571c4ff569f 1619 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1620 {
Anna Bridge 160:5571c4ff569f 1621 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1622 {
Anna Bridge 169:a7c7b631e539 1623 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 160:5571c4ff569f 1624 }
Anna Bridge 160:5571c4ff569f 1625 }
Anna Bridge 160:5571c4ff569f 1626
Anna Bridge 160:5571c4ff569f 1627
Anna Bridge 160:5571c4ff569f 1628 /**
Anna Bridge 160:5571c4ff569f 1629 \brief Get Pending Interrupt (non-secure)
Anna Bridge 160:5571c4ff569f 1630 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
Anna Bridge 160:5571c4ff569f 1631 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1632 \return 0 Interrupt status is not pending.
Anna Bridge 160:5571c4ff569f 1633 \return 1 Interrupt status is pending.
Anna Bridge 160:5571c4ff569f 1634 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1635 */
Anna Bridge 160:5571c4ff569f 1636 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1637 {
Anna Bridge 160:5571c4ff569f 1638 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1639 {
Anna Bridge 169:a7c7b631e539 1640 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 160:5571c4ff569f 1641 }
Anna Bridge 160:5571c4ff569f 1642 else
Anna Bridge 160:5571c4ff569f 1643 {
Anna Bridge 160:5571c4ff569f 1644 return(0U);
Anna Bridge 160:5571c4ff569f 1645 }
Anna Bridge 160:5571c4ff569f 1646 }
Anna Bridge 160:5571c4ff569f 1647
Anna Bridge 160:5571c4ff569f 1648
Anna Bridge 160:5571c4ff569f 1649 /**
Anna Bridge 160:5571c4ff569f 1650 \brief Set Pending Interrupt (non-secure)
Anna Bridge 160:5571c4ff569f 1651 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Anna Bridge 160:5571c4ff569f 1652 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1653 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1654 */
Anna Bridge 160:5571c4ff569f 1655 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1656 {
Anna Bridge 160:5571c4ff569f 1657 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1658 {
Anna Bridge 169:a7c7b631e539 1659 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 160:5571c4ff569f 1660 }
Anna Bridge 160:5571c4ff569f 1661 }
Anna Bridge 160:5571c4ff569f 1662
Anna Bridge 160:5571c4ff569f 1663
Anna Bridge 160:5571c4ff569f 1664 /**
Anna Bridge 160:5571c4ff569f 1665 \brief Clear Pending Interrupt (non-secure)
Anna Bridge 160:5571c4ff569f 1666 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Anna Bridge 160:5571c4ff569f 1667 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1668 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1669 */
Anna Bridge 160:5571c4ff569f 1670 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1671 {
Anna Bridge 160:5571c4ff569f 1672 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1673 {
Anna Bridge 169:a7c7b631e539 1674 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 160:5571c4ff569f 1675 }
Anna Bridge 160:5571c4ff569f 1676 }
Anna Bridge 160:5571c4ff569f 1677
Anna Bridge 160:5571c4ff569f 1678
Anna Bridge 160:5571c4ff569f 1679 /**
Anna Bridge 160:5571c4ff569f 1680 \brief Get Active Interrupt (non-secure)
Anna Bridge 160:5571c4ff569f 1681 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
Anna Bridge 160:5571c4ff569f 1682 \param [in] IRQn Device specific interrupt number.
Anna Bridge 160:5571c4ff569f 1683 \return 0 Interrupt status is not active.
Anna Bridge 160:5571c4ff569f 1684 \return 1 Interrupt status is active.
Anna Bridge 160:5571c4ff569f 1685 \note IRQn must not be negative.
Anna Bridge 160:5571c4ff569f 1686 */
Anna Bridge 160:5571c4ff569f 1687 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1688 {
Anna Bridge 160:5571c4ff569f 1689 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1690 {
Anna Bridge 169:a7c7b631e539 1691 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 160:5571c4ff569f 1692 }
Anna Bridge 160:5571c4ff569f 1693 else
Anna Bridge 160:5571c4ff569f 1694 {
Anna Bridge 160:5571c4ff569f 1695 return(0U);
Anna Bridge 160:5571c4ff569f 1696 }
Anna Bridge 160:5571c4ff569f 1697 }
Anna Bridge 160:5571c4ff569f 1698
Anna Bridge 160:5571c4ff569f 1699
Anna Bridge 160:5571c4ff569f 1700 /**
Anna Bridge 160:5571c4ff569f 1701 \brief Set Interrupt Priority (non-secure)
Anna Bridge 160:5571c4ff569f 1702 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Anna Bridge 160:5571c4ff569f 1703 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 160:5571c4ff569f 1704 or negative to specify a processor exception.
Anna Bridge 160:5571c4ff569f 1705 \param [in] IRQn Interrupt number.
Anna Bridge 160:5571c4ff569f 1706 \param [in] priority Priority to set.
Anna Bridge 160:5571c4ff569f 1707 \note The priority cannot be set for every non-secure processor exception.
Anna Bridge 160:5571c4ff569f 1708 */
Anna Bridge 160:5571c4ff569f 1709 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 160:5571c4ff569f 1710 {
Anna Bridge 160:5571c4ff569f 1711 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1712 {
Anna Bridge 160:5571c4ff569f 1713 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 160:5571c4ff569f 1714 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 160:5571c4ff569f 1715 }
Anna Bridge 160:5571c4ff569f 1716 else
Anna Bridge 160:5571c4ff569f 1717 {
Anna Bridge 160:5571c4ff569f 1718 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 160:5571c4ff569f 1719 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 160:5571c4ff569f 1720 }
Anna Bridge 160:5571c4ff569f 1721 }
Anna Bridge 160:5571c4ff569f 1722
Anna Bridge 160:5571c4ff569f 1723
Anna Bridge 160:5571c4ff569f 1724 /**
Anna Bridge 160:5571c4ff569f 1725 \brief Get Interrupt Priority (non-secure)
Anna Bridge 160:5571c4ff569f 1726 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Anna Bridge 160:5571c4ff569f 1727 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 160:5571c4ff569f 1728 or negative to specify a processor exception.
Anna Bridge 160:5571c4ff569f 1729 \param [in] IRQn Interrupt number.
Anna Bridge 160:5571c4ff569f 1730 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge 160:5571c4ff569f 1731 */
Anna Bridge 160:5571c4ff569f 1732 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
Anna Bridge 160:5571c4ff569f 1733 {
Anna Bridge 160:5571c4ff569f 1734
Anna Bridge 160:5571c4ff569f 1735 if ((int32_t)(IRQn) >= 0)
Anna Bridge 160:5571c4ff569f 1736 {
Anna Bridge 160:5571c4ff569f 1737 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 160:5571c4ff569f 1738 }
Anna Bridge 160:5571c4ff569f 1739 else
Anna Bridge 160:5571c4ff569f 1740 {
Anna Bridge 160:5571c4ff569f 1741 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 160:5571c4ff569f 1742 }
Anna Bridge 160:5571c4ff569f 1743 }
Anna Bridge 160:5571c4ff569f 1744 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 160:5571c4ff569f 1745
Anna Bridge 160:5571c4ff569f 1746 /*@} end of CMSIS_Core_NVICFunctions */
Anna Bridge 160:5571c4ff569f 1747
Anna Bridge 160:5571c4ff569f 1748 /* ########################## MPU functions #################################### */
Anna Bridge 160:5571c4ff569f 1749
Anna Bridge 160:5571c4ff569f 1750 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 160:5571c4ff569f 1751
Anna Bridge 160:5571c4ff569f 1752 #include "mpu_armv8.h"
Anna Bridge 160:5571c4ff569f 1753
Anna Bridge 160:5571c4ff569f 1754 #endif
Anna Bridge 160:5571c4ff569f 1755
Anna Bridge 160:5571c4ff569f 1756 /* ########################## FPU functions #################################### */
Anna Bridge 160:5571c4ff569f 1757 /**
Anna Bridge 160:5571c4ff569f 1758 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 160:5571c4ff569f 1759 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Anna Bridge 160:5571c4ff569f 1760 \brief Function that provides FPU type.
Anna Bridge 160:5571c4ff569f 1761 @{
Anna Bridge 160:5571c4ff569f 1762 */
Anna Bridge 160:5571c4ff569f 1763
Anna Bridge 160:5571c4ff569f 1764 /**
Anna Bridge 160:5571c4ff569f 1765 \brief get FPU type
Anna Bridge 160:5571c4ff569f 1766 \details returns the FPU type
Anna Bridge 160:5571c4ff569f 1767 \returns
Anna Bridge 160:5571c4ff569f 1768 - \b 0: No FPU
Anna Bridge 160:5571c4ff569f 1769 - \b 1: Single precision FPU
Anna Bridge 160:5571c4ff569f 1770 - \b 2: Double + Single precision FPU
Anna Bridge 160:5571c4ff569f 1771 */
Anna Bridge 160:5571c4ff569f 1772 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Anna Bridge 160:5571c4ff569f 1773 {
Anna Bridge 160:5571c4ff569f 1774 return 0U; /* No FPU */
Anna Bridge 160:5571c4ff569f 1775 }
Anna Bridge 160:5571c4ff569f 1776
Anna Bridge 160:5571c4ff569f 1777
Anna Bridge 160:5571c4ff569f 1778 /*@} end of CMSIS_Core_FpuFunctions */
Anna Bridge 160:5571c4ff569f 1779
Anna Bridge 160:5571c4ff569f 1780
Anna Bridge 160:5571c4ff569f 1781
Anna Bridge 160:5571c4ff569f 1782 /* ########################## SAU functions #################################### */
Anna Bridge 160:5571c4ff569f 1783 /**
Anna Bridge 160:5571c4ff569f 1784 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 160:5571c4ff569f 1785 \defgroup CMSIS_Core_SAUFunctions SAU Functions
Anna Bridge 160:5571c4ff569f 1786 \brief Functions that configure the SAU.
Anna Bridge 160:5571c4ff569f 1787 @{
Anna Bridge 160:5571c4ff569f 1788 */
Anna Bridge 160:5571c4ff569f 1789
Anna Bridge 160:5571c4ff569f 1790 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 160:5571c4ff569f 1791
Anna Bridge 160:5571c4ff569f 1792 /**
Anna Bridge 160:5571c4ff569f 1793 \brief Enable SAU
Anna Bridge 160:5571c4ff569f 1794 \details Enables the Security Attribution Unit (SAU).
Anna Bridge 160:5571c4ff569f 1795 */
Anna Bridge 160:5571c4ff569f 1796 __STATIC_INLINE void TZ_SAU_Enable(void)
Anna Bridge 160:5571c4ff569f 1797 {
Anna Bridge 160:5571c4ff569f 1798 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
Anna Bridge 160:5571c4ff569f 1799 }
Anna Bridge 160:5571c4ff569f 1800
Anna Bridge 160:5571c4ff569f 1801
Anna Bridge 160:5571c4ff569f 1802
Anna Bridge 160:5571c4ff569f 1803 /**
Anna Bridge 160:5571c4ff569f 1804 \brief Disable SAU
Anna Bridge 160:5571c4ff569f 1805 \details Disables the Security Attribution Unit (SAU).
Anna Bridge 160:5571c4ff569f 1806 */
Anna Bridge 160:5571c4ff569f 1807 __STATIC_INLINE void TZ_SAU_Disable(void)
Anna Bridge 160:5571c4ff569f 1808 {
Anna Bridge 160:5571c4ff569f 1809 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
Anna Bridge 160:5571c4ff569f 1810 }
Anna Bridge 160:5571c4ff569f 1811
Anna Bridge 160:5571c4ff569f 1812 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 160:5571c4ff569f 1813
Anna Bridge 160:5571c4ff569f 1814 /*@} end of CMSIS_Core_SAUFunctions */
Anna Bridge 160:5571c4ff569f 1815
Anna Bridge 160:5571c4ff569f 1816
Anna Bridge 160:5571c4ff569f 1817
Anna Bridge 160:5571c4ff569f 1818
Anna Bridge 160:5571c4ff569f 1819 /* ################################## SysTick function ############################################ */
Anna Bridge 160:5571c4ff569f 1820 /**
Anna Bridge 160:5571c4ff569f 1821 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 160:5571c4ff569f 1822 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge 160:5571c4ff569f 1823 \brief Functions that configure the System.
Anna Bridge 160:5571c4ff569f 1824 @{
Anna Bridge 160:5571c4ff569f 1825 */
Anna Bridge 160:5571c4ff569f 1826
Anna Bridge 160:5571c4ff569f 1827 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge 160:5571c4ff569f 1828
Anna Bridge 160:5571c4ff569f 1829 /**
Anna Bridge 160:5571c4ff569f 1830 \brief System Tick Configuration
Anna Bridge 160:5571c4ff569f 1831 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge 160:5571c4ff569f 1832 Counter is in free running mode to generate periodic interrupts.
Anna Bridge 160:5571c4ff569f 1833 \param [in] ticks Number of ticks between two interrupts.
Anna Bridge 160:5571c4ff569f 1834 \return 0 Function succeeded.
Anna Bridge 160:5571c4ff569f 1835 \return 1 Function failed.
Anna Bridge 160:5571c4ff569f 1836 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge 160:5571c4ff569f 1837 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge 160:5571c4ff569f 1838 must contain a vendor-specific implementation of this function.
Anna Bridge 160:5571c4ff569f 1839 */
Anna Bridge 160:5571c4ff569f 1840 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge 160:5571c4ff569f 1841 {
Anna Bridge 160:5571c4ff569f 1842 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge 160:5571c4ff569f 1843 {
Anna Bridge 160:5571c4ff569f 1844 return (1UL); /* Reload value impossible */
Anna Bridge 160:5571c4ff569f 1845 }
Anna Bridge 160:5571c4ff569f 1846
Anna Bridge 160:5571c4ff569f 1847 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 160:5571c4ff569f 1848 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 160:5571c4ff569f 1849 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 160:5571c4ff569f 1850 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 160:5571c4ff569f 1851 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 160:5571c4ff569f 1852 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 160:5571c4ff569f 1853 return (0UL); /* Function successful */
Anna Bridge 160:5571c4ff569f 1854 }
Anna Bridge 160:5571c4ff569f 1855
Anna Bridge 160:5571c4ff569f 1856 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 160:5571c4ff569f 1857 /**
Anna Bridge 160:5571c4ff569f 1858 \brief System Tick Configuration (non-secure)
Anna Bridge 160:5571c4ff569f 1859 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Anna Bridge 160:5571c4ff569f 1860 Counter is in free running mode to generate periodic interrupts.
Anna Bridge 160:5571c4ff569f 1861 \param [in] ticks Number of ticks between two interrupts.
Anna Bridge 160:5571c4ff569f 1862 \return 0 Function succeeded.
Anna Bridge 160:5571c4ff569f 1863 \return 1 Function failed.
Anna Bridge 160:5571c4ff569f 1864 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge 160:5571c4ff569f 1865 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge 160:5571c4ff569f 1866 must contain a vendor-specific implementation of this function.
Anna Bridge 160:5571c4ff569f 1867
Anna Bridge 160:5571c4ff569f 1868 */
Anna Bridge 160:5571c4ff569f 1869 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
Anna Bridge 160:5571c4ff569f 1870 {
Anna Bridge 160:5571c4ff569f 1871 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge 160:5571c4ff569f 1872 {
Anna Bridge 160:5571c4ff569f 1873 return (1UL); /* Reload value impossible */
Anna Bridge 160:5571c4ff569f 1874 }
Anna Bridge 160:5571c4ff569f 1875
Anna Bridge 160:5571c4ff569f 1876 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 160:5571c4ff569f 1877 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 160:5571c4ff569f 1878 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 160:5571c4ff569f 1879 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 160:5571c4ff569f 1880 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 160:5571c4ff569f 1881 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 160:5571c4ff569f 1882 return (0UL); /* Function successful */
Anna Bridge 160:5571c4ff569f 1883 }
Anna Bridge 160:5571c4ff569f 1884 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 160:5571c4ff569f 1885
Anna Bridge 160:5571c4ff569f 1886 #endif
Anna Bridge 160:5571c4ff569f 1887
Anna Bridge 160:5571c4ff569f 1888 /*@} end of CMSIS_Core_SysTickFunctions */
Anna Bridge 160:5571c4ff569f 1889
Anna Bridge 160:5571c4ff569f 1890
Anna Bridge 160:5571c4ff569f 1891
Anna Bridge 160:5571c4ff569f 1892
Anna Bridge 160:5571c4ff569f 1893 #ifdef __cplusplus
Anna Bridge 160:5571c4ff569f 1894 }
Anna Bridge 160:5571c4ff569f 1895 #endif
Anna Bridge 160:5571c4ff569f 1896
Anna Bridge 160:5571c4ff569f 1897 #endif /* __CORE_CM23_H_DEPENDANT */
Anna Bridge 160:5571c4ff569f 1898
Anna Bridge 160:5571c4ff569f 1899 #endif /* __CMSIS_GENERIC */