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TARGET_MTB_ADV_WISE_1530/mpu_armv7.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
167:84c0a372a020 
mbed library. Release version 162

Who changed what in which revision?

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AnnaBridge 167:84c0a372a020 1 /******************************************************************************
AnnaBridge 167:84c0a372a020 2 * @file mpu_armv7.h
Anna Bridge 169:a7c7b631e539 3 * @brief CMSIS MPU API for Armv7-M MPU
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.4
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
AnnaBridge 167:84c0a372a020 6 ******************************************************************************/
AnnaBridge 167:84c0a372a020 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
AnnaBridge 167:84c0a372a020 9 *
AnnaBridge 167:84c0a372a020 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 167:84c0a372a020 11 *
AnnaBridge 167:84c0a372a020 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 167:84c0a372a020 13 * not use this file except in compliance with the License.
AnnaBridge 167:84c0a372a020 14 * You may obtain a copy of the License at
AnnaBridge 167:84c0a372a020 15 *
AnnaBridge 167:84c0a372a020 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 167:84c0a372a020 17 *
AnnaBridge 167:84c0a372a020 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:84c0a372a020 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 167:84c0a372a020 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:84c0a372a020 21 * See the License for the specific language governing permissions and
AnnaBridge 167:84c0a372a020 22 * limitations under the License.
AnnaBridge 167:84c0a372a020 23 */
AnnaBridge 167:84c0a372a020 24
Anna Bridge 169:a7c7b631e539 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
Anna Bridge 169:a7c7b631e539 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 169:a7c7b631e539 29 #endif
Anna Bridge 169:a7c7b631e539 30
AnnaBridge 167:84c0a372a020 31 #ifndef ARM_MPU_ARMV7_H
AnnaBridge 167:84c0a372a020 32 #define ARM_MPU_ARMV7_H
AnnaBridge 167:84c0a372a020 33
AnnaBridge 167:84c0a372a020 34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
AnnaBridge 167:84c0a372a020 35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
AnnaBridge 167:84c0a372a020 36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
AnnaBridge 167:84c0a372a020 37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
AnnaBridge 167:84c0a372a020 38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
AnnaBridge 167:84c0a372a020 39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
AnnaBridge 167:84c0a372a020 40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
AnnaBridge 167:84c0a372a020 41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
AnnaBridge 167:84c0a372a020 42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
AnnaBridge 167:84c0a372a020 43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
AnnaBridge 167:84c0a372a020 44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
AnnaBridge 167:84c0a372a020 45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
AnnaBridge 167:84c0a372a020 46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
AnnaBridge 167:84c0a372a020 47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
AnnaBridge 167:84c0a372a020 48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
AnnaBridge 167:84c0a372a020 49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
AnnaBridge 167:84c0a372a020 50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
AnnaBridge 167:84c0a372a020 51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
AnnaBridge 167:84c0a372a020 52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
AnnaBridge 167:84c0a372a020 53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
AnnaBridge 167:84c0a372a020 54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
AnnaBridge 167:84c0a372a020 55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
AnnaBridge 167:84c0a372a020 56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
AnnaBridge 167:84c0a372a020 57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
AnnaBridge 167:84c0a372a020 58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
AnnaBridge 167:84c0a372a020 59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
AnnaBridge 167:84c0a372a020 60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
AnnaBridge 167:84c0a372a020 61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 #define ARM_MPU_AP_NONE 0U
AnnaBridge 167:84c0a372a020 64 #define ARM_MPU_AP_PRIV 1U
AnnaBridge 167:84c0a372a020 65 #define ARM_MPU_AP_URO 2U
AnnaBridge 167:84c0a372a020 66 #define ARM_MPU_AP_FULL 3U
AnnaBridge 167:84c0a372a020 67 #define ARM_MPU_AP_PRO 5U
AnnaBridge 167:84c0a372a020 68 #define ARM_MPU_AP_RO 6U
AnnaBridge 167:84c0a372a020 69
AnnaBridge 167:84c0a372a020 70 /** MPU Region Base Address Register Value
AnnaBridge 167:84c0a372a020 71 *
AnnaBridge 167:84c0a372a020 72 * \param Region The region to be configured, number 0 to 15.
AnnaBridge 167:84c0a372a020 73 * \param BaseAddress The base address for the region.
AnnaBridge 167:84c0a372a020 74 */
AnnaBridge 167:84c0a372a020 75 #define ARM_MPU_RBAR(Region, BaseAddress) \
AnnaBridge 167:84c0a372a020 76 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
AnnaBridge 167:84c0a372a020 77 ((Region) & MPU_RBAR_REGION_Msk) | \
AnnaBridge 167:84c0a372a020 78 (MPU_RBAR_VALID_Msk))
AnnaBridge 167:84c0a372a020 79
AnnaBridge 167:84c0a372a020 80 /**
Anna Bridge 169:a7c7b631e539 81 * MPU Region Attribute and Size Register Value
AnnaBridge 167:84c0a372a020 82 *
AnnaBridge 167:84c0a372a020 83 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
AnnaBridge 167:84c0a372a020 84 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
AnnaBridge 167:84c0a372a020 85 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
AnnaBridge 167:84c0a372a020 86 * \param IsShareable Region is shareable between multiple bus masters.
AnnaBridge 167:84c0a372a020 87 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
AnnaBridge 167:84c0a372a020 88 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
AnnaBridge 167:84c0a372a020 89 * \param SubRegionDisable Sub-region disable field.
AnnaBridge 167:84c0a372a020 90 * \param Size Region size of the region to be configured, for example 4K, 8K.
AnnaBridge 167:84c0a372a020 91 */
AnnaBridge 167:84c0a372a020 92 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
AnnaBridge 167:84c0a372a020 93 ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
AnnaBridge 167:84c0a372a020 94 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
AnnaBridge 167:84c0a372a020 95 (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
AnnaBridge 167:84c0a372a020 96 (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
AnnaBridge 167:84c0a372a020 97 (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
AnnaBridge 167:84c0a372a020 98 (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
AnnaBridge 167:84c0a372a020 99 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
AnnaBridge 167:84c0a372a020 100 (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
AnnaBridge 167:84c0a372a020 101 (MPU_RASR_ENABLE_Msk))
AnnaBridge 167:84c0a372a020 102
AnnaBridge 167:84c0a372a020 103
AnnaBridge 167:84c0a372a020 104 /**
AnnaBridge 167:84c0a372a020 105 * Struct for a single MPU Region
AnnaBridge 167:84c0a372a020 106 */
Anna Bridge 169:a7c7b631e539 107 typedef struct {
AnnaBridge 167:84c0a372a020 108 uint32_t RBAR; //!< The region base address register value (RBAR)
AnnaBridge 167:84c0a372a020 109 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
AnnaBridge 167:84c0a372a020 110 } ARM_MPU_Region_t;
AnnaBridge 167:84c0a372a020 111
AnnaBridge 167:84c0a372a020 112 /** Enable the MPU.
AnnaBridge 167:84c0a372a020 113 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 167:84c0a372a020 114 */
AnnaBridge 167:84c0a372a020 115 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
AnnaBridge 167:84c0a372a020 116 {
AnnaBridge 167:84c0a372a020 117 __DSB();
AnnaBridge 167:84c0a372a020 118 __ISB();
AnnaBridge 167:84c0a372a020 119 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 167:84c0a372a020 120 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 167:84c0a372a020 121 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 167:84c0a372a020 122 #endif
AnnaBridge 167:84c0a372a020 123 }
AnnaBridge 167:84c0a372a020 124
AnnaBridge 167:84c0a372a020 125 /** Disable the MPU.
AnnaBridge 167:84c0a372a020 126 */
AnnaBridge 167:84c0a372a020 127 __STATIC_INLINE void ARM_MPU_Disable(void)
AnnaBridge 167:84c0a372a020 128 {
AnnaBridge 167:84c0a372a020 129 __DSB();
AnnaBridge 167:84c0a372a020 130 __ISB();
AnnaBridge 167:84c0a372a020 131 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 167:84c0a372a020 132 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 167:84c0a372a020 133 #endif
AnnaBridge 167:84c0a372a020 134 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 167:84c0a372a020 135 }
AnnaBridge 167:84c0a372a020 136
AnnaBridge 167:84c0a372a020 137 /** Clear and disable the given MPU region.
AnnaBridge 167:84c0a372a020 138 * \param rnr Region number to be cleared.
AnnaBridge 167:84c0a372a020 139 */
AnnaBridge 167:84c0a372a020 140 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
AnnaBridge 167:84c0a372a020 141 {
AnnaBridge 167:84c0a372a020 142 MPU->RNR = rnr;
AnnaBridge 167:84c0a372a020 143 MPU->RASR = 0U;
AnnaBridge 167:84c0a372a020 144 }
AnnaBridge 167:84c0a372a020 145
AnnaBridge 167:84c0a372a020 146 /** Configure an MPU region.
AnnaBridge 167:84c0a372a020 147 * \param rbar Value for RBAR register.
AnnaBridge 167:84c0a372a020 148 * \param rsar Value for RSAR register.
AnnaBridge 167:84c0a372a020 149 */
AnnaBridge 167:84c0a372a020 150 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
AnnaBridge 167:84c0a372a020 151 {
AnnaBridge 167:84c0a372a020 152 MPU->RBAR = rbar;
AnnaBridge 167:84c0a372a020 153 MPU->RASR = rasr;
AnnaBridge 167:84c0a372a020 154 }
AnnaBridge 167:84c0a372a020 155
AnnaBridge 167:84c0a372a020 156 /** Configure the given MPU region.
AnnaBridge 167:84c0a372a020 157 * \param rnr Region number to be configured.
AnnaBridge 167:84c0a372a020 158 * \param rbar Value for RBAR register.
AnnaBridge 167:84c0a372a020 159 * \param rsar Value for RSAR register.
AnnaBridge 167:84c0a372a020 160 */
AnnaBridge 167:84c0a372a020 161 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
AnnaBridge 167:84c0a372a020 162 {
AnnaBridge 167:84c0a372a020 163 MPU->RNR = rnr;
AnnaBridge 167:84c0a372a020 164 MPU->RBAR = rbar;
AnnaBridge 167:84c0a372a020 165 MPU->RASR = rasr;
AnnaBridge 167:84c0a372a020 166 }
AnnaBridge 167:84c0a372a020 167
AnnaBridge 167:84c0a372a020 168 /** Memcopy with strictly ordered memory access, e.g. for register targets.
AnnaBridge 167:84c0a372a020 169 * \param dst Destination data is copied to.
AnnaBridge 167:84c0a372a020 170 * \param src Source data is copied from.
AnnaBridge 167:84c0a372a020 171 * \param len Amount of data words to be copied.
AnnaBridge 167:84c0a372a020 172 */
AnnaBridge 167:84c0a372a020 173 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
AnnaBridge 167:84c0a372a020 174 {
AnnaBridge 167:84c0a372a020 175 uint32_t i;
AnnaBridge 167:84c0a372a020 176 for (i = 0U; i < len; ++i)
AnnaBridge 167:84c0a372a020 177 {
AnnaBridge 167:84c0a372a020 178 dst[i] = src[i];
AnnaBridge 167:84c0a372a020 179 }
AnnaBridge 167:84c0a372a020 180 }
AnnaBridge 167:84c0a372a020 181
AnnaBridge 167:84c0a372a020 182 /** Load the given number of MPU regions from a table.
AnnaBridge 167:84c0a372a020 183 * \param table Pointer to the MPU configuration table.
AnnaBridge 167:84c0a372a020 184 * \param cnt Amount of regions to be configured.
AnnaBridge 167:84c0a372a020 185 */
AnnaBridge 167:84c0a372a020 186 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 167:84c0a372a020 187 {
Anna Bridge 169:a7c7b631e539 188 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
Anna Bridge 169:a7c7b631e539 189 while (cnt > MPU_TYPE_RALIASES) {
AnnaBridge 167:84c0a372a020 190 orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
Anna Bridge 169:a7c7b631e539 191 table += MPU_TYPE_RALIASES;
Anna Bridge 169:a7c7b631e539 192 cnt -= MPU_TYPE_RALIASES;
AnnaBridge 167:84c0a372a020 193 }
Anna Bridge 169:a7c7b631e539 194 orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
AnnaBridge 167:84c0a372a020 195 }
AnnaBridge 167:84c0a372a020 196
AnnaBridge 167:84c0a372a020 197 #endif