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TARGET_MTB_ADV_WISE_1530/core_sc000.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
167:84c0a372a020 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /**************************************************************************//**
AnnaBridge 167:84c0a372a020 2 * @file core_sc000.h
AnnaBridge 167:84c0a372a020 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.3
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
AnnaBridge 167:84c0a372a020 6 ******************************************************************************/
AnnaBridge 167:84c0a372a020 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 167:84c0a372a020 9 *
AnnaBridge 167:84c0a372a020 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 167:84c0a372a020 11 *
AnnaBridge 167:84c0a372a020 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 167:84c0a372a020 13 * not use this file except in compliance with the License.
AnnaBridge 167:84c0a372a020 14 * You may obtain a copy of the License at
AnnaBridge 167:84c0a372a020 15 *
AnnaBridge 167:84c0a372a020 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 167:84c0a372a020 17 *
AnnaBridge 167:84c0a372a020 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:84c0a372a020 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 167:84c0a372a020 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:84c0a372a020 21 * See the License for the specific language governing permissions and
AnnaBridge 167:84c0a372a020 22 * limitations under the License.
AnnaBridge 167:84c0a372a020 23 */
AnnaBridge 167:84c0a372a020 24
AnnaBridge 167:84c0a372a020 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
AnnaBridge 167:84c0a372a020 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 167:84c0a372a020 29 #endif
AnnaBridge 167:84c0a372a020 30
AnnaBridge 167:84c0a372a020 31 #ifndef __CORE_SC000_H_GENERIC
AnnaBridge 167:84c0a372a020 32 #define __CORE_SC000_H_GENERIC
AnnaBridge 167:84c0a372a020 33
AnnaBridge 167:84c0a372a020 34 #include <stdint.h>
AnnaBridge 167:84c0a372a020 35
AnnaBridge 167:84c0a372a020 36 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 37 extern "C" {
AnnaBridge 167:84c0a372a020 38 #endif
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 /**
AnnaBridge 167:84c0a372a020 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 167:84c0a372a020 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 167:84c0a372a020 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 167:84c0a372a020 46
AnnaBridge 167:84c0a372a020 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 167:84c0a372a020 48 Unions are used for effective representation of core registers.
AnnaBridge 167:84c0a372a020 49
AnnaBridge 167:84c0a372a020 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 167:84c0a372a020 51 Function-like macros are used to allow more efficient code.
AnnaBridge 167:84c0a372a020 52 */
AnnaBridge 167:84c0a372a020 53
AnnaBridge 167:84c0a372a020 54
AnnaBridge 167:84c0a372a020 55 /*******************************************************************************
AnnaBridge 167:84c0a372a020 56 * CMSIS definitions
AnnaBridge 167:84c0a372a020 57 ******************************************************************************/
AnnaBridge 167:84c0a372a020 58 /**
AnnaBridge 167:84c0a372a020 59 \ingroup SC000
AnnaBridge 167:84c0a372a020 60 @{
AnnaBridge 167:84c0a372a020 61 */
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 #include "cmsis_version.h"
AnnaBridge 167:84c0a372a020 64
AnnaBridge 167:84c0a372a020 65 /* CMSIS SC000 definitions */
AnnaBridge 167:84c0a372a020 66 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
AnnaBridge 167:84c0a372a020 67 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 167:84c0a372a020 68 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 167:84c0a372a020 69 __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 167:84c0a372a020 70
AnnaBridge 167:84c0a372a020 71 #define __CORTEX_SC (000U) /*!< Cortex secure core */
AnnaBridge 167:84c0a372a020 72
AnnaBridge 167:84c0a372a020 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 167:84c0a372a020 74 This core does not support an FPU at all
AnnaBridge 167:84c0a372a020 75 */
AnnaBridge 167:84c0a372a020 76 #define __FPU_USED 0U
AnnaBridge 167:84c0a372a020 77
AnnaBridge 167:84c0a372a020 78 #if defined ( __CC_ARM )
AnnaBridge 167:84c0a372a020 79 #if defined __TARGET_FPU_VFP
AnnaBridge 167:84c0a372a020 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 81 #endif
AnnaBridge 167:84c0a372a020 82
AnnaBridge 167:84c0a372a020 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 167:84c0a372a020 84 #if defined __ARM_PCS_VFP
AnnaBridge 167:84c0a372a020 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 86 #endif
AnnaBridge 167:84c0a372a020 87
AnnaBridge 167:84c0a372a020 88 #elif defined ( __GNUC__ )
AnnaBridge 167:84c0a372a020 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 167:84c0a372a020 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 91 #endif
AnnaBridge 167:84c0a372a020 92
AnnaBridge 167:84c0a372a020 93 #elif defined ( __ICCARM__ )
AnnaBridge 167:84c0a372a020 94 #if defined __ARMVFP__
AnnaBridge 167:84c0a372a020 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 96 #endif
AnnaBridge 167:84c0a372a020 97
AnnaBridge 167:84c0a372a020 98 #elif defined ( __TI_ARM__ )
AnnaBridge 167:84c0a372a020 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 167:84c0a372a020 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 101 #endif
AnnaBridge 167:84c0a372a020 102
AnnaBridge 167:84c0a372a020 103 #elif defined ( __TASKING__ )
AnnaBridge 167:84c0a372a020 104 #if defined __FPU_VFP__
AnnaBridge 167:84c0a372a020 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 106 #endif
AnnaBridge 167:84c0a372a020 107
AnnaBridge 167:84c0a372a020 108 #elif defined ( __CSMC__ )
AnnaBridge 167:84c0a372a020 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 167:84c0a372a020 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:84c0a372a020 111 #endif
AnnaBridge 167:84c0a372a020 112
AnnaBridge 167:84c0a372a020 113 #endif
AnnaBridge 167:84c0a372a020 114
AnnaBridge 167:84c0a372a020 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 167:84c0a372a020 116
AnnaBridge 167:84c0a372a020 117
AnnaBridge 167:84c0a372a020 118 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 119 }
AnnaBridge 167:84c0a372a020 120 #endif
AnnaBridge 167:84c0a372a020 121
AnnaBridge 167:84c0a372a020 122 #endif /* __CORE_SC000_H_GENERIC */
AnnaBridge 167:84c0a372a020 123
AnnaBridge 167:84c0a372a020 124 #ifndef __CMSIS_GENERIC
AnnaBridge 167:84c0a372a020 125
AnnaBridge 167:84c0a372a020 126 #ifndef __CORE_SC000_H_DEPENDANT
AnnaBridge 167:84c0a372a020 127 #define __CORE_SC000_H_DEPENDANT
AnnaBridge 167:84c0a372a020 128
AnnaBridge 167:84c0a372a020 129 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 130 extern "C" {
AnnaBridge 167:84c0a372a020 131 #endif
AnnaBridge 167:84c0a372a020 132
AnnaBridge 167:84c0a372a020 133 /* check device defines and use defaults */
AnnaBridge 167:84c0a372a020 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 167:84c0a372a020 135 #ifndef __SC000_REV
AnnaBridge 167:84c0a372a020 136 #define __SC000_REV 0x0000U
AnnaBridge 167:84c0a372a020 137 #warning "__SC000_REV not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 138 #endif
AnnaBridge 167:84c0a372a020 139
AnnaBridge 167:84c0a372a020 140 #ifndef __MPU_PRESENT
AnnaBridge 167:84c0a372a020 141 #define __MPU_PRESENT 0U
AnnaBridge 167:84c0a372a020 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 143 #endif
AnnaBridge 167:84c0a372a020 144
AnnaBridge 167:84c0a372a020 145 #ifndef __NVIC_PRIO_BITS
AnnaBridge 167:84c0a372a020 146 #define __NVIC_PRIO_BITS 2U
AnnaBridge 167:84c0a372a020 147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 148 #endif
AnnaBridge 167:84c0a372a020 149
AnnaBridge 167:84c0a372a020 150 #ifndef __Vendor_SysTickConfig
AnnaBridge 167:84c0a372a020 151 #define __Vendor_SysTickConfig 0U
AnnaBridge 167:84c0a372a020 152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 167:84c0a372a020 153 #endif
AnnaBridge 167:84c0a372a020 154 #endif
AnnaBridge 167:84c0a372a020 155
AnnaBridge 167:84c0a372a020 156 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 167:84c0a372a020 157 /**
AnnaBridge 167:84c0a372a020 158 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 167:84c0a372a020 159
AnnaBridge 167:84c0a372a020 160 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 167:84c0a372a020 161 \li to specify the access to peripheral variables.
AnnaBridge 167:84c0a372a020 162 \li for automatic generation of peripheral register debug information.
AnnaBridge 167:84c0a372a020 163 */
AnnaBridge 167:84c0a372a020 164 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 165 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 167:84c0a372a020 166 #else
AnnaBridge 167:84c0a372a020 167 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 167:84c0a372a020 168 #endif
AnnaBridge 167:84c0a372a020 169 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 167:84c0a372a020 170 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 167:84c0a372a020 171
AnnaBridge 167:84c0a372a020 172 /* following defines should be used for structure members */
AnnaBridge 167:84c0a372a020 173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 167:84c0a372a020 174 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 167:84c0a372a020 175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 167:84c0a372a020 176
AnnaBridge 167:84c0a372a020 177 /*@} end of group SC000 */
AnnaBridge 167:84c0a372a020 178
AnnaBridge 167:84c0a372a020 179
AnnaBridge 167:84c0a372a020 180
AnnaBridge 167:84c0a372a020 181 /*******************************************************************************
AnnaBridge 167:84c0a372a020 182 * Register Abstraction
AnnaBridge 167:84c0a372a020 183 Core Register contain:
AnnaBridge 167:84c0a372a020 184 - Core Register
AnnaBridge 167:84c0a372a020 185 - Core NVIC Register
AnnaBridge 167:84c0a372a020 186 - Core SCB Register
AnnaBridge 167:84c0a372a020 187 - Core SysTick Register
AnnaBridge 167:84c0a372a020 188 - Core MPU Register
AnnaBridge 167:84c0a372a020 189 ******************************************************************************/
AnnaBridge 167:84c0a372a020 190 /**
AnnaBridge 167:84c0a372a020 191 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 167:84c0a372a020 192 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 167:84c0a372a020 193 */
AnnaBridge 167:84c0a372a020 194
AnnaBridge 167:84c0a372a020 195 /**
AnnaBridge 167:84c0a372a020 196 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 197 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 167:84c0a372a020 198 \brief Core Register type definitions.
AnnaBridge 167:84c0a372a020 199 @{
AnnaBridge 167:84c0a372a020 200 */
AnnaBridge 167:84c0a372a020 201
AnnaBridge 167:84c0a372a020 202 /**
AnnaBridge 167:84c0a372a020 203 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 167:84c0a372a020 204 */
AnnaBridge 167:84c0a372a020 205 typedef union
AnnaBridge 167:84c0a372a020 206 {
AnnaBridge 167:84c0a372a020 207 struct
AnnaBridge 167:84c0a372a020 208 {
AnnaBridge 167:84c0a372a020 209 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 167:84c0a372a020 210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:84c0a372a020 211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:84c0a372a020 212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:84c0a372a020 213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:84c0a372a020 214 } b; /*!< Structure used for bit access */
AnnaBridge 167:84c0a372a020 215 uint32_t w; /*!< Type used for word access */
AnnaBridge 167:84c0a372a020 216 } APSR_Type;
AnnaBridge 167:84c0a372a020 217
AnnaBridge 167:84c0a372a020 218 /* APSR Register Definitions */
AnnaBridge 167:84c0a372a020 219 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 167:84c0a372a020 220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 167:84c0a372a020 221
AnnaBridge 167:84c0a372a020 222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 167:84c0a372a020 223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 167:84c0a372a020 224
AnnaBridge 167:84c0a372a020 225 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 167:84c0a372a020 226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 167:84c0a372a020 227
AnnaBridge 167:84c0a372a020 228 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 167:84c0a372a020 229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 167:84c0a372a020 230
AnnaBridge 167:84c0a372a020 231
AnnaBridge 167:84c0a372a020 232 /**
AnnaBridge 167:84c0a372a020 233 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 167:84c0a372a020 234 */
AnnaBridge 167:84c0a372a020 235 typedef union
AnnaBridge 167:84c0a372a020 236 {
AnnaBridge 167:84c0a372a020 237 struct
AnnaBridge 167:84c0a372a020 238 {
AnnaBridge 167:84c0a372a020 239 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:84c0a372a020 240 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 167:84c0a372a020 241 } b; /*!< Structure used for bit access */
AnnaBridge 167:84c0a372a020 242 uint32_t w; /*!< Type used for word access */
AnnaBridge 167:84c0a372a020 243 } IPSR_Type;
AnnaBridge 167:84c0a372a020 244
AnnaBridge 167:84c0a372a020 245 /* IPSR Register Definitions */
AnnaBridge 167:84c0a372a020 246 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 167:84c0a372a020 247 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 167:84c0a372a020 248
AnnaBridge 167:84c0a372a020 249
AnnaBridge 167:84c0a372a020 250 /**
AnnaBridge 167:84c0a372a020 251 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 167:84c0a372a020 252 */
AnnaBridge 167:84c0a372a020 253 typedef union
AnnaBridge 167:84c0a372a020 254 {
AnnaBridge 167:84c0a372a020 255 struct
AnnaBridge 167:84c0a372a020 256 {
AnnaBridge 167:84c0a372a020 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:84c0a372a020 258 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 167:84c0a372a020 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 167:84c0a372a020 260 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 167:84c0a372a020 261 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:84c0a372a020 262 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:84c0a372a020 263 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:84c0a372a020 264 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:84c0a372a020 265 } b; /*!< Structure used for bit access */
AnnaBridge 167:84c0a372a020 266 uint32_t w; /*!< Type used for word access */
AnnaBridge 167:84c0a372a020 267 } xPSR_Type;
AnnaBridge 167:84c0a372a020 268
AnnaBridge 167:84c0a372a020 269 /* xPSR Register Definitions */
AnnaBridge 167:84c0a372a020 270 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 167:84c0a372a020 271 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 167:84c0a372a020 272
AnnaBridge 167:84c0a372a020 273 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 167:84c0a372a020 274 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 167:84c0a372a020 275
AnnaBridge 167:84c0a372a020 276 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 167:84c0a372a020 277 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 167:84c0a372a020 278
AnnaBridge 167:84c0a372a020 279 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 167:84c0a372a020 280 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 167:84c0a372a020 281
AnnaBridge 167:84c0a372a020 282 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 167:84c0a372a020 283 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 167:84c0a372a020 284
AnnaBridge 167:84c0a372a020 285 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 167:84c0a372a020 286 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 167:84c0a372a020 287
AnnaBridge 167:84c0a372a020 288
AnnaBridge 167:84c0a372a020 289 /**
AnnaBridge 167:84c0a372a020 290 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 167:84c0a372a020 291 */
AnnaBridge 167:84c0a372a020 292 typedef union
AnnaBridge 167:84c0a372a020 293 {
AnnaBridge 167:84c0a372a020 294 struct
AnnaBridge 167:84c0a372a020 295 {
AnnaBridge 167:84c0a372a020 296 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 167:84c0a372a020 297 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 167:84c0a372a020 298 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 167:84c0a372a020 299 } b; /*!< Structure used for bit access */
AnnaBridge 167:84c0a372a020 300 uint32_t w; /*!< Type used for word access */
AnnaBridge 167:84c0a372a020 301 } CONTROL_Type;
AnnaBridge 167:84c0a372a020 302
AnnaBridge 167:84c0a372a020 303 /* CONTROL Register Definitions */
AnnaBridge 167:84c0a372a020 304 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 167:84c0a372a020 305 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 167:84c0a372a020 306
AnnaBridge 167:84c0a372a020 307 /*@} end of group CMSIS_CORE */
AnnaBridge 167:84c0a372a020 308
AnnaBridge 167:84c0a372a020 309
AnnaBridge 167:84c0a372a020 310 /**
AnnaBridge 167:84c0a372a020 311 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 312 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 167:84c0a372a020 313 \brief Type definitions for the NVIC Registers
AnnaBridge 167:84c0a372a020 314 @{
AnnaBridge 167:84c0a372a020 315 */
AnnaBridge 167:84c0a372a020 316
AnnaBridge 167:84c0a372a020 317 /**
AnnaBridge 167:84c0a372a020 318 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 167:84c0a372a020 319 */
AnnaBridge 167:84c0a372a020 320 typedef struct
AnnaBridge 167:84c0a372a020 321 {
AnnaBridge 167:84c0a372a020 322 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 167:84c0a372a020 323 uint32_t RESERVED0[31U];
AnnaBridge 167:84c0a372a020 324 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 167:84c0a372a020 325 uint32_t RSERVED1[31U];
AnnaBridge 167:84c0a372a020 326 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 167:84c0a372a020 327 uint32_t RESERVED2[31U];
AnnaBridge 167:84c0a372a020 328 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 167:84c0a372a020 329 uint32_t RESERVED3[31U];
AnnaBridge 167:84c0a372a020 330 uint32_t RESERVED4[64U];
AnnaBridge 167:84c0a372a020 331 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 167:84c0a372a020 332 } NVIC_Type;
AnnaBridge 167:84c0a372a020 333
AnnaBridge 167:84c0a372a020 334 /*@} end of group CMSIS_NVIC */
AnnaBridge 167:84c0a372a020 335
AnnaBridge 167:84c0a372a020 336
AnnaBridge 167:84c0a372a020 337 /**
AnnaBridge 167:84c0a372a020 338 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 339 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 167:84c0a372a020 340 \brief Type definitions for the System Control Block Registers
AnnaBridge 167:84c0a372a020 341 @{
AnnaBridge 167:84c0a372a020 342 */
AnnaBridge 167:84c0a372a020 343
AnnaBridge 167:84c0a372a020 344 /**
AnnaBridge 167:84c0a372a020 345 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 167:84c0a372a020 346 */
AnnaBridge 167:84c0a372a020 347 typedef struct
AnnaBridge 167:84c0a372a020 348 {
AnnaBridge 167:84c0a372a020 349 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 167:84c0a372a020 350 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 167:84c0a372a020 351 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 167:84c0a372a020 352 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 167:84c0a372a020 353 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 167:84c0a372a020 354 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 167:84c0a372a020 355 uint32_t RESERVED0[1U];
AnnaBridge 167:84c0a372a020 356 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 167:84c0a372a020 357 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 167:84c0a372a020 358 uint32_t RESERVED1[154U];
AnnaBridge 167:84c0a372a020 359 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
AnnaBridge 167:84c0a372a020 360 } SCB_Type;
AnnaBridge 167:84c0a372a020 361
AnnaBridge 167:84c0a372a020 362 /* SCB CPUID Register Definitions */
AnnaBridge 167:84c0a372a020 363 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 167:84c0a372a020 364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 167:84c0a372a020 365
AnnaBridge 167:84c0a372a020 366 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 167:84c0a372a020 367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 167:84c0a372a020 368
AnnaBridge 167:84c0a372a020 369 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 167:84c0a372a020 370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 167:84c0a372a020 371
AnnaBridge 167:84c0a372a020 372 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 167:84c0a372a020 373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 167:84c0a372a020 374
AnnaBridge 167:84c0a372a020 375 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 167:84c0a372a020 376 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 167:84c0a372a020 377
AnnaBridge 167:84c0a372a020 378 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 167:84c0a372a020 379 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 167:84c0a372a020 380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 167:84c0a372a020 381
AnnaBridge 167:84c0a372a020 382 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 167:84c0a372a020 383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 167:84c0a372a020 384
AnnaBridge 167:84c0a372a020 385 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 167:84c0a372a020 386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 167:84c0a372a020 387
AnnaBridge 167:84c0a372a020 388 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 167:84c0a372a020 389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 167:84c0a372a020 390
AnnaBridge 167:84c0a372a020 391 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 167:84c0a372a020 392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 167:84c0a372a020 393
AnnaBridge 167:84c0a372a020 394 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 167:84c0a372a020 395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 167:84c0a372a020 396
AnnaBridge 167:84c0a372a020 397 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 167:84c0a372a020 398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 167:84c0a372a020 399
AnnaBridge 167:84c0a372a020 400 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 167:84c0a372a020 401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 167:84c0a372a020 402
AnnaBridge 167:84c0a372a020 403 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 167:84c0a372a020 404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 167:84c0a372a020 405
AnnaBridge 167:84c0a372a020 406 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 167:84c0a372a020 407 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 167:84c0a372a020 408 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 167:84c0a372a020 409
AnnaBridge 167:84c0a372a020 410 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 167:84c0a372a020 411 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 167:84c0a372a020 412 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 167:84c0a372a020 413
AnnaBridge 167:84c0a372a020 414 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 167:84c0a372a020 415 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 167:84c0a372a020 416
AnnaBridge 167:84c0a372a020 417 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 167:84c0a372a020 418 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 167:84c0a372a020 419
AnnaBridge 167:84c0a372a020 420 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 167:84c0a372a020 421 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 167:84c0a372a020 422
AnnaBridge 167:84c0a372a020 423 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 167:84c0a372a020 424 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 167:84c0a372a020 425
AnnaBridge 167:84c0a372a020 426 /* SCB System Control Register Definitions */
AnnaBridge 167:84c0a372a020 427 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 167:84c0a372a020 428 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 167:84c0a372a020 429
AnnaBridge 167:84c0a372a020 430 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 167:84c0a372a020 431 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 167:84c0a372a020 432
AnnaBridge 167:84c0a372a020 433 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 167:84c0a372a020 434 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 167:84c0a372a020 435
AnnaBridge 167:84c0a372a020 436 /* SCB Configuration Control Register Definitions */
AnnaBridge 167:84c0a372a020 437 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 167:84c0a372a020 438 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 167:84c0a372a020 439
AnnaBridge 167:84c0a372a020 440 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 167:84c0a372a020 441 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 167:84c0a372a020 442
AnnaBridge 167:84c0a372a020 443 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 167:84c0a372a020 444 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 167:84c0a372a020 445 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 167:84c0a372a020 446
AnnaBridge 167:84c0a372a020 447 /*@} end of group CMSIS_SCB */
AnnaBridge 167:84c0a372a020 448
AnnaBridge 167:84c0a372a020 449
AnnaBridge 167:84c0a372a020 450 /**
AnnaBridge 167:84c0a372a020 451 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 452 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 167:84c0a372a020 453 \brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge 167:84c0a372a020 454 @{
AnnaBridge 167:84c0a372a020 455 */
AnnaBridge 167:84c0a372a020 456
AnnaBridge 167:84c0a372a020 457 /**
AnnaBridge 167:84c0a372a020 458 \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge 167:84c0a372a020 459 */
AnnaBridge 167:84c0a372a020 460 typedef struct
AnnaBridge 167:84c0a372a020 461 {
AnnaBridge 167:84c0a372a020 462 uint32_t RESERVED0[2U];
AnnaBridge 167:84c0a372a020 463 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
AnnaBridge 167:84c0a372a020 464 } SCnSCB_Type;
AnnaBridge 167:84c0a372a020 465
AnnaBridge 167:84c0a372a020 466 /* Auxiliary Control Register Definitions */
AnnaBridge 167:84c0a372a020 467 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
AnnaBridge 167:84c0a372a020 468 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
AnnaBridge 167:84c0a372a020 469
AnnaBridge 167:84c0a372a020 470 /*@} end of group CMSIS_SCnotSCB */
AnnaBridge 167:84c0a372a020 471
AnnaBridge 167:84c0a372a020 472
AnnaBridge 167:84c0a372a020 473 /**
AnnaBridge 167:84c0a372a020 474 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 475 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 167:84c0a372a020 476 \brief Type definitions for the System Timer Registers.
AnnaBridge 167:84c0a372a020 477 @{
AnnaBridge 167:84c0a372a020 478 */
AnnaBridge 167:84c0a372a020 479
AnnaBridge 167:84c0a372a020 480 /**
AnnaBridge 167:84c0a372a020 481 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 167:84c0a372a020 482 */
AnnaBridge 167:84c0a372a020 483 typedef struct
AnnaBridge 167:84c0a372a020 484 {
AnnaBridge 167:84c0a372a020 485 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 167:84c0a372a020 486 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 167:84c0a372a020 487 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 167:84c0a372a020 488 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 167:84c0a372a020 489 } SysTick_Type;
AnnaBridge 167:84c0a372a020 490
AnnaBridge 167:84c0a372a020 491 /* SysTick Control / Status Register Definitions */
AnnaBridge 167:84c0a372a020 492 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 167:84c0a372a020 493 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 167:84c0a372a020 494
AnnaBridge 167:84c0a372a020 495 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 167:84c0a372a020 496 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 167:84c0a372a020 497
AnnaBridge 167:84c0a372a020 498 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 167:84c0a372a020 499 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 167:84c0a372a020 500
AnnaBridge 167:84c0a372a020 501 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 167:84c0a372a020 502 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 167:84c0a372a020 503
AnnaBridge 167:84c0a372a020 504 /* SysTick Reload Register Definitions */
AnnaBridge 167:84c0a372a020 505 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 167:84c0a372a020 506 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 167:84c0a372a020 507
AnnaBridge 167:84c0a372a020 508 /* SysTick Current Register Definitions */
AnnaBridge 167:84c0a372a020 509 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 167:84c0a372a020 510 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 167:84c0a372a020 511
AnnaBridge 167:84c0a372a020 512 /* SysTick Calibration Register Definitions */
AnnaBridge 167:84c0a372a020 513 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 167:84c0a372a020 514 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 167:84c0a372a020 515
AnnaBridge 167:84c0a372a020 516 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 167:84c0a372a020 517 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 167:84c0a372a020 518
AnnaBridge 167:84c0a372a020 519 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 167:84c0a372a020 520 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 167:84c0a372a020 521
AnnaBridge 167:84c0a372a020 522 /*@} end of group CMSIS_SysTick */
AnnaBridge 167:84c0a372a020 523
AnnaBridge 167:84c0a372a020 524 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 167:84c0a372a020 525 /**
AnnaBridge 167:84c0a372a020 526 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 527 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 167:84c0a372a020 528 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 167:84c0a372a020 529 @{
AnnaBridge 167:84c0a372a020 530 */
AnnaBridge 167:84c0a372a020 531
AnnaBridge 167:84c0a372a020 532 /**
AnnaBridge 167:84c0a372a020 533 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 167:84c0a372a020 534 */
AnnaBridge 167:84c0a372a020 535 typedef struct
AnnaBridge 167:84c0a372a020 536 {
AnnaBridge 167:84c0a372a020 537 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 167:84c0a372a020 538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 167:84c0a372a020 539 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 167:84c0a372a020 540 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 167:84c0a372a020 541 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 167:84c0a372a020 542 } MPU_Type;
AnnaBridge 167:84c0a372a020 543
AnnaBridge 167:84c0a372a020 544 /* MPU Type Register Definitions */
AnnaBridge 167:84c0a372a020 545 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 167:84c0a372a020 546 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 167:84c0a372a020 547
AnnaBridge 167:84c0a372a020 548 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 167:84c0a372a020 549 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 167:84c0a372a020 550
AnnaBridge 167:84c0a372a020 551 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 167:84c0a372a020 552 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 167:84c0a372a020 553
AnnaBridge 167:84c0a372a020 554 /* MPU Control Register Definitions */
AnnaBridge 167:84c0a372a020 555 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 167:84c0a372a020 556 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 167:84c0a372a020 557
AnnaBridge 167:84c0a372a020 558 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 167:84c0a372a020 559 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 167:84c0a372a020 560
AnnaBridge 167:84c0a372a020 561 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 167:84c0a372a020 562 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 167:84c0a372a020 563
AnnaBridge 167:84c0a372a020 564 /* MPU Region Number Register Definitions */
AnnaBridge 167:84c0a372a020 565 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 167:84c0a372a020 566 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 167:84c0a372a020 567
AnnaBridge 167:84c0a372a020 568 /* MPU Region Base Address Register Definitions */
AnnaBridge 167:84c0a372a020 569 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
AnnaBridge 167:84c0a372a020 570 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 167:84c0a372a020 571
AnnaBridge 167:84c0a372a020 572 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
AnnaBridge 167:84c0a372a020 573 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 167:84c0a372a020 574
AnnaBridge 167:84c0a372a020 575 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
AnnaBridge 167:84c0a372a020 576 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 167:84c0a372a020 577
AnnaBridge 167:84c0a372a020 578 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 167:84c0a372a020 579 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 167:84c0a372a020 580 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 167:84c0a372a020 581
AnnaBridge 167:84c0a372a020 582 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 167:84c0a372a020 583 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 167:84c0a372a020 584
AnnaBridge 167:84c0a372a020 585 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 167:84c0a372a020 586 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 167:84c0a372a020 587
AnnaBridge 167:84c0a372a020 588 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 167:84c0a372a020 589 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 167:84c0a372a020 590
AnnaBridge 167:84c0a372a020 591 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 167:84c0a372a020 592 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 167:84c0a372a020 593
AnnaBridge 167:84c0a372a020 594 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 167:84c0a372a020 595 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 167:84c0a372a020 596
AnnaBridge 167:84c0a372a020 597 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 167:84c0a372a020 598 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 167:84c0a372a020 599
AnnaBridge 167:84c0a372a020 600 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 167:84c0a372a020 601 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 167:84c0a372a020 602
AnnaBridge 167:84c0a372a020 603 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
AnnaBridge 167:84c0a372a020 604 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 167:84c0a372a020 605
AnnaBridge 167:84c0a372a020 606 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
AnnaBridge 167:84c0a372a020 607 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 167:84c0a372a020 608
AnnaBridge 167:84c0a372a020 609 /*@} end of group CMSIS_MPU */
AnnaBridge 167:84c0a372a020 610 #endif
AnnaBridge 167:84c0a372a020 611
AnnaBridge 167:84c0a372a020 612
AnnaBridge 167:84c0a372a020 613 /**
AnnaBridge 167:84c0a372a020 614 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 615 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 167:84c0a372a020 616 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 167:84c0a372a020 617 Therefore they are not covered by the SC000 header file.
AnnaBridge 167:84c0a372a020 618 @{
AnnaBridge 167:84c0a372a020 619 */
AnnaBridge 167:84c0a372a020 620 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 167:84c0a372a020 621
AnnaBridge 167:84c0a372a020 622
AnnaBridge 167:84c0a372a020 623 /**
AnnaBridge 167:84c0a372a020 624 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 625 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 167:84c0a372a020 626 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 167:84c0a372a020 627 @{
AnnaBridge 167:84c0a372a020 628 */
AnnaBridge 167:84c0a372a020 629
AnnaBridge 167:84c0a372a020 630 /**
AnnaBridge 167:84c0a372a020 631 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 167:84c0a372a020 632 \param[in] field Name of the register bit field.
AnnaBridge 167:84c0a372a020 633 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:84c0a372a020 634 \return Masked and shifted value.
AnnaBridge 167:84c0a372a020 635 */
AnnaBridge 167:84c0a372a020 636 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 167:84c0a372a020 637
AnnaBridge 167:84c0a372a020 638 /**
AnnaBridge 167:84c0a372a020 639 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 167:84c0a372a020 640 \param[in] field Name of the register bit field.
AnnaBridge 167:84c0a372a020 641 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:84c0a372a020 642 \return Masked and shifted bit field value.
AnnaBridge 167:84c0a372a020 643 */
AnnaBridge 167:84c0a372a020 644 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 167:84c0a372a020 645
AnnaBridge 167:84c0a372a020 646 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 167:84c0a372a020 647
AnnaBridge 167:84c0a372a020 648
AnnaBridge 167:84c0a372a020 649 /**
AnnaBridge 167:84c0a372a020 650 \ingroup CMSIS_core_register
AnnaBridge 167:84c0a372a020 651 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 167:84c0a372a020 652 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 167:84c0a372a020 653 @{
AnnaBridge 167:84c0a372a020 654 */
AnnaBridge 167:84c0a372a020 655
AnnaBridge 167:84c0a372a020 656 /* Memory mapping of Core Hardware */
AnnaBridge 167:84c0a372a020 657 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 167:84c0a372a020 658 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 167:84c0a372a020 659 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 167:84c0a372a020 660 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 167:84c0a372a020 661
AnnaBridge 167:84c0a372a020 662 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 167:84c0a372a020 663 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 167:84c0a372a020 664 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 167:84c0a372a020 665 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 167:84c0a372a020 666
AnnaBridge 167:84c0a372a020 667 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 167:84c0a372a020 668 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 167:84c0a372a020 669 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 167:84c0a372a020 670 #endif
AnnaBridge 167:84c0a372a020 671
AnnaBridge 167:84c0a372a020 672 /*@} */
AnnaBridge 167:84c0a372a020 673
AnnaBridge 167:84c0a372a020 674
AnnaBridge 167:84c0a372a020 675
AnnaBridge 167:84c0a372a020 676 /*******************************************************************************
AnnaBridge 167:84c0a372a020 677 * Hardware Abstraction Layer
AnnaBridge 167:84c0a372a020 678 Core Function Interface contains:
AnnaBridge 167:84c0a372a020 679 - Core NVIC Functions
AnnaBridge 167:84c0a372a020 680 - Core SysTick Functions
AnnaBridge 167:84c0a372a020 681 - Core Register Access Functions
AnnaBridge 167:84c0a372a020 682 ******************************************************************************/
AnnaBridge 167:84c0a372a020 683 /**
AnnaBridge 167:84c0a372a020 684 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 167:84c0a372a020 685 */
AnnaBridge 167:84c0a372a020 686
AnnaBridge 167:84c0a372a020 687
AnnaBridge 167:84c0a372a020 688
AnnaBridge 167:84c0a372a020 689 /* ########################## NVIC functions #################################### */
AnnaBridge 167:84c0a372a020 690 /**
AnnaBridge 167:84c0a372a020 691 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:84c0a372a020 692 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 167:84c0a372a020 693 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 167:84c0a372a020 694 @{
AnnaBridge 167:84c0a372a020 695 */
AnnaBridge 167:84c0a372a020 696
AnnaBridge 167:84c0a372a020 697 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 167:84c0a372a020 698 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 167:84c0a372a020 699 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 167:84c0a372a020 700 #endif
AnnaBridge 167:84c0a372a020 701 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 167:84c0a372a020 702 #else
AnnaBridge 167:84c0a372a020 703 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
AnnaBridge 167:84c0a372a020 704 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
AnnaBridge 167:84c0a372a020 705 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 167:84c0a372a020 706 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 167:84c0a372a020 707 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 167:84c0a372a020 708 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 167:84c0a372a020 709 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 167:84c0a372a020 710 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 167:84c0a372a020 711 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
AnnaBridge 167:84c0a372a020 712 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 167:84c0a372a020 713 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 167:84c0a372a020 714 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 167:84c0a372a020 715 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 167:84c0a372a020 716
AnnaBridge 167:84c0a372a020 717 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 167:84c0a372a020 718 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 167:84c0a372a020 719 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 167:84c0a372a020 720 #endif
AnnaBridge 167:84c0a372a020 721 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 167:84c0a372a020 722 #else
AnnaBridge 167:84c0a372a020 723 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 167:84c0a372a020 724 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 167:84c0a372a020 725 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 167:84c0a372a020 726
AnnaBridge 167:84c0a372a020 727 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 167:84c0a372a020 728
AnnaBridge 167:84c0a372a020 729
Anna Bridge 169:a7c7b631e539 730 /* Interrupt Priorities are WORD accessible only under Armv6-M */
AnnaBridge 167:84c0a372a020 731 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 167:84c0a372a020 732 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 167:84c0a372a020 733 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 167:84c0a372a020 734 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 167:84c0a372a020 735
AnnaBridge 167:84c0a372a020 736
AnnaBridge 167:84c0a372a020 737 /**
AnnaBridge 167:84c0a372a020 738 \brief Enable Interrupt
AnnaBridge 167:84c0a372a020 739 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:84c0a372a020 740 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 741 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 742 */
AnnaBridge 167:84c0a372a020 743 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 744 {
AnnaBridge 167:84c0a372a020 745 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 746 {
Anna Bridge 169:a7c7b631e539 747 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 748 }
AnnaBridge 167:84c0a372a020 749 }
AnnaBridge 167:84c0a372a020 750
AnnaBridge 167:84c0a372a020 751
AnnaBridge 167:84c0a372a020 752 /**
AnnaBridge 167:84c0a372a020 753 \brief Get Interrupt Enable status
AnnaBridge 167:84c0a372a020 754 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 167:84c0a372a020 755 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 756 \return 0 Interrupt is not enabled.
AnnaBridge 167:84c0a372a020 757 \return 1 Interrupt is enabled.
AnnaBridge 167:84c0a372a020 758 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 759 */
AnnaBridge 167:84c0a372a020 760 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 761 {
AnnaBridge 167:84c0a372a020 762 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 763 {
Anna Bridge 169:a7c7b631e539 764 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 765 }
AnnaBridge 167:84c0a372a020 766 else
AnnaBridge 167:84c0a372a020 767 {
AnnaBridge 167:84c0a372a020 768 return(0U);
AnnaBridge 167:84c0a372a020 769 }
AnnaBridge 167:84c0a372a020 770 }
AnnaBridge 167:84c0a372a020 771
AnnaBridge 167:84c0a372a020 772
AnnaBridge 167:84c0a372a020 773 /**
AnnaBridge 167:84c0a372a020 774 \brief Disable Interrupt
AnnaBridge 167:84c0a372a020 775 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:84c0a372a020 776 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 777 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 778 */
AnnaBridge 167:84c0a372a020 779 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 780 {
AnnaBridge 167:84c0a372a020 781 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 782 {
Anna Bridge 169:a7c7b631e539 783 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 784 __DSB();
AnnaBridge 167:84c0a372a020 785 __ISB();
AnnaBridge 167:84c0a372a020 786 }
AnnaBridge 167:84c0a372a020 787 }
AnnaBridge 167:84c0a372a020 788
AnnaBridge 167:84c0a372a020 789
AnnaBridge 167:84c0a372a020 790 /**
AnnaBridge 167:84c0a372a020 791 \brief Get Pending Interrupt
AnnaBridge 167:84c0a372a020 792 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 167:84c0a372a020 793 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 794 \return 0 Interrupt status is not pending.
AnnaBridge 167:84c0a372a020 795 \return 1 Interrupt status is pending.
AnnaBridge 167:84c0a372a020 796 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 797 */
AnnaBridge 167:84c0a372a020 798 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 799 {
AnnaBridge 167:84c0a372a020 800 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 801 {
Anna Bridge 169:a7c7b631e539 802 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:84c0a372a020 803 }
AnnaBridge 167:84c0a372a020 804 else
AnnaBridge 167:84c0a372a020 805 {
AnnaBridge 167:84c0a372a020 806 return(0U);
AnnaBridge 167:84c0a372a020 807 }
AnnaBridge 167:84c0a372a020 808 }
AnnaBridge 167:84c0a372a020 809
AnnaBridge 167:84c0a372a020 810
AnnaBridge 167:84c0a372a020 811 /**
AnnaBridge 167:84c0a372a020 812 \brief Set Pending Interrupt
AnnaBridge 167:84c0a372a020 813 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:84c0a372a020 814 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 815 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 816 */
AnnaBridge 167:84c0a372a020 817 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 818 {
AnnaBridge 167:84c0a372a020 819 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 820 {
Anna Bridge 169:a7c7b631e539 821 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 822 }
AnnaBridge 167:84c0a372a020 823 }
AnnaBridge 167:84c0a372a020 824
AnnaBridge 167:84c0a372a020 825
AnnaBridge 167:84c0a372a020 826 /**
AnnaBridge 167:84c0a372a020 827 \brief Clear Pending Interrupt
AnnaBridge 167:84c0a372a020 828 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:84c0a372a020 829 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:84c0a372a020 830 \note IRQn must not be negative.
AnnaBridge 167:84c0a372a020 831 */
AnnaBridge 167:84c0a372a020 832 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 833 {
AnnaBridge 167:84c0a372a020 834 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 835 {
Anna Bridge 169:a7c7b631e539 836 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 167:84c0a372a020 837 }
AnnaBridge 167:84c0a372a020 838 }
AnnaBridge 167:84c0a372a020 839
AnnaBridge 167:84c0a372a020 840
AnnaBridge 167:84c0a372a020 841 /**
AnnaBridge 167:84c0a372a020 842 \brief Set Interrupt Priority
AnnaBridge 167:84c0a372a020 843 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:84c0a372a020 844 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 845 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 846 \param [in] IRQn Interrupt number.
AnnaBridge 167:84c0a372a020 847 \param [in] priority Priority to set.
AnnaBridge 167:84c0a372a020 848 \note The priority cannot be set for every processor exception.
AnnaBridge 167:84c0a372a020 849 */
AnnaBridge 167:84c0a372a020 850 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 167:84c0a372a020 851 {
AnnaBridge 167:84c0a372a020 852 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 853 {
AnnaBridge 167:84c0a372a020 854 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 167:84c0a372a020 855 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 167:84c0a372a020 856 }
AnnaBridge 167:84c0a372a020 857 else
AnnaBridge 167:84c0a372a020 858 {
AnnaBridge 167:84c0a372a020 859 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 167:84c0a372a020 860 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 167:84c0a372a020 861 }
AnnaBridge 167:84c0a372a020 862 }
AnnaBridge 167:84c0a372a020 863
AnnaBridge 167:84c0a372a020 864
AnnaBridge 167:84c0a372a020 865 /**
AnnaBridge 167:84c0a372a020 866 \brief Get Interrupt Priority
AnnaBridge 167:84c0a372a020 867 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:84c0a372a020 868 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 869 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 870 \param [in] IRQn Interrupt number.
AnnaBridge 167:84c0a372a020 871 \return Interrupt Priority.
AnnaBridge 167:84c0a372a020 872 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 167:84c0a372a020 873 */
AnnaBridge 167:84c0a372a020 874 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 875 {
AnnaBridge 167:84c0a372a020 876
AnnaBridge 167:84c0a372a020 877 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:84c0a372a020 878 {
AnnaBridge 167:84c0a372a020 879 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 167:84c0a372a020 880 }
AnnaBridge 167:84c0a372a020 881 else
AnnaBridge 167:84c0a372a020 882 {
AnnaBridge 167:84c0a372a020 883 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 167:84c0a372a020 884 }
AnnaBridge 167:84c0a372a020 885 }
AnnaBridge 167:84c0a372a020 886
AnnaBridge 167:84c0a372a020 887
AnnaBridge 167:84c0a372a020 888 /**
AnnaBridge 167:84c0a372a020 889 \brief Set Interrupt Vector
AnnaBridge 167:84c0a372a020 890 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 167:84c0a372a020 891 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 892 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 893 VTOR must been relocated to SRAM before.
AnnaBridge 167:84c0a372a020 894 \param [in] IRQn Interrupt number
AnnaBridge 167:84c0a372a020 895 \param [in] vector Address of interrupt handler function
AnnaBridge 167:84c0a372a020 896 */
AnnaBridge 167:84c0a372a020 897 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 167:84c0a372a020 898 {
AnnaBridge 167:84c0a372a020 899 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 167:84c0a372a020 900 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 167:84c0a372a020 901 }
AnnaBridge 167:84c0a372a020 902
AnnaBridge 167:84c0a372a020 903
AnnaBridge 167:84c0a372a020 904 /**
AnnaBridge 167:84c0a372a020 905 \brief Get Interrupt Vector
AnnaBridge 167:84c0a372a020 906 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 167:84c0a372a020 907 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:84c0a372a020 908 or negative to specify a processor exception.
AnnaBridge 167:84c0a372a020 909 \param [in] IRQn Interrupt number.
AnnaBridge 167:84c0a372a020 910 \return Address of interrupt handler function
AnnaBridge 167:84c0a372a020 911 */
AnnaBridge 167:84c0a372a020 912 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 167:84c0a372a020 913 {
AnnaBridge 167:84c0a372a020 914 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 167:84c0a372a020 915 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 167:84c0a372a020 916 }
AnnaBridge 167:84c0a372a020 917
AnnaBridge 167:84c0a372a020 918
AnnaBridge 167:84c0a372a020 919 /**
AnnaBridge 167:84c0a372a020 920 \brief System Reset
AnnaBridge 167:84c0a372a020 921 \details Initiates a system reset request to reset the MCU.
AnnaBridge 167:84c0a372a020 922 */
AnnaBridge 167:84c0a372a020 923 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 167:84c0a372a020 924 {
AnnaBridge 167:84c0a372a020 925 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 167:84c0a372a020 926 buffered write are completed before reset */
AnnaBridge 167:84c0a372a020 927 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 167:84c0a372a020 928 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 167:84c0a372a020 929 __DSB(); /* Ensure completion of memory access */
AnnaBridge 167:84c0a372a020 930
AnnaBridge 167:84c0a372a020 931 for(;;) /* wait until reset */
AnnaBridge 167:84c0a372a020 932 {
AnnaBridge 167:84c0a372a020 933 __NOP();
AnnaBridge 167:84c0a372a020 934 }
AnnaBridge 167:84c0a372a020 935 }
AnnaBridge 167:84c0a372a020 936
AnnaBridge 167:84c0a372a020 937 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 167:84c0a372a020 938
AnnaBridge 167:84c0a372a020 939
AnnaBridge 167:84c0a372a020 940 /* ########################## FPU functions #################################### */
AnnaBridge 167:84c0a372a020 941 /**
AnnaBridge 167:84c0a372a020 942 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:84c0a372a020 943 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 167:84c0a372a020 944 \brief Function that provides FPU type.
AnnaBridge 167:84c0a372a020 945 @{
AnnaBridge 167:84c0a372a020 946 */
AnnaBridge 167:84c0a372a020 947
AnnaBridge 167:84c0a372a020 948 /**
AnnaBridge 167:84c0a372a020 949 \brief get FPU type
AnnaBridge 167:84c0a372a020 950 \details returns the FPU type
AnnaBridge 167:84c0a372a020 951 \returns
AnnaBridge 167:84c0a372a020 952 - \b 0: No FPU
AnnaBridge 167:84c0a372a020 953 - \b 1: Single precision FPU
AnnaBridge 167:84c0a372a020 954 - \b 2: Double + Single precision FPU
AnnaBridge 167:84c0a372a020 955 */
AnnaBridge 167:84c0a372a020 956 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 167:84c0a372a020 957 {
AnnaBridge 167:84c0a372a020 958 return 0U; /* No FPU */
AnnaBridge 167:84c0a372a020 959 }
AnnaBridge 167:84c0a372a020 960
AnnaBridge 167:84c0a372a020 961
AnnaBridge 167:84c0a372a020 962 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 167:84c0a372a020 963
AnnaBridge 167:84c0a372a020 964
AnnaBridge 167:84c0a372a020 965
AnnaBridge 167:84c0a372a020 966 /* ################################## SysTick function ############################################ */
AnnaBridge 167:84c0a372a020 967 /**
AnnaBridge 167:84c0a372a020 968 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:84c0a372a020 969 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 167:84c0a372a020 970 \brief Functions that configure the System.
AnnaBridge 167:84c0a372a020 971 @{
AnnaBridge 167:84c0a372a020 972 */
AnnaBridge 167:84c0a372a020 973
AnnaBridge 167:84c0a372a020 974 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 167:84c0a372a020 975
AnnaBridge 167:84c0a372a020 976 /**
AnnaBridge 167:84c0a372a020 977 \brief System Tick Configuration
AnnaBridge 167:84c0a372a020 978 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 167:84c0a372a020 979 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 167:84c0a372a020 980 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 167:84c0a372a020 981 \return 0 Function succeeded.
AnnaBridge 167:84c0a372a020 982 \return 1 Function failed.
AnnaBridge 167:84c0a372a020 983 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 167:84c0a372a020 984 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 167:84c0a372a020 985 must contain a vendor-specific implementation of this function.
AnnaBridge 167:84c0a372a020 986 */
AnnaBridge 167:84c0a372a020 987 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 167:84c0a372a020 988 {
AnnaBridge 167:84c0a372a020 989 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 167:84c0a372a020 990 {
AnnaBridge 167:84c0a372a020 991 return (1UL); /* Reload value impossible */
AnnaBridge 167:84c0a372a020 992 }
AnnaBridge 167:84c0a372a020 993
AnnaBridge 167:84c0a372a020 994 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 167:84c0a372a020 995 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 167:84c0a372a020 996 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 167:84c0a372a020 997 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 167:84c0a372a020 998 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 167:84c0a372a020 999 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 167:84c0a372a020 1000 return (0UL); /* Function successful */
AnnaBridge 167:84c0a372a020 1001 }
AnnaBridge 167:84c0a372a020 1002
AnnaBridge 167:84c0a372a020 1003 #endif
AnnaBridge 167:84c0a372a020 1004
AnnaBridge 167:84c0a372a020 1005 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 167:84c0a372a020 1006
AnnaBridge 167:84c0a372a020 1007
AnnaBridge 167:84c0a372a020 1008
AnnaBridge 167:84c0a372a020 1009
AnnaBridge 167:84c0a372a020 1010 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 1011 }
AnnaBridge 167:84c0a372a020 1012 #endif
AnnaBridge 167:84c0a372a020 1013
AnnaBridge 167:84c0a372a020 1014 #endif /* __CORE_SC000_H_DEPENDANT */
AnnaBridge 167:84c0a372a020 1015
AnnaBridge 167:84c0a372a020 1016 #endif /* __CMSIS_GENERIC */