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TARGET_MTB_ADV_WISE_1530/core_cm33.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:: Anna Bridge
Date:: Fri Jun 22 15:38:59 2018 +0100
Revision:: 169:a7c7b631e539
Parent:: 167:84c0a372a020

mbed library. Release version 162

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:84c0a372a020	1	/************************************************************************//
AnnaBridge	167:84c0a372a020	2	* @file core_cm33.h
AnnaBridge	167:84c0a372a020	3	* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
Anna Bridge	169:a7c7b631e539	4	* @version V5.0.5
Anna Bridge	169:a7c7b631e539	5	* @date 08. January 2018
AnnaBridge	167:84c0a372a020	6	******************************************************************************/
AnnaBridge	167:84c0a372a020	7	/*
AnnaBridge	167:84c0a372a020	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	167:84c0a372a020	9	*
AnnaBridge	167:84c0a372a020	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	167:84c0a372a020	11	*
AnnaBridge	167:84c0a372a020	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	167:84c0a372a020	13	* not use this file except in compliance with the License.
AnnaBridge	167:84c0a372a020	14	* You may obtain a copy of the License at
AnnaBridge	167:84c0a372a020	15	*
AnnaBridge	167:84c0a372a020	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	167:84c0a372a020	17	*
AnnaBridge	167:84c0a372a020	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	167:84c0a372a020	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	167:84c0a372a020	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	167:84c0a372a020	21	* See the License for the specific language governing permissions and
AnnaBridge	167:84c0a372a020	22	* limitations under the License.
AnnaBridge	167:84c0a372a020	23	*/
AnnaBridge	167:84c0a372a020	24
AnnaBridge	167:84c0a372a020	25	#if defined ( __ICCARM__ )
Anna Bridge	169:a7c7b631e539	26	#pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge	169:a7c7b631e539	27	#elif defined (__clang__)
AnnaBridge	167:84c0a372a020	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	167:84c0a372a020	29	#endif
AnnaBridge	167:84c0a372a020	30
AnnaBridge	167:84c0a372a020	31	#ifndef __CORE_CM33_H_GENERIC
AnnaBridge	167:84c0a372a020	32	#define __CORE_CM33_H_GENERIC
AnnaBridge	167:84c0a372a020	33
AnnaBridge	167:84c0a372a020	34	#include <stdint.h>
AnnaBridge	167:84c0a372a020	35
AnnaBridge	167:84c0a372a020	36	#ifdef __cplusplus
AnnaBridge	167:84c0a372a020	37	extern "C" {
AnnaBridge	167:84c0a372a020	38	#endif
AnnaBridge	167:84c0a372a020	39
AnnaBridge	167:84c0a372a020	40	/**
AnnaBridge	167:84c0a372a020	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	167:84c0a372a020	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	167:84c0a372a020	43
AnnaBridge	167:84c0a372a020	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	167:84c0a372a020	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	167:84c0a372a020	46
AnnaBridge	167:84c0a372a020	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	167:84c0a372a020	48	Unions are used for effective representation of core registers.
AnnaBridge	167:84c0a372a020	49
AnnaBridge	167:84c0a372a020	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	167:84c0a372a020	51	Function-like macros are used to allow more efficient code.
AnnaBridge	167:84c0a372a020	52	*/
AnnaBridge	167:84c0a372a020	53
AnnaBridge	167:84c0a372a020	54
AnnaBridge	167:84c0a372a020	55	/*******************************************************************************
AnnaBridge	167:84c0a372a020	56	* CMSIS definitions
AnnaBridge	167:84c0a372a020	57	******************************************************************************/
AnnaBridge	167:84c0a372a020	58	/**
AnnaBridge	167:84c0a372a020	59	\ingroup Cortex_M33
AnnaBridge	167:84c0a372a020	60	@{
AnnaBridge	167:84c0a372a020	61	*/
AnnaBridge	167:84c0a372a020	62
AnnaBridge	167:84c0a372a020	63	#include "cmsis_version.h"
AnnaBridge	167:84c0a372a020	64
AnnaBridge	167:84c0a372a020	65	/* CMSIS CM33 definitions */
AnnaBridge	167:84c0a372a020	66	#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
AnnaBridge	167:84c0a372a020	67	#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
AnnaBridge	167:84c0a372a020	68	#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	167:84c0a372a020	69	__CM33_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
AnnaBridge	167:84c0a372a020	70
AnnaBridge	167:84c0a372a020	71	#define __CORTEX_M (33U) /!< Cortex-M Core /
AnnaBridge	167:84c0a372a020	72
AnnaBridge	167:84c0a372a020	73	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	167:84c0a372a020	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge	167:84c0a372a020	75	*/
AnnaBridge	167:84c0a372a020	76	#if defined ( __CC_ARM )
Anna Bridge	169:a7c7b631e539	77	#if defined (__TARGET_FPU_VFP)
AnnaBridge	167:84c0a372a020	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	79	#define __FPU_USED 1U
AnnaBridge	167:84c0a372a020	80	#else
AnnaBridge	167:84c0a372a020	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	82	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	83	#endif
AnnaBridge	167:84c0a372a020	84	#else
AnnaBridge	167:84c0a372a020	85	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	86	#endif
AnnaBridge	167:84c0a372a020	87
Anna Bridge	169:a7c7b631e539	88	#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
Anna Bridge	169:a7c7b631e539	89	#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	90	#define __DSP_USED 1U
AnnaBridge	167:84c0a372a020	91	#else
AnnaBridge	167:84c0a372a020	92	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
AnnaBridge	167:84c0a372a020	93	#define __DSP_USED 0U
AnnaBridge	167:84c0a372a020	94	#endif
AnnaBridge	167:84c0a372a020	95	#else
AnnaBridge	167:84c0a372a020	96	#define __DSP_USED 0U
AnnaBridge	167:84c0a372a020	97	#endif
AnnaBridge	167:84c0a372a020	98
AnnaBridge	167:84c0a372a020	99	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Anna Bridge	169:a7c7b631e539	100	#if defined (__ARM_PCS_VFP)
AnnaBridge	167:84c0a372a020	101	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	102	#define __FPU_USED 1U
AnnaBridge	167:84c0a372a020	103	#else
AnnaBridge	167:84c0a372a020	104	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	105	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	106	#endif
AnnaBridge	167:84c0a372a020	107	#else
AnnaBridge	167:84c0a372a020	108	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	109	#endif
AnnaBridge	167:84c0a372a020	110
Anna Bridge	169:a7c7b631e539	111	#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
Anna Bridge	169:a7c7b631e539	112	#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	113	#define __DSP_USED 1U
AnnaBridge	167:84c0a372a020	114	#else
AnnaBridge	167:84c0a372a020	115	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
AnnaBridge	167:84c0a372a020	116	#define __DSP_USED 0U
AnnaBridge	167:84c0a372a020	117	#endif
AnnaBridge	167:84c0a372a020	118	#else
AnnaBridge	167:84c0a372a020	119	#define __DSP_USED 0U
AnnaBridge	167:84c0a372a020	120	#endif
AnnaBridge	167:84c0a372a020	121
AnnaBridge	167:84c0a372a020	122	#elif defined ( __GNUC__ )
AnnaBridge	167:84c0a372a020	123	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	167:84c0a372a020	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	125	#define __FPU_USED 1U
AnnaBridge	167:84c0a372a020	126	#else
AnnaBridge	167:84c0a372a020	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	128	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	129	#endif
AnnaBridge	167:84c0a372a020	130	#else
AnnaBridge	167:84c0a372a020	131	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	132	#endif
AnnaBridge	167:84c0a372a020	133
Anna Bridge	169:a7c7b631e539	134	#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
Anna Bridge	169:a7c7b631e539	135	#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	136	#define __DSP_USED 1U
AnnaBridge	167:84c0a372a020	137	#else
AnnaBridge	167:84c0a372a020	138	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
AnnaBridge	167:84c0a372a020	139	#define __DSP_USED 0U
AnnaBridge	167:84c0a372a020	140	#endif
AnnaBridge	167:84c0a372a020	141	#else
AnnaBridge	167:84c0a372a020	142	#define __DSP_USED 0U
AnnaBridge	167:84c0a372a020	143	#endif
AnnaBridge	167:84c0a372a020	144
AnnaBridge	167:84c0a372a020	145	#elif defined ( __ICCARM__ )
Anna Bridge	169:a7c7b631e539	146	#if defined (__ARMVFP__)
AnnaBridge	167:84c0a372a020	147	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	148	#define __FPU_USED 1U
AnnaBridge	167:84c0a372a020	149	#else
AnnaBridge	167:84c0a372a020	150	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	151	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	152	#endif
AnnaBridge	167:84c0a372a020	153	#else
AnnaBridge	167:84c0a372a020	154	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	155	#endif
AnnaBridge	167:84c0a372a020	156
Anna Bridge	169:a7c7b631e539	157	#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
Anna Bridge	169:a7c7b631e539	158	#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	159	#define __DSP_USED 1U
AnnaBridge	167:84c0a372a020	160	#else
AnnaBridge	167:84c0a372a020	161	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
AnnaBridge	167:84c0a372a020	162	#define __DSP_USED 0U
AnnaBridge	167:84c0a372a020	163	#endif
AnnaBridge	167:84c0a372a020	164	#else
AnnaBridge	167:84c0a372a020	165	#define __DSP_USED 0U
AnnaBridge	167:84c0a372a020	166	#endif
AnnaBridge	167:84c0a372a020	167
AnnaBridge	167:84c0a372a020	168	#elif defined ( __TI_ARM__ )
Anna Bridge	169:a7c7b631e539	169	#if defined (__TI_VFP_SUPPORT__)
AnnaBridge	167:84c0a372a020	170	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	171	#define __FPU_USED 1U
AnnaBridge	167:84c0a372a020	172	#else
AnnaBridge	167:84c0a372a020	173	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	174	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	175	#endif
AnnaBridge	167:84c0a372a020	176	#else
AnnaBridge	167:84c0a372a020	177	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	178	#endif
AnnaBridge	167:84c0a372a020	179
AnnaBridge	167:84c0a372a020	180	#elif defined ( __TASKING__ )
Anna Bridge	169:a7c7b631e539	181	#if defined (__FPU_VFP__)
AnnaBridge	167:84c0a372a020	182	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	183	#define __FPU_USED 1U
AnnaBridge	167:84c0a372a020	184	#else
AnnaBridge	167:84c0a372a020	185	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	186	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	187	#endif
AnnaBridge	167:84c0a372a020	188	#else
AnnaBridge	167:84c0a372a020	189	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	190	#endif
AnnaBridge	167:84c0a372a020	191
AnnaBridge	167:84c0a372a020	192	#elif defined ( __CSMC__ )
AnnaBridge	167:84c0a372a020	193	#if ( __CSMC__ & 0x400U)
AnnaBridge	167:84c0a372a020	194	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	195	#define __FPU_USED 1U
AnnaBridge	167:84c0a372a020	196	#else
AnnaBridge	167:84c0a372a020	197	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	198	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	199	#endif
AnnaBridge	167:84c0a372a020	200	#else
AnnaBridge	167:84c0a372a020	201	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	202	#endif
AnnaBridge	167:84c0a372a020	203
AnnaBridge	167:84c0a372a020	204	#endif
AnnaBridge	167:84c0a372a020	205
AnnaBridge	167:84c0a372a020	206	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	167:84c0a372a020	207
AnnaBridge	167:84c0a372a020	208
AnnaBridge	167:84c0a372a020	209	#ifdef __cplusplus
AnnaBridge	167:84c0a372a020	210	}
AnnaBridge	167:84c0a372a020	211	#endif
AnnaBridge	167:84c0a372a020	212
AnnaBridge	167:84c0a372a020	213	#endif /* __CORE_CM33_H_GENERIC */
AnnaBridge	167:84c0a372a020	214
AnnaBridge	167:84c0a372a020	215	#ifndef __CMSIS_GENERIC
AnnaBridge	167:84c0a372a020	216
AnnaBridge	167:84c0a372a020	217	#ifndef __CORE_CM33_H_DEPENDANT
AnnaBridge	167:84c0a372a020	218	#define __CORE_CM33_H_DEPENDANT
AnnaBridge	167:84c0a372a020	219
AnnaBridge	167:84c0a372a020	220	#ifdef __cplusplus
AnnaBridge	167:84c0a372a020	221	extern "C" {
AnnaBridge	167:84c0a372a020	222	#endif
AnnaBridge	167:84c0a372a020	223
AnnaBridge	167:84c0a372a020	224	/* check device defines and use defaults */
AnnaBridge	167:84c0a372a020	225	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	167:84c0a372a020	226	#ifndef __CM33_REV
AnnaBridge	167:84c0a372a020	227	#define __CM33_REV 0x0000U
AnnaBridge	167:84c0a372a020	228	#warning "__CM33_REV not defined in device header file; using default!"
AnnaBridge	167:84c0a372a020	229	#endif
AnnaBridge	167:84c0a372a020	230
AnnaBridge	167:84c0a372a020	231	#ifndef __FPU_PRESENT
AnnaBridge	167:84c0a372a020	232	#define __FPU_PRESENT 0U
AnnaBridge	167:84c0a372a020	233	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	167:84c0a372a020	234	#endif
AnnaBridge	167:84c0a372a020	235
AnnaBridge	167:84c0a372a020	236	#ifndef __MPU_PRESENT
AnnaBridge	167:84c0a372a020	237	#define __MPU_PRESENT 0U
AnnaBridge	167:84c0a372a020	238	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	167:84c0a372a020	239	#endif
AnnaBridge	167:84c0a372a020	240
AnnaBridge	167:84c0a372a020	241	#ifndef __SAUREGION_PRESENT
AnnaBridge	167:84c0a372a020	242	#define __SAUREGION_PRESENT 0U
AnnaBridge	167:84c0a372a020	243	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge	167:84c0a372a020	244	#endif
AnnaBridge	167:84c0a372a020	245
AnnaBridge	167:84c0a372a020	246	#ifndef __DSP_PRESENT
AnnaBridge	167:84c0a372a020	247	#define __DSP_PRESENT 0U
AnnaBridge	167:84c0a372a020	248	#warning "__DSP_PRESENT not defined in device header file; using default!"
AnnaBridge	167:84c0a372a020	249	#endif
AnnaBridge	167:84c0a372a020	250
AnnaBridge	167:84c0a372a020	251	#ifndef __NVIC_PRIO_BITS
AnnaBridge	167:84c0a372a020	252	#define __NVIC_PRIO_BITS 3U
AnnaBridge	167:84c0a372a020	253	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	167:84c0a372a020	254	#endif
AnnaBridge	167:84c0a372a020	255
AnnaBridge	167:84c0a372a020	256	#ifndef __Vendor_SysTickConfig
AnnaBridge	167:84c0a372a020	257	#define __Vendor_SysTickConfig 0U
AnnaBridge	167:84c0a372a020	258	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	167:84c0a372a020	259	#endif
AnnaBridge	167:84c0a372a020	260	#endif
AnnaBridge	167:84c0a372a020	261
AnnaBridge	167:84c0a372a020	262	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	167:84c0a372a020	263	/**
AnnaBridge	167:84c0a372a020	264	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	167:84c0a372a020	265
AnnaBridge	167:84c0a372a020	266	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	167:84c0a372a020	267	\li to specify the access to peripheral variables.
AnnaBridge	167:84c0a372a020	268	\li for automatic generation of peripheral register debug information.
AnnaBridge	167:84c0a372a020	269	*/
AnnaBridge	167:84c0a372a020	270	#ifdef __cplusplus
AnnaBridge	167:84c0a372a020	271	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	167:84c0a372a020	272	#else
AnnaBridge	167:84c0a372a020	273	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	167:84c0a372a020	274	#endif
AnnaBridge	167:84c0a372a020	275	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	167:84c0a372a020	276	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	167:84c0a372a020	277
AnnaBridge	167:84c0a372a020	278	/* following defines should be used for structure members */
AnnaBridge	167:84c0a372a020	279	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	167:84c0a372a020	280	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	167:84c0a372a020	281	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	167:84c0a372a020	282
AnnaBridge	167:84c0a372a020	283	/@} end of group Cortex_M33 /
AnnaBridge	167:84c0a372a020	284
AnnaBridge	167:84c0a372a020	285
AnnaBridge	167:84c0a372a020	286
AnnaBridge	167:84c0a372a020	287	/*******************************************************************************
AnnaBridge	167:84c0a372a020	288	* Register Abstraction
AnnaBridge	167:84c0a372a020	289	Core Register contain:
AnnaBridge	167:84c0a372a020	290	- Core Register
AnnaBridge	167:84c0a372a020	291	- Core NVIC Register
AnnaBridge	167:84c0a372a020	292	- Core SCB Register
AnnaBridge	167:84c0a372a020	293	- Core SysTick Register
AnnaBridge	167:84c0a372a020	294	- Core Debug Register
AnnaBridge	167:84c0a372a020	295	- Core MPU Register
AnnaBridge	167:84c0a372a020	296	- Core SAU Register
AnnaBridge	167:84c0a372a020	297	- Core FPU Register
AnnaBridge	167:84c0a372a020	298	******************************************************************************/
AnnaBridge	167:84c0a372a020	299	/**
AnnaBridge	167:84c0a372a020	300	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	167:84c0a372a020	301	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	167:84c0a372a020	302	*/
AnnaBridge	167:84c0a372a020	303
AnnaBridge	167:84c0a372a020	304	/**
AnnaBridge	167:84c0a372a020	305	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	306	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	167:84c0a372a020	307	\brief Core Register type definitions.
AnnaBridge	167:84c0a372a020	308	@{
AnnaBridge	167:84c0a372a020	309	*/
AnnaBridge	167:84c0a372a020	310
AnnaBridge	167:84c0a372a020	311	/**
AnnaBridge	167:84c0a372a020	312	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	167:84c0a372a020	313	*/
AnnaBridge	167:84c0a372a020	314	typedef union
AnnaBridge	167:84c0a372a020	315	{
AnnaBridge	167:84c0a372a020	316	struct
AnnaBridge	167:84c0a372a020	317	{
AnnaBridge	167:84c0a372a020	318	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
AnnaBridge	167:84c0a372a020	319	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	167:84c0a372a020	320	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
AnnaBridge	167:84c0a372a020	321	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	167:84c0a372a020	322	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	167:84c0a372a020	323	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	167:84c0a372a020	324	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	167:84c0a372a020	325	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	167:84c0a372a020	326	} b; /!< Structure used for bit access /
AnnaBridge	167:84c0a372a020	327	uint32_t w; /!< Type used for word access /
AnnaBridge	167:84c0a372a020	328	} APSR_Type;
AnnaBridge	167:84c0a372a020	329
AnnaBridge	167:84c0a372a020	330	/* APSR Register Definitions */
AnnaBridge	167:84c0a372a020	331	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	167:84c0a372a020	332	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	167:84c0a372a020	333
AnnaBridge	167:84c0a372a020	334	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	167:84c0a372a020	335	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	167:84c0a372a020	336
AnnaBridge	167:84c0a372a020	337	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	167:84c0a372a020	338	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	167:84c0a372a020	339
AnnaBridge	167:84c0a372a020	340	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	167:84c0a372a020	341	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	167:84c0a372a020	342
AnnaBridge	167:84c0a372a020	343	#define APSR_Q_Pos 27U /!< APSR: Q Position /
AnnaBridge	167:84c0a372a020	344	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
AnnaBridge	167:84c0a372a020	345
AnnaBridge	167:84c0a372a020	346	#define APSR_GE_Pos 16U /!< APSR: GE Position /
AnnaBridge	167:84c0a372a020	347	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
AnnaBridge	167:84c0a372a020	348
AnnaBridge	167:84c0a372a020	349
AnnaBridge	167:84c0a372a020	350	/**
AnnaBridge	167:84c0a372a020	351	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	167:84c0a372a020	352	*/
AnnaBridge	167:84c0a372a020	353	typedef union
AnnaBridge	167:84c0a372a020	354	{
AnnaBridge	167:84c0a372a020	355	struct
AnnaBridge	167:84c0a372a020	356	{
AnnaBridge	167:84c0a372a020	357	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	167:84c0a372a020	358	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	167:84c0a372a020	359	} b; /!< Structure used for bit access /
AnnaBridge	167:84c0a372a020	360	uint32_t w; /!< Type used for word access /
AnnaBridge	167:84c0a372a020	361	} IPSR_Type;
AnnaBridge	167:84c0a372a020	362
AnnaBridge	167:84c0a372a020	363	/* IPSR Register Definitions */
AnnaBridge	167:84c0a372a020	364	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	167:84c0a372a020	365	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	167:84c0a372a020	366
AnnaBridge	167:84c0a372a020	367
AnnaBridge	167:84c0a372a020	368	/**
AnnaBridge	167:84c0a372a020	369	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	167:84c0a372a020	370	*/
AnnaBridge	167:84c0a372a020	371	typedef union
AnnaBridge	167:84c0a372a020	372	{
AnnaBridge	167:84c0a372a020	373	struct
AnnaBridge	167:84c0a372a020	374	{
AnnaBridge	167:84c0a372a020	375	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	167:84c0a372a020	376	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
AnnaBridge	167:84c0a372a020	377	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	167:84c0a372a020	378	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
AnnaBridge	167:84c0a372a020	379	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
AnnaBridge	167:84c0a372a020	380	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
AnnaBridge	167:84c0a372a020	381	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	167:84c0a372a020	382	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	167:84c0a372a020	383	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	167:84c0a372a020	384	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	167:84c0a372a020	385	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	167:84c0a372a020	386	} b; /!< Structure used for bit access /
AnnaBridge	167:84c0a372a020	387	uint32_t w; /!< Type used for word access /
AnnaBridge	167:84c0a372a020	388	} xPSR_Type;
AnnaBridge	167:84c0a372a020	389
AnnaBridge	167:84c0a372a020	390	/* xPSR Register Definitions */
AnnaBridge	167:84c0a372a020	391	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	167:84c0a372a020	392	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	167:84c0a372a020	393
AnnaBridge	167:84c0a372a020	394	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	167:84c0a372a020	395	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	167:84c0a372a020	396
AnnaBridge	167:84c0a372a020	397	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	167:84c0a372a020	398	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	167:84c0a372a020	399
AnnaBridge	167:84c0a372a020	400	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	167:84c0a372a020	401	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	167:84c0a372a020	402
AnnaBridge	167:84c0a372a020	403	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
AnnaBridge	167:84c0a372a020	404	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
AnnaBridge	167:84c0a372a020	405
AnnaBridge	167:84c0a372a020	406	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
AnnaBridge	167:84c0a372a020	407	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
AnnaBridge	167:84c0a372a020	408
AnnaBridge	167:84c0a372a020	409	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	167:84c0a372a020	410	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	167:84c0a372a020	411
AnnaBridge	167:84c0a372a020	412	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
AnnaBridge	167:84c0a372a020	413	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
AnnaBridge	167:84c0a372a020	414
AnnaBridge	167:84c0a372a020	415	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	167:84c0a372a020	416	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	167:84c0a372a020	417
AnnaBridge	167:84c0a372a020	418
AnnaBridge	167:84c0a372a020	419	/**
AnnaBridge	167:84c0a372a020	420	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	167:84c0a372a020	421	*/
AnnaBridge	167:84c0a372a020	422	typedef union
AnnaBridge	167:84c0a372a020	423	{
AnnaBridge	167:84c0a372a020	424	struct
AnnaBridge	167:84c0a372a020	425	{
AnnaBridge	167:84c0a372a020	426	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	167:84c0a372a020	427	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
AnnaBridge	167:84c0a372a020	428	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
AnnaBridge	167:84c0a372a020	429	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
AnnaBridge	167:84c0a372a020	430	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
AnnaBridge	167:84c0a372a020	431	} b; /!< Structure used for bit access /
AnnaBridge	167:84c0a372a020	432	uint32_t w; /!< Type used for word access /
AnnaBridge	167:84c0a372a020	433	} CONTROL_Type;
AnnaBridge	167:84c0a372a020	434
AnnaBridge	167:84c0a372a020	435	/* CONTROL Register Definitions */
AnnaBridge	167:84c0a372a020	436	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
AnnaBridge	167:84c0a372a020	437	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
AnnaBridge	167:84c0a372a020	438
AnnaBridge	167:84c0a372a020	439	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
AnnaBridge	167:84c0a372a020	440	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
AnnaBridge	167:84c0a372a020	441
AnnaBridge	167:84c0a372a020	442	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	167:84c0a372a020	443	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	167:84c0a372a020	444
AnnaBridge	167:84c0a372a020	445	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	167:84c0a372a020	446	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	167:84c0a372a020	447
AnnaBridge	167:84c0a372a020	448	/@} end of group CMSIS_CORE /
AnnaBridge	167:84c0a372a020	449
AnnaBridge	167:84c0a372a020	450
AnnaBridge	167:84c0a372a020	451	/**
AnnaBridge	167:84c0a372a020	452	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	453	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	167:84c0a372a020	454	\brief Type definitions for the NVIC Registers
AnnaBridge	167:84c0a372a020	455	@{
AnnaBridge	167:84c0a372a020	456	*/
AnnaBridge	167:84c0a372a020	457
AnnaBridge	167:84c0a372a020	458	/**
AnnaBridge	167:84c0a372a020	459	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	167:84c0a372a020	460	*/
AnnaBridge	167:84c0a372a020	461	typedef struct
AnnaBridge	167:84c0a372a020	462	{
AnnaBridge	167:84c0a372a020	463	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	167:84c0a372a020	464	uint32_t RESERVED0[16U];
AnnaBridge	167:84c0a372a020	465	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	167:84c0a372a020	466	uint32_t RSERVED1[16U];
AnnaBridge	167:84c0a372a020	467	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	167:84c0a372a020	468	uint32_t RESERVED2[16U];
AnnaBridge	167:84c0a372a020	469	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	167:84c0a372a020	470	uint32_t RESERVED3[16U];
AnnaBridge	167:84c0a372a020	471	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	167:84c0a372a020	472	uint32_t RESERVED4[16U];
AnnaBridge	167:84c0a372a020	473	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
AnnaBridge	167:84c0a372a020	474	uint32_t RESERVED5[16U];
AnnaBridge	167:84c0a372a020	475	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	167:84c0a372a020	476	uint32_t RESERVED6[580U];
AnnaBridge	167:84c0a372a020	477	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
AnnaBridge	167:84c0a372a020	478	} NVIC_Type;
AnnaBridge	167:84c0a372a020	479
AnnaBridge	167:84c0a372a020	480	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	167:84c0a372a020	481	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
AnnaBridge	167:84c0a372a020	482	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
AnnaBridge	167:84c0a372a020	483
AnnaBridge	167:84c0a372a020	484	/@} end of group CMSIS_NVIC /
AnnaBridge	167:84c0a372a020	485
AnnaBridge	167:84c0a372a020	486
AnnaBridge	167:84c0a372a020	487	/**
AnnaBridge	167:84c0a372a020	488	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	489	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	167:84c0a372a020	490	\brief Type definitions for the System Control Block Registers
AnnaBridge	167:84c0a372a020	491	@{
AnnaBridge	167:84c0a372a020	492	*/
AnnaBridge	167:84c0a372a020	493
AnnaBridge	167:84c0a372a020	494	/**
AnnaBridge	167:84c0a372a020	495	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	167:84c0a372a020	496	*/
AnnaBridge	167:84c0a372a020	497	typedef struct
AnnaBridge	167:84c0a372a020	498	{
AnnaBridge	167:84c0a372a020	499	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	167:84c0a372a020	500	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	167:84c0a372a020	501	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	167:84c0a372a020	502	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	167:84c0a372a020	503	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	167:84c0a372a020	504	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	167:84c0a372a020	505	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	167:84c0a372a020	506	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	167:84c0a372a020	507	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	167:84c0a372a020	508	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	167:84c0a372a020	509	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	167:84c0a372a020	510	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	167:84c0a372a020	511	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	167:84c0a372a020	512	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	167:84c0a372a020	513	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	167:84c0a372a020	514	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	167:84c0a372a020	515	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	167:84c0a372a020	516	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	167:84c0a372a020	517	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	167:84c0a372a020	518	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
AnnaBridge	167:84c0a372a020	519	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
AnnaBridge	167:84c0a372a020	520	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
AnnaBridge	167:84c0a372a020	521	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
AnnaBridge	167:84c0a372a020	522	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	167:84c0a372a020	523	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
AnnaBridge	167:84c0a372a020	524	uint32_t RESERVED3[92U];
AnnaBridge	167:84c0a372a020	525	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
AnnaBridge	167:84c0a372a020	526	uint32_t RESERVED4[15U];
AnnaBridge	167:84c0a372a020	527	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
AnnaBridge	167:84c0a372a020	528	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
AnnaBridge	167:84c0a372a020	529	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
AnnaBridge	167:84c0a372a020	530	uint32_t RESERVED5[1U];
AnnaBridge	167:84c0a372a020	531	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
AnnaBridge	167:84c0a372a020	532	uint32_t RESERVED6[1U];
AnnaBridge	167:84c0a372a020	533	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
AnnaBridge	167:84c0a372a020	534	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
AnnaBridge	167:84c0a372a020	535	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
AnnaBridge	167:84c0a372a020	536	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
AnnaBridge	167:84c0a372a020	537	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
AnnaBridge	167:84c0a372a020	538	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
AnnaBridge	167:84c0a372a020	539	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
AnnaBridge	167:84c0a372a020	540	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
AnnaBridge	167:84c0a372a020	541	uint32_t RESERVED7[6U];
AnnaBridge	167:84c0a372a020	542	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
AnnaBridge	167:84c0a372a020	543	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
AnnaBridge	167:84c0a372a020	544	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
AnnaBridge	167:84c0a372a020	545	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
AnnaBridge	167:84c0a372a020	546	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
AnnaBridge	167:84c0a372a020	547	uint32_t RESERVED8[1U];
AnnaBridge	167:84c0a372a020	548	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
AnnaBridge	167:84c0a372a020	549	} SCB_Type;
AnnaBridge	167:84c0a372a020	550
AnnaBridge	167:84c0a372a020	551	/* SCB CPUID Register Definitions */
AnnaBridge	167:84c0a372a020	552	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	167:84c0a372a020	553	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	167:84c0a372a020	554
AnnaBridge	167:84c0a372a020	555	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	167:84c0a372a020	556	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	167:84c0a372a020	557
AnnaBridge	167:84c0a372a020	558	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	167:84c0a372a020	559	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	167:84c0a372a020	560
AnnaBridge	167:84c0a372a020	561	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	167:84c0a372a020	562	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	167:84c0a372a020	563
AnnaBridge	167:84c0a372a020	564	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	167:84c0a372a020	565	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	167:84c0a372a020	566
AnnaBridge	167:84c0a372a020	567	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	167:84c0a372a020	568	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
AnnaBridge	167:84c0a372a020	569	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
AnnaBridge	167:84c0a372a020	570
AnnaBridge	167:84c0a372a020	571	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
AnnaBridge	167:84c0a372a020	572	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
AnnaBridge	167:84c0a372a020	573
AnnaBridge	167:84c0a372a020	574	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	167:84c0a372a020	575	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	167:84c0a372a020	576
AnnaBridge	167:84c0a372a020	577	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	167:84c0a372a020	578	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	167:84c0a372a020	579
AnnaBridge	167:84c0a372a020	580	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	167:84c0a372a020	581	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	167:84c0a372a020	582
AnnaBridge	167:84c0a372a020	583	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	167:84c0a372a020	584	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	167:84c0a372a020	585
AnnaBridge	167:84c0a372a020	586	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
AnnaBridge	167:84c0a372a020	587	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
AnnaBridge	167:84c0a372a020	588
AnnaBridge	167:84c0a372a020	589	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	167:84c0a372a020	590	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	167:84c0a372a020	591
AnnaBridge	167:84c0a372a020	592	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	167:84c0a372a020	593	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	167:84c0a372a020	594
AnnaBridge	167:84c0a372a020	595	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	167:84c0a372a020	596	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	167:84c0a372a020	597
AnnaBridge	167:84c0a372a020	598	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	167:84c0a372a020	599	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	167:84c0a372a020	600
AnnaBridge	167:84c0a372a020	601	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	167:84c0a372a020	602	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	167:84c0a372a020	603
AnnaBridge	167:84c0a372a020	604	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	167:84c0a372a020	605	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	167:84c0a372a020	606	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	167:84c0a372a020	607
AnnaBridge	167:84c0a372a020	608	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	167:84c0a372a020	609	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	167:84c0a372a020	610	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	167:84c0a372a020	611
AnnaBridge	167:84c0a372a020	612	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	167:84c0a372a020	613	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	167:84c0a372a020	614
AnnaBridge	167:84c0a372a020	615	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	167:84c0a372a020	616	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	167:84c0a372a020	617
AnnaBridge	167:84c0a372a020	618	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
AnnaBridge	167:84c0a372a020	619	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
AnnaBridge	167:84c0a372a020	620
AnnaBridge	167:84c0a372a020	621	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
AnnaBridge	167:84c0a372a020	622	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
AnnaBridge	167:84c0a372a020	623
AnnaBridge	167:84c0a372a020	624	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
AnnaBridge	167:84c0a372a020	625	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
AnnaBridge	167:84c0a372a020	626
AnnaBridge	167:84c0a372a020	627	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
AnnaBridge	167:84c0a372a020	628	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
AnnaBridge	167:84c0a372a020	629
AnnaBridge	167:84c0a372a020	630	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	167:84c0a372a020	631	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	167:84c0a372a020	632
AnnaBridge	167:84c0a372a020	633	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	167:84c0a372a020	634	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	167:84c0a372a020	635
AnnaBridge	167:84c0a372a020	636	/* SCB System Control Register Definitions */
AnnaBridge	167:84c0a372a020	637	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	167:84c0a372a020	638	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	167:84c0a372a020	639
AnnaBridge	167:84c0a372a020	640	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
AnnaBridge	167:84c0a372a020	641	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
AnnaBridge	167:84c0a372a020	642
AnnaBridge	167:84c0a372a020	643	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	167:84c0a372a020	644	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	167:84c0a372a020	645
AnnaBridge	167:84c0a372a020	646	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	167:84c0a372a020	647	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	167:84c0a372a020	648
AnnaBridge	167:84c0a372a020	649	/* SCB Configuration Control Register Definitions */
AnnaBridge	167:84c0a372a020	650	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
AnnaBridge	167:84c0a372a020	651	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
AnnaBridge	167:84c0a372a020	652
AnnaBridge	167:84c0a372a020	653	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
AnnaBridge	167:84c0a372a020	654	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
AnnaBridge	167:84c0a372a020	655
AnnaBridge	167:84c0a372a020	656	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
AnnaBridge	167:84c0a372a020	657	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
AnnaBridge	167:84c0a372a020	658
AnnaBridge	167:84c0a372a020	659	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
AnnaBridge	167:84c0a372a020	660	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
AnnaBridge	167:84c0a372a020	661
AnnaBridge	167:84c0a372a020	662	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	167:84c0a372a020	663	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	167:84c0a372a020	664
AnnaBridge	167:84c0a372a020	665	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	167:84c0a372a020	666	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	167:84c0a372a020	667
AnnaBridge	167:84c0a372a020	668	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	167:84c0a372a020	669	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	167:84c0a372a020	670
AnnaBridge	167:84c0a372a020	671	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	167:84c0a372a020	672	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	167:84c0a372a020	673
AnnaBridge	167:84c0a372a020	674	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	167:84c0a372a020	675	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
AnnaBridge	167:84c0a372a020	676	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
AnnaBridge	167:84c0a372a020	677
AnnaBridge	167:84c0a372a020	678	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
AnnaBridge	167:84c0a372a020	679	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
AnnaBridge	167:84c0a372a020	680
AnnaBridge	167:84c0a372a020	681	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
AnnaBridge	167:84c0a372a020	682	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
AnnaBridge	167:84c0a372a020	683
AnnaBridge	167:84c0a372a020	684	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
AnnaBridge	167:84c0a372a020	685	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
AnnaBridge	167:84c0a372a020	686
AnnaBridge	167:84c0a372a020	687	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
AnnaBridge	167:84c0a372a020	688	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
AnnaBridge	167:84c0a372a020	689
AnnaBridge	167:84c0a372a020	690	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
AnnaBridge	167:84c0a372a020	691	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
AnnaBridge	167:84c0a372a020	692
AnnaBridge	167:84c0a372a020	693	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	167:84c0a372a020	694	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	167:84c0a372a020	695
AnnaBridge	167:84c0a372a020	696	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
AnnaBridge	167:84c0a372a020	697	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
AnnaBridge	167:84c0a372a020	698
AnnaBridge	167:84c0a372a020	699	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
AnnaBridge	167:84c0a372a020	700	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
AnnaBridge	167:84c0a372a020	701
AnnaBridge	167:84c0a372a020	702	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
AnnaBridge	167:84c0a372a020	703	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
AnnaBridge	167:84c0a372a020	704
AnnaBridge	167:84c0a372a020	705	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	167:84c0a372a020	706	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	167:84c0a372a020	707
AnnaBridge	167:84c0a372a020	708	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	167:84c0a372a020	709	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	167:84c0a372a020	710
AnnaBridge	167:84c0a372a020	711	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
AnnaBridge	167:84c0a372a020	712	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
AnnaBridge	167:84c0a372a020	713
AnnaBridge	167:84c0a372a020	714	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	167:84c0a372a020	715	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	167:84c0a372a020	716
AnnaBridge	167:84c0a372a020	717	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
AnnaBridge	167:84c0a372a020	718	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
AnnaBridge	167:84c0a372a020	719
AnnaBridge	167:84c0a372a020	720	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
AnnaBridge	167:84c0a372a020	721	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
AnnaBridge	167:84c0a372a020	722
AnnaBridge	167:84c0a372a020	723	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
AnnaBridge	167:84c0a372a020	724	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
AnnaBridge	167:84c0a372a020	725
AnnaBridge	167:84c0a372a020	726	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
AnnaBridge	167:84c0a372a020	727	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
AnnaBridge	167:84c0a372a020	728
AnnaBridge	167:84c0a372a020	729	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
AnnaBridge	167:84c0a372a020	730	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
AnnaBridge	167:84c0a372a020	731
AnnaBridge	167:84c0a372a020	732	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
AnnaBridge	167:84c0a372a020	733	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
AnnaBridge	167:84c0a372a020	734
AnnaBridge	167:84c0a372a020	735	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	167:84c0a372a020	736	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
AnnaBridge	167:84c0a372a020	737	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
AnnaBridge	167:84c0a372a020	738
AnnaBridge	167:84c0a372a020	739	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
AnnaBridge	167:84c0a372a020	740	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
AnnaBridge	167:84c0a372a020	741
AnnaBridge	167:84c0a372a020	742	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
AnnaBridge	167:84c0a372a020	743	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
AnnaBridge	167:84c0a372a020	744
AnnaBridge	167:84c0a372a020	745	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:84c0a372a020	746	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	167:84c0a372a020	747	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	167:84c0a372a020	748
AnnaBridge	167:84c0a372a020	749	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
AnnaBridge	167:84c0a372a020	750	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
AnnaBridge	167:84c0a372a020	751
AnnaBridge	167:84c0a372a020	752	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	167:84c0a372a020	753	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	167:84c0a372a020	754
AnnaBridge	167:84c0a372a020	755	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	167:84c0a372a020	756	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	167:84c0a372a020	757
AnnaBridge	167:84c0a372a020	758	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	167:84c0a372a020	759	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	167:84c0a372a020	760
AnnaBridge	167:84c0a372a020	761	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	167:84c0a372a020	762	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	167:84c0a372a020	763
AnnaBridge	167:84c0a372a020	764	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:84c0a372a020	765	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	167:84c0a372a020	766	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	167:84c0a372a020	767
AnnaBridge	167:84c0a372a020	768	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
AnnaBridge	167:84c0a372a020	769	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
AnnaBridge	167:84c0a372a020	770
AnnaBridge	167:84c0a372a020	771	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	167:84c0a372a020	772	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	167:84c0a372a020	773
AnnaBridge	167:84c0a372a020	774	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	167:84c0a372a020	775	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	167:84c0a372a020	776
AnnaBridge	167:84c0a372a020	777	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	167:84c0a372a020	778	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	167:84c0a372a020	779
AnnaBridge	167:84c0a372a020	780	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	167:84c0a372a020	781	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	167:84c0a372a020	782
AnnaBridge	167:84c0a372a020	783	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	167:84c0a372a020	784	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	167:84c0a372a020	785
AnnaBridge	167:84c0a372a020	786	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:84c0a372a020	787	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	167:84c0a372a020	788	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	167:84c0a372a020	789
AnnaBridge	167:84c0a372a020	790	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	167:84c0a372a020	791	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	167:84c0a372a020	792
AnnaBridge	167:84c0a372a020	793	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
AnnaBridge	167:84c0a372a020	794	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
AnnaBridge	167:84c0a372a020	795
AnnaBridge	167:84c0a372a020	796	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	167:84c0a372a020	797	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	167:84c0a372a020	798
AnnaBridge	167:84c0a372a020	799	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	167:84c0a372a020	800	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	167:84c0a372a020	801
AnnaBridge	167:84c0a372a020	802	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	167:84c0a372a020	803	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	167:84c0a372a020	804
AnnaBridge	167:84c0a372a020	805	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	167:84c0a372a020	806	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	167:84c0a372a020	807
AnnaBridge	167:84c0a372a020	808	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	167:84c0a372a020	809	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
AnnaBridge	167:84c0a372a020	810	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
AnnaBridge	167:84c0a372a020	811
AnnaBridge	167:84c0a372a020	812	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
AnnaBridge	167:84c0a372a020	813	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
AnnaBridge	167:84c0a372a020	814
AnnaBridge	167:84c0a372a020	815	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
AnnaBridge	167:84c0a372a020	816	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
AnnaBridge	167:84c0a372a020	817
AnnaBridge	167:84c0a372a020	818	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	167:84c0a372a020	819	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
AnnaBridge	167:84c0a372a020	820	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
AnnaBridge	167:84c0a372a020	821
AnnaBridge	167:84c0a372a020	822	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
AnnaBridge	167:84c0a372a020	823	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
AnnaBridge	167:84c0a372a020	824
AnnaBridge	167:84c0a372a020	825	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
AnnaBridge	167:84c0a372a020	826	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
AnnaBridge	167:84c0a372a020	827
AnnaBridge	167:84c0a372a020	828	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
AnnaBridge	167:84c0a372a020	829	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
AnnaBridge	167:84c0a372a020	830
AnnaBridge	167:84c0a372a020	831	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
AnnaBridge	167:84c0a372a020	832	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
AnnaBridge	167:84c0a372a020	833
AnnaBridge	167:84c0a372a020	834	/* SCB Non-Secure Access Control Register Definitions */
AnnaBridge	167:84c0a372a020	835	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
AnnaBridge	167:84c0a372a020	836	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
AnnaBridge	167:84c0a372a020	837
AnnaBridge	167:84c0a372a020	838	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
AnnaBridge	167:84c0a372a020	839	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
AnnaBridge	167:84c0a372a020	840
AnnaBridge	167:84c0a372a020	841	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
AnnaBridge	167:84c0a372a020	842	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
AnnaBridge	167:84c0a372a020	843
AnnaBridge	167:84c0a372a020	844	/* SCB Cache Level ID Register Definitions */
AnnaBridge	167:84c0a372a020	845	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
AnnaBridge	167:84c0a372a020	846	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
AnnaBridge	167:84c0a372a020	847
AnnaBridge	167:84c0a372a020	848	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
AnnaBridge	167:84c0a372a020	849	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
AnnaBridge	167:84c0a372a020	850
AnnaBridge	167:84c0a372a020	851	/* SCB Cache Type Register Definitions */
AnnaBridge	167:84c0a372a020	852	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
AnnaBridge	167:84c0a372a020	853	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
AnnaBridge	167:84c0a372a020	854
AnnaBridge	167:84c0a372a020	855	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
AnnaBridge	167:84c0a372a020	856	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
AnnaBridge	167:84c0a372a020	857
AnnaBridge	167:84c0a372a020	858	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
AnnaBridge	167:84c0a372a020	859	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
AnnaBridge	167:84c0a372a020	860
AnnaBridge	167:84c0a372a020	861	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
AnnaBridge	167:84c0a372a020	862	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
AnnaBridge	167:84c0a372a020	863
AnnaBridge	167:84c0a372a020	864	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
AnnaBridge	167:84c0a372a020	865	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
AnnaBridge	167:84c0a372a020	866
AnnaBridge	167:84c0a372a020	867	/* SCB Cache Size ID Register Definitions */
AnnaBridge	167:84c0a372a020	868	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
AnnaBridge	167:84c0a372a020	869	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
AnnaBridge	167:84c0a372a020	870
AnnaBridge	167:84c0a372a020	871	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
AnnaBridge	167:84c0a372a020	872	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
AnnaBridge	167:84c0a372a020	873
AnnaBridge	167:84c0a372a020	874	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
AnnaBridge	167:84c0a372a020	875	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
AnnaBridge	167:84c0a372a020	876
AnnaBridge	167:84c0a372a020	877	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
AnnaBridge	167:84c0a372a020	878	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
AnnaBridge	167:84c0a372a020	879
AnnaBridge	167:84c0a372a020	880	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
AnnaBridge	167:84c0a372a020	881	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
AnnaBridge	167:84c0a372a020	882
AnnaBridge	167:84c0a372a020	883	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
AnnaBridge	167:84c0a372a020	884	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
AnnaBridge	167:84c0a372a020	885
AnnaBridge	167:84c0a372a020	886	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
AnnaBridge	167:84c0a372a020	887	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
AnnaBridge	167:84c0a372a020	888
AnnaBridge	167:84c0a372a020	889	/* SCB Cache Size Selection Register Definitions */
AnnaBridge	167:84c0a372a020	890	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
AnnaBridge	167:84c0a372a020	891	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
AnnaBridge	167:84c0a372a020	892
AnnaBridge	167:84c0a372a020	893	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
AnnaBridge	167:84c0a372a020	894	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
AnnaBridge	167:84c0a372a020	895
AnnaBridge	167:84c0a372a020	896	/* SCB Software Triggered Interrupt Register Definitions */
AnnaBridge	167:84c0a372a020	897	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
AnnaBridge	167:84c0a372a020	898	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
AnnaBridge	167:84c0a372a020	899
AnnaBridge	167:84c0a372a020	900	/* SCB D-Cache Invalidate by Set-way Register Definitions */
AnnaBridge	167:84c0a372a020	901	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
AnnaBridge	167:84c0a372a020	902	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
AnnaBridge	167:84c0a372a020	903
AnnaBridge	167:84c0a372a020	904	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
AnnaBridge	167:84c0a372a020	905	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
AnnaBridge	167:84c0a372a020	906
AnnaBridge	167:84c0a372a020	907	/* SCB D-Cache Clean by Set-way Register Definitions */
AnnaBridge	167:84c0a372a020	908	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
AnnaBridge	167:84c0a372a020	909	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
AnnaBridge	167:84c0a372a020	910
AnnaBridge	167:84c0a372a020	911	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
AnnaBridge	167:84c0a372a020	912	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
AnnaBridge	167:84c0a372a020	913
AnnaBridge	167:84c0a372a020	914	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
AnnaBridge	167:84c0a372a020	915	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
AnnaBridge	167:84c0a372a020	916	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
AnnaBridge	167:84c0a372a020	917
AnnaBridge	167:84c0a372a020	918	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
AnnaBridge	167:84c0a372a020	919	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
AnnaBridge	167:84c0a372a020	920
AnnaBridge	167:84c0a372a020	921	/* Instruction Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	167:84c0a372a020	922	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
AnnaBridge	167:84c0a372a020	923	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
AnnaBridge	167:84c0a372a020	924
AnnaBridge	167:84c0a372a020	925	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
AnnaBridge	167:84c0a372a020	926	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
AnnaBridge	167:84c0a372a020	927
AnnaBridge	167:84c0a372a020	928	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
AnnaBridge	167:84c0a372a020	929	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
AnnaBridge	167:84c0a372a020	930
AnnaBridge	167:84c0a372a020	931	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
AnnaBridge	167:84c0a372a020	932	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
AnnaBridge	167:84c0a372a020	933
AnnaBridge	167:84c0a372a020	934	/* Data Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	167:84c0a372a020	935	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
AnnaBridge	167:84c0a372a020	936	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
AnnaBridge	167:84c0a372a020	937
AnnaBridge	167:84c0a372a020	938	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
AnnaBridge	167:84c0a372a020	939	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
AnnaBridge	167:84c0a372a020	940
AnnaBridge	167:84c0a372a020	941	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
AnnaBridge	167:84c0a372a020	942	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
AnnaBridge	167:84c0a372a020	943
AnnaBridge	167:84c0a372a020	944	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
AnnaBridge	167:84c0a372a020	945	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
AnnaBridge	167:84c0a372a020	946
AnnaBridge	167:84c0a372a020	947	/* AHBP Control Register Definitions */
AnnaBridge	167:84c0a372a020	948	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
AnnaBridge	167:84c0a372a020	949	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
AnnaBridge	167:84c0a372a020	950
AnnaBridge	167:84c0a372a020	951	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
AnnaBridge	167:84c0a372a020	952	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
AnnaBridge	167:84c0a372a020	953
AnnaBridge	167:84c0a372a020	954	/* L1 Cache Control Register Definitions */
AnnaBridge	167:84c0a372a020	955	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
AnnaBridge	167:84c0a372a020	956	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
AnnaBridge	167:84c0a372a020	957
AnnaBridge	167:84c0a372a020	958	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
AnnaBridge	167:84c0a372a020	959	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
AnnaBridge	167:84c0a372a020	960
AnnaBridge	167:84c0a372a020	961	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
AnnaBridge	167:84c0a372a020	962	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
AnnaBridge	167:84c0a372a020	963
AnnaBridge	167:84c0a372a020	964	/* AHBS Control Register Definitions */
AnnaBridge	167:84c0a372a020	965	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
AnnaBridge	167:84c0a372a020	966	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
AnnaBridge	167:84c0a372a020	967
AnnaBridge	167:84c0a372a020	968	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
AnnaBridge	167:84c0a372a020	969	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
AnnaBridge	167:84c0a372a020	970
AnnaBridge	167:84c0a372a020	971	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
AnnaBridge	167:84c0a372a020	972	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
AnnaBridge	167:84c0a372a020	973
AnnaBridge	167:84c0a372a020	974	/* Auxiliary Bus Fault Status Register Definitions */
AnnaBridge	167:84c0a372a020	975	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
AnnaBridge	167:84c0a372a020	976	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
AnnaBridge	167:84c0a372a020	977
AnnaBridge	167:84c0a372a020	978	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
AnnaBridge	167:84c0a372a020	979	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
AnnaBridge	167:84c0a372a020	980
AnnaBridge	167:84c0a372a020	981	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
AnnaBridge	167:84c0a372a020	982	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
AnnaBridge	167:84c0a372a020	983
AnnaBridge	167:84c0a372a020	984	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
AnnaBridge	167:84c0a372a020	985	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
AnnaBridge	167:84c0a372a020	986
AnnaBridge	167:84c0a372a020	987	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
AnnaBridge	167:84c0a372a020	988	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
AnnaBridge	167:84c0a372a020	989
AnnaBridge	167:84c0a372a020	990	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
AnnaBridge	167:84c0a372a020	991	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
AnnaBridge	167:84c0a372a020	992
AnnaBridge	167:84c0a372a020	993	/@} end of group CMSIS_SCB /
AnnaBridge	167:84c0a372a020	994
AnnaBridge	167:84c0a372a020	995
AnnaBridge	167:84c0a372a020	996	/**
AnnaBridge	167:84c0a372a020	997	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	998	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	167:84c0a372a020	999	\brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge	167:84c0a372a020	1000	@{
AnnaBridge	167:84c0a372a020	1001	*/
AnnaBridge	167:84c0a372a020	1002
AnnaBridge	167:84c0a372a020	1003	/**
AnnaBridge	167:84c0a372a020	1004	\brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge	167:84c0a372a020	1005	*/
AnnaBridge	167:84c0a372a020	1006	typedef struct
AnnaBridge	167:84c0a372a020	1007	{
AnnaBridge	167:84c0a372a020	1008	uint32_t RESERVED0[1U];
AnnaBridge	167:84c0a372a020	1009	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	167:84c0a372a020	1010	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
AnnaBridge	167:84c0a372a020	1011	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
AnnaBridge	167:84c0a372a020	1012	} SCnSCB_Type;
AnnaBridge	167:84c0a372a020	1013
AnnaBridge	167:84c0a372a020	1014	/* Interrupt Controller Type Register Definitions */
AnnaBridge	167:84c0a372a020	1015	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
AnnaBridge	167:84c0a372a020	1016	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
AnnaBridge	167:84c0a372a020	1017
AnnaBridge	167:84c0a372a020	1018	/@} end of group CMSIS_SCnotSCB /
AnnaBridge	167:84c0a372a020	1019
AnnaBridge	167:84c0a372a020	1020
AnnaBridge	167:84c0a372a020	1021	/**
AnnaBridge	167:84c0a372a020	1022	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1023	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	167:84c0a372a020	1024	\brief Type definitions for the System Timer Registers.
AnnaBridge	167:84c0a372a020	1025	@{
AnnaBridge	167:84c0a372a020	1026	*/
AnnaBridge	167:84c0a372a020	1027
AnnaBridge	167:84c0a372a020	1028	/**
AnnaBridge	167:84c0a372a020	1029	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	167:84c0a372a020	1030	*/
AnnaBridge	167:84c0a372a020	1031	typedef struct
AnnaBridge	167:84c0a372a020	1032	{
AnnaBridge	167:84c0a372a020	1033	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	167:84c0a372a020	1034	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	167:84c0a372a020	1035	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	167:84c0a372a020	1036	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	167:84c0a372a020	1037	} SysTick_Type;
AnnaBridge	167:84c0a372a020	1038
AnnaBridge	167:84c0a372a020	1039	/* SysTick Control / Status Register Definitions */
AnnaBridge	167:84c0a372a020	1040	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	167:84c0a372a020	1041	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	167:84c0a372a020	1042
AnnaBridge	167:84c0a372a020	1043	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	167:84c0a372a020	1044	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	167:84c0a372a020	1045
AnnaBridge	167:84c0a372a020	1046	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	167:84c0a372a020	1047	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	167:84c0a372a020	1048
AnnaBridge	167:84c0a372a020	1049	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	167:84c0a372a020	1050	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	167:84c0a372a020	1051
AnnaBridge	167:84c0a372a020	1052	/* SysTick Reload Register Definitions */
AnnaBridge	167:84c0a372a020	1053	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	167:84c0a372a020	1054	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	167:84c0a372a020	1055
AnnaBridge	167:84c0a372a020	1056	/* SysTick Current Register Definitions */
AnnaBridge	167:84c0a372a020	1057	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	167:84c0a372a020	1058	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	167:84c0a372a020	1059
AnnaBridge	167:84c0a372a020	1060	/* SysTick Calibration Register Definitions */
AnnaBridge	167:84c0a372a020	1061	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	167:84c0a372a020	1062	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	167:84c0a372a020	1063
AnnaBridge	167:84c0a372a020	1064	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	167:84c0a372a020	1065	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	167:84c0a372a020	1066
AnnaBridge	167:84c0a372a020	1067	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	167:84c0a372a020	1068	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	167:84c0a372a020	1069
AnnaBridge	167:84c0a372a020	1070	/@} end of group CMSIS_SysTick /
AnnaBridge	167:84c0a372a020	1071
AnnaBridge	167:84c0a372a020	1072
AnnaBridge	167:84c0a372a020	1073	/**
AnnaBridge	167:84c0a372a020	1074	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1075	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	167:84c0a372a020	1076	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge	167:84c0a372a020	1077	@{
AnnaBridge	167:84c0a372a020	1078	*/
AnnaBridge	167:84c0a372a020	1079
AnnaBridge	167:84c0a372a020	1080	/**
AnnaBridge	167:84c0a372a020	1081	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge	167:84c0a372a020	1082	*/
AnnaBridge	167:84c0a372a020	1083	typedef struct
AnnaBridge	167:84c0a372a020	1084	{
AnnaBridge	167:84c0a372a020	1085	__OM union
AnnaBridge	167:84c0a372a020	1086	{
AnnaBridge	167:84c0a372a020	1087	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	167:84c0a372a020	1088	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	167:84c0a372a020	1089	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	167:84c0a372a020	1090	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	167:84c0a372a020	1091	uint32_t RESERVED0[864U];
AnnaBridge	167:84c0a372a020	1092	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	167:84c0a372a020	1093	uint32_t RESERVED1[15U];
AnnaBridge	167:84c0a372a020	1094	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	167:84c0a372a020	1095	uint32_t RESERVED2[15U];
AnnaBridge	167:84c0a372a020	1096	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	167:84c0a372a020	1097	uint32_t RESERVED3[29U];
AnnaBridge	167:84c0a372a020	1098	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	167:84c0a372a020	1099	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	167:84c0a372a020	1100	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	167:84c0a372a020	1101	uint32_t RESERVED4[43U];
AnnaBridge	167:84c0a372a020	1102	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	167:84c0a372a020	1103	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	167:84c0a372a020	1104	uint32_t RESERVED5[1U];
AnnaBridge	167:84c0a372a020	1105	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
AnnaBridge	167:84c0a372a020	1106	uint32_t RESERVED6[4U];
AnnaBridge	167:84c0a372a020	1107	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	167:84c0a372a020	1108	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	167:84c0a372a020	1109	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	167:84c0a372a020	1110	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	167:84c0a372a020	1111	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	167:84c0a372a020	1112	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	167:84c0a372a020	1113	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	167:84c0a372a020	1114	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	167:84c0a372a020	1115	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	167:84c0a372a020	1116	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	167:84c0a372a020	1117	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	167:84c0a372a020	1118	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
AnnaBridge	167:84c0a372a020	1119	} ITM_Type;
AnnaBridge	167:84c0a372a020	1120
AnnaBridge	167:84c0a372a020	1121	/* ITM Stimulus Port Register Definitions */
AnnaBridge	167:84c0a372a020	1122	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
AnnaBridge	167:84c0a372a020	1123	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
AnnaBridge	167:84c0a372a020	1124
AnnaBridge	167:84c0a372a020	1125	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
AnnaBridge	167:84c0a372a020	1126	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
AnnaBridge	167:84c0a372a020	1127
AnnaBridge	167:84c0a372a020	1128	/* ITM Trace Privilege Register Definitions */
AnnaBridge	167:84c0a372a020	1129	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
Anna Bridge	169:a7c7b631e539	1130	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
AnnaBridge	167:84c0a372a020	1131
AnnaBridge	167:84c0a372a020	1132	/* ITM Trace Control Register Definitions */
AnnaBridge	167:84c0a372a020	1133	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
AnnaBridge	167:84c0a372a020	1134	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
AnnaBridge	167:84c0a372a020	1135
AnnaBridge	167:84c0a372a020	1136	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
AnnaBridge	167:84c0a372a020	1137	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
AnnaBridge	167:84c0a372a020	1138
AnnaBridge	167:84c0a372a020	1139	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
AnnaBridge	167:84c0a372a020	1140	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
AnnaBridge	167:84c0a372a020	1141
AnnaBridge	167:84c0a372a020	1142	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
AnnaBridge	167:84c0a372a020	1143	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
AnnaBridge	167:84c0a372a020	1144
AnnaBridge	167:84c0a372a020	1145	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
AnnaBridge	167:84c0a372a020	1146	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
AnnaBridge	167:84c0a372a020	1147
AnnaBridge	167:84c0a372a020	1148	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
AnnaBridge	167:84c0a372a020	1149	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
AnnaBridge	167:84c0a372a020	1150
AnnaBridge	167:84c0a372a020	1151	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
AnnaBridge	167:84c0a372a020	1152	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
AnnaBridge	167:84c0a372a020	1153
AnnaBridge	167:84c0a372a020	1154	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
AnnaBridge	167:84c0a372a020	1155	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
AnnaBridge	167:84c0a372a020	1156
AnnaBridge	167:84c0a372a020	1157	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
AnnaBridge	167:84c0a372a020	1158	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
AnnaBridge	167:84c0a372a020	1159
AnnaBridge	167:84c0a372a020	1160	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
AnnaBridge	167:84c0a372a020	1161	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
AnnaBridge	167:84c0a372a020	1162
AnnaBridge	167:84c0a372a020	1163	/* ITM Integration Write Register Definitions */
AnnaBridge	167:84c0a372a020	1164	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
AnnaBridge	167:84c0a372a020	1165	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
AnnaBridge	167:84c0a372a020	1166
AnnaBridge	167:84c0a372a020	1167	/* ITM Integration Read Register Definitions */
AnnaBridge	167:84c0a372a020	1168	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
AnnaBridge	167:84c0a372a020	1169	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
AnnaBridge	167:84c0a372a020	1170
AnnaBridge	167:84c0a372a020	1171	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	167:84c0a372a020	1172	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
AnnaBridge	167:84c0a372a020	1173	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
AnnaBridge	167:84c0a372a020	1174
AnnaBridge	167:84c0a372a020	1175	/* ITM Lock Status Register Definitions */
AnnaBridge	167:84c0a372a020	1176	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
AnnaBridge	167:84c0a372a020	1177	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
AnnaBridge	167:84c0a372a020	1178
AnnaBridge	167:84c0a372a020	1179	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
AnnaBridge	167:84c0a372a020	1180	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
AnnaBridge	167:84c0a372a020	1181
AnnaBridge	167:84c0a372a020	1182	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
AnnaBridge	167:84c0a372a020	1183	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
AnnaBridge	167:84c0a372a020	1184
AnnaBridge	167:84c0a372a020	1185	/@}/ /* end of group CMSIS_ITM */
AnnaBridge	167:84c0a372a020	1186
AnnaBridge	167:84c0a372a020	1187
AnnaBridge	167:84c0a372a020	1188	/**
AnnaBridge	167:84c0a372a020	1189	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1190	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	167:84c0a372a020	1191	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	167:84c0a372a020	1192	@{
AnnaBridge	167:84c0a372a020	1193	*/
AnnaBridge	167:84c0a372a020	1194
AnnaBridge	167:84c0a372a020	1195	/**
AnnaBridge	167:84c0a372a020	1196	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	167:84c0a372a020	1197	*/
AnnaBridge	167:84c0a372a020	1198	typedef struct
AnnaBridge	167:84c0a372a020	1199	{
AnnaBridge	167:84c0a372a020	1200	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	167:84c0a372a020	1201	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	167:84c0a372a020	1202	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	167:84c0a372a020	1203	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	167:84c0a372a020	1204	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	167:84c0a372a020	1205	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	167:84c0a372a020	1206	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	167:84c0a372a020	1207	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	167:84c0a372a020	1208	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	167:84c0a372a020	1209	uint32_t RESERVED1[1U];
AnnaBridge	167:84c0a372a020	1210	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	167:84c0a372a020	1211	uint32_t RESERVED2[1U];
AnnaBridge	167:84c0a372a020	1212	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	167:84c0a372a020	1213	uint32_t RESERVED3[1U];
AnnaBridge	167:84c0a372a020	1214	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	167:84c0a372a020	1215	uint32_t RESERVED4[1U];
AnnaBridge	167:84c0a372a020	1216	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	167:84c0a372a020	1217	uint32_t RESERVED5[1U];
AnnaBridge	167:84c0a372a020	1218	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	167:84c0a372a020	1219	uint32_t RESERVED6[1U];
AnnaBridge	167:84c0a372a020	1220	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	167:84c0a372a020	1221	uint32_t RESERVED7[1U];
AnnaBridge	167:84c0a372a020	1222	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	167:84c0a372a020	1223	uint32_t RESERVED8[1U];
AnnaBridge	167:84c0a372a020	1224	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
AnnaBridge	167:84c0a372a020	1225	uint32_t RESERVED9[1U];
AnnaBridge	167:84c0a372a020	1226	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
AnnaBridge	167:84c0a372a020	1227	uint32_t RESERVED10[1U];
AnnaBridge	167:84c0a372a020	1228	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
AnnaBridge	167:84c0a372a020	1229	uint32_t RESERVED11[1U];
AnnaBridge	167:84c0a372a020	1230	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
AnnaBridge	167:84c0a372a020	1231	uint32_t RESERVED12[1U];
AnnaBridge	167:84c0a372a020	1232	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
AnnaBridge	167:84c0a372a020	1233	uint32_t RESERVED13[1U];
AnnaBridge	167:84c0a372a020	1234	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
AnnaBridge	167:84c0a372a020	1235	uint32_t RESERVED14[1U];
AnnaBridge	167:84c0a372a020	1236	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
AnnaBridge	167:84c0a372a020	1237	uint32_t RESERVED15[1U];
AnnaBridge	167:84c0a372a020	1238	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
AnnaBridge	167:84c0a372a020	1239	uint32_t RESERVED16[1U];
AnnaBridge	167:84c0a372a020	1240	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
AnnaBridge	167:84c0a372a020	1241	uint32_t RESERVED17[1U];
AnnaBridge	167:84c0a372a020	1242	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
AnnaBridge	167:84c0a372a020	1243	uint32_t RESERVED18[1U];
AnnaBridge	167:84c0a372a020	1244	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
AnnaBridge	167:84c0a372a020	1245	uint32_t RESERVED19[1U];
AnnaBridge	167:84c0a372a020	1246	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
AnnaBridge	167:84c0a372a020	1247	uint32_t RESERVED20[1U];
AnnaBridge	167:84c0a372a020	1248	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
AnnaBridge	167:84c0a372a020	1249	uint32_t RESERVED21[1U];
AnnaBridge	167:84c0a372a020	1250	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
AnnaBridge	167:84c0a372a020	1251	uint32_t RESERVED22[1U];
AnnaBridge	167:84c0a372a020	1252	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
AnnaBridge	167:84c0a372a020	1253	uint32_t RESERVED23[1U];
AnnaBridge	167:84c0a372a020	1254	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
AnnaBridge	167:84c0a372a020	1255	uint32_t RESERVED24[1U];
AnnaBridge	167:84c0a372a020	1256	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
AnnaBridge	167:84c0a372a020	1257	uint32_t RESERVED25[1U];
AnnaBridge	167:84c0a372a020	1258	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
AnnaBridge	167:84c0a372a020	1259	uint32_t RESERVED26[1U];
AnnaBridge	167:84c0a372a020	1260	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
AnnaBridge	167:84c0a372a020	1261	uint32_t RESERVED27[1U];
AnnaBridge	167:84c0a372a020	1262	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
AnnaBridge	167:84c0a372a020	1263	uint32_t RESERVED28[1U];
AnnaBridge	167:84c0a372a020	1264	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
AnnaBridge	167:84c0a372a020	1265	uint32_t RESERVED29[1U];
AnnaBridge	167:84c0a372a020	1266	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
AnnaBridge	167:84c0a372a020	1267	uint32_t RESERVED30[1U];
AnnaBridge	167:84c0a372a020	1268	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
AnnaBridge	167:84c0a372a020	1269	uint32_t RESERVED31[1U];
AnnaBridge	167:84c0a372a020	1270	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
AnnaBridge	167:84c0a372a020	1271	uint32_t RESERVED32[934U];
AnnaBridge	167:84c0a372a020	1272	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
AnnaBridge	167:84c0a372a020	1273	uint32_t RESERVED33[1U];
AnnaBridge	167:84c0a372a020	1274	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
AnnaBridge	167:84c0a372a020	1275	} DWT_Type;
AnnaBridge	167:84c0a372a020	1276
AnnaBridge	167:84c0a372a020	1277	/* DWT Control Register Definitions */
AnnaBridge	167:84c0a372a020	1278	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	167:84c0a372a020	1279	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	167:84c0a372a020	1280
AnnaBridge	167:84c0a372a020	1281	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	167:84c0a372a020	1282	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	167:84c0a372a020	1283
AnnaBridge	167:84c0a372a020	1284	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	167:84c0a372a020	1285	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	167:84c0a372a020	1286
AnnaBridge	167:84c0a372a020	1287	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	167:84c0a372a020	1288	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	167:84c0a372a020	1289
AnnaBridge	167:84c0a372a020	1290	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	167:84c0a372a020	1291	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	167:84c0a372a020	1292
AnnaBridge	167:84c0a372a020	1293	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
AnnaBridge	167:84c0a372a020	1294	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
AnnaBridge	167:84c0a372a020	1295
AnnaBridge	167:84c0a372a020	1296	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
AnnaBridge	167:84c0a372a020	1297	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
AnnaBridge	167:84c0a372a020	1298
AnnaBridge	167:84c0a372a020	1299	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
AnnaBridge	167:84c0a372a020	1300	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
AnnaBridge	167:84c0a372a020	1301
AnnaBridge	167:84c0a372a020	1302	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
AnnaBridge	167:84c0a372a020	1303	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
AnnaBridge	167:84c0a372a020	1304
AnnaBridge	167:84c0a372a020	1305	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
AnnaBridge	167:84c0a372a020	1306	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
AnnaBridge	167:84c0a372a020	1307
AnnaBridge	167:84c0a372a020	1308	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
AnnaBridge	167:84c0a372a020	1309	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
AnnaBridge	167:84c0a372a020	1310
AnnaBridge	167:84c0a372a020	1311	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
AnnaBridge	167:84c0a372a020	1312	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
AnnaBridge	167:84c0a372a020	1313
AnnaBridge	167:84c0a372a020	1314	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
AnnaBridge	167:84c0a372a020	1315	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
AnnaBridge	167:84c0a372a020	1316
AnnaBridge	167:84c0a372a020	1317	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
AnnaBridge	167:84c0a372a020	1318	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
AnnaBridge	167:84c0a372a020	1319
AnnaBridge	167:84c0a372a020	1320	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
AnnaBridge	167:84c0a372a020	1321	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
AnnaBridge	167:84c0a372a020	1322
AnnaBridge	167:84c0a372a020	1323	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
AnnaBridge	167:84c0a372a020	1324	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
AnnaBridge	167:84c0a372a020	1325
AnnaBridge	167:84c0a372a020	1326	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
AnnaBridge	167:84c0a372a020	1327	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
AnnaBridge	167:84c0a372a020	1328
AnnaBridge	167:84c0a372a020	1329	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
AnnaBridge	167:84c0a372a020	1330	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
AnnaBridge	167:84c0a372a020	1331
AnnaBridge	167:84c0a372a020	1332	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
AnnaBridge	167:84c0a372a020	1333	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
AnnaBridge	167:84c0a372a020	1334
AnnaBridge	167:84c0a372a020	1335	/* DWT CPI Count Register Definitions */
AnnaBridge	167:84c0a372a020	1336	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
AnnaBridge	167:84c0a372a020	1337	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
AnnaBridge	167:84c0a372a020	1338
AnnaBridge	167:84c0a372a020	1339	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	167:84c0a372a020	1340	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
AnnaBridge	167:84c0a372a020	1341	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
AnnaBridge	167:84c0a372a020	1342
AnnaBridge	167:84c0a372a020	1343	/* DWT Sleep Count Register Definitions */
AnnaBridge	167:84c0a372a020	1344	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
AnnaBridge	167:84c0a372a020	1345	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
AnnaBridge	167:84c0a372a020	1346
AnnaBridge	167:84c0a372a020	1347	/* DWT LSU Count Register Definitions */
AnnaBridge	167:84c0a372a020	1348	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
AnnaBridge	167:84c0a372a020	1349	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
AnnaBridge	167:84c0a372a020	1350
AnnaBridge	167:84c0a372a020	1351	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	167:84c0a372a020	1352	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
AnnaBridge	167:84c0a372a020	1353	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
AnnaBridge	167:84c0a372a020	1354
AnnaBridge	167:84c0a372a020	1355	/* DWT Comparator Function Register Definitions */
AnnaBridge	167:84c0a372a020	1356	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
AnnaBridge	167:84c0a372a020	1357	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
AnnaBridge	167:84c0a372a020	1358
AnnaBridge	167:84c0a372a020	1359	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	167:84c0a372a020	1360	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	167:84c0a372a020	1361
AnnaBridge	167:84c0a372a020	1362	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	167:84c0a372a020	1363	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	167:84c0a372a020	1364
AnnaBridge	167:84c0a372a020	1365	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
AnnaBridge	167:84c0a372a020	1366	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
AnnaBridge	167:84c0a372a020	1367
AnnaBridge	167:84c0a372a020	1368	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
AnnaBridge	167:84c0a372a020	1369	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
AnnaBridge	167:84c0a372a020	1370
AnnaBridge	167:84c0a372a020	1371	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	167:84c0a372a020	1372
AnnaBridge	167:84c0a372a020	1373
AnnaBridge	167:84c0a372a020	1374	/**
AnnaBridge	167:84c0a372a020	1375	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1376	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	167:84c0a372a020	1377	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	167:84c0a372a020	1378	@{
AnnaBridge	167:84c0a372a020	1379	*/
AnnaBridge	167:84c0a372a020	1380
AnnaBridge	167:84c0a372a020	1381	/**
AnnaBridge	167:84c0a372a020	1382	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	167:84c0a372a020	1383	*/
AnnaBridge	167:84c0a372a020	1384	typedef struct
AnnaBridge	167:84c0a372a020	1385	{
AnnaBridge	167:84c0a372a020	1386	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	167:84c0a372a020	1387	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	167:84c0a372a020	1388	uint32_t RESERVED0[2U];
AnnaBridge	167:84c0a372a020	1389	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	167:84c0a372a020	1390	uint32_t RESERVED1[55U];
AnnaBridge	167:84c0a372a020	1391	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	167:84c0a372a020	1392	uint32_t RESERVED2[131U];
AnnaBridge	167:84c0a372a020	1393	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	167:84c0a372a020	1394	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	167:84c0a372a020	1395	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	167:84c0a372a020	1396	uint32_t RESERVED3[759U];
AnnaBridge	167:84c0a372a020	1397	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	167:84c0a372a020	1398	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	167:84c0a372a020	1399	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	167:84c0a372a020	1400	uint32_t RESERVED4[1U];
AnnaBridge	167:84c0a372a020	1401	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	167:84c0a372a020	1402	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	167:84c0a372a020	1403	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	167:84c0a372a020	1404	uint32_t RESERVED5[39U];
AnnaBridge	167:84c0a372a020	1405	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	167:84c0a372a020	1406	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	167:84c0a372a020	1407	uint32_t RESERVED7[8U];
AnnaBridge	167:84c0a372a020	1408	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	167:84c0a372a020	1409	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	167:84c0a372a020	1410	} TPI_Type;
AnnaBridge	167:84c0a372a020	1411
AnnaBridge	167:84c0a372a020	1412	/* TPI Asynchronous Clock Prescaler Register Definitions */
Anna Bridge	169:a7c7b631e539	1413	#define TPI_ACPR_PRESCALER_Pos 0U /!< @Deprecated TPI ACPR: PRESCALER Position /
Anna Bridge	169:a7c7b631e539	1414	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< @Deprecated TPI ACPR: PRESCALER Mask /
Anna Bridge	169:a7c7b631e539	1415
Anna Bridge	169:a7c7b631e539	1416	#define TPI_ACPR_SWOSCALER_Pos 0U /!< TPI ACPR: SWOSCALER Position /
Anna Bridge	169:a7c7b631e539	1417	#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/) /!< TPI ACPR: SWOSCALER Mask /
AnnaBridge	167:84c0a372a020	1418
AnnaBridge	167:84c0a372a020	1419	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	167:84c0a372a020	1420	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	167:84c0a372a020	1421	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	167:84c0a372a020	1422
AnnaBridge	167:84c0a372a020	1423	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	167:84c0a372a020	1424	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	167:84c0a372a020	1425	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	167:84c0a372a020	1426
AnnaBridge	167:84c0a372a020	1427	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	167:84c0a372a020	1428	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	167:84c0a372a020	1429
AnnaBridge	167:84c0a372a020	1430	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	167:84c0a372a020	1431	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	167:84c0a372a020	1432
AnnaBridge	167:84c0a372a020	1433	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	167:84c0a372a020	1434	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	167:84c0a372a020	1435
AnnaBridge	167:84c0a372a020	1436	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	167:84c0a372a020	1437	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	167:84c0a372a020	1438	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	167:84c0a372a020	1439
AnnaBridge	167:84c0a372a020	1440	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	167:84c0a372a020	1441	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	167:84c0a372a020	1442
AnnaBridge	167:84c0a372a020	1443	/* TPI TRIGGER Register Definitions */
AnnaBridge	167:84c0a372a020	1444	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	167:84c0a372a020	1445	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	167:84c0a372a020	1446
AnnaBridge	167:84c0a372a020	1447	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	167:84c0a372a020	1448	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	167:84c0a372a020	1449	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	167:84c0a372a020	1450
AnnaBridge	167:84c0a372a020	1451	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	167:84c0a372a020	1452	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	167:84c0a372a020	1453
AnnaBridge	167:84c0a372a020	1454	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	167:84c0a372a020	1455	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	167:84c0a372a020	1456
AnnaBridge	167:84c0a372a020	1457	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	167:84c0a372a020	1458	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	167:84c0a372a020	1459
AnnaBridge	167:84c0a372a020	1460	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
AnnaBridge	167:84c0a372a020	1461	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	167:84c0a372a020	1462
AnnaBridge	167:84c0a372a020	1463	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
AnnaBridge	167:84c0a372a020	1464	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	167:84c0a372a020	1465
AnnaBridge	167:84c0a372a020	1466	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
AnnaBridge	167:84c0a372a020	1467	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	167:84c0a372a020	1468
AnnaBridge	167:84c0a372a020	1469	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	167:84c0a372a020	1470	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
AnnaBridge	167:84c0a372a020	1471	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
AnnaBridge	167:84c0a372a020	1472
AnnaBridge	167:84c0a372a020	1473	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	167:84c0a372a020	1474	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	167:84c0a372a020	1475	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	167:84c0a372a020	1476
AnnaBridge	167:84c0a372a020	1477	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	167:84c0a372a020	1478	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	167:84c0a372a020	1479
AnnaBridge	167:84c0a372a020	1480	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	167:84c0a372a020	1481	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	167:84c0a372a020	1482
AnnaBridge	167:84c0a372a020	1483	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	167:84c0a372a020	1484	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	167:84c0a372a020	1485
AnnaBridge	167:84c0a372a020	1486	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
AnnaBridge	167:84c0a372a020	1487	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	167:84c0a372a020	1488
AnnaBridge	167:84c0a372a020	1489	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
AnnaBridge	167:84c0a372a020	1490	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	167:84c0a372a020	1491
AnnaBridge	167:84c0a372a020	1492	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
AnnaBridge	167:84c0a372a020	1493	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	167:84c0a372a020	1494
AnnaBridge	167:84c0a372a020	1495	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	167:84c0a372a020	1496	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
AnnaBridge	167:84c0a372a020	1497	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
AnnaBridge	167:84c0a372a020	1498
AnnaBridge	167:84c0a372a020	1499	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	167:84c0a372a020	1500	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	167:84c0a372a020	1501	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	167:84c0a372a020	1502
AnnaBridge	167:84c0a372a020	1503	/* TPI DEVID Register Definitions */
AnnaBridge	167:84c0a372a020	1504	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	167:84c0a372a020	1505	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	167:84c0a372a020	1506
AnnaBridge	167:84c0a372a020	1507	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	167:84c0a372a020	1508	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	167:84c0a372a020	1509
AnnaBridge	167:84c0a372a020	1510	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	167:84c0a372a020	1511	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	167:84c0a372a020	1512
AnnaBridge	167:84c0a372a020	1513	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
AnnaBridge	167:84c0a372a020	1514	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	167:84c0a372a020	1515
AnnaBridge	167:84c0a372a020	1516	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	167:84c0a372a020	1517	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	167:84c0a372a020	1518
AnnaBridge	167:84c0a372a020	1519	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	167:84c0a372a020	1520	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	167:84c0a372a020	1521
AnnaBridge	167:84c0a372a020	1522	/* TPI DEVTYPE Register Definitions */
AnnaBridge	167:84c0a372a020	1523	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	167:84c0a372a020	1524	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	167:84c0a372a020	1525
AnnaBridge	167:84c0a372a020	1526	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	167:84c0a372a020	1527	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	167:84c0a372a020	1528
AnnaBridge	167:84c0a372a020	1529	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	167:84c0a372a020	1530
AnnaBridge	167:84c0a372a020	1531
AnnaBridge	167:84c0a372a020	1532	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	1533	/**
AnnaBridge	167:84c0a372a020	1534	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1535	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	167:84c0a372a020	1536	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	167:84c0a372a020	1537	@{
AnnaBridge	167:84c0a372a020	1538	*/
AnnaBridge	167:84c0a372a020	1539
AnnaBridge	167:84c0a372a020	1540	/**
AnnaBridge	167:84c0a372a020	1541	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	167:84c0a372a020	1542	*/
AnnaBridge	167:84c0a372a020	1543	typedef struct
AnnaBridge	167:84c0a372a020	1544	{
AnnaBridge	167:84c0a372a020	1545	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	167:84c0a372a020	1546	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	167:84c0a372a020	1547	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
AnnaBridge	167:84c0a372a020	1548	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	167:84c0a372a020	1549	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
AnnaBridge	167:84c0a372a020	1550	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
AnnaBridge	167:84c0a372a020	1551	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
AnnaBridge	167:84c0a372a020	1552	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
AnnaBridge	167:84c0a372a020	1553	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
AnnaBridge	167:84c0a372a020	1554	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
AnnaBridge	167:84c0a372a020	1555	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
AnnaBridge	167:84c0a372a020	1556	uint32_t RESERVED0[1];
AnnaBridge	167:84c0a372a020	1557	union {
AnnaBridge	167:84c0a372a020	1558	__IOM uint32_t MAIR[2];
AnnaBridge	167:84c0a372a020	1559	struct {
AnnaBridge	167:84c0a372a020	1560	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
AnnaBridge	167:84c0a372a020	1561	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
AnnaBridge	167:84c0a372a020	1562	};
AnnaBridge	167:84c0a372a020	1563	};
AnnaBridge	167:84c0a372a020	1564	} MPU_Type;
AnnaBridge	167:84c0a372a020	1565
AnnaBridge	167:84c0a372a020	1566	#define MPU_TYPE_RALIASES 4U
AnnaBridge	167:84c0a372a020	1567
AnnaBridge	167:84c0a372a020	1568	/* MPU Type Register Definitions */
AnnaBridge	167:84c0a372a020	1569	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	167:84c0a372a020	1570	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	167:84c0a372a020	1571
AnnaBridge	167:84c0a372a020	1572	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	167:84c0a372a020	1573	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	167:84c0a372a020	1574
AnnaBridge	167:84c0a372a020	1575	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	167:84c0a372a020	1576	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	167:84c0a372a020	1577
AnnaBridge	167:84c0a372a020	1578	/* MPU Control Register Definitions */
AnnaBridge	167:84c0a372a020	1579	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	167:84c0a372a020	1580	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	167:84c0a372a020	1581
AnnaBridge	167:84c0a372a020	1582	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	167:84c0a372a020	1583	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	167:84c0a372a020	1584
AnnaBridge	167:84c0a372a020	1585	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	167:84c0a372a020	1586	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	167:84c0a372a020	1587
AnnaBridge	167:84c0a372a020	1588	/* MPU Region Number Register Definitions */
AnnaBridge	167:84c0a372a020	1589	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	167:84c0a372a020	1590	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	167:84c0a372a020	1591
AnnaBridge	167:84c0a372a020	1592	/* MPU Region Base Address Register Definitions */
AnnaBridge	167:84c0a372a020	1593	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: ADDR Position /
AnnaBridge	167:84c0a372a020	1594	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: ADDR Mask /
AnnaBridge	167:84c0a372a020	1595
AnnaBridge	167:84c0a372a020	1596	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
AnnaBridge	167:84c0a372a020	1597	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
AnnaBridge	167:84c0a372a020	1598
AnnaBridge	167:84c0a372a020	1599	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
AnnaBridge	167:84c0a372a020	1600	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
AnnaBridge	167:84c0a372a020	1601
AnnaBridge	167:84c0a372a020	1602	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
AnnaBridge	167:84c0a372a020	1603	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
AnnaBridge	167:84c0a372a020	1604
AnnaBridge	167:84c0a372a020	1605	/* MPU Region Limit Address Register Definitions */
AnnaBridge	167:84c0a372a020	1606	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
AnnaBridge	167:84c0a372a020	1607	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
AnnaBridge	167:84c0a372a020	1608
AnnaBridge	167:84c0a372a020	1609	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
AnnaBridge	167:84c0a372a020	1610	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
AnnaBridge	167:84c0a372a020	1611
AnnaBridge	167:84c0a372a020	1612	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
AnnaBridge	167:84c0a372a020	1613	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
AnnaBridge	167:84c0a372a020	1614
AnnaBridge	167:84c0a372a020	1615	/* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge	167:84c0a372a020	1616	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
AnnaBridge	167:84c0a372a020	1617	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
AnnaBridge	167:84c0a372a020	1618
AnnaBridge	167:84c0a372a020	1619	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
AnnaBridge	167:84c0a372a020	1620	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
AnnaBridge	167:84c0a372a020	1621
AnnaBridge	167:84c0a372a020	1622	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
AnnaBridge	167:84c0a372a020	1623	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
AnnaBridge	167:84c0a372a020	1624
AnnaBridge	167:84c0a372a020	1625	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
AnnaBridge	167:84c0a372a020	1626	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
AnnaBridge	167:84c0a372a020	1627
AnnaBridge	167:84c0a372a020	1628	/* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge	167:84c0a372a020	1629	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
AnnaBridge	167:84c0a372a020	1630	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
AnnaBridge	167:84c0a372a020	1631
AnnaBridge	167:84c0a372a020	1632	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
AnnaBridge	167:84c0a372a020	1633	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
AnnaBridge	167:84c0a372a020	1634
AnnaBridge	167:84c0a372a020	1635	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
AnnaBridge	167:84c0a372a020	1636	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
AnnaBridge	167:84c0a372a020	1637
AnnaBridge	167:84c0a372a020	1638	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
AnnaBridge	167:84c0a372a020	1639	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
AnnaBridge	167:84c0a372a020	1640
AnnaBridge	167:84c0a372a020	1641	/@} end of group CMSIS_MPU /
AnnaBridge	167:84c0a372a020	1642	#endif
AnnaBridge	167:84c0a372a020	1643
AnnaBridge	167:84c0a372a020	1644
AnnaBridge	167:84c0a372a020	1645	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:84c0a372a020	1646	/**
AnnaBridge	167:84c0a372a020	1647	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1648	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge	167:84c0a372a020	1649	\brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge	167:84c0a372a020	1650	@{
AnnaBridge	167:84c0a372a020	1651	*/
AnnaBridge	167:84c0a372a020	1652
AnnaBridge	167:84c0a372a020	1653	/**
AnnaBridge	167:84c0a372a020	1654	\brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge	167:84c0a372a020	1655	*/
AnnaBridge	167:84c0a372a020	1656	typedef struct
AnnaBridge	167:84c0a372a020	1657	{
AnnaBridge	167:84c0a372a020	1658	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
AnnaBridge	167:84c0a372a020	1659	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
AnnaBridge	167:84c0a372a020	1660	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	1661	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
AnnaBridge	167:84c0a372a020	1662	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
AnnaBridge	167:84c0a372a020	1663	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
AnnaBridge	167:84c0a372a020	1664	#else
AnnaBridge	167:84c0a372a020	1665	uint32_t RESERVED0[3];
AnnaBridge	167:84c0a372a020	1666	#endif
AnnaBridge	167:84c0a372a020	1667	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
AnnaBridge	167:84c0a372a020	1668	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
AnnaBridge	167:84c0a372a020	1669	} SAU_Type;
AnnaBridge	167:84c0a372a020	1670
AnnaBridge	167:84c0a372a020	1671	/* SAU Control Register Definitions */
AnnaBridge	167:84c0a372a020	1672	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
AnnaBridge	167:84c0a372a020	1673	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
AnnaBridge	167:84c0a372a020	1674
AnnaBridge	167:84c0a372a020	1675	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
AnnaBridge	167:84c0a372a020	1676	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
AnnaBridge	167:84c0a372a020	1677
AnnaBridge	167:84c0a372a020	1678	/* SAU Type Register Definitions */
AnnaBridge	167:84c0a372a020	1679	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
AnnaBridge	167:84c0a372a020	1680	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
AnnaBridge	167:84c0a372a020	1681
AnnaBridge	167:84c0a372a020	1682	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	1683	/* SAU Region Number Register Definitions */
AnnaBridge	167:84c0a372a020	1684	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
AnnaBridge	167:84c0a372a020	1685	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
AnnaBridge	167:84c0a372a020	1686
AnnaBridge	167:84c0a372a020	1687	/* SAU Region Base Address Register Definitions */
AnnaBridge	167:84c0a372a020	1688	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
AnnaBridge	167:84c0a372a020	1689	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
AnnaBridge	167:84c0a372a020	1690
AnnaBridge	167:84c0a372a020	1691	/* SAU Region Limit Address Register Definitions */
AnnaBridge	167:84c0a372a020	1692	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
AnnaBridge	167:84c0a372a020	1693	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
AnnaBridge	167:84c0a372a020	1694
AnnaBridge	167:84c0a372a020	1695	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
AnnaBridge	167:84c0a372a020	1696	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
AnnaBridge	167:84c0a372a020	1697
AnnaBridge	167:84c0a372a020	1698	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
AnnaBridge	167:84c0a372a020	1699	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
AnnaBridge	167:84c0a372a020	1700
AnnaBridge	167:84c0a372a020	1701	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge	167:84c0a372a020	1702
AnnaBridge	167:84c0a372a020	1703	/* Secure Fault Status Register Definitions */
AnnaBridge	167:84c0a372a020	1704	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
AnnaBridge	167:84c0a372a020	1705	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
AnnaBridge	167:84c0a372a020	1706
AnnaBridge	167:84c0a372a020	1707	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
AnnaBridge	167:84c0a372a020	1708	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
AnnaBridge	167:84c0a372a020	1709
AnnaBridge	167:84c0a372a020	1710	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
AnnaBridge	167:84c0a372a020	1711	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
AnnaBridge	167:84c0a372a020	1712
AnnaBridge	167:84c0a372a020	1713	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
AnnaBridge	167:84c0a372a020	1714	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
AnnaBridge	167:84c0a372a020	1715
AnnaBridge	167:84c0a372a020	1716	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
AnnaBridge	167:84c0a372a020	1717	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
AnnaBridge	167:84c0a372a020	1718
AnnaBridge	167:84c0a372a020	1719	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
AnnaBridge	167:84c0a372a020	1720	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
AnnaBridge	167:84c0a372a020	1721
AnnaBridge	167:84c0a372a020	1722	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
AnnaBridge	167:84c0a372a020	1723	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
AnnaBridge	167:84c0a372a020	1724
AnnaBridge	167:84c0a372a020	1725	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
AnnaBridge	167:84c0a372a020	1726	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
AnnaBridge	167:84c0a372a020	1727
AnnaBridge	167:84c0a372a020	1728	/@} end of group CMSIS_SAU /
AnnaBridge	167:84c0a372a020	1729	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:84c0a372a020	1730
AnnaBridge	167:84c0a372a020	1731
AnnaBridge	167:84c0a372a020	1732	/**
AnnaBridge	167:84c0a372a020	1733	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1734	\defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge	167:84c0a372a020	1735	\brief Type definitions for the Floating Point Unit (FPU)
AnnaBridge	167:84c0a372a020	1736	@{
AnnaBridge	167:84c0a372a020	1737	*/
AnnaBridge	167:84c0a372a020	1738
AnnaBridge	167:84c0a372a020	1739	/**
AnnaBridge	167:84c0a372a020	1740	\brief Structure type to access the Floating Point Unit (FPU).
AnnaBridge	167:84c0a372a020	1741	*/
AnnaBridge	167:84c0a372a020	1742	typedef struct
AnnaBridge	167:84c0a372a020	1743	{
AnnaBridge	167:84c0a372a020	1744	uint32_t RESERVED0[1U];
AnnaBridge	167:84c0a372a020	1745	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
AnnaBridge	167:84c0a372a020	1746	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
AnnaBridge	167:84c0a372a020	1747	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
AnnaBridge	167:84c0a372a020	1748	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
AnnaBridge	167:84c0a372a020	1749	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
AnnaBridge	167:84c0a372a020	1750	} FPU_Type;
AnnaBridge	167:84c0a372a020	1751
AnnaBridge	167:84c0a372a020	1752	/* Floating-Point Context Control Register Definitions */
AnnaBridge	167:84c0a372a020	1753	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
AnnaBridge	167:84c0a372a020	1754	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
AnnaBridge	167:84c0a372a020	1755
AnnaBridge	167:84c0a372a020	1756	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
AnnaBridge	167:84c0a372a020	1757	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
AnnaBridge	167:84c0a372a020	1758
AnnaBridge	167:84c0a372a020	1759	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
AnnaBridge	167:84c0a372a020	1760	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
AnnaBridge	167:84c0a372a020	1761
AnnaBridge	167:84c0a372a020	1762	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
AnnaBridge	167:84c0a372a020	1763	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
AnnaBridge	167:84c0a372a020	1764
AnnaBridge	167:84c0a372a020	1765	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
AnnaBridge	167:84c0a372a020	1766	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
AnnaBridge	167:84c0a372a020	1767
AnnaBridge	167:84c0a372a020	1768	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
AnnaBridge	167:84c0a372a020	1769	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
AnnaBridge	167:84c0a372a020	1770
AnnaBridge	167:84c0a372a020	1771	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
AnnaBridge	167:84c0a372a020	1772	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
AnnaBridge	167:84c0a372a020	1773
AnnaBridge	167:84c0a372a020	1774	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
AnnaBridge	167:84c0a372a020	1775	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
AnnaBridge	167:84c0a372a020	1776
AnnaBridge	167:84c0a372a020	1777	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
AnnaBridge	167:84c0a372a020	1778	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
AnnaBridge	167:84c0a372a020	1779
AnnaBridge	167:84c0a372a020	1780	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
AnnaBridge	167:84c0a372a020	1781	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
AnnaBridge	167:84c0a372a020	1782
AnnaBridge	167:84c0a372a020	1783	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
AnnaBridge	167:84c0a372a020	1784	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
AnnaBridge	167:84c0a372a020	1785
AnnaBridge	167:84c0a372a020	1786	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
AnnaBridge	167:84c0a372a020	1787	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
AnnaBridge	167:84c0a372a020	1788
AnnaBridge	167:84c0a372a020	1789	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
AnnaBridge	167:84c0a372a020	1790	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
AnnaBridge	167:84c0a372a020	1791
AnnaBridge	167:84c0a372a020	1792	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
AnnaBridge	167:84c0a372a020	1793	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
AnnaBridge	167:84c0a372a020	1794
AnnaBridge	167:84c0a372a020	1795	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
AnnaBridge	167:84c0a372a020	1796	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
AnnaBridge	167:84c0a372a020	1797
AnnaBridge	167:84c0a372a020	1798	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
AnnaBridge	167:84c0a372a020	1799	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
AnnaBridge	167:84c0a372a020	1800
AnnaBridge	167:84c0a372a020	1801	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
AnnaBridge	167:84c0a372a020	1802	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
AnnaBridge	167:84c0a372a020	1803
AnnaBridge	167:84c0a372a020	1804	/* Floating-Point Context Address Register Definitions */
AnnaBridge	167:84c0a372a020	1805	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
AnnaBridge	167:84c0a372a020	1806	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
AnnaBridge	167:84c0a372a020	1807
AnnaBridge	167:84c0a372a020	1808	/* Floating-Point Default Status Control Register Definitions */
AnnaBridge	167:84c0a372a020	1809	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
AnnaBridge	167:84c0a372a020	1810	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
AnnaBridge	167:84c0a372a020	1811
AnnaBridge	167:84c0a372a020	1812	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
AnnaBridge	167:84c0a372a020	1813	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
AnnaBridge	167:84c0a372a020	1814
AnnaBridge	167:84c0a372a020	1815	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
AnnaBridge	167:84c0a372a020	1816	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
AnnaBridge	167:84c0a372a020	1817
AnnaBridge	167:84c0a372a020	1818	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
AnnaBridge	167:84c0a372a020	1819	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
AnnaBridge	167:84c0a372a020	1820
AnnaBridge	167:84c0a372a020	1821	/* Media and FP Feature Register 0 Definitions */
AnnaBridge	167:84c0a372a020	1822	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
AnnaBridge	167:84c0a372a020	1823	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
AnnaBridge	167:84c0a372a020	1824
AnnaBridge	167:84c0a372a020	1825	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
AnnaBridge	167:84c0a372a020	1826	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
AnnaBridge	167:84c0a372a020	1827
AnnaBridge	167:84c0a372a020	1828	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
AnnaBridge	167:84c0a372a020	1829	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
AnnaBridge	167:84c0a372a020	1830
AnnaBridge	167:84c0a372a020	1831	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
AnnaBridge	167:84c0a372a020	1832	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
AnnaBridge	167:84c0a372a020	1833
AnnaBridge	167:84c0a372a020	1834	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
AnnaBridge	167:84c0a372a020	1835	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
AnnaBridge	167:84c0a372a020	1836
AnnaBridge	167:84c0a372a020	1837	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
AnnaBridge	167:84c0a372a020	1838	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
AnnaBridge	167:84c0a372a020	1839
AnnaBridge	167:84c0a372a020	1840	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
AnnaBridge	167:84c0a372a020	1841	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
AnnaBridge	167:84c0a372a020	1842
AnnaBridge	167:84c0a372a020	1843	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
AnnaBridge	167:84c0a372a020	1844	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
AnnaBridge	167:84c0a372a020	1845
AnnaBridge	167:84c0a372a020	1846	/* Media and FP Feature Register 1 Definitions */
AnnaBridge	167:84c0a372a020	1847	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
AnnaBridge	167:84c0a372a020	1848	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
AnnaBridge	167:84c0a372a020	1849
AnnaBridge	167:84c0a372a020	1850	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
AnnaBridge	167:84c0a372a020	1851	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
AnnaBridge	167:84c0a372a020	1852
AnnaBridge	167:84c0a372a020	1853	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
AnnaBridge	167:84c0a372a020	1854	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
AnnaBridge	167:84c0a372a020	1855
AnnaBridge	167:84c0a372a020	1856	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
AnnaBridge	167:84c0a372a020	1857	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
AnnaBridge	167:84c0a372a020	1858
AnnaBridge	167:84c0a372a020	1859	/@} end of group CMSIS_FPU /
AnnaBridge	167:84c0a372a020	1860
AnnaBridge	167:84c0a372a020	1861
AnnaBridge	167:84c0a372a020	1862	/**
AnnaBridge	167:84c0a372a020	1863	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1864	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	167:84c0a372a020	1865	\brief Type definitions for the Core Debug Registers
AnnaBridge	167:84c0a372a020	1866	@{
AnnaBridge	167:84c0a372a020	1867	*/
AnnaBridge	167:84c0a372a020	1868
AnnaBridge	167:84c0a372a020	1869	/**
AnnaBridge	167:84c0a372a020	1870	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	167:84c0a372a020	1871	*/
AnnaBridge	167:84c0a372a020	1872	typedef struct
AnnaBridge	167:84c0a372a020	1873	{
AnnaBridge	167:84c0a372a020	1874	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	167:84c0a372a020	1875	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	167:84c0a372a020	1876	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	167:84c0a372a020	1877	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	167:84c0a372a020	1878	uint32_t RESERVED4[1U];
AnnaBridge	167:84c0a372a020	1879	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
AnnaBridge	167:84c0a372a020	1880	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
AnnaBridge	167:84c0a372a020	1881	} CoreDebug_Type;
AnnaBridge	167:84c0a372a020	1882
AnnaBridge	167:84c0a372a020	1883	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	167:84c0a372a020	1884	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	167:84c0a372a020	1885	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	167:84c0a372a020	1886
AnnaBridge	167:84c0a372a020	1887	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
AnnaBridge	167:84c0a372a020	1888	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
AnnaBridge	167:84c0a372a020	1889
AnnaBridge	167:84c0a372a020	1890	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	167:84c0a372a020	1891	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	167:84c0a372a020	1892
AnnaBridge	167:84c0a372a020	1893	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	167:84c0a372a020	1894	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	167:84c0a372a020	1895
AnnaBridge	167:84c0a372a020	1896	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	167:84c0a372a020	1897	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	167:84c0a372a020	1898
AnnaBridge	167:84c0a372a020	1899	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	167:84c0a372a020	1900	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	167:84c0a372a020	1901
AnnaBridge	167:84c0a372a020	1902	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	167:84c0a372a020	1903	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	167:84c0a372a020	1904
AnnaBridge	167:84c0a372a020	1905	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	167:84c0a372a020	1906	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	167:84c0a372a020	1907
AnnaBridge	167:84c0a372a020	1908	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
AnnaBridge	167:84c0a372a020	1909	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
AnnaBridge	167:84c0a372a020	1910
AnnaBridge	167:84c0a372a020	1911	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	167:84c0a372a020	1912	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	167:84c0a372a020	1913
AnnaBridge	167:84c0a372a020	1914	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	167:84c0a372a020	1915	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	167:84c0a372a020	1916
AnnaBridge	167:84c0a372a020	1917	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	167:84c0a372a020	1918	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	167:84c0a372a020	1919
AnnaBridge	167:84c0a372a020	1920	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	167:84c0a372a020	1921	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	167:84c0a372a020	1922
AnnaBridge	167:84c0a372a020	1923	/* Debug Core Register Selector Register Definitions */
AnnaBridge	167:84c0a372a020	1924	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	167:84c0a372a020	1925	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	167:84c0a372a020	1926
AnnaBridge	167:84c0a372a020	1927	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	167:84c0a372a020	1928	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	167:84c0a372a020	1929
AnnaBridge	167:84c0a372a020	1930	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	167:84c0a372a020	1931	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
AnnaBridge	167:84c0a372a020	1932	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
AnnaBridge	167:84c0a372a020	1933
AnnaBridge	167:84c0a372a020	1934	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
AnnaBridge	167:84c0a372a020	1935	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
AnnaBridge	167:84c0a372a020	1936
AnnaBridge	167:84c0a372a020	1937	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
AnnaBridge	167:84c0a372a020	1938	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
AnnaBridge	167:84c0a372a020	1939
AnnaBridge	167:84c0a372a020	1940	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
AnnaBridge	167:84c0a372a020	1941	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
AnnaBridge	167:84c0a372a020	1942
AnnaBridge	167:84c0a372a020	1943	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
AnnaBridge	167:84c0a372a020	1944	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
AnnaBridge	167:84c0a372a020	1945
AnnaBridge	167:84c0a372a020	1946	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	167:84c0a372a020	1947	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	167:84c0a372a020	1948
AnnaBridge	167:84c0a372a020	1949	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
AnnaBridge	167:84c0a372a020	1950	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
AnnaBridge	167:84c0a372a020	1951
AnnaBridge	167:84c0a372a020	1952	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
AnnaBridge	167:84c0a372a020	1953	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
AnnaBridge	167:84c0a372a020	1954
AnnaBridge	167:84c0a372a020	1955	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
AnnaBridge	167:84c0a372a020	1956	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
AnnaBridge	167:84c0a372a020	1957
AnnaBridge	167:84c0a372a020	1958	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
AnnaBridge	167:84c0a372a020	1959	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
AnnaBridge	167:84c0a372a020	1960
AnnaBridge	167:84c0a372a020	1961	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
AnnaBridge	167:84c0a372a020	1962	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
AnnaBridge	167:84c0a372a020	1963
AnnaBridge	167:84c0a372a020	1964	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
AnnaBridge	167:84c0a372a020	1965	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
AnnaBridge	167:84c0a372a020	1966
AnnaBridge	167:84c0a372a020	1967	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	167:84c0a372a020	1968	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	167:84c0a372a020	1969
AnnaBridge	167:84c0a372a020	1970	/* Debug Authentication Control Register Definitions */
AnnaBridge	167:84c0a372a020	1971	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
AnnaBridge	167:84c0a372a020	1972	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
AnnaBridge	167:84c0a372a020	1973
AnnaBridge	167:84c0a372a020	1974	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
AnnaBridge	167:84c0a372a020	1975	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
AnnaBridge	167:84c0a372a020	1976
AnnaBridge	167:84c0a372a020	1977	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
AnnaBridge	167:84c0a372a020	1978	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
AnnaBridge	167:84c0a372a020	1979
AnnaBridge	167:84c0a372a020	1980	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
AnnaBridge	167:84c0a372a020	1981	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
AnnaBridge	167:84c0a372a020	1982
AnnaBridge	167:84c0a372a020	1983	/* Debug Security Control and Status Register Definitions */
AnnaBridge	167:84c0a372a020	1984	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
AnnaBridge	167:84c0a372a020	1985	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
AnnaBridge	167:84c0a372a020	1986
AnnaBridge	167:84c0a372a020	1987	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
AnnaBridge	167:84c0a372a020	1988	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
AnnaBridge	167:84c0a372a020	1989
AnnaBridge	167:84c0a372a020	1990	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
AnnaBridge	167:84c0a372a020	1991	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
AnnaBridge	167:84c0a372a020	1992
AnnaBridge	167:84c0a372a020	1993	/@} end of group CMSIS_CoreDebug /
AnnaBridge	167:84c0a372a020	1994
AnnaBridge	167:84c0a372a020	1995
AnnaBridge	167:84c0a372a020	1996	/**
AnnaBridge	167:84c0a372a020	1997	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1998	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	167:84c0a372a020	1999	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	167:84c0a372a020	2000	@{
AnnaBridge	167:84c0a372a020	2001	*/
AnnaBridge	167:84c0a372a020	2002
AnnaBridge	167:84c0a372a020	2003	/**
AnnaBridge	167:84c0a372a020	2004	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	167:84c0a372a020	2005	\param[in] field Name of the register bit field.
AnnaBridge	167:84c0a372a020	2006	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	167:84c0a372a020	2007	\return Masked and shifted value.
AnnaBridge	167:84c0a372a020	2008	*/
AnnaBridge	167:84c0a372a020	2009	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	167:84c0a372a020	2010
AnnaBridge	167:84c0a372a020	2011	/**
AnnaBridge	167:84c0a372a020	2012	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	167:84c0a372a020	2013	\param[in] field Name of the register bit field.
AnnaBridge	167:84c0a372a020	2014	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	167:84c0a372a020	2015	\return Masked and shifted bit field value.
AnnaBridge	167:84c0a372a020	2016	*/
AnnaBridge	167:84c0a372a020	2017	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	167:84c0a372a020	2018
AnnaBridge	167:84c0a372a020	2019	/@} end of group CMSIS_core_bitfield /
AnnaBridge	167:84c0a372a020	2020
AnnaBridge	167:84c0a372a020	2021
AnnaBridge	167:84c0a372a020	2022	/**
AnnaBridge	167:84c0a372a020	2023	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	2024	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	167:84c0a372a020	2025	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	167:84c0a372a020	2026	@{
AnnaBridge	167:84c0a372a020	2027	*/
AnnaBridge	167:84c0a372a020	2028
AnnaBridge	167:84c0a372a020	2029	/* Memory mapping of Core Hardware */
AnnaBridge	167:84c0a372a020	2030	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	167:84c0a372a020	2031	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	167:84c0a372a020	2032	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	167:84c0a372a020	2033	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	167:84c0a372a020	2034	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	167:84c0a372a020	2035	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	167:84c0a372a020	2036	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	167:84c0a372a020	2037	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	167:84c0a372a020	2038
AnnaBridge	167:84c0a372a020	2039	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	167:84c0a372a020	2040	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	167:84c0a372a020	2041	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	167:84c0a372a020	2042	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	167:84c0a372a020	2043	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	167:84c0a372a020	2044	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	167:84c0a372a020	2045	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	167:84c0a372a020	2046	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
AnnaBridge	167:84c0a372a020	2047
AnnaBridge	167:84c0a372a020	2048	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	2049	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	167:84c0a372a020	2050	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	167:84c0a372a020	2051	#endif
AnnaBridge	167:84c0a372a020	2052
AnnaBridge	167:84c0a372a020	2053	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:84c0a372a020	2054	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
AnnaBridge	167:84c0a372a020	2055	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
AnnaBridge	167:84c0a372a020	2056	#endif
AnnaBridge	167:84c0a372a020	2057
AnnaBridge	167:84c0a372a020	2058	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
AnnaBridge	167:84c0a372a020	2059	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
AnnaBridge	167:84c0a372a020	2060
AnnaBridge	167:84c0a372a020	2061	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:84c0a372a020	2062	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
AnnaBridge	167:84c0a372a020	2063	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
AnnaBridge	167:84c0a372a020	2064	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
AnnaBridge	167:84c0a372a020	2065	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
AnnaBridge	167:84c0a372a020	2066	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
AnnaBridge	167:84c0a372a020	2067
AnnaBridge	167:84c0a372a020	2068	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
AnnaBridge	167:84c0a372a020	2069	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
AnnaBridge	167:84c0a372a020	2070	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
AnnaBridge	167:84c0a372a020	2071	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
AnnaBridge	167:84c0a372a020	2072	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
AnnaBridge	167:84c0a372a020	2073
AnnaBridge	167:84c0a372a020	2074	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	2075	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
AnnaBridge	167:84c0a372a020	2076	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
AnnaBridge	167:84c0a372a020	2077	#endif
AnnaBridge	167:84c0a372a020	2078
AnnaBridge	167:84c0a372a020	2079	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
AnnaBridge	167:84c0a372a020	2080	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
AnnaBridge	167:84c0a372a020	2081
AnnaBridge	167:84c0a372a020	2082	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:84c0a372a020	2083	/@} /
AnnaBridge	167:84c0a372a020	2084
AnnaBridge	167:84c0a372a020	2085
AnnaBridge	167:84c0a372a020	2086
AnnaBridge	167:84c0a372a020	2087	/*******************************************************************************
AnnaBridge	167:84c0a372a020	2088	* Hardware Abstraction Layer
AnnaBridge	167:84c0a372a020	2089	Core Function Interface contains:
AnnaBridge	167:84c0a372a020	2090	- Core NVIC Functions
AnnaBridge	167:84c0a372a020	2091	- Core SysTick Functions
AnnaBridge	167:84c0a372a020	2092	- Core Debug Functions
AnnaBridge	167:84c0a372a020	2093	- Core Register Access Functions
AnnaBridge	167:84c0a372a020	2094	******************************************************************************/
AnnaBridge	167:84c0a372a020	2095	/**
AnnaBridge	167:84c0a372a020	2096	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	167:84c0a372a020	2097	*/
AnnaBridge	167:84c0a372a020	2098
AnnaBridge	167:84c0a372a020	2099
AnnaBridge	167:84c0a372a020	2100
AnnaBridge	167:84c0a372a020	2101	/* ########################## NVIC functions #################################### */
AnnaBridge	167:84c0a372a020	2102	/**
AnnaBridge	167:84c0a372a020	2103	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:84c0a372a020	2104	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	167:84c0a372a020	2105	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	167:84c0a372a020	2106	@{
AnnaBridge	167:84c0a372a020	2107	*/
AnnaBridge	167:84c0a372a020	2108
AnnaBridge	167:84c0a372a020	2109	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	167:84c0a372a020	2110	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	167:84c0a372a020	2111	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	167:84c0a372a020	2112	#endif
AnnaBridge	167:84c0a372a020	2113	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	167:84c0a372a020	2114	#else
AnnaBridge	167:84c0a372a020	2115	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge	167:84c0a372a020	2116	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge	167:84c0a372a020	2117	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	167:84c0a372a020	2118	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	167:84c0a372a020	2119	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	167:84c0a372a020	2120	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	167:84c0a372a020	2121	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	167:84c0a372a020	2122	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	167:84c0a372a020	2123	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	167:84c0a372a020	2124	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	167:84c0a372a020	2125	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	167:84c0a372a020	2126	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	167:84c0a372a020	2127	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	167:84c0a372a020	2128
AnnaBridge	167:84c0a372a020	2129	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	167:84c0a372a020	2130	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	167:84c0a372a020	2131	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	167:84c0a372a020	2132	#endif
AnnaBridge	167:84c0a372a020	2133	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	167:84c0a372a020	2134	#else
AnnaBridge	167:84c0a372a020	2135	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	167:84c0a372a020	2136	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	167:84c0a372a020	2137	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	167:84c0a372a020	2138
AnnaBridge	167:84c0a372a020	2139	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	167:84c0a372a020	2140
AnnaBridge	167:84c0a372a020	2141
AnnaBridge	167:84c0a372a020	2142
AnnaBridge	167:84c0a372a020	2143	/**
AnnaBridge	167:84c0a372a020	2144	\brief Set Priority Grouping
AnnaBridge	167:84c0a372a020	2145	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	167:84c0a372a020	2146	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	167:84c0a372a020	2147	Only values from 0..7 are used.
AnnaBridge	167:84c0a372a020	2148	In case of a conflict between priority grouping and available
AnnaBridge	167:84c0a372a020	2149	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	167:84c0a372a020	2150	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	167:84c0a372a020	2151	*/
AnnaBridge	167:84c0a372a020	2152	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge	167:84c0a372a020	2153	{
AnnaBridge	167:84c0a372a020	2154	uint32_t reg_value;
AnnaBridge	167:84c0a372a020	2155	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	167:84c0a372a020	2156
AnnaBridge	167:84c0a372a020	2157	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	167:84c0a372a020	2158	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	167:84c0a372a020	2159	reg_value = (reg_value \|
AnnaBridge	167:84c0a372a020	2160	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	169:a7c7b631e539	2161	(PriorityGroupTmp << 8U) ); /* Insert write key and priority group */
AnnaBridge	167:84c0a372a020	2162	SCB->AIRCR = reg_value;
AnnaBridge	167:84c0a372a020	2163	}
AnnaBridge	167:84c0a372a020	2164
AnnaBridge	167:84c0a372a020	2165
AnnaBridge	167:84c0a372a020	2166	/**
AnnaBridge	167:84c0a372a020	2167	\brief Get Priority Grouping
AnnaBridge	167:84c0a372a020	2168	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	167:84c0a372a020	2169	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	167:84c0a372a020	2170	*/
AnnaBridge	167:84c0a372a020	2171	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge	167:84c0a372a020	2172	{
AnnaBridge	167:84c0a372a020	2173	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	167:84c0a372a020	2174	}
AnnaBridge	167:84c0a372a020	2175
AnnaBridge	167:84c0a372a020	2176
AnnaBridge	167:84c0a372a020	2177	/**
AnnaBridge	167:84c0a372a020	2178	\brief Enable Interrupt
AnnaBridge	167:84c0a372a020	2179	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	167:84c0a372a020	2180	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2181	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2182	*/
AnnaBridge	167:84c0a372a020	2183	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2184	{
AnnaBridge	167:84c0a372a020	2185	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2186	{
Anna Bridge	169:a7c7b631e539	2187	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	167:84c0a372a020	2188	}
AnnaBridge	167:84c0a372a020	2189	}
AnnaBridge	167:84c0a372a020	2190
AnnaBridge	167:84c0a372a020	2191
AnnaBridge	167:84c0a372a020	2192	/**
AnnaBridge	167:84c0a372a020	2193	\brief Get Interrupt Enable status
AnnaBridge	167:84c0a372a020	2194	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	167:84c0a372a020	2195	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2196	\return 0 Interrupt is not enabled.
AnnaBridge	167:84c0a372a020	2197	\return 1 Interrupt is enabled.
AnnaBridge	167:84c0a372a020	2198	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2199	*/
AnnaBridge	167:84c0a372a020	2200	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2201	{
AnnaBridge	167:84c0a372a020	2202	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2203	{
Anna Bridge	169:a7c7b631e539	2204	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:84c0a372a020	2205	}
AnnaBridge	167:84c0a372a020	2206	else
AnnaBridge	167:84c0a372a020	2207	{
AnnaBridge	167:84c0a372a020	2208	return(0U);
AnnaBridge	167:84c0a372a020	2209	}
AnnaBridge	167:84c0a372a020	2210	}
AnnaBridge	167:84c0a372a020	2211
AnnaBridge	167:84c0a372a020	2212
AnnaBridge	167:84c0a372a020	2213	/**
AnnaBridge	167:84c0a372a020	2214	\brief Disable Interrupt
AnnaBridge	167:84c0a372a020	2215	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	167:84c0a372a020	2216	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2217	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2218	*/
AnnaBridge	167:84c0a372a020	2219	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2220	{
AnnaBridge	167:84c0a372a020	2221	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2222	{
Anna Bridge	169:a7c7b631e539	2223	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	167:84c0a372a020	2224	__DSB();
AnnaBridge	167:84c0a372a020	2225	__ISB();
AnnaBridge	167:84c0a372a020	2226	}
AnnaBridge	167:84c0a372a020	2227	}
AnnaBridge	167:84c0a372a020	2228
AnnaBridge	167:84c0a372a020	2229
AnnaBridge	167:84c0a372a020	2230	/**
AnnaBridge	167:84c0a372a020	2231	\brief Get Pending Interrupt
AnnaBridge	167:84c0a372a020	2232	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	167:84c0a372a020	2233	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2234	\return 0 Interrupt status is not pending.
AnnaBridge	167:84c0a372a020	2235	\return 1 Interrupt status is pending.
AnnaBridge	167:84c0a372a020	2236	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2237	*/
AnnaBridge	167:84c0a372a020	2238	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2239	{
AnnaBridge	167:84c0a372a020	2240	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2241	{
Anna Bridge	169:a7c7b631e539	2242	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:84c0a372a020	2243	}
AnnaBridge	167:84c0a372a020	2244	else
AnnaBridge	167:84c0a372a020	2245	{
AnnaBridge	167:84c0a372a020	2246	return(0U);
AnnaBridge	167:84c0a372a020	2247	}
AnnaBridge	167:84c0a372a020	2248	}
AnnaBridge	167:84c0a372a020	2249
AnnaBridge	167:84c0a372a020	2250
AnnaBridge	167:84c0a372a020	2251	/**
AnnaBridge	167:84c0a372a020	2252	\brief Set Pending Interrupt
AnnaBridge	167:84c0a372a020	2253	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	167:84c0a372a020	2254	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2255	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2256	*/
AnnaBridge	167:84c0a372a020	2257	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2258	{
AnnaBridge	167:84c0a372a020	2259	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2260	{
Anna Bridge	169:a7c7b631e539	2261	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	167:84c0a372a020	2262	}
AnnaBridge	167:84c0a372a020	2263	}
AnnaBridge	167:84c0a372a020	2264
AnnaBridge	167:84c0a372a020	2265
AnnaBridge	167:84c0a372a020	2266	/**
AnnaBridge	167:84c0a372a020	2267	\brief Clear Pending Interrupt
AnnaBridge	167:84c0a372a020	2268	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	167:84c0a372a020	2269	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2270	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2271	*/
AnnaBridge	167:84c0a372a020	2272	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2273	{
AnnaBridge	167:84c0a372a020	2274	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2275	{
Anna Bridge	169:a7c7b631e539	2276	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	167:84c0a372a020	2277	}
AnnaBridge	167:84c0a372a020	2278	}
AnnaBridge	167:84c0a372a020	2279
AnnaBridge	167:84c0a372a020	2280
AnnaBridge	167:84c0a372a020	2281	/**
AnnaBridge	167:84c0a372a020	2282	\brief Get Active Interrupt
AnnaBridge	167:84c0a372a020	2283	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	167:84c0a372a020	2284	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2285	\return 0 Interrupt status is not active.
AnnaBridge	167:84c0a372a020	2286	\return 1 Interrupt status is active.
AnnaBridge	167:84c0a372a020	2287	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2288	*/
AnnaBridge	167:84c0a372a020	2289	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2290	{
AnnaBridge	167:84c0a372a020	2291	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2292	{
Anna Bridge	169:a7c7b631e539	2293	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:84c0a372a020	2294	}
AnnaBridge	167:84c0a372a020	2295	else
AnnaBridge	167:84c0a372a020	2296	{
AnnaBridge	167:84c0a372a020	2297	return(0U);
AnnaBridge	167:84c0a372a020	2298	}
AnnaBridge	167:84c0a372a020	2299	}
AnnaBridge	167:84c0a372a020	2300
AnnaBridge	167:84c0a372a020	2301
AnnaBridge	167:84c0a372a020	2302	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:84c0a372a020	2303	/**
AnnaBridge	167:84c0a372a020	2304	\brief Get Interrupt Target State
AnnaBridge	167:84c0a372a020	2305	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	167:84c0a372a020	2306	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2307	\return 0 if interrupt is assigned to Secure
AnnaBridge	167:84c0a372a020	2308	\return 1 if interrupt is assigned to Non Secure
AnnaBridge	167:84c0a372a020	2309	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2310	*/
AnnaBridge	167:84c0a372a020	2311	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2312	{
AnnaBridge	167:84c0a372a020	2313	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2314	{
Anna Bridge	169:a7c7b631e539	2315	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:84c0a372a020	2316	}
AnnaBridge	167:84c0a372a020	2317	else
AnnaBridge	167:84c0a372a020	2318	{
AnnaBridge	167:84c0a372a020	2319	return(0U);
AnnaBridge	167:84c0a372a020	2320	}
AnnaBridge	167:84c0a372a020	2321	}
AnnaBridge	167:84c0a372a020	2322
AnnaBridge	167:84c0a372a020	2323
AnnaBridge	167:84c0a372a020	2324	/**
AnnaBridge	167:84c0a372a020	2325	\brief Set Interrupt Target State
AnnaBridge	167:84c0a372a020	2326	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	167:84c0a372a020	2327	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2328	\return 0 if interrupt is assigned to Secure
AnnaBridge	167:84c0a372a020	2329	1 if interrupt is assigned to Non Secure
AnnaBridge	167:84c0a372a020	2330	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2331	*/
AnnaBridge	167:84c0a372a020	2332	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2333	{
AnnaBridge	167:84c0a372a020	2334	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2335	{
Anna Bridge	169:a7c7b631e539	2336	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge	169:a7c7b631e539	2337	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:84c0a372a020	2338	}
AnnaBridge	167:84c0a372a020	2339	else
AnnaBridge	167:84c0a372a020	2340	{
AnnaBridge	167:84c0a372a020	2341	return(0U);
AnnaBridge	167:84c0a372a020	2342	}
AnnaBridge	167:84c0a372a020	2343	}
AnnaBridge	167:84c0a372a020	2344
AnnaBridge	167:84c0a372a020	2345
AnnaBridge	167:84c0a372a020	2346	/**
AnnaBridge	167:84c0a372a020	2347	\brief Clear Interrupt Target State
AnnaBridge	167:84c0a372a020	2348	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	167:84c0a372a020	2349	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2350	\return 0 if interrupt is assigned to Secure
AnnaBridge	167:84c0a372a020	2351	1 if interrupt is assigned to Non Secure
AnnaBridge	167:84c0a372a020	2352	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2353	*/
AnnaBridge	167:84c0a372a020	2354	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2355	{
AnnaBridge	167:84c0a372a020	2356	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2357	{
Anna Bridge	169:a7c7b631e539	2358	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge	169:a7c7b631e539	2359	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:84c0a372a020	2360	}
AnnaBridge	167:84c0a372a020	2361	else
AnnaBridge	167:84c0a372a020	2362	{
AnnaBridge	167:84c0a372a020	2363	return(0U);
AnnaBridge	167:84c0a372a020	2364	}
AnnaBridge	167:84c0a372a020	2365	}
AnnaBridge	167:84c0a372a020	2366	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:84c0a372a020	2367
AnnaBridge	167:84c0a372a020	2368
AnnaBridge	167:84c0a372a020	2369	/**
AnnaBridge	167:84c0a372a020	2370	\brief Set Interrupt Priority
AnnaBridge	167:84c0a372a020	2371	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	167:84c0a372a020	2372	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:84c0a372a020	2373	or negative to specify a processor exception.
AnnaBridge	167:84c0a372a020	2374	\param [in] IRQn Interrupt number.
AnnaBridge	167:84c0a372a020	2375	\param [in] priority Priority to set.
AnnaBridge	167:84c0a372a020	2376	\note The priority cannot be set for every processor exception.
AnnaBridge	167:84c0a372a020	2377	*/
AnnaBridge	167:84c0a372a020	2378	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	167:84c0a372a020	2379	{
AnnaBridge	167:84c0a372a020	2380	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2381	{
Anna Bridge	169:a7c7b631e539	2382	NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:84c0a372a020	2383	}
AnnaBridge	167:84c0a372a020	2384	else
AnnaBridge	167:84c0a372a020	2385	{
Anna Bridge	169:a7c7b631e539	2386	SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:84c0a372a020	2387	}
AnnaBridge	167:84c0a372a020	2388	}
AnnaBridge	167:84c0a372a020	2389
AnnaBridge	167:84c0a372a020	2390
AnnaBridge	167:84c0a372a020	2391	/**
AnnaBridge	167:84c0a372a020	2392	\brief Get Interrupt Priority
AnnaBridge	167:84c0a372a020	2393	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	167:84c0a372a020	2394	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:84c0a372a020	2395	or negative to specify a processor exception.
AnnaBridge	167:84c0a372a020	2396	\param [in] IRQn Interrupt number.
AnnaBridge	167:84c0a372a020	2397	\return Interrupt Priority.
AnnaBridge	167:84c0a372a020	2398	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	167:84c0a372a020	2399	*/
AnnaBridge	167:84c0a372a020	2400	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2401	{
AnnaBridge	167:84c0a372a020	2402
AnnaBridge	167:84c0a372a020	2403	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2404	{
Anna Bridge	169:a7c7b631e539	2405	return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:84c0a372a020	2406	}
AnnaBridge	167:84c0a372a020	2407	else
AnnaBridge	167:84c0a372a020	2408	{
Anna Bridge	169:a7c7b631e539	2409	return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:84c0a372a020	2410	}
AnnaBridge	167:84c0a372a020	2411	}
AnnaBridge	167:84c0a372a020	2412
AnnaBridge	167:84c0a372a020	2413
AnnaBridge	167:84c0a372a020	2414	/**
AnnaBridge	167:84c0a372a020	2415	\brief Encode Priority
AnnaBridge	167:84c0a372a020	2416	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	167:84c0a372a020	2417	preemptive priority value, and subpriority value.
AnnaBridge	167:84c0a372a020	2418	In case of a conflict between priority grouping and available
AnnaBridge	167:84c0a372a020	2419	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	167:84c0a372a020	2420	\param [in] PriorityGroup Used priority group.
AnnaBridge	167:84c0a372a020	2421	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	167:84c0a372a020	2422	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	167:84c0a372a020	2423	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	167:84c0a372a020	2424	*/
AnnaBridge	167:84c0a372a020	2425	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	167:84c0a372a020	2426	{
AnnaBridge	167:84c0a372a020	2427	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	167:84c0a372a020	2428	uint32_t PreemptPriorityBits;
AnnaBridge	167:84c0a372a020	2429	uint32_t SubPriorityBits;
AnnaBridge	167:84c0a372a020	2430
AnnaBridge	167:84c0a372a020	2431	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	167:84c0a372a020	2432	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	167:84c0a372a020	2433
AnnaBridge	167:84c0a372a020	2434	return (
AnnaBridge	167:84c0a372a020	2435	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	167:84c0a372a020	2436	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	167:84c0a372a020	2437	);
AnnaBridge	167:84c0a372a020	2438	}
AnnaBridge	167:84c0a372a020	2439
AnnaBridge	167:84c0a372a020	2440
AnnaBridge	167:84c0a372a020	2441	/**
AnnaBridge	167:84c0a372a020	2442	\brief Decode Priority
AnnaBridge	167:84c0a372a020	2443	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	167:84c0a372a020	2444	preemptive priority value and subpriority value.
AnnaBridge	167:84c0a372a020	2445	In case of a conflict between priority grouping and available
AnnaBridge	167:84c0a372a020	2446	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	167:84c0a372a020	2447	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	167:84c0a372a020	2448	\param [in] PriorityGroup Used priority group.
AnnaBridge	167:84c0a372a020	2449	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	167:84c0a372a020	2450	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	167:84c0a372a020	2451	*/
AnnaBridge	167:84c0a372a020	2452	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge	167:84c0a372a020	2453	{
AnnaBridge	167:84c0a372a020	2454	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	167:84c0a372a020	2455	uint32_t PreemptPriorityBits;
AnnaBridge	167:84c0a372a020	2456	uint32_t SubPriorityBits;
AnnaBridge	167:84c0a372a020	2457
AnnaBridge	167:84c0a372a020	2458	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	167:84c0a372a020	2459	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	167:84c0a372a020	2460
AnnaBridge	167:84c0a372a020	2461	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	167:84c0a372a020	2462	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	167:84c0a372a020	2463	}
AnnaBridge	167:84c0a372a020	2464
AnnaBridge	167:84c0a372a020	2465
AnnaBridge	167:84c0a372a020	2466	/**
AnnaBridge	167:84c0a372a020	2467	\brief Set Interrupt Vector
AnnaBridge	167:84c0a372a020	2468	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	167:84c0a372a020	2469	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:84c0a372a020	2470	or negative to specify a processor exception.
AnnaBridge	167:84c0a372a020	2471	VTOR must been relocated to SRAM before.
AnnaBridge	167:84c0a372a020	2472	\param [in] IRQn Interrupt number
AnnaBridge	167:84c0a372a020	2473	\param [in] vector Address of interrupt handler function
AnnaBridge	167:84c0a372a020	2474	*/
AnnaBridge	167:84c0a372a020	2475	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	167:84c0a372a020	2476	{
AnnaBridge	167:84c0a372a020	2477	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	167:84c0a372a020	2478	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	167:84c0a372a020	2479	}
AnnaBridge	167:84c0a372a020	2480
AnnaBridge	167:84c0a372a020	2481
AnnaBridge	167:84c0a372a020	2482	/**
AnnaBridge	167:84c0a372a020	2483	\brief Get Interrupt Vector
AnnaBridge	167:84c0a372a020	2484	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	167:84c0a372a020	2485	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:84c0a372a020	2486	or negative to specify a processor exception.
AnnaBridge	167:84c0a372a020	2487	\param [in] IRQn Interrupt number.
AnnaBridge	167:84c0a372a020	2488	\return Address of interrupt handler function
AnnaBridge	167:84c0a372a020	2489	*/
AnnaBridge	167:84c0a372a020	2490	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2491	{
AnnaBridge	167:84c0a372a020	2492	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	167:84c0a372a020	2493	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	167:84c0a372a020	2494	}
AnnaBridge	167:84c0a372a020	2495
AnnaBridge	167:84c0a372a020	2496
AnnaBridge	167:84c0a372a020	2497	/**
AnnaBridge	167:84c0a372a020	2498	\brief System Reset
AnnaBridge	167:84c0a372a020	2499	\details Initiates a system reset request to reset the MCU.
AnnaBridge	167:84c0a372a020	2500	*/
AnnaBridge	167:84c0a372a020	2501	__STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	167:84c0a372a020	2502	{
AnnaBridge	167:84c0a372a020	2503	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	167:84c0a372a020	2504	buffered write are completed before reset */
AnnaBridge	167:84c0a372a020	2505	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	167:84c0a372a020	2506	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
AnnaBridge	167:84c0a372a020	2507	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge	167:84c0a372a020	2508	__DSB(); /* Ensure completion of memory access */
AnnaBridge	167:84c0a372a020	2509
AnnaBridge	167:84c0a372a020	2510	for(;;) /* wait until reset */
AnnaBridge	167:84c0a372a020	2511	{
AnnaBridge	167:84c0a372a020	2512	__NOP();
AnnaBridge	167:84c0a372a020	2513	}
AnnaBridge	167:84c0a372a020	2514	}
AnnaBridge	167:84c0a372a020	2515
AnnaBridge	167:84c0a372a020	2516	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:84c0a372a020	2517	/**
AnnaBridge	167:84c0a372a020	2518	\brief Set Priority Grouping (non-secure)
AnnaBridge	167:84c0a372a020	2519	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
AnnaBridge	167:84c0a372a020	2520	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	167:84c0a372a020	2521	Only values from 0..7 are used.
AnnaBridge	167:84c0a372a020	2522	In case of a conflict between priority grouping and available
AnnaBridge	167:84c0a372a020	2523	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	167:84c0a372a020	2524	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	167:84c0a372a020	2525	*/
AnnaBridge	167:84c0a372a020	2526	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
AnnaBridge	167:84c0a372a020	2527	{
AnnaBridge	167:84c0a372a020	2528	uint32_t reg_value;
AnnaBridge	167:84c0a372a020	2529	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	167:84c0a372a020	2530
Anna Bridge	169:a7c7b631e539	2531	reg_value = SCB_NS->AIRCR; /* read old register configuration */
Anna Bridge	169:a7c7b631e539	2532	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	167:84c0a372a020	2533	reg_value = (reg_value \|
AnnaBridge	167:84c0a372a020	2534	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	169:a7c7b631e539	2535	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
AnnaBridge	167:84c0a372a020	2536	SCB_NS->AIRCR = reg_value;
AnnaBridge	167:84c0a372a020	2537	}
AnnaBridge	167:84c0a372a020	2538
AnnaBridge	167:84c0a372a020	2539
AnnaBridge	167:84c0a372a020	2540	/**
AnnaBridge	167:84c0a372a020	2541	\brief Get Priority Grouping (non-secure)
AnnaBridge	167:84c0a372a020	2542	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
AnnaBridge	167:84c0a372a020	2543	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	167:84c0a372a020	2544	*/
AnnaBridge	167:84c0a372a020	2545	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
AnnaBridge	167:84c0a372a020	2546	{
AnnaBridge	167:84c0a372a020	2547	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	167:84c0a372a020	2548	}
AnnaBridge	167:84c0a372a020	2549
AnnaBridge	167:84c0a372a020	2550
AnnaBridge	167:84c0a372a020	2551	/**
AnnaBridge	167:84c0a372a020	2552	\brief Enable Interrupt (non-secure)
AnnaBridge	167:84c0a372a020	2553	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	167:84c0a372a020	2554	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2555	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2556	*/
AnnaBridge	167:84c0a372a020	2557	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2558	{
AnnaBridge	167:84c0a372a020	2559	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2560	{
Anna Bridge	169:a7c7b631e539	2561	NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	167:84c0a372a020	2562	}
AnnaBridge	167:84c0a372a020	2563	}
AnnaBridge	167:84c0a372a020	2564
AnnaBridge	167:84c0a372a020	2565
AnnaBridge	167:84c0a372a020	2566	/**
AnnaBridge	167:84c0a372a020	2567	\brief Get Interrupt Enable status (non-secure)
AnnaBridge	167:84c0a372a020	2568	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	167:84c0a372a020	2569	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2570	\return 0 Interrupt is not enabled.
AnnaBridge	167:84c0a372a020	2571	\return 1 Interrupt is enabled.
AnnaBridge	167:84c0a372a020	2572	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2573	*/
AnnaBridge	167:84c0a372a020	2574	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2575	{
AnnaBridge	167:84c0a372a020	2576	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2577	{
Anna Bridge	169:a7c7b631e539	2578	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:84c0a372a020	2579	}
AnnaBridge	167:84c0a372a020	2580	else
AnnaBridge	167:84c0a372a020	2581	{
AnnaBridge	167:84c0a372a020	2582	return(0U);
AnnaBridge	167:84c0a372a020	2583	}
AnnaBridge	167:84c0a372a020	2584	}
AnnaBridge	167:84c0a372a020	2585
AnnaBridge	167:84c0a372a020	2586
AnnaBridge	167:84c0a372a020	2587	/**
AnnaBridge	167:84c0a372a020	2588	\brief Disable Interrupt (non-secure)
AnnaBridge	167:84c0a372a020	2589	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	167:84c0a372a020	2590	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2591	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2592	*/
AnnaBridge	167:84c0a372a020	2593	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2594	{
AnnaBridge	167:84c0a372a020	2595	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2596	{
Anna Bridge	169:a7c7b631e539	2597	NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	167:84c0a372a020	2598	}
AnnaBridge	167:84c0a372a020	2599	}
AnnaBridge	167:84c0a372a020	2600
AnnaBridge	167:84c0a372a020	2601
AnnaBridge	167:84c0a372a020	2602	/**
AnnaBridge	167:84c0a372a020	2603	\brief Get Pending Interrupt (non-secure)
AnnaBridge	167:84c0a372a020	2604	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge	167:84c0a372a020	2605	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2606	\return 0 Interrupt status is not pending.
AnnaBridge	167:84c0a372a020	2607	\return 1 Interrupt status is pending.
AnnaBridge	167:84c0a372a020	2608	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2609	*/
AnnaBridge	167:84c0a372a020	2610	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2611	{
AnnaBridge	167:84c0a372a020	2612	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2613	{
Anna Bridge	169:a7c7b631e539	2614	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:84c0a372a020	2615	}
AnnaBridge	167:84c0a372a020	2616	else
AnnaBridge	167:84c0a372a020	2617	{
AnnaBridge	167:84c0a372a020	2618	return(0U);
AnnaBridge	167:84c0a372a020	2619	}
AnnaBridge	167:84c0a372a020	2620	}
AnnaBridge	167:84c0a372a020	2621
AnnaBridge	167:84c0a372a020	2622
AnnaBridge	167:84c0a372a020	2623	/**
AnnaBridge	167:84c0a372a020	2624	\brief Set Pending Interrupt (non-secure)
AnnaBridge	167:84c0a372a020	2625	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	167:84c0a372a020	2626	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2627	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2628	*/
AnnaBridge	167:84c0a372a020	2629	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2630	{
AnnaBridge	167:84c0a372a020	2631	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2632	{
Anna Bridge	169:a7c7b631e539	2633	NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	167:84c0a372a020	2634	}
AnnaBridge	167:84c0a372a020	2635	}
AnnaBridge	167:84c0a372a020	2636
AnnaBridge	167:84c0a372a020	2637
AnnaBridge	167:84c0a372a020	2638	/**
AnnaBridge	167:84c0a372a020	2639	\brief Clear Pending Interrupt (non-secure)
AnnaBridge	167:84c0a372a020	2640	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	167:84c0a372a020	2641	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2642	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2643	*/
AnnaBridge	167:84c0a372a020	2644	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2645	{
AnnaBridge	167:84c0a372a020	2646	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2647	{
Anna Bridge	169:a7c7b631e539	2648	NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	167:84c0a372a020	2649	}
AnnaBridge	167:84c0a372a020	2650	}
AnnaBridge	167:84c0a372a020	2651
AnnaBridge	167:84c0a372a020	2652
AnnaBridge	167:84c0a372a020	2653	/**
AnnaBridge	167:84c0a372a020	2654	\brief Get Active Interrupt (non-secure)
AnnaBridge	167:84c0a372a020	2655	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge	167:84c0a372a020	2656	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	2657	\return 0 Interrupt status is not active.
AnnaBridge	167:84c0a372a020	2658	\return 1 Interrupt status is active.
AnnaBridge	167:84c0a372a020	2659	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	2660	*/
AnnaBridge	167:84c0a372a020	2661	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2662	{
AnnaBridge	167:84c0a372a020	2663	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2664	{
Anna Bridge	169:a7c7b631e539	2665	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:84c0a372a020	2666	}
AnnaBridge	167:84c0a372a020	2667	else
AnnaBridge	167:84c0a372a020	2668	{
AnnaBridge	167:84c0a372a020	2669	return(0U);
AnnaBridge	167:84c0a372a020	2670	}
AnnaBridge	167:84c0a372a020	2671	}
AnnaBridge	167:84c0a372a020	2672
AnnaBridge	167:84c0a372a020	2673
AnnaBridge	167:84c0a372a020	2674	/**
AnnaBridge	167:84c0a372a020	2675	\brief Set Interrupt Priority (non-secure)
AnnaBridge	167:84c0a372a020	2676	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	167:84c0a372a020	2677	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:84c0a372a020	2678	or negative to specify a processor exception.
AnnaBridge	167:84c0a372a020	2679	\param [in] IRQn Interrupt number.
AnnaBridge	167:84c0a372a020	2680	\param [in] priority Priority to set.
AnnaBridge	167:84c0a372a020	2681	\note The priority cannot be set for every non-secure processor exception.
AnnaBridge	167:84c0a372a020	2682	*/
AnnaBridge	167:84c0a372a020	2683	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	167:84c0a372a020	2684	{
AnnaBridge	167:84c0a372a020	2685	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2686	{
Anna Bridge	169:a7c7b631e539	2687	NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:84c0a372a020	2688	}
AnnaBridge	167:84c0a372a020	2689	else
AnnaBridge	167:84c0a372a020	2690	{
Anna Bridge	169:a7c7b631e539	2691	SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:84c0a372a020	2692	}
AnnaBridge	167:84c0a372a020	2693	}
AnnaBridge	167:84c0a372a020	2694
AnnaBridge	167:84c0a372a020	2695
AnnaBridge	167:84c0a372a020	2696	/**
AnnaBridge	167:84c0a372a020	2697	\brief Get Interrupt Priority (non-secure)
AnnaBridge	167:84c0a372a020	2698	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	167:84c0a372a020	2699	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:84c0a372a020	2700	or negative to specify a processor exception.
AnnaBridge	167:84c0a372a020	2701	\param [in] IRQn Interrupt number.
AnnaBridge	167:84c0a372a020	2702	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	167:84c0a372a020	2703	*/
AnnaBridge	167:84c0a372a020	2704	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	2705	{
AnnaBridge	167:84c0a372a020	2706
AnnaBridge	167:84c0a372a020	2707	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	2708	{
Anna Bridge	169:a7c7b631e539	2709	return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:84c0a372a020	2710	}
AnnaBridge	167:84c0a372a020	2711	else
AnnaBridge	167:84c0a372a020	2712	{
Anna Bridge	169:a7c7b631e539	2713	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:84c0a372a020	2714	}
AnnaBridge	167:84c0a372a020	2715	}
AnnaBridge	167:84c0a372a020	2716	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:84c0a372a020	2717
AnnaBridge	167:84c0a372a020	2718	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	167:84c0a372a020	2719
AnnaBridge	167:84c0a372a020	2720	/* ########################## MPU functions #################################### */
AnnaBridge	167:84c0a372a020	2721
AnnaBridge	167:84c0a372a020	2722	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	2723
AnnaBridge	167:84c0a372a020	2724	#include "mpu_armv8.h"
AnnaBridge	167:84c0a372a020	2725
AnnaBridge	167:84c0a372a020	2726	#endif
AnnaBridge	167:84c0a372a020	2727
AnnaBridge	167:84c0a372a020	2728	/* ########################## FPU functions #################################### */
AnnaBridge	167:84c0a372a020	2729	/**
AnnaBridge	167:84c0a372a020	2730	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:84c0a372a020	2731	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	167:84c0a372a020	2732	\brief Function that provides FPU type.
AnnaBridge	167:84c0a372a020	2733	@{
AnnaBridge	167:84c0a372a020	2734	*/
AnnaBridge	167:84c0a372a020	2735
AnnaBridge	167:84c0a372a020	2736	/**
AnnaBridge	167:84c0a372a020	2737	\brief get FPU type
AnnaBridge	167:84c0a372a020	2738	\details returns the FPU type
AnnaBridge	167:84c0a372a020	2739	\returns
AnnaBridge	167:84c0a372a020	2740	- \b 0: No FPU
AnnaBridge	167:84c0a372a020	2741	- \b 1: Single precision FPU
AnnaBridge	167:84c0a372a020	2742	- \b 2: Double + Single precision FPU
AnnaBridge	167:84c0a372a020	2743	*/
AnnaBridge	167:84c0a372a020	2744	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	167:84c0a372a020	2745	{
AnnaBridge	167:84c0a372a020	2746	uint32_t mvfr0;
AnnaBridge	167:84c0a372a020	2747
AnnaBridge	167:84c0a372a020	2748	mvfr0 = FPU->MVFR0;
AnnaBridge	167:84c0a372a020	2749	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
AnnaBridge	167:84c0a372a020	2750	{
AnnaBridge	167:84c0a372a020	2751	return 2U; /* Double + Single precision FPU */
AnnaBridge	167:84c0a372a020	2752	}
AnnaBridge	167:84c0a372a020	2753	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge	167:84c0a372a020	2754	{
AnnaBridge	167:84c0a372a020	2755	return 1U; /* Single precision FPU */
AnnaBridge	167:84c0a372a020	2756	}
AnnaBridge	167:84c0a372a020	2757	else
AnnaBridge	167:84c0a372a020	2758	{
AnnaBridge	167:84c0a372a020	2759	return 0U; /* No FPU */
AnnaBridge	167:84c0a372a020	2760	}
AnnaBridge	167:84c0a372a020	2761	}
AnnaBridge	167:84c0a372a020	2762
AnnaBridge	167:84c0a372a020	2763
AnnaBridge	167:84c0a372a020	2764	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	167:84c0a372a020	2765
AnnaBridge	167:84c0a372a020	2766
AnnaBridge	167:84c0a372a020	2767
AnnaBridge	167:84c0a372a020	2768	/* ########################## SAU functions #################################### */
AnnaBridge	167:84c0a372a020	2769	/**
AnnaBridge	167:84c0a372a020	2770	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:84c0a372a020	2771	\defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge	167:84c0a372a020	2772	\brief Functions that configure the SAU.
AnnaBridge	167:84c0a372a020	2773	@{
AnnaBridge	167:84c0a372a020	2774	*/
AnnaBridge	167:84c0a372a020	2775
AnnaBridge	167:84c0a372a020	2776	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:84c0a372a020	2777
AnnaBridge	167:84c0a372a020	2778	/**
AnnaBridge	167:84c0a372a020	2779	\brief Enable SAU
AnnaBridge	167:84c0a372a020	2780	\details Enables the Security Attribution Unit (SAU).
AnnaBridge	167:84c0a372a020	2781	*/
AnnaBridge	167:84c0a372a020	2782	__STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge	167:84c0a372a020	2783	{
AnnaBridge	167:84c0a372a020	2784	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
AnnaBridge	167:84c0a372a020	2785	}
AnnaBridge	167:84c0a372a020	2786
AnnaBridge	167:84c0a372a020	2787
AnnaBridge	167:84c0a372a020	2788
AnnaBridge	167:84c0a372a020	2789	/**
AnnaBridge	167:84c0a372a020	2790	\brief Disable SAU
AnnaBridge	167:84c0a372a020	2791	\details Disables the Security Attribution Unit (SAU).
AnnaBridge	167:84c0a372a020	2792	*/
AnnaBridge	167:84c0a372a020	2793	__STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge	167:84c0a372a020	2794	{
AnnaBridge	167:84c0a372a020	2795	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge	167:84c0a372a020	2796	}
AnnaBridge	167:84c0a372a020	2797
AnnaBridge	167:84c0a372a020	2798	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:84c0a372a020	2799
AnnaBridge	167:84c0a372a020	2800	/@} end of CMSIS_Core_SAUFunctions /
AnnaBridge	167:84c0a372a020	2801
AnnaBridge	167:84c0a372a020	2802
AnnaBridge	167:84c0a372a020	2803
AnnaBridge	167:84c0a372a020	2804
AnnaBridge	167:84c0a372a020	2805	/* ################################## SysTick function ############################################ */
AnnaBridge	167:84c0a372a020	2806	/**
AnnaBridge	167:84c0a372a020	2807	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:84c0a372a020	2808	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	167:84c0a372a020	2809	\brief Functions that configure the System.
AnnaBridge	167:84c0a372a020	2810	@{
AnnaBridge	167:84c0a372a020	2811	*/
AnnaBridge	167:84c0a372a020	2812
AnnaBridge	167:84c0a372a020	2813	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	167:84c0a372a020	2814
AnnaBridge	167:84c0a372a020	2815	/**
AnnaBridge	167:84c0a372a020	2816	\brief System Tick Configuration
AnnaBridge	167:84c0a372a020	2817	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	167:84c0a372a020	2818	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	167:84c0a372a020	2819	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	167:84c0a372a020	2820	\return 0 Function succeeded.
AnnaBridge	167:84c0a372a020	2821	\return 1 Function failed.
AnnaBridge	167:84c0a372a020	2822	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	167:84c0a372a020	2823	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	167:84c0a372a020	2824	must contain a vendor-specific implementation of this function.
AnnaBridge	167:84c0a372a020	2825	*/
AnnaBridge	167:84c0a372a020	2826	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	167:84c0a372a020	2827	{
AnnaBridge	167:84c0a372a020	2828	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	167:84c0a372a020	2829	{
AnnaBridge	167:84c0a372a020	2830	return (1UL); /* Reload value impossible */
AnnaBridge	167:84c0a372a020	2831	}
AnnaBridge	167:84c0a372a020	2832
AnnaBridge	167:84c0a372a020	2833	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	167:84c0a372a020	2834	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	167:84c0a372a020	2835	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	167:84c0a372a020	2836	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	167:84c0a372a020	2837	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	167:84c0a372a020	2838	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	167:84c0a372a020	2839	return (0UL); /* Function successful */
AnnaBridge	167:84c0a372a020	2840	}
AnnaBridge	167:84c0a372a020	2841
AnnaBridge	167:84c0a372a020	2842	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	167:84c0a372a020	2843	/**
AnnaBridge	167:84c0a372a020	2844	\brief System Tick Configuration (non-secure)
AnnaBridge	167:84c0a372a020	2845	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge	167:84c0a372a020	2846	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	167:84c0a372a020	2847	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	167:84c0a372a020	2848	\return 0 Function succeeded.
AnnaBridge	167:84c0a372a020	2849	\return 1 Function failed.
AnnaBridge	167:84c0a372a020	2850	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	167:84c0a372a020	2851	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	167:84c0a372a020	2852	must contain a vendor-specific implementation of this function.
AnnaBridge	167:84c0a372a020	2853
AnnaBridge	167:84c0a372a020	2854	*/
AnnaBridge	167:84c0a372a020	2855	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge	167:84c0a372a020	2856	{
AnnaBridge	167:84c0a372a020	2857	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	167:84c0a372a020	2858	{
AnnaBridge	167:84c0a372a020	2859	return (1UL); /* Reload value impossible */
AnnaBridge	167:84c0a372a020	2860	}
AnnaBridge	167:84c0a372a020	2861
AnnaBridge	167:84c0a372a020	2862	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	167:84c0a372a020	2863	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	167:84c0a372a020	2864	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	167:84c0a372a020	2865	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	167:84c0a372a020	2866	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	167:84c0a372a020	2867	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	167:84c0a372a020	2868	return (0UL); /* Function successful */
AnnaBridge	167:84c0a372a020	2869	}
AnnaBridge	167:84c0a372a020	2870	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	167:84c0a372a020	2871
AnnaBridge	167:84c0a372a020	2872	#endif
AnnaBridge	167:84c0a372a020	2873
AnnaBridge	167:84c0a372a020	2874	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	167:84c0a372a020	2875
AnnaBridge	167:84c0a372a020	2876
AnnaBridge	167:84c0a372a020	2877
AnnaBridge	167:84c0a372a020	2878	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	167:84c0a372a020	2879	/**
AnnaBridge	167:84c0a372a020	2880	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:84c0a372a020	2881	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	167:84c0a372a020	2882	\brief Functions that access the ITM debug interface.
AnnaBridge	167:84c0a372a020	2883	@{
AnnaBridge	167:84c0a372a020	2884	*/
AnnaBridge	167:84c0a372a020	2885
AnnaBridge	167:84c0a372a020	2886	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	167:84c0a372a020	2887	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
AnnaBridge	167:84c0a372a020	2888
AnnaBridge	167:84c0a372a020	2889
AnnaBridge	167:84c0a372a020	2890	/**
AnnaBridge	167:84c0a372a020	2891	\brief ITM Send Character
AnnaBridge	167:84c0a372a020	2892	\details Transmits a character via the ITM channel 0, and
AnnaBridge	167:84c0a372a020	2893	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	167:84c0a372a020	2894	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	167:84c0a372a020	2895	\param [in] ch Character to transmit.
AnnaBridge	167:84c0a372a020	2896	\returns Character to transmit.
AnnaBridge	167:84c0a372a020	2897	*/
AnnaBridge	167:84c0a372a020	2898	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge	167:84c0a372a020	2899	{
AnnaBridge	167:84c0a372a020	2900	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge	167:84c0a372a020	2901	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge	167:84c0a372a020	2902	{
AnnaBridge	167:84c0a372a020	2903	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	167:84c0a372a020	2904	{
AnnaBridge	167:84c0a372a020	2905	__NOP();
AnnaBridge	167:84c0a372a020	2906	}
AnnaBridge	167:84c0a372a020	2907	ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge	167:84c0a372a020	2908	}
AnnaBridge	167:84c0a372a020	2909	return (ch);
AnnaBridge	167:84c0a372a020	2910	}
AnnaBridge	167:84c0a372a020	2911
AnnaBridge	167:84c0a372a020	2912
AnnaBridge	167:84c0a372a020	2913	/**
AnnaBridge	167:84c0a372a020	2914	\brief ITM Receive Character
AnnaBridge	167:84c0a372a020	2915	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	167:84c0a372a020	2916	\return Received character.
AnnaBridge	167:84c0a372a020	2917	\return -1 No character pending.
AnnaBridge	167:84c0a372a020	2918	*/
AnnaBridge	167:84c0a372a020	2919	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	167:84c0a372a020	2920	{
AnnaBridge	167:84c0a372a020	2921	int32_t ch = -1; /* no character available */
AnnaBridge	167:84c0a372a020	2922
AnnaBridge	167:84c0a372a020	2923	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	167:84c0a372a020	2924	{
AnnaBridge	167:84c0a372a020	2925	ch = ITM_RxBuffer;
AnnaBridge	167:84c0a372a020	2926	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge	167:84c0a372a020	2927	}
AnnaBridge	167:84c0a372a020	2928
AnnaBridge	167:84c0a372a020	2929	return (ch);
AnnaBridge	167:84c0a372a020	2930	}
AnnaBridge	167:84c0a372a020	2931
AnnaBridge	167:84c0a372a020	2932
AnnaBridge	167:84c0a372a020	2933	/**
AnnaBridge	167:84c0a372a020	2934	\brief ITM Check Character
AnnaBridge	167:84c0a372a020	2935	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	167:84c0a372a020	2936	\return 0 No character available.
AnnaBridge	167:84c0a372a020	2937	\return 1 Character available.
AnnaBridge	167:84c0a372a020	2938	*/
AnnaBridge	167:84c0a372a020	2939	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	167:84c0a372a020	2940	{
AnnaBridge	167:84c0a372a020	2941
AnnaBridge	167:84c0a372a020	2942	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	167:84c0a372a020	2943	{
AnnaBridge	167:84c0a372a020	2944	return (0); /* no character available */
AnnaBridge	167:84c0a372a020	2945	}
AnnaBridge	167:84c0a372a020	2946	else
AnnaBridge	167:84c0a372a020	2947	{
AnnaBridge	167:84c0a372a020	2948	return (1); /* character available */
AnnaBridge	167:84c0a372a020	2949	}
AnnaBridge	167:84c0a372a020	2950	}
AnnaBridge	167:84c0a372a020	2951
AnnaBridge	167:84c0a372a020	2952	/@} end of CMSIS_core_DebugFunctions /
AnnaBridge	167:84c0a372a020	2953
AnnaBridge	167:84c0a372a020	2954
AnnaBridge	167:84c0a372a020	2955
AnnaBridge	167:84c0a372a020	2956
AnnaBridge	167:84c0a372a020	2957	#ifdef __cplusplus
AnnaBridge	167:84c0a372a020	2958	}
AnnaBridge	167:84c0a372a020	2959	#endif
AnnaBridge	167:84c0a372a020	2960
AnnaBridge	167:84c0a372a020	2961	#endif /* __CORE_CM33_H_DEPENDANT */
AnnaBridge	167:84c0a372a020	2962
AnnaBridge	167:84c0a372a020	2963	#endif /* __CMSIS_GENERIC */